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The IEEE Verilog 1364-2000 2001 Standard: What's New, and Why You Need It
The IEEE Verilog 1364-2000 2001 Standard: What's New, and Why You Need It
DISCLAIMER:
This
This presentation
presentation is
is strictly
strictly an
an overview
overview — — itit is
is NOT
NOT the
the full
full IEEE
IEEE standard,
standard,
and
and does
does NOT
NOT reflect
reflect the
the full
full details
details of
of the
the enhancements
enhancements to to the
the Verilog
Verilog standard!
standard!
by Stuart Sutherland
Sutherland HDL, Inc.
Verilog Training and Consulting Experts
This
This presentation
presentation was
was updated
updated August,
August, 2001
2001
to
to clarify
clarify some
some points
points and
and make
make minor
minor corrections
corrections in
in some
some examples
examples
(my
(my thanks
thanks to to Cliff
Cliff Cummings
Cummings ofof Sunburst
Sunburst Design
Design for
for suggesting
suggesting the
the changes)
changes)
Sutherland
HD
Verilog-2000 2001 Status L
/*
/* location
location of
of RTL
RTL models
models (current
(current directory)
directory) */
*/
library
library rtlLib
rtlLib ./*.v;
./*.v;
Library Map File /*
/* Location
Location of
of synthesized
synthesized models
models */
*/
library
library gateLib
gateLib ./synth_out/*.v;
./synth_out/*.v;
module
module multiplier
multiplier (a,
(a, b,
b, product);
product);
parameter
parameter a_width
a_width == 8,
8, b_width
b_width == 8;
8;
localparam
localparam product_width
product_width == a_width
a_width ++ b_width;
b_width;
input
input [a_width-1:0]
[a_width-1:0] a;
a;
input [b_width-1:0] b; localparams
localparams are
are constants,
constants,
input [b_width-1:0] b;
output which
which cannot
cannot be
be redefined
redefined
output [product_width-1:0]
[product_width-1:0] product;
product;
generate
generate
if
if ((a_width
((a_width << 8)
8) |||| (b_width
(b_width << 8)) 8))
CLA_multiplier
CLA_multiplier #(a_width,
#(a_width, b_width)
b_width) u1 u1 (a,
(a, b,
b, product);
product);
else
else
WALLACE_multiplier
WALLACE_multiplier #(a_width,
#(a_width, b_width)
b_width) u1 u1 (a,
(a, b,b, product);
product);
endgenerate
endgenerate
•• IfIf the
the input
input bus
bus widths
widths are
are 8-bits
8-bits or
or less,
less, generate
generate and
and
endmodule
endmodule
instance
instance of of aa carry-look-ahead
carry-look-ahead multiplier
multiplier
•• IfIf the
the input
input bus
bus widths
widths are
are greater
greater than
than 8-bits,
8-bits,
generate
generate an an instance
instance of
of aa wallace-tree
wallace-tree multiplier
multiplier
module
module ram
ram (...);
(...); Verilog
Verilog 1995:
1995:
parameter
parameter RAM_SIZE
RAM_SIZE == 1024;
1024;
parameter
parameter ADDRESS
ADDRESS == 12;
12; Vector
Vector widths
widths can
can be
be calculated
calculated
input
input [ADDRESS-1:0]
[ADDRESS-1:0] address_bus;
address_bus; using
using simple
simple constant
constant expressions
expressions
module
module ram
ram (...);
(...);
parameter
parameter RAM_SIZE
RAM_SIZE == 1024;
1024;
input
input [clogb2(RAM_SIZE)-1:0]
[clogb2(RAM_SIZE)-1:0] address_bus;
address_bus;
... Verilog
... Verilog 2001:
2001:
function integer clogb2;
function integer clogb2;
Vector
Vector widths
widths can
can be
be calculated
calculated
input
input [31:0]
[31:0] depth;
depth;
using
using complex
complex constant
constant functions
functions
begin
begin
for(clogb2=0;
for(clogb2=0; depth>0;
depth>0; clogb2=clogb2+1)
clogb2=clogb2+1)
depth
depth == depth
depth >>
>> 1;
1;
end
end
endfunction
endfunction
...
...
reg
reg [63:0]
[63:0] word;
word;
reg
reg [3:0]
[3:0] byte_num;
byte_num; //a
//a value
value from
from 00 to
to 77
wire
wire [7:0]
[7:0] byteN
byteN == word[byte_num*8
word[byte_num*8 +:
+: 8];
8];
The
The starting
starting point
point of
of the
the The
The width
width of
of the
the
part-select
part-select is
is variable
variable part-select
part-select is
is constant
constant
+: indicates
+: indicates the
the part-select
part-select increases
increases from
from the
the starting
starting point
point
-: indicates
-: indicates the
the part-select
part-select decreases
decreases from
from the
the starting
starting point
point
//declare
//declare aa 3-dimensional
3-dimensional array
array of
of 8-bit
8-bit wire
wire nets
nets
wire
wire [7:0]
[7:0] array3
array3 [0:255][0:255][0:15];
[0:255][0:255][0:15];
//select
//select one
one word
word out
out of
of aa 3-dimensional
3-dimensional array
array
wire
wire [7:0]
[7:0] out3
out3 == array3[addr1][addr2][addr3];
array3[addr1][addr2][addr3];
//select
//select the
the high-order
high-order byte
byte of
of one
one word
word in
in aa
//2-dimensional
//2-dimensional array
array of
of 32-bit
32-bit reg
reg variables
variables
reg
reg [31:0]
[31:0] array2
array2 [0:255][0:15];
[0:255][0:15];
wire
wire [7:0]
[7:0] out2
out2 == array2[100][7][31:24];
array2[100][7][31:24];
reg
reg [WORD_SIZE-1:0]
[WORD_SIZE-1:0] core
core [0:(2**ADDR_SIZE)-1];
[0:(2**ADDR_SIZE)-1];
...
...
Verilog-1995 Verilog-2001
always
always @(sel
@(sel or
or aa or
or bb or
or cc or
or d)
d) always
always @(sel,
@(sel, a,a, b,
b, c,
c, d)
d)
case
case (sel)
(sel) case
case (sel)
(sel)
2’b00:
2’b00: yy == a;
a; 2’b00:
2’b00: yy == a;
a;
2’b01:
2’b01: yy == b;
b; 2’b01:
2’b01: yy == b;
b;
2’b10:
2’b10: yy == c;
c; 2’b10:
2’b10: yy == c;
c;
2’b11:
2’b11: yy == d;
d; 2’b11:
2’b11: yy == d;
d;
endcase
endcase endcase
endcase
Verilog-2001 assign
assign eq
eq == (a
(a ==
== b);
b); //defaults
//defaults to
to 1-bit
1-bit wire
wire
Verilog-1995 Verilog-2001
module
module my_chip
my_chip (...);
(...); module
module my_chip
my_chip (...);
(...);
...
... ...
...
RAM
RAM #(8,1023)
#(8,1023) ram2
ram2 (...);
(...); RAM
RAM #(.SIZE(1023))
#(.SIZE(1023)) ram2
ram2 (...);
(...);
endmodule
endmodule endmodule
endmodule
Verilog-1995 Verilog-2001
module
module mux8
mux8 (y,
(y, a,
a, b,
b, en);
en); module
module mux8
mux8 (y,
(y, a,
a, b,
b, en);
en);
output
output [7:0]
[7:0] y;
y; output
output reg
reg [7:0]
[7:0] y;
y;
input
input [7:0]
[7:0] a,
a, b;
b; input
input wire
wire [7:0]
[7:0] a,
a, b;
b;
input
input en;
en; input
input wire
wire en;
en;
...
...
reg
reg [7:0]
[7:0] y;
y;
wire
wire [7:0]
[7:0] a,
a, b;
b;
wire
wire en;
en;
...
...
Verilog-1995 Verilog-2001
module
module mux8
mux8 (y,
(y, a,
a, b,
b, en);
en); module
module mux8
mux8 (output
(output reg
reg [7:0]
[7:0] y,
y,
output
output [7:0]
[7:0] y;
y; input
input wire
wire [7:0]
[7:0] a,
a,
input
input [7:0]
[7:0] a,
a, b;
b; input
input wire
wire [7:0]
[7:0] b,
b,
input
input en;
en; input
input wire
wire en);
en);
...
...
reg
reg [7:0]
[7:0] y;
y;
wire
wire [7:0]
[7:0] a,
a, b;
b;
wire
wire en;
en;
...
...
Verilog-1995 Verilog-2001
reg
reg clock;
clock; reg
reg clock
clock == 0;
0;
initial
initial
clk
clk == 0;
0;
Verilog-2001 (*
(* rtl_synthesis,
rtl_synthesis, parallel_case
parallel_case *)
*) case
case (1'b1)
(1'b1) //1-hot
//1-hot FSM
FSM
Verilog-2001 is complete
The proposed IEEE 1364-2000 Verilog standard is now
in the final balloting phase
Verilog-2001 contains
Over 30 major enhancements
Many clarifications and errata corrections
Verilog-2001 adds powerful capabilities
Greater deep submicron accuracy
More abstract system level modeling
Scalable, re-usable modeling
Final approval is expected in late 2000
UPDATE:
UPDATE: The The definition
definition of
of the
the new
new Verilog
Verilog standard
standard was
was completed
completed in
in 2000,
2000,
original: 10but
Mar the
but the IEEE
2000 IEEE did
did not
not finishing
finishing ratifying
ratifying the
the standard
standard until
until March,
March, 2001.
2001.
updated: 18 Oct 2001 © 2000, 2001 by Sutherland HDL, Inc., www.sutherland-hdl.com 47
Sutherland
HD
For More Information L
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Stuart Sutherland
President of Sutherland HDL, Inc., Portland, Oregon
Provides expert Verilog design consulting and training
More than 15 years design experience, and over 12
years working with Verilog
Author of “Verilog-2001: A Guide to the New Features
of the Verilog HDL”, “The Verilog HDL Quick Reference
Guide”, “The Verilog PLI Quick Reference Guide” and
“The Verilog PLI Handbook”
Member of the IEEE 1364 Verilog standards
committee since 1993; co-chair of the PLI task force
UPDATE:
UPDATE: Verilog-2001
Verilog-2001 versions
versions of of the
the Verilog
Verilog HDL
HDL andand PLI
PLI Quick
Quick
original: 10 Mar 2000
updated: 18 Oct 2001
Reference
Reference Guides
Guides
© 2000,
are
2001 byare
now
now available
Sutherland available at
at www.sutherland-hdl.com.
www.sutherland-hdl.com.
HDL, Inc., www.sutherland-hdl.com 49