TALLER DE DISEÑOS DE SISTEMAS DIGITALES

INTEGRANTES

JORGE MIGUEL MALDONADO GONZALEZ – COD: 2015219054

EFRAIN PATIÑO-COD:20151119065

DOCENTE
ING. EYBERTH ROLANDO ROJAS MARTINEZ

UNIVERSIDAD DEL MAGDALENA

FACULTAD DE INGENIERIA
INGENIERIA ELECTRONICA
SANTA MARTA 2019-1
1) Comportamental
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comparador is
Port ( T1 : in STD_LOGIC_VECTOR (1 downto 0);
T2 : in STD_LOGIC_VECTOR (1 downto 0);
T3 : in STD_LOGIC_VECTOR (1 downto 0);
TP : in STD_LOGIC_VECTOR (1 downto 0);
S : out STD_LOGIC);
end comparador;

architecture Behavioral of comparador is

begin
process(T1,T2,T3,TP)
begin
if TP>=T1 then
S <= '1';
elsif TP<=T2 then
S <= '1';
elsif TP>=T3 then
S <= '1';
else
S<='0';
end if;
end process;

end Behavioral;
 Estructural
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ej_1comp is
Port ( sen : in STD_LOGIC_VECTOR (2 downto 0);
err : out STD_LOGIC;
sal : out STD_LOGIC);
end ej_1comp;

architecture Behavioral of ej_1comp is

begin

process (sen) is
begin

if ( sen = "000") then

sal <= '0';
err <= '0';
elsif ( sen = "001") then
sal <= '1';
err <= '0';
elsif (sen = "011") then
sal <= '0';
err <= '0';
elsif (sen = "111") then
sal <= '1';
err <= '0';

else
sal <= '0';
err <= '1';
end if;
end process;

END Behavioral;
EJERCIO 2

comportamental
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity taller is

Port ( bot : in STD_LOGIC;

A : in STD_LOGIC;

B : in STD_LOGIC;

C : in STD_LOGIC;

M : out STD_LOGIC;

V : out STD_LOGIC;

C1 : out STD_LOGIC;

C2 : out STD_LOGIC);

end taller;
architecture Behavioral of taller is

begin

process(A,B,C,bot)

begin

if bot = '1' then

V<='0';

C2<='0';

C1<='0';

M<='1';

elsif bot = '0' then

M<='0';

if A = '1' then

V<='0';

elsif A='0' then

V<='1';

end if;

if B = '1' then

C1<='1';

elsif B='0' then

C1<='0';

end if;

if C = '1' then

C2<='1';
 elsif C='0' then

C2<='0';

end if;

end if;

end process;

end Behavioral;
 estructural
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity eje2_compor is
Port ( sens : in STD_LOGIC_VECTOR (2 downto 0);
bot : in STD_LOGIC;
SAL : out STD_LOGIC_VECTOR (3 downto 0));
end eje2_compor;

architecture Behavioral of eje2_compor is

begin
process (sens, bot)
begin
if ( bot = '0') then
if ( sens = "000") then
SAL <= "1000";

elsif (sens = "100") then

SAL <= "0000";

elsif (sens = "010") then

SAL <= "1100";

elsif ( sens = "001") then

SAL <= "1010";

else
SAL <= "1000";

end if;

else

SAL <= "1001";

end if;
end process;

end Behavioral;
3)Comportamental

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity punto_3 is
Port ( b1 : in STD_LOGIC;
b2 : in STD_LOGIC;
n1 : in STD_LOGIC;
n2 : in STD_LOGIC;
m1 : out STD_LOGIC;
m2 : out STD_LOGIC);
end punto_3;

architecture Behavioral of punto_1 is

begin
process(b1,b2,n1,n2)
begin

if b1='1' and b2='1' then

m1 <= '0';
m2 <= '0';

elsif b1='0' and b2='1' and n1='1' then

m1 <= '1';
m2 <= '0';

elsif b1='0' and b2='1' and n1='0' and n2='1' then

m1 <= '0';
m2 <= '1';

elsif b1='0' and b2='0' then

m1 <= '1';
m2 <= '1';

else
m1 <= '0';
m2 <= '0';

end if;
end process;

end Behavioral;
RTL schematic
 estructural
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-
entity ejer_3 is
Port ( ENTSENSORES : in STD_LOGIC_VECTOR (3 downto 0);
SALBOM : out STD_LOGIC_VECTOR (1 downto 0));
end ejer_3;

architecture Behavioral of ejer_3 is

begin
Process ( ENTSENSORES) IS
BEGIN
CASE ENTSENSORES IS
when "0011" => SALBOM<= "00";
when "0111" => SALBOM<= "00";
when "1011" => SALBOM<= "00";
when "1111" => SALBOM<= "00";
when "1001" => SALBOM<= "00";
when "0101" => SALBOM<= "00";
when "0000" => SALBOM<= "00";
when "1100" => SALBOM<= "00";
when "1000" => SALBOM<= "00";
when "0100" => SALBOM<= "00";
when OTHERS => SALBOM<= "00";
END CASE;
END PROCESS;

end Behavioral;
RTL SCHEMATIC
 

4. Preguntas de selección múltiple única respuesta.

a) ¿Cuántos bits de selección tiene un multiplexor de 260 canales?

 7 bits.
 8 bits
 9 bits.
 10 bits.
b) Si un decodificador de 4 líneas a 16 con salidas activas a nivel bajo muestra
un nivel bajo en la salida decimal 11 ¿Cuáles son sus entradas?
 1010
 1011
 1100
 0100
c) Los selectores de datos son:
 Decodificadores
 Demultiplexores
 Multiplexores
 Codificadores
d) El número -60 representado en complemento a dos (7 bits) es:
 1000011
 1111100
 1011100
  1000100
 Ninguna de las anteriores

5. La Figura muestra el diagrama de RTL del módulo top denominado “VISUALIZACION”,

A la descripción en VHDL del circuito le hace falta el mapeo de los componentes para

El modulo. Complete donde sea necesario:

1. library IEEE;

2. use IEEE.STD_LOGIC_1164.ALL;

3.

4. entity visualizacion is

5. Port ( a : in STD_LOGIC_VECTOR (2 downto 0);

6. b : in STD_LOGIC_VECTOR (2 downto 0);

7. selx : in STD_LOGIC;

8. dout : out STD_LOGIC_VECTOR (6 downto 0);

9. dig : out STD_LOGIC_VECTOR (1 downto 0));

10. end visualizacion;

11. architecture Behavioral of visualizacion is

12. COMPONENT sumador

13. PORT(

14. D0 : IN std_logic_vector(2 downto 0);

15. D1 : IN std_logic_vector(2 downto 0);

16. a1 : OUT std_logic_vector(3 downto 0);

17. a2 : OUT std_logic_vector(3 downto 0)

18. );

19. END COMPONENT;

20. COMPONENT MUX2_1

21. PORT(

22. D0 : IN std_logic_vector(3 downto 0);

23. D1 : IN std_logic_vector(3 downto 0);

24. SEL : IN std_logic;

25. s : OUT std_logic_vector(3 downto 0)

26. );

27. END COMPONENT;

28. COMPONENT DEC_BCD_7SEG

29. PORT(

30. n : IN std_logic_vector(3 downto 0);

31. seg : OUT std_logic_vector(6 downto 0)

32. );

33. END COMPONENT;

34. COMPONENT DEC2_1

35. PORT(

36. din : IN std_logic;

37. sal : OUT std_logic_vector(1 downto 0)

38. );

39. END COMPONENT;

40. signal sa1: std_logic_vector( downto 0);

41. signal sa2: std_logic_vector( downto 0);

42. signal ss: std_logic_vector( downto 0);

43. begin

44. Inst_sumador: sumador PORT MAP(

45. D0 => a ,

46. D1 => b ,
47. a1 => sa1 ,

48. a2 => sa2

49. );

50. Inst_MUX2_1: MUX2_1 PORT MAP(

51. D0 => sa1 ,

52. D1 => sa2 ,

53. SEL => sel(x) ,

54. s => ss

55. );

56. Inst_DEC_BCD_7SEG: DEC_BCD_7SEG PORT MAP(

57. n => ss ,

58. seg => dout

59. );

60. Inst_DEC2_1: DEC2_1 PORT MAP(

61. din => sel(x) ,

62. sal => dig

63. );

64. end Behavioral;