Test Conditions for various vector groups

commonly under use are listed along with

pictorial representation. Assuming the
reader has sufficient exposure to
transformer winding connections.

Transformer
Vector
Group Test
conditions
YNd1, YNd11, Dyn11, YNyn0
and more
Pandian
 Transformer Vector Group Test conditions

Index
Chapter Page
Cover page
Index 1
Introduction about Vector Group Notation 2
Test Conditions for Ii0 & Ii6 3
Test Conditions for YNyn0 4
Test Conditions for YNyn6 5
Test Conditions for Dd0 7
Test Conditions for Dd6 8
Test Conditions for YNd1 10
Test Conditions for YNd11 11
Test Conditions for Dyn11 12
Test Conditions for Dyn1 13

1. Ensure only one terminal of HV and one terminal of LV is connected together

2. Ensure the additive voltage does not exceeds the safe limit Page 1
 Transformer Vector Group Test conditions

Introduction
In transformers the interconnection of the coils and the phase angle between the primary and
secondary side are denoted by standard form. Transformers with similar connections and phase shift
are grouped under a Vector group.

Standard notations to denote the connection are listed below

Connection Notation
Star Y
Delta D
HV Winding Neutral N
Zig Zag Z
Single Phase I
Star y
Delta d
LV Winding Zig Zag z
Neutral n
Single Phase i

The phase shift between the primary and secondary side are denoted in the form of Clock Position.
Taking HV side as the reference (i.e. 12 o Clock position) phase shift of the LV side is mentioned in
numerical values in multiples of 30°

0 denotes 0°, 1 denotes 30°, 6 denotes 180° and so on. In special transformer where the phase shift
is not in multiples of 30° particularly for the isolation transformer incorporated to reduce the
harmonics, directly the phase angle is been mentioned by the manufacturers

To carry out the Vector Group test one should establish the electrical connection between Primary
and Secondary since the separate winding transformers are inductively coupled whereas the auto
transformers are electrically coupled and so no need for latter.

After establishing the electrical connection between two windings under test, voltage may be
applied in either of the winding preferably in the HV side as it is safe and the voltage measured
between the various terminals will be indicative to ensure the phase shift. Testing Engineer should
derive at least three conditions to compare, add and or equate the particular set of voltage to be
measured. These conditions should be in such way to ensure the phase shift and phase sequence.

Usually 1U and 2u are connected but it is not necessarily to be so, Testing Engineer can choose by
his/her own choice and the conditions shall be derived accordingly.

If the derived conditions are satisfied the vector shall be confirmed.

1. Ensure only one terminal of HV and one terminal of LV is connected together

2. Ensure the additive voltage does not exceeds the safe limit Page 2
 Transformer Vector Group Test conditions

1P 2p
Ii0
Connect 1P and 2p
Keep the neutral(1N & 2n)l floating 2n
Apply Voltage in HV side

1N

Condition
1P & 2p
Measure Voltage between
V1P2n
1. 1P and 2n (V1P2n ) 2n
2. 2n and 1N (V2n1N ) V1P1N
3. 1P and 1N (V1P1N ) V1N2n

V1P2n + V2n1N = V1P1N

1N

Ii6 1P 2n

Connect 1P and 2p
Keep the neutral(1N & 2n)l floating
Apply Voltage in HV side 2p

1N

Condition 2n
Measure Voltage between V1P2n
1P & 2p
1. 1P and 2n (V1P2n )
2. 2n and 1N (V2n1N )
V2n1N
3. 1P and 1N (V1P1N )

V1P2n + V1P1N = V2n1N V1P1N

1N

1. Ensure only one terminal of HV and one terminal of LV is connected together

2. Ensure the additive voltage does not exceeds the safe limit Page 3
 Transformer Vector Group Test conditions

YNyn0 1U
2u

Connect 1U and 2u
Keep the neutral floating 2n
Apply 3Φ Voltage in HV side 2w 2v
1N

1W 1V

Condition – 1

Measure Voltage between

1U&2u
1. 1U and 2n (V1U2n )
V1U2n
2. 2n and 1N (V2n1N ) V1U1N 2n
3. 1U and 1N (V1U1N ) 2v V2n1N
2w
V1U2n + V2n1N = V1U1N 1N

1W 1V
Condition – 2

Measure Voltage between

1U&2u
1. 1W and 2w ( V1W2w )
2n
2. 1V and 2v (V1V2v )
2w 2v
V1W2w = V1V2v V1W2w V1V2v
1N

1W 1V
Condition – 3

Measure Voltage between

1U&2u
1. 1W and 2w (V1W2w )
2. 1W and 2v (V1V2v ) 2n V1W2v

V1W2w < V1w2v 2w 2v

V1W2w
1N

1W 1V

1. Ensure only one terminal of HV and one terminal of LV is connected together

2. Ensure the additive voltage does not exceeds the safe limit Page 4
 Transformer Vector Group Test conditions

YNyn6 1U 2v 2w
2n
Connect 1U and 2u
Keep the neutral floating
Apply 3Φ Voltage in HV side 2u

1N

1W 1V

Condition – 1
2v 2w
Measure Voltage between 2n

1. 1U and 2n (V2n1U ) V2n1U

2. 2n and 1N (V2n1N ) 1U& 2u
3. 1U and 1N (V1U1N ) V2n1N
V1U1N

V2n1U + V1U1N = V2n1N

1N

1W 1V

2v 2w
Condition – 2 2n

Measure Voltage between

1U& 2u
1. 1W and 2v ( V1W2v )
V1W2v
2. 1V and 2w (V1V2w ) V1V2w

V1W2v = V1V2w
1N

1W 1V

1. Ensure only one terminal of HV and one terminal of LV is connected together

2. Ensure the additive voltage does not exceeds the safe limit Page 5
 Transformer Vector Group Test conditions

YNyn6…(contd)
2v 2w
2n
Condition – 3

Measure Voltage between 1U& 2u V1W2w

1. 1W and 2v (V1W2v ) V1W2v

2. 1W and 2w (V1w2w )

V1W2w > V1w2v 1N

1W 1V

*By connecting 1U and 2u the Voltage V1W2w may be high, hence the author feels
comfortable to connect 1U and 2n. Then the Condition – 1 changes as follows

and the Conditions – 2 & 3 remains unchanged

Measure Voltage between

2v 2w
1. 1U and 2u (V1U2u )
V1U2u 1U& 2n
2. 2u and 1N (V2u1N )
2u V1W2w
3. 1U and 1N (V1U1N )
V2u1N
V1U2u + V2u1N = V1U1N
1N

1W 1V

1. Ensure only one terminal of HV and one terminal of LV is connected together

2. Ensure the additive voltage does not exceeds the safe limit Page 6
 Transformer Vector Group Test conditions

1U
Dd0 2u
Connect 1U and 2u
Apply 3Φ Voltage in HV side
2w 2v

1W 1V
Condition – 1

Measure Voltage between

1U&2u
1. 1U and 2w (V1U2w )
2. 2w and 1W (V2w1W ) 2w 2v
3. 1U and 1W (V1U1W )

V1U2w + V2w1W = V1U1W

1W 1V

Condition – 2

Measure Voltage between 1U&2u

1. 1U and 2v (V1U2v )
2. 2v and 1V (V2v1V ) 2w 2v
3. 1U and 1V (V1U1V )

V1U2v + V2v1V = V1U1V

1W 1V

Condition – 3
1U&2u
Measure Voltage between

2v V1W2v
1. 1W and 2v (V1W2v ) 2w
2. 1W and 2w (V1w2w )

V1W2w < V1w2v

1W 1V

1. Ensure only one terminal of HV and one terminal of LV is connected together

2. Ensure the additive voltage does not exceeds the safe limit Page 7
 Transformer Vector Group Test conditions

Dd6 1U

Connect 1U and 2u 2v 2w
Apply 3Φ Voltage in HV side

2u

1W 1V

Condition – 1
2v 2w
Measure Voltage between

1. 1U and 2w (V1U2w ) 1U&2u

V1U2w
2. 2w and 1W (V1W2w )
3. 1U and 1W (V1U1W ) V1W2w

V1U1W + V1U2w = V1W2w

1W 1V

Condition – 2

Measure Voltage between 2v 2w

1. 1U and 2v (V1U2v )
1U&2u
2. 2v and 1V (V1V2v ) V1U2v
3. 1U and 1V (V1U1V ) V1V2v

V1U1V + V1U2v = V1V2v

1W 1V

1. Ensure only one terminal of HV and one terminal of LV is connected together

2. Ensure the additive voltage does not exceeds the safe limit Page 8
 Transformer Vector Group Test conditions

Dd6…(contd)
Condition – 3

Measure Voltage between 2v 2w

1. 1W and 2v (V1W2v )
1U&2u
2. 1W and 2w (V1w2w )
V1W2w
V1W2w > V1w2v

1W 1V

*By connecting 1U and 2u the Voltage V1W2w may be high, hence the author feels
comfortable to connect 1U and 2v and conditions shall be derived accordingly.

1. Ensure only one terminal of HV and one terminal of LV is connected together

2. Ensure the additive voltage does not exceeds the safe limit Page 9
 Transformer Vector Group Test conditions

YNd1 1U 2u

Connect 1U and 2u 2w
Keep the neutral floating 2v
Apply 3Φ Voltage in HV side
1N

1W 1V

Condition - 1
1U & 2u
Measure Voltage between V1U2v 2w V1U1N
2v
1. 1U and 2v (V1U2v ) V2v1N
2. 2v and 1N (V2v1N )
1N
3. 1U and 1N (V1U1N )
1W 1V
V1U2v + V2v1N = V1U1N

Condition – 2 1U & 2u

Measure Voltage between 2w

2v
1. 1W and 2w ( V1W2w ) V1W2w V1V2w
2. 1V and 2w (V1V2w ) 1N

V1W2w < V1V2w 1W 1V

Condition – 3
1U & 2u
Measure Voltage between
2w
2v
1. 1W and 2v (V1W2V )
2. 1V and 2v (V1V2v ) V1W2v V1V2v
1N
V1W2V = V1V2v
1W 1V

1. Ensure only one terminal of HV and one terminal of LV is connected together

2. Ensure the additive voltage does not exceeds the safe limit Page 10
 Transformer Vector Group Test conditions

YNd11
1U 2u
Connect 1U and 2u
2v
Keep the neutral floating
2w
Apply 3Φ Voltage in HV side

1N

1W 1V

Condition - 1

Measure Voltage between 1U & 2u

V1U2w 2v
1. 1U and 2w (V1U2w )
2w V1U1N
2. 2w and 1N (V2w1N ) V2w1N
3. 1U and 1N (V1U1N )
1N
V1U2w + V2w1N = V1U1N
1W 1V

Condition - 2

Measure Voltage between 1U & 2u

1. 1W and 2v ( V1W2v ) 2v
2w
2. 1V and 2v (V1V2v )
V1W2v V1V2v
V1W2v > V1V2v 1N

1W 1V

Condition -3

Measure Voltage between

1. 1W and 2w (V1W2w ) 1U & 2u

2. 1V and 2w (V1V2w ) 2v
2w
V1W2w = V1V2w
V1W2w V1V2w
1N

1W 1V

1. Ensure only one terminal of HV and one terminal of LV is connected together

2. Ensure the additive voltage does not exceeds the safe limit Page 11
 Transformer Vector Group Test conditions

Dyn11
1U
2u
Connect 1U and 2u
Keep the neutral floating
Apply 3Φ Voltage in HV side 2n 2v

2w
1W 1V

1U& 2u
Condition - 1 V1U2n
V1U1V
Measure Voltage between 2n 2v

1. 1U and 2n (V1U2n ) V2n1V

2w
2. 2n and 1V (V2n1V )
3. 1U and 1V (V1U1V ) 1W 1V

V1U2n + V2n1V = V1U1V

Condition - 2 1U& 2u

Measure Voltage between V1W2w 2n

2v
1. 1W and 2v ( V1W2v ) 2w
2. 1W and 2w (V1W2w ) V1W2v

V1W2v > V1W2w 1W 1V

Condition -3
1U& 2u
Measure Voltage between
2n
2v
1. 1V and 2v (V1V2v )
2. 1V and 2w (V1V2w ) 2w

V1V2v = V1V2w 1W 1V

1. Ensure only one terminal of HV and one terminal of LV is connected together

2. Ensure the additive voltage does not exceeds the safe limit Page 12
 Transformer Vector Group Test conditions

Dyn1 1U 2u

Connect 1U and 2u 2w 2n
Keep the neutral floating
Apply 3Φ Voltage in HV side 2v

1W 1V

Condition - 1
1U&2u
V1U2n
Measure Voltage between V1U1W
2n
2w
1. 1U and 2n (V1U2n )
V2n1W
2. 2n and 1W (V2n1W ) 2v
3. 1U and 1W (V1U1W )
1W 1V
V1U2n + V2n1W = V1U1W

1U&2u
V1V2v
Condition - 2
2n
2w
Measure Voltage between
2v
1. 1V and 2v ( V1V2v )
2. 1V and 2w (V1V2w ) 1W 1V

V1V2w > V1V2v

V1V2w

Condition -3 1U&2u

Measure Voltage between

2n
2w
1. 1W and 2v (V1W2v )
V1V2w
2. 1W and 2w (V1W2w ) 2v
V1V2v
V1W2v = V1W2w 1W 1V

1. Ensure only one terminal of HV and one terminal of LV is connected together

2. Ensure the additive voltage does not exceeds the safe limit Page 13