: To design a Traffic Light Controller.

Specifications:
Ø The traffic signal for the main highway gets highest priority because cars are
continuously present on the main highway. Thus, the main highway signal
remains by default.
Ø Occasionally car from country road arrive at the traffic signal. The traffic signal
for the country road must turn green only long enough to let the cars on the
country road go.
Ø As soon as there are no cars on the country road, the country road traffic signal
turns yellow and then red and the traffic signal on the main highway turns green
again.
Ø There is a sensor to detect cars waiting on the country road. The sensor sense a
signal ‘x’ as the input of the controller. ‘x’=1 if there are cars on the country road.
Otherwise, ‘x’=0.
Ø There are delays on transition from s1 to s2, s2 to s3, and from s4 to s0. The
delays must be controller.
PROGRAM:
`define true 1'b1
`define false 1'b0
`define y_rdelay 3
`define r_gdelay 2

module sig_controller(highway, country, x, clock, clear);

output[1:0]highway, country;
reg[1:0]highway, country;
input x, clock, clear;

parameter red=2'd0, yellow=2'd1, green=2'd2;

parameter s0=3'd0,
s1=3'd1,
s2=3'd2,
s3=3'd3,
s4=3'd4;

reg[2:0]state, next_state;

always@(posedge clock)
if(clear)
state<=s0;
else state<=next_state;
always@(state)
begin
highway=green;
country=red;
case(state)
s0: begin highway=green; country=red; end
s1: begin highway=yellow; country=red; end
s2: begin highway=red; country=red; end
s3: begin highway=red; country=green; end
s4: begin highway=red; country=yellow; end
endcase
end

always@(state or x)
begin
case(state)
s0: if(x)
next_state=s1;
else
next_state=s0;
s1:
begin
repeat(`y_rdelay)@(posedge clock);
next_state=s2;
end
s2:
begin
repeat(`r_gdelay)@(posedge clock);
next_state=s3;
end
s3:
if(x)
next_state=s3;