vhdl module:

entity Vmachine is
Port ( dime : in STD_LOGIC;
nikel : in STD_LOGIC;
clk : in STD_LOGIC;
y : out STD_LOGIC);
end Vmachine;

architecture Behavioral of Vmachine is

type state is (a,b,c,d,e);
signal s:state;
begin
process (dime,nikel,clk)
begin
if (clk='1' and clk'event) then
case s is
when a=>
if (dime='0' and nikel='0') then
s<=a;
end if;
if (dime='1' and nikel='0') then
s<=b;
end if;
if (dime='0' and nikel='1') then
s<=c;
end if;
y<='0';

when b=>
if (dime='0' and nikel='0') then
s<=b;
end if;
if (dime='1' and nikel='0') then
s<=e;
end if;
if (dime='0' and nikel='1') then
s<=d;
end if;
y<='0';

when c=>
if (dime='0' and nikel='0') then
s<=c;
end if;
if (dime='1' and nikel='0') then
s<=d;
end if;
if (dime='0' and nikel='1') then
s<=b;
end if;
y<='0';

when d=>
s<=a;
 y<='1';

when e=>
s<=c;
y<='1';
when others=> null;
end case;
end if;
end process;

end Behavioral;

vhdl test bench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY Vmachine_tb IS
END Vmachine_tb;

ARCHITECTURE behavior OF Vmachine_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT Vmachine
PORT(
dime : IN std_logic;
nikel : IN std_logic;
clk : IN std_logic;
y : OUT std_logic
);
END COMPONENT;

--Inputs
signal dime : std_logic := '0';
signal nikel : std_logic := '0';
signal clk : std_logic := '0';

--Outputs
signal y : std_logic;

-- Clock period definitions

constant clk_period : time := 100 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: Vmachine PORT MAP (
dime => dime,
nikel => nikel,
 clk => clk,
y => y
);

-- Clock process definitions

clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin

wait for 50 ns;

dime<='1';
nikel<='0';
wait for 100 ns;
dime<='1';
nikel<='0';
wait for 100 ns;
dime<='1';
nikel<='0';

wait for 200 ns;

dime<='0';
nikel<='0';

wait for clk_period*10;

wait;
end process;

END;