Library IEEE;

Use IEEE.STD_LOGIC_1164.ALL;

Use IEEE.STD_LOGIC_ARITH.ALL;

Use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top level is

port (clock :in STD_LOGIC;

reset : in STD_LOGIC;

enable: in STD_LOGIC;

sw_selM:in STD_LOGIC_VECTOR 81 downto 0);

display: out STD_LOGIC_VECTOR 86 downto 0);

an : out std_logic_vector (7 downto 0);

);

end top_level;

architecture Behavioral of top_level is

-------------------------------------------------------

COMPONENT banco_contadorAN

PORT(

clock: IN std_logic;

reset : in STD_LOGIC;

enable: in STD_LOGIC;

cuent: out std_logic_vector (2 downto 0)

);

END COMPONENT;

----------------------------------------------

Entity banco_contadorAN is

Generic (n : positive := 3);

 Port (clock : in STD_LOGIC;

reset: in STD_LOGIC;

enable: in STD_LOGIC;

cuenta : out std_logic_vector (n-1 downto 0)

);

End banco_contadorAN;

Architecture behavioral of banco_contadorAN is

-------------------------------------------------------------------------

COMPONENT contador_anodos

PORT (

clock : IN STD_LOGIC;

reset: IN STD_LOGIC;

enable: IN STD_LOGIC;

cuenta : OUT std_logic_vector (2 downto 0)

);

END COMPONENT;

-------------------------------------------------------------------------

COMPONENT div_freq_anodos

PORT (

clock : IN STD_LOGIC;

reset: IN STD_LOGIC;

enable: IN STD_LOGIC;

clkdiv_an : OUT std_logic

);

END COMPONENT;

-------------------------------------------------------------------------

signal freq500hz : std_logic;

begin
------------------------------------------------------------------------------

Inst_div_freq_anodos: div_freq_anodos PORT MAP (

Clock=>clock,

Reset =>reset,

Enable=>enable;

Clkdiv_an => freq500hz

);

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

Inst_contador_anodos: contador_anodos PORT MAP (

clock=>clock,

reset =>reset,

enable=> freq500hz;

cuenta => cuenta

);

-------------------------------------------------------------------------------

End behavioral;

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 08:45:23 04/17/2018

-- Design Name:

-- Module Name: inst_contador_anodos-contador_anodos - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:
-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

Library IEEE;

Use IEEE.STD_LOGIC_1164.ALL;

Use IEEE.STD_LOGIC_ARITH.ALL;

Use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity contador_anodos is

Generic (n : positive := 3);

Port (clock : in STD_LOGIC;

reset: in STD_LOGIC;

enable: in STD_LOGIC;

cuenta : out std_logic_vector (n-1 downto 0)

);

End contador_anodos;

Architecture behavioral of contador_anodos is

Signal D_bus,Q_bus : STD_LOGIC_VECTOR (n-1 downto 0);

Signal MC, sumador : STD_LOGIC_VECTOR (n-1 downto 0);

Signal compara,com : STD_LOGIC;

Begin

MC <= ´´111´´;
-----------------------------------registro de estado 1----------------------------

Process (clock)

Begin

If clock´event and clock=´1´then

If reset =´1´then

Q_bus <= (others => ´0´);

Elsif enable =´1´then

Q_bus <= D_bus;

End if;

End if;

End process;

---------------------logica de estado siguiente 1----------------

Compara <= ´1´when Q_ bus >= MC else ´0´;

Sumador <= Q_bus+1;

D_bus <= sumador when compara <= ´0´else (others=> ´0´);

----------------------------logica de salida-------------------------

Cuenta <= Q_bus;

End behavioral;

Library IEEE;

Use IEEE.STD_LOGIC_1164.ALL;

Use IEEE.STD_LOGIC_ARITH.ALL;

Use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity banco_contadores is

Generic (n: positive:=4);

 Port ( clock : in STD_LOGIC;

reset: in STD_LOGIC;

Enable: in STD_LOGIC;

selMF: IN std_logic_vector (1 downto 0);

selDpy: IN std_logic_vector (2 downto 0);

in_display: out STD_LOGIC_VECTOR (n-1 downto 0);

pulso: out STD_LOGIC

);

end banco_contadores;

Architecture Behavioral of banco_contadores is

-----------------------------------------------------

COMPONENT contador

PORT (

clock : IN STD_LOGIC;

reset: IN STD_LOGIC;

Enable: IN STD_LOGIC;

in_display: OUT STD_LOGIC_VECTOR (3 downto 0);

pulso1: OUT STD_LOGIC

);

END COMPONENT;

------------------------------------------------------------------------------------------

----------------------------------------------------------------------------------------------------------------------

COMPONENT divisor_freq

PORT (

clock : IN STD_LOGIC;

reset: IN STD_LOGIC;
 enable: IN STD_LOGIC;

selMF: IN std_logic_vector (1 downto 0);

--in_display: OUT STD_LOGIC_VECTOR (1 downto 0);

clkdiv:OUT STD_LOGIC

);

END COMPONENT;

---------------------------------------------------------------------------------

----------------------------------------------------------------------------------

Signal clkdiv,pulso1,pulso2,pulso3,: std_logic;

Signal pulso4,pulso5,pulso6,pulso7,pulso8,:std_logic;

Signal in_displays1, in_displays2, in_displays3,in_displays4 :std_logic_vector (3 downto 0);

Signal in_displays5, in_displays6, in_displays7,in_displays8 :std_logic_vector (3 downto 0);

------------------------------------------------------------------------

begin

-------------------------------------------------------------------------

Inst_divisor_freq: divisor_freq PORT MAP (

clock=>clock,

reset =>reset,

enable=>enable;

selMf=>selMF,

--in_display =>in_display0,

clkdiv =>clkdiv

);

-------------------------------------------------

-------------------------------------------------

Inst_contador1: contador PORT MAP (

clock=>clock,

reset =>reset,

enable=>clkdiv;
 in_display => in_displays1,

pulso1 => pulso1

);

-----------------------------------------------------------

------------------------------------------------------------

Inst_contador2: contador PORT MAP (

clock=>clock,

reset =>reset,

enable=>pulso1,

in_display =>in_displays2,

pulso1 => pulso2

);

-----------------------------------------------------------

------------------------------------------------------------

Inst_contador3: contador PORT MAP (

clock=>clock,

reset =>reset,

enable=>pulso2,

in_display =>in_displays3,

pulso1 => pulso3

);

-----------------------------------------------------------

------------------------------------------------------------

Inst_contador4: contador PORT MAP (

clock=>clock,

reset =>reset,

enable=>pulso3,

in_display =>in_displays4,

pulso1 => pulso4

);

-----------------------------------------------------------

------------------------------------------------------------

Inst_contador5: contador PORT MAP (

clock=>clock,

reset =>reset,

enable=>pulso4,

in_display =>in_displays5,

pulso1 => pulso5

);

-----------------------------------------------------------

------------------------------------------------------------

Inst_contador6: contador PORT MAP (

clock=>clock,

reset =>reset,

enable=>pulso5,

in_display =>in_displays6,

pulso1 => pulso6

);

-----------------------------------------------------------

------------------------------------------------------------

Inst_contador7: contador PORT MAP (

clock=>clock,

reset =>reset,

enable=>pulso6,

in_display =>in_displays7,

pulso1 => pulso7

);

-----------------------------------------------------------
------------------------------------------------------------

Inst_contador8: contador PORT MAP (

clock=>clock,

reset =>reset,

enable=>pulso7,

in_display =>in_displays8,

pulso1 => pulso8

);

-----------------------------------------------------------

------------------------------------------------------------

Wiht selDpy select

In_display <= in_display1 when ´´000´´,

in_displays2 when "001",

in_displays3 when "010",

in_displays4 when "011",

in_displays5 when "100",

in_displays6 when "101",

in_displays7 when "110",

in_displays8 when others;

end Behavioral;

---------------------------------------------------------------------------------------

----------------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity divisor_freq is

generic (n: positive:=25);

Port ( clock : in STD_LOGIC;

reset: in STD_LOGIC;

enable: in STD_LOGIC;

selMF: IN std_logic_vector (1 downto 0);

selDpy: IN std_logic_vector (2 downto 0);

----in_display: out STD_LOGIC_VECTOR (n-1 downto 0);

clkdiv: out STD_LOGIC

);

end divisor_freq;

Architecture Behavioral of divisor_freq is

Signal D_bus,Q_bus : STD_LOGIC_VECTOR (n-1 downto 0);

Signal M, sumador : STD_LOGIC_VECTOR (n-1 downto 0);

Signal compara : STD_LOGIC;

Begin

--1001100010010110100000000 5hz

--0100110001001011010000000 10 hz

--0011010101100111111000000 15 hz

--0010011000100101101000000 20 hz

With selMf select

M<="1001100010010110100000000" when "00",

"0100110001001011010000000" when "01",

"0011010101100111111000000" when "10",

"0010011000100101101000000" when others;

------------------------------registro de estado 1---------------------------

Process (clock)

Begin

If clock'event and clock ='1'then

If reset ='1' then

Q_bus <= (others => '0');

Elsif enable ='1'then

Q_bus <= D_bus;

End if;

End if;

End process;

----logica de estado siguiente 1 -------------

compara <='1'when Q_bus >= M else '0';

sumador <= Q_bus+1;

D_bus <= sumador when compara <= '0'else (others=> '0');

----------------logica de salida----------------------

clkdiv <= compara;

----in_display<=sumador;

End Behavioral;

Library IEEE;

Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;

Use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity contador is

generic (n: positive:=4);

Port ( clock : in STD_LOGIC;

reset: in STD_LOGIC;

enable: in STD_LOGIC;

in_display: out STD_LOGIC_VECTOR (n-1 downto 0);

pulso1 : out STD_LOGIC

);

end contador;

architecture Behavioral of contador is

Signal D_bus,Q_bus : STD_LOGIC_VECTOR (n-1 downto 0);

Signal MC, sumador : STD_LOGIC_VECTOR (n-1 downto 0);

Signal compara,com : STD_LOGIC;

Begin

MC<="1001"; -------el contador que permite contar de cero a 9 y activa el siguiente multiplexor

----------------------------------registro de estado 1------------------------------------------

process (clock)

begin

if clock'event and clock='1' then

 if reset ='1' then

Q_bus <= (others => '0');

elsif enable ='1'then

Q_bus <= D_bus;

end if;

end if;

end process;

-------------------------------logica de estado siguiente1--------------------

compara <='1'when Q_bus >= MC else '0';

sumador <= Q_bus+1;

D_bus <= sumador when compara <= '0'else (others=> '0');

-----------------------------logica de salida---------------------------------

Process (clock)

begin

if clock'event and clock='1'then

if reset ='1' then

Com<= '0';

else

com <= not compara;

end if;

end if

end process;

pulso1 <= com and compara;

in_display <= Q_bus;

end behavioral;
Library IEEE;

Use IEEE.STD_LOGIC_1164.ALL;

Use IEEE.STD_LOGIC_ARITH.ALL;

Use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity contador is

generic (n: positive:=4);

Port ( clock : in STD_LOGIC;

reset: in STD_LOGIC;

enable: in STD_LOGIC;

in_display: out STD_LOGIC_VECTOR (n-1 downto 0);

pulso1 : out STD_LOGIC

);

end contador;

architecture Behavioral of contador is

Signal D_bus,Q_bus : STD_LOGIC_VECTOR (n-1 downto 0);

Signal MC, sumador : STD_LOGIC_VECTOR (n-1 downto 0);

Signal compara,com : STD_LOGIC;

Begin
MC<="1001"; -------el contador que permite contar de cero a 9 y activa el siguiente multiplexor

----------------------------------registro de estado 1------------------------------------------

process (clock)

begin

if clock'event and clock='1' then

if reset ='1' then

Q_bus <= (others => '0');

elsif enable ='1'then

Q_bus <= D_bus;

end if;

end if;

end process;

-------------------------------logica de estado siguiente1--------------------

compara <='1'when Q_bus >= MC else '0';

sumador <= Q_bus+1;

D_bus <= sumador when compara <= '0'else (others=> '0');

-----------------------------logica de salida---------------------------------

Process (clock)

begin

if clock'event and clock='1'then

if reset ='1' then

Com<= '0';

else

com <= not compara;

end if;

end if
end process;

pulso1 <= com and compara;

in_display <= Q_bus;

end behavioral;

Library IEEE;

Use IEEE.STD_LOGIC_1164.ALL;

Use IEEE.STD_LOGIC_ARITH.ALL;

Use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity contador is

generic (n: positive:=4);

Port ( clock : in STD_LOGIC;

reset: in STD_LOGIC;

enable: in STD_LOGIC;

in_display: out STD_LOGIC_VECTOR (n-1 downto 0);

pulso1 : out STD_LOGIC

);

end contador;

architecture Behavioral of contador is

Signal D_bus,Q_bus : STD_LOGIC_VECTOR (n-1 downto 0);

Signal MC, sumador : STD_LOGIC_VECTOR (n-1 downto 0);

Signal compara,com : STD_LOGIC;

Begin

MC<="1001"; -------el contador que permite contar de cero a 9 y activa el siguiente multiplexor

----------------------------------registro de estado 1------------------------------------------

process (clock)

begin

if clock'event and clock='1' then

if reset ='1' then

Q_bus <= (others => '0');

elsif enable ='1'then

Q_bus <= D_bus;

end if;

end if;

end process;

-------------------------------logica de estado siguiente1--------------------

compara <='1'when Q_bus >= MC else '0';

sumador <= Q_bus+1;

D_bus <= sumador when compara <= '0'else (others=> '0');

-----------------------------logica de salida---------------------------------

Process (clock)

begin
 if clock'event and clock='1'then

if reset ='1' then

Com<= '0';

else

com <= not compara;

end if;

end if

end process;

pulso1 <= com and compara;

in_display <= Q_bus;

end behavioral;

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 08:46:00 04/17/2018

-- Design Name:

-- Module Name: inst_divfreq_anodos-div_freq_anodos - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:
--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

Library IEEE;

Use IEEE.STD_LOGIC_1164.ALL;

Use IEEE.STD_LOGIC_ARITH.ALL;

Use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity div_freq_anodos is

Generic (n: positive:=18);

Port ( clock : in STD_LOGIC;

reset: in STD_LOGIC;

Enable: in STD_LOGIC;

Clkdiv_an: out STD_LOGIC

);

End div_freq_anodos;

Architecture behavioral of div_frecuecnia_anodos is

Signal D_bus,Q_bus : STD_LOGIC_VECTOR (n-1 downto 0);

Signal M, sumador : STD_LOGIC_VECTOR (n-1 downto 0);

Signal compara : STD_LOGIC;

Begin

MC <= ´´110000110101000000´´; ---------------para una relación de 500 hz y un clk 100Meg

---------------------------------registro de estado 1----------------------------

Process (clock)
Begin

If clock´event and clock=´1´then

If reset =´1´then

Q_bus <= (others => ´0´);

Elsif enable =´1´then

Q_bus <= D_bus;

End if;

End if;

End process;

---------------------logica de estado siguiente 1----------------

Compara <= ´1´when Q_ bus >= MC else ´0´;

Sumador <= Q_bus+1;

D_bus <= sumador when compara <= ´0´else (others=> ´0´);

----------------------------logica de salida-------------------------

Clkdiv_an<= compara;

End behavioral;

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 08:31:17 04/17/2018

-- Design Name:

-- Module Name: inst_mux_anodos-mux_anodos-behavioral - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:
-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

Library IEEE;

Use IEEE.STD_LOGIC_1164.ALL;

Entity mux_anodos is

Port (sel : in STD_LOGIC_VECTOR (2 downto 0);

An: out STD_LOGIC_VECTOR (7 downto 0);

End mux_anodos;

architecture behavioral of mux_anodos is

Begin

With sel select

An<=´´11111110´´ when ´´000´´,

´´11111101´´ when ´´001´´,

´´11111011´´ when ´´010´´,

´´11110111´´ when ´´011´´,

´´11101111´´ when ´´100´´,

´´11011111´´ when ´´101´´,

´´10111111´´ when ´´110´´,

´´01111111´´ when others;

End behavioral;

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 08:30:33 04/17/2018

-- Design Name:

-- Module Name: inst_segmentos-segmentos-behavioral - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

Library IEEE;

Use IEEE.STD_LOGIC_1164.ALL;

Entity segmentos is

Port (

Entrada :in STD_LOGIC_VECTOR (3 downto 0);

Salida : out STD_LOGIC_VECTOR (6 downto 0);

End segmentos;
Architecture behavioral of segmentos is

Begin

---------------------------multiplexor---------

With entrada select

Salida <= ´´0000001´´ when ´´0000´´,

´´1001111´´ when ´´0001´´,

´´0010010´´ when ´´0010´´,

´´0000110´´ when ´´0011´´,

´´1001100´´ when ´´0100´´,

´´0100100´´ when ´´0101´´,

´´0100000´´ when ´´0110´´,

´´0001111´´ when ´´0111´´,

´´0000000´´ when ´´1000´´,

´´0000100´´ when ´´1001´´,

´´0001000´´ when ´´1010´´,

´´1100000´´ when ´´1011´´,

´´0110001´´ when ´´1100´´,

´´1000010´´ when ´´1101´´,

´´0110000´´ when ´´1110´´,

´´0111000´´ when others;

--------------------------------------------------------------------------------------

End behavioral;

Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;

Use IEEE.STD_LOGIC_ARITH.ALL;

Use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top level is

port (clock :in STD_LOGIC;

reset : in STD_LOGIC;

enable: in STD_LOGIC;

sw_selM:in STD_LOGIC_VECTOR 81 downto 0);

display: out STD_LOGIC_VECTOR 86 downto 0);

an : out std_logic_vector (7 downto 0);

);

end top_level;

architecture Behavioral of top_level is

-------------------------------------------------------

COMPONENT banco_contadorAN

PORT(

clock: IN std_logic;

reset : in STD_LOGIC;

enable: in STD_LOGIC;

cuent: out std_logic_vector (2 downto 0)

);

END COMPONENT;

----------------------------------------------

Entity banco_contadorAN is

Generic (n : positive := 3);

Port (clock : in STD_LOGIC;

reset: in STD_LOGIC;
enable: in STD_LOGIC;

cuenta : out std_logic_vector (n-1 downto 0)

);

End banco_contadorAN;

Architecture behavioral of banco_contadorAN is

-------------------------------------------------------------------------

COMPONENT contador_anodos

PORT (

clock : IN STD_LOGIC;

reset: IN STD_LOGIC;

enable: IN STD_LOGIC;

cuenta : OUT std_logic_vector (2 downto 0)

);

END COMPONENT;

-------------------------------------------------------------------------

COMPONENT div_freq_anodos

PORT (

clock : IN STD_LOGIC;

reset: IN STD_LOGIC;

enable: IN STD_LOGIC;

clkdiv_an : OUT std_logic

);

END COMPONENT;

-------------------------------------------------------------------------

signal freq500hz : std_logic;

begin

------------------------------------------------------------------------------

Inst_div_freq_anodos: div_freq_anodos PORT MAP (

 Clock=>clock,

Reset =>reset,

Enable=>enable;

Clkdiv_an => freq500hz

);

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

Inst_contador_anodos: contador_anodos PORT MAP (

clock=>clock,

reset =>reset,

enable=> freq500hz;

cuenta => cuenta

);

-------------------------------------------------------------------------------

End behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity top level is

Port (clock :in STD_LOGIC;

reset : in STD_LOGIC;

enable: in STD_LOGIC;
 sw_selM:in STD_LOGIC_VECTOR (1 downto 0);

display: out STD_LOGIC_VECTOR (6 downto 0);

an : out std_logic_vector (7 downto 0);

);

end top_level;

architecture Behavioral of top_level is

-------------------------------------------------------

COMPONENT banco_contadorAN

PORT(

clock: IN std_logic;

reset : IN STD_LOGIC;

enable: IN STD_LOGIC;

cuenta: out std_logic_vector (2 downto 0)

);

END COMPONENT;

----------------------------------------------

Entity banco_contadorAN is

Generic (n : positive := 3);

Port (clock : in STD_LOGIC;

reset: in STD_LOGIC;

enable: in STD_LOGIC;

cuenta : out std_logic_vector (n-1 downto 0)

);

End banco_contadorAN;

Architecture behavioral of banco_contadorAN is

-------------------------------------------------------------------------
 COMPONENT contador_anodos

PORT (

clock : IN STD_LOGIC;

reset: IN STD_LOGIC;

enable: IN STD_LOGIC;

cuenta : OUT std_logic_vector (2 downto 0)

);

END COMPONENT;

-------------------------------------------------------------------------

COMPONENT div_freq_anodos

PORT (

clock : IN STD_LOGIC;

reset: IN STD_LOGIC;

enable: IN STD_LOGIC;

clkdiv_an : OUT std_logic

);

END COMPONENT;

-------------------------------------------------------------------------

signal freq500hz : std_logic;

begin

------------------------------------------------------------------------------

Inst_div_freq_anodos: div_freq_anodos

PORT MAP (

clock=>clock,

reset =>reset,

enable=>enable;

Clkdiv_an => freq500hz

);

-------------------------------------------------------------------------------
-------------------------------------------------------------------------------

Inst_contador_anodos: contador_anodos

PORT MAP (

clock=>clock,

reset =>reset,

enable=> freq500hz;

cuenta => cuenta

);

-------------------------------------------------------------------------------

End behavioral;