Vedic multiplier code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity ha is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

s : out STD_LOGIC;

c: out STD_LOGIC);

end ha;

architecture Behavioral of ha is

begin

s <= ( a xor b);

c <= (a and b);

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity fa is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

cin : in STD_LOGIC;

s : out STD_LOGIC;

cout : out STD_LOGIC);

end fa;
architecture Behavioral of fa is

begin

s <= ( a xor b) xor cin;

cout <= (a and b) or (( a xor b)and cin);

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Adder_4bit is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

b : in STD_LOGIC_VECTOR (3 downto 0);

c : out STD_LOGIC_VECTOR (3 downto 0);

cout : out STD_LOGIC);

end Adder_4bit;

architecture Behavioral of Adder_4bit is

Component ha

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

s : out STD_LOGIC;

c: out STD_LOGIC);

end component;

Component fa

Port ( a : in STD_LOGIC;
 b : in STD_LOGIC;

cin : in STD_LOGIC;

s : out STD_LOGIC;

cout : out STD_LOGIC);

end component;

Signal s: STD_LOGIC_VECTOR (2 downto 0);

begin

ha1:ha port map( a =>a(0),b =>b(0),s=>c(0),c=>s(0));

fa1:fa port map( a =>a(1),b =>b(1),cin=>s(0),s=>c(1),cout=>s(1));

fa2:fa port map( a =>a(2),b =>b(2),cin=>s(1),s=>c(2),cout=>s(2));

fa3:fa port map( a =>a(3),b =>b(3),cin=>s(2),s=>c(3),cout=>cout);

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Adder_6bit is

Port ( a : in STD_LOGIC_VECTOR (5 downto 0);

b : in STD_LOGIC_VECTOR (5 downto 0);

c : out STD_LOGIC_VECTOR (5 downto 0);

cout : out STD_LOGIC);

end Adder_6bit;

architecture Behavioral of Adder_6bit is

Component ha

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

s : out STD_LOGIC;

c: out STD_LOGIC);

end component;
Component fa

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

cin : in STD_LOGIC;

s : out STD_LOGIC;

cout : out STD_LOGIC);

end component;

Signal s: STD_LOGIC_VECTOR (4 downto 0);

begin

ha1:ha port map( a =>a(0),b =>b(0),s=>c(0),c=>s(0));

fa1:fa port map( a =>a(1),b =>b(1),cin=>s(0),s=>c(1),cout=>s(1));

fa2:fa port map( a =>a(2),b =>b(2),cin=>s(1),s=>c(2),cout=>s(2));

fa3:fa port map( a =>a(3),b =>b(3),cin=>s(2),s=>c(3),cout=>s(3));

fa4:fa port map( a =>a(4),b =>b(4),cin=>s(3),s=>c(4),cout=>s(4));

fa5:fa port map( a =>a(5),b =>b(5),cin=>s(4),s=>c(5),cout=>cout);

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Vedic_Multiplier_2bits is

Port ( a : in STD_LOGIC_VECTOR (1 downto 0);

b : in STD_LOGIC_VECTOR (1 downto 0);

c : out STD_LOGIC_VECTOR (3 downto 0));

end Vedic_Multiplier_2bits;
architecture Behavioral of Vedic_Multiplier_2bits is

signal s1: STD_LOGIC;

signal s2: STD_LOGIC;

signal s3: STD_LOGIC;

signal s4: STD_LOGIC;

begin

c(0)<= a(0) and b(0);

s1<=a(1) and b(0);

s2<= a(0) and b(1);

c(1)<= s1 xor s2;

s3<= s1 and s2;

s4<= a(1) and b(1);

c(2)<= s3 xor s4;

c(3)<= s3 and s4;

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Vedic_Multiplier_4bit is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

b : in STD_LOGIC_VECTOR (3 downto 0);

c : out STD_LOGIC_VECTOR (7 downto 0));

end Vedic_Multiplier_4bit;

architecture Behavioral of Vedic_Multiplier_4bit is

Component Vedic_Multiplier_2bits

Port ( a : in STD_LOGIC_VECTOR (1 downto 0);

 b : in STD_LOGIC_VECTOR (1 downto 0);

c : out STD_LOGIC_VECTOR (3 downto 0));

end component;

Component Adder_4bit

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

b : in STD_LOGIC_VECTOR (3 downto 0);

c : out STD_LOGIC_VECTOR (3 downto 0);

cout : out STD_LOGIC);

end component;

Component Adder_6bit

Port ( a : in STD_LOGIC_VECTOR (5 downto 0);

b : in STD_LOGIC_VECTOR (5 downto 0);

c : out STD_LOGIC_VECTOR (5 downto 0);

cout : out STD_LOGIC);

end component;

signal s1 :STD_LOGIC_Vector (3 downto 0);

signal s2 :STD_LOGIC_Vector (3 downto 0);

signal s3 :STD_LOGIC_Vector (3 downto 0);

signal s4 :STD_LOGIC_Vector (3 downto 0);

signal s5 :STD_LOGIC_Vector (4 downto 0);

signal s6 :STD_LOGIC_Vector (5 downto 0);

signal s7 :STD_LOGIC_Vector (3 downto 0);

signal s8 :STD_LOGIC_Vector (5 downto 0);

signal s9 :STD_LOGIC_Vector (5 downto 0);

signal s10 :STD_LOGIC_Vector (5 downto 0);

begin

l1:Vedic_Multiplier_2bits port map( a =>a(1 downto 0),b =>b(1 downto 0),c=>s1);

l2:Vedic_Multiplier_2bits port map( a =>a(3 downto 2),b =>b(1 downto 0),c=>s2);

l3:Vedic_Multiplier_2bits port map( a =>a(1 downto 0),b =>b(3 downto 2),c=>s3);

l4:Vedic_Multiplier_2bits port map( a =>a(3 downto 2),b =>b(3 downto 2),c=>s4);

c(1 downto 0)<= s1( 1 downto 0);

s7<=("00"&s1(3 downto 2));

l5:Adder_4bit port map(a=>s2,b=>s7,c=>s5(3 downto 0),cout=>s5(4));

s8<=("00"&s3(3 downto 0));

s9<=(s4(3 downto 0)&"00");

l6:Adder_6bit port map(a=>s8,b=>s9,c=>s6);

s10<=('0'&s5);

l7:Adder_6bit port map(a=>s10,b=>s6,c=>c(7 downto 2));

end Behavioral;
 Modified booth multiplier code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_unsigned.all;

entity booth_multiplier8 is

Port ( A : in STD_LOGIC_VECTOR (7 downto 0);

B : in STD_LOGIC_VECTOR (7 downto 0);

prod : out STD_LOGIC_VECTOR (15 downto 0));

end booth_multiplier8;

architecture Behavioral of booth_multiplier8 is

begin

process(A,B)

variable D : std_logic_vector(8 downto 0):= (others=>'0');

variable mcd: std_logic_vector(8 downto 0):= (others=>'0');

variable acqr: std_logic_vector(17 downto 0):= (others=>'0');

variable minusA : std_logic_vector(8 downto 0):= (others=>'0');

variable twiceA: std_logic_vector(8 downto 0):= (others=>'0');

variable twice_minusA :std_logic_vector(8 downto 0):= (others=>'0');

variable minusA4 : std_logic_vector(7 downto 0):= (others=>'0');

begin

D :=B&'0';

minusA4:=(((not A)+1));

if A= "10000000" then

minusA:= "010000000";

else

minusA:=minusA4(7)&minusA4;

end if;

mcd:= A(7)&A;

twiceA:=std_logic_vector(A)&'0';

twice_minusA:=minusA(7 downto 0)& '0';

acqr(8 downto 1):=b(7 downto 0);

acqr(0):='0';

for i in 0 to 3 loop

if acqr(2 downto 0)="001" or acqr(2 downto 0)="010" then

acqr(17 downto 9):=mcd + acqr(17 downto 9);

elsif acqr(2 downto 0)="011" then

acqr(17 downto 9):=twiceA + acqr(17 downto 9);

elsif acqr(2 downto 0)="100" then

acqr(17 downto 9):=twice_minusA + acqr(17 downto 9);

elsif acqr(2 downto 0)="101" or acqr(2 downto 0)="110" then

acqr(17 downto 9):=minusA + acqr(17 downto 9);

else

acqr(17 downto 9):=acqr(17 downto 9);

end if;

acqr(15 downto 0):=acqr(17 downto 2);

acqr(16):=acqr(17);

end loop;

prod<=acqr(16 downto 1);

end process;

end Behavioral;