Timing Diagram
Graphical representation
Dr. S. Paul Sathiyan
Asst. Prof / EEE
Timing Diagram
Is a graphical representation. It represents the execution time taken by
each instruction in a graphical format. The execution time is represented in T-
states.
Instruction Cycle:
The time required to execute an instruction is called instruction cycle.
Machine Cycle:
The time required to access the memory or input/output devices is called
machine cycle.
T-State:
• The machine cycle and instruction cycle takes multiple clock periods.
• A portion of an operation carried out in one system clock period is called as
T-state.
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MACHINE CYCLES OF 8085:
The 8085 microprocessor has 5 (seven) basic machine cycles. They are
1. Opcode fetch cycle (4T)
2. Memory read cycle (3 T)
3. Memory write cycle (3 T)
4. I/O read cycle (3 T)
5. I/O write cycle (3 T)
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Opcode Fetch Machine Cycle
• The first step of executing any instruction is the Opcode fetch cycle.
– In this cycle, the microprocessor brings in the instruction’s Opcode from
memory.
• To differentiate this machine cycle from the very similar “memory
read” cycle, the control & status signals are set as follows:
– IO/M=0, s0 and s1 are both 1.
– This machine cycle has four T-states.
• The 8085 uses the first 3 T-states to fetch the opcode.
• T4 is used to decode and execute it.
– It is also possible for an instruction to have 6 T-states in an opcode fetch
machine cycle.
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Memory Read Machine Cycle
• The memory read machine cycle is exactly the same as the
opcode fetch except:
– It only has 3 T-states
– The s0 signal is reset to 0 instead.
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Memory Read Machine Cycle
– To understand the memory read machine cycle, let’s study the execution of
the following instruction: 2000H 3E
• MVI A, 32 2001H 32
– In memory, this instruction looks like:
• The first byte 3EH represents the opcode for loading a byte into the
accumulator (MVI A), the second byte is the data to be loaded.
– The 8085 needs to read these two bytes from memory before it can execute
the instruction. Therefore, it will need at least two machine cycles.
– The first machine cycle is the opcode fetch discussed earlier.
– The second machine cycle is the Memory Read Cycle.
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Memory Write Operation
In a memory write operation:
– The 8085 places the address on the address bus
– Identifies the operation as a ‘memory write’ (IO/M=0, s1=0, s0=1).
– Places the contents of the accumulator on the data bus and asserts the
signal WR.
– During the last T-state, the contents of the data bus are saved into the
memory location.
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ഥ 𝑺𝟎, 𝑺𝟏 𝐂𝐨𝐧𝐭𝐫𝐨𝐥 𝐋𝐢𝐧𝐞𝐬
IO/𝐌,
ഥ
IO/M Comment
0 Memory
1 IO – Input Output
ഥ
IO/𝐌 𝐒𝟏 𝐒0 Comment
0 0 0 HALT
0 0 1 Mem Write
0 1 0 Mem Read
0 1 1 Opcode Fetch
1 0 1 IO Write
1 1 0 IO Read
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Timing Diagram
• Memory Read
– MVI Reg, 8bit
– LXI Reg Pair, 16bit
• Memory Write
– STA 16bit
• IO Read
– IN 8bit address
• IO Write
– OUT 8bit address
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Opcode Fetch M/C Cycle 4207 MOV A,C
4207 79
T1 T2 T3 T4
Clk
ഥ
IO/M
S0
S1
A8-A15
42 Unspecified
ALE
AD0-AD7
07 79
𝑅𝐷
𝑊𝑅
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Opcode Fetch M/C Cycle Mem RD M/C Cycle 4207 MVI B, 03
4207 06
T1 T2 T3 T4 T5 T6 T7
Clk
4208 03
ഥ
IO/M
S0
S1
A8-A15
42 Unspecified 42
ALE
AD0-AD7
07 06 08 03
𝑅𝐷
𝑊𝑅
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4207 STA 4500
Opcode Fetch M/C Cycle Mem RD M/C Cycle Mem RD 4207 32
M/C Cycle Mem WR M/C Cycl
4208 00
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T124209 T45
13
Clk
ഥ
IO/M
S0
S1
A8-A15
42 Unspecified 42 42 45
ALE
AD0-AD7
07 32 08 00 09 45 00 Data
𝑅𝐷
𝑊𝑅
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4207 LDA 4500
Opcode Fetch M/C Cycle Mem RD M/C Cycle Mem RD 4207 3A
M/C Cycle Mem RD M/C Cycle
4208 00
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T124209 T45
13
Clk
ഥ
IO/M
S0
S1
A8-A15
42 Unspecified 42 42 45
ALE
AD0-AD7
07 3A 08 00 09 45 00 Data
𝑅𝐷
𝑊𝑅
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Opcode Fetch M/C Cycle Mem RD M/C Cycle IO RD M/C Cycle 4207 IN 80
4207 DB
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Clk
4208 80
ഥ
IO/M
S0
S1
A8-A15
42 Unspecified 42 80
ALE
AD0-AD7
DATA
07 DB 08 80 80
𝑅𝐷
𝑊𝑅
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MVI B, data
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8085 timing diagram for Opcode fetch
cycle for MOV C, A .
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INR M
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ADD M
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STA addr
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IN Byte
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S. No Instruction with 6 T States for Opcode Fetch
1 CALL – Call Unconditional
2 CC – Call on Carry
3 CM- Call on Minus
4 CNC- Call on No Carry
Conditional Call
5 CNZ- Call on No Zero
6 CP – Call on Positive
7 CPE- Call on Parity Even
8 RC – Return on Carry
9 RM – Return on Minus
10 RNC – Return on No Carry
11 RNZ – Return on No Zero
12 Conditional Return RP – Return on Positive
13 RPE – Return on Parity Even
14 RPO – Return on Parity ODD
15 RST N – Reset
16 RZ – Return on Zero
17 DCX Rp- Decrement Register Pair
18 INX Rp – Increment Register Pair
19 PCHL – Move PC to HL
20 PUSH Rp– Push PC to Stack
21 SPHL – Move HL to SP
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