COE121 Compilation

Quiz#1
Tanqueco, Samantha Aeriel Y. May 15, 2017
COE121/B2 Prof. Villamor
For Quiz 1:
1. Mapua shall be among the best universities in the _____.

a. Philippines
b. Globe
c. Universe
d. World
2. The Institute shall provide a/an _____ in order for its students to acquire the attributes that will
make them globally competitive.
a. Research
b. Development
c. Learning Environment
d. Innovation
3. The Institute shall provide state-of-the-art _____ of industries and communities.

a. Solutions to Problems
b. Answers to Questions
c. Problem solving
d. Conclusion
4. How many core values MAPÚA emphasizes?

a. 2
b. 3
c. 4
d. 5
5. Which is a core value of MAPÚA?

a. Dependable
b. Open-minded
c. Excellence
d. Adveturous
6. Who invented the Babbage Difference Engine?
a. Charl Babbage
b. Charles Babbage
c. Jack Babbage
d. Jack Kilby
7. Used when computing machines only perform simple arithmetic.

a. ASCII
b. Operation Code
c. Binary-Coded Decimal
d. ENIAC
8. It is also considered as a Special Purpose Register.

a. General Purpose Registers
b. Segment Registers
c. Multipurpose Registers
d. Accumulator
9. Points to a memory location in all versions of the microprocessor for memory data transfers.
a. Base Index
b. Data
c. Destination Index
d. Base Pointer
10. Additional Data Segment used by some of the string instructions.

a. Code Segment Register
b. Data Segment Register
c. Extra Segment Register
d. Stack Segment Register
11. It is found at bit 0.

a. Carry Flag
b. Parity Flag
c. Zero Flag
d. Sign Flag
12. A Trap Flag enables trapping through an on-chip debugging feature. If T = ?, it will debug. If T = ?,
it will not debug.
a. 00,11
b. 11,00
c. 0,1
d. 1,0
13. It occurs when signed numbers are added or subtracted and indicates that the result has
exceeded the capacity.
a. Interrupt Flag
b. Overflow
c. Nested Task
d. Sign Flag
14. Instruction decoder interprets the address.

a. Reset
b. Fetch
c. Decode
d. Execute
15. Memory is sometimes accessed, I/O devices are used to display the result of the instruction
execution.
a. Reset
b. Fetch
c. Decode
d. Execute
1.) It is a type of integrated circuit or chip and is the heart of every computer.
a. Monitor
b. Keyboard
c. Internet
d. Microprocessor
Ans. D
2. Which of the following is not an Intel engineer?
a. Gary Boone
b. Ted Hoff
c. Federico Faggin
d. Stan Mazor
Ans. A
3. First Intel microprocessor invented is _____?
a. Intel 4008
b. Intel 4004
c. Pentium 1
d. Intel 8008
Ans. B
4. What does A in ASCII stands for?
a. American
b. Algorithm
c. African
d. Access
Ans. A
5. According to Moore’s law, the number or complexity of transistors per IC ______ every 2 years. a.
Triples
b. Quadruples
c. Doubles
d. Stays the same
Ans. C
6. What does ALU stands for?
a. Arithmetic Logic Unit
b. American Logic Unit
c. American Logical Unit
d. Arithmetic Logical Units
Ans. A
7. Robert Noyce and Gordon Moore are the founders of ______?
a. Texas Instruments
b. Motorola
c. Intel
d. Samsung
Ans. C
8. What does I in ENIAC stands for?
a. Integrated
b. Integrator
c. Intel
d. Integral
Ans. B
9. Transistors are ____ generation of microprocessors.
a. 4th
b. 3rd
c. 2nd
d. 1 st
Ans. C
10. Intel is shortened word for _____?
a. Integrated Electronics
b. Intelligence
c. Interrupt
d. Integrated and Electrical
Ans. A
1. by common practice, 8-bit binary numbers are referred to as ____ ?
A. Bits
B. Bytes
C. Kilobytes
D. Megabytes
ANS: B
2. A special parallel operation that is used to transfer data from a hard disk to a microcomputer’s
memory?
A. Direct memory access (DMA)
B. Random access memory (RAM)
C. Read only memory (ROM)
D. None of the choices
ANS: A
3. It is a type of a flag register that indicates if result equals to zero.
A. Carry Flag (CF)
B. Zero Flag (ZF)
C. Sign Flag (SF)
D. Interrupt Flag (IF)
ANS. B
4. Intel CPUs are also called __________ computers, while Motorola processors are called __________
computers.
A. little endian; big endian
B. big endian; little endian
C. little indian; big indian
D. big indian; little indian
ANS. A
5. It is a type of flag register that provides single-step capability for debugging.
A. Trap Flag (TF)
B. Nested Task (NT)
C. Overflow Flag (OF)
D. Auxiliary Flag (AF)
ANS. A
6. It is a type of flag register that contains carry out of MSB of result.
A. Overflow Flag (OF)
B. Auxiliary Flag (AF)
C. Interrupt Flag (IF)
D. Carry Flag (CF)
ANS. D
7. 32-bit binary numbers are referred to as __________.
A. Double-Word
B. Long-Word
C. Word
D. Both A and B
ANS. D
8. The first practical IC was developed in this year.
A. 1959
B. 1961
C. 1967
D. 1973
ANS. A
9. This element is the one responsible in decoding the operation code of an instruction.
A. Instruction Encoder
B. Instruction Converter
C. Instruction Interpreter
D. Instruction Decoder
ANS. D
10. This element is the one responsible in monitoring the bus operation.
A. Bus Snooping
B. Watchdog Monitor
C. Branch Prediction
D. Address Bus
ANS. B
11. Simulate the given instructions (below) and determine which among the choices is correct.
Initially CF=0; AF=0; ZF=0; IF=0
MOV AL, 1F
MOV BL, F1
ADD AL, BL
Assume that there is an interrupt.
A. CF=1; AF=1; ZF=1; IF=1;
B. CF=1; AF=1; ZF=0; IF=1;
C. CF=1; AF=0; ZF=0; IF=0;
D. CF=1; AF=1; ZF=0; IF=0
ANS. B
MOV AL, 1F MOV
BL, F1
ADD AL, BL
A. CF=1; AF=1; ZF=1; IF=1;
B. CF=1; AF=1; ZF=0; IF=1;
C. CF=1; AF=0; ZF=0; IF=0;
D. CF=1; AF=1; ZF=0; IF=0
ANS. A
MOV AL, FF
MOV BL, 01
ADD AL, BL
CLC
CLI
A. CF=1; AF=1; ZF=1; IF=1;
B. CF=0; AF=1; ZF=0; IF=1;
C. CF=0; AF=0; ZF=0; IF=0;
D. CF=0; AF=1; ZF=0; IF=0
ANS. D
14. A hardware ________ is an event that occurs while the processor is executing an instruction. It
temporarily suspends execution of the main program in favor of a special routine that services it. A.
Interrupt
B. Error
C. Restrict
D. Interject
ANS: A
15. A method that began with the 8-bit 8080 and has been used on all upgrades from the 8085 to the
Pentium is a technique called _____ ?
A. Byte-changer
B. Byte-swapping
C. Byte-swarming
D. None of the choices
ANS: B
Tarun, Nars-Icon Z.
COE121/B2
QUIZ #1
MULTIPLE CHOICE
1. If a POP instruction is executed, the base pointer will be ____ by two
a. subtracted
b. incremented
c. added
d. multiplied
ANS: b. INCREMENTED
2. This register works very closely with the instruction decoder of the control unit and stores all
instructions coming from the data bus
a. instruction register
b. segment register
c. index register
d. memory register
ANS: INSTRUCTION REGISTER
3. This element is always in phase with the clock system of the microprocessor
a. Program Counter
b. Timing
c. Little Endian
d. DMA
ANS: a. PROGRAM COUNTER
4. These are signals that indicate need of attention, perform special task and resume the pre-empted
operation.
a. address bus
b. program loader failure
c. interrupt
d. control logic
ANS: c. INTERRUPT
5. This is a group of lines that has a related function within a microprocessor system.
a. address bus
b. system bus
c. control bus
d. data bus
ANS: b. SYSTEM BUS
6. This element serves as a medium of communication between the processor and the outside world
a. i/o port
b. DMA
c. data segment
d. ALU
ANS: a. I/O PORT
7. This element is the one responsible in monitoring the bus operation
a. control logic
b. watchdog monitor
c. instruction decoder
d. DMA
ANS: b. WATCHDOG MONITOR
8. This is used to indicate the results of arithmetic and logical instructions
a. data segment
b. synchronization
c. flag
d. ALU
ANS: d. ALU
9. The first microprocessor was delivered by _____ with the help of Ted Hoff in 1971 a. Gordon Moore
b. Bill Gates
c. Paul Allen
d. Robert Noyce
ANS: d. Robert Noyce
10. Used in the first PC, the ALTAIR computer. Created at MITS by ED ROBERTS. No keyboard and
monitor. Can only be programmed in straight binary.
a. Intel 4004
b. Intel 8080
c. Intel 8088
d. Intel 8086
ANS: b. Intel 8080
QUIZ #1
COE121 - B1
4Q1617
PREPARED BY: NEO JADE A. DE GUZMAN / 2013102865
I. TRUE OR FALSE
1. The name of Japanese company that produces the first microprocessor that could carry
out calculator's functions is BUSICOM. TRUE
2. BCD or Bulk Coded Decimal is used as computing machines that performs simple
arithmetic operations? FALSE
3. Inted 4040 is the first single-chip microprocessor. FALSE
4. A Transistor acts as logical switches in digital circuits. It replaced the vacuum tubes.
TRUE
5. INTEL 8081 is a microprocessor that used in the first pc or ALTAIR computer which
created by Ed Roberts. FALSE
II. IDENTIFICATION
1. He developed a single general-purpose chip that could be programmed to carry out calculator's
function. Ted Hoff
2. This is an 8-bit microprocessor that can handle a simple word processing and was developed in
1973. Intel 8080
3. This processor is considered as one of the XTs or experimental technologies. Intel 80186
4. This element is the one respolnsible in creating signals or commands for the execution of the
instruction. Control Logic
5. Base Index register is responsible in handling this type of address. Offset Address, Relative,
Displacement
6. If pin INTR is connected to the ground, which flag is affected? Interrupt Flag
7. This register is the one responsible in pointing to the address of the next instruction to be fetched
and executed. Program Counter
8. This element is the one responsible in decoding the operation code of an instruction. Instruction
Decoder
9. Which among the choices that does not serve as a pathway? Address Bus
10. This element is the one responsible in monitoring the bus operation. Watchdog Monitor
11. Which among the choices is not a software interrupt? Program Loader Failure
12. Which among the choices is not one of the categories of interrupts? Hardware Interrupt
13. These are signals that indicate need of attention, perform special task and resume the pre-
empted operation. Interrupts
14. This element serves as a medium of communication between the processor and the outside
world. I/O Port
15. This is a group of lines that has a related function within a microprocessor system. System Bus
16. This is very important because it signifies how powerful an Integrated Circuit is. Level of
Integration
17. Which of the following is not part of the Microprocessor? Memory
18. These are used to indicate status of the microprocessor and even control some of its features.
Flag
19. Which among the flags is affected by the direction flow during string operations? Direction Flag
20. The first practical IC was developed in this year. 1959
Using the given information in table #1 and determine which among the choices is correct.
INSTRUCTION/S OPCODE ADDRESS/ES
1.MOV AX, DEF8 B8F8DE 1234-1237
2.MOV BX, AD23 BB23AD 1238 -123A
3.ADD AX, BX 03C3 123B -123C
4.MOV DX, 7EBF BABF7E 123D -123F
5.SUB DX, AX 2BD0 1240 -1241
6.HLT F4 1242
21. What is the OpCode for the operator MOV AX? B8

22. What is the OpCode for the operator MOV BX? BB
23. At what address will the program counter point to if the next to be fetched and executed is
instruction #5? 1240
24. At what address will the program counter point to if the next to be fetched and executed is
instruction #3? 123B
25. What will happen if instruction #3 is executed? AX=8C1B; CF=1
26. What will happen if instruction #5 is executed? DX=F2A4; CF=1
27. How many memory locations does instruction #4 requires? 1,2,3,4
28. #2 is a ? - byte size instruction. 3-byte size
29. What is the content of address 1239? 23
30. If a POP instruction is executed, the base pointer will be ____ by two. incremented
31. This register serves as a bank of codes. Code Segment
32. This instruction is used to put information onto the stack. PUSH
33. This processor is one of the ATs or Advance Technologies. Intel 80486
34. Which among the choices is not true about flag register? This register is 11-bit size.
35. Which among the choices is not part of the standard block diagram of a microprocessor? NVM
36. Is interrupt logic the same with interrupt circuitry? Yes
37. Which among the choices is at par with Intel 8086 when it comes to its performance? Intel 8088
38. Was used to build electronic numerical integrator and computer. Vacumm Tubes
39. This is the main focus of all the designers of computers. Speed
40. This element is the one responsible in setting the schedule. Timing
41. This element stores information either temporarily or permanently. Memory
III. ENUMERATION
A) Give the Mission and Vision of Mapua Institute of Technology
42. Mapua shall be among the best universities in the world.
43.The institute shall provide a learning environment in order for its students to acquire
the attributes that will make them globally competitive.
44. The institute shall engage in economically viable research, development and
innovation.
45. The institute shall provide state-of-the-art solutions to problems of industries and
communities.
IV Matching Type A. Intel 4004
P 1 States the result that contains carry B. Auxiliary Flag
H 2 States if the result occurred exceeded the C. Interrupt Flag

limit
D. Pentium III
G 3 States the direction flow during string
E. Pentium 4
operations
F. Input/Output Privilege Level
B 4 States the condition of the bit 3 and bit 4
G. Direction Flag
J 5 Used in the first PC, the ALTAIR computer.
Created at MITS by ED ROBERTS. No keyboard H. Overflow Flag
and monitor. Can only be programmed in
straight binary. I. Trap Flag
C 6 States the condition of Interrupt Request J. Intel 8008

Input Pin K. Nested Task
A 7 The first single-chip microprocessor. L. Sign Flag
F 8 States the priority level of the current task M. Parity Flag
E 9 Used in desktops and entry-level N. Zero Flag
workstations.
O. Intel 8080
I 10 States the microprocessor’s debugging
feature. P. Carry Flag
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
Quiz#2
Tanqueco, Samantha Aeriel Y. May 28, 2017 COE121/B2
Prof. Villamor
For Quiz 2:
CHAPTER 13,
1. Transfers data from the memory to the I/O device.

. Data Transfer Speed
. DMA controller
. DMA write
. DMA read
ans. D
2. The _____ is a four-channel device that is compatible with the 8086/8088 microprocessors. a.
8237
. 8141
. 8220
. 8188
ans. A
3. Clears the command, status, request, and temporary registers. It also clears the first/last flipflop and sets the mask register.
Clock Input
Reset Pin
Chip Select
Hold Acknowledge
ans. B
4. In the Software Commands, it enables all four DMA channels.

. Clear the First/Last Flip-flop
. Master Clear
https://canvas.instructure.com/courses/918717/quizzes/1176306 17/80
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
. Clear Mask Register
. Master Clean ans. C
5. Often called a rigid disk or a fixed disk because it is not removable. a. Disk Memory
. Floppy Disk
. Hard Disk
. Memory Disk
Ans. C
CHAPTER 15,
6. The _____ bus is virtually the only bus found in the newest Pentium 4 systems and just about all the Pentium systems.
a. Industry Standard Architecture
b. Universal Serial
c. Parallel Printer Interface
d. Peripheral Component Interconnect
ans. D
7. Which is not a data transfer rate of a USB?

a. 1.5 Mbps
b. 12 Mbps
c. 580 Mbps
d. 480 Mbps
ans. C
8. The _____ is a high-speed connection between the memory system and the video graphics card. a. Parallel Port
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
b. Accelerated Graphics Port
c. Serial Communications Ports
d. Connector Port
ans. B
OTHER TOPICS,
9. Computer operate in these modes except

a. Real Mode
b. Protected Mode
c. Flat Memory Mode
d. Address Mode
ans. D
10. Floating Point cannot be paired with a/an _____ and vice-versa. a. Integer
b. CISC
c. RISC
d. SIMD
ans. A
11. When two instructions are to be pair, it:

a. Must Lack Dependencies
b. Must be Basic
c. Must Contain No Displacement
d. All of the Above
ans. D
12. In the Brach Prediction, which state predict a jump?

a. State 0, State 1
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
b. State 1, State 2
c. State 2, State 3
d. State 0, State 3
ans. C
1. The three kinds of processor modes or CPU modes.

A. Real, Protected and Privilege mode
B. Real, Privilege and Plain mode
C. Real, Plain and Protected mode
D. Real, Protected and Flat mode
ANSWER: D
2. The state where the data requested for processing by a component or application is not found in the cache memory?
A. Cache Hit
B. Cache drop
C. Cache fluff
D. Cache miss
ANSWER: D
a3. Choosing to make the instruction set smaller using fewer instructions and simpler addressing codes was the decision of
____________ designers.
A. Computer
B. CISC
C. RISC
D. System
ANSWER: C
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
4. RISC is also known as _________.

A. Resized Instruction Set Compatibility
B. Reduced Instructions Set Computers
C. Resized Instructions Set Compatibilities
D. Reduced Instruction Set Computer
ANSWER: D
5. A __________ allows a new 8-byte chunk to transfer every clock cycle.

A. Burst operation
B. Bus operation
C. Pipelining
D. Brach Prediction
ANSWER: A
6. The Pentium is known as a superscalar machine because ___________.

A. it can execute three integers or three floating-point instructions simultaneously.
B. it can execute ten integers or ten floating-point instructions simultaneously.
C. of its Pentium’s twin U and W pipelines.
D. it can perform parallel instruction execution of multiple instructions.
ANSWER: D
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
7. It is used to help maintain consistent data in a multiprocessor system where each processor has a separate cache.
A. TLBs
B. Triple Ported
C. Cache Coherency
D. Bus Snooping
ANSWER: D
8. Which is NOT a component of NetBurst Architecture?

A. HyperPiped Line Technology
B. Rapid Execution Engine
C. Execution Trace Cache
D. None of the above
ANSWER: D
9. It provides a way for other processors in a multiprocessor system to instantly take over the Pentium’s buses.
A. BOFF
B. Shutdown
C. Bus Hold
D. HALT
ANSWER: A
10. An implementation technique where multiple instructions are overlapped in execution?

A. Superscaling
B. Pipelining
C. RISC D. CISC
ANSWER: B
1. A _____ cycle is run if the Pentium detects an interval parity error.
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
A. shutdown
B. restart
C. bus snooping
D. Debug
Ans. A
2. This data dependency exists if the second instruction reads an operand written to it by the first instruction.
A. write after read
B. execute
C. execute after read
D. read after write
Ans. D
3. Bus ______ cycle is when the Pentium processor is able to watch the system bus in a multiprocessor system.
A. clearing
B. snooping
C. sweeping
D. cleaning
Ans. B
4. This specifies the percentage of hits to total cache accesses

A. miss ratio
B. accuracy
C. precision
D. hit ratio
Ans. D
5. This translate linear addresses into physical addresses

A. MESI
B. TTL
C. TTF
D. TLB Ans. D
6. This is a Pentium’s mechanism that is used to maintain cache coherency in its data cache.
A. TLB
B. TTL
C. TTF
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
D. MESI
Ans. D
7. The state where the data requested for processing by a component or application is not found in the cache memory?
A. Cache Hit
B. Cache miss
C. Cache drop
D. Cache fluff
Ans. B
8. CISC stands for ___________________.

A. Complex Instructive System Computer
B. Complex Instruction System Computer
C. Complex Instruction Set Computer
D. Complex Instructive Set Computer
Ans. C
9. Choosing to make the instruction set smaller using fewer instructions and simpler addressing codes was the decision of
____________ designers.
A. Computer
B. CISC
C. RISC
D. System Ans C
10. As the Pentium also contains six 16-bit segment registers, 32-bit stack pointer, and eight ______. A. Floating point registers
B. Index registers
C. Control flags
D. Offset Addresses
Ans. A
11. A __________ allows a new 8-byte chunk to transfer every clock cycle.
A. Burst operation
B. Bus operation
C. Pipelining
D. Brach Prediction
Ans. A
12. Bus _______ input provides a second way for a different bus master to take control of the
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
Pentium’s buses.
A. BOFF
B. HOLD
C. INTR
D. FLUSH
Ans. B
13. Also known as an external cache.

A. Second-level cache
B. Third-level cache
C. Data cache
Ans. A
12. Which is true about caches?

A. It speeds up access to memory and reduce traffic on the processor’s buses.
B. When an instruction or data is found in the cache it is called a hit.

C. When an instruction or data is not found in the caches it is called a miss.
D. All of the above.
Ans. D
13. Bus snooping is used to maintain consistent data in a __________________. A.

Multiprocessor system where each processor has one cache.
B. Multiprocessor system where each processor has a separate cache.
C. Multiprocessor system where both processors has a separate cache.
D. Multiprocessor system where both processors has one cache.
Ans. B
14. The state in which data requested for processing by a component or application is found in the cache memory?
A. Cache Hit
B. Cache miss
C. Cache Drop
D. Cache fluff
Ans. A
15. It is used to store frequently used data.

A. Data Cache
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
B. Instruction Cache
C. Address Cache
Ans. A
16. It is a technique used to enable one instruction to complete with each clock cycle.
A. Clock
B. Pipelining
C. Non-pipelining
D. Float Pointing
Ans. B
17. It is used to store frequently used instructions, such as those in a short loop.
A. Data Cache
B. Instruction Cache
C. Address Cache
Ans. B
18. It is a special type of high speed RAM where data and the address of the data are stored. A. Clock
B. Burst Ready
C. Cache
D. Bus Lock Ans. C

19. An internal parity error is detected by the Pentium allowing the _________ to run.
A. Shutdown
B. Halt
C. Pipelined
D. Inquire Ans. A
20. Compute for the number of clock cycles of the following instructions in UV pipelining.
MOV AX, 02 MOV

BX, 03 MOV CX,
04
ADD AX, CX
INC BX
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
SUB BX, AX
MOV CX, BX
DEC CX
A. 8
B. 9
C. 10 D. 11
Ans. C
1. Pentium III’s former name is ______.

a. Katmai
b. MMX
c. Superscalar
d. Xeon
Ans. A
2. It is the architectural advancement to the IA-32 architecture.

a. SSE
b. SSE2
c. SSE3
d. SSE4
Ans. B
3. It introduced dual-core technology.

a. Intel Celeron
b. Intel Xeon
c. Pentium III
d. Intel Pentium Processor Extreme Edition
Ans. D
4. It is based on Intel Netburst Microarchitecture.
a. Pentium I Processor Family
b. Pentium II Processor Family
c. Pentium III Processor Family
d. Pentium 4 Processor Family
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
Ans. D
5. Three methods of prefetching are the following except for?

a. renaming only
b. instruction only
c. data only
d. code or data
Ans. A
Determine whether the following characteristics points to CISC or RISC.
CISC 1. Emphasis on hardware

RISC 2. Single-clock, reduced instruction only
RISC 3. Spends more transistors on memory registers
RISC 4. Store and load are independent instructions
CISC 5. Load and store are incorporated in instructions
CISC 6. Includes multi-clock complex instructions
RISC 7. Software is its emphasis
CISC 8. Transistors used for storing complex instructions
CISC 9. High cycles per second RISC 10. Short or low cycles per
second Fill in the blanks.
1. MMX – Multi____ Extension Media
2. SIMD - ____ Instruction stream Multiple Data stream Single
3. BTB – Branch _____ Buffer Target
4. CISC - _____ Instruction Set Computer Complex
5. RISC - _____ Instruction Set Computer Reduced
6. SSE – Streaming ____ Extensions SIMD
Reyes, Malvin Angelo C.
COE121/B2
1. The prediction of whether a jump will occur or not, is based on the behavior of the _________.
2. _________ divides the instruction execution pipeline into the smaller stages.
3. _________ executes two or more instruction per clock cycle by using multiple execution units. 4.
What does MMX stand for? ___________
5. _________ is a new approach to processing S/W instructions that reduces idle processor time.
6. It is a processor that includes 4-way and 8-way, 2 Mbyte 2nd-level cache running on a dual-clock speed backside bus.
___________.
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
7. What does SSE stand for? ______________.
8. Designed for extending battery life and seamless integration. ___________
9. Introduced dual-core technology that provides advanced H/W multi-threading support. ___________
10. SSE and SSE2 both support operations on 128-bit XMM register. True or False? ___________
11. It is a decoded RISC-like instructions. ___________
12. When was the Intel Celeron Processor introduced? ___________
13. Give one of the risks of overclocking the Celeron. ___________
14. How many stages of pipeline does a Hyper-Pipelined Technology has in order to enable high clock rates?
___________
15. In Branch Prediction, the _____________is designed to optimize the performance by handling the most common operations
in the most common context as fast as possible.
Answers:
1. Branch Prediction
2. Superpipelining
3. Superscalar
4. Multimedia Extension
5. Dynamic Execution
6. Pentium II Xeon processor
7. Streaming SIMD Extensions
8. Intel Pentium M Processor
9. Intel Pentium Processor Extreme Edition
10. True
11. Micro-op
12. 1999
13. Destroying the Chip
14. 20
15. Out-of-Order Execution
QUIZ #3
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
SET 1
1. How to calculate the physical memory location or the memory address?
Answer: (Segment Register x 10) + Offset
2. In the real mode, show the starting and ending addresses of each segment located by the following segment register
values:
Segment Address Starting Address Ending Address

a. 1000H 10000H 1FFFFH
b. 2301H 23010H 3300FH
c. E070H E0700H F06FFH
Solution:
a. Starting Address: 1000H x 10 = 10000H
Ending Address: 10000H + FFFF = 1FFFFH
b. Starting Address: 3300FH – FFFF = 23010H

Segment Address: 23010H / 10 = 2301H
c. Segment Address: E0700H /10 = E070H

Ending Address: E0700H + FFFF = F06FFH
3. Find the memory address of the next instruction executed by the microprocessor, when operated in the real mode,
for the following CS: IP and 80286 register combinations:
a. CS = 2987H and IP = 1452H 2ACC2H

b. SS = 2900H and SP = 3A00H 2CA00H
c. DS = A000H and BX = 1000H A1000H
Solution:
a. 29870H + 1452H = 2ACC2H
b. 29000H + 3A00H = 2CA00H
c. A0000H + 1000H = A1000H
4. For a Core2 descriptor that contains a base address of 01000000H, a limit of 0FFFFH, and G = 0, what starting and
ending locations are addressed by this descriptor?
Answer: Start = 01000000H

End = 100FFFFH
Solution:
Base address = 01000000H
Limit = 0FFFFH
G=0
Start = Base = 01000000H

End = Base + Limit
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
= 01000000H + 0FFFFH
End = 100FFFFH
5. For a Core2 descriptor that contains a base address of 28000000H, a limit of 00100H, and G = 1, what starting and
ending locations are addressed by this descriptor?
Answer: Start = 28000000H

End = 28100FFFH
Solution:
Base address = 28000000H
Limit = 00100H
G=1
Start = Base = 28000000H

End = Base + Limit
= 28000000H + 00100FFFH
End = 28100FFFH
SET 2
1. The most common addressing mode that consists of a 16 bit constant that specifies the address of the target location:
a. Register addressing mode c. displacement-only addressing mode
b. Immediate addressing mode d. base plus index addressing mode
Answer : c.
2. What is the starting and ending address of the segment address, 3456H?
a. 3456∅H, 4455FH c. 6543∅H, 5545FH
b. 3546∅H, 4378FH d. 2134∅H, 4545FH
Answer: a.
3. What is the starting and ending address of the segment located by the segment register value, 1000H?
a. 12340H , 2233FH c. 12000H, 1FFFFH
b. E0000H, EFFFFH d. 10000H, 1FFFFH
Answer: d.
4. An addressing form in which the byte value to be used or retrieved in the instruction, is located immediately after the
opcode for the instruction itself.
a. Immediate addressing mode c. Direct addressing mode
b. Indirect addressing mode d. register addressing mode
Answer: a.
5. In this addressing mode, the data in a segment of memory are addressed by adding the displacement to the contents of a
base or an index register (BP, BX, DI, or SI).
a. Immediate addressing mode c. Indirect addressing mode
b. Register relative addressing mode d. Direct addressing mode
Answer: b.
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
6. What segment address has the starting address of ABCD∅H and an ending address of BBCCFH?
a. BCDAH c. ABDCH
b. DACDH d. ABCDH
Answer: d.
7. Given CS=1000H and IP= 2000H, Find the memory address of the next instruction executed by the microprocessor.
a. 15000H c. 12000H
b. 12500H d.21000H
Answer: c.
8. This mode uses a register to hold the actual address that identifies either the source or the destination to be used in the
data move.
a. Indirect addressing mode c. Direct addressing mode
b. Register relative addressing mode d. Immediate addressing mode
Answer: a.
9. Given CS= 2000H and IP= 1000H, Find the memory address of the next instruction executed by the microprocessor.
a. 21000H c. 2100H
b. 22000H d. 12000H
Answer: a.
10. One must never use the segment registers as data registers to hold arbitrary values because:
a. They should only contain register addresses
b. The should only contain ending addresses
c. They should only contain segment addresses
d. They should only contain indirect addresses
Answer: c.
SET 3
1. Code a descriptor that describes a memory segment that begins at location 003F BA68H and ends at location 00DA 3FBDH.
The memory segment is a code segment and can’t be read. The instruction used is a 16-bit size. It is also assumed that the segment
has been accessed. What is byte number 0?
A. 85
B. 09
C. A8
D. 55
2. Given the following: Var3=8EB7, ECX=9D12, ESI=A97C D18AH, EDI=AC99 B558H, EBX-BE83 48E5H. Suppose that
DS=0046H, what will be the address/es accessed by the instruction MOV EBP, Var3 [ECX][EDI-E6B2H] assuming protected
mode?
A. 16A6F781A-16A6F781D
B. 16A6F781A
C. 16A6F781A-16A6F781C
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
D. 16A6F781A-16A6F781B
3. This is used to select data memory addressing mode.

A. R/M field
B. MOD field
C. Direction Bit
D. REG field
4. What is memory address of the next instruction executed by the microprocessor when operated in real mode for combinations
DS=3DC7H and DX=ACE3H?
A. EAAA
B. 4DC6FH
C. 48953H
D. 1EAA9
5. Given the instruction MOV=CY[BP][CX+1024], AL, which among the segment registers has the highest priority?
A. Stack segment
B. Data segment
C. Code segment
D. Extra segment
6. This addressing mode moves a byte or a word between a register and a memory location addressed by an index register plus a
displacement.
A. Register relative
B. Base relative plus index
C. Direct addressing mode
D. Base plus index
7. This is an additional byte that appends to the front of an instruction to select an alternate segment register.
A. Displacement
B. Segment Register
C. Operand
D. Segment override prefix
has been accessed. What is byte number 0?
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
A. B9
B. BC
C. 9D
D. BD
9. In real mode, this jump accesses any location within the first 1M byte of memory by changing both CS and IP.
A. Intrasegment Jump
B. Far Jump
C. Near Jump
D. Short Jump
10. This register defines the starting address of the section of memory holding code.
A. Segment Address
B. Code Segment
C. Memory
D. Program Address
11. In the case that the descriptor privilege level is given in the problem, which among the choices is true?
A. C is 0
B. DPL is 00
C. C is reset
D. C is set
12. Suppose that DS=E3DAH, SS=DB67H, BX=23FEH, DX=F8BCH, DI=87CCH, BP=AAE4H, SI=9FEBH, ER=DC45H, and
FI=C6FH. What will be the content/s of the destination by the instruction MOV FI[BP][SI][5FADH], DX?
A. 1B6EB
B. F8
C. F8BC
D. 1B6EB-1B6EC
13. Suppose that DS=E3DAH, ES=CF69H, SS=DB67H, AX=9BCDH, BX=23FEH, DX=F8BCH, DI=87CCH, BP=AAE4H,
SI=9FEBH, ER=DC45H, and FI=C6FH. What is the address accessed by the instruction MOV AH, ER[DI+BX]?
A. 9B
B. E7E9F-E7EA0
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
B. CD
D. E7E9F
14. For a Pentium Pro descriptor that contains and address of 00DF 34EBH, a limit of 9DE5C, and G=1. What is the ending
address location addressed by this descriptor?
A. 9EC4F4EBH
B. 0DFD2D0CH
C.00E91347
D. 9EC504EAH
15. If DS=003DH, what is the ending address assuming protected mode?

A. 7135349FH
B. 71362439H
C. C7074439H
D. 7131915BH
has been accessed. The privilege level is third to the lowest. What the limit?
A. 9A855
B. 009A8
C. 009A8
D. A8555
17. This refers to the location that is called or jumped to instead of the actual numeric address.
A. Label
B. Address Name
C. Heading
D. Directive
18. In the real mode, what is the ending address of the segment located by the segment register value F9A4H?
A. 1F9A3
B. E9A41
C. 109A3F
D. F9A40
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
19. A SUB instruction stores a value BA67H at offset value BDEFH. If the computed address is 53DBFH, what will be the ending
address? Assume real mode operation.
A. 4AFD0
B. 5AFCF
C. 53DBF
D. 4BFCFF
20. An ADD instruction stores a value 7308h at offset value 9371h. If the computed address is 7CB31h, what will be the ending
address? Assume real mode operation.
A. 82BBFH
B. 72BC0H
C. 73BBFFH
D. 7CB31H
SET 4
Multiple Choice
1. It is also called conventional memory system

a. Real mode
b. Protected mode
c. Conventional mode
d. Memory mode
2. Real mode must consist of _______.

a. Segment address only
b. Offset address only
c. Segment and offset address
d. None of the choices
3. RPL means ______.

a. Real Privilege Level
b. Requested Privilege Level
c. Real Protected Level
d. Requested Protected Level
4. TI means ______.
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
a. Table Identifier
b. Table Indicator
c. Task Identifier
d. Task Indicator
5. TI=0 indicates that TI is _______.

a. A local descriptor table
b. A real descriptor table
c. Not a descriptor table
d. A global descriptor table
Match the following instructions to its appropriate addressing mode type.
a. Immediate addressing
b. Register addressing
c. Direct addressing
d. Register indirect
e. Based addressing
f. Index addressing
g. Base relative plus index addressing
h. Based index with displacement addressing
i. Scaled- index addressing
__b_1. MOV AL, BL

__i_2. MOV [EBX+2*ESI], AX
__g_3. MOV ARRAY[BX+SI], DX
__h_4. MOV AL, [BP+SI+disp]
__e_5. MOV AX, [BX+4]
__a_6. MOV AL, 12H
__d_7.MOV DL, [SI]
__c_8. MOV[500H], AL
__f_9.MOV [ DI-8], BL
Determine whether the instruction is allowable or not: A- allowable / NA- not allowable
NA 1. MOV ES, DS
A 2. MOV AX, BX
NA 3. MOV CS, AX
A 4. MOV [BX], CL
NA 5. MOV [DI], [BX]
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
SET 5
1.) The source file is converted into an __________ wherein it contains all the actual binary information.
A. Machine code
B. Pseudo-opcode
C. List file
D. Object file
Ans: D
2.) An _________ is a special program that will understand the contents of the object file/
A. Assembler
B. Compiler
C. Linker
D. Library
Ans: A
3.) This type of assemblers work with one source line at a time and are restricted in operation.
A. One-liner-assemblers
B. Special-assemblers
C. Cross-assemblers
D. Single-line-assemblers
Ans: D
4.) ______ contains many new pseudocodes to help the assembler generate the correct machine code for the object file.
A. Module
B. Operands
C. Segments
D. Linker
Ans: C
5.) Data transfer group contains instructions that transfer from ____________.
A. Memory to register, register to memory, memory to memory, register to register
B. Memory to memory, register to register, register to memory
C. Memory to memory, memory to register, register to memory
D. Memory to register, register to register, register to memory
Ans: D
6.) A _____ is a collection of bytes stored sequentially in memory, whose length can be up to _______.
A. String, 64KB
B. String, 8KBytes
C. Char, 1KB
D. Char, 64KB
Ans: A
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
7.) Bit manipulation is used for __________.

A. AND, OR, NOR, NOT
B. AND, OR, XOR, NOT
C. AND, NOR, OR, XOR
D. TEST, NOR, AND, OR
Ans: B
8.) Address is referred to ________ when the processor’s address bus is formed by some combination of segment register and
an additional numerical offset.
A. Effective Address
B. Immediate Addressing
C. Register Addressing
D. Base Addressing
Ans: A
9.) MOV CX, 7 is a sample of which type of addressing?

A. Indirect Addressing
B. Base Addressing
D. Immediate Addressing
Ans: D
10.) MOV AX, [BX+4] is a sample of which type of addressing?

B. Base Addressing
Ans: B
11.) MOV DL, [SI] is a sample of which type of addressing?

B. Base Addressing
D. Register Indirect Addressing
Ans: D
12.) Base registers, BX or BP, is used as a pointer to the desired memory location in this type of addressing.
B. Base Addressing
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
Ans: B
13.) This instruction pushes all registers to the stack.

A. PUSHD
B. PUSH
C. PUSHF
D. PUSHA
Ans: D
14.) MOVS is used to ___________

A. Move the signed value to the destination
B. Move the source to the destination
C. Copy the source to the destination
D. Copy the source of the string to the destination string.
Ans: D
15.) BSWAP swaps bytes in a ______

A. 16-bit general purpose register
B. 32-bit general purpose register
C. 16-byte general purpose register
D. 32-byte general purpose register
Ans: B
16.) It is an addressing mode in which the data operand is a part of the instruction itself.
A. Implied Mode
B. Immediate Mode
C. Direct Mode
D. Register Mode
Ans: B
17.) An example of indexed addressing mode
A. ADD AL, [DI+16]
B. MOV DX, [BX+04]
C. MOV AL, FFH
D. MOV CX, AX
Ans: A
18.) Based addressing mode example
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
A. MOV CX, AX
B. MOV DX, [BX+04]
C. MOV AL, FFH
D. MOV AX, [BX]
Ans: B
19.) An example of immediate addressing mode
A. MOV AL, FFH
B. MOV CX, AX
C. MOV DX, [BX+04]
D. MOV AX, [BX]
Ans: A
20.) An example of register addressing mode
A. MOV CX, AX
B. MOV AL, FFH
C. MOV DX, [BX+04]
D. MOV AX, [BX]
Ans: A
SET 6
1. What is the starting and ending address of the segment address 2345?
Solution:
Starting Address: 23450
Ending Address: 23450
+ FFFF
________
3344F – Answer
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
2. Find the memory address of the next instruction executed by the microprocessor, when operated in the real mode, for the
combination
CS= 2000H and IP = ABCDH
Solution:
20000
+ABCD
_____
2ABCDH – Answer
3. If the base pointer (BP) addresses memory, the ________ segment contains the data.
Ans: STACK
4. The PUSH and POP instructions always transfer a_______________-bit number between the stack and a register or memory
location in the 8086 microprocessors.
Ans: 16
5. ___________ transfers the source immediate byte or word of data into the destination register or memory location.
Ans: Immediate addressing mode
6. The addressing mode in which the effective address of the memory location is written directly in the instruction.
A. Implied Mode
B. Immediate Mode
C. Direct Mode
D. Register Mode
Ans: C
7. The addressing mode, in which the instructions has no source and destination operands is
a) register instructions
b) register specific instructions
c) direct addressing
d) indirect addressing
Ans: B
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
8. The data address of look-up table is found by adding the contents of
a) accumulator with that of program counter
b) accumulator with that of program counter or data pointer
c) data register with that of program counter or accumulator
d) data register with that of program counter or data pointer
Ans: B
9. The addressing mode which makes use of in-direction pointers is ______ .
a) Indirect addressing mode
b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode
Answer: A
10. _____ addressing mode is most suitable to change the normal sequence of execution of instructions.
a) Relative
b) Indirect
c) Index with Offset
d) Immediate
Ans: A
Quiz#4
Due Mar 25 at 11:59pm Points 144 Questions 48 Available Mar 24 at 11pm - Mar 25 at 12:30am about 2 hours Time Limit 90 Minutes
Attempt History
Attempt Time Score
LATEST Attempt 1 59 minutes 139 out of 144
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
Question 4 2 / 2 pts
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
This mnemonic instruction logically multiply the content of the count register and the data contained in the offset address DF45H. The instruction
accesses the stack segment. The result will be stored in the count register.
ADD CX, SS:[DF45]
OR CX, SS:[DF45]
INC SS:[DF45]
AND CX,SS:[DF45]
This mnemonic instruction jumps to a memory location labelled as CYREL without satisfying any condition.
JMP CYREL
JNZ CYREL
BRE CYREL
JUMP CYREL
This mnemonic instruction logically add the data stored 37 bytes after the location addressed by the base index register. The result will be saved
at the higher data register.
INC DH, [BX+37]
ADD DH, [BX+37]
OR DH. [DI+37]
OR DH, [BX37]
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
This mnemonic instruction subtracts the data addressed formed by the data index register from the lower data register.
SUB [DI], DL
SUB DI, [DL]
SUB [DL], DI
SUB DL, [DI]
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
AL=36
What is the final content of the accumulator after executing the instruction SHR AL, 5. Given AL= 1100 0110; C=1.
AL=36
AL=FE
AL=B1
AL=6E
What is the final content of the accumulator after executing the instruction SAR AL, 3. Given AL= 1100 0110; C=1.
AL=F1
AL=F8
AL=B8
AL=D8
Incorrect Question 14 0 / 5 pts
What is the final content of the accumulator after executing the instruction ROR AL, 3. Given AL= 1100 0110; C=1.
AL=D8
AL=F8
AL=B8
AL=C8
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
What is the final content of the accumulator after executing the instruction RCR AL, 5. Given AL= 1100 0110; C=1.
AL=36
AL=3E
AL=FE
AL=6E
What is the final content of the accumulator after executing the instruction ROL AL, 2. Given AL= 1100 0110; C=1.
AL=18
AL=31
AL=F1
AL=1B
From the given program, what is the handcode equivalent of line 1.

1. ACE: XOR DX,DX
2. MOV [DI+BP+29h], DX
3. SUB DX, [7654h]
4. SPADE: ADD DX, [SI+ADh]
5. DEC DX
6. JNZ SIMA
7. XOR AX, AX
8. MOV AX, DX
9. JMP PURI
10. HLT
33 C0
33 D2
32 C0
32 D2
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)

1. ACE: XOR DX,DX
3. SUB DX, [7654h]
5. DEC DX
6. JNZ SPADE
7. XOR AX, AX
8. MOV AX, DX
9. JMP ACE
10. HLT
8956
8953
8955
8952

1. ACE: XOR DX,DX
3. SUB DX, [7654h]
5. DEC DX
6. JNZ SPADE
7. XOR AX, AX
8. MOV AX, DX
9. JMP ACE
10. HLT
2BD 6
2B16
2B96
2B56
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
1. ACE: XOR DX,DX
3. SUB DX, [7654h]
5. DEC DX
6. JNZ SPADE
7. XOR AX, AX
8. MOV AX, DX
9. JMP ACE
10. HLT
03 D4
0354
0314
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
0394

1. ACE: XOR DX,DX
3. SUB DX, [7654h]
5. DEC DX
6. JNZ SPADE
7. XOR AX, AX
8. MOV AX, DX
9. JMP ACE
10. HLT
42
F1
F2
43
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
1. ACE: XOR DX,DX
3. SUB DX, [7654h]
5. DEC DX
6. JNZ SPADE
7. XOR AX, AX
8. MOV AX, DX
9. JMP ACE
10. HLT
75FA
75 F 7
75 FB
75 FF
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
1. ACE: XOR DX,DX
3. SUB DX, [7654h]
5. DEC DX
6. JNZ SPADE
7. XOR AX, AX
8. MOV AX, DX
9. JMP aCE
10. HLT
8 BD0
89 DC
8 BC2
89 C 2

1. ACE: XOR DX,DX
3. SUB DX, [7654h]
5. DEC DX
6. JNZ SPADE
7. XOR AX, AX
8. MOV AX, DX
9. JMP ACE
10. HLT
E9F0FF
E9F0
EBF0FF
EBF0
ACE: XOR DX,DX
1.
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
3. SUB DX, [7654h]
5. DEC DX
6. JNZ SPADE
7. XOR AX, AX
8. MOV AX, DX
9. JMP ACE
10. HLT
F1
F3
F2
F4
From the given program, what is the displacement in the instruction 9?

1. ACE: XOR DX,DX
3. SUB DX, [7654h]
5. DEC DX
6. JNZ SPADE
7. XOR AX, AX
8. MOV AX, DX
9. JMP ACE
10. HLT
FFF0
F0
F0FF
FF
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
From the given program, at what address does the instruction 3 is located?
1. ACE: XOR DX,DX
3. SUB DX, [7654h]
5. DEC DX
6. JNZ SPADE
7. XOR AX, AX
8. MOV AX, DX
9. JMP ACE
10. HLT
0006-0007
0005-0007
0005-0006
0004-0005
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
From the given program, at what address does instruction 6 is located?
1. ACE: XOR DX,DX
3. SUB DX, [7654h]
5. DEC DX
6. JNZ SPADE
7. XOR AX, AX
8. MOV AX, DX
9. JMP ACE
10. HLT
0009-000B
0008-0009
0008-000 A
0009-000 A
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
1. ACE: XOR DX,DX
3. SUB DX, [7654h]
5. DEC DX
6. JNZ SPADE
7. XOR AX, AX
8. MOV AX, DX
9. JMP ACE
10. HLT
0002-0004
0002-0003
0003-0004
0000-0003

1. ACE: XOR DX,DX
3. SUB DX, [7654h]
5. DEC DX
6. JNZ SPADE
7. XOR AX, AX
8. MOV AX, DX
9. JMP ACE
10. HLT
000 B-000C
000 D-000F
000 F- 0010
000 D-000E
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
1. ACE: XOR DX,DX
3. SUB DX, [7654h]
5. DEC DX
6. JNZ SPADE
7. XOR AX, AX
8. MOV AX, DX
9. JMP ACE
10. HLT
0009
000 A
0008
000 B

1. ACE: XOR DX,DX
3. SUB DX, [7654h]
5. DEC DX
6. JNZ SPADE
7. XOR AX, AX
8. MOV AX, DX
9. JMP PURI
10. HLT
0004-0006
0004-0005
0006-0007
0006-0008
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
From the given expression and program, determine the missing instruction (1) to accomplish the given task.
AC78 – 8E + (12 * B) + (D – 0128/4A) – (B0/16)
MOV AL, 12h
____________ (1)
MUL BL
PUSH AX
XOR AX, AX
____________ (2)
MOV BL, 4Ah
____________ (3) ;obtain the quotient
____________ (4) ;transfer the quotient to DL register
MOV AL, 0Dh
SUB AL,DL
____________ (5) ;clear the content of AH
ADD AX, AC78H
____________ (6) ;read the stored value from the stack to DX
ADD AX,DX
PUSH AX
XOR AX,AX
____________ (7)
MOV BL, 16h
DIV BL
____________ (8) ;add the quotient and 8Eh
____________ (9) ;copy the sum to BL
POP AX
MOV BH,0h
____________ (10) ;subtract the content of BX from AX
MOV, BL,0B
MOV AX, 0012
MOV BX, 000B
XOR BL, BL
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
AC78 – 8E + (12 * B) + (D – 0128/4A) – (B0/16)
MOV AL, 12h
____________ (1)
MUL BL
PUSH AX
XOR AX, AX
____________ (2)
MOV BL, 4Ah
MOV AL, 0Dh
SUB AL,DL
ADD AX, AC78H
ADD AX,DX
PUSH AX
XOR AX,AX
____________ (7)
MOV BL, 16h
DIV BL
____________ (9) ;copy the sum to BL
POP AX
MOV BH,0h
MOV AX, 000D
SUB AX, BX
MOV AX, 0128
XOR BX, BX
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
AC78 – 8E + (12 * B) + (D – 0128/4A) – (B0/16)
MOV AL, 12h

____________ (1)
MUL BL
PUSH AX
XOR AX, AX
____________ (2)
MOV BL, 4Ah

MOV AL, 0Dh
SUB AL,DL

ADD AX, AC78H

ADD AX,DX
PUSH AX
XOR AX,AX
____________ (7)
MOV BL, 16h
DIV BL
____________ (9) ;copy the sum to BL
POP AX
MOV BH,0h
____________ (10) ;subtract the content of BX from AX SUB

AX, BX
DIV BL
DIV AL
SUB AX, BL
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
AC78 – 8E + (12 * B) + (D – 0128/4A) – (B0/16)
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
AC78 – 8E + (12 * B) + (D – 0128/4A) – (B0/16)
MOV AL, 12h
____________ (1)
MUL BL
PUSH AX
XOR AX, AX
____________ (2)
MOV BL, 4Ah
MOV AL, 0Dh
SUB AL,DL
ADD AX, AC78H
ADD AX,DX
PUSH AX
XOR AX,AX
____________ (7)
MOV BL, 16h
DIV BL
____________ (9) ;copy the sum to BL
POP AX
MOV BH,0h
MOV AH, 00
MOV AL, 00
MOV AX, 0000
XOR AX, AX
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
AC78 – 8E + (12 * B) + (D – 0128/4A) – (B0/16)
MOV AL, 12h
____________ (1)
MUL BL
PUSH AX
XOR AX, AX
____________ (2)
MOV BL, 4Ah
MOV AL, 0Dh
SUB AL,DL
ADD AX, AC78H
ADD AX,DX
PUSH AX
XOR AX,AX
____________ (7)
MOV BL, 16h
DIV BL
____________ (9) ;copy the sum to BL
POP AX
MOV BH,0h
POP DX
POP DL
POP DH
PUSH DX
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
AC78 – 8E + (12 * B) + (D – 0128/4A) – (B0/16)
MOV AL, 12h
____________ (1)
MUL BL
PUSH AX
XOR AX, AX
____________ (2)
MOV BL, 4Ah
MOV AL, 0Dh
SUB AL,DL
ADD AX, AC78H
ADD AX,DX
PUSH AX
XOR AX,AX
____________ (7)
MOV BL, 16h
DIV BL
____________ (9) ;copy the sum to BL
POP AX
MOV BH,0h
MOV B0, AX
MOV AH, B0
MOV AL, B0
MOV AX, B0
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
AC78 – 8E + (12 * B) + (D – 0128/4A) – (B0/16)
MOV AL, 12h
____________ (1)
MUL BL
PUSH AX
XOR AX, AX
____________ (2)
MOV BL, 4Ah
MOV AL, 0Dh
SUB AL,DL
ADD AX, AC78H
ADD AX,DX
PUSH AX
XOR AX,AX
____________ (7)
MOV BL, 16h
DIV BL
____________ (9) ;copy the sum to BL
POP AX
MOV BH,0h
ADD AH, 8E
ADD AX, 008E
ADD AL, 8E
ADD AH,008E
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
AC78 – 8E + (12 * B) + (D – 0128/4A) – (B0/16)
MOV AL, 12h
____________ (1)
MUL BL
PUSH AX
XOR AX, AX
____________ (2)
MOV BL, 4Ah
MOV AL, 0Dh
SUB AL,DL
ADD AX, AC78H
ADD AX,DX
PUSH AX
XOR AX,AX
____________ (7)
MOV BL, 16h
DIV BL
____________ (9) ;copy the sum to BL
POP AX
MOV BH,0h
MOV AL, BL
MOV BL, AL
MOV BL, AH
MOV AH, BL
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
ter simulating the
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
ter simulating the
After determining the missing instructions to accomplish the given task, what will be the final content of the register BX af
whole program?
AC78 – 8E + (12 * B) + (D – 0128/4A) – (B0/16)
MOV AL, 12h
____________ (1)
MUL BL
PUSH AX
XOR AX, AX
____________ (2)
MOV BL, 4Ah
MOV AL, 0Dh
SUB AL,DL
ADD AX, AC78H
ADD AX,DX
PUSH AX
XOR AX,AX
____________ (7)
MOV BL, 16h
DIV BL
____________ (9) ;copy the sum to BL
POP AX
MOV BH,0h
0096
00 C6
004 A
0016
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
ter simulating the
After determining the missing instructions to accomplish the given task, what will be the final content of the register DX af
whole program?
AC78 – 8E + (12 * B) + (D – 0128/4A) – (B0/16)
MOV AL, 12h
____________ (1)
MUL BL
PUSH AX
XOR AX, AX
____________ (2)
MOV BL, 4Ah
MOV AL, 0Dh
SUB AL,DL
ADD AX, AC78H
ADD AX,DX
PUSH AX
XOR AX,AX
____________ (7)
MOV BL, 16h
DIV BL
____________ (9) ;copy the sum to BL
POP AX
MOV BH,0h
ACB1
00 C6
0004
AD47
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
ter simulating the
After determining the missing instructions to accomplish the given task, what will be the final content of the stack after si mulating the whole
program?
AC78 – 8E + (12 * B) + (D – 0128/4A) – (B0/16)
MOV AL, 12h
____________ (1)
MUL BL
PUSH AX
XOR AX, AX
____________ (2)
MOV BL, 4Ah
MOV AL, 0Dh
SUB AL,DL
ADD AX, AC78H
ADD AX,DX
PUSH AX
XOR AX,AX
____________ (7)
MOV BL, 16h
DIV BL
____________ (9) ;copy the sum to BL
POP AX
MOV BH,0h
zero
AD47
00 C6
none
Quiz
Score:
139
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
ter simulating the
out of
144
Tanqueco, Samantha Aeriel Y.

June 21, 2017
COE121/B2
Prof. Villamor
For Quiz 4:
Convert the Machine Language into MOV instructions.
1. 1 0 0 0 1 0 0 0 1 1 0 0 0 0 1 1
Answer: MOV BL, AL
Solution:
100010 – MOV 0 – Reg to R/M 0-
Byte 11 – R/M is also a reg 000 – AL
011-BL
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
ter simulating the
2.
1 0 0 0 1 0 1 1 0 0 0 0 0 1 1 1
0 0 0 1 0 0 0 0 1 0
0
0 0 0 0 0
0 0 1 1 0 1 0 0 0 0 0 1 0 0 1 0
Answer: MOV [BX], 1234H
Solution:
100010 – MOV 1 – R/M to reg 1- Word
00 – no disp. 000 – AX (not used) 111-BX+disp.
Reyes, Malvin Angelo C.

COE121/B2
QUIZ#4
1. Which is not an example of data movement instructions?

a. MOV b. MOVSX c. MOVZX d. MOVS
Answer: D
2. Which of the following are not string instructions?

a. LODS b. STOS c. INS d. LEA
Answer: D
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
ter simulating the
3. It is the native binary code that the microprocessor understands and uses as its
instructions to control its operation.
a. Machine Language b. Data Language c. Data Code d. Machine Code
Answer: A
4. The first 2 bytes of the 32-bit instruction mode format are called ______ because they
are not always present.
a. overall prefixes c. overhaul prefixes
b. override prefixes d. overwrite prefixes
Answer: B
5. The ______ selects the operation (addition, subtraction, move, and so on) that is
performed by the microprocessor.
a. Encoder c. Decoder
b. Segment Register d. Opcode
Answer: D
6. If the direction bit (D)=1, data flow to the register REG field from the R/M field located
in the second byte of an instruction.
a. from, to c. to, from
b. to, within d. None of the above
Answer: C
7. If the, the W-bit=0 data size is always a ____.

a. 4-bit c. word
b. doubleword d. byte
Answer: D
8. The MOV AL,[DI] instruction is an example that contains _____________.

a. No displacement c. 16-bit displacement
b. Extended displacement d. none of the above
Answer: A
9. The MOV AL,[DI+2] instruction is an example that uses _____________.

Answer: C
10. The MOV AL,[DI+1000H] instruction is an example that uses _____________.
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
ter simulating the

Answer: C
11. If the MOD field contains a 00, 01, or 10 and R/M Code is 111, the addressing mode is
____.
a. DS:[BX+SI] c. DS:[DI]
b. DS:[BX+DI] d. DS:[BX]
Answer: D
____.
Answer: A
____.
Answer: B
14. In 32-bit addressing modes selected by R/M, if the R/M code is 000 the function is
_____.
a. DS:[EAX] c. Uses scaled-index byte
b. DS:[EBX] d. DS:[EDI]
Answer: A
_____.
Answer: C
_____.
Answer: D
4/21/2015 Quiz4-COE121B2/Q320142015: COE121 B2 (Q320142015)
ter simulating the
17. The ________ directive indicates to the assembler that the instruction uses a word-sized
memory pointer
a. WORD PTR c. WORD PTR
b. BYTE PTR d. BYTE PTR
Answer: A
18. In Segment register selection, if the code is 000, the segment register is ______.
a. ES c. SS
b. CS d. GS
Answer: A
a. ES c. SS
b. CS d. GS
Answer: C
a. ES c. SS
b. CS d. GS
Answer: D

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COE121 Compilation

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Quiz#1

Tanqueco, Samantha Aeriel Y. May 15, 2017

COE121/B2 Prof. Villamor

1. Mapua shall be among the best universities in the _____.

3. The Institute shall provide state-of-the-art _____ of industries and communities.

4. How many core values MAPÚA emphasizes?

5. Which is a core value of MAPÚA?

7. Used when computing machines only perform simple arithmetic.

8. It is also considered as a Special Purpose Register.

10. Additional Data Segment used by some of the string instructions.

11. It is found at bit 0.

14. Instruction decoder interprets the address.

2. Which of the following is not an Intel engineer?

3. First Intel microprocessor invented is _____?

4. What does A in ASCII stands for?

d. Stays the same

6. What does ALU stands for?

a. Arithmetic Logic Unit

b. American Logic Unit

c. American Logical Unit

d. Arithmetic Logical Units

7. Robert Noyce and Gordon Moore are the founders of ______?

8. What does I in ENIAC stands for?

9. Transistors are ____ generation of microprocessors.

10. Intel is shortened word for _____?

d. Integrated and Electrical

1. by common practice, 8-bit binary numbers are referred to as ____ ?

A. Direct memory access (DMA)

B. Random access memory (RAM)

C. Read only memory (ROM)

D. None of the choices

3. It is a type of a flag register that indicates if result equals to zero.

A. Carry Flag (CF)

B. Zero Flag (ZF)

C. Sign Flag (SF)

D. Interrupt Flag (IF)

B. big endian; little endian

C. little indian; big indian

D. big indian; little indian

5. It is a type of flag register that provides single-step capability for debugging.

A. Trap Flag (TF)

B. Nested Task (NT)

C. Overflow Flag (OF)

D. Auxiliary Flag (AF)

6. It is a type of flag register that contains carry out of MSB of result.

A. Overflow Flag (OF)

B. Auxiliary Flag (AF)

C. Interrupt Flag (IF)

D. Carry Flag (CF)

7. 32-bit binary numbers are referred to as __________.

8. The first practical IC was developed in this year.

Initially CF=0; AF=0; ZF=0; IF=0

Assume that there is an interrupt.

A. CF=1; AF=1; ZF=1; IF=1;

B. CF=1; AF=1; ZF=0; IF=1;

C. CF=1; AF=0; ZF=0; IF=0;

D. CF=1; AF=1; ZF=0; IF=0

Initially CF=1; AF=1; ZF=1; IF=1

MOV AL, 1F MOV

A. CF=1; AF=1; ZF=1; IF=1;

B. CF=1; AF=1; ZF=0; IF=1;

C. CF=1; AF=0; ZF=0; IF=0;

D. CF=1; AF=1; ZF=0; IF=0

Initially CF=0; AF=0; ZF=0; IF=1