ch05 PDF

VLSI Design
Chapter 5
CMOS Circuit and Logic Design
Jin-Fu Li
Chapter 5 CMOS Circuit and Logic
Design
• CMOS Logic Gate Design

• Physical Design of Logic Gates
• CMOS Logic Structures
• Clocking Strategies
• I/O Structures
• Low-Power Design
National Central University EE613 VLSI Design 2

Logic Gate Design Issues
• Hierarchical design
− Architecture level
− RTL/logic gate level
− Circuit level
− Layout level
• Critical paths – the path with the longest delay

that require attention to timing details
• The number of Fanins and Fanouts affects the
performance of the circuits

Concept of Fanin and Fanout
• Fanin
− The fanin of any complex gate is defined as the number of
inputs of this gate
• Fanout
− The fanout of a complex gate is defined as the number of
driven inputs attached to the output of this gate
N N
Fanout=N Fanin=N

Logic Gate Design – NAND Gate
Rp
t dr = ( mnC d + C r + kC g )
n
• Rp = the effective resistance of p-device in a minimum-
sized inverter
• n = width multiplier for p-devices in this gate
• k = the fanout
• m = fanin of gate
• Cg = gate capacitance of a minimum-sized inverter
• Cd = source/drain capacitance of a minimum-sized
inverter
• Cr = routing capacitance
Logic Gate Design – Fanins and Fanouts
m=3, k=4
Cr
mnCd kCg

Logic Gate Design – NAND Gate Rise Time
Rp
t dr = ( mnC d + C r + kC g )
n
Rp
= ( mnrC g + q ( k ) C g + kC g )
n
R pC g
= ( mnr + q ( k ) + k )
n
R pC g R pC g
= R g C g mr + q (k ) + k
n n
Separate delay into internal delay and external delay caused by fanouts
t dr = tint − r + k × toutput − r
tint − r = R p C g mr
R pC g q(k )
toutput − r = (1 + )
n k
Logic Gate Design – NAND Gate Fall Time
Rn
t df = m ( mnrC g + q ( k ) C g + kC g )
n
RnC g q (k )
= R n C g m r + mk
2
(1 + )
n k
= t int − f + k × t output − f
We want the rise time to be equal to the fall time

t dr = t df
Rp Rn
( mnrC g + q ( k )C g + kC g ) = m ( mnrC g + q ( k )C g + kC g )
n n
R p = mR n
Hence we must design Wp = Wn , thus the delay time is
m
Rn
t df = t dr = ( m 2 nrC g + mq ( k )C g + mkC g )
n
Typical CMOS NAND & NOR Delays
Rn − nand
Assume : t f − nand = m (m × 4 × 0.005 + C L )
n=4 4
kC g = C L 4 × t f − nand
Rn − nand =
q(k ) = 0 m(0.02 × m + kC g )
rC g = Cd = 0.005 pf
A Delay (ns) Delay (ns)

B NR4-Rise
C 10.0 ns
D ND4-Fall 10.0 ns
ND4-Rise
A NR4-Fall
B
C
D 0.0 0.25 0.5 0.75 1.0 0.0 0.25 0.5 0.75 1.0
Capacitive load (pf) Capacitive load (pf)

Logic Gate Design – Gate Delays
NAND- and NOR-Gates Delays Measured with SPICE

GATE tinternal-f toutput-f tinternal-r toutput-r
(ns) (ns/pf) (ns) (ns/pf)
INV .08 1.7 .08 2.1

ND2 .2 3.1 .15 2.1
ND3 .41 4.4 .2 2.1
ND4 .68 5.7 .25 2.1
ND8 2.44 10.98 .38 2.2
NR2 .135 1.75 .25 4.1
NR3 .14 1.83 .52 6.2
NR4 .145 1.88 .9 8.2
NR8 .19 1.8 3.35 16.4

Logic Gate Design – Efficient Resistance
Efficient Resistance Value for a

Typical 1u CMOS Process
GATE Rn ( Ω) Rp ( Ω)
INV 7.1K 8.5K

ND2 6.3K 8.6K
ND3 6.0K 8.7K
ND4 5.9K 8.8K
NR2 7.3K 8.4K
NR3 7.4K 8.4K
NR4 7.5K 8.4K

Logic Gate Design – 8-Input AND Gate
A
CB
D
E Approach 1
F CL
G
H
A
B
C
D
E CL Approach 2
F
G
H
A
B
C
D
E Approach 3
F CL
G
H

Logic Gate Design – 8-Input AND Gate
Comparison of Approaches to Designing an 8-Input AND Gate

Approach Delay Delay Delay Delay Total Delay
Stage 1ns Stage 2ns Stage 3ns Stage 4ns (SPICE) ns
1 2.82 3.37 6.2

ND8->INV ND8 INV (6.5)
falling rising
2 .88 4.36 5.24

ND4->NR2 ND4 NR2 (5.26)
falling rising
3 .31 .4 .31 2.17 3.19

ND2->NR2 ND2 NR2 ND2 INV (3.46)
ND2->INV falling rising falling rising

Basic Physical Design
• Gates: Inverter, NAND, and NOR
• Complex Gates
• Standard Cells
• Gate Array
• Sea of Gates
• Layout Optimization
• Transmission Gates
• 2-Input Multiplexer

Physical Design – CMOS Inverter
Vdd
Vdd
a z a z
Vss
Vss

Physical Design – NAND Gate
Vdd
Vdd
z
a
z b
b
Vss
Vss

Physical Design – NOR Gate
Vdd Vdd
a
z z
b
Vss Vss
b a

Physical Design – Complex Gates
• All complex gates can be designed using a single
row of N-transistors and a single row of P-
transistors, aligned at common gate connections
• Design procedure
− Draw two dual graphs to P transistor tree and N
transistor tree
− Find all Euler paths that cover the graph
− Find a P and an N Euler path that have identical
labeling
− If not found, break the gate in the minimum
numbers of places to achieve step 3

VDD
C D
Z C D Vss
I1 I3
B
I1
I2
A
B
Z I2
C A B A
I3
D Z

D C D C
B B
A A
Vdd
Vss
A B C D
Physical Design – XNOR Gate (1)
A Z’
B Z
Vdd
A Z’
Z’ z
B
A B
Z’
Vss
A B
Physical Design – XNOR Gate (2)
A
B
Z
Vss Vdd

Physical Design – Automated Approach
A B C D E
Vdd
E A
D C B
E
Vss
D E C A B D E C A B
Vdd
Vss

Physical Design – Standard-Cell Approach
WVdd
Wp
Dnp
Wn
a b c d z
WVss

Physical Design – Standard-Cell Layout
Vdd Vdd
Vss Vss
a b c z a b c z

Physical Design – Gate Array Layout (1)
Vdd
Vss

Physical Design – Gate Array Layout (2)
Vdd
Gate array cells
Routing channels
Vss

Physical Design – Sea-of-Gate Layout
well contacts
Vdd supply
P-transistors
poly gates
N-transistors
Vss supply
substrate contacts
Physical Design – Sea-of-Gate (NAND3)
a b c
a b c z z
a b c

Physical Design – CMOS Layout Guidelines
• Run VDD and VSS in metal at the top and bottom of
the cell
• Run a vertical poly line for each gate input
• Order the poly gate signals to allow the maximal
connection between transistors via abutting
source-drain connection.
• Place n-gate segments close to VSS and p-gate
segments close to VDD
• Connection to complete the logic gate should be
made in poly, metal, or, where appropriate, in
diffusion
Physical Design – Improvement in Density
• Better use of routing layers – routes can occurs

over cells
• More “merged” source-drain connections
• More usage of “white” space in sparse gates
• Use of optimum device sizes – the use of smaller
devices leads to smaller layouts

Physical Design – Layout Optimization
Vdd
clk
F
A<0>
A<1> F
A<2>
A<3>
Vss
clk A<3> A<2> A<1> A<0>

Physical Design – Layout Optimization
2
A
B
C Z B C D
D
Vdd
Z Wrong
Right
Vss
A B C D A B C D
Physical Design – Transmission Gate

Physical Design – Transmission Gate

Physical Design – 2-Input Multiplexer
a
z b
-c a z
b
c -c

CMOS Logic – Pseudo-nMOS Logic
VDD
βp
F
A βn VL
Time
βn
β n (VDD − VTn )VOL = (VDD − | VTp |) 2
2
for VTn = −VTp = VT
βp
VOL = (VDD − VT )
2βn

CMOS Logic – Dynamic CMOS Logic
Z
N-logic
inputs evaluate
Block
precharge
clk
clk
clk
clk
A Y=ABC
C Z=(A+B).C
B
A B C
clk clk

clk=1
A
1 C A
B C1 C2 C1 C
1
C C2
0
charge sharing model
clk=1
CVDD = (C + C1 + C2 )VA
C
VA = VDD
C + C1 + C2
If for example C1 = C2 = 0.5C then this voltage would be VDD/2

clock
N1 N2
N1
inputs N Logic N Logic
T d1
Erroneous State
clock N2
T d2

CMOS Logic – Clocked CMOS Logic
-clk
clk Z

CMOS Logic – Pass-Transistor Logic
A
-A A
-B
-B
-A OUT OUT
A OUT
B
B B
Complementary Single-polarity Cross-coupled

CMOS Logic – CMOS Domino Logic
Basic gate
A Z
clk

weak p device
Z Z
inputs N-logic inputs N-logic

Block Block
clk clk
Static version Latched version

clk
clk
N-logic
A5 C2 C1
A4 C3
N-logic N-logic
A3 C4
A2 C5
A1 C6 N-logic
A0 C7

CMOS Logic – NP Domino Logic
clk -clk clk
to futher P blocks
inputs N-logic P-logic N-logic
stable
during
clk=1
other P blocks other N blocks
other N blocks other P blocks
clk -clk clk
to futher P blocks
inputs N-logic P-logic N-logic
stable
during
clk=1
other P blocks other N blocks

CMOS Logic–Advantages of Dynamic Logic
• Smaller area than fully static gates

• Smaller parasitic capacitance, hence higher speed
• Glitch free operation if designed carefully

CMOS Logic – CVSL
Q F
-F
-Q
nMOS d a -d -e
Differential
Inputs Combinational -a
Network e b c -b
-c
Basic version A particular function

CMOS Logic – CVSL
(abcd)=(0000)
-Q clock Q
clock -d d -d d
-Q Q
nMOS c -c c -c
Differential
Inputs Combinational
Network
b -b b -b
clock
a -a
clock
Clocked version A 4-way XOR gate

Clocking Strategies – Clocked Systems
inputs outputs
Combinational Logic
current
state next
bits state
Q D bits
Q D
Q D
clock
A simple finite state machine

Clocking Strategies – Clocked Systems
10 ns 10 ns
inputs C1 C2 outputs
D Q D Q D Q
D Q D Q D Q
C1 C2 outputs
inputs
D Q D Q D Q
A pipeline system

Clocking Strategies – Latches and Reg.
Cycle time Tc
clock
Setup Time (Ts)
Data
Hold Time (Th)
Clock-to-Q Delay (Tq)

Clocking Strategies – Latches
D 0 clk
Q
1 D
S
clk
Q
0 clk
Q
D 1 D
S
clk
Q

Clocking Strategies – Registers
clk
D 0 0
QM D
Q
1 1
S S QM
clk clk
Q
master slave

clk=0
clk=1
master slave

clk clk

Clocking Strategies – JK Registers
K
J
A
D
K
J B
clk Q
QN
Q
QN
clk -clk
J=K=0; Q=D
JN=KN=1; A=QN, B=1; D=AN=Q J K clk Q QN
J=0;K=1
0 0 Q QN
KN=0,JN=1; A=1, B=1; D=0 0 1 0 1
J=1; K=0 1 0 1 0
KN=1, JN=0; A=QN, B=Q; D=1; 1 1 QN Q
J=1; K=1
KN=0, JN=0; A=1, B=Q; D=QN
Clocking Strategies – System Timing
Reg. Tq Combinational Logic Ts Reg.

A Td B
clock
Latch Tq Combinational Logic Ts Latch

A Td B
clock
A B
Latch Combinational Logic Ts Latch Combinational Logic Latch
A Tq Tda B Tdb C
clock

Clocking Strategies – System Timing
Tda < Tc1 − Tqa − Tsb

Tqa : the clock-to-Q time of latch A
Tsb : the setup time of latch B
Similarly,
Tdb < Tc 0 − Tqb − Tsc
Finally,
Tc = Tda + Tdb + 2[Tq + Ts ]

Clocking Strategies – Setup & Hold Time
Td
Din Pad D Q
Tφ
φin Pad
φ
φin
t = t− t = t+
Din
For an ideal DFF,

= t − , then Q should be high
If Din is high when t
If Din becomes to low when t = t + , then Q still is high

Tφ Tφ
φ
Td
Td
D
When Td > Tφ , Din should become high earlier and Q can become high
When Td < Tφ , Din should retain at high longer and Q can be still at high
Tφ
Din TS Tφ Din
Th Td
D Td D
TS = Td − Tφ Th = Td − Tφ

Td2
D Q D Q
q1 d2
Logic
Tdq Tdl 1. When Tdc>Tdq+Tdl, M2 latches
M1 Tdc M2
the New data
clk delay delay
T c1 T c2 2. When Tdq+Tdl-Tdc>TC , M2
latches Old data twice
Therefore, 0<Tdq+Tdl-Tdc<TC
clk
T c1
Td2 Old data New data

New Data
TC
T c2 Tdc

Clocking Strategies – D Register
-clk
clk clk -clk clk
D -Q
-clk clk -clk
Q
clk -clk
D -clk clk Q
-clk clk
clk -clk

Clocking Strategies – Clock Skew
-clk
clk
Feedthrough condition
D Q
clk-in clk clk

Buffers Necessary for
Large Loads
-clk -clk

Clocking Strategies–Skew Clock Pipeline
CL1 CL2 CL3

FF
FF
FF
FF
(5ns) (9ns) (5ns)
clk1 clk2 clk3
-2ns
-2ns
0ns
clk
A 7ns B C D
clk
A B C D
clk1
A B C D
clk2
A B C
clk3
-clk
D Q
clk
1. Low area cost

2. Driving capability of D must override the feedback inverter
clk
D Q
-clk
-clk
clk
Vdd
clk
D -clk Q
D -clk
Q
clk
clk -clk
Vss

Clocking Strategies – DETDFF
clk
D -D
clk
Q1
Q1 -Q1
clk
Latch 1

clk
Q2 -Q2
clk
Q2
D -D
clk
Latch 2

Latch 2
D Q2
-Q2 Q
-Q
-Q1
Q1
clk
Latch 1
clk Latch 1 enabled Latch 2 enabled

Q2=-Q2=low Q1=-Q1=high

Clocking Strategies – Register
Asynchronously resettable register
-clk -reset
clk -clk -clk clk
-clk clk -clk
clk
-reset

Clocking Strategies – Register
Asynchronously settable and resettable register
-clk -reset
clk -clk clk

-clk
-clk
clk -clk
-set

Clocking Strategies – Dynamic Registers
Dynamic single clock latches
clk clk
clk
D -Q D D
-clk
-clk -clk
Dynamic single clock registers
clk -clk
-Q clk -clk
D Q D Q
-clk clk
-clk clk

Clocking Strategies – Single Clock
clock
Logic
L1 L2
Logic
L2 opaque
clock L1 opaque L1 transparent
L2 transparent

Dynamic Latches – Single-Phase Clocking
Clock active high latch Clock active high latch with buffer
D X D X
CLK Q CLK -Q
Dn CLK Xn Qn
0 H 1 0
1 H 0 1
1 L Xn-1 Qn-1
0 L 1 Qn-1

Clock active low latch Clock active low latch with buffer
D D
CLK CLK
X Q X -Q
Dn CLK Xn Qn
0 L 1 0
1 L 0 1
1 H Xn-1 Qn-1
0 H 1 Qn-1

Clock active high latch without Clock active low latch without
feedback feedback
D X D
CLK Q CLK
X Q
Assume that the capacitance of node X

is 0.002pF and the leakage current I is
1nA.
Therefore, T=CV/I=0.002pFx5V/1nA=100us.
That is, the latch needs to be refreshed each 100us.
Otherwise, the output Q will become high.

Dynamic Registers – TSPC
Positive edge trigger register
CLK
D
B -Q
CLK
D A
A
B
-Q
tr
tf
The value of the hold time of this flip flop is

close to zero.

Phase Locked Loop Clock Techniques
• PLL for synchronization
clock clock
chip clock pad chip PLL clock pad
clock route clock route
dclk dclk
output pad output pad
dclk+dpad dclk+dpad
clock clock
T1 T1=Input buffer delay
dclk +routing RC delay dclk
T2 T2
T2=Clock-to-Q delay
data out +output buffer delay data out

Phase Locked Loop – Clock Multiplying
Clock-multiplying PLL Synchronize data transfer between chips
clock
chip PLL clock pad
clock clock
/4 clock route
PLL PLL
bus
dclk system clock

output pad
dclk+dpad Synchronize the output enable signals
1. Reduce tristate fights
clock 2. Improve overall timing
dclk

Typical Phase Locked Loop
Programmable
Frequency divider
(/n)
U
Phase Detector Charge Pump Filter VCO
Vc nxfn
reference clock fn D
Vdd
U Low-pass filter
Vc
D

Phase Locked Loop – Phase Detector
S Q U
clkext
R
S Q D
clk
R
S clk clk
Q
UP NOP DN
clkext clkext
R

Phase Locked Loop – Charge Pump
• Charge pump circuits
Vrefp Pref
U
U
Out
Out
D
D
Vrefn Nref
Biased by current mirror

The output current of the charge pump
can be adjusted through the control of
the current mirror.

Phase Locked Loop – Low-Pass Filter
• Simple implementation of low-pass filter
In Out
TG
NC1 NC2
• The two capacitors C1 and C2 are in the order of tens of pF

• The capacitor C2 is added in parallel to the simple RC low-
pass filter to form a second order filter
− The stability of the system is maintained even with the
process variation of these on-chip components
• Note that these capacitors can occupy a large portion of
the PLL

Phase Locked Loop – VCO
Current-starved inverter type VCO
Delay cell
I I
I
fVCO
V
Control voltage
V-I converter Odd number of stages
Voltage-Controlled Delay Line (VCDL) type VCO
tin tin+t
Control voltage

Phase Locked Loop
U Low-pass filter
Phase Detector VCO

Vc fout
fin D
fout
fin

Phase Locked Loop – Programmable VCO
Shift register
V-I converter
Delay cell
Delay cell
Delay cell
VC
Generated clock

Single-Phase Logic – NP Domino Logic
• NP-Domino Logic
− Allow pipelined system architecture
clk -clk
-clk
nMOS pMOS
Logic Logic clk
The circuit performs precharge-discharge operation when clock is low,

and all stage evaluate output levels when the clock is high.
clk section

Single-Phase Logic – NP-Domino Logic
• -clk section
-clk clk
clk
nMOS pMOS
Logic Logic -clk
The circuit performs precharge-discharge operation when clock is high,

and all stage evaluate output levels when the clock is low.

Single-Phase Logic – NP-Domino Logic
• A pipelined NP-Domino CMOS system
clk A -clk B clk C

section section section
clk
A a0 a1 a2
B b0 b1 b2
C c0 b1 b2

Single-Phase Logic – Clock Skew
• Uses of clock skew to extend clock cycle (not
recommended)
Td2
Logic
clock delay Tc1
clock
Tc1
Td2 old data new data
Td2 < Tc1

Single-Phase Logic – Avoiding Clock Skew
• Lock-up Latch
Lock-up latch
Logic
clock delay
• Contra-data-direction clock
Logic
delay clock

Two-Phase Clocking
• Dynamic register
-ph1 -ph2
D Q
ph1 ph2
ph1
ph2
ph1=1,ph2=0
C1 C2
ph1=0,ph2=1
C1 C2

Two-Phase Clocking
• Failure due to clock skew
ph1
ph2
ph1=1,ph2=1
C1 C2

Two-Phase Clocking
• Two-phase registers with single-polarity clocks
ph1 ph2
ph1 ph2

Clock Distribution
• In a large CMOS chip, clock distribution is a serious
problem
− Vdd=5V
− Creg=2000pF (20K register bits @ 0.1pF)
− Tclk=10ns
− Trise/fall=1ns
− Ipeak=Cdv/dt=(2000px5)/1n=10A
− Pd=CVdd2f=2000px25x100=5W
• Methods for reducing the values of Ipeak and Pd
− Reduce C
− Interleaving the rise/fall time

Clock Distribution
• Clocking is a floorplanning problem because clock delay
varies with position on the chip
• Ways to improve clock distribution
− Physical design
∗ Make clock delays more even
∗ At least more predictable
− Circuit design
∗ Minimizing delays using several stages of drivers
• Two most common types of physical clocking networks

− H tree
− Balanced tree

Clocking Distribution – H Tree
clock

Clocking Distribution – Balanced Tree
clock

Clocking Distribution – Reducing Power
• Techniques used to reduce the high dynamic

power dissipation
− Use a low capacitance clock routing line such as
metal3. This layer of metal can be, for example,
dedicated to clock distribution only
− Using low-swing drivers at the top level of the tree
or in intermediate levels

Clocking Distribution – Half-Swing Driver
Vdd
C1 C2
clkp -clkp CA
Vout
clkn -clkn
CB
C3 C4
Gnd
Clock

I/O Structures – Pads
• Types of pads
− Vdd, Vss pad
− Input pad (ESD)
− Output pad (driver)
− I/O pad (ESD+driver)
• All pads need guard ring for latch-up protection
• Core-limited pad & pad-limited pad
Core-limited pad Pad-limited pad
PAD PAD
I/O circuitry I/O circuitry

Input Pads – ESD Protection
Input pad without ESD protection
Assume I=10uA, Cg=0.03pF, and t=1us
PAD The voltage that appears on the gate is about 330volts
Input pad with ESD protection
PAD

I/O Pads – Tristate & Bidirectional Pads
Tristate pad
output-enable OE
P OE D N P OUT
OUT 0 X 0 1 Z
PAD 1 0 1 1 0
1 1 0 0 1
N
data D
Bidirectional pad
PAD

Input Pads – Schmitt Trigger Circuit
Transfer characteristic of Schmitt trigger
Vout
VDD
Vin
VT- VT+ VDD
1. Hysteresis voltage VH=VT+-VT-

2. When the input is rising, it switches when Vin=VT+
3. When the input is falling, it switches when Vin=VT-

Voltage waveforms for slow input
Vout
VDD Vin
VT+
VT-
Time
Schmitt trigger turns a signal with a very slow transition into a signal with a sharp
transition

A CMOS version of the Schmitt trigger
VDD
P1
VFP P3
P2
Vin Vout
N2
VFN N3
N1
1. When the input is rising, the VGS of the transistor N2 is given by VGS 2 = Vin − VFN
2. When Vin = VT + , N2 enters in conduction mode which means VGS2 = VTn
3. Then VFN = VT + − VTn

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VLSI Design

CMOS Circuit and Logic Design

• CMOS Logic Gate Design

National Central University EE613 VLSI Design 2

• Critical paths – the path with the longest delay

National Central University EE613 VLSI Design 3

National Central University EE613 VLSI Design 4

National Central University EE613 VLSI Design 6

We want the rise time to be equal to the fall time

A Delay (ns) Delay (ns)

National Central University EE613 VLSI Design 9

NAND- and NOR-Gates Delays Measured with SPICE

INV .08 1.7 .08 2.1

National Central University EE613 VLSI Design 10

Efficient Resistance Value for a

INV 7.1K 8.5K

National Central University EE613 VLSI Design 11

National Central University EE613 VLSI Design 12

Comparison of Approaches to Designing an 8-Input AND Gate

1 2.82 3.37 6.2

2 .88 4.36 5.24

3 .31 .4 .31 2.17 3.19

National Central University EE613 VLSI Design 13

National Central University EE613 VLSI Design 14

National Central University EE613 VLSI Design 15

National Central University EE613 VLSI Design 16

National Central University EE613 VLSI Design 17

National Central University EE613 VLSI Design 18

National Central University EE613 VLSI Design 19

National Central University EE613 VLSI Design 22

National Central University EE613 VLSI Design 23

National Central University EE613 VLSI Design 24

National Central University EE613 VLSI Design 25

National Central University EE613 VLSI Design 26

Gate array cells

National Central University EE613 VLSI Design 27

National Central University EE613 VLSI Design 29

• Better use of routing layers – routes can occurs

National Central University EE613 VLSI Design 31

clk A<3> A<2> A<1> A<0>

National Central University EE613 VLSI Design 32

National Central University EE613 VLSI Design 34

National Central University EE613 VLSI Design 35

National Central University EE613 VLSI Design 36

National Central University EE613 VLSI Design 37

National Central University EE613 VLSI Design 38

If for example C1 = C2 = 0.5C then this voltage would be VDD/2

National Central University EE613 VLSI Design 39

National Central University EE613 VLSI Design 40

National Central University EE613 VLSI Design 41

Complementary Single-polarity Cross-coupled

National Central University EE613 VLSI Design 42

National Central University EE613 VLSI Design 43

inputs N-logic inputs N-logic

Static version Latched version

National Central University EE613 VLSI Design 44

National Central University EE613 VLSI Design 45

other P blocks other N blocks

other N blocks other P blocks

clk -clk clk

other P blocks other N blocks

National Central University EE613 VLSI Design 46

• Smaller area than fully static gates