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RLC Circuit Analysis and Damping Types

This document compares and contrasts series and parallel RLC circuits in three sentences or less: Series RLC circuits experience current that decays exponentially over time, while parallel RLC circuits experience an exponentially decaying voltage over time. The damping factor determines whether the circuit response is overdamped, critically damped, or underdamped, affecting the shape of the exponential decay. Key differences between series and parallel circuits include whether the initial condition is of current or voltage and whether the source is present or absent.

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Brijendra Singh
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0% found this document useful (0 votes)
102 views1 page

RLC Circuit Analysis and Damping Types

This document compares and contrasts series and parallel RLC circuits in three sentences or less: Series RLC circuits experience current that decays exponentially over time, while parallel RLC circuits experience an exponentially decaying voltage over time. The damping factor determines whether the circuit response is overdamped, critically damped, or underdamped, affecting the shape of the exponential decay. Key differences between series and parallel circuits include whether the initial condition is of current or voltage and whether the source is present or absent.

Uploaded by

Brijendra Singh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

SERIES RLC PARALLEL RLC

CURRENT; NO PRIOR VOLTAGE; SOURCE-FREE VOLTAGE; SOURCE-FREE VOLTAGE; RAMP


CASE CHARGE ON CAPACITOR CAPACITOR PRECHARGED CAPACITOR PRECHARGED CURRENT INJECTION

CIRCUIT R L C R L C

i I.t R L C
V R L VO C
VO

BOUNDARY CONDITIONS di(0 + ) dv (0 ) dv (0 ) V dv (0 )


i(0) = 0 =VL v( 0) = Vo =0 v(0) = Vo =− o v (0 ) = 0 =0
dt dt dt RC dt

BASIC EQUATION d2i R di 1 d2 v R dv 1 d2 v 1 dv 1 d2 v 1 dv 1 I


+ ⋅ + i=0 + + v=0 + + v=0 + + v=
2 L dt LC 2 L dt LC 2 RC dt LC 2 RC dt LC C
dt dt dt dt

DAMPING FACTOR R L R L Rc L Rc L
ds = Rc = 2 = 2Z ds = Rc = 2 = 2Z dp = R c = 0.5 = 0.5Z dp = R c = 0.5 = 0.5Z
Rc C Rc C R C R C

OVERDAMPED ds > 1 R > Rc ds > 1 R > Rc dp > 1 R < Rc dp > 1 R < Rc


V
i(t ) =
− ds t g
⋅e sinh d2s − 1 ⋅ t g − dst g 
v (t ) = e cosh d2 − 1 ⋅ t
− dp t g 
v (t ) = e v (t ) = 1 − e p g  cosh dp2 − 1 ⋅ t g
2 −d t
Z d2s −1 cosh d s − 1 ⋅ t g  p g
 
ds dp
+ sinh d 2s − 1 ⋅ t g  − sinh dp2 − 1 ⋅ t g  +
dp 
sinh dp2 − 1 ⋅ t g 
2
ds − 1   
dp2 − 1 dp2 −1

CRITICALLY DAMPED ds = 1 R = Rc ds = 1 R = Rc dp = 1 R = Rc dp = 1 R = Rc

i(t ) =
V −t
⋅ tg ⋅ e g
−t
(
v (t ) = e g 1 + t g ) −t
(
v (t ) = e g 1 − t g ) −t
(
v (t ) = 1 − e g 1 + t g )
Z

UNDERDAMPED ds < 1 R < Rc ds < 1 R < Rc dp < 1 R > Rc dp < 1 R > Rc


V
i(t ) =
− ds t g
v (t ) = e s g cos 1 − d2s ⋅ t g
⋅e sin 1 − d2s ⋅ t g −d t − dp t g cos 1 − d2 ⋅ t 
v (t ) = e v (t ) = 1 − e p g  cos 1 − dp2 ⋅ t g
−d t
Z 1− d2s   p g


ds
sin 1 − d2s ⋅ t g 
dp dp
+ − sin 1 − dp2 ⋅ t g  +

sin 1 − dp2 ⋅ t g 
1 − d2s  
2
1 − dp 1 − dp2 

USE FOR INRUSH SINGLE + BACK-TO-BACK TRVs FOR INDUCTIVE LOAD CIRCUITS; VARIATION OF SERIES PRECHARGED TRVs FOR TERMINAL FAULTS
CAPACITOR BANKS; RESTRIKE + RESTRIKING INDUCTIVE + CAPACITOR CASE
REIGNITION CURRENTS REACTIVE CAPACITIVE LOAD CIRCUITS
LOAD CIRCUITS

Note: t g is generic time given by t g = t LC where t is real time.

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