EE5311 ASSIGNMENT 3 (GROUP 14)

1.Schematic and Layout of FA circuit

2. DRC and LVS clean

3.Functionality
NOTE- According to the question give we have given input before the invertors as A1,Cin1.
 4. Sin vs. Cslew

Here we have taken A1 as an square waveform and B as ground(given in

the diagram),Cin1 as 0,and plotted the graph of A vs. A1 and measured the Input slew for
A.

5.Output delay of Sum vs. Sin and Cload

Keeping Cload Constant and Varying Cslew,we have given A1 as square pulse,B
ground,Cin1 as 0,and measure the delay for O/p S.
Keeping Cslew Constant and Cload Varying, we have given A1 as square pulse,B
ground,Cin1 as 0,and measure the delay for O/p S.

6. O/P Delay Of Cout by varying Cload & Cslew

Cslew constant and cload varying. ,we have given Cin1 as square pulse,B
ground,A1 as 0 and measure the delay of output Cout.
Cload constant and cslew varying, we have given Cin1 as square pulse,B
ground,A1 as 0 and measure the delay of output Cout.

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