NANOELECTRONICS –BOTTOM UP APPROACHES

CHAPTER 1

1.1 INTRODUCTION[1]
Nanoelectronic is concerned with understanding and exploiting the properties of devices, which
have dimensions at the nanometre scale.

Microelectronics will gradually evolve into nano-electronic. In fact, this has already happened as
can be seen from the smallest feature size of present integrated circuits, which is below of one
micrometer. It is currently believed that optical lithography can be used for ground rules down to
150 nm and might even be used for the 100 nm generation and below. This would imply an
increasing process and mask complexity, and consequently, increasing the cost.

Molecular-scale electronic has been widely touted as "the next step" in electronic
miniaturization, with theory and research suggesting that single molecules may have the
capability to take the place of today's much larger electronic components.

what are the advantages of scaling down of devices?

Speed of operation - Reduction of the parasitic capacitances associated with non-conductive

paths in an electronic device leads to a higher cut-off frequency. This enables a device to operate
at much higher speeds. Density - An obvious advantage. This reduces size and cuts materials
cost. Power dissipation - This is reduced due to lesser resistance in interconnects and currents
flowing in smaller circuits. In lasers, the use of lower dimensional systems reduces the threshold
current due to improved density of states distribution. New applications - This enables certain
uses, currently speculative, but very much in the offing.

Integrated circuits are also known as microelectronic. The term micro derives from micro-
fabrication technology, which embraces all highly sophisticated techniques like optical- and
electron-beam lithography, metallization, implantation and etching that allow generating
structures on the scale of one micrometer.

In the early 1970's, two scientists, Ari Aviram and Mark Ratner, began to envision electronic
circuit elements made from single molecules and described in detail how they might function.

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This was the origin of the field of molecular electronics, now sometimes called molecular-scale
electronics.

The emergence of molecular electronics and spintronics is providing a challenge to traditional

electronic manufacturing techniques. Significant reduction in size and the sheer enormity of
numbers in manufacturing are the benefits of molecular electronics. Scientists predict that
computers will be assembled using molecules in the future, pushing technology far beyond the
limits of silicon.

1.2 WHAT IS NANOELECTRONICS[1]

Nanoelectronics refers to the use of nano technology on electronic components,

especially transistors.Although the term nanotechnology is generally defined as utilizing
technology less than 100 nm in size, nanoelectronics often refer to transistor devices that are so
small that inter-atomic interactions and quantum mechanical properties need to be studied
extensively. As a result, present transistors do not fall under this category, even though these
devices are manufactured with 45 nm, 32 nm, or 22 nm technology.

Nanoelectronics are sometimes considered as disruptive technology because present candidates

are significantly different from traditional transistors. Some of these candidates include: hybrid
molecular/semiconductor electronics,one dimensional nanotubes/nanowires, or
advanced molecular electronics.

1.3 WHY NANO[1]

The term Nano is occupying a remarkable place in modern technology. But, I believe
many of us are wondering what Nano can really do for us. The aim of this blog is to give an
overview about the nanotechnology to students, academic heads aiming to start nanotechnology
course in their institutes, and industrialists willing to know the potentiality of nanotechnology to
influence their industry.

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The basic element of most of the electronic devices has been the transistor which replaced
previously existing vacuum tubes, since its invention in 1947 by John Bardeen and Walter
Brattain at AT&T's Bell Labs in the United States. A Nobel Laureaute of Physics for the year
1965, "Richard Fenyman" has emphasized the potential of nanotechnology with his famous
quote "There's Plenty of Room at the Bottom" made in 1959. In 1965, Gordon E. Moore, co-
founder of Intel predicted that the number of components on the integrated circuit doubles every
two years for at least 10 years from then. This trend is called Moore's law has been valid even
now and is expected to continue for a couple of more years.

1.4 APPROACHES IN NANOELECTRONICS[1]

1.4.1 BOTTOM UP

Fig 1. Nanoelectronics bottom up

Electronics obtained through the bottom-up approach of molecular-level control of

material composition and structure may lead to devices and fabrication strategies not possible
with top-down methods. This review presents a brief summary of bottom-up and hybrid bottom-
up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar
motif.

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First, we will discuss representative electromechanical and resistance-change memory

devices based on carbon nanotube and core–shell nanowire structures, respectively. These device
structures show robust switching, promising performance metrics and the potential for terabit-
scale density.

Second, we will review architectures being developed for circuit-level integration, hybrid
crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key
concepts such lithography-independent, chemically coded stochastic demultipluxers. Finally,
bottom-up fabrication approaches, including the opportunity for assembly of three-dimensional,
vertically integrated multifunctional circuits, will be critically discussed.

1.4.2 TOP DOWN[1]

The most common top-down approach to fabrication involves lithographic patterning

techniques using short-wavelength optical sources. A key advantage of the top-down approach—
as developed in the fabrication of integrated circuits—is that the parts are both patterned and
built in place, so that no assembly step is needed. Optical lithography is a relatively mature field
because of the high degree of refinement in microelectronic chip manufacturing, with current
short-wavelength optical lithography techniques reaching dimensions just below 100 nanometres
(the traditional threshold definition of the nanoscale).

Shorter-wavelength sources, such as extreme ultraviolet and X-ray, are being developed
to allow lithographic printing techniques to reach dimensions from 10 to 100 nanometres.
Scanning beam techniques such as electron-beam lithography provide patterns down to about 20
nanometres. Here the pattern is written by sweeping a finely focused electron beam across the
surface. Focused ion beams are also used for direct processing and patterning of wafers, although
with somewhat less resolution than in electron-beam lithography. Still-smaller features are
obtained by using scanning probes to deposit or remove thin layers.

Mechanical printing techniques—nanoscale imprinting, stamping, and molding—have

been extended to the surprisingly small dimensions of about 20 to 40 nanometres. The details of
these techniques vary, but they are all based on making a master “stamp” by a high-resolution
technique such as electron-beam lithography and then applying this stamp, or subsequent

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generations of it, to a surface to create the pattern. In one variation a stamp’s surface is coated
with a very thin layer of material (the “ink”) that can then be deposited (“inked”) directly onto
the surface to reproduce the stamp’s pattern. For example, the controlled patterning of a
molecular monolayer on a surface can be achieved by stamping an ink of thiol functionalized
organic molecules directly onto a gold-coated surface (molecules that contain a sulfur end group,
called a thiol, bond strongly to gold).

In another approach the stamp is used mechanically to press the pattern into a thin layer
of material. This surface layer is typically a polymeric material that has been made pliable for the
molding process by being heated during the stamping procedure. Plasma etching can then be
used to remove the thin layer of the masking material under the stamped regions; any residual
polymer is thus removed, and a nanoscale lithographic pattern is left on the surface. Still another
variation is to make the relief pattern out of photoresist on a silicon wafer by optical or electron-
beam lithography and then pour a liquid precursor—for example, polydimethylsiloxane, a form
of silicone—over the pattern and then cure it. The result is a rubbery solid that can be peeled off
and used as a stamp.

These stamps can be inked and printed as described above, or they can be pressed to the
surface and a liquid polymer allowed to flow into the raised regions of the mask by capillary
action and cured in place. A distinction for this latter approach is that the stamp is flexible and
can thus be used to print nanoscale features on curved surfaces.

These nanoscale printing techniques offer several advantages beyond the ability to use a
wider variety of materials with curved surfaces. In particular, such approaches can be carried out
in ordinary laboratories with far-less-expensive equipment than that needed for conventional
submicron lithography. The challenge for all top-down techniques is that, while they work well
at the microscale (at millionths of a metre), it becomes increasingly difficult to apply them at
nanoscale dimensions.

A second disadvantage is that they involve planar techniques, which means that
structures are created by the addition and subtraction of patterned layers (deposition and
etching), so arbitrary three-dimensional objects are difficult to construct.

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CHAPTER 2[2]

2.1 BOTTOM DEVICES / CORE DEVICES IN NANO ELECTRONICS

2.1.1 CARBON NANOTUBES (CNTS):

Fig 2. Carbon Nanotubes

Carbon Nanotubes (Cnts) are allotropes of carbon with a cylindrical nanostructure. Nanotubes
have been constructed with length-to-diameter ratio of up to 132,000,000:1,[1] significantly larger
than for any other material. These cylindrical carbon molecules have unusual properties, which
are valuable for nanotechnology, electronics, optics and other fields of materials science and
technology. In particular, owing to their extraordinary thermal conductivity and mechanical
and electrical properties, carbon nanotubes find applications as additives to various structural
materials

2.1.2 ELECTRICAL PROPERTIES

Fig 3. CNT Electrical properties

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Band structures computed using tight binding approximation for CNT (zigzag, metallic) CNT
(semiconducting) and CNT (armchair, metallic).

Because of the symmetry and unique electronic structure of graphene, the structure of a
nanotube strongly affects its electrical properties. For a given (n,m) nanotube, if n = m, the
nanotube is metallic; if n − m is a multiple of 3, then the nanotube is semiconducting with a very
small band gap, otherwise the nanotube is a moderate semiconductor. Thus all armchair (n = m)
nanotubes are metallic, and nanotubes etc. are semiconducting.

However, this rule has exceptions, because curvature effects in small diameter carbon
nanotubes can strongly influence electrical properties. Thus, SWCNT that should be
semiconducting in fact is metallic according to the calculations. Likewise, vice versa—zigzag
and chiral SWCNTs with small diameters that should be metallic have finite gap (armchair
nanotubes remain metallic). In theory, metallic nanotubes can carry an electric current density of
4 × 109 A/cm2, which is more than 1,000 times greater than those of metals such
as copper, where for copper interconnects current densities are limited by electromigration.

2.1.3 FABRICATION OF CARBON NANOTUBES

FABRICATION
The most common method used to fabricate carbon nanotubes is electric-arc discharge.
An electric arc is an electrical breakdown of a gas which produces an ongoing plasma discharge,
similar to the instant spark, resulting from a current flowing through normally nonconductive
material such as air. The arc occurs in the gas-filled space between two conductive electrodes
(often made of carbon) and it results in a very high temperature, capable of melting or vaporizing
just about anything. So this process takes place like this:

1) A current is run through an anode, or a positively charged piece of carbon,

2) Then this current jumps through a certain type of plasma material to a cathode, or a negatively
charged piece of carbon, where there is an evaporation and deposition of carbon particles in
through the plasma,

3) Finally an outer hard-shell region made of decomposed graphite is formed and an inner core
region with loosely packed columns which consist of straight, stiff multishell carbon nanotubes

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and closed polyhedral particles (also known as carbon nanoparticles). These columns grow at a
rate of approximately 1mm per minute on the cathode surface. The best result of carbon
nanotubes and nanoparticles from the anode that can be obtained is about 25%. The average
temperature in the plasma where the nanotubes are formed is very high at 4000 K (about 6740
degrees F).

To obtain single-shell carbon nanotubes, a catalyst must be added to the evaporated

carbon. This catalyst is commonly a metal such as cobalt, nickel, or a mixture of certain other
metals. This metal catalyst along with graphite powder is added in a hole drilled through the
anode contact (we will see later that this catalyst addition adds to the impurities on the
nanotubes). During the arc-discharge, web-like structures are formed around the cooler parts of
the electrodes. Within these structures, bundles of 10-100 single shell nanotubes are formed. This
particular method is normally very inefficient, but the use of a nickel-yttrium catalyst has
improved the efficiency and overall production of single shell nanotubes.

2.1.4 ADVANTAGES

 Improves conductive, mechanical, and flame barrier properties of plastics and composites
 Optimizes processing fabrication, and reduces shipping costs
 Enables eco-friendly anti-fouling paints, and other new applications
 Enables clean, bulk micromachining and assembly of electronic components
 Improves the true total cost of formulation, processing, and manufacturing
 Extremely small and lightweight, making them excellent replacements for metallic wires
 Resources required to produce them are plentiful, and many can be made with only a
small amount of material
 Are resistant to temperature changes, meaning they function almost just as well in
extreme cold as they do in extreme heat
 Have been in the R&D phase for a long time now, meaning most of the kinks have been
worked out
 As a new technology, investors have been piling into these R&D companies, which will
boost the economy

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2.1.5 DISADVANTAGES

 Despite all the research, scientists still don't understand exactly how they work
 Extremely small, so are difficult to work with
 Currently, the process is relatively expensive to produce the nanotubes
 Would be expensive to implement this new technology in and replace the older
technology in all the places that we could
 At the rate our technology has been becoming obsolete, it may be a gamble to bet
on this technology

2.2 CNFET[2]
A carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes
a single carbon nanotube or an array of carbon nanotubes as the channel material instead of
bulk silicon in the traditional MOSFET structure

Fig 4. CNFET

2.2.1 CNFET FABRICATION

There are many types of CNTFET devices; a general survey of the most common geometries are
covered below.

Back-gated CNTFETs

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Fig 5 Back gated CNTFET : Top view side view

The earliest techniques for fabricating carbon nanotube (CNT) field-effect transistors
involved pre-patterning parallel strips of metal across a silicon dioxide substrate, and then
depositing the CNTs on top in a random pattern. The semiconducting CNTs that happened to fall
across two metal strips meet all the requirements necessary for a rudimentary field-effect
transistor. One metal strip is the "source" contact while the other is the "drain" contact. The
silicon oxide substrate can be used as the gate oxide and adding a metal contact on the back
makes the semiconducting CNT gateable.

This technique suffered from several drawbacks, which made for non-optimized
transistors. The first was the metal contact, which actually had very little contact to the CNT,
since the nanotube just lay on top of it and the contact area was therefore very small. Also, due to
the semiconducting nature of the CNT, a Schottkey Barrier forms at the metal-semiconductor
interface, increasing the contact resistance. The second drawback was due to the back-gate
device geometry. Its thickness made it difficult to switch the devices on and off using low
voltages, and the fabrication process led to poor contact between the gate dielectric and CNT.

Top-gated CNTFETs

Fig 6.The process for fabricating a top-gated CNTFET.

Eventually, researchers migrated from the back-gate approach to a more advanced top-gate
fabrication process. In the first step, single-walled carbon nanotubes are solution deposited onto
a silicon oxide substrate. Individual nanotubes are then located via atomic force microscope or

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scanning electron microscope. After an individual tube is isolated, source and drain contacts are
defined and patterned using high resolution electron beam lithography. A high temperature
anneal step reduces the contact resistance by improving adhesion between the contacts and CNT.
A thin top-gate dielectric is then deposited on top of the nanotube, either via evaporation or
atomic layer deposition. Finally, the top gate contact is deposited on the gate dielectric,
completing the process.

Arrays of top-gated CNTFETs can be fabricated on the same wafer, since the gate
contacts are electrically isolated from each other, unlike in the back-gated case. Also, due to the
thinness of the gate dielectric, a larger electric field can be generated with respect to the
nanotube using a lower gate voltage. These advantages mean top-gated devices are generally
preferred over back-gated CNTFETs, despite their more complex fabrication process.

Wrap-around gate CNTFETs

Sheathed CNT

Gate all-around CNT Device

Wrap-around gate CNTFETs, also known as gate-all-around CNTFETs were developed in

2008, and are a further improvement upon the top-gate device geometry. In this device, instead
of gating just the part of the CNT that is closer to the metal gate contact, the entire circumference
of the nanotube is gated. This should ideally improve the electrical performance of the CNTFET,
reducing leakage current and improving the device on/off ratio.

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Device fabrication begins by first wrapping CNTs in a gate dielectric and gate contact via atomic
layer deposition. These wrapped nanotubes are then solution-deposited on an insulating substrate,
where the wrappings are partially etched off, exposing the ends of the nanotube. The source,
drain, and gate contacts are then deposited onto the CNT ends and the metallic outer gate
wrapping.

2.2.2 ELECTRICAL PROPERTIES

The electrical properties of carbon nanotube fets (cntfets) have been studied in Detail.
The conduction type of the cntfets was dependent on the work function of The contact metal,
which suggests that Fermi level pinning at the metal/nanotube Interface does not happen. Based
on the two-probe and four-probe resistance Measurements, it was shown that the carrier transport
at the contact is explained by the Edge contact model even in the diffusive regime. The chemical
doping using F4TCNQ Was effective to reduce not only the channel resistance but also the
contact resistance

It has also been shown that the surface potential measurement based on the electrostatic
Force detection in the scanning probe microscopy was effective in studying the behavior Of the
cntfets such as the transient behavior and the effect of the defects. Finally, in The cntfets
fabricated using plasma-enhanced (PE) CVD-grown nanotubes, most of The drain current could
be modulated by the gate voltage with little non-depletable drain Current suggesting the
preferential growth of the nanotubes with semiconducting Behavior.

 Electrical properties of the CNT-fets

 Dependence on the work function of the contact metal The operation of the device with
back gate (BG) is explained by the Schottky barrier transistor model [3, 4] where the
Schottky barrier formed at the contact which determines the carrier injection from the
Contacts is controlled by the gate voltage. In such model, we can expect I-V
characteristics are Dependent on the work function of the contact metal because Schottky
barrier height is dependent on The work function.

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 Quasi pn diodes
If we take advantage of the work function dependence of the I-V characteristics, it is
possible to Implement quasi pn diode using different contact metals for anode and
cathode without any impurity Doping. Figure 2 shows I-V characteristics of the quasi pn
diode in which Pd and Ca are used for the Anode and cathode, respectively. Rectifying
behavior is obtained in the quasi pn diode as shown in the Figure. The insets show
schematic band diagrams of the nanotube diode at forward and reverse biases,
Respectively, which explains the rectifying behavior.

Fig 7. Drain current as a function of the gate voltage for various contact metals.

Fig 8. I-V Characteristics Of The Nanotube Quasi-Pn Diode.

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2.2.3 ADVANTAGES

 Better control over channel formation.

 Better threshold voltage.
 Better subthreshold slope.
 High electron mobility.
 High current density.
 High transconductance

2.2.4 DISADVANTAGES

 Lifetime (Degradation)

The carbon nanotube degrades in a few days when exposed to oxygen. There has been
several works done on passivating the nanotubes with different polymers and increasing their
lifetime.

 Reliability
Carbon nanotubes have shown reliability issues when operated under high electric field
or temperature gradients. Avalanche breakdown occurs in semiconducting CNT and joule
breakdown in metallic CNT. Unlike avalanche behavior in silicon, avalanche in CNTs is
negligibly temperature-dependent. Applying high voltages beyond avalanche point results in
Joule heating and eventual breakdown in CNTs. This reliability issue has been studied, and it is
noticed that the multi-channeld structure can improve the reliability of the CNTFET.

The multi-channeled CNTFETs can keep a stable performance after several months,
while the single-channeled CNTFETs are usually out of work after a few weeks in the ambient
atmosphere. The multi-channeled CNTFETs keep operating when some channels break down,
this won’t happen in the single-channeled ones.

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 Difficulties in mass production, production cost

Although CNTs have unique properties such as stiffness, strength, and tenacity compared
to other materials especially to silicon, There is currently no technology for their mass
production and high production cost. To overcome the fabrication difficulties, several methods
have been studied such as direct growth, solution dropping, and various transfer printing
techniques

2.3 SI NANODOTS[3]

fig 9. Si nanodots

What Are Nanodots?

Nanodots, also known as quantum dots, consist of 100s-1000s of atoms of inorganic

semiconductor nanoparticles and are approximately one billionth of a meter in size. Developed in
the mid-1980s for optoelectronic applications, they have interesting structural, electronic, and
optical properties - they strongly absorb light in the near UV range and re-emit visible light that
has its color determined by both the nanodot size and surface chemistry. And as the size of
nanodots can be controlled during synthesis with nanoscale precision, so the optical properties

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can be manipulated. In addition, nanodots have a longer life than organic fluorophores, and have
a broad excitation spectrum. These factors combined make the use of quantum dots as light-
emitting phosphors a strong candidate for a major application of nanotechnology in the future.

2.3.1 FABRICATION OF SI NANODOTS

Fig 10. Fabrication Of Si Nanodots

schematically in Figure 1(a). Details of the fabrication processcan be found elsewhere.19 In our
experiment, optical deep-UV lithography (DUVL) was used to form the initial polysilicon line
patterns with widths of 250 nm, lengths of12 μm, and thicknesses of 120 nm. A 10-nm-thick
silicon dioxide film was deposited conformally by low-pressure chemical vapor deposition
(LPCVD). Directional blank etching of the silicon dioxide film removes the film on the
horizontal surface to leave residual silicon dioxide spacer nanowires on the sidewalls of the
original polysilicon features. Silicon dioxide nanowires were formed by selective removal of the
polysilicon using reactive ion etching (RIE).
Then the silicon dioxide nanowire pattern was transferred into the silicon substrate to
form silicon nanowires. Note that the width of the silicon nanowire pattern is determined by the
thickness of the conformal silicon dioxide layer,whereas the pitch of the silicon nanowire is
determined by the initial line width of the optical lithography. Because thethickness of the
deposited film can be controlled to 10 nm or less with high precision, this method permits the

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generation of nanopatterns far smaller than possible by optical lithography. In this way, we have
batch-fabricated high aspectratio sub-20-nm Si wires from 250-nm patterns generated by DUV
optical photolithography (Figure 1b and c).

2.3.2 ELECTRICAL PROPERTIES

The electrical transport behavior of n-n indium nitride nanodot-silicon (InN ND-Si)
heterostructure Schottky diodes is reported here, which have been fabricated by plasma-assisted
molecular beam epitaxy. InN ND structures were grown on a 20 nmInN buffer layer on Si
substrates. These dots were found to be single crystalline and grown along [0 0 0 1] direction.
Temperature-dependent current density-voltage plots (J-V-T) reveal that the ideality factor (?)
and Schottky barrier height (SBH) (FB) are temperature dependent. The incorrect values of the
Richardson constant (A**) produced suggest an inhomogeneous barrier.

Descriptions of the experimental results were explained by using two models. First one is
barrier height inhomogeneities (BHIs) model, in which considering an effective area of the
inhomogeneous contact provided a procedure for a correct determination of A**. The
Richardson constant is extracted ~110 A cm-2 K-2 using the BHI model and that is in very good
agreement with the theoretical value of 112 A cm-2 K-2. The second model uses Gaussian
statistics and by this, mean barrier height F0 and A** were found to be 0.69 eV and 113 A cm-2

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K-2, respectively.

2.4 NANOWIRES[3]

A nanowire is a nanostructure, with the diameter of the order of a nanometer

(10−9 meters). Alternatively, nanowires can be defined as structures that have a thickness or
diameter constrained to tens of nanometers or less and an unconstrained length. At these scales,
quantum mechanical effects are important — which coined the term "quantum wires". Many
different types of nanowires exist, including metallic (e.g., Ni, Pt, Au), semiconducting
(e.g., Si, InP, GaN, etc.), and insulating (e.g., SiO2, TiO2). Molecular nanowires are composed of
repeating molecular units either organic (e.g. DNA) or inorganic (e.g. Mo6S9-xIx).

The nanowires could be used, in the near future, to link tiny components into extremely
small circuits. Using nanotechnology, such components could be created out of chemical
compounds.

Fig 11. Nanowires

2.4.1 FABRICATION OF NANOWIRES AT SURFACES

The goal of this project is the design of artificial materials that consist of
ultrafine wires or linear arrays of dots, ten to hundred times finer than those produced with

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commercial micro-structure fabrication techniques. In fact, we have gone all the way down
to atom chains which may be viewed as the ultimate nanowires (scroll to the bottom for those).
These patterns are formed by self-assembly, where atoms arrange themselves naturally
at stepped silicon surfaces.

An important aspect in fabricating nanowires is the ability to prepare wires of an any material on
any substrate with any thickness. In particular, using silicon wafers as substrate is highly-
desirable. To achieve this goal we suggest the following "universal" process. First, a silicon
substrate with a regular array of steps is prepared (A). Then, stripes (B) or dots (C) of a
passivating material are attached to the step edges. This part is analogous to creating a
photoresist mask in traditional lithography.

As mask material we use calcium fluoride, which is lattice-matched to silicon and chemically
inert. Eventually, the desired material is deposited on the remaining silicon, for example by
substrate-selective chemical vapor deposition (CVD) or electroplating. Alternatively, calcium
fluoride could become useful as an etch mask for producing trenches in the silicon that can be
filled with new materials to achieve a planar structure.

The figure below shows the preparation of calcium fluoride masks in schematic form (top),
together with actual data (bottom).

Fig 12 Preparation Of Calcium Fluoride Masks

To start along this pathway, we determine the conditions for obtaining highly-regular step

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structures on silicon. The images below demonstrate the range of step arrays that can be formed
on silicon surfaces by self-assembly. Typically, the step spacing is comparable to the size of a
virus. These images are taken with a scanning tunneling microscope (STM). They show the
derivative of the tip height. That gives the impression of a surface illuminated from the left, with
the steps casting dark shadows to the right.

Particularly perfect step arrays could be achieved on the Si(111)7x7 surface. The 7x7
structure causes steps running along the [011]-direction to become extremely straight, because
each kink requires generating 14 new rows of silicon atoms (7 rows, two layers deep). The step
edges are atomically-straight with a kink spacing as low as a single kink in 20,000 atoms, as
seen in the image below. These are taken with a scanning tunneling microscope (STM). The x-
derivative of the topography is displayed, which makes steps appear as dark lines. The image on
the right zooms in on the terrace between two steps (heavy dark lines). The atomic pattern of the
7x7 structure structure is resolved, which has fine grooves built in that run parallel to the step
edges. These grooves are 2.3 nm apart and determine the location of possible step edges. They
may be viewed as the LEGO blocks of the aspiring nano-engineer.
Fabrication of straight steps:

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Our "universal process" can be carried further by producing a calcium fluoride mask, as shown
in the image below. A stepped silicon surface is coated with a layer of CaF1 and CaF2 stripes are
formed on top of that layer. These stripes are are continuous and do not touch each other,
because adjacent stripes cannot bond to each other. The stripe width of 7 nm achieved here is
well below the resolution of 180 nm achieved in commercial lithography for chip fabrication.

The third step of the "universal process" involves selective deposition or etching between the
masked areas. The picture below shows that molecules can be deposited selectiveley in the
CaF1 grooves between CaF2stripes. Using organometallic molecules, such as ferrocene, it is
possible to fabricate iron wires 3 nanometers wide.

2.4.2 ELECTRICALPROPERTIES

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A simple and useful experimental alternative to field-effect transistors for measuring

electrical properties (free electron concentration nd, electrical mobility μ, and conductivity σ) in
individual nanowires has been developed. A combined model involving thermionic emission and
tunneling through interface states is proposed to describe the electrical conduction through the
platinum nanowire contacts, fabricated by focused ion beam techniques. Current-voltage (I-V)
plots of single nanowires measured in both two- and four-probe configurations revealed high
contact resistances and rectifying characteristics. The observed electrical behavior was modeled
using an equivalent circuit constituted by a resistance placed between two back-to-back Schottky
barriers, arising from the metal-semiconductor-metal (M-S-M) junctions. Temperature-
dependent I-V measurements revealed effective Schottky barrier heights up to ΦBE=0.4 eV.

2.4.3 ADVANTAGES

 They can be used to build the next generation of computing devices.

 Nanowires are used to create p-type and n-type semiconductors.

 These Nanowires are used to create a p-n junction with only one wire.

 After p-n junctions were built with nanowires, the next logical step was to build logic
gates. By connecting several p-n junctions together, researchers have been able to create
the basis of all logic circuits: the AND, OR, and NOT gates have all been built from
semiconductor nanowire crossings.

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2.4.4 DISADVANTAGES

 The drawback of nanowire battery is that the process used in making battery, feeds
gaseous silicon to a liquid gold catalyst to make the solid electrode. This involves a high-
temperature (600 to 900 °C) process that could be costly to scale up. So this drawback of
nanowire batteries can be a downturn for organisations too. As in order to invest in this
technology they may need a lot of money which will indirectly increase the cost of their
product as total cost of product would increase.

 Secondly this will also affect the economies of scale of the company.

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CHAPTER 3[4]

3.1 APPLICATION BUILT USING BOTTOM DEVICES

3.1.1 CNFET

Carbon Nanotube FETs (CNFETs) are showing significant promise in nanoelectronics.

They are one of the principle areas of research that are seen as having the capability of replacing
MOSFET transistors. In fact, their performance is much better than MOSFETs below 10nm, with
the operation frequencies of CNFET devices being up to1000 times greater. This project
investigates various properties of CNFETs and particularly their application in digital logic
design. Various logic gates were built using CNFETs, and their properties are studied. Finally, a
4-bit Ripple Carry Adder (RCA) was built using the gates and the power dissipation and
propagation times are observed.

The logic gates built were the inverter (INV), NAND, NOR, XOR, AND and OR. The
gates were implemented using the generic Pull-Up- and Pull-Down-Network with a 0.5V power
supply. Parasitic capacitances of the gates were estimated and included in the models. The gates
were then simulated.

3.1.2 SI NANODOTS

While silicon nanotubes are still in the early stages of their development, scientists and
engineers have already begun to consider the possible uses for the new material.

Silicon nanotubes have been considered for use in electronics, because it appears that
silicon nano-materials may behave like a metal fuel, since the structure can accommodate
molecules of hydrogen so it might resemble coal without the CO2. A silicon nanotube charged
with hydrogen delivers energy and in the process leaves residual water, ethanol, silicon and sand.
However, as hydrogen production requires considerable energy, this is only a proposed method
of storing energy, not producing it.

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3.1.3 CNT

Current use and application of nanotubes has mostly been limited to the use of bulk
nanotubes, which is a mass of rather unorganized fragments of nanotubes. Bulk nanotube
materials may never achieve a tensile strength similar to that of individual tubes, but such
composites may, nevertheless, yield strengths sufficient for many applications. Bulk carbon
nanotubes have already been used as composite fibers in polymers to improve the mechanical,
thermal and electrical properties of the bulk product.

 Easton-Bell Sports, Inc. have been in partnership with Zyvex Performance Materials,
using CNT technology in a number of their bicycle components—including flat and riser
handlebars, cranks, forks, seatposts, stems and aero bars.
 Zyvex Technologies has also built a 54' maritime vessel, the Piranha Unmanned Surface
Vessel, as a technology demonstrator for what is possible using CNT technology. CNTs
help improve the structural performance of the vessel, resulting in a lightweight 8,000 lb
boat that can carry a payload of 15,000 lb over a range of 2,500 miles.[130]
 Amroy Europe Oy manufactures Hybtonite carbon nanoepoxy resins where carbon
nanotubes have been chemically activated to bond to epoxy, resulting in a composite
material that is 20% to 30% stronger than other composite materials. It has been used for
wind turbines, marine paints and variety of sports gear such as skis, ice hockey sticks,
baseball bats, hunting arrows, and surfboards.

Other current applications include:

 Tips for atomic force microscope probes

 In tissue engineering, carbon nanotubes can act as scaffolding for bone growth

3.1.4 NANOWIRES

Nanowires still belong to the experimental world of laboratories. However, they may
complement or replace carbon nanotubes in some applications.

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To create active electronic elements, the first key step was to chemically dope a
semiconductor nanowire. This has already been done to individual nanowires to create p-type
and n-type semiconductors.

The next step was to find a way to create a p-n junction, one of the simplest electronic
devices. This was achieved in two ways. The first way was to physically cross a p-type wire over
an n-type wire. The second method involved chemically doping a single wire with different
dopants along the length. This method created a p-n junction with only one wire.

After p-n junctions were built with nanowires, the next logical step was to build logic
gates. By connecting several p-n junctions together, researchers have been able to create the
basis of all logic circuits: the AND, OR, and NOT gates have all been built from semiconductor
nanowire crossings.

Researchers reported constructing the first NAND gate from undoped silicon nanowires.
This avoids the problem of how to achieve precision doping of complementary nanocircuits,
which is unsolved. They were able to control the Schottky barrier to achieve low-resistance
contacts by placing a silicide layer in the metal-silicon interface.

It is possible that semiconductor nanowire crossings will be important to the future of

digital computing. Though there are other uses for nanowires beyond these, the only ones that
actually take advantage of physics in the nanometer regime are electronic.

Nanowires are being studied for use as photon ballistic waveguides as interconnects
in quantum dot/quantum effect well photon logic arrays. Photons travel inside the tube, electrons
travel on the outside shell. When two nanowires acting as photon waveguides cross each other
the juncture acts as a quantum dot.

Conducting nanowires offer the possibility of connecting molecular-scale entities in a molecular

computer. Dispersions of conducting nanowires in different polymers are being investigated for
use as transparent electrodes for flexible flat-screen displays.

Because of their high Young's moduli, their use in mechanically enhancing composites is being
investigated. Because nanowires appear in bundles, they may be used as tribological additives to
improve friction characteristics and reliability of electronic transducers and actuators.

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Because of their high aspect ratio, nanowires are also uniquely suited
to dielectrophoretic manipulation.

3.2 MEMORY[5]

Memory storage

Electronic memory designs in the past have largely relied on the formation of transistors.
However, research into crossbar switch based electronics have offered an alternative using
reconfigurable interconnections between vertical and horizontal wiring arrays to create ultra high
density memories. Two leaders in this area are Nantero which has developed a carbon nanotube
based crossbar memory called Nano-RAM and Hewlett-Packard which has proposed the use
of memristor material as a future replacement of Flash memory.

An example of such novel devices is based on spintronics.The dependence of the

resistance of a material (due to the spin of the electrons) on an external field is
called magnetoresistance. This effect can be significantly amplified (GMR - Giant Magneto-
Resistance) for nanosized objects, for example when two ferromagnetic layers are separated by a
nonmagnetic layer, which is several nanometers thick (e.g. Co-Cu-Co). The GMR effect has led
to a strong increase in the data storage density of hard disks and made the gigabyte range
possible. The so-called tunneling magnetoresistance (TMR) is very similar to GMR and based on
the spin dependent tunneling of electrons through adjacent ferromagnetic layers. Both GMR and
TMR effects can be used to create a non-volatile main memory for computers, such as the so-
called magnetic random access memory or MRAM

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CHAPTER 4[6]

4.1 FUTURE SCOPE OF NANOELECTRONICS

Nanoelectronics is flourishing its manufacturing day by day scientists are exploring new
characteristics of natural resources with the help of nanaoelectronics. Smallest featured
integrated circuit chip which are further inserted into robots are the inventions of
nanaoelectronics. Micro electronics is also evolving gradually in the nano electronics which
would of great use to the technological world in the coming future. Researchers are now
predicting that intelligent devices like computers will be assembled in the future by using
molecules which would be the major achievement of nanoelectronics.

We can imagine a future for hybrid devices, combining the strength of both approaches.
In such a scenario, we would use exotic materials for new functions that are needed only at
certain places on a very large-scale circuit that is generated by a conventional semiconductor
process. Newly synthesized nanostructures can also compete in applications where perfection is
not of paramount importance but cheap processing, chemical flexibility, and function are.
Electronic biosensors in which carbon nanotubes or nanowires are used to detect specific
molecules are certainly one of those promising areas, but there may well be others that we have
not imagined yet.

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4.2 CONCLUSION

Electronics obtained through the bottom-up approach of molecular-level control of

material composition and structure may lead to devices and fabrication strategies not possible
with top-down methods. This review presents a brief summary of bottom-up and hybrid bottom-
up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar
motif.

First, we discussed representative electromechanical and resistance-change memory

devices based on carbon nanotube and core-shell nanowire structures, respectively. These device
structures show robust switching, promising performance metrics and the potential for terabit-
scale density.

Second, we will revied architectures being developed for circuit-level integration, hybrid
crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key
concepts such lithography-independent, chemically coded stochastic demultipluxers. Finally,
bottom-up fabrication approaches, including the opportunity for assembly of three-dimensional,
vertically integrated multifunctional circuits

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REFERENCES

1. ^ "MEMS Overview". Retrieved 2009-06-06.

2. ^ Melosh, N.; Boukai, Abram; Diana, Frederic; Gerardot, Brian; Badolato, Antonio;
Petroff, Pierre & Heath, James R. (2003). "Ultrahigh density nanowire lattices and
circuits". Science 300(5616): 112–
5. Bibcode:2003Sci...300..112M. doi:10.1126/science.1081940.PMID 12637672.
3. ^ Das, S.; Gates, A.J.; Abdu, H.A.; Rose, G.S.; Picconatto, C.A. & Ellenbogen, J.C.
(2007)."Designs for Ultra-Tiny, Special-Purpose Nanoelectronic Circuits". IEEE Trans.
on Circuits and Systems I 54 (11): 11. doi:10.1109/TCSI.2007.907864.
4. ^ Goicoechea, J.; Zamarreñoa, C.R.; Matiasa, I.R. & Arregui, F.J. (2007). "Minimizing
the photobleaching of self-assembled multilayers for sensor applications". Sensors and
Actuators B: Chemical 126 (1): 41–47. doi:10.1016/j.snb.2006.10.037.
5. ^ Petty, M.C.; Bryce, M.R. & Bloor, D. (1995). An Introduction to Molecular
Electronics. London: Edward Arnold. ISBN 0-19-521156-1.
6. ^ Aviram, A.; Ratner, M. A. (1974). "Molecular Rectifier". Chemical Physics Letters

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