YCT Experts Team Electronics & Communication Eng Anand Mahajan Print

ALL INDIA ENGINEERING SERVICES AND
PSU'S EXAMINATIONS
Electronics &
Communication
Engineering
VOLUME-1
Previous Years Chapterwise and
Sub-topicwise Objective Solved Papers
Useful for : UPSC ESE (Pre), ISRO SCIENTIST/ENGINEER, UPPCL AE, UPRVUNL AE, RRB SSE,
DMRC/LMRC AM, UPJN AE, UPPSC AE, UKPSC AE, UPSC JWM, UJVNL AE, PTCUL,
ASSAM PSC, APPSC, BPSC, CGPSC, DRDO Scientist, GATE, Gujarat PSC, Haryana PSC,
HPPSC, JPSC, J&K PSC, Kerala PSC, Karnataka PSC, KPTCL AE, Maharashtra PSC, MP
PSC, Mizoram PSC, Odisha PSC, Punjab PSC, RPSC, TNPSC, TANGEDCO AE, Tamilnadu
TRB, Telangana PSC, Vizag Steel MT, JUVNL AE, TSGENCO AE, AP TRANSCO AE,
GPSC, DFCCIL AM, AAI, NAGALAND PSC, NIELIT SCIENTIST, SIKKIM PSC.
Chief Editor
A.K. Mahajan
Compiled by
Er. Pradeep Kumar
Edited by
Er. Anil Kumar, Er. Rakesh Patel
Computer Graphics by
Balkrishna Tripathi, Charan Singh, Vinay Sahu
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Electronics &
Communication Engineering
Chapterwise solved Papers
VOLUME -I
Electronic Devices and Circuits
Analog Electronics
Electronics Measurements and Instrumentation
Digital Electronics
Advanced Electronics
Power Electronics & Drives
Control system
Signals and Systems Processing
VOLUME - II
Network Theory
Electromagnetic Field Theory
Communication System
Advance Communication System
Microprocessor and Microcontroller
Computer Organization and Architecture
Basic Electrical Engineering
Material Science
Engineering mathematics
Microwave Engineering
2
CONTENT
Electronics & Communication Engineering AE Syllabus ....................... 5-6
Electronics & Communication Engineering AE Previous
Year Exam Paper Analysis Chart ............................................................ 7-11
Trend Analysis of Previous Year Papers
Through Bar Graph and Pie Chart.............................................................. 12
Electronic devices and Circuits ............................................................. 13-198
Basic semiconductors physics ............................................................................... 13-79
p-n junction diode and Opto- Electronics ............................................................ 80-140
Bipolar junction transistors (BJTs) .................................................................... 141-166
Field Effect transistors (FETs)........................................................................... 167-190
Integrated circuit (ICs) ....................................................................................... 190-198
Analog Electronics ............................................................................... 199-502

Diode circuit ......................................................................................................199–246
BJT Amplifiers .................................................................................................. 247-299
Frequency response of BJT amplifiers .............................................................. 300-326
Analysis of FETs circuits .................................................................................. 326-358
Power amplifiers ............................................................................................... 359-376
Feedback amplifiers .......................................................................................... 376-392
Oscillator ........................................................................................................... 392-409
Operational amplifiers and their applications. ................................................. 410-484
Multivibrators, Voltage Regulators & power supply ........................................ 485-502
Electronics Measurements and Instrumentation.............................. 503-636

Error Analysis, Units and Dimensions ............................................................. 503-518
Basic Instruments ............................................................................................. 518-547
Potentiometers and Q-meters ........................................................................... 547-552
Bridge measurements ....................................................................................... 552-565
Power and Energy Measurement ...................................................................... 565-570
Electronic Voltmeters and Digital Voltmeters ................................................. 571-581
Cathode Ray Oscilloscope................................................................................ 582-592
DF Meters and Analyzers ................................................................................ 592-594
Transducers ...................................................................................................... 594-634
Data Acquisition Systems and Telemetry systems........................................... 635-636
3
Digital Electronics ................................................................................ 637-866
Number system ................................................................................................. 637-661
Boolean Algebra and Simplification of Boolean functions .............................. 662-693
Logic gates ........................................................................................................ 694-718
Combinational Logic Circuits ........................................................................... 719-752
Sequential Logic Circuits.................................................................................. 753-803
IC Logic Families ............................................................................................. 804-832
A/D and D/A Converters .................................................................................. 832-855
Semiconductors Memories ............................................................................... 855-866
Advanced Electronics........................................................................... 867-870
Power Electronics & Drives ................................................................ 871-891
Control system .................................................................................... 892-1126
Mathematical Modelling of Dynamic Linear Continuous System ....................... 892-900
Block Diagram & Signal Flow Graph .................................................................. 900-929
Time Response Specification................................................................................ 930-980
Concepts of Stability........................................................................................... 981-1008
Root Locus Technique ..................................................................................... 1008-1027
Frequency Response Analysis .......................................................................... 1028-1079
Compensators & Controllers ............................................................................ 1080-1106
State Space Analysis ......................................................................................... 1106-1126
Signals and Systems Processing ...................................................... 1127-1312
Introduction of Signals and Systems ................................................................ 1127-1159
Linear Time Invariant System .......................................................................... 1159-1185
Continuous Time Fourier Series ....................................................................... 1186-1195
Continuous Time Fourier Transform (CTFT) .................................................. 1195-1216
Laplace Transform ............................................................................................ 1217-1241
Sampling ........................................................................................................... 1241-1255
Discrete Fourier Transform (DFT) ................................................................... 1255-1267
Z-Transform ...................................................................................................... 1268-1297
Random Signal and Application ....................................................................... 1297-1304
Digital Filters .................................................................................................... 1304-1312
Note : Network Theory, Electromagnetic Field Theory, Communication System, Advance

communication system, Microprocessor and Microcontroller, Computer Organization
and Architecture, Basic Electrical Engineering, Materials Science, Engineering
mathematics, Microwave Engineering (Study Volume-II)
4
Electronics & Communication Engineering
AE, State PSC, PSU SYLLABUS
Networks Theory:
Basic of Network Theory, Nodal and Mesh analysis, Network Theorems- Superposition Theorem, Thevenin and
Norton's Theorem, Maximum power transfer Theorem, Star-Delta transformation, Duality Steady state,
Sinusoidal analysis, Time domain analysis of simple linear circuits, Frequency domain analysis of RLC (Series
and Parallel) circuits, Two port network parameters, Graph Theory.
Electromagnetics:
Electrostatics, Maxwell's equations, wave equation, Poynting theorem & vector. Plane waves- Reflection and
refraction, polarization, phase and group velocity, calculation of skin depth, Transmission lines- Equations,
characteristic impedance, impedance matching, impedance transformation, S-parameters, Smith chart,
Waveguides- Basic of Waveguides. Antennas- Basic Concept, Definition, Types of Antenna, radiation pattern,
gain, and directivity return loss etc.
ELECTRONIC COMPONENTS AND MATERIALS
Materials : Classification of materials , Conducting, semi-conducting and insulating materials through a brief
reference to their atomic structure. Conducting Materials : Resistors and factors affecting resistivity such as
temperature, alloying and mechanical stressing. Classification of conducting materials into low resistivity and
high resistivity materials. Insulating Materials : Important relevant characteristics (electrical, mechanical and
thermal) and applications of the following material: Mica, Glass, Copper, Silver, PVC, Silicon, Rubber,
Bakelite, Cotton, Ceramic, Polyester, Polythene and Varnish. Magnetic Materials : Different Magnetic
materials; (Dia, Para, Ferro) and their properties. Ferro magnetism, Domains, permeability, Hysteresis loop.
Soft and hard magnetic materials, their examples and typical applications.
Electronics measurement and instrumentation:
Electronics measurement and non-electrical quantities, Electronics measuring instruments, Error analysis,
Measurements of basic electrical quantities, Transducers, Working principle of measuring instruments.
Electronic Devices Circuits (EDC):
Energy bands in intrinsic and extrinsic silicon, Carrier transport- diffusion current, Drift current, Mobility and
Resistivity, Diffusion constant, Generation and recombination of carriers, Diode, BJT (Bipolar Junction
Transistor), P-N junction, Transistor, Zener diode, LED (Light Emitting Diode), a photodiode and solar cell.
Analog Electronics:
BJT (Bipolar Junction Transistor), and MOSFETs, Simple diode circuits- clipping, clamping and rectifiers, BJT
and MOSFET amplifiers- multi-stage, differential, feedback, power and operational, Operational Amplifier
circuits, Active filters, Oscillators- criterion for oscillation, RC Phase Shift, using transistor and FET, Wein
bridge, Clapp's, Colpitts oscillator only Formula, Function generators, wave-shaping circuits and 555 timers,
Voltage reference circuits, Power supplies- ripple removal and regulation.
Power Electronics:
Power semiconductor: Power semiconductor devices their symbols and static characteristics and
specifications of switches, types of power electronics circuits Operations, steady state & switch
characteristics & switching limits of Power Transistor Operation and steady state characteristics of Power
MOSFET and IGBT Thyristor Operation V-I characteristics, two transistor mode, methods of turn-on
operation of GTO, MCT and TRIAC.
Phase Controlled Rectifiers: Phase Angle Control, Single-phase half-wave Controlled Rectifier (One
quadrant), Single-phase Full-wave Controlled Rectifier (Two quadrant Converters), Performance Factors of
Line-commutated Converters. The Performance Measures of Two-pulse converters, Three phase Controlled
Converters.
Signal and System:
Time Shifting, Scaling & Reversal, System- Linear, causality, stability, Fourier series and Fourier transform
representations, Sampling theorem, Discrete- Time signals – discrete-time Fourier transform, DFT (Discrete
Fourier transform), FFT and Z-transform, LTI systems- Properties, frequency response, group delay, phase
delay.
Control Systems:
Basic control system, Transfer function mason's formula, Block diagram representation, Signal flow graph,
Transient and steady-state analysis of LTI systems- First and Second Order System, Frequency response-
5
Routh-Hurwitz criterion, Polar Plot analysis, and Nyquist stability criteria, Bode plot and root-locus plots,
Calculation of Gain and Phase Margin, Lag, lead and lag-lead compensation, P, PI, PD, and PID, State variable
Analysis- State model solution of LTI systems, State model to transfer function, Controllability, and
Observability. Non-Linear Control System : Introduction, behaviour of non-linear control system. Different
types of nonlinearities, saturation, backlash, hysteresis, dead zone, relay, fiction, characteristics of non-linear
control system, limit cycles, jump resonance, jump phenomenon. Difference between linear and non-linear
control system.
Digital Electronics:
Number systems, Code converters: BCD, Binary, HEX, Octal other codes, Combinational Circuits, Boolean
algebra, Karnaugh map, CMOS implementations, Arithmetic Circuits Multiplexers, Encoder & Decoders,
Sequential circuits- latches and all flip-flops, counters, shift-registers, Data converters- ADC (Analog to Digital
Converter) and DAC (Digital to Analog Converter). Semiconductor memories: ROM (Read Only Memory),
SRAM (Static Read Access Memory), DRAM (Dynamic read Access Memory).
Microprocessor and Microcontroller:
Architecture, All Instruction, Programming, Memory. Architecture of a typical microprocessor, configurations
and instructional pair configuration systems and working of various peripheral interface chips. 8085
Microprocessors, architecture, instruction sets and introduction to 8086.Micro controller: Introduction,
Microcontrollers and Embedded systems, Overview of the 8051, Inside the 8051, Addressing modes, assembly
programming, 8051 data types and directives, interfacing with 8051, Programming the 8051 times.
Communication System:
Analog Communication System: Amplitude modulation and demodulation For Sinusoidal, Rectangular and
Triangular Signal, Angle modulation (Frequency and Phase Modulation) and demodulation, AM and FM
Spectrum Analysis, super heterodyne receivers. Digital communications: PCM (Pulse Code Modulation),
DPCM (Delta Pulse Code Modulation), digital modulation schemes, Bandwidth Calculation, SNR (Signal to
Noise ratio) and BER/Probability error for digital modulation, Fundamentals of error correction, Hamming
codes, Inter-symbol interference, Basics of TDMA, FDMA and CDMA (Code-division Multiple access),
Information theory-Entropy, mutual information and channel capacity theorem.
Advance Communication System
Telephone instruments and signal: Introduction, the subscriber loop, standard telephone set, basic call
procedure, cordless telephones, electronic telephones. Telephone circuit: Introduction, the local subscriber
loop, channel noise and units of power measurements, transmission parameters, voice frequency circuit
arrangements. Public telephone network: Transmission system, public telephone network, automated central
office switches and exchanges, telephone switching hierarchy, common channel signaling system. Multiplexing
of telephone channels: TDM, digital hierarchy, digital carrier line encoding, T-carrier systems, digital carrier
frame synchronization, FDM, WDM. Digital telephony: Introduction, voice digitization, TDM of PCM signals,
digital carrier, Fractional T-Carrier Service, Data Terminal, Digital Carrier Line Encoding, Error Detection, T
Carrier System, T-1 Carrier Computer Networking: Network features- Network topologies, protocols-
TCP/IP, UDP, FTP, models, types, network components, network medias, Specification and standards, types of
cables, UTP, STP, Coaxial cables, Network components like hub, Ethernet switch, router, NIC Cards,
connectors, media and firewall. Difference between PC & Server.
COMPUTER AIDED INSTRUMENTATION
Computer aided Instrumentation, Buses and Standards : Introduction , BUS types : The I/O BUS a) ISA
bus b) EISA Bus c) PCI bus , GPIB 2.5 RS-232, Linear Circuits and Signal Conditioning, Parallel Port (PP)
Interfacing Techniques, Serial Port (SP) Interfacing Techniques, USB Port Interfacing Techniques.
Microwave Engineering:
Rectangular wave Guide: Field components, TE, TM modes, Dominant TE10 mode, Field Distribution, Power
Attenuation. Circular waveguides: TE, TM mode, Wave velocities, Microstrip Transmission line (TL),
Coupled TL, Strip TL, Coupled Strip Line, Coplanar TL, Microwave Cavities. Scattering Matrix, Passive
microwave devices: Microwave Hybrid Circuits, Terminations, Attenuators, Phase Shifters, Directional
Couplers: Two Hole directional couplers, S Matrix of a Directional coupler, Hybrid Couplers, Microwave
Propagation in ferrites, Faraday Rotations, Isolators, Circulators. Microwave Tubes: Limitation of
Conventional Active Devices at Microwave frequency, Two cavity Klystron, Reflex Klystron, Magnetron,
Traveling Wave Tube, Backward Wave Oscillators: Their Schematic, Principle of Operation, Performance
Characteristics and their applications. Solid state amplifiers and oscillators: Microwave Bipolar Transistor,
Microwave tunnel diode, microwave Field-effect Transistor, Transferred electron devices, Avalanche Transit-
time device: IMPATT Diode, TRAPATT Diode. Microwave Measurements: General setup of a microwave
testbench, Slotted line carriage, VSWR Meter, microwave power measurements techniques, Crystal Detector,
frequency measurement, wavelength measurements, Impedance and Reflection coefficient, VSWR, insertion
and attenuation loss measurement, measurement of antenna characteristics, microwave link design.
6
Electronics & Communication Engineering AE Previous Year
Exam Paper Analysis Chart
S.L. Exam NAME EXAM DATE/TIME No. of Questions

Uttar Pradesh Public Service Commission
1. UPPSC Poly. Tech. Lect. Paper-I 22.03.2022 1 × 100
2. UPPSC Poly. Tech. Lect. Paper-II 22.03.2022 1 × 100
3. UPPSC ITI Principal/Asstt. Director 09.01.2022 1 × 100
ISRO Scientist / Engineer
4. ISRO Scientist / Engineer 12.01.2020 1× 80
12. ISRO Scientist / Engineer 2012 1× 80
Union Public Service Commission
19. ESE 20.02.2022 1 × 150
20. ESE 18.07.2021 1 × 150
21. ESE 05.01.2020 1 × 150
22. ESE 06.01.2019 1 × 150
23. ESE 07.01.2018 1 × 150
24. ESE 08.01.2017 1 × 150
25. ESE 2016 2 × 120
26. ESE 2015 2 × 120
27. ESE 2014 2 × 120
28. ESE 2013 2 × 120
29. ESE 2012 2 × 120
30. ESE 2011 2 × 120
31. ESE 2010 2 × 120
32. ESE 2009 2 × 120
33. ESE 2008 2 × 120
34. ESE 2007 2 × 120
35. ESE 2006 2 × 120
36. ESE 2005 2 × 120
37. ESE 2004 2 × 120
38. ESE 2003 2 × 120
39. ESE 2002 2 × 120
40. ESE 2001 2 × 120
41. ESE 2000 2 × 120
42. ESE 1999 2 × 120
43. ESE 1998 2 × 120
44. ESE 1997 2 × 120
7
45. ESE 1996 2 × 120
46. ESE 1995 2 × 120
47. ESE 1994 2 × 120
48. ESE 1993 2 × 120
49. ESE 1992 2 × 120
50. ESE 1991 2 × 120
51. UPSC Poly. Lect. 10.03.2019 1 × 100
52. UPSC JWM 2016 1 × 100
Uttar Pradesh Rajya Vidyut Utpadan Nigam Limited
53. UPRVUNL AE, Shift-II 19.07.2021 1 × 150
54. UPRVUNL AE 2016 1 × 150
55. UPRVUNL AE 2014 1 × 150
Uttar Pradesh Power Corporation Limited
56. UPPCL AE 30.03.2022 1 × 150
57. UPPCL AE 05.11.2019 1 × 150
58. UPPCL AE 31.12.2018 1 × 150
59. UPPCL AE 16.11.2013 1 × 150
UKPSC/UJVNL/PTCUL/UPCL Uttarakhand
60. UKPSC Asstt. Radio officer 2011 1 × 100
61. UJVNL AE 08.05.2016 1 × 126
Andhra Pradesh PSC
62. APPSC Poly. Lect. 14.03.2020 1×150
63. APPSC Poly. Lect. 15.03.2020 1×150
64. APGENCO AE 23.04.2017 1×70
Airports Authority of India
65. AAI ATC 2015 1 × 85
Bhabha Atomic Research Centre
66. BARC Scientific Officer 2016 1 × 75
Bihar Public Service Commission
67. BPSC Asstt. Prof. 12.04.2022 1 × 80
68. BPSC Poly. Lect. 2014 1 × 80
Bharat Sanchar Nigam Limited (BSNL JTO)
69. BSNL JTO 2009 1 × 100
70. BSNL (JTO) 2006 1 × 100
71. BSNL(JTO) 2002 1 × 100
72. BSNL JTO 2001 1 × 100
Chhattishgarh PSC
73. CGPSC Scientific Officer 14.02.2016 1 × 100
Defence Research and Development
74. DRDO Scientist 2009 1× 100
75. DRDO Scientist 2008 1 × 100
Graduate Aptitude Test in Engineering (GATE)
76. GATE 2022 1 × 55
77. GATE 2021 1 × 55
78. GATE 2020 1 × 55
79. GATE 2019 1 × 55
80. GATE 2018 1 × 55
81. GATE 2017 SET-1 1 × 55
82. GATE 2017 SET-2 1 × 55
83. GATE 2016 SET-1 1 × 55
84. GATE 2016 SET-2 1 × 55
85. GATE 2016 SET-3 1 × 55
86. GATE 2015 SET-1 1 × 55
8
87. GATE 2015 SET-2 1 × 55
88. GATE 2015 SET-3 1 × 55
89. GATE 2014 SET-1 1 × 55
90. GATE 2014 SET-2 1 × 55
91. GATE 2014 SET-3 1 × 55
92. GATE 2014 SET-4 1 × 55
93. GATE 2013 1 × 55
94. GATE 2012 1 × 55
95. GATE 2011 1 × 55
96. GATE 2010 1 × 55
97. GATE 2009 1 × 60
98. GATE 2008 1 × 60
99. GATE 2007 1 × 60
100. GATE 2006 1 × 60
101. GATE 2005 1 × 60
102. GATE 2004 1 × 60
103. GATE 2003 1 × 40
104. GATE 2002 1 × 40
105. GATE 2001 1 × 40
106. GATE 2000 1 × 40
107. GATE 1999 1 × 40
108. GATE 1998 1 × 40
109. GATE 1997 1 × 40
110. GATE 1996 1 × 40
111. GATE 1995 1 × 40
112. GATE 1994 1 × 40
113. GATE 1993 1 × 40
114. GATE 1992 1 × 40
115. GATE 1991 1 × 40
Dedicated Freight Corridor Corporation of India Ltd.
116. DFCCIL Executive S &T 29.09.2021 1×96
117. DFCCIL Executive S &T 11.11.2018 1×96
118. DFCCIL Executive S &T 2016 1×80
Gujarat Public Service Commission
119. GPSC Asstt. Prof. 02.04.2017 1×200
120. GPSC Asstt. Prof. 18.03.2017 1×100
121. GPSC Lect. 16.10.2016 1×100
122. GPSC Asstt. Prof. 21.08.2016 1×100
Himachal Pradesh PSC
123. HPPSC Poly. Lect. 27.03.2016 1×80
124. HPPSC Asstt. Prof. 28.12.2014 1×80
KVS TGT (Work Experience)
125. KVS TGT (WE) 2018 1×100
126. KVS TGT (WE) 2017 1×150
127. KVS TGT (WE) 2016 1×150
128. KVS TGT (WE) 2014 1×150
9
Kerala PSC
129. Kerala PSC AE 06.04.2017 1×80
130. Kerala PSC Lect. (NCA) 04.07.2017 1×200
131. Kerala PSC Lect. 09.12.2016 1×80
132. Kerala Asstt. Prof. 06.05.2016 1×80
UPMRCL/LMRC/DMRC Asstt. Manager
133. UPMRCL AM 2021 1×90
134. UPMRCL AM (Operation) 20.01.2020 1×90
135. LMRC AM (S&T) 13.05.2018 1×75
136. DMRC AM (S&T) 2020 1×75
Madhya Pradesh PSC
137. MPPSC Forest Service Exam.-2014 2014 1×150
Maharashtra Public Service Commission
138. MPSC HOD Govt. Poly. 2013 1 × 80
Mizoram PSC
139. Mizoram PSC IOLM Paper- I 2018 1×100
140. Mizoram PSC IOLM Paper-II 2018 1×100
141. Mizoram PSC IOLM Paper-III 2018 1×100
142. Mizoram PSC Jr. Grade Paper-I 2018 1×50
143. Mizoram PSC Jr. Grade Paper-II 2018 1×50
144. Mizoram PSC Jr. Grade Paper-III 2018 1×50
145. Mizoram PSC Jr. Grade Paper-I 2015 1×50
146. Mizoram PSC Jr. Grade Paper-II 2015 1×50
147. Mizoram PSC Jr. Grade Paper-III 2015 1×50
148. Mizoram PSC AE/SDO Paper-I 2012 1×200
149. Mizoram PSC AE/SDO Paper-III 2012 1×150
150. Mizoram PSC IOLM Paper-I 2010 1×150
151. Mizoram PSC IOLM Paper-II 2010 1×150
Nagaland PSC
152. Nagaland PSC CTSE (Diploma), Paper-I 2018 1 × 200
153. Nagaland Psc CTSE (Diploma), Paper-II 2018 1 × 200
154. Nagaland PSC CTSE (Degree), Paper-I 2018 1 × 200
155. Nagaland PSC CTSE (Degree), Paper-II 2018 1 × 200
156. Nagaland PSC CTSE (Diploma), Paper-I 2017 1 × 200
157. Nagaland PSC CTSE (Diploma), Paper II 2017 1 × 200
162. Nagaland PSC CTSE (Degree) , Paper I 2015 1 × 200
Nuclear Power Corporation of India Limited
164. NPCIL ET 2015 1×90
NLC India Limited
165. NLC GET 24.11.2020 1×80
10
National Institute of Electronics & Information Technology
166. NIELIT Scientist-B 2017 1×60
167. NIELIT Scientist-B 2016 1×60
Odisha Public Service Commission
168. OPSC Poly. Lect. (Instrumentation & Control), Paper-I 2018 1 × 100
169. OPSC Poly. Lect. (Instrumentation & Control), Paper-II 2018 1 × 100
170. OPSC Poly. Lect. (Electronic Engineering), Paper-I 2018 1 × 100
171. OPSC Poly. Lect. (Electronic Engineering), Paper-II 2018 1 × 100
Punjab PSC
172. Punjab PSC Poly. Lect. 20.08.2017 1 × 100
Rajasthan Public Service Commission
173. RPSC ACF & FRO 23.02.2021 1 × 120
174. RPSC Vice Principal ITI/Suptdt. 2016 1 ×100
175. RPSC Lect. (Tech. Edu. Dept.) 10.01.2016 1 ×100
176. RPSC Lect. (Tech. Edu. Dept.) 2011 1 ×100
177. RPSC Vice Principal ITI/Suptdt. 05.11.2019 1 ×100
Railway Recruitment Board
178. RRB JE Shift-I 01.09.2019 1 × 100
179. RRB JE Shift-II 31.08.2019 1 × 100
180. RRB SSE Shift-I 01.09.2015 1×21
181. RRB SSE Shift-II 01.09.2015 1×22
182. RRB SSE Shift-III 01.09.2015 1×20
183. RRB SSE Shift-I 02.09.2015 1×20
184. RRB SSE Shift-II 02.09.2015 1×21
185. RRB SSE Shift-III 02.09.2015 1×22
186. RRB SSE Shift-I 03.09.2015 1×22
187. RRB SSE Shift-II 03.09.2015 1×21
188. RRB SSE Shift-III 03.09.2015 1×20
189. RRB SSE (Green) 21.12.2014 1×21
190. RRB SSE (RED) 21.12.2014 1×22
191. RRB SSE (yellow) 21.12.2014 1×20
Sikkim PSC
192. Sikkim PSC SI (Mains) 2018 1×50
Tamil Nadu Public Service Commission
193. TNPSC AE 2019 1 ×200
194. TNPSC AE 2018 1 ×200
195. TNPSC AE 2014 1 ×200
196. TNPSC AE 2013 1 ×200
197. TNPSC AE 2008 1 ×200
198. TANGEDCO AE 2018 1×60
199. TANGEDCO AE 2015 1×60
200. TRB Poly. Lect. 2012 1×150
201. TRB Poly. Lect. 2017 1×150
202. TRB Poly. Lect. 2021 1×150
Telangana PSC
203. TSGENCO AE 2015 1×80
204. TSPSC Manager (Engg.) 2015 1×150
205. TSTRANSCO AE 2018 1×80
206. TSPSC Manager (Engg.) in HMWSSB 12.11.2020 1×150
Total 23515
11
Trend Analysis of Previous Year Electronics &
Communication Engineering Exams Papers Through Pie
Chart and Bar Graph
12
01.
Electronic Devices and Circuits
(a) 226 meV (b) 174 meV
(i) Basic semiconductors Physics (c) 218 meV (d) 182 meV
GATE-2022
1. n-type silicon is obtained by doping silicon with Ans. (c) : According to questions
300 K is N 
(a) Germanium (b) Aluminium ( E C − E Fn )1 = kTln  C  = 200meV
(c) Boron (d) Phosphorus  N D1 
UPPSC Poly. Tech. Lect.-22.03.2022, Paper -I  N 
GATE-2003 ( E C − E Fn ) 2 = kTln  C 
Ans. (d) : Phosphorus (P), Arsenic (As), and Antimony  N D2 
−3
(Sb) is called pentavalent or n type semiconductor N D1 = 10 cm 16
impurity. An n-type semiconductor is created when pure N = 0.5 × 1016 cm −3

D2
semiconductor like Si and Ge are doped with
pentavalent element. N   N 
2. Doping of Boron in Silicon results in ( E C − E Fn )1 − ( EC − E Fn )2 = kTln  C  − kTln  C 
N
 D1   N D2 
(a) An intrinsic Si semiconductor
(b) A p - type extrinsic semiconductor N 
(c) An n-type extrinsic semiconductor 200meV − ( E C − E Fn ) 2 = kTln  D2 
(d) An intrinsic B semiconductor  N D1 
UPPSC ITI Principal/Asstt. Director-09.01.2022  1016 × 0.5 
TNTRB AE– 2017 200meV − ( E C − E Fn ) 2 = 0.026ln  16 
Ans. (b) : There are 4 valence electrons in silicon while  10 
3 valence electrons in boron. When silicon is doped 200meV − ( E C − E Fn ) 2 = 0.026 ln ( 0.5)
with boron, the three electrons of boron bonded with the 200meV − ( E − E ) = −0.01802 Volt
C Fn 2
three electrons of silicon and one valence electron of
silicon remains free. To bond this one free electron of 200meV − ( E C − E Fn ) 2 = −18.02 meV
silicon the neighbouring silicon atom is taken thus a ( E C − E Fn )2 = 200 meV + 18.02 meV
hole is created there i.e. the deficiency of one electron is
called as positive hole and this extra positive hole is ( E C − E Fn )2 = 218.02 meV
called as p-type extrinsic semiconductor. 5. Select the CORRECT statement(s) regarding
3. The value of thermal voltage at T = 27ºC is semiconductor devices.
approximately (a) Electrons and holes are of equal density in an
(a) 26 mV (b) 26µV intrinsic semiconductor at equilibrium.
(c) 2.6 mV (d) 260 µV (b) Collector region is generally more heavily
UPPSC ITI Principal/Asstt. Director-09.01.2022 doped than Base region in a BJT.
Mizoram PSC AE/SDO 2012-Paper-I (c) Total current is spatially constant in a two
Ans. (a) : As given that, terminal electronic device in dark under
T = 27 0 C steady state condition.
= 27 + 273 = 300K (d) Mobility of electrons always increases with
Thermal voltage (VT) = ? temperature in Silicon beyond 300 K.
T 300 GATE-2022
VT = = = 0.02586V = 25.86mV Ans. (a & c) : In intrinsic semiconductor at equilibrium
11600 11600
26mV n = p = ni
4. In a non-degenerate bulk semiconductor with • Collector region is generally moderate doped than
16 –3
electron density n = 10 cm , the value of EC – base region in a BJT.
EFn = 200 meV, where EC and EFn denote the • Total current is spatially constant in a two terminal
bottom of the conduction band energy and electronic device however individual currents vary
electron Fermi level energy, respectively. spatially under dark and steady state condition.
Assume thermal voltage as 26 meV and the 6. The total efficiency of an injection laser with a
intrinsic carrier concentration is 1010 cm–3. For GaAs active region is 18%. The voltage applied
n = 0.5 × 1016 cm–3, the closest approximation to the device is 2.5 V and the bandgap energy
of the value of (EC – EFn), among the given for GaAs is 1.43 eV. The external power
options, is ______. efficiency of the device is
Electronic Devices & Circuits 13 YCT
(a) 5% (b) 10% Ans. (b) : Silicon is not a conductor because silicon has
(c) 15% (d) 20% four valence electron, hence silicon is a semiconductor
IES-2021 material.
Ans.(b) : External power efficiency (ηex ) • Germanium has less resistance than silicon.
E  • Intrinsic silicon act as an insulator at room
= ηT  G  × 100% temperature because at room temperature no free
 V 
electron present in intrinsic silicon.
1.43
ηex = 0.18 × × 100 12. A silicon diode does not begin conducting until
2.5
__________of forward bias is applied.
ηex = 10.29%
(a) 0.5 V (b) 0.2 V
ηex ≅ 10% (c) 0.7 V (d) 0.3 V
7. Out of the following materials, which one will NLC GET -24.11.2020
have maximum Forbidden Band Gap? Ans. (c) : A silicon diode does not begin conducting
(a) Aluminium (Al) (b) Silicon (Si) until 0.7V of forward bias is applied.
(c) Germanium (Ge) (d) Silica (SiO2) A germanium diode typically begins to conduct electric
APPSC POLY. LECT. 14.03.2020 current when voltage properly applied across the diode
Ans. (d) : Forbidden band gap, also known a band reaches 0.3 volts. Silicon diodes require more voltage
refers to the energy difference (eV) between the top of to conduct current it takes 0.7 volts to creates a forward-
conduction band and the bottom of the valence band. In bias situation in a silicon diode.
materials silica (SiO2) has maximum forbidden band 13. A single crystal intrinsic semiconductor is at a
gap. temperature of 300 K with effective density of
8. The current flowing in a semiconductor due to states for holes twice that of electrons. The
the application of an external DC voltage is thermal voltage is 26 mV. The intrinsic Fermi
called : level is shifted from mid-band-gap energy level
(a) drift current (b) diffusion current by
(c) intrinsic current (d) extrinsic current (a) 13.45 meV (b) 18.02 meV
APPSC POLY. LECT. 14.03.2020 (c) 26.90 meV (d) 9.01 meV
Ans. (a) : Drift current is the electric current caused by GATE- 2020
particles getting pulled by an electric field.
Ans. (d) : Given that,
Drift current in a semiconductor due to the application
Thermal voltage (VT) = 26mV = 0.026V
of an external DC voltage.
• Hole is twice than electron so that we called the
9. In a semiconductor, the holes exist in the____
band. N
semiconductor is P-type , its means ⇒ N C = V
(a) conduction (b) valence 2
(c) forbidden (d) fermi EC + EV kT  N C 
APPSC POLY. LECT. 14.03.2020 − E Fi = ln  
KVS TGT (WE)- 2018 2 2  NV 
Ans. (b) : Semiconductors are materials which bare a  NV 
conductivity between conductors and non conductors. 0.026  2 
The holes exist in the valence band. = ln  
2  N V 
10. When silicon is doped with arsenic, each
arsenic atom will give the crystal _________.  
(a) Two holes (b) Two electrons 1
= 0.013ln  
(c) One electron (d) One hole 2
NLC GET -24.11.2020 = 0.013 ln(0.5)
Ans. (c) : When silicon is doped with arsenic each
= –9.01meV
arsenic (As) atom will give the crystal one electron.
where, ln(0.5) = −0.6931
11. Determine whether each statement is true or
false. 14. The Ohm's law for conduction in metals is
(i) Silicon is a conductor (a) J = σE (b) J = E/σ
(ii) Silicon has four valence electrons (c) J ∝ σE (d) J ∝ E/σ
(iii) Germanium has less resistance than silicon IES-1999
(iv) Intrinsic silicon acts as an insulator at room Ans. (a) : Ohm's Law- A current density J and an
temperature electric field E are established in an object that has a
(a) (i) True, (ii) True, (iii) True and (d) True potential difference VD across it in some materials the
(b) (i) False, (ii) True, (iii) True and (d) True current density is directly proportional to the electric
(c) (i) True, (ii) True, (iii) True and (d) False field, these materials are known as ohmic material is.
(d) (i) False, (ii) True, (iii) False and (d) True
NLC GET -24.11.2020 Ohm's law: J = σ E

15. An n-type silicon sample of 10–3 m length and (a) NA–ND (b) NA+ND
10–10 m2 cross sectional area has an impurity NA ND
concentration of 5 × 1020 atom/m3. If mobility (c) (d) ni
2 n i2
of majority carries is 0.125 m /v-sec, then the
resistance of the sample will be _____. KVS TGT (WE)- 2017
(a) 4 MΩ (b) 1 MΩ Nagaland PSC CTSE (Degree)-2016, Paper-I
(c) 25 kΩ (d) 5 kΩ Ans. (a) : For intrinsic S.C, - no of e = n 0
UPPCL AE-30.03.2022 no of hole = P0
Ans. (b) : Given, l = 10−3 m after adding ND no of donors, The S.C becomes n–type.
no of e = n 0 + N D
A = 10−10 m 2
n = 5 × 1020 atom / m 2 no of holes = p0
µ = 0.125m / V − sec
2 Now after adding NA no of acceptor to n-type S.C.
no of holes = p0 + NA ....(i)
l 1 l 1 l no of es = n0 +ND ....(ii)
R =ρ = × = ×
A σ A nµe A from (i) & (ii) equations.
10−3 Case-I when NA = ND
R= −19 −10 Then → no of holes = no of electron
1.6 × 10 × 0.125 × 10 × 5 × 10 20
Types of S.C. is intrinsic only.
R = 1MΩ Case-II NA> ND then
16. A semiconductor material is doped with donor Then→ no of holes > no of electron
type impurities with 1015 atoms/cm3. If the So → P-type SC. It will become with-
10 –3
intrinsic carrier concentration is 10 cm , then - effective holes = NA–ND
the concentration of holes in the doped
–3
semiconductors in equilibrium (in cm ) will be: 19. A silicon sample is uniformly doped with 1016
(a) 108 (b) 105 phosphorus atoms/cm3 and 2×1016 boron
(c) 1010 (d) 1012 atoms/cm3. If all the dopants are fully ionized,
UPPCL AE-30.03.2022 the material is
15 3 (a) n-type with carrier concentration of 1016/ cm3
Ans. (b) donor impurity (ND) = 10 atoms/cm (b) p-type with carrier concentration of 1016/cm3
Intrinsic concentration (ni) = 1010cm–3 (c) p-type with carrier of 2×1016 /cm3
NA = ? (d) n-type with a carrier concentration of 2×1016
we know the mass action Law /cm3
ND×NA = (ni)2 GATE-1991
∴ 1015×NA = (1010)2
Ans. (b) : We know that,
1020 Vd = µE
∴ NA = 15 = 105 cm −3
10 µ = constant
17. Due to illumination by light, the electron and When, E < 103 V / cm
hole concentrations in a heavily doped N type
semiconductor increases by ∆n and µ ∝ 1 when 103 < E < 104 V / cm
∆p respectively if ni is the intrinsic E
concentration then, 1
µ ∝ when E > 104 V / cm
(a) ∆n < ∆p (b) ∆n > ∆p E
(c) ∆n = ∆p (d) ∆n × ∆p = n i2 ∴ When E increase mobility decrease.
Given that,
Nagaland PSC CTSE (Degree)-2015, Paper-I P-type carrier concentration- 2×1016 /cm3
Ans. (c) : The light results in breaking of covalent N-type carrier concentration- 1016/cm3
bonds. Thus, ∆n = ∆p ND = 1016/cm3, NA = 2×1016/cm3
n 2
Q N A >> N D
N-type ⇒ n n ≅ N D and p n ≅ i
ND So, resultant
after light illumination, = NA − ND
Let ∆ number of covalent bonds are broken = 2 × 1016 − 1016
2
n = 1016 / cm 3
nn = ND +∆n and p n = i + ∆p
ND 20. A semi conductor is irradiated with light such
∆n = ∆p = no of covalent bond that carriers are uniformly generated
∆n = ∆p ⇒ No. of electron hole pair. throughout its volume. The semiconductor is n-
type with ND=1019/cm3. If the excess electron
18. The concentration of ionized acceptors and
concentration in the steady state is
donors in a semi conductor are NA, ND
respectively. If NA>ND and ni is the intrinsic ∆n = 1015 /cm 3 and if τ p = 10µsec. (minority
concentration, the position of the Fermi level carrier life time) the generation rate due to
with respect to the intrinsic level depends on irradiation
(a) is 1020 e-h pairs/cm3/s Where,
(b) is 1024 e-h pairs/cm3/s Vd - Drift velocity
(c) is 1010 e-h pairs/cm3/s µ - mobility
(d) cannot be determined, the given data is E - Applied electric field.
insufficient In the above graph
GATE-1992 Q For smaller electric field applied, mobility of charge
Ans. (a) : Given, carrier will remain almost constant and for smaller
∆n =1015/cm3, τ p = 10 µsec. electric field applied, drift velocity (Vd) increases
Under steady state generation rate = Recombination rate linearly with electric field.
∆n When we increase electric field (very large) mobility of
G' = R' = charge carrier will be decreases and the drift velocity
τP gradually saturates at higher values of electric field.
Where → ∆n is a electron concentration 22. The probability that an electron in a metal
τP → minority carrier life times occupies the Fermi level, at any temperature.
∆n 1015 (T > 0K)
G' = R' = = (a) 0 (b) 1
τP 10µ sec
(c) 0.5 (d) 1.0
1015 DFCCIL Executive (S&T) 11.11.2018, 4:30 to 6:30PM
G' = = 1020
10 × 10−6 GATE-1995
Ans. (c) : In the band gap structure theory, used in
G ' = 10 e-h pairs/cm /sec
20 3
solid state physics to analyze the energy levels in a
21. The drift velocity of electrons, in silicon solid, the fermi level can be considered to be a
(a) is proportional to the electric field for all hypothetical energy level of an electron , such that at
values of electric field thermodynamic equilibrium this energy level would
(b) is independent of the electric field. have a 50% probability of being occupied at any given
(c) increases at low values of electric field and time.
decreases at high values of electric field 23. A small concentration of minority carriers is
exhibiting negative differential resistance. injected into a homogeneous semiconductor
(d) increases linearly with electric field at low crystal at one point. An electric field of 10 V/cm
values of electric field and gradually saturates is applied across the crystal and this moves the
at higher values of electric field. minority carries a distance of 1 cm in 20 µsec .
GATE-1995
Ans. (d) : The mobility (in cm2/V-sec) will be
(a) 1,000 (b) 2,000
(c) 5,000 (d) 500,000
GATE-1995
Ans. (c) : Given that
E = 10V/cm, d = 1cm, t = 20µ sec
We know that →
d
Vd =
t
Where,
Vd → drift velocity
d → Distance
t → time
Now
1cm
Vd =
20µ sec
1
Vd =
20 ×10−6
106
Vd = cm / sec
20
Q Now, we know that
Vd ∝ E
Vd = µE
Vd ∝ E
V
Vd = µE µ= d ...(i)
E

Now, put the value of E & Vd in equation (i), (c) n = 2.25 × 1015 , p = 1.0 ×105 / cm3
106 (d) n = 1.5 ×1010 , p = 1.5 × 1010 / cm3
µ = 20 Nagaland PSC CTSE (Diploma)-2017, Paper-I
10 GATE-2014, 1997, 1995
106 Ans. (c) : Given that,
µ= Intrinsic carrier concentration (ni)
20 × 10
(n i ) = 1.5 × 1010 / cm3
cm 2 Electron density = ND = n
µ = 5000
V.sec (n) = 2.25 ×1015 atom/cm3
q We know that -
24. The units of are ni2
KT P = ...(i)
(a) V (b) V–1 ND
(c) J (d) J/K Put the value of (ni) & (n) in equation (i).
Nagaland PSC CTSE (Degree)-2015, Paper-I 1.5 ×1010 × 1.5 × 1010
GATE-1998, 1997 P=
2.25 × 1015
Ans. (b) : Diode equation
2.25 × 1020
 ηVKT
Dq
 P=
I D = Is  e − 1 ……………(i) 2.25 × 1015
  20
×10–15
  P = 10
Where, P = 105 atoms / cm3
I D − Total diode current
26. The electron concentration in a sample of non-
Is − Reverse saturation current uniformly doped n-type silicon at 300 K varies
VD- Applied voltage across the diode linearly from 1017/cm3 at x= 0 to 6× 1016/cm3 at
η − ideality factor x= 2 µm. Assume a situation that electrons are
VT- Thermal voltage supplied to keep this concentration gradient
From equation (i) constant with time. If electronic charge is
1.6×10–19 Coulomb and the diffusion constant
 ηVVD

I D = Is  e T − 1  Dn = 35cm2/s, the current density in the silicon,
  if no electric field is present is
 
(a) zero (b) 120 A/cm2
KT 2
(d) –1120 A/cm2
∴ VT = (c) +1120 A/cm
q GATE-1997
−23
K = 1.38 × 10 J / K Ans. (d) : Total current density (j n )
q = 1.6×10–19C dn
T = Room temperature ( jn ) = nqµ n E + Dn .q.
dx
Thermal voltage is directly proportional to temperature.
Diffusion current density where E = 0
VT ∝ Tempreture
dn
KT jn (diff ) = D n q
Now→ VT = dx
q
Where → Dn→electron diffusion constant
Where, q → charge of charge carrier concentration
K → Boltzmann's constant
dn
q → charge (e − ) → Concentration gradient
dx
T→ Room Temperature We know that
Q Now
dn n1 − n 2
q 1 =
= dx x1 − x 2
KT V
dn 6 × 1016 − 1017
q −1
=
=V dx 2 × 10−4 − 0
KT
dn 6 × 1016 − 10 ×1016
25. The intrinsic carrier density at 300 K is =
10 3
1.5×10 /cm , in silicon for n-type silicon doped dx 2 ×10−4
dn 10 ( 6 − 10 )
16
to 2.25×1015 atoms/cm3, the equilibrium
=
electron and hole densities are dx 2 ×10−4
(a) n = 1.5 × 1015 , p = 1.5 ×1010 / cm3 dn −4
= × 1016 × 104
(b) n = 1.5 ×1010 , p = 2.25 × 1015 / cm3 dx 2
dn Ans. (b) : The concentration of minority carriers in an
= −2 × 10 20 extrinsic semiconductor under equilibrium is inversely
dx proportional to the doping concentration.
Now, According to mass action law-
dn n.p. = n i2
jn = D n q
dx n = concentration of electrons
jn = (35) (1.6×10–19) (–2×1020) p = concentration of holes
jn = –70 ×1.6 ×101 ni = intrinsic carriers
jn = −1120 A / cm 2 In n - type semiconductor
minority Holes concentration
27. An n-type silicon bar 0.1 cm long and 100 µm 2 p = n i2 /ND
in cross-sectional area has a majority carrier ND = concentration of donor impurity
concentration of 5×1020/m3 and the carrier 29. The band-gap of silicon at 300 K is
mobility is 0.13 m2/V-s at 300 K. If the charge (a) 1.36 eV (b) 1.10 eV
of an electron is 1.6×10–19 Coulomb, then the (c) 0.80 eV (d) 0.67 eV
resistance of the bar is GATE-2003
(a) 106 Ω (b) 10 4 Ω Ans. (b)
(c) 10 Ω
–1
(d) 10 –4 Ω 1
GATE-1997 ↑↓ E g ∝
Ans. (a) : Given that, Temp↑↓
q = 1.6 ×10–19 Coulomb, A = 100µm2 = 100×10–12 m2 Truth table of energy gap
µn = 0.13 m2/V-sec , n = 5×1020/m3 Energy Gap Si Ge GaAs
−3
l = 0.1cm = 10 m With temp
As we know that, Eg (0º K) 1.21 eV 0.785 eV 1.52 eV
Conductivity (σ) = nqµ n Eg (300ºK) 1.1 eV 0.72 eV 1.43 eV
30. The intrinsic carrier concentration of silicon
1 sample at 300 K is 1.5 ×1016/m3. If after doping,
Resistivity (ρ) = the number of majority carriers is 5×1020/m3,
conductivity (σ)
the minority carrier density is
ρl (a) 4.50×1011/m3 (b) 3.33 ×104/m3
Resistance (R) =
A (c) 5.00×1020/m3 (d) 3.00×10–5/m3
1 l GATE-2003
R =  × Ans. (a) : Given that,
σ A
Intrinsic concentration (ni) = 1.5 ×1016/m3
l majority carrier (n) = 5×1020/m3
R=
nqµ n A We know that
Now, n2
Put the value of l, n, q, µ n & A n i 2 = np , p= i
n
10−3 Putting the value-
R= 1.5 ×1016 × 1.5 × 1016
(5 ×1020 ) × (1.6 ×10−19 ) × (0.13) × (100 × 10−12 ) p=
10−3 × 1011 5 ×1020
R= 2.25 × 1032 × 10−20
104 p=
R = 0.0096 ×108 5
R = 0.96 ×106 p = 0.45 ×1012
R 106 p = 4.5 × 1011 / m3
28. The concentration of minority carriers in an 31. The resistivity of a uniformly doped n-type
extrinsic semiconductor under equilibrium is silicon sample is 0.5Ω – cm. If the electron
(a) directly proportional to the doping
concentration mobility ( µ n ) is 1250 cm2/V-sec and the charge
(b) inversely proportional to the doping of an electron is 1.6×10–19 Coulomb, the donor
concentrations impurity concentration (ND) in the sample is
(c) directly proportional to the intrinsic (a) 2×1016/cm3 (b) 1×1016/cm3
15 3
concentration (c) 2.5×10 /cm (d) 2×1015/cm3
(d) inversely proportional to the intrinsic GATE-2004
concentration Ans. (b) : Given that,
UPPSC ITI Principal/Asstt. Director-09.01.2022 Electron mobility (µn) = 1250cm 2 / V − s
TANGEDCO AE-2018
Nagaland PSC CTSE (Degree)-2015, Paper-I Charge of electron (q) = 1.6×10–19 Coulomb.
GATE-2006 Resistivity (ρ) = 0.5Ω cm
We know that, 34. The primary reason for the widespread use of
1 silicon in semiconductor device technology is
(Resistivity) ρ = (a) abundance of silicon on the surface of the Earth.
σ(Conductivity)
(b) larger bandgap of Silicon in comparison to
Q σ = N D qµ n Ω / cm Germanium
(c) favorable properties of silicon-dioxide (SiO2)
1 1
ρ= , ND = (d) lower melting point
N D qµ n ρqµ n Nagaland PSC CTSE (Degree)-2015, Paper-I
1 GATE-2005
ND = Ans. (a) : The primary reason for the widespread use of
0.5 ×1.60 ×10−19 × 1250
silicon in semiconductor device technology is
N D = 1016 / cm3 abundance of silicon on the surface of the Earth.
32. The longest wavelength that can be absorbed 35. A silicon sample A is doped with 1018
by silicon, which has the bandgap of 1.12 eV, is atoms/cm3 of Boron. Another sample B of
1.1µm . If the longest wavelength that can be identical dimensions is doped with 1018
absorbed by another material is 0.87 µm , then atoms/cm3 of Phosphorus. The ratio of electron
to hole mobility is 3. The ratio of conductivity
the band gap of this material is
of the sample A to B is
(a) 1.416 eV (b) 0.886 eV
(a) 3 (b) 1/3 (c) 2/3 (d) 3/2
(c) 0. 854 eV (d) 0.706 eV
IES-2016
BPSC Asst. Prof. - 12.04.2022
GATE-2005
GATE-2004
Ans. (a) : Given that, Ans. (b) : For n-type (σ n ) = n.q.µ n Sample A→ -type
wave length (λ) = 0.87µm For p-type (σ p ) = p.q.µ p Sample B → types
Eg = h.v Now,
c σ n nµ n
Eg = h. =
λ(µm) σ p pµ p
1.24 σp µ p 1
Eg = σB σn σ
0.87 = ⇒ A = = =
σA σ p σB σn µ n 3
E g = 1.425eV
σA 1
33. The neutral base width of a bipolar transistor, =
σB 3
biased in the active region, is 0.5 µm. The
maximum electron concentration and the 36. Under low level injection assumption, the
diffusion constant in the base are injected minority carrier current for an
1014 /cm 3and Dn = 25cm 2 /sec respectively. extrinsic semiconductor is essentially the
(a) diffusion current (b) drift current
Assuming negligible recombination in the base, (c) recombination current (d) induced current
the collector current density is (the electron GATE-2006
charge is 1.6 ×10 –19 Coulomb) Ans. (a) : The current is by diffusion as there is
(a) 800 A/cm2 (b) 8 A/cm2 concentration gradient due to low-level injection.
2
(c) 200 A/cm (d) 2 A/cm2
37. The majority carriers in an n-type
GATE-2004
semiconductor have an average drift velocity v
Ans. (b) : Given that, in a direction perpendicular to a uniform
Dn= 25 cm2/sec, q = 1.6 ×10–19C magnetic field B. The electric field E induced
 dn  1014 due to Hall effect acts in the direction
Concentration gradient   = −4
 dx  0.5 × 10 (a) v×B (b) B×v
We know that, (c) along v (d) opposite to v
GATE-2006
dn
J C = qD n Ans. (b) : The given semiconductor of n-type and the
dx average drift velocity of carriers is Vd
1014 Force (F) = qE ............(i)
J C = 1.6 × 10−19 × 25 × The force for an n-type semiconductor is,
0.5 × 10−4
F = −q(Vd × B) = q(B × Vd ) .........(ii)
80
J C = 80 ×10 −1 JC = From equation (i) and (ii)
10 qE = q(B×Vd)
J C = 8 A / cm 2 E = B × Vd

38. A heavily doped n-typed semiconductor has the
n2
following data: n= i
Hole-electron mobility ratio: 0.4 p
Doping concentration : 4.2× 108 atoms/m3
n2
Intrinsic concentration : 1.5 ×104 atoms/m3 n= i
The ratio of conductance of the n-type NA
semiconductor to that of the intrinsic Where p = NA
semiconductor of same material and at the NA is a acceptor concentration
same temperature is given by 40. Which of the following is true?
(a) 0.00005 (b) 2,000 (a) A silicon wafer heavily doped with boron is a
(c) 10,000 (d) 20,000 p+ substrate
GATE-2006 (b) A silicon wafer lightly doped with boron is a
+
Ans. (d) : Given that p substrate
Doping concentration (n) = 4.2×108 atoms/m3 (c) A silicon wafer heavily doped with arsenic is
Intrinsic concentration (ni)= 1.5×104 atoms/m3 a p+ substrate
(d) A silicon wafer lightly doped with arsenic is a
 µp  p+ substrate
Hole-electron mobility ratio   = 0.4
GATE-2008
 µn 
Ans. (a) → A silicon wafer heavily doped with boron is
For n-type semiconductor ( σ n ) = nqµ n a P+ substrate.
For intrinsic semiconductor (δi) = n i q(µ n + µ p ) → In electronics a wafer (also called a slice or
substrate) is a thin slice of semiconductor such as a
σn nqµ n nµ n crystalline silicon (C-Si), used for the fabrication of
= =
σi n i q(µ n + µ p )  µp  integrated circuits and, in photovoltaics, to manufacture
n i µ n 1 +  solar cells. The wafer serves as the substrate for
 µn  microelectronic devices built in and upon the wafer.
σn n 41. Silicon is doped with boron to a concentration
=
σi  µp  of 4×1017 atoms/cm3. Assume the intrinsic
n i 1 +  carrier concentration of silicon to be
 µn  1.5 ×1010 /cm 3 and the value of kT/q to be 25mV
σn 4.2 × 10 8
at 300K. Compared to undoped silicon, the
= Fermi level of doped silicon
σi 1.5 × 10 4 (1 + 0.4 )
(a) goes down by 0.13 eV
σn 4.2 × 108 (b) goes up by 0.13 eV
= (c) goes down by 0.427 eV
σi 1.5 × 1.4 ×104
(d) goes up by 0.427 eV
σn 42 × 108 GATE-2008
=
σi 21.0 × 10 4 Ans. (c) : Given that
NA = 4×1017 atoms/cm3
σn ni = 1.5 ×1010/cm3
= 2 × 10 4
σi kT
= 25mV = 25 × 10−3
σn q
= 20, 000 Since it is doped with acceptor impurity.
σi Fermi level will shift down.
39. The electron and hole concentrations in an kT N A
EF − EV = ln
intrinsic semiconductor are ni per cm3 at 300 q ni
K. Now, if acceptor impurities are introduced
with a concentration of NA per cm3 (where NA 4 × 1017
= 25 ×10−3 ln
>> ni) the electron concentration per cm3 at 300 1.5 × 1010
−3
K will be = 25 × 10 ln(2.667 ×107 )
(a) ni (b) ni+NA = 25×10–3 ×17.099
n i2 25 × 17.099
(c) NA–ni (d) =
NA 1000
= 0.427 eV
GATE-2007
42. In an n-type silicon crystal at room
Ans. (d) : Mass action law
temperature, which of the following can have a
→ In extrinsic semiconductor under thermal
concentration of 4 ×1019 cm –3?
equilibrium product of hole concentration is always
(a) Silicon atoms (b) Holes
constant & is equal to square of intrinsic concentration (c) Dopant atoms (d) Valence electrons
n.p = n i2 GATE-2009

Ans. (c) : Given that So, I depends upon carrier concentration and electric
In an N-type silicon crystal at room temperature. field.
n ND Where,
J = Current density
Where → ND is doping concentration n = No of e– concentration
We know that → q = Magnitude of charge
By mass action law µ = mobility
n.p = ni2 E = Applied electric field
n2 45. The doping concentration on the p-side and n-
p= i
n side of a silicon diode are 1×1016 cm –3 , and
1×1017cm-3 respectively. A forward bias of 0.3V
p=
(1.5 ×10 )
10 2
is applied to the diode. At T=300 K, the
4 × 1019 intrinsic carrier concentration of silicon
2.25 × 1020 kT
p= n i = 1.5 ×1010 cm –3 and = 26mV. The electron
4 ×1019 q
p = 0.5625×10 concentration at the edge of the depletion
Q p = 5.625 cm–3 region on the p-side is
n >> p (a) 2.3 × 109 cm –3 (b) 1 × 1016 cm –3
(c) 1 × 10 cm
17 –3
(d) 2.25 × 106 cm –3
So, in an n-type silicon crystal at room temperature
GATE-2014, Set-I
dopant atom can have a concentration of 4 × 1019 cm −3 .
Ans. (a) : Given that,
43. The ratio of the mobility to the diffusion NA = 1×1016/cm3
coefficient in a semiconductor has the unit ND = 1×1017/cm3
(a) V –1 (b) cm.V –1 ni = 1.5 ×1010/cm3
(c) V.cm –1 (d) V.s Vf = 0.3V
GATE-2009 kT
= 26mV = 0.026 V
Ans. (a) : According to Einstein's Relation- q
At constant temperature, ratio of diffusion constant The electron concentration at the edge of the depletion
to mobility is constant and it is equal to thermal region on the p-side is given by
voltage.
n p = n p0 e(qV / kT) ......(i)
It gives the relationship between diffusion constant,
mobility & thermal voltage. Using mass action law-
D Dn n2
= VT = VT → For electron n p0 = i
µ µn NA
(1.5 × 1010 ) 2
µ 1 DP n p0 =
= = VT → For hole 1×1016
D VT µP
n p0 = 2.25 × 104 / cm3
µ
= VT−1 Now, putting the value in equation (i)
D  0.3 
 
Where → D = Diffusion constant n p = (2.25 × 104 )e 0.026 
VT = Thermal voltage
µ = mobility n p = (2.25 × 104 ) × 1.025 × 105
44. Drift current in semiconductors depends upon n p = 2.25 × 1.025 × 109
(a) only the electric field
(b) only the carrier concentration gradient n p = 2.306 × 109 / cm3
(c) both the electric field and the carrier
concentration 46. When a silicon diode having a doping
(d) Neither the electric field nor the carrier concentration of N A = 9 ×1016 cm –3 on p-side
concentration gradient and N D = 1×1016 cm –3 on n-side is reverse
GATE-2011 biased, the total depletion width is found to be
Ans. (c) : Drift current in semiconductor depends upon 3 µm . Given that the permittivity of silicon is
both the electric field and the carrier concentration.
1.04 ×10 –12 F/cm , the depletion width on the p-
J = n.q.µ.E side and the maximum electric field in the
We, know that depletion region, respectively, are
I = J.A (a) 2.7µm and 2.3 ×105 V / cm
I = nqµE.A (b) 0.3µm and 4.15 ×105 V / cm

(c) 0.3µm and 0.42 ×105 V / cm (a) 0.42µm < λ C < 0.87µm
(d) 2.1µm and 0.42 ×10 V / cm
5 (b) 0.87µm < λ C < 1.42µm
GATE-2014, Set-II (c) 1.42µm < λ C < 1.62µm
Ans. (b) : As we know that (d) 1.62µm < λ C < 6.62µm
W P N A = W NN D GATE-2014, Set-IV
Where,
NA → Acceptor concentration Eg = 1.42eV
ND → Donor concentration We know that
WP → Width of p region
1.24
WN → Width of n region λC ≤ µm
Let, E g ( eV )
WN = x. µm 1.24
then WP = (3–x)µm λc ≤ (µm)
Eg
(3–x)×9×1016 = x ×1016
27–9x = x 1.24
10x = 27 λc ≤ (µm)
1.42
x = 2.7 λ c ≤ 0.87(µm)
then,
WN = 2.7µm 49. A small percentage of impurity is added to an
intrinsic semiconductor at 300 K. Which one of
WP = 0.3µm the following statements is true for the energy
qWN N D band diagram shown in the following figure?
Egmax =
ε
1.6 × 10−19 × 2.7 × 10−4 × 1× 1016
Egmax =
1.04 ×10−12
4.32 × 105
Egmax =
1.04
E gmax = 4.15 × 105 V / cm
(a) Intrinsic semiconductor doped with
47. A thin P-type silicon sample is uniformly pentavalent atoms to form n-type
illuminated with light which generates excess semiconductor
carriers. The recombination rate is directly (b) Intrinsic semiconductor doped with trivalent
proportional to atoms to form n-type semiconductor
(a) the minority carrier mobility (c) Intrinsic semiconductor doped with
(b) the minority carrier recombination lifetime pentavalent atoms to form p-type
(c) the majority carrier concentration semiconductor
(d) the excess minority carrier concentration (d) Intrinsic semiconductor doped with trivalent
APGENCO AE- 23.04.2017 atoms to form p-type semiconductor
GATE-2014, Set-III GATE-2016, Set-I
Ans. (d) : Ans. (a) :
• A thin P-type silicon sample is uniformly illuminated • Here fermi energy level is lying just below the
with light. Which generates excess carriers. The conduction band which show that it is n-type
recombination rate is directly proportional to " the semiconductor doped, i.e. an intrinsic semiconductor
excess minority carrier concentration". is doped with pentavalent impurity to form n-type.
• When a p-n junction is forward biased, minority • All these fifth electron will occupy a new energy
carriers are injected in to the semiconductors on the level just below the conduction band.
two sides of the junction. • At 00K the 5th e of pentavalent impurity will be at
Here δn is the excess minority electron concentration on donor energy level.
the p-side of the junction and δP is the excess minority • Intrinsic and extrinsic semiconductor 00K at
hole concentration on the n-side of the junction. temperature behaves as a Insulator.
48. At T=300 K, the band gap and the intrinsic 50. Consider a silicon sample at T=300 K, with a
carrier concentration of GaAs are 1.42 eV and uniform donor density Nd=5×1016 cm–3
106 cm–3, respectively. In order to generate illuminated uniformly such that the optical
electron hole pairs in GaAs, which one of the generation rate is Gopt=1.5×1020 cm–3 s–1
wavelength ( λ C ) ranges of incident radiation, is throughout the sample. The incident radiation is
most suitable? (Given that: Plank's constant is turned off at t=0. Assume low- level injection to
6.62 ×10–34 J-s, velocity of light is 3×1010 cm/s be valid and ignore surface effects. The carrier
and charge of electron is 1.6×10–19 C) lifetimes are τ p0 = 0.1µs and τ n0 = 0.5µs.

53. The type of lasers that use organic dyes
enclosed in glass tube for an active medium is
(a) plasma lasers (b) liquid lasers
(c) ruby lasers (d) neon lasers
TSGENCO AE-2015
Ans. (b) : Liquid lasers are used in organic dyes
The hole concentration at t=0 and the hole enclosed in glass tube for an active medium. Dyes lasers
concentration at t=0.3 µs , respectively, are can be used to study the absorption and emission
spectrum of various materials.
(a) 1.5 × 1013 cm –3and 7.47 × 1011 cm –3
54. Measurement of hall coefficient in a
(b) 1.5 ×1013 cm –3and8.23 ×1011 cm –3 semiconductor provides information about
(c) 7.5 × 1013 cm –3 and 3.73 × 1011 cm –3 (a) sign and mass of charge carriers
(b) sign of charge carriers alone
(d) 7.5 × 1013 cm –3and 4.12 × 1011 cm –3 (c) mass and concentration of charge carriers
GATE-2016, Set-I (d) sign and concentration of charge carriers
Ans. (a) : Given that, Punjab PSC Poly. Lect. 20.08.2017
Donor density (ND) = 5×1016 /cm3 Ans. (d) : Hall voltage, VH =
IB
Optical generation rate (Gopt) = 1.5 ×1020/cm3-s W
Carrier life times (τ p0 ) = 0.1µ sec 1 VH W
Hall coefficient RH = =
Carrier life times ( τn 0 ) = 0.5µ sec δ IB
• It determines the sign and concentration of charge
NA carriers.
(i) Gopt (R) =
τP 55. Consider the following statements in a
NA = 1.5 × 1020 × 0.1× 10 −6 semiconductor crystal
1. As temperature increases lattice scattering
= 1.5 × 1013 / cm 3 increases.
 −t 
  2. Lattice Scattering is directly proportional to
 τP 
(ii) Pt = P0 .e Doping levels.
 −0.3×10−6  3. As temperature increases mobility due to
 
13  0.1×10  ionized impurity scattering increases.
−6
Pt = 1.5 × 10 e
4. As doping increases mobility due to ionized
Pt = 7.47 × 1011 cm −3 scattering decreases scattering events
decreases.
51. A bar of Gallium Arsenide (GaAs) is doped Which of the following statements are correct?
with Silicon such that the Silicon atoms occupy (a) 1, 2 and 4 (b) 2 and 4
Gallium and Arsenic sites in the GaAs crystal. (c) 1, 2 and 3 (d) 1 and 3
Which one of the following statements is true? Punjab PSC Poly. Lect. 20.08.2017
(a) Silicon atoms act as p-type dopants in Arsenic Ans. (d) :
sites and n-type dopants in Gallium sites. • As temperature increases, phonon concentration,
(b) Silicon atoms act as n-type dopants in Arsenic increases, Lattice scattering increases.
sites and p-type dopants in Gallium sites. • Lattice scattering inversely proportional as to doping.
(c) Silicon atoms act as p-type dopants in Arsenic • As temperature increases mobility due to ionized
as well as Gallium sites. scattering increases.
(d) Silicon atoms act as n-type dopants in Arsenic • As doping increases mobility due to ionized
as well as Gallium sites. scattering increases because scattering event increases.
GATE-2017, Set-I 56. Which among the following material is used for
Ans. (a) : Silicon (Si) is IVth group element, so it acts LED
like P-type dopant in Vth group sites (N, P, As, Sb, Bi) (a) Si (b) Ge
and it is like a n-type dopant like in IIIrd Group sites (B, (c) C (d) GaAs
Al, Ga, In, etc). Punjab PSC Poly. Lect. 20.08.2017
52. Which one of the following light sensors Ans. (d) :
produces largest output current? GaAs is used for making as LED because GaAs
(a) PIN photodiode devices generate less noises than other
(b) Photovoltaic diode semiconductor materials.
GaAs is direct energy band gap semiconductor
(c) Avalanche Photodiode
material.
(d) Zener diode
57. Doping materials are called impurities because
TSGENCO AE-2015
they
Ans. (b) : A photo-voltaic diode produce largest output (a) change the temperature of the material
current from light sensors. Hence it is used in photo (b) alter the crystal structure of the pure
voltaic cells. semiconductor
(c) change the chemical properties of Ans. (b) : At room temperature (300K or 27ºC)
semiconductors Germanium has greater value of intrinsic concentration
(d) decrease the number of charge carriers than silicon
TNPSC AE-2019 i.e Si = 1.5×1010cc
TSPSC Manager (Engg.) - 2015 This is because the energy band gap of Ge (0.72) is less
Ans. (b) : Doping materials are called impurities than that of silicon (1.1eV) at room temperature At
because they alter the crystal structures of pure room temperature the energy band gap of silicon is
semiconductors. When a pentavalent impurity, like higher than germanium. So Germanium having a higher
arsenic is added to germanium, it will form covalent conductivity than silicon. Silicon devices can be
bonds with the germanium atoms. employed for a higher temperature limit (190ºC to
58. An intrinsic semiconductor at absolute zero 200ºC ) as compared to germanium devices (80ºC to
temperature 100ºC). i.e. silicon has a higher resistivity.
(a) has large number of holes ∴ Statement 1, 2, 3 are correct.
(b) has a large number of electrons
(c) behaves likes an insulator 62. A sample of germanium is made p-type by
(d) behaves like a metallic conductor addition of indium at the rate of one indium
TSPSC Manager (Engg.) - 2015 atom for every 2.5 × 108 germanium atoms.
Ans. (c) : An intrinsic semiconductor at 0º K has Given, ni = 2.5 × 1019/ m3 at 300 K and the
electron only in valence band. Forbidden gap-3eV as a number of germanium atoms per m3 = 4.4 ×
result, electrons do not have sufficient energy to excite to 1028. What is the value of np?
go to conduction band since there are no electrons in the (a) 3.55 × 1018/m3 (b) 3.76 × 1018/m3
18 3
conduction band so it behaves as an insulator at 0º K. (c) 7.87 × 10 /m (d) 9.94 × 1018/m3
59. Which is not an example of convection IES-2018
current? Ans. (a) : Given,
(a) A moving charged belt Germanium atoms per m3 = 4.4 ×1028
(b) Electronic movement in a vacuum tube indium atom for every germanium atoms is 2.5 ×108
(c) An electron beam in a television tube then P-type impurities of germanium atom
(d) Electric current flowing in a copper wire 4.4 × 1028
TSPSC Manager (Engg.) - 2015 nA =
2.5 × 108
Ans. (d) : Electric current flowing through a copper
nA = 1.76×1020atom
wire is conduction current.
ni = 2.5 ×1019/m3
60. Which of the following is obtained by drawing by using mass action law-
a single crystal from a melt of germanium nA. nP = ni2
whose type is changed during the drawing
process by adding first p-type and then n-type n2
nP = i
impurities? nA
1. Alloy junction 2. Diffused junction
3. Grown junction
nP =
( 2.5 ×10 )
19 2
(a) 1 only (b) 2 only 1.76 ×1020

(c) 3 only (d) 1, 2 and 3
UPSC Poly.Lect.10.03.2019 6.25 × 1038
nP =
Ans. (c) : In grown junction technique a single crystal 1.76 × 1020
from a melt of germanium whose type is change during 6.25
the drawing process by adding p-type and n-type nP = × 1018
1.76
impurity.
nP = 3.55×1018/m3
61. Silicon devices can be employed for a higher
63. The electrical conductivity of pure
temperature limit (190ºC to 200ºC ) as
compared to germanium devices (80ºC to semiconductor is :
100ºC). With respect to this, which of the (a) Proportional to temperature
following are incorrect? (b) Increases exponentially with temperature
1. Higher resistivity of silicon (c) Decreases exponentially with temperature
2. Higher gap energy of silicon (d) Not altered with temperature
3. Lower intrinsic concentration of silicon IES-2016
4. Use of silicon devices in high-power Ans. (b) :The electrical conductivity of a semiconductor
applications increases exponentially with an increase in temperature
Select the correct answer using the code given because as temperature is increased more electrons get
below: energy and can jump to the conduction band which
(a) 1, 2 and 4 (b) 1, 2 and 3 increases conductivity
(c) 1, 3 and 4 (d) 2, 3 and 4 σ = C T3 / 2 e − Eg / 2kT e ( α + β ) T −3/ 2
IES-2018
64. Which one of the following statements is
correct?
n0 =
(1.5 ×10 )13 2
(a) For insulators the band-gap is narrow as 2.75 × 1016

compared to semiconductors
2.25 ×1026
(b) For insulators the band-gap is relatively wide n0 =
whereas for semiconductors it is narrow 2.75 ×1016
(c) The band-gap is narrow in width for both the 2.25
insulators and conductors n0 = ×1010
2.75
(d) The band-gap is equally wide for both
conductors and semiconductors. n 0 = 0.818 × 1010 / cm3
IES-2016
Ans. (b) : An insulator has a large gap between the 67. Assume that the values of mobility of holes and
valence band and conduction band. The valence band is that of electrons in an intrinsic semiconductor
full as no electrons can move up to the conduction band are equal and the values of conductivity and
as a result the conduction band is empty. intrinsic electron density are 2.32/Ωm and 2.5 ×
In a semiconductor the gap between the valence band 1019/m3 respectively. Then, the mobility of
and conduction band is smaller. At room temperature electron/hole is approximately:
there is sufficient energy available to move some (a) 0.3 m2/Vs (b) 0.5m2/Vs
2
electrons from the valence band in to conduction band. (c) 0.7 m /Vs (d) 0.9 m2/Vs
In a conductor there are no band gaps between the IES-2016
valence band and conduction bands. Ans. (a): Given,
65. In an extrinsic semiconductor the conductivity Mobility of holes and electrons are equal µ n = µ p
significantly depends upon:
(a) Majority charge carriers generated due to conductivity σ = 2.32/Ωm
impurity doping electron density ni = 2.5×1019/m3
(b) Minority charge carriers generated due to Conductivity (σ) = n i q(µ n + µ p )
thermal agitation
(c) Majority charge carriers generated due to (σ) = n i q(µ n + µ n ) Q µn = µ p
thermal agitation = 2n i q µ n
(d) Minority charge carriers generated due to
σ
impurity doping. µn =
KVS TGT (WE)-2016 2n i q
IES-2016
2.32
Ans. (a) : In an extrinsic semiconductor the µn =
conductivity significantly depends upon majority 2 × 2.5 × 1019 × 1.6 × 10−19
charge carriers generally due to doping. An extrinsic 2.32
semiconductor is a semiconductor doped by a specific µn =
5 × 1.6
impurity which is able to deeply modify its electrical
properties. 2.32
µn =
66. A Ge sample at room temperature has 8
intrinsic carrier concentration, ni = 1.5 × 1013 µ n = 0.29
cm–3 and is uniformly doped with acceptor of 3
× 1016 cm–3 and donor of 2.5 × 1015 cm–3. Then, µ n 0.3m 2 / Vs
the minority charge carrier concentration is: 68. The Hall-coefficient of a specimen of doped
(a) 0.918 × 1010 cm–3 (b) 0.818 × 1010 cm–3 semiconductor is 3.06 × 10–4 m3 C–1 and the
12 –3 12 –3
(c) 0.918 × 10 cm (d) 0.818 × 10 cm resistivity of the specimen is 6.93 × 10–3 Ωm.
IES-2016 The majority carrier mobility will be:
Ans. (b) : Given, (a) 0.014 m2 V–1 s–1 (b) 0.024 m2 V–1 s–1
Intrinsic carrier concentration (ni) = 1.5×1013/cm3 (c) 0.034 m V s2 –1 –1
(d) 0.044 m2 V–1 s–1
Acceptor concentration (NA) = 3×1016/cm3
IES-2016
Donor concentration ND = 2.5×1015/cm3
Q NA > ND Ans. (d) : Given,
Hall-Coefficient RH = 3.06×10–4 m3C–1
Then majority hole concentration
P0 = NA –ND Resistivity ( ρ ) = 6.93 ×10−3 Ωm
P0 = 30×1015–2.5×1015 Mobility (µ) = σ RH
P0 = 27.5×1015 R
P0 = 2.75×1016/cm3 (µ) = H
by using mass action law- ρ
n0P0 = ni2 3.06 ×10−4
n 2 ( µ ) =
n0 = i 6.93 ×10−3
P0 (µ) = 0.044m2/V-s

69. Doped silicon has Hall-coefficient of For hydrogen atom z =1, list orbit n= 1
3.68×10–4m3C–1 and then its carrier n2h2
concentration value is : r1 = 2
(a) 2.0 × 1022 m–3 (b) 2.0 × 10–22 m–3 4π mze2
(c) 0.2 × 1022 m–3 (d) 0.2 × 10–22 m–3 h2 o
IES-2016 r1 = 2 2 = 0.529 A
4π me
Ans. (a) : Given, for H e+ ion z = 2, second orbit n = 2
Hall coefficient (RH) = 3.68×10–4m3C–1
( 2)
2
1 h2
RH = r(He+ ) =
n×q 4π2 me 2 .2
1 4h 2
n= r(He+ ) = 2
R H .q 4π m e 2 .2
n is a carrier concentration value  h2 
1 r(He+ ) = 2  2 2 
n=  4π m e 
3.68 × 10−4 ×1.6 ×10−19 o
1 r(He + ) = 2 × 0.529A
n=
5.88 × 10−23 r(He + ) = 1.058 A
o
10
n= ×1022 = 1.70 × 1022 72. At temperature of 298 Kelvin, Silicon is not
5.88 suitable for most electronic applications, due to
n 2.0 × 10 22 / m 3 small amount of conductivity. This can be
70. The position of the intrinsic Fermi level of an altered by
undoped semiconductor (EFi) is given by: (a) Gettering (b) Doping
E − E V kT N V (c) Squeezing (d) Sintering
(a) C + ln IES-2015
2 2 NC Ans. (b) : Due to small amount of conductivity it can be
E + E V kT N V altered by doping the semiconductor with extra charge
(b) C − ln
2 2 NC carriers. The addition of impurities is called doping.
Doping is the process of adding some impurity atoms in
E + E V kT N V a pure (intrinsic) semiconductor so as to increase the
(c) C + ln
2 2 NC conductivity of a semiconductor.
E C − E V kT N V 73. The energy gap in the energy band structure of
(d) − ln a material is 9 eV at room temperature. The
2 2 NC material is
IES-2016 (a) Semiconductor (b) Conductor
Ans. (c) : Fermi level EF in intrinsic semiconductor is- (c) Metal (d) Insulator
E + E V kT  N V  IES-2015
EF = C + ln   Ans. (d) : The energy band gap is the energy difference
2 2  NC  between two bands i.e. valence band and conduction
if N V ≅ N C then fermi level lies in the middle band. In case of insulators energy band gap is very
of energy gap high (E g ≥ 5eV) . The band gap of insulator is more
Fermi level in n-type semiconductor is given by, than the band gap of semiconductor and conductor.
N 
E Fn = E C − kT ln  C 
 ND 
Fermi level in p-type semiconductor is given by,
N 
E FP = E V − kTl n  V  Hence at 9eV room temperature the material acts as a
 NA  insulator.
71. The radius of the first Bohr orbit of electrons 74. By doping Germanium with Gallium, the types
in hydrogen atom is 0.529 Å. What is the radius of semiconductors formed are:
of the second Bohr orbit in singly ionized 1. N type 2. P type
helium atom? 3. Intrinsic 4. Extrinsic
(a) 1.058 Å (b) 0.264 Å Which of the above are correct?
(c) 10.58 Å (d) 0.0264 Å (a) 1 and 4 (b) 2 and 4
IES-2015 (c) 1 and 3 (d) 2 and 3
Ans. (a) : Let us consider the nth bohr orbit. IES-2015
n2h2 Ans. (b) : Doping of germanium with gallium the types
rn = 2
4π mze 2 of semiconductor is p-type extrinsic semiconductor.

Type of dopants in extrinsic semiconductor. 78. Drift velocity in a metal is
Pentavalent-Arsenic (As), Antimony (Sb) (a) inversely proportional to the force on an
Phosphorous (P), etc. electron due to applied electric field
Trivalent - Indium (In), Boron (B), Gallium (Ga) etc. (b) directly proportional to the mass of an
Extrinsic p type semiconductor is formed when a electron
trivalent impurity is added to a pure semiconductor. (c) proportional to the mobility of an electron
75. An n-type of silicon can be formed by adding (d) inversely proportional to the strength of the
impurity of: applied electric field.
1. Phosphorous 2. Arsenic IES-2014
3. Boron 4. Aluminium
Ans. (c) : Drift velocity in a metal is proportional to the
Which of the above are correct?
(a) 1 and 2 (b) 2 and 3 mobility of an electron.
(c) 3 and 4 (d) 1 and 4 Drift velocity (Vd) = µ.E
IES-2015 Where µ = mobility
Ans. (a) : Phosphorus (P), Arsenic (As), and Antimony E = Electric field
(Sb) is called pentavalent or n type semiconductor Vd ∝ µ
impurity. An n-type semiconductor is created when pure
semiconductor like Si and Ge are doped with m2
drift velocity per unit electric field →
pentavalent element. When a pentavalent atom takes the V−s
place of a Si atom, four of its electrons bond with four • Drift velocity is directly proportional to the electric
neighboring Si atoms. However, the fifth electron field applied
remains loosely bound to the parent atom.
• Drift velocity is inversely proportional to the mass
76. According to Einstein's relationship for a of the electron.
semiconductor, the ratio of diffusion constant
to the mobility of the charge carriers is 79. At very high temperature, an n-type
(a) Variable and is twice the volt equivalent of semiconductor behaves like
the temperature (a) a p-type semiconductor
(b) Constant and is equal to the volt equivalent of (b) an intrinsic semiconductor
the temperature (c) a superconductor
(c) Equal to two and is twice the volt equivalent (d) an n-type semiconductor
of the temperature IES-2014
(d) Equal to one and is equal to the volt Ans. (b) : At very high temperature, an n-type
equivalent of the temperature semiconductor behave like an intrinsic semiconductor.
IES-2015 As the temperature increase the carrier concentration
Ans. (b) : According to Einstein's for a semiconductor increases significantly this is because extra electrons are
or, the ratio of the diffusion constant to the mobility of excited from the valence band to the conduction band, due
the charge carrier is equal to volt equivalent of to which the number of free electron-hole pair increases.
temperature.
Einstein Relation- 80. The Fermi level in a p-type semiconductor lies
• This gives the relation between diffusion coefficient close to
(D), mobility (µ) and temperature and given as- (a) top of the valence band
(b) bottom of the valence band
D n D P kT
= = = VT (Thermal voltage) (c) top of the conduction band
µn µ P q (d) bottom of the conduction band
77. The number of holes in an N-type silicon with KVS TGT (WE)- 2014
intrinsic value 1.5 × 1010/cm3 and doping IES-2014
concentration of 1017/cm3, by using mass-action Ans. (a) : The Fermi level in a p-type semiconductor
law is lies close to the top of valence band.
(a) 6.67 × 106/cm3 (b) 4.44 × 10–25/cm3
(c) 1.5 × 10–24/cm3 (d) 2.25 × 103/cm3
IES-2015
n i = 1.5 × 1010 / cm3
ND = 1017/cm3 In case of a p-type semiconductor, the number of holes
According to mass-action law- in valence band is greater than number of electron in
n 2 (1.5 ×10 )
10 2 conduction band hence the probability of occupation of
2.25 × 1020 energy level by the holes in valence band is greater
p= i = =
ND 1017 1017 than probability of occupation of energy levels by the
3 3
p = 2.25×10 /cm electron in conduction bands.
81. The following represents the energy band BI
diagram for: Hall voltage (VH) = R H .
W
−3.16 ×10−11 × 0.6 × 25
(VH) =
15 ×10−3
−47.4 × 10−8
(VH) =
15
VH = −3.16 ×10−8 V
(a) a p-type semiconductor
(b) an intrinsic semiconductor 84. A p-type silicon sample has an intrinsic carrier
(c) a conductor concentration of 1.5 × 1010/cm3 and a hole
(d) an insulator concentration of 2.25 × 1015/cm3. Then the
DFCCIL Executive S&T 29.09.2021, 12:30 to 2:30PM electron concentration is
Ans. (d) : (a) 1.5 × 1025/cm3 (b) 105/cm3
10 3
(c) 10 /cm (d) 0
IES-2014
Ans. (b) : Given,
Intrinsic carrier concentration (ni) = 1.5×1010/cm3
Insulators are those matterials which have no electrons hole concentration (p0) = 2.25 ×1015/cm3
in conduction band, that means outer shell as no according to mass action law-
0 .n 0 = n i
2
electrons. p
So no current flows in Insulator.
( ni )
2
82. Which of the following statements is true? n0 =

(a) Silicon doped with either phosphorous only p0
or boron only is p-type semiconductor. 2.25 × 1020
(b) Silicon doped with either phosphorous only n 0 =
2.25 × 1015
or boron only is n-type semiconductor. Electron concentration = 105/cm3
(c) Silicon doped with phosphorous is n-type
semiconductor. 85. The majority carriers in an n-type
semiconductor have an average drift velocity
(d) Silicon doped with boron is n-type
Vd in a direction perpendicular to a uniform
semiconductor. magnetic field B. The electric field E induced
BSNL(JTO)-2002 due to Hall Effect acts in the direction
Ans. (c) : Semiconductors have conductivity due to (a) Vd × B (b) B × Vd
many factors like the addition of an impurity or because (c) Along Vd (d) Opposite to Vd
of temperature effects An extrinsic semiconductor Punjab PSC Poly. Lect.-20.08.2017
where the dopant atoms provide extra conduction IES-2014
electrons to the host material like phosphorus (P) in Ans. (b) : Hall voltage (VH) = E.d or
silicon Si called donor impurities. B.I
This creates an excess of negative (n-type) electron VH =
charge carriers that are able to move freely. In the donor ρ.W
replacement atom, the outermost shell contains 5 electrons. Where,
E – Electric field induced
83. The electrical conductivity and electron W– Width of specimen
7 –1
mobility for aluminium are 3.8 × 10 (ohm-m) ρ – Charge density
2
and 0.0012 m /V-s, respectively. What is the Force (F) = q.E .......(I)
Hall voltage for an aluminium specimen that is drift velocity V = µ.E
15 mm thick for a current of 25 A and a the force for an dn-type semiconductor is
magnetic field of 0.6 tesla (imposed in a F = –q(Vd×B)
direction perpendicular to the current) for the F = q(B×Vd)
given value of Hall coefficient, RH as –3.16 ×
F
10–11 V-m/A-tesla? E=
(a) –316 × 10 V–8
(b) –3.16 × 10 V–8 q
(c) 316 × 10–8 V (d) 3.16 × 10–8 V
E=
( B × Vd ) q
IES-2014
q
Ans. (b) : Given,
Electrical conductivity (σ) = 3.8×107(ohm-m)-1 E = B × Vd
2
electron mobility (µ) = 0.0012 m /V-s 86. A heavily doped semiconductor has
W = 15mm = 15×10–3m (a) a resistivity which decreases exponentially
Current (I) = 25A with temperature
magnetic field (B) = 0.6 tesla (b) a resistivity which rises almost linearly with
Hall coefficient (RH) = –3.16×10–11 V-m/A-tesla temperature

(c) a negative temperature coefficient of resistance 91. An electric field is applied to a semiconductor.
(d) a positive temperature coefficient of resistance Let the number of charge carrier be n and the
IES-2014 average drift speed be v. If the temperature is
Ans. (d) : A heavily doped semiconductor increase with increased then
a rise in temperature such that semiconductor have a (a) both n and v will increase
positive temperature coefficient of resistance. (b) n will increase but v will decrease
87. For a particular material, the Hall coefficient is (c) v will increase but n will decrease
found to be zero. The material is (d) both n and v will decrease
(a) intrinsic semiconductor IES-2013
(b) extrinsic semiconductor Ans. (b) : When we increase the temperature then more
(c) metal charge carriers (n) are produced due to the breaking of
(d) insulator covalent bonds then average drift speed (Vd)avg
IES-2015, 2014 decrease.
1 1 Q Vd = µ.E
Ans. (c) : Hall coefficient R H = = Where, µ = mobility
ρ qN
E = Electric field
Where q = charge
N = Number of Atom/cm3 1
Q µ∝
We know that, N = ∞ for conductor T
1 1
So, R H = VD ∝
∞×q T
RH = 0 When temperature increase then mobility of charge
88. A continuity equation is also called as the law carrier decrease and drift velocity also decrease.
of conservation of 92. If the drift velocity of holes under a field
(a) Mass (b) Energy gradient of 200 V/m is 100 m/s, their mobility
(c) Charge (d) Power in SI units is
IES-2014 (a) 0.5 (b) 0.05
Ans. (c) : A continuity equation is also called as the law (c) 50 (d) 500
of conservation of charge. IES-2012
∂ρv Ans. (a) : Given, drift velocity (Vd) = 100m/s
+ ∇.J = 0 Electric field gradient (E) = 200V/m
∂t Vd = µ.E
89. A 'hole' in a semiconductor has Vd
1. Positive charge equal to the electron Mobility (µ) =
charge. E
2. Positive mass equal to the mass of the 100
µ=
electron. 200
3. An 'effective mass' greater than the µ = 0.5 m2/Vsec
effective mass of electron. 93. The concentration of hole-electron pairs in
4. Negative mass and positive charge equal to pure silicon at T=300 K is 7 × 1015 per cubic
the charge in nucleus. meter. Antimony is doped into silicon in a
Which of these statements are correct? proportion of 1 atom to 107 atoms. Assuming
(a) 1, 2, 3 and 4 (b) 1 and 3 only that half of the impurity atoms contribute
(c) 2 and 4 only (d) 3 and 4 only electrons in the conduction band, the factor by
IES-2013 which the number of charge carriers increases
Ans. (b) : An electron which has a negative charge, due to doping (the number of silicon atoms per
holes have a positive charge that is equal in magnitude cubic meter is 5 × 1028) is
but opposite in polarity to the charge. (a) 14 × 1015 (b) 0.5 × 1021
21
− + −19
e = p = 1.6 ×10 C . (c) 2.5 × 10 (d) 3.6 × 105
A hole is in a semiconductor has an effective mass IES-2012
greater than effective mass of electron. Ans. (d) : Given,
Mass of electron is 9.1 ×10–31kg. Intrinsic carrier concentration (ni) = 7×1015/cm3
90. Medium doping in Silicon and Germanium The number of charge carrier before doping is equal to
corresponds to impurity of the order of the number of holes
(a) 1 part in 106 (b) 1 part in 105 p = n = n i = 7 ×1015 / cm3
4
(c) 1 part in 10 (d) 1 part in 108 p + n = 7×1015 +7×1015
IES-2013 = 14×1015/cm3
Ans. (a) : Medium doping in silicon and Germanium since antimony is doped in a proportion of 1 in 107 The
corresponds to impurity of the order of 1 part in 106. number of antimony atoms per cubic meter is
5 × 1028 • The resistivity of a material can be defined in terms
= of the resistance (R), length ( l ), and area of the
107 material (A).
= 5×1021
As half of these atoms contribute electrons to the RA
ρ=
conduction band, then number of extra conduction l
5 × 1021 96. The diffusion constant for holes in silicon is
electron produced in = = 2.5 ×1021 atoms / cm3 13 cm2/ sec. What is the diffusion current if the
2
The factor by which the number of charge is gradient of the hole concentration
dp/dx = – 2× 1014 holes per cm3 per cm?
2.5 × 1021 (a) – 0.146 mA (b) –3.2 × 10–5 A
increased = = 3.571× 105
7 × 1015 (c) 32 µA (d) 0.416 mA
3.6 ×105 IES-2011
94. An intrinsic semiconductor has the following Ans. (d) : Given in the question.
properties: Diffusion constant (DP) = 13 cm2/sec
1. its electron concentration equals its hole dp
concentration. = −2 ×1014
2. Its carrier density increases with temperature. dx
3. Its conductivity decreases with temperature. dp
J P(diff ) = −q D P
Which of these statements are correct? dx
(a) 1, 2 and 3 (b) 2 and 3 only Where, JP → Diffusion current density for hole.
(c) 1 and 3 only (d) 1 and 2 only q → Charge of charge carrier.
IES-2011 DP → Diffusion constant for hole.
Ans. (d) : Intrinsic semiconductor- dp
• Available in nature or found in Nature. → Concentration gradient for holes.
• It is a pure semi-conductor without any Impurity or dx
dopants. Now, JP = –1.6×10–19 ×13×(–2×1014)
JP = 0.416 ×10–3
• In an Intrinsic S.C concentration n=p i.e electron
concentration is equal to hole concentration. J P = 0.416mA
Effect of temperature or carrier concentration in 97. Given that at room temperature the volt
intrinsic semiconductor- equivalent of temperature VT = 26 mV, hole
• In Intrinsic S.C ⇒ ↑ n = p ↑= n i ↑ mobility µP = 500 cm2/v-s and the life time of
and holes is 130 ns, in a sample of n-type silicon bar
that is exposed to radiation at one end at low-
↑ n i α T3 / 2 ↑ injection level, what is the diffusion length of
• So that in Intrinsic S.C carrier concentration will be holes?
Increased with temperature. (a) 1300 microns (b) 100 Angstroms
• It is also known as non degenerated S.C. (c) 169 microns (d) 100 microns
• In a periodic table I/II/III behaving like a conductor. IES-2011
• IVth group element are behaving like as Ans. (a) : Given in the question→
semiconductor. Room temperature the equivalent of temperature VT =
• 7th & 8th group element are behaving like as 26mV
Insulator & perfect Insulator respectively. cm 2
95. The resistivity of a metal is a function of Hole mobility (µP)=500
v−s
temperature because
(a) The electron density varies with temperature Carrier life time (τP ) = 130ns
(b) The electron gas density varies with By Einstein relation →
temperature • It gives the relationship between Diffusion constant,
(c) The lattices vibration increases with mobility & Thermal Voltage.
temperature DP
(d) Collision of electrons increases as = VT
temperature increases µP
IES-2011 DP = µP VT
Ans. (c) : DP =500 ×26mV
• The resistivity of metal is function of temperature D P = 500 × 26 × 10−3
because The lattices vibration increases with
temperature.
• In the case of metals or conductors, when the
Now → diffusion length, (LP) = (
DP τP )
temperature increases, the resistivity of the metal LP = 500 × 26 × 10−3 × 130 × 10−9
increases as a result. Thus, the flow of current in the LP = 1300×10–6m
metal decreases. This phenomenon reflects a
positive temperature coefficient. L P = 1300µm

98. Consider a semiconductor carrying current • Arsenic is pentavalent, therefore when added with
placed in a transverse magnetic field B, as silicon it leaves one electron as a free electron. In
shown below. The measured potential across 1 this the conduction of electricity is due to motion of
and 2 surfaces is positive at 2. electrons, so the resulting material is n-type
What is the type of material? semiconductor.
• In N-type S.C using pentavalent Impurity atom.
• N-type S.C is also known Donor type Impurity.
Example of n-type semiconductor → N, P, As, Sb, Bi
100. When donor atoms are added to
(a) Intrinsic Si material semiconductor, it
(b) n-type semiconductor material (a) Increases the energy bandgap of the
(c) p-type semiconductor material semiconductor
(d) no such conclusion can be drawn (b) Decreases the energy bandgap of the
IES-2011 semiconductor
Ans. (b) : When a current carrying speciman (metal or (c) Introduces a new narrow bandgap near the
semiconductor) is placed in a transverse magnetic field conduction band
then an electric field is introduced in the direction (d) Introduces a new discrete energy level below
perpendicular to both, current & magnetic field, this the conduction band
effect is known as hall effect. IES-2011
Y Ans. (d) :
w
X
• In N-type semiconductor we will add pentavalent

Impurity or doping.
• In a X direction we assume current by application of • Donor energy level is a discrete energy level
Battery. created just below conduction band.
• In a Z- direction I have assumed magnetic field. • Discrete energy level means the energy level not
VH → Hall Voltage (Induced voltage) continuous C.B energy level.
• Donor energy level denotes the energy level of all
EH → Hall electric field (Induced electric field)
V the pentavalent atom added to pure semiconductor.
E H = H (Voltage per unit distance) • All the fifth electrons will occupy a new energy
d
level just below of the conduction band.
• VH = –ve for n-type semiconductor
VH = +ve for p-type semiconductor 101. On applying an electric field of intensity
• Hence, from Hall effect, the specimen is an n-type 10V/cm across a semiconductor at a certain
semiconductor because, due to F=q (V×B), all the holes temperature the average drift velocity of free
should accumulate at upper surface. electrons is measured to be 70 m/s. Then the
99. Doping intrinsic Silicon with Arsenic as an electron mobility is
impurity (a) 7 × 104 cm2/Vs (b) 700 cm2/Vs
2
(a) Only increases the conductivity of Silicon by (c) 7 m /Vs (d) 700 cm/Vs
increasing the number of free electrons IES-2011
available Ans. (b) : As given in the question.
(b) Produces a semiconductor in which the Drift velocity of free electron is (Vd) = 70 m/s
charge carriers are predominantly electrons Applied electric field intensity (E) = 10 V/cm
but holes are also present
In a semiconductor the drift velocity is → Vd = µE
(c) Produces a semiconductor in which the
charge carriers are predominantly holes but Where → µ = mobility
free electrons also present Vd = drift velocity
(d) Produces a semiconductor in which the E = Applied electric field
charge carriers contain nearly equal number Now
of electrons and holes
V 70 × 100cm / s
IES-2011 µ= d =
Ans. (b) : E 10V / cm
• Doping intrinsic silicon with Arsenic as an impurity 700cm 2
produces a semiconductor in which the charge carriers µ =
a predominantly electrons but holes are also present. V sec

102. The diffusion length for holes Lp, is the dp dp
(a) Average distance which an injected hole (a) (b)
dx 2 dx
travels before recombining with an electron
(b) Maximum distance travelled by a hole before dp d 2p
(c) (d)
recombining with an electron dt dx 2
(c) Length of the region in which diffusion takes IES-2009
place Ans. (b) : Diffusion current of holes in a semiconductor
(d) Minimum distance travelled by a hole before is proportional to product of charge of charge carrier
it recombines with an electron. with concentration gradient.
IES-2010 Diffusion current ∝ concentration gradient.
Ans. (a) : dp
• Diffusion length for holes (LP) is average distance jp (Diff ) ∝ q
which an injected hole travels before recombination dx
with an electron. 105. Which of the following quantities cannot be
• Diffusion length is a average length a carrier moves measured/determined using Hall effect?
between generation and recombination. (a) Type of semiconductor (p or n)
• Semiconductor materials that are heavily doped (b) Mobility of charge carriers
have greater recombination rates and consequently, (c) Diffusion constant
have shorter diffusion lengths. (d) Carrier concentration
• Hole diffusion length (LP) = D P τP TNPRB-2017
IES-2009
Where → DP →Diffusion constant for hole.
Ans. (c) : Hall Effect-When a current carrying
τP → Carrier life time for hole specimen (metal or semiconductor) is placed in a
• Diffusion length (L) depends on → transverse magnetic field then an electric field is a
(i) Diffusion constant Introduced in the direction perpendicular to both,
(ii) Carrier life time current an magnetic field, this effect is known as hall
(iii) Mobility effect.
(iv) Temperature. • Quantities that can be measured using hall effect.
(v) Thermal voltage (a) Whether the given specimen in metal or
103. Consider the following statements: semiconductor.
1. Acceptor level is formed very close to the (b) To measure carrier concentration.
conduction band. (c) Mobility of charge carrier.
2. The effective mass of the free electron is (d) Magnetic flux density.
same as that of a hole. (e) To design hall effect transducer.
3. The magnitude of the charge of a free (f) To measure the signal power in the electromagnetic
electron is same as that of a hole. wave.
4. Addition of donor impurities adds holes to (g) Type of semiconductor (p-type or n-type)
the semiconductor.
Which of the above statements are correct?
(a) 1 and 3 (b) 2 and 3
(c) 2 and 4 (d) 3 and 4
IES-2010
Ans. (b) : 106. An intrinsic semiconductor is doped lightly
• Acceptor level formed very close to the conduction with p-type impurity. It is found that the
band, thus statement 1 is false. conductivity actually decreases till a certain
• The effective mass of free electron is same as that of doping level is reached. Why does this occur?
hole. (a) The mobility of holes decreases
But (Effective mass of hole & Electrons) (b) The mobility of both electrons and holes
m*P > m*n decreases
↓ (c) The hole density actually reduces
Veryslightly (d) Effect of reduction in electron due to increase
• The charge of the electron is equivalent to the in holes compensates more than the effect of
magnitude of the elementary charge but in a increase in holes on conductivity
negative sign, because electron possess negative IES-2009
charges. Ans. (d) : In an doped intrinsic semiconductor
• Addition of donor Impurities adds electrons to the conductivity will decrease with increase temperature
semiconductor. still a certain doping level reached because effect of
104. Diffusion current of holes in a semiconductor is reduction in electron due to increase in holes
proportional to (with p = concentration of compensates more then the effect of increase in holes
holes/unit volume) on conductivity.

107. The minimum energy of a photon required for (a) parallel to I
intrinsic excitation is equal to (b) perpendicular to B and parallel to I
(a) energy of bottom of conduction band (c) parallel to I and B
(b) energy of top of valence band (d) perpendicular to Both I and B
(c) forbidden gap energy IES-2009
(d) Fermi energy Ans. (d) : Hall effect- When a current carrying
IES-2009 specimen (metal or semiconductor) is placed in at
Ans. (c) : transverse magnetic field then an electric field is a
introduced in the direction perpendicular to both.
Current & magnetic field this effect known as hall
effect, and the potential produced is called the "Hall
Voltage".
• In a X direction we assume current By application
of battery.
• In a Z-direction I have assumed magnetic field .
• There will be an induced electric field because of
• Forbidden energy gap, also known as band gap refers charge separation (Lower surface become -Ve
to the energy difference (eV) between the top of valence charge & upper surface becomes +Ve charge)
band and the bottom of conduction band in materials.
• So, for excitation of photon from valence band to
conduction band the minimum energy required is
forbidden gap energy.
• EC = lowest energy level of conduction band.
EV = Highest energy level of valence band
EG = E C − E V
VH → Hall voltage (Induced voltage)
1 EH → Hall electric field (Induced electric field)
T∝
Eg V
E H = H (Voltage per unit distance)
• If energy gap (EG) decreases then conductivity will d
increases its behave like as conductor. VH = E H .d d = distance between upper and
• If energy gap (EG) increases then conductivity will
decreases its behave like as insulator. lower surface.
108. In a material, the Fermi level is located between 110. Assuming that the electron mobility in intrinsic
the centre of the forbidden band and the silicon is 1500 cm2/V-Sec at room temperature
conduction band. Then what is that material? (T=300K and the corresponding ' volt
(a) A p-type semiconductor equivalent of temperature' VT = 25.9 mV, what
(b) A n-type semiconductor is the approximate value of the electron
(c) An intrinsic semiconductor diffusion constant?
(d) An insulator (a) 40 cm2/s (b) 4 cm2/s
2
IES-2009 (c) 400 cm /s (d) 4000 cm2/s
Ans. (b) : IES-2008
Ans. (a) : Given in the question
cm 2
Electron mobility (µn) = 1500
V − Sec
Volt equivalent of temperature (VT) = 25.9mV
• From the energy level diagram of the n-type Electron diffusion constant (Dn) = ?
semiconductor, it's clear that the Fermi level is ∴ Einstein equation
present near the conduction band and for away D n
= VT
from the valence band. In the case of n-type µn
semiconductor, the Fermi level is present just below Dn = VT × µn
the conduction band. Dn = 25.9 ×10–3 ×1500
• If the fermi level is at centre of the forbidden band Dn = 388.5 ×10–1
then the material is called intrinsic semiconductor.
• If fermi level is below the centre of forbidden band cm 2
D n = 38.85
[Eg] then the material is P-type semiconductor. Sec
109. As per hall effect, if any specimen carrying a Approximate
current I is placed in a transverse magnetic cm 2
field B, then an electric field E is induced in the D n = 40
specimen in the direction Sec

111. An intrinsic semiconductor with energy gap • In N-type semiconductor we will add pentavalent
1eV has a carrier concentration N at Impurity or doping.
temperature 200K. Another intrinsic Ex- N, P, As, Sb, Bi
semiconductor has the same value of carrier • It is a donar type semiconductor.
concentration N at temperature 600 K. What is N - type S.C →
the energy gap value for the second
semiconductor?
(a) (1/3) eV (b) (3/2) eV
(c) 3 eV (d) 9 eV
IES-2008 −
donar e
Ans. (c) : As it is known
 − EG 0 
 
n i2 = A 0 T3e KT 
 − EG 0 
113. For a semiconductor, the conductivity is a
  function of the products of the number of charge
n i ∝ T3 / 2 e 2kT 
carriers and their mobilities. As a result, if the
Given that, temperature of a slab of intrinsic silicon
at T = 200K ; EG0 = 1eV increases, how does its conductivity vary?
Now→ (a) Decreases
When at T = 600K, EG0 = ? (b) Increases as a non-linear variation
n i = N ∝ (200)3 / 2 e −1/ 2kT .......(i) (c) Remains unaffected
− EG 0 (d) Increases or decreases depending upon the
n i = N ∝ (600)3/ 2 e 2kT
.......(ii) rise in temperature
Equation (i) and (ii) are equal IES-2008
 −1   − EG 0  Ans. (b) : Conductivity of semiconductor-
   
→ (200)3/ 2 e 2kT  = (600)3 / 2 e 2kT 
n = p = ni
→ Taking ln on both sides- σ = nqµ n + nqµ p
1 −E G 0
→ ln(0.192) − = σ = nq(µ n + µ P )
2kT 2kT
EG0 Where
→ 30.72 = σ → conductivity
2kT
→ 30.72 ×2kT= EG0 n → free electron
→ EG0 = 3.17 eV q → charge of carrier
µ n → Electron mobility
E G 0 = 3eV
µ P → Hole mobility.
112. Consider the following statements: • In Intrinsic semiconductor as we increases the
N-type silicon can be temperature then conductivity will increase.
1. formed by adding impurity of phosphorous
• At the same time charge carrier concentration
2. formed by adding impurity of arsenic
increases. As number of co-valent bond will be
3. formed by adding impurity of boron
broken & equal numbers of free electron and holes
4. formed by adding impurity of aluminium
will generated and then this charge carrier
Which of the statements given above are
concentration increases by large value so
correct?
(a) 1 and 3 only (b) 3 and 4 only conductivity increases by large value.
(c) 1 and 2 only (d) 1, 2, 3 and 4 • So over all total conductivity will increases with
IES-2008 increase temperature.
Ans. (c) : ↑ σ =↑ nqµ n ↓ + ↑ pqµ P ↓
• An N-type semiconductor in an Intrinsic mainly conductivity depends on charge carrier
semiconductor doped with phosphorus impurity concentration.
silicon of group IV has four valence electron and 114. An n-type semiconductor is illuminated by a
phosphorus of group V has five valence electron steady flux of photons with energy greater than
• However, phosphorus has five electrons, and when the band gap energy. The change in
combined, the fifth electron becomes a "free" conductivity ∆σ obeys which relation?
electrons that moves easily within the crystal when
(a) ∆σ = 0
a voltage is applied. because the charge carriers are
electrons, n-type refer to a negative charge. (b) ∆σ = e(µ n + µρ )∆ n
Intrinsic Semiconductor (c) ∆σ = e(µ n ∆n − µρ ∆p)
• It is a pure semi-conductor without any Impurity
(or) dopants (d) ∆σ = eµ n ∆n
Ex- Si, Ge, .......etc. IES-2007

Ans. (b) : When the semiconductor is illuminated by a 117. In a homogeneously doped n-type
steady flux of photons, the number of new hole-electron semiconductor bar, holes are injected at one
pairs is proportional to the number of incident photons end of the bar. How will the holes flow to the
and also the are equal. other end?
i.e ∆n = ∆p (a) By drift mechanism only
There for, change in conductivity (b) By diffusion mechanism only
(c) By combination of drift and diffusion
∆ σ = e ( µ n + µ P ) ∆n mechanisms
115. Which one of the following expressions may be (d) By recombination mechanism
used to correctly describe the temperature (T) IES-2007
variation of the intrinsic carrier density (ni) of Ans. (b) :
a semiconductor?
Eg is the band gap, A is pre-factor,s k is
Boltzmann constant.
(a) ni(T) = (A/T) exp (–Eg/kT2)
(b) ni(T) = A (Eg/kT)10
(c) ni(T) = A exp (–Eg/2kT)
(d) ni(T) = AT3/2 exp (–Eg/2kT) • Diffusion is a natural phenomena.
IES-2007 which holes are injected, at, one end of N-type
Ans. (d) : The intrinsic carrier concentration is known semiconductor, then the concentration near the
as- injected surface increases compared to bulk.
− Eg • Migration of charge carrier from higher
(n i ) 2 = A 0 T 3e kT concentration to lower concentration or higher
− Eg
density to lower density is called on diffusion.
ni = A0 T e 3 / 2 2kT • Diffusion is mainly due to concentration gradient.
Where- dn (e − / cm3 )
= e − concentration gradient
A0- material constant dx cm
Which is independent of temperature. dp Hole / cm3
T - Temp (in K) = Hole concentration gradient
EG0 - Energy gap at 0K dx cm
K - Boltzmann's constant • From the figure
• Diffusion length (L) having relation with diffusion
K = 1.38 × 10−23 joule / K Coefficient (D) & carrier life time (τ)
n i ∝ T3 / 2 L = Dτ
− E g0
118. Why does the mobility of electrons in a
n i ∝ e 2kT semiconductor decrease with increasing donor
From the above two dependency we are considering density?
dominating dependency. (a) Doping increases the effective mass of electrons
116. An intrinsic semiconductor (intrinsic electron (b) Doping decreases the relaxation time of electrons
density = 1016 m–3) is doped with donors to a (c) Electrons are trapped by the donors
level of 1022 m–3. What is the hole density (d) More holes are generated so that the effective
assuming all donors to be ionized ? mobility decreases
(a) 107 m–3 (b) 108 m–3 IES-2007
(c) 10 m10 –3
(d) 106 m–3 Ans. (b) : As doping increases (↑), more number of
IES-2007 electrons (e–s) will move in the conduction Band, Due
Ans. (c) : Given that to increased concentration of electrons the scattering
ni = 1016 m–3 Increases (↑), Relaxation time (τ) decreases (↓). So
n = 1022 m–3 mobility (µ) decreases (↓).
p=? 119. Match List-I (Item) with List-II (Position) and
We know mass action law select the correct answer using the codes given
n × p = (n i ) 2 below the lists:
List-I
n i2 A. Donor energy band
p=
n B. Fermi level of p-type semiconductor at
room temperature
(1016 ) 2
p= C. Acceptor energy band
1022 D. Fermi level in intrinsic semiconductor
p = 1032 ×10–22 List-II
1. At the middle of forbidden energy gap
p = 1010 m −3
2. Close to the conduction band
3. Very close to the valence band • Mass action law is mainly used to calculate minority
4. Close to the valence band carrier concentration under thermal equilibrium.
Codes:
miniority carrier concentration
A B C D
(a) 4 3 2 1 1
∝
(b) 2 1 4 3 majority carrier concentration
(c) 4 1 2 3
(d) 2 3 4 1 121. Consider the following statements:
IES-2007 Electrical conductivity of a metal has negative
temperature coefficient since
Ans. (d)
1. electron concentration increases with
temperature
Donar energy level(ND) 2. electron mobility decreases with
fi
temperature
3. electron-lattice scattering rate increases
with temperature
correct?
Donor energy band (ND): (a) 1, 2 and 3 (b) only 1 and 2
The states of the donors lie below the conduction band (c) Only 2 and 3 (d) Only 1 and 3
and the states of the acceptor above the valence band.
IES-2007
Fermi level of p-type semiconductor:
P-type semiconductor at room temperature. the Fermi Ans. (c) : Electrical conductivity of a metal has
energy level is just below the acceptor energy level and negative temperature coefficient since, electron mobility
just above the maximum energy level of valence Band. decreases, with temperature. And electron-lattice
Acceptor energy band: scattering increases with temperature.
Si or Ge doped with impurities like aluminium, • As temperature decreases
produces energy level which is situated in the energy • Energy decreases
gap slightly above the valence band. This is called as • Velocity of charge particle decreases
acceptor energy level. • Relaxation time (τ) decreases
Acceptor energy band, very closed to the valence band. As temperature Increases
Fermi level in Intrinsic semiconductor- • Energy of particle increases
(n = p) • Velocity of particle increases
At → T = 0ºk • Scattering decreases
n = p = 0 there is a no any free electron. • Relaxation time (τ) increases
• Mobility increases
In intrinsic semiconductor at T = 0ºK As the temperature increases the carrier concentration
fermi-level is situated in the middle (centre) of remain almost the same but there is a decrease in
conduction band & valence band. mobility due to lattice scattering or the frequency of
120. The electron and hole concentrations, n and p collision increases and hence resistance also increases.
respectively obey the relation np = n i2 where ni So, that conductivity decreases resistivity increases
is the intrinsic carrier density. This expression which Implies the temperature coefficient of resistivity
is valid for which of the following? metals is positive.
(a) For all semiconductors under any condition 122. The drift velocity of electrons in silicon varies
(b) For direct band gap semiconductor only with applied electric field in which one of the
(c) For non-degenerate semiconductor under ways?
thermal equilibrium condition (a) It monotonically increases with increasing
(d) For degenerate semiconductors having excess field
electrons and holes (b) It first increases linearly, then sub linearly
and finally attains saturation with increasing
KVS TGT (WE)- 2017 field
IES-2007 (c) It first increases, then decreases showing a
Ans. (c) : negative differential region, again increases
• Mass action law- and finally saturates
At thermal equilibrium, product of electron (d) The drift velocity remains unchanged with
concentration and Hole concentration remain constant, increase in field
and it is equal to square of intrinsic concentration. IES-2007
Ans. (b) : Drift velocity is directly proportional to
n.p = n i2 applied electric field.
• Mass action law is used to find minority carrier Vd ∝ E where, Vd → drift velocity
concentration in a non-degenerate semiconductor of Vd = µE E → electric field
thermal equilibrium.
Here, velocity is depend upon mobility (µ) and applied List-I List-II
electric field. A. Intrinsic semiconductor 1. 1028
When electric field applied, then mobility is varies. and B. Insulator 2. 1022
C. Extrinsic semiconductor 3. 1018
it is shown in the figure given below.
D. Conductor 4. 1014
Codes:
A B C D
(a) 3 4 2 1
(b) 2 1 3 4
(c) 3 1 2 4
(d) 2 4 3 1
IES-2006
Ans. (a) :
Material Carrier concentration
Intrinsic semiconductor 1018
Insulator 1014
Extrinsic semiconductor 1022
Conductor 1028
The carrier concentration will be as.
Conductor (1028) > Extrinsic (1022) > Intrinsic (1018) >
Insulator (1014)
125. Which one of the following element has
Case-I. For smaller electric field (0< E<103) the Forbidden energy band approximately equal to
mobility is constant i.e. drift velocity increasing 6 eV?
linearly. (a) Metal (b) Insulator
Case-II. For medium electric field (103< E <104) the (c) Conductor (d) Semiconductor
DFCCIL Executive S&T-17.04.2016, Shift-II
mobility is decreases i.e. drift velocity Increases sub
linearly. Ans. (b) : The forbidden gap between the valence band
4 7 and conduction band is very large in insulator. The
Case-III. For larger electric field (10 < E < 10 )
electrons in valence band cannot move because they are
product of mobility and electric field becomes constant locked up between the atoms. Insulator has forbidden
value of drift velocity. energy band approximately equal to 6eV.
Vd = µE 126. Which of the following can be determined by
V using a Hall crystal?
µ = d (Saturation or constant) 1. Concentration of holes in a p-type
E↑
semiconductor.
1 2. Concentration of electrons in an n-type
↓µ ∝ {∴µ = decrease} semiconductor.
E↑
3. Temperature of the set-up with any type of
123. A Si sample is doped with a fixed number of semiconductor.
group V impurities. The electron density n is 4. Diffusion constant and life-time of minority
measured from 4 K to 1200 K for the sample. carriers of any type of semiconductor.
Which one of the following is correct? Select the correct answer using the code given
(a) n remains constant over the temperature range below:
(b) n increases monotonically with increasing (a) Only 1 and 2 (b) 1, 2 and 4
temperature (c) Only 3 and 4 (d) Only 2 and 4
(c) n increases first, remains constant over a Nagaland PSC CTSE (Degree) -2015, Paper I
range and gain increases with increasing IES-2006
temperature Ans. (a) • Hall effect can be used to determine.
(d) n increases, shows a peak and then decreases A. Whether the given specimen in metal or
with rise in temperature semiconductor.
IES-2007 B. To measure carrier concentration.
(i) Concentration of holes in p-type semi
Ans. (c) : A Si sample is doped with a fixed number of
conductor.
group V impurities. The electron density n is measured
(ii) Concentration of electrons in n-type
from 4 K to 1200 K for the sample n increases first,
semiconductor.
remains constant over a range and gain increases with (C) Mobility of charge carrier.
increasing temperature. (D) Magnetic flux density.
124. Match List-I (Material) with List-II (Carrier (E) To design Hall effect transducer.
Concentration/m3) and select the correct (F) To measure the signal power in the
answer using the codes given below the lists: electromagnetic wave.
127. Match List-I (Current) with List-II (Variation) 129. In addition to conduction, which one of the
and select the correct answer using the code following mechanisms can account for the
given below the lists: transport of charges in a semiconductor (not
List-I List-II ordinarily encountered in metals)?
A. Hole diffusion current 1. n.E (a) E.M.F. generated with in the body of the
B. Electron drift current 2. p.E semiconductor
C. Hole drift current 3. –dp/dx (b) Mutual attraction between charges
D. Electron diffusion current 4. dn/dx (c) Mutual repulsion between charges
(d) Diffusion
Codes:
IES-2006
A B C D
(a) 2 1 3 4 Ans. (d) :
(b) 3 4 2 1 • Diffusion is a natural phenomena
(c) 2 4 3 1 • Magnetic field of charge carrier from higher
(d) 3 1 2 4 concentration to lower concentration or higher
density to lower density is called as diffusion.
IES-2006
• Diffusion occurs in semiconductor due to non-
Ans. (d) : uniform concentration of carriers i.e. due to
−dp concentration gradient.
• Hole diffusion current ∝
dx 130. Match List-I (material) with List-II (Energy
• Hole drift current ∝ p.E Level) and select the correct answer using the
• Electron drift current ∝ n.E codes given below the lists:
List-I List-II
dn
• Electron diffusion current ∝ A. p-type semiconductor 1. Donor energy
dx at 0K temperature level is close to
128. The electron concentration in a silicon sample the conduction the conduction
doped with 1015 cm-3 P atoms, will vary, in the band
temperature range of 4.2 – 1000 K, as follows B. Intrinsic semiconductor 2. Acceptor
(a) It will be 1015 cm–3 over the whole range at 0K temperature energy level is
(b) It will be 1015 cm–3 upto a temperature T at close to the
which intrinsic concentration is 1015 cm–3 and valence band
then it will increase exponentially C. n-type semiconductor 3. Fermi-level is
at room temperature very close to
(c) It will first increase exponentially upto a
valence band
temperature T then remain constant at 1015 D. p-type semiconductor 4. Fermi-level is
cm–3 over the remaining range at room temperature half way
(d) It will first increase exponentially upto a between the
temperature T1 then remain constant at 1015 valence band
cm–3 upto a temperature T2 and then increase the conduction
exponentially band
IES-2006 Codes:
Ans. (d) : The electron concentration in a silicon A B C D
sample doped with 1015cm–3 atoms will first increase (a) 1 2 3 4
exponentially upto a temperature T1 then remain (b) 3 4 1 2
constant at 1015cm–3 upto a temperature T2 and then (c) 1 4 3 2
increases exponentially. Since, as the temperature is (d) 3 2 1 4
raised, the donor electrons are donated to the IES-2006
conduction band and at temperature T1 all the donor Ans. (b) : For p-type semiconductor.
atoms are ionized. This temperature range is called the
ionization region in which electron concentration p
increases exponentially.
When every available extrinsic electron has been
transferred to the conduction band, the conduction band
electron concentration n0 is virtual constant with
temperature until the concentration of extrinsic ni N 
becomes comparable to the extrinsic concentration Nd. E fP − Ev = kTln  V 
Finally at higher temperature, ni is much greater than Nd  NA 
and the intrinsic carriers dominate. The electron • At T = 0ºk
concentration increases exponentially given as- EfP – EV = 0
− Eg E fP = E V
n i2 = A 0T 3e
kT
So, fermi level is very closed to valence band.

(b) Intrinsic semiconductor- 132. The free electron density in a conductor is
(1/1.6) × 1022 cm–3. The electron mobility is 10
E + E V kT  N C  cm2/Vs. What is the value of its resistivity?
Ef = C − ln  
2 2  NV  (a) 10–4 Ωm (b) 1.6 × 10–2 Ωm
at T = 0ºk (c) 10 Ωcm
–4
(d) 104 mho cm–1
E + EV IES-2005
Efi = C −0 Ans. (c) : Given that →
2
1
E + EV Free electron density (n) = × 1022 cm −3
Ef i = C 1.6
2
10cm 2
Electron mobility (µn) =
V −S
We know that
fi
→ Conductivity (σ) = nq µ n
1
Resistivity (ρ) =
conductivity(σ)
• Fermi level is half way between the valence band and
the conduction band. 1
ρ=
(c) n-type semiconductor at room temperature n.q. µ n
1
ND
ρ=
1
×10 ×1.6 ×10−19 × 10
22
1.6
1
ρ= 4
At T = 300K, donor energy level is closed to the 10
conduction band. ρ = 10−4 Ω − cm
N  133. The intrinsic concentration in a semiconductor
E C − E fn = kT ln  C 
N
 D at 300K is 1013 cm–3. When it is doped with
donor type impurities, the majority carrier
(d) P-type semiconductor at room temperature
concentration becomes 1017 cm–3. What is the
value of its minority carrier density?
DN (a) 0.999 × 1017 cm–3 (b) 1017 cm–3
4 –3
(c) 10 cm (d) 109 cm–3
AN IES-2005
Ans. (d) : Given that
Intrinsic concentration (ni) = 1013 cm–3
• For P-type semiconductor at room temperature, majority carrier concentration (n) = 1017cm–3
Acceptor energy level is close to the valence band. minority carrier density (p) =?
131. The mobility of electrons in a semiconductor is We know that-
defined as the By mass action law.
(a) Diffusion velocity per unit electric field n.p = n i2
(b) Diffusion velocity per unit magnetic field n2
(c) Drift velocity per unit magnetic field p= i
(d) Drift velocity per unit electric field n
(1013 )
2
IES-2006
Ans. (d) : Drift velocity is directly proportional to p=
1017
applied electric field.
p = 1026 ×10–17
V ( meter )
2
Vd = µE ⇒ µ = d p = 109 cm −3
E ( Volt.Sec )
134. Two pure specimen of a semiconductor
Where, material are taken. One is doped with 1018 cm–3
µ = Mobility number of donors and the other is doped with
Vd = Drift velocity 1016cm–3 number of acceptors. The minority
E = Applied Electric field. carrier density in the first specimen is 107 cm–3.
V What is the minority carrier density in the
• µ= d other specimen?
E (a) 1016 cm–3 (b) 1027 cm–3
From the above equation we can observe that mobility 18
(c) 10 cm -3
(d) 109 cm–3
(µ) is given by, drift velocity per unit electric field. IES-2005
Ans. (d) : Two pure specimen of a semiconductor (c) In Intrinsic Semiconductor-
material taken. Fermi-level is situated in the middle (centre) of
n1p1 = n i2 ....(i) conduction band & valence band.
n 2 p 2 = n i2 ....(ii) Mathematically-
Given that EC + E V N 
→ n1 = 1018 cm −3 ; P1 = 107 cm −3 Ef = − KT ln  C 
2  NV 
→ P2 = 1016 cm −3 ; n 2 = ?
if NC = NV
Now
From equation (i) & (ii), we get EC + EV
Then, E f =
n1p1 = n 2 p 2 2
n1p1 (d) In degenerated n-type semiconductor, If doping
n2 =
p2 Increases then Fermi level moves towards the
10 × 10
18 7 conduction band and for high level doping it start
n2 = touching the conduction band & may enter into the
1016
2
n2 = 10 ×10 7 conduction band same like in tunnel diode.
136. What is the approximate mobility of holes in
n 2 = 109 cm −3
Germanium at room temperature?
135. Match List-I (Type of Conductor) with List-II (a) 4500 cm2/V.s (b) 2400 cm2V.s
(Position of Fermi Level) and select the correct 2
(c) 1800 cm /V.s (d) 900 cm2/V.s
answer using the codes given below the lists: KVS TGT (WE)- 2014
List-I List-II
A. n-type semiconductor 1. Middle of band IES-2005
gap Ans. (c) :
B. p-type semiconductor 2. Above Mobility Si Ge Ga As
conduction band (µ)
C. Intrinsic 3. Near but below e– cm 2 cm 2 cm 2
semiconductor conduction band 1300 3800 8500
D. Degenerate n-type 4. Near but above mobility V − sec V − sec V − sec
semiconductor valence band (µn )
Codes: Holes
A B C D cm 2 cm 2 cm 2
mobility 500 1800 400
(a) 1 2 3 4 V − sec V − sec V − sec
(b) 3 4 1 2 (µP)
(c) 1 4 3 2 µn 2.6 2.1 21.35
(d) 3 2 1 4
IES-2005 µP
Ans. (b) : So, at room temperature i.e. at
cm 2
T = 300ºK, µ P = 1800 for germanium.
V- s
137. The diffusion of both electrons and holes
occurs in a semiconductor (with q = charge of
electron/hole; Dn, Dp = diffusion constant for
electrons/holes ∂n/∂x, ∂p/∂x = gradient for
(a) In N-type semiconductor Fermi energy level is electrons/holes). What is the total diffusion
above the donor energy and below the conduction band. current (Jdiff)?
Mathematically → ∂n ∂p
(a) qD n + qD p
N  ∂x ∂x
E f = E c − kT ln  C 
 ND  ∂  ∂n  ∂  ∂p 
(b) qD n   + qD p  
(b) In P-type Semiconductor the Fermi Energy level is ∂x  ∂x  ∂x  ∂x 
just below the acceptor energy level and just above the ∂  ∂n  ∂  ∂p 
maximum energy level of valence band. (c) qD n   − qD p  
∂x  ∂x  ∂x  ∂x 
Mathematically-
∂n ∂p
N  (d) qD n − qD p
E F = E V + KT ln  V  ∂x ∂x
 NA  IES-2004

Ans. (d) : Total diffusion current (Jdiff) due to both Ans. (c)
electrons and Holes is given as→
J diff = (J n )diff + (J P )diff
dn
Q ( J n )diff = D n .q
dx
dn
Q ( J P )diff = − D P .q
dx Above diagram of indirect band gap semiconductor
Now→ In an indirect band gap semiconductor, electron
dn dp transition across energy gap-
J diff = D n q.
− D P .q. We observed-
dx dx When electron falling C.B to V.B, this type of transition
For initially small length first in come to trapped energy state, then goes to
∂n ∂P valence band so the momentum of electron change then
J diff = qD n
− qD P velocity may also change so kinetic energy of electron
∂x ∂x
change as well as potential.
138. Consider the following statements this energy is liberated as 99% heat energy and 1% light
The intrinsic concentration of a semiconductor energy.
1. depends on doping the direction of falling electron will not change (C.B. to
2. increases exponentially with decrease of V.B.)
band gap of the semiconductor
3. increases non-linearly with increase of 140. Match List-I (Equation) with List-II (Relation
temperature between/Description) and select the correct
4. increases linearly with increase of answer using the codes given below the lists:
temperature List-I List-II
Which of the statements given above are A. Continuity equation 1. Relates diffusion
correct? constant with
(a) 1, 2 and 3 (b) 1 and 3 mobility
(c) 2 and 3 (d) 2 and 4 B. Einstein's equation 2. Relates charge
IES-2004 density with
Ans. (c) : The intrinsic concentration is known as- electric field
C. Poisson's equation 3. Relates flow with
− E go
rate of change of
n i2 = A 0 T 3e KT
concentration in
Where- space
A0 → material constant which is independent of D. Diffusion equation 4. Rate of change of
temperature. minority carrier
T → Temperature (°K) density with time
E g o →Energy gap at 0ºK Codes:
3
A B C D
(a) 4 1 3 2
(I) n i ∝ T 2
(b) 4 1 2 3
Intrinsic concentration increases non-linearly with (c) 1 4 2 3
increase of temperature. (d) 1 4 3 2
− E go
IES-2004
(II) n i ∝ e 2KT
Ans. (b) :
Intrinsic concentration increases exponentially with • Continuity equation: based on rate of change of
decrease of band gap of the semiconductor. minority carrier density with respect to time...
139. Consider the following statements: dn 1 dJ n
During an electron transition across the energy for e − → = − Rn + Gn
gap in an indirect energy gap material like dt q dx
silicon dp 1 dJ p
1. the momentum of the electron changes for Hole → =− − RP + GP
2. the direction of motion of the electron dt q dx
change Where-
3. the potential energy of the electron change Gn/GP = e/hole generation rate
4. the kinetic energy of the electron changes Rn/RP = e/hole- recombination rate
Which of the statements given above are Jn/JP = e/hole density.
correct? • Poisson's equation:-
(a) 1, 2 and 3 (b) 2, 3 and 4 dε p(x)
(c) 1, 3 and 4 (d) 1, 2 and 4 general form : =
dx kε 0
IES-2004
Where- 2. EF lies above ED as T → 0
ε = electric field. 3. EF = ED at some intermediate temperature
ρ (x) = space charge density (Charge/cm3) 4. EF is invariant with temperature.
K = dielectric constant where EF is Fermi energy and ED is donor level
ε 0 = permittivity of free space (8.854 ×10– energy. Which of these statements(s) is/are
14 correct?
F/cm)
2
(a) 1 and 2 (b) 2 and 3
d V P (c) 4 only (d) 1, 2 and 3
=−
dx 2
ε IES-2003
Poisson's equation related charge density with electric Ans. (d) : In N-type semiconductor-
field. n ≈ ND
• Diffusion equation-
− (EC − Efn )
dn ND = N C e kT
for e– Jn(diff) = q Dn.
dx − ( E −E )
ND C fn
dp = e kT
for hole JP (diff) = – q Dp NC
dx
total diffusion = Jn(diff) + Jp(diff) taking ln both side-
dn dn  N  E − E fn
J diff = q D n − q Dp ln  D  = C
dx dx  NC  kT
• Einstein equation: E C − E fn = kT ln (N C / N D )
D n D p KT T(k) From this equation we observed-
= = = VT = Volt
µn µp q 11600 (i) Ef lies below ED at T = 300ºK
diffusion equation relates flow with rate of change of (ii) at T = 0ºK
concentration in space. Ec – Efn = 0
141. Consider the following statements for an n-type E C = E fn
semiconductor: i.e fermi level lies at EC which is above ED
1. Donor level ionization decrease with (iii) If T ↑ , Efn fermi energy level goes down and at the
temperature some intermediate temperature, It may lie at ED
2. Donor level ionization increases with (iv) Fermi energy level is dependent of temperature.
temperature
3. Donor level ionization is independent of 143. Assume ni = 1.45 × 1010/cm3 for silicon. In an n-
temperature type silicon sample, the donor concentration at
4. Donor level ionization increases as Ep 300 K is 5 × 1014/cm3 and corresponds to 1
(donor energy level) moves towards the impurity atom for 108 silicon atoms. The electron
conduction band at a given temperature. and hole concentrations in the sample will be
Which of these statements is/are correct? (a) n = 5 × 1014/cm3, p = 4.2 × 105/cm3
(a) 1 only (b) 2 only (b) n < 5 × 1014/cm3, P > 4.2 × 105/cm3
(c) 2 and 4 (d) 3 only (c) n > 5 × 1014/cm3, p < 4.2 × 105/cm3
IES-2004 (d) n < 5 × 1014/cm3, p < 4.2 × 105/cm3
Ans. (c) : IES-2003
Ans. (c) : We know-
Electrical Neutrally Equation-
ND + p = NA + n
ND → Donor atoms (+Ve) p → Hole (+Ve)
NA → Accepter atoms (–Ve) n → electron (–Ve)
• At T = 0ºK the N-type S.C behaves like as perfect In other words-
insulator total positive atom = total negative atom
• At 300º K the 5th electron of all impurity atom will In N-type semiconductor-
be existing in Donor energy level. ND + p = NA + n ⇒ ND + p ≈ n
• As the temperature rise these electrons are moved n ≥ ND
to conduction band up to 100K. i.e. all the donor
atoms are ionized. n ≥ 5 ×1014 / cm3
Hence if we increase temperature donor level ionization We know
will increase upto room temperature (T=300K) then all Mass action law-
the ionization is completed at the donor energy level. n.p. = (ni)2
142. Consider the following statements for an n-type (n )2
p= i
semiconductor: n
1. EF lies below ED at a room temperature (T).
In N-type semiconductor- Ans. (d) : We know-
n ≈ ND B.I
VH =
(n i ) 2 ρ.w
p<
ND So,
Hall voltage (VH) ∝ magnetic field (B)
p<
(1.45 ×10 )10 2
(VH) ∝ Current (I)
5 × 1014 1
( VH ) ∝
2.1025 × 1020 width (w)
p<
5 × 1014 1
VH ∝
p < 4.2 × 105 cm −3 ρ (Charge density)
144. The resistivity at room temperature of intrinsic 1
silicon is 2.3 × 103Ωm and that of an n-type • According to option VH is not proportional to  d 
extrinsic silicon sample is 8.33 × 10–2 Ωm. A
bar of this extrinsic silicon 50 × 100 mm and a 146. The conductivity of a semiconductor crystal due
steady current of 1 µA exists in the bar. The to any current carrier is NOT proportional to
voltage across the bar is found to be 50 mV. If (a) mobility of the carrier
the same bar is of intrinsic silicon, the voltage (b) effective density of states in the conduction
across the bar will be about band
(a) 1400 V (b) 140 V (c) electronic charge
(c) 14 V (d) 1.4 V (d) surface states in the semiconductor
IES-2003 IES-2002
Ans. (a) : We know- Ans. (d) : We know-
BI Conductivity of semiconductor crystal-
Hall voltage (VH) =
ρW σ = σn + σp
1 σ = n qµn + p qµp
Hall coefficient (RH) =
Ch arg e density ( ρ ) σ = (nµn+pµp).q
Where-
B.I
VH = RH µn → Mobility of electron
W µp → Mobility of Hole
Where,
n → Concentration of electron
B → Magnetic field
I → Current through semiconductor p → Concentration of Hole
ρ → Charge density (ρ = n.q) q → Charge of electron & Hole.
W → Width of semiconductor Hence, Conductivity is not proportion to surface states
1 in the semiconductor crystal.
VH ∝ 147. Excess carriers are generated in a sample of
σ
N-type semiconductor by shining light at one
VH ∝ R H end. The current flow in the sample will be
Hence voltage across intrinsic semiconductor bar is made up of
Vi R i (a) diffusion flow of carriers
= (b) drift flow of carriers
Ve R e
(c) both diffusion and drift flow of carriers
Vi 2.3 ×10 Ωm
3
(d) neither diffusion nor drift flow of carriers
=
50 × 10 V 8.33 × 10−2 Ωm
−3
IES-2002
50 × 10−3 × 2.30 ×103 Ans. (a)
Vi =
8.33 × 10−2
115
Vi = × 102 = 1380.5V
8.33
Vi ≈ 1400V
145. A semiconductor specimen of breadth d, width If photon is incident on the surface of N-type
w and carrying current I is placed in a semiconductor, it will be absorbed by this material, the
magnetic field B to develop Hall voltage VH in a covalent bond near the illuminated surface, as a result,
direction perpendicular to I and B. VH is NOT
proportional to electron hole pair generated by breaking covalent
(a) B (b) I (c) 1/W (d) 1/d bonds. There are high Concentration near to
IES-2003 illuminated surface, there exist concentration gradient.
148. Consider two samples of silicon semiconductors Ans. (a) : Unit of mobility (µ) -
identical in all respects except that one is V
uniformly doped with 1015 cm–3 donor impurity µ= d
atoms (sample A), and the other is non- E
uniformly doped with donors from one side Where- Vd → drift velocity
(sample B), such that let a = 1 (nm)–1 and N0 = E → electric field
1017 cm–3. µ=
m / sec
⇒ m 2 / V − sec
Consider the following statements: V/m
1. Sample A will not have any current at
equilibrium but current will flow out of µ = m 2 V −1 s −1
sample B 151. The Haynes-Shockley experiment enables one
2. Both samples will have built-in electric to determine the
field (a) diffusion coefficient of majority carriers
3. Sample A will have zero built-in electric (b) effective mass of the minority carriers
field whereas sample B will have a (c) mobility of the minority carriers
constant built-in electric field (d) lifetime of the majority carriers
4. No current will flow at equilibrium IES-2002
from either sample A or sample B. Ans. (c) : In semiconductor physics, the Haynes
Which of these statements are correct ? Shockley experiment was an experiment that
(a) 1 and 2 (b) 1 and 3 demonstrated that diffusion of minority carrier in a
(c) 1 and 4 (d) 3 and 4 semiconductor could result in current, the experiment
IES-2002 can be used to measure-
Ans. (d) : Any semiconductor is electrically neutral 1. Carrier mobility. 2. Carrier life time.
that means N-type, P-type and intrinsic semiconductor 3. Diffusion coefficient.
is also electrically neutral at equilibrium. i.e. there is no 152. The Hall constant in a p-type Si bar is given by
current component exists at equilibrium. Other than 5 × 103 cm3/coulomb. The hole concentration in
this due to doping, there is Non uniform distribution of the bar is given by
charge carrier exist due to which built in electric field (a) 1.00 × 1015/cm3 (b) 1.25 × 1015/cm3
15 3
will exist in sample B. (c) 1.50 × 10 /cm (d) 1.6 × 1015/cm3
IES-2002
149. Consider the following statements:
Ans. (b) : Given data-
The temperature dependence of resistivity of a RH = 5×103 cm3/Coulomb.
sample of N-type silicon is based upon carrier
concentration and carrier mobility variations 1 1
Hall coefficient (RH) ⇒ =
with temperature because ρ p.q
1. the resistivity of silicon increases with Where- q → Carrier charge
temperature p → Hole concentration
2. the mobility decreases with temperature 1
3. the carrier concentration increases with p=
temperature R H .q
4. the resistivity of silicon decreases with 1
temperature. p= −19
cm −3
5 × 103 ×1.6 × 10
Which of these statements are correct? p = 0.125 ×1016
(a) 1, 2 and 3 (b) 2, 3 and 4
(c) 1 and 2 (d) 3 and 4 p = 1.25 ×1015 cm −3
IES-2002 153. In an extrinsic semiconductor, the Hall
Ans. (b) : coefficient RH
• Semiconductor have N.T.C. of Resistance. (a) increases with increase of temperature
NTC → (Negative temperature Coefficient) (b) decreases with increase of temperature
If we increase temperature, Resistivity will decrease. (c) is independent of the change of temperature
• If temperature increase, there will be vibration in (d) changes with the change of magnetic field
atom called atomic vibration so relaxation time IES-2002
decreases. Ans. (c,d) : We know -
Hence mobility decrease. 1
RH =
T↑ ↓ µ ∝τ ↓ n.q
• Intrinsic carrier concentration (ni ∝T 3/2) Where n is the majority charge carrier concentration, As
as T ↑ then n i↑ we know majority carrier is independent of temperature
variation so Hall coefficient (RH) is independent of
150. The unit of mobility is temperature.
(a) m2 V–1 s–1 (b) mV–1 s–1
–1 W
(c) Vsm (d) Vms–1 RH = × VH
IES-2002 B.I

Where- 156. For which of the following semiconductors,
VH → Hall voltage resistance does not follow Ohm's law over some
W → Width of semiconductor. specific range of the applied voltage?
B → Magnetic flux density. 1. Germanium
2. Gallium arsenide
I → Current.
3. Indium phosphide
1 Select the correct answer using the codes given
↑ RH ∝
B↓ below:
Hall coefficient changes with the change in magnetic (a) 1, 2 and 3 (b) 1 and 2
field. (c) 2 and 3 (d) 1 and 3
154. Consider a semiconductor bar having square IES-2001
cross-section. Assume that holes drift in the Ans. (a) : Germanium, Gallium arsenide and Indium
positive x-direction and magnetic field is phosphide are semiconductor materials.
applied perpendicular to the direction in which All semiconductor material is nonlinear element.
holes drift. The sample will show Semiconductor material does not follow ohm’s law
(a) a negative resistance in positive y-direction Ohm’s law is only applicable for linear and bilateral
(b) a positive voltage in positive y-direction element.
(c) a negative voltage in positive y-direction 157. Electron mobility and life-time in a
(d) a magnetic field in positive y-direction semiconductor at room temperature are
IES-2002 respectively 0.36 m2/V-s and 340 µs. The
Ans. (c) : diffusion length is
(a) 3.13 mm (b) 1.77 mm
(c) 3.55 mm (d) 3.13 cm
IES-2001
Ans. (b) : Given that-
Mobility (µ) = 0.36m2/V-s
carrier life time (τ) = 340µ sec
d We know-
• Force due to magnetic field on moving charge Einstein relation-
carrierrcan be given by D kT T(º K)
r r = VT = =
Fm = q(V × B) µ q 11600
In a X - axis direction given current by application of
kT
battery. D= .µ
In a Z - direction is magnetic field. q
By Fleming Left hand Rule- 1.380 × 10−23 × 300
In the above diagram shown the electric field is induced D= × 0.36
in the negative Y direction, the sample will show a +Ve 1.6 × 10−19
voltage in negative Y-direction and a Negative Voltage D = 93.15 × 10 −4 m 2 / sec
in +Ve Y-direction. D = 9.315×10–3 m2/sec
–19 We know-
155. As the Fermi energy of silver is 8.8 × 10
joule, the velocity of the fastest electron in Diffusion length is given as-
silver at 0ºK (Given: Rest mass of electron= 9.1 L = Dτ
× 10–31 kg) is
L= 9.315 × 10−3 × 340 ×10−6
(a) 3.33 × 105 m/s (b) 1.39 × 106 m/s
(c) 4.40 × 107 m/s (d) 3 × 108 m/s L = 3167.1× 10−9
IES-2002 L = 0.00177m
Ans. (b) : We know- L = 1.77mm
1 2 158. Consider the following statements:
E = mv
2 Impurity diffusion is used in semiconductor to
Where- E → Energy of electron control the conductivity. The nature of the
m → Mass of electron impurity profile should be such that the
v → Velocity of electron 1. impurity concentration decreases with
2E diffusion depth.
v =
2
2. profile result in an internal electric field.
m 3. impurity concentration is homogeneous
2 × 8.8 × 10−19 with no internal electric field.
v =
2
9.1× 10−31 which of these statements are correct?

v 2 =1.93 × 1012 (a) 1, 2 and 3 (b) 1 and 3
(c) 2 and 3 (d) 1 and 2
v = 1.39 ×106m/s IES-2001
Ans. (d) : The impurity concentration is non (n i ) 2
homogeneous in diffusion. P=
the diffusion hole-current density (Jp) is proportional to ND
the concentration gradient and is given by.
dp
J p = −qD p
dx
Where Dp is called the diffusion constant for hole.
Diffusion electron current density
dn
J n = qD n
dx
159. Which of the following statements relate to the
Hall effect?
1. A potential difference is developed across a
current-carrying metal strip when the strip
is placed in a transverse magnetic field.
2. The Hall effect is very weak in metals but
is large in semiconductors. If N D↑ (Increase) the P↓ (decrease) due to
3. The Hall effect is very weak in recombination of hole and electron both concentration
semiconductors but is large in metals. will maintain below the Intrinsic concentration (ni)2
4. It is applied in the measurement of the value.
magnetic field intensity. 161. Match List-I with List-II and select the correct
Select the correct answer using the codes given answer using the codes given below the lists:
below: List-I List-II
(a) 1, 2 and 3 (b) 2 and 4 A. Drift current 1. Law of
(c) 1, 3 and 4 (d) 1, 2 and 4 conservation of
IES-2001 charge
Ans. (d) : When a current carrying specimen (Metal or B. Einstein's equation 2. Electric field
conductor) is placed in a transverse magnetic field, then C. Diffusion current 3. Thermal voltage
an electric field is introduced in the direction D. Continuity equation 4. Concentration
perpendicular to both, current and magnetic field, this gradient
effect is known as hall effect. Codes:
A B C D
1 1
• Hall coefficient (RH) = = (a) 2 1 4 3
ρ nq (b) 4 3 2 1
In a metal free electron is more (c) 4 1 2 3
1 (d) 2 3 4 1
↓ RH = IES-2000
n↑q Ans. (d) : Drift current- Drift current is force
↓ R H ∝ VH ↓ phenomena current flow due to apply electric field.
the Hall effect is very weak in metals but large in (B) Einstein’s equation-
semiconductor. It gives, the relationship between diffusion constant,
• Hall effect is used for measurement of magnetic flux mobility & thermal voltage.
density as well as magnetic field intensity. D kT T(º k)
= VT = = Volt
160. For the n-type semiconductor with n = ND and µ q 11600
p = n i2 /N D , the hole concentration will fall (C) Diffusion Current-
below the intrinsic value because some of the Diffusion is mainly due to concentration gradient-
holes dp
(a) drop back to acceptor impurity states J diff ∝ q.
(b) drop to donor impurity states dx
(c) virtually leave the crystal Concentration gradient.
(d) recombine with the electrons (D) Continuity equation-
Continuity equation is based on law of conservation of
IES-2001
charge.
Ans. (d) : Mass action law →
dn 1 djn
At thermal equilibrium, product of electron = − R n + Gn
concentration and hole concentration remain constant, dt q dx
and it is equal to square of intrinsic concentration. 162. Consider the following statements:
n.p = (n i )2 If an electric field is applied to an n-type
for N-type semiconductor- semiconductor bar, the electrons and holes
move in opposite directions due to their
n ≈ ND opposite charges. The net current is
1. due to both electrons and holes with (iii) Bismuth (Bi) (iv) antimony (Sb)
electrons as majority carriers these elements have five electron in their outer most
2. the sum of electrons and hole currents. electron shell (there are five valence electrons).
3. the difference between electron and hole 165. Consider the following statements regarding a
current. semiconductor:
Which of these statements is/are correct? 1. Acceptor level lies close to the valence
(a) 1 alone (b) 1 and 2 band
(c) 2 alone (d) 3 alone 2 Donor level lies close to the valence band
IES-2000 3. N-type semiconductor behaves as an
Ans. (b) : The Net current (In N-type semiconductor) insulator at zero Kelvin
direction due to movement of electron (majority carrier) 4. P-type semiconductor behaves as an
is opposite to the flow of electron direction. insulator at zero Kelvin
Current direction due to movement of Hole (minority Of these statements
carrier) is same to the hole flow. (a) 2 and 3 are correct (b) 1 and 3 are correct
(c) 1 and 4 are correct (d) 3 and 4 are correct
IES-1998
Ans. (b,c) :
Total net current in semiconductor - I = In + I P

163. At very high temperature, the extrinsic
semiconductors become intrinsic because
(a) of drive-in diffusion of dopants and carriers.
(b) band to band transition dominates over • The energy band diagram of both N-type and P-type
impurity ionization semiconductor is shown above.
(c) impurity ionization dominates over band to • N-type semiconductor -
band transition • Intrinsic semiconductor doped with pentavalent
(d) band to band transition is balanced by Impurity or donor Impurity is called as N-type
impurity ionization semiconductor.
IES-1998 • From the energy band diagram, Donor Energy level
Ans. (b) : (Ed) closer to the conduction band.
Temp Impurity Breaking Hole • At 0ºk there will be no thermal Energy so no co-
(ºk) Ionization of Co- generatio valent bond can be broken & no free electrons will
valant n or Band be at conduction band. So no conductivity hence at
band or transition 0K n-type Extrinsic semiconductor also behaves at
free e– e– perfect Insulator.
300 ºk 10 e –
10 e –
10 Holes n>p
P-type semiconductor -
400 ºk 10 e –
100 e –
100 Holes n≥p • In p-type semiconductor trivalent doping is used.
600 ºk 10 e– 1 k e– 1k Holes n≈p • The acceptor energy level discrete energy level just
1 ºk 10 e –
2k e –
2k Holes n=p above the valence band.
Note- Everything data (EHP generation) is assumed. • At 0 K the P-type semiconductor behaves like a
• At very high temperature (100ºK) Extrinsic perfect insulator.
semiconductor behave like as intrinsic 166. If the energy gap of a semiconductor is 1.1 eV,
semiconductor because band to band transition is then it would be:
more dominant compare to impurity ionization. (a) opaque to the visible light
EHP generation >> Impurity Ionization Dominant (b) transparent to the visible light
164. Which of the following elements act as donor (c) transparent to the ultraviolet radiation
impurities? (d) opaque to the infrared radiation
1. Gold 2. Phosphorus IES-1998
3. Boron 4. Antimony Ans. (a) :
5. Arsenic 6. Indium Where→
Select the correct answer using the codes given Eg → Energy gap
below: λ C → Wavelength of the light.
Codes :
(a) 1, 2 and 3 (b) 1, 2, 4 and 6 1.24
(c) 3, 4, 5 and 6 (d) 2, 4 and 5 λC = (µm)
Eg
IES-1998
at, Eg = 1.1eV
Ans. (d) : The group V element that often serve as
1.24
donor impurity include λC =
(i) Arsenic (As) (ii) Phosphorus (P) 1.1

λ C = 1.13 µm  x1   x2 
So, Cs erfc   = Cs erfc  
Visible light lies between 0.38 µm to 0.76µm. Hence  2 Dt   2 Dt 
 1   2 
Eg = 1.1eV will be opaque to the visible light.
x1 x2
167. The carrier mobility in a semiconductor is 0.4 =
m2/vs. Its diffusion constant at 300 K will be (in 2 dt1 2 dt 2
M2/s) x1 x
(a) 0.43 (b) 0.16 = 1
(c) 0.04 (d) 0.01 t 1 t2
IES-1998 Given that,
Ans. (d) : Relationship between diffusion constant and x1 = x1
mobility (Einstein relationship) x 2 = 2x1
Dn DP t1 = 1hour , t2 = ?
= = VT
µn µP x1 2x1
=
Where, 1 t2
Dn → Diffusion constant for e –
t2 = 2
µ n → Mobility for e–
DP → Diffusion constant for hole. t 2 = 4 hour
µ P → Mobility for hole. 169. Given that the band gap of cadmium sulphide
kT is 2.5 eV, the maximum photon for electron
VT = , k → Boltz man constant hole pair generation will be
q (a) 5400 µm (b) 540 µm
k = 1.38×10–23J/ºK (c) 5400 Å (d) 540 Å
q = 1.6 ×10–19C IES-1998
Now Ans. (c) : Given that
1.38 × 10−23 j/º k Eg = 2.5eV
VT = Eg = 2.5 × 1.6 ×10–19J
1.6 × 10−19 C
We know that
T
VT = hc
11600 Eg = ,
at room temperature, T = 300ºk λ
hc
So, λ=
300 Eg
VT =
11600 where h = 6.626×10–34m2kg/sec c = 3×108m/s
VT = 0.026V 6.626 ×10−34 × 3 × 108
Now, λ= =4.9695×10–7
2.5 ×1.6 ×10−19
We know that
D = µ × VT λ ≈ 5400 A
º
D = 0.4 × 0.026 Hence, option C is correct.

D = 0.0104 m 2 / s 170. By increasing temperature, the electrical
168. In a wafer, a junction depth of x1 is achieved by conductivity would:
a constant source diffusion process of 1 hour (a) increase in metals as well as in intrinsic
diffusion time. How long should the diffusion semiconductors
process continue, if a junction depth of 2x1 is to (b) increase in metals but decrease in intrinsic
be achieved? semiconductors
(a) 2 hours (b) 4 hours (c) decrease in metals but increase in intrinsic
(c) 5 hours (d) 7 hours semiconductors
IES-1998 (d) decrease in metals as well as in intrinsic
semiconductors
Ans. (b) : Dopant concentration
IES-1997
 x 
C(x, t) = Cs erfc   Ans. (c)
 2 Dt  • In metal as we are increasing temperature
Where Cs is the surface concentration (at x = 0) conductivity will decreases because
• erfc stand for the complementary error function metal have PTC (Positive temperature coefficient)
• D is the diffusion constant. of Resistance.
• x is the distance T ↑, R ↑, R ∝ ρ (Re sistivity)
• t is diffusion time 1
surface that dopant concentration is means C is same in ↑ ρ (Resistivity) =
both case ↓ σ(Conductivity)

Hence, 173. Which one of the following statements with
In metal as we increase temperature conductivity will reference to effective mass is incorrect?
decreases. (a) It is a function of wave vector K.
• In Intrinsic semiconductor we increase temperature (b) It can be positive or negative
conductivity will increases because intrinsic (c) It is different from free mass because of
semiconductor have NTC (Negative temperature lattice interaction
coefficient) of Resistance. (d) Its concept is applicable only to electrons and
• T ↑, R ↓ not to holes.
IES-1996
↓ R ∝ ρ (Resistivity) ↓ Ans. (a) : The effective mass is quantity that is used to
1 simplify band structures by modeling the behavior of a
↓ ρ(Resistivity) = free particle with that mass. It can be positive or
↑ σ(Conductivity)
negative.
Hence, In semiconductor we are increasing temperature • It is different from free mass because of lattice
conductivity will Increases. interaction
• This concept is applicable only to electrons and not
for holes.
174. Hall effect is observed in a specimen when it
(metal or a semiconductor) is carrying current
and is placed in a magnetic field. The resultant
electric field inside the specimen will be in
(a) a direction normal to both current and
magnetic field
171. The allowed energies for the electro system of (b) the direction of current
an atom are determined using (c) a direction anti parallel to magnetic field
(a) Einstein's theory of relativity (d) an arbitrary direction depending upon the
(b) Planck's theory conductivity of the specimen
(c) Schrodinger's equation IES-1996
(d) Pauli exclusion principle Ans. (a) : If current carrying specimen (Metal or
IES-1997 semiconductor) is placed in transverse Magnetic field,
Ans. (b) : The allowed energies for the electro system then an electric field is Introduced in the direction
of an atom are determined using Planck's theory. When perpendicular to both. This effect is known as hall effect.
an electric current is passed through a gas, some of
175. In a p-type semiconductor, the conductivity
molecules move from their ground energy state to an
excited state that is farther away from their nuclei. due to holes (σ p ) is equal to (e = charge of hole,
When the electrons return to the ground state, they emit µp = hole mobility, p = hole concentration).
energy of various wavelength which exhibits various p.e µ
energy states. (a) (b) p
µp p.e
172. According to classical free electron theory, the
relaxation time and mean free path for 1
(c) p.e.µp (d)
aluminum are respectively 0.75 × 10–10 s and p.e.µ p
0.88 nm. Give that the density of aluminium is IES-1996
2700 kg/m3 and the atomic weight of
aluminium is 26.98, the resistivity of Ans. (c) : Conductivity is given mathematically
aluminium is σ = nqµ n + pqµ p
(a) 1.73 × 10–8 Ωm (b) 1.47 × 10–8 Ωm Where → n → electron concentration
(c) 2.62 × 10–8 Ωm (d) 4.32 × 10–8 Ωm q → magnitude of charge
IES-1996 µn → mobility of electrons
Ans. (a) : Given data, µp→ mobility of hole
Relaxation time (τ) = 0.75 ×10–10 sec p → Hole concentration
Mean free path for aluminium (λ) = 0.88 nm For P-type semiconductor.
Aluminimum density (ρ) = 2700kg/m3 P >> n
Atomic weight of aluminium = 26.98 σ p ≈ pq µ p
We know
ne 2 τ 176. The minority carrier lifetime and diffusion
σ= constant in a semiconducting material are
m
respectively 100 microsecond and 100 cm2/s.
σ = 57.803 × 10 s 6
The diffusion length of the carrier is
1 1
ρ= = (a) 0.1 cm (b) 0.01 cm
σ 57.803 ×106 (c) 0.0141 cm (d) 1 cm
ρ = 1.73 × 10−8 Ω − m IES-1996
Ans. (a) : Given that- Ans. (a)
diffusion constant (D) = 100 cm2/s Conductor Semiconductor Insulator
carrier life time (τ) = 100 µsec.
We know-
Diffusion length (L) = Dτ
= 100 × 100 × 10−6
= 10×10×10–3 179. At room temperature, the current in an
L = 0.1cm intrinsic semiconductor changes in its
directions. This phenomenon is due to
177. The conductivity of an intrinsic (a) holes (b) electrons
semiconductor is (symbols have the usual (c) ions (d) holes and electrons
meanings). IES-1995
(a) generally less than that of a doped Ans. (d) :
semiconductor. • In Intrinsic semiconductor as we increases the
(b) given by σ1 = en i ( µ n − µ p ) temperature then conductivity will increases.
• At room temperature, intrinsic semiconductor will
(c) given by σ1 = en i ( µ n + µ p ) have equal number of holes and electron.
(d) given by σ1 = n i ( µ n + µ p ) • I = In + Ip
Where-
IES-1996 In→ Current due to electron in Intrinsic semiconductor.
Ans. (c) : The conductivity formula of an extrinsic Ip → Current due to hole in Intrinsic semiconductor
semiconductor is So,
σ = σ n + σP Any kind of change in current will be attributed both
σ = nqµ n + pqµ p holes and electrons.
180. Which one of the following is true with regard
Where- to photo emission?
n → electron concentration (a) Velocity of emitted electrons is dependent on
p → Hole concentration light intensity.
µn → Mobility of electron (b) Rate of photo emission is inversely
µp → Mobility of hole proportional to light intensity.
q → Charge of carrier (c) Maximum velocity of electrons increases with
In intrinsic semiconductor- decreasing wavelength.
n = p = ni (d) Both electrons and holes are produced.
Conductivity for intrinsic semiconductor will be- IES-1994
σ : = n i q.µ n + n i qµ p Ans. (c) :
hc
σ : = n i q µ n + µ p  E = λυ =
λ
178. Match List-I with List-II and select the correct As wavelength decreases, frequency increases and
answer using the codes given below the lists: maximum velocity of electron also increases.
List-I List-II 181. If a sample of germanium and a sample of
[List of Materials] [Energy-band silicon have the same impurity density and are
diagram] kept at room temperature.
(a) both will have equal value of resistivity
A. Conductor 1. (b) both will have equal negative resistivity
(c) resistivity of germanium will be higher than
that of silicon
B. Semiconductor 2. (d) resistivity of silicon will be higher than that
of germanium.
IES-1994
Ans. (d) :
C. Insulator 3.
• Consider the P-N diode for Ge 0.3 eV is the
breakdown voltage and in the case of silicon (Si) its
Codes : 0.7eV Since the Impurities are added in the same
A B C amount the bond due to the other atoms of the silicon
(a) 1 3 2 makes it resistive compared to the Ge.
(b) 3 1 2 • When a sample of germanium and silicon having
(c) 1 2 3 same impurity density are kept at room temperature
(d) 2 3 1 then, Resistivity of silicon will be higher than that of
IES-1995 Germanium.

182. When ne and nh are the electron and hole Electron from rest to 0.6c
densities, and µe and µh are the carrier 1
mobilities, then Hall coefficient is positive when ∆E = ∆γ m c 2 where γ =
2
(a) n h µ h > n eµ e (b) n h µ 2h > n e µ 2e  v
1−  
(c) n h µ h < n eµ e (d) n h µ 2h < n eµ e2 c
At rest condition
IES-1993
v
Ans. (b) : The low field hall coefficient is =0
mathematically given as- c
n h µh 2 − n e µe2 ∴ γ2 = 1
RH = Electron has energy of 0.6c
| q | ( n h µ h + n e µe )
2
v
Now, for RH > 0 = 0.6
n h µ h − n e µe > 0
2 2 c
2
n h µ h 2 > n eµe2 v
  = 0.36
183. Which of the following will serve as a donor c
2
impurity in silicon?  v
(a) Boron (b) Indium 1−   = 0.64 = 0.8
(c) Germanium (d) Antimony c
9.31× 10−31 × ( 3 × 108 )
2
IES-1992
Ans. (d) : The group V elements that often serve as Now mc = = 0.5237 MeV
th 2
donor impurities include, Arsenic (As), phosphorus (P), 1.6 ×10−19

bismuth (Bi) and antimony (Sb). So, ∆E = ∆γ mc 2
These elements have five electrons in their outermost ∆E = ( γ 2 − γ1 ) mc 2 = (1 − 0.8) × 0.5237 MeV
electron shell (there are five valence electrons).
∆E = 0.105 MeV
184. n-type semiconductors
(a) are negatively charged Nearest to it is option ‘b’
(b) are produced when Indium is added as an 186. In the Fermi-Dirac statistics, the probability of
impurity to Germanium electron occupancy of an energy level equal to
(c) are produced when Phosphorus is added as an the Fermi level is
impurity to Silicon (a) 0 (b) 0.25 (c) 0.5 (d) 1.0
(d) none of the above IES-1992
IES-1992 Ans. (c) : Concept of fermi Dirac Function- It will
Ans. (c) : provide information about probability of finding
electron at any energy level at any temperature and
mathematically it can be given by following formula.
1
F(E) = (E − E F )
1+ e kT
• Where,
F(E) = probability of finding e–
at any energy level.
• Intrinsic semiconductor doped with pentavalent E = Energy
Impurity or donor Impurity is called as N-type EF = Fermi energy level (eV)
semiconductor According to question-
• Pentavalent Impurity or donor impurity
Q At, E = E F
(i) Phosphorus (P)
(ii) Arsenic (As) at, T = 0º k
(iii) Antimony (Sb)
(iv) Bismuth (Bi) 1
f(E) = (E − E F )
• Phosphorous is pentavalent and silicon is
tetravalent. Then for it is doped with pentavalent 1+ e kT
impurity, it forms a N-type semiconductor. 1

f (E) =
185. The energy required to change the speed of one 2
electron from rest to 0.6c is nearly: f (E) = 0.5
(a) 0.085 MeV (b) 0.13 MeV
1
(c) 0.26 MeV (d) 0.37 MeV At E = EF , f (E) = (for any value of temperature).
IES-1992 2
Ans. (b) : The energy required to change the speed of Then fermi level represents the energy state with 50%
electron is given by probability of being filled electron.

187. The drift current velocity for holes in a 1 mm (a) Extrinsic semiconductor
length of silicon at 270C. when the terminal (b) pn junction
voltage is 10V. (Electron and hole mobility (c) Intrinsic semiconductor
constants are 1500cm2/V-sec. and 500cm2/V- (d) Excitons
sec. respectively). (e) Bi polar transistor
(a) -1500m/s (b) -500m/s CGPSC SO 14.02.2016
(c) 500m/s (d) 1500m/s Ans. (c) : A perfect semiconductor crystal containing
TNPSC AE- 2019 no impurities or lattice. defects is called Intrinsic
E 10V semiconductor.
Ans. (c) : Vn = −µ n =-1500cm2/V-sec × 192. In semiconductors, work function is defined as
l 1mm
= –1500 m/sec the
(a) difference between Valence band and the
E 10V Vacuum level
Vp = µ p = 500cm 2 / V − sec× (b) difference between Valence band and
l 1mm Conduction band
= 500m / sec (c) difference between Vacuum level and
188. Temperature co-efficient is expressed as conduction band
1 1 (d) difference between Fermi and Vacuum level
(a) α= . 1/ ohms 0 C (e) difference between Fermi and conduction
R 0 ∆T band
1 ∆R 0 CGPSC SO 14.02.2016
(b) α = . ohms / ohm / 0 C Ans. (d) : In semiconductors, work function is defined
R 0 ∆T as the difference between Fermi level and vacuum level.
∆R 0 193. Cathodoluminescence happens through
(c) α = ohms / 0 C (a) Excitation arising from the absorption of
∆T photons
R0 (b) Excitation by bombardment with a beam of
(d) α = ohm / 0C electrons
∆T
TNPSC AE- 2019 (c) Excitation resulting from the application of an
electric field
Ans. (b) : Temperature co-efficient– The change in
(d) Excitation arising from dissipation of
resistance per ohm for change in temperatures of t0C
electrons
from 00C.
(e) Injection of minority carriers
RT = R0 (1+ α∆T) CGPSC SO 14.02.2016
RT = R0 + R0 α∆T
Ans. (b) : Cathodoluminescence happens through
R − R0 ∆R 0 Excitation by bombardment with a beam of electrons.
α= T = ohms/ohm/oC
R 0T R 0 ∆T Cathodoluminescence is an optical and electromagnetic
189. Ripple factor of halfwave rectifier is phenomena in which electron impacting on a luminance
(a) 1.21 (b) 1.11 material.
(c) 0.48 (d) 0.81 194. Which combination is not used in hetrojunction
TNPSC AE- 2019 semiconductor?
Ans. (a) (a) n-N doping (b) p-P doping
Half wave Centre-tap Bridge (c) n-P doping (d) P-n doping
(e) n-P-n doping
Average Vm 2Vm 2Vm CGPSC SO 14.02.2016
value Ans. (e) : Hetrojunction semiconductor used n doping
π π π
and p doping combination.
RMS Vm Vm Vm npn doping combination is not used in hetrojunction
Value
2 2 2 semiconductor.
Ripple 1.21 0.482 0.482 Homojunction is junction between the same material
factor with same crystalline structure. A heterojunction is
PIV Vm 2Vm Vm junction between different material or between the same
material, but with different crystalline structure.
190. Temperature range for Ge transistors 195. Number of electron-hole pairs generated per
(a) –25º C to +175º C (b) –65º C to +75º C incident photon is called ________.
(c) –65º C to +175ºC (d) –25º C to +75ºC (a) Power efficiency
Nagaland PSC- 2018, Diploma Paper-II (b) Luminescence efficiency
Ans. (b) : A Germanium transistor are operated over the (c) Optical efficiency
temperature range from -65ºC to +75ºC. (d) Frequency response
191. A perfect semiconductor crystal containing no (e) Quantum efficiency
impurities or lattice defects is called _____. CGPSC SO 14.02.2016
Ans. (e) : Quantum efficiency is the ratio of the number (e)
of carriers collected by the solar cell to the number of
photons of a given energy incident on the solar cell.
So the number of the electron hole pairs generated per
incident photon is called quantum efficiency.
196. The method of raising a particle from lower
CGPSC SO 14.02.2016
energy state to higher energy state is called
Ans. (a) :
(a) Pumping
(b) pumping source
(c) population inversion
(d) optical pumping
(e) inelastic atom-atom collision
CGPSC SO 14.02.2016
Ans. (c) : Population inversion due extrinsic applied on
the semiconductor. So the method of raising a particle 199. Measurement of Hall coefficient in a doped
from lower state to higher energy state is called semiconductor enables the determination of:
population inversion. (a) Mobility of charge carriers
197. What is main advantage of ion implantation (b) Type of conductivity and concentration of
charge carriers
over diffusion for doping of semiconductors? (c) Temperature coefficient
(a) Ion implantation is non-destructive process (d) Thermal conductivity
(b) Ion implantation provides control on doping (e) Band gap of semiconductor
density and doping profile CGPSC SO 14.02.2016, IES-1994
(c) Ion implantation is cost effective process Ans. (b) : Measurement of Hall coefficient in a doped
(d) Ion implantation consumes less time semiconductor enables the determine types of
(e) Ion implantation is reliable and repeatable conductivity and concentration of charge carrier.
CGPSC SO 14.02.2016 V ×t
Ans. (b) : The main advantage of ion implementation RH = H
IH × B
over diffusion for doping of semiconductors is ion
implementation provides control on doping density and 200. In an intrinsic semiconductor, the mobility of
doping profile. Doping is define as impurity adding in electrons in the conduction band is
the semiconductor material. (a) Less than the mobility of holes in the valence
band
198. Which one predicts the intrinsic carrier density (b) Zero
in silicon? (c) Greater than the mobility of holes in the
(a) valence band
(d) Is equal to mobility of holes in valence band
(e) Is equal to mobility of holes in conduction
band
CGPSC SO 14.02.2016
Ans. (c) : In an intrinsic semiconductor, the mobility of
(b) electron in the conduction band is greater than the
mobility of holes in the valence band because electrons
exist centermost shell of atom.
µ n > µ p in valence band.
201. Consider the following statements: pure
germanium and pure silicon are examples of:
(c) 1. Direct band-gap semiconductors
2. Indirect band-gap semiconductors
3. Degenerate semiconductors of these
statements.
(a) 1 alone is correct (b) 2 alone is correct
(c) 3 alone is correct (d) 1 and 3 are correct
(d) (e) 2 and 3 are correct
CGPSC SO 14.02.2016
Ans. (b) : In an indirect bandgap semiconductor, the
maximum energy of the valence band occurs at a
different value of momentum to the minimum in the
conduction band energy eg. Silicon and Germanium
202. The electron and hole concentrations in an Ans. (a) : In direct band gap semiconductor bottom of
intrinsic semiconductor are ni and pi valence band and top conduction band occur same value
respectively. When doped with a p-type of momentum.
material, these change to n and p, respectively. In indirect band gap they occur different value of
Then: momentum.
(a) n + p = ni + pi (b) n + ni = p + pi
(c) np = nipi (d) n + pi = ni + p
(e) npi = nip
CGPSC SO 14.02.2016
Ans. (c) : The electron and hole concentration in an
intrinsic semiconductor are ni and pi respectively. When 205. Consider the following statements
doped with P type. The charge in np is S1: Silicon is indirect bandgap semiconductor
S2: Germanium is direct bandgap semiconductor
ni2
np = S3: Gallium Arsenide is direct bandgap
NA semiconductor
According to mass action law. S4: Indium Phosphide is indirect bandgap
semiconductor
np = n i pi
(a) S1 and S3 are correct
for an intrinsic semiconductor- n i = pi (b) S2 and S4 are correct
(c) S1, S2, S3 are correct
So np = n i 2 (d) S2 and S3 are correct
203. If the temperature of an extrinsic (e) Only S1 is correct
semiconductor is increased so that the intrinsic CGPSC SO 14.02.2016
carrier concentration is doubled, then: Ans. (a) : In direct bandgap semiconductor bottom of
(a) The majority carrier density doubles valence band and top conduction band occur same value
(b) The minority carrier density doubles of momentum.
(c) Both majority and minority carrier densities (i) Indirect bandgap
double Ex- Si, Ge, AlAs
(d) The majority carrier density doubles and (ii) Direct bandgap
minority carrier density is halved Ex- Gallium Arsenide etc.
(e) The minority carrier density is doubles and 206. 1 cm3 of pure Germanium at 20ºC contains
majority carrier density is halved about 4.2×1022 atoms, 2.5×1013 free electrons
CGPSC SO 14.02.2016 and 2.5×1013 holes. 0.001% of Arsenic doping
Ans. (c) : If the temperature of an extrinsic donates an extra 1017 free electrons in the same
semiconductor is increased so that the intrinsic carrier volume. The approximate number of holes in
concentration is doubled then one cm3 in the doped semiconductor under
equilibrium condition is :
(a) 6.25×109 (b) 2.5×109
9
(c) 10.5×10 (d) 1017
ISRO Scientist Engg.-2012
Both majority and minority carrier densities doubled. Ans. (a) : Given, ni = n = p = 2.5 ×1013
204. Which of the below statement is true for Band After Arsenic doping with extra 1017 free electrons
diagrams of semiconductors shown in fig -1 number of free electrons n = (2.5×1013) +1017
and fig-2? Here, Intrinsic concentration (ni) will remain same
By Mass-Action Law, n.p = n i2
{( 2.5 ×10 ) + 10 } × p = ( 2.5 ×10 )

13 17 13 2
p=
( 2.5 ×10 ) 13 2
(a) Band Diagram in Fig-1 is Direct and Fig-2 is ( 2.5 ×10 ) + 10

13 17
indirect Bandgap semiconductor

p = 6.25 × 109
(b) Band Diagram in Fig-2 is Direct and Fig-1 is
indirect Bandgap semiconductor 207. Silicon is not suitable for fabrication of light
(c) Both are Band Diagram of Direct Bandgap emitting diodes because it is :
semiconductor (a) An indirect band gap semiconductor
(d) Both are Band Diagram of Indirect Bandgap (b) A direct band gap semiconductor
semiconductor (c) A wide band gap semiconductor
(e) Both semiconductor are suitable for making (d) A narrow band gap semiconductor
LEDs and LASER diodes ISRO Scientist Engg.-2012
CGPSC SO 14.02.2016 Mizoram PSC IOLM-2010, Paper-II
Ans. (a) : (a) 1 Ω-cm (b) 10 Ω-cm
• Silicon has low efficiency because it has indirect (c) 0.1 Ω-cm (d) 100 Ω-cm
band gap it has very narrow bandgap. ISRO Scientist Engg. -2015
• The narrow band gap makes silicon useful in PV Ans. (c) : Given,
panels because it can absorb photons in all visible ND = 1017 atoms/cm3, µn = 700 cm3/V-s
spectrum and extending into infrared. The resistivity of doped Si
• Silicon has better temperature handling capacity 1 1
than germanium. ρ= =
σ nqµ n + 0
208. The band gap of elements arranged in
ascending order is : 1 1
= =
(a) Diamond, Ge, Si (b) Si, Ge, Diamond nqµ n N D qµ n
(c) Ge, Si, Diamond (d) Diamond, Si, Ge 1 1
ISRO Scientist Engg.-2012 ρ = 17 −19
=
Ans. (c) : The band gap of elements at 300K (room 10 × 1.6 × 10 × 700 1.6 × 7
temperature) ρ 0.1Ω − cm
Silicon (Si) = 1.1 eV 212. The electrical conductivity of a semiconductor
Germanium (Ge) = 0.67 eV increases when a radiation of wavelength
Diamond = 5.5 eV shorter than 1000 nm is incident on it. The
So, ascending order of band gap of elements = Ge < Si band gap of the semiconductor is:
< diamond. (a) 2.4 eV (b) 1.2 eV
209. Electric Field of 1 V/m is applied to a Boron (c) 3.4 eV (d) 4.0 eV
doped Silicon semiconductor slab having doping ISRO Scientist Engg. -2015
density of 1016 atoms/cm3 at 300 K temperature. Ans. (b) : Given, wavelength λ = 1000 nm = 1µm
Determine the approximate resistivity of the We know, Band gap of the semiconductor
slab. (Consider intrinsic carrier concentration of
1.24 1.24
Silicon at 300 K = 1.5 ×1010 /cm 3 Hole Mobility = Eg = =
λ ( in µm ) 1
500 cm2/Vs at 300 K; Electron Mobility =1300
cm2/Vs at 300 K). E g = 1.24 eV
(a) 0.48 Ω − cm (b) 0.35 Ω − cm
213. The graph below shows operating load line and
(c) 0.16 Ω − cm (d) 1.25 Ω − cm
I-V characteristic of a Schottky diode at two
ISRO Scientist Engg.-2018 different RF power levels. Under this bias
Ans.(d): Given, condition RF resistance of the diode:
E = 1V/m, NA = 1016 atoms/cm3, µn = 1300 cm2/V-s
µp = 500 cm2/V-s
1
ρ= σ = NAq µp
σ
= 1016×1.6×10–19×500 (a) Remains constant with the RF power level
σ = 0.8 / cm (b) Decreases with the increase of RF power
level
1 (c) Increases with the increase of RF power level
Now, ρ= = 1.25Ω − cm
0.8 (d) None of the above
ρ = 1.25 Ω − cm ISRO Scientist Engg. -2015
Ans. (c)
210. Electron mobility of the following intrinsic
elements in descending order is:
(a) GaAs, Ge, Si (b) GaAs, Si, Ge
(c) Si, Ge, GaAs (d) Ge, Si, GaAs
ISRO Scientist Engg. -2015 In the given graph the change of voltage is large for
Ans. (a) : Mobility at 300 K change in current from maximum to minimum value.
Intrinsic elements Electron Mobility (µn) The change in current large for large power.
GaAs 4600–8500 cm2/V-s Under this bias condition RF resistance of the diode
Ge 3800 cm2/V-s increases with increase of RF power level.
Si 1300 cm2/V-s 214. The conductivity of the intrinsic germanium at
Hence, the descending order of given elements is 300K is ______. When, ni at 300K = 2.5 × 1013
GaAs > Ge > Si. /cm and µn and µp in germanium are 3800 and
211. A sample of Si is doped with 1017 donor 1800 cm2/Vs respectively.
atoms/cm3. Considering electron mobility in the (a) 0.244 S/cm (b) 0.0224 S/cm
doped Si 700 cm3/V-sec, the approximate (c) 2.24 S/cm (d) 0.00224 S/cm
resistivity of the doped Si is: ISRO Scientist Engg.-2011
Ans. (b) : ni = 2.5 ×1013/cm, µn = 3800 cm2/V-s = 1.6×10–19×4.955×1014 ×400
q = 1.6×10-19C µ P = 1800 cm 2 / V − s σ = 0.0317
1 1
The conductivity of the intrinsic semiconductor (Ge), So, the resistivity ρ = =
σ = niq (µn+ µp) σ 0.0317
= 2.5 ×1013 ×1.6 ×10-19 (3800 +1800) ρ ≈ 31.25ohm − cm
= 4.00 ×10–6 (5600)
217. In a p-type Si at 300K and Na = 8×1015 cm–3,
σ = 0.0224 S / cm
variation of space-charge density in the
215. If a donor type impurity is added to the semiconductor as a function of surface
semiconductor, then at a given temperature, potential is plotted, then select the true
the Fermi Level statement for weak inversion region. Given
(a) Moves towards the center of the energy gap that ps and ns are hole and electron
(b) Moves towards the valence band concentrations at the surface.
(c) Moves towards the conduction band (a) ps > Na (b) ns < Na and ns > ps
(d) Doesn't change (c) ns < Na and ps < Na (d) ns > Na
ISRO Scientist Engg.-2016 ISRO Scientist Engg. -2020
Ans.(c): Effect of doping on the fermi level- The Ans. (b) : For weak inversion, electron concentration
fermi level in intrinsic semiconductor exists in the should be less than Na but more than hole concentration,
middle of valence band and the conduction band. When i.e. n s < N a and n s > Ps .
we add the donor type impurity to the semiconductor, 218. Acceptor impurity concentration of Si at 300K
then the fermi level moves towards the conduction is 1019 cm–3. Calculate the concentration of
band. donor impurity atoms that must be added so
that Si is n-type and the Fermi energy is 26
meV below the conduction band edge.
(Given : Effective density state Nc = 2.7×1019
cm–3 and Thermal voltage (VT) at 300 K is 26
mV)
(a) 1.5×1019 cm–3 (b) 3×1019 cm–3
E C + E V kT NC 19 –3
EF = − log (c) 10 cm (d) 2×1019 cm–3
2 q NV ISRO Scientist Engg. -2020
216. For the following energy band diagram, Ans. (d) : Given,
determine the approximate resistivity for x > L NA = 1019/cm3, NC =2.7×1019/cm2
portion of semiconductor. Eg = 1.12 eV, VT = 26mV, ND = ?
2
T = 300 K, µn = 600 cm /V-sec, µp = 400 cm / 2  NC 
E C − E F = kT ln  
V-sec, ni = 1010/cm3.  ND − NA 
NC
= e( C F )
E − E / kT
ND − NA
2.7 × 1019
= e 26mV / 26mV
ND − NA
(a) 11.00 ohm-cm (b) 15.75 ohm-cm
(c) 23 ohm-cm (d) 31.25 ohm-cm 2.7 ×1019
= N D − 1019
ISRO Scientist Engg. -2020 e1
Ans. (d) : Given,  2.7 × 1019 
ni = 1010/cm3, Eg = 1.12 eV, µP = 400cm2/V-s ND =   + 10
19
 2.7 
µ n = 600cm 2 / V − s, T = 300 K
 Ei − Ef 
N D = 2 ×1019 / cm3
 
Hole concentration, P = n i e  kT 
219. Waveform shown in the given figure is a ____.
 Eg / 4 
   Eg 
= (1010 ) e  kT 
Q E i − E f = 
 4 
 1.12 / 4 
= (1010 ) e 0.026 
 
(a) continuous signal

p = 4.955 × 1014 / cm 2 (b) noisy signal
We know, The conductivity (c) multivalued digital signal
(d) sawtooth signal
σ = q × p × µp
UPRVUNL AE -19.07.2021, Shift-II
Ans. (c) 222. Major part of the current in an intrinsic
semiconductor is due to
(a) Conduction - band electrons
(b) Valence - band electrons
(c) Holes in the valence band
(d) Thermally generated electrons
When the digital signal having more than two states TNPSC AE – 2018
then circuitry using signal are called multivalued digital KVS TGT (WE)-2016
signal. A digital signal is a pulse train i.e. a sequence of Ans. (a)
fixed-width square wave. • In pure semiconductor (or intrinsic semiconductor),
The digital signal can assume three possible states are the current which flow, consists of both electron and
called multivalued digital logic signal. hole current . Electron in conduction band can move
220. A bar of intrinsic germanium 5 cm long is through the material.
subjected to an electric potential of 12 V. If the • The current flow in intrinsic semiconductor is highly
velocity of electrons in bar is 75 m/s, then find temperature dependent.
mobility of electrons. • After flowing the current in intrinsic semiconductor,
(a) 31.25 cm2 /V-sec (b) 3.125 cm2 /V-sec the fermi energy level moves towards the
2
(c) 3125 cm /V-sec (d) 60.25 cm2 /V-sec conduction band.
UPRVUNL AE -19.07.2021, Shift-II 223. What is the conductivity when Hall effect
Ans. (c) : Given, coefficient is 5 and mobility is 5 cm2/V-sec?
(a) 100 S/m (b) 10 S/m
Vd = 75m/s = 7500 cm/s, V = 12V , d = 5 cm (c) 0.0001 S/m (d) 0.01 S/m
V 12 TNPSC AE - 2018
E= =
d 5 Ans. (c) : Given,
Vd Hall effect coefficient RH = 5
Mobility of electrons, µ = Mobility µH = 5 cm2/V-sec
E = 5 ×10–4m2/V-sec
7500 × 5 µ
= We know, conductivity σ = H
12 RH
µ = 3125 cm 2 / V − s
5 × 10−4
=
221. A 10 kΩ NTC thermistor has a Β values of 3455 5
for 250C and 1000C temperature range. σ = 10–4 S/m
Calculate its resistance value at 1000C.
σ = 0.0001 S / m
(a) 1 kΩ (b) 973 Ω
(c) 9.73 Ω (d) 97.3 Ω 224. The drift current velocity for electrons and for
UPRVUNL AE -19.07.2021, Shift-II holes in a 1 mm length of silicon at 27ºC when
the terminal voltage = 10 V is
Ans. (b) : Given,
(a) Vn = –1500 m/s and Vp = 500 m/s
T1 = 25ºC = 273+25 = 298K
(b) Vn = –500 m/s and Vp = 1500 m/s
T2 = 100ºC = 273 +100 = 373 K (c) Vn = 1500 m/s and Vp = –500 m/s
R1 = 10kΩ , B = 3455 (constant) (d) Vn = 500 m/s and Vp = –1500 m/s
R2 = ? TNPSC AE - 2018
Thermistor Equation, Ans. (a) : Given,
T ×T R  terminal voltage Vt = 10V
B( T1 / T2 ) = 2 1 × ln  1 
T2 − T1 length of silicon l = 1mm
 R2 
= 0.1 cm
373 × 298 10 ×103
3455 = × ln We know, the drift current velocity for electrons
373 − 298 R2 Vf
Vn = −µ n (Q µ n = 1500 approx )
111154 104 l
3455 = × ln
75 R2 10
= −1500 ×
10 4 0.1cm
2.33 = ln
R2 Vn = −1500 m / s
104 104 the drift current velocity for holes.
R 2 = 2.33 = V 10
e 10.277 VP = µ P t = 500 ×
R = 973.04 Ω l 0.1cm
2
R2 973Ω VP = 500 m / s

225. Find the wrong statement: specific heat of a 2eV 2 × 1.6 × 10−19 × 1
material is v2 = =
(a) constant me 9.1× 10−31
(b) heat capacity per unit mass 3.2
v2 = × 1012 = 0.351648 ×1012
(c) extrinsic property 9.1
(d) of units as Joule/Kg-K
v = 0.351648 ×1012 = 0.592999 × 106
Mizoram PSC AE/SDO 2012-Paper-I
Ans. (c) v 600km / sec
• Specific heat refers to the heat capacity per unit 229. Which of the following is the correct
mass of pure material. relationship between the band gap of a
• It is defined as the amount of heat needed to material used in a photo detector and the
increase the temperature of 1kg of a material. energy of incident photon-
• Its unit is expressed in terms of Joule/Kg-K or (Where Eg = band gap energy, h = planck's
Joule/Kg ºC. constant, c = speed of light, λ = wave length of
• It has an intensive property i.e. specific heat incident photon, v = frequency of incident
capacity changes with change in the material's type, photon)
phase and size. (a) hv ≥ E g (b) hv 2 / λ ≥ E g
• Specific heat can expressed at constant volume or
(c) 1/ 2hv ≤ E g (d) E g ≥ hc / λ
constant pressure and it is constant for every substance.
226. Metals have thermal conductivities in the range UPPCL AE-16.11.2013
of Ans. (d) : Energy gap of semiconductors is given by
(a) < 1 (b) 1-5 hc
Eg ≥ c = speed of light
(c) 5-25 (d) 20-400 λ
Mizoram PSC AE/SDO 2012-Paper-I λ = wave length
Ans. (d) • Thermal conductivity is a measure of its h = plank constant
ability to conduct heat. ν = frequency
• Thermal conductivity range 230. The width of the energy band depends on
for metal - 20 to 400 W/m-K which of the following?
for insulator - 0.1 to 2 W/m-K (a) Temperature
• When a material undergoes a phase change, the (b) Pressure
thermal conductivity may change abruptly. (c) Relative freedom of electrons in the crystal
227. The knee voltage of GaAs is (d) Mass of atom in the material
(a) 0.3 V (b) 0.7 V Mizoram PSC IOLM -2018, Paper I
(c) 1.2 V (d) 2.3 V KVS TGT (WE)- 2014
Mizoram PSC AE/SDO 2012-Paper-I Ans. (a) : The bands have different widths, widths
Ans. (c) : Knee voltage- It is the forward voltage at depending upon the degree of overlap in the atomic
which the flow of the current through the PN junction of orbits from which they arise. Energy band gap depends
the diode increases rapidly. on temperature.
• Knee voltage also known as cut-in voltage, threshold 231. Mobility of electrons and holes in a
voltage or potential barrier voltage. semiconductor depends on-
a. Type of semiconductor
b. Temperature of semiconductor
c. Scattering of impurities
d. Relaxation time
(a) a, b and c (b) b, c and d
228. An electron falls through a potential difference
(c) a, c and d (d) only b and d
of 1V. If velocity is zero, the final velocity of
electron is about UPPCL AE-16.11.2013
(a) 1m/sec (b) 1Km/sec Ans. (a) : Semi conductor mobility depends on the
(c) 100Km/sec (d) 600Km/sec impurity concentration, defect concentration,
Mizoram PSC AE/SDO-2012 Paper-III temperature and electrons and holes concentration.
Ans. (d) : Given, It also depends on the electric field, particularly at high
Potential difference V = 1V field when velocity saturation occurs.
The energy gained by the electron is equal to the 232. The p-side and n-side of a germanium (Ge)
kinetic energy. diode have resistivity 2 ohm- cm and 1 ohm -
So, cm respectively. The value of the potential
eV = kE (Q e = 1.6 ×10−19 C ) barrier (V0)-
(a) 0.22 Volts (b) 0.55 Volts
eV =
1
2
me v2 (Q m e = 9.1× 10−31 kg )
(c) 0.88 Volts (d) 0.44 Volts
UPPCL AE-16.11.2013
Ans. (b) : We know that – (c) An electron and a hole in the conduction band
1 (d) An electron and a hole in the valence band
NP = UPSC JWM-2016
PqµP
Ans. (a) : In an intrinsic semiconductor, breaking of a
kT  N A − N D  covalent bond results in the generation of an electron in
VB = ln  σ
q  NL  the conduction band and a hole in the valence band.
VB = 26ln ( 2 ) mV 236. When a group III impurity is doped into silicon
(a) Holes become majority
VB = 0.55V (b) Electrons become majority
233. Consider two energy levels : E1 ev above the (c) Either holes or electrons may become
fermi level and E2 ev below the fermi level P1 majority
and P2 are respectively the probabilities of E1 (d) Concept majority of charge carrier can be
being empty the E2 being occupied by the decided
electron, then UPSC JWM-2016
(a) P1 = P2 Ans. (a) : Silicon is a semiconductor which has 4
(b) P1 and P2 depend on number of electrons. balance electron. When a group III impurity is doped
(c) P1 > P2 into silicon then p-type semiconductor is formed which
(d) P1 < P2 has holes as a majority charge carrier.
UPPCL AE-16.11.2013 237. In a semiconductor, holes exists in _____band.
1 (a) the conduction band
Ans. (a) : For E1 = Eev, PC (E1) = E1−E f (b) the forbidden energy
1 + e KT (c) no
given E1 – Ef = E (d) the valence band
1 UKPSC Assistant Radio Officer Screening Exam.-2011
PC (E1) = ––––(1)
1+ e E / kT
Ans. (d) : In a semiconductor, holes exists in the
for E2 = E below Fermi level, the probability of E2 valence band.
being occupied an electron is given by 238. Forbidden band is largest in.
1 (a) Conductor (b) Semiconductor
P (E2) =
1 + e( E 2 −Ef ) / KT (c) Insulator (d) Super conductor
Probability of E2 being empty is = 1– probability of UJVNL AE-2016
occupancy Ans. (c) : Forbidden band provides the information
1 about the conduction in any material if forbidden band
1− E 2 − Ef is large then conduction will less. Hence in insulators
1 + e KT Forbidden band is largest.
Given EF – E2 = E 239. Drift current in semiconductor depends upon
1 (a) Only the electric field
1−
1 + e − E / KT (b) Only the carrier concentration gradient
e E / KT (c) Both the electric field and the carrier
P (E2 ) = 1 − concentration
1+ e E / KT
(d) Both the electric field and the carrier
1 + e E / KT − e E / KT
P (E2 ) = concentration gradient
1 + e E / KT UJVNL AE-2016
P(E 2 ) = P(E1 ) Nagaland PSC CTSE (Degree) -2015, Paper I
P1 = P2 Ans. (c) : Drift current in semiconductor depends upon
234. Above absolute zero Kelvin, silicon in its purest the electric field and the carrier concentration. Drift
form behaves as current is given by
(a) Intrinsic semiconductor i = neAVd
(b) Extrinsic semiconductor
240. In a junction built - Potential depends on
(c) Conductor
(a) Temperature
(d) An insulator
UPSC JWM-2016 (b) Doping densities
(c) Doping densities & temperature
Ans. (d) : Silicon is a type of a semiconductor. Above (d) None of these
absolute zero Kelvin, silicon in its purest form behaves
UJVNL AE-2016
as an insulator.
Ans. (c) : Built in potential is given by
235. In an intrinsic semiconductor, breaking of a
covalent bond results in the generation of: kT  N D N A 
ln 
 n 2 
(a) An electron in the conduction band and a hole Vbuilt.in =
q  i 
in the valence band
(b) An electron in the valence band and a hole in So built in potential depends both on doping densities
the conduction band and temperature.

241. An electron rising through a potential of 500 V 12400
will acquire an energy of E= eV
-2
(a) 800 × 10 Joules (b) 800 Joules λ(Å)
(c) 500 Joules (d) 500 eV 12400
E= = 1.653 eV
UJVNL AE-2016 7500
Ans. (d) : Electron - volt is energy required to rise of 246. In an intrinsic semiconductor, the Fermi level:
electron from valence band when 1V is applied. (a) Lies at the center of forbidden energy gap
So here 500V is applied Hence energy required is (b) Is near the conduction band
500eV. (c) Is near the valence band
242. Carbon is in the group IV of periodic table, (d) May be anywhere in the forbidden energy gap
UPRVUNL AE-2016
even, it is not used as semiconductor because it
has Ans. (a) : In an intrinsic semiconductor, the Fermi level
(a) high dielectric constant lies at the center of forbidden energy gap
(b) large energy gap (> 5 eV)
(c) low temperature coefficient
(d) low thermal conductivity
UKPSC Assistant Radio Officer Screening Exam.-2011
Mizoram PSC IOLM-2010 Paper-I E + EV
EF = C (In Intrinsic semiconductor)
Ans. (b) : Carbon is in the group IV of periodic table, 2
even then, it is not used as semiconductor because it has 247. The energy gap in a semiconductor:
large energy gap >5eV(Approx 5.4eV). (a) Increases with temperature
243. A base diffusion layer length is 80µ and its (b) Decreases with temperature
width is 8µ. Given the sheet resistance of layer (c) No effect of temperature
is 100 ohm/square, the resistance of layer is (d) Is zero
UPRVUNL AE-2016
_____.
(a) 1 K ohm (b) 10 ohm Ans. (b) : The energy gap in a semiconductor decreases
(c) 6.4 K ohm (d) 8.8 K ohm with temperature .
UPRVUNL AE-2016 In solid-state physics, the energy gap or the band gap is
an energy range between valence band and conduction
Ans. (a) : Given, l = 80 µ, W = 8 µ, Rs = 100 Ω/sq. band where electron states are forbidden in contrast to
l lρ conductors electron in a semiconductor must obtain
R =ρ =
A t×W energy to cross the band gap and to reach the
l 80 conduction band.
R = Rs × = 100 × 248. The most preferred cleavage plane for silicon
W 8
R = 1000 Ω = 1 kΩ is:
(a) <111> (b) <211>
244. The band gap in a material is 1 eV; the (c) <100> (d) <112>
corresponding wavelength emitted is _______. UPRVUNL AE-2016
(a) 1.240 µm (b) 1.240 mm Ans. (a) : The most preferred cleavage plane for silicon
(c) 1.240 nm (d) 1.240 cm is < 111>.
UPRVUNL AE-2016 • It is used to identity mineral and its quality.
Ans. (a) : Given, • It forms generally in a lower energy crystal structure.
E = 1 eV, 249. Consider the statements-
12400 1. Annealing is required to repair lattice
E= damage.
λÅ
12400 2. Success of annealing can be measured
λ= Å using Hall effect technique.
1 The correct statements is-
λ = 1.24 µm (a) Only (1) (b) Only (2)
245. For material emitting 4×1014 Hz the band gap (c) Both (1) and (2) (d) None of the above
is ______ eV. UPPSC Poly. Tech. Lect.-22.03.2022, Paper -I
(a) 14.87 (b) 1.33 Ans. (c) : Both (i) and (ii) statements are correct
(c) 4.9 (d) 1.653 Ion implantation damages the target and displaces mean
UPRVUNL AE-2016 atoms from the target lattice.
Ans. (d) : Given, The electrical behaviour after implantation is dominated
Frequency ( f ) = 4 × 1014 Hz by deep level electron and hole traps.
Annealing is required to repair lattice damage.
c The different methods for annealing are.
f=
λ (i) Furnace annealing
3 ×10 8 (ii) Rapid thermal Annealing
λ= = 75 × 10−8 = 7500 × 10−10 Annealing temperature dependence of Hall
4 × 1014
measurement results.

250. Which of the following is correct? Ans. (a) : 1 eV is equal to 1.6 × 10–19 Joule it is a unit
(a) Intrinsic and extrinsic semiconductors have of energy which used in semiconductor physics.
negative temperature coefficient and 254. In a P-type semiconductor, Fermi-level is close
conductors have positive temperature to ________.
coefficient. (a) The bottom of the valence band
(b) Conductors and extrinsic semiconductors (b) The top of the valence band
have negative temperature coefficient and (c) The top of the conduction band
intrinsic semiconductors have positive (d) The bottom of the conduction band
temperature coefficient. RRB SSE 02.09.2015, Shift-I
(c) Insulators and semiconductors have positive Ans. (b) : The highest energy level that an electron can
temperature coefficient whereas conductors occupy at the absolute zero temperature is known as the
have negative temperature coefficient. fermi level .
(d) Conductors and extrinsic semiconductors • For P - type semiconductor the fermi level lies close
have positive temperature coefficient and to the top of the valance band.
pure semiconductors have negative • For N-type semiconductor the fermi level lies close
temperature coefficient. to the bottom of the conduction band.
KVS TGT (WE)- 2017 • For intrinsic semiconductor the fermi level is nearly
Ans. (d) : The conductivity increase with temperature midway between the conduction band and valance
as more and more electrons are librated. Intrinsic band at absolute zero temperature.
semiconductor have negative temperature coefficients 255. In a p-type semiconductor, acceptor
of resistance but conductor and extrinsic semiconductor concentration is 1013/cm3 and intrinsic
have positive temperature coefficient. concentration is 1.5×1016/cm3, then find
251. The Fermi level EF in an intrinsic electron concentration ?
semiconductor, if effective masses of holes and (a) 2.25 × 1019/cm3 (b) 1.5 × 1016/cm3
16 3
electrons are same, is : (c) 2.25 × 10 /cm (d) 1.5 × 1019/cm3
(a) EC – EV (b) EC + EV SAIL- 2014
EC + E V E − EV Ans. (a) : Given that,
(c) (d) C ni = 1.5 ×1016/cm3
2 2
p = 1 ×1013/cm3
KVS TGT (WE)- 2017
n=?
Ans. (c) : Fermi Level– Fermi level is energy state
pn = n i2
having probability 1/2 of being occupied of an electron,
n i2 (1.5 × 10 )
2
if there is no forbidden band exist. 16
Fermi level in intrinsic semiconductor n= =

p 1× 1013
E + E V KT N
Ef = C − ln C 2.25 × 1032
2 2 NV n=
EC = Maximum energy of conduction band 1× 1013
EV= Maximum energy of valence band n = 2.25 × 1019 / cm3
m e = m h at T = 0 256. A silicon sample is uniformly doped with 1016
EC + E V phosphorus atoms/cm3 and 2×1016 boron
Ef = atoms/cm3. If all the dopants are fully ionized,
2
In intrinsic semiconductor fermi level stays at centre of the material is
energy gap such as that fermi level is independent of (a) n-type with carrier concentration of 1016 cm–3
temperature. (b) n-type with carrier concentration of 2×1016
252. An insulator is one whose cm–3
(a) valence band is empty (c) p-type with carrier concentration of 1016 cm–3
(b) conduction band is full (d) p-type with carrier concentration of 2×1016
(c) energy gap between the two band is large cm–3
(d) none of these BPSC Polytechnic Lecturer-2014
Mizoram PSC AE/SDO 2012-Paper-I Ans. (c) : Here n<p or NA>ND
Ans. (c) : An insulator has no electrons in its ∴ Semiconductor is p-type with carrier of 1016 cm–3.
conduction band. So that the conductivity of an 257. An N-type semiconductor as a whole is:
insulator ideally zero. Hence there is large gap between (a) Positively charged
the conduction and valence band. (b) Positively or negatively charged depending
253. One electron volt is equal to on doping
(a) 1.6 × 10–19 Joule (b) 54.6 × 10–9 Joule (c) Negatively charged
–12
(c) 4.6 × 10 Joule (d) 1.3 × 10–7 Joule (d) electrically neutral
Mizoram PSC IOLM -2018, Paper I RRB SSE 01.09.2015 Shit-I
Ans. (d) : The n-type semiconductor has excess of free 261. Mobilities of free electrons and holes in pure Ge
electrons for conduction. These electrons are unbound. are 0.38 and 0.18 m2/V s, respectively. Assume ni
Since, the total number of free electrons in the atom is for Ge = 2.5×1019m-3. Calculate the intrinsic
equal to the total number of protons in the nucleus. So resistivity of Ge. Take q = 1.6×1019 Coul.
n- type semiconductor is electrically neutral. (a) 0.786 Ωm (b) 0.846 Ωm
258. Which of the following will serve as donor (c) 0.446 Ωm (d) 0.946 Ωm
impurity in silicon? UPPCL AE-05.11.2019
(a) Boron (b) Indium Ans. (c) : Formula of resistivity is given by-
(c) Germanium (d) Antimony
1
RRB SSE 01.09.2015 Shit-I ρ =
Ans. (d) : Antimony will serve as donor impurity in niq (µn + µp )
silicon. The element whose atom has 5 valance electron µ = 0.38, µ = 0.18, n = 2.5 × 1019
n p i
and donate an extra free electron. −19
259. A bar of silicon is doped with boron q = 1.6 × 10 c
concentration of 1016 cm–3 and assumed to be 1
fully ionized. It is exposed to light such that ρ = 2.5 × 1019 ×1.6 × 10 −19 ( 0.38 + 0.18 )
electron-hole pairs are generated throughout
the volume of the bar at the rate of ρ = 1
20 –3 –1
10 cm s . If the recombination lifetime is 2.5 ×1.6 × (.56 )
100 µs, intrinsic carrier concentration of silicon
is 1010 cm–3 and assuming 100% ionization of ρ = 0.4464 Ω − m
boron, then the approximate product of steady- 262. A particular sample of n-type Germanium has
state electron and hole concentrations due to a resistivity of 0.1Ωm at 300K. Calculate the
this light exposure is donor concentration. Take µ n = 0.38 and
(a) 1020 cm–6 (b) 2×1020 cm–6
(c) 10 cm32 –6 32
(d) 2×10 cm –6 q = 1.6 ×10–19 Coul.
GATE-2021 (a) 1.24 × 10 20 m −3 (b) 1.64 × 10 20 m −3
Ans. (d) : Given as (c) 1.84 × 10 20 m −3 (d) 1.44 × 10 20 m −3
N A = 1016 cm3 UPPCL AE-05.11.2019
G = 1020 cm3 − sec Ans. (b) : We know that
τ = 100µ sec σ = N D .q.µ n
n i = 10 cm10 3 1
= N D .q.µ n
Electron concentration ρ
n 2 1020 1
( n ) = i = 16 = 104 cm3 ND =
p 10 ρ× q × µn
After light illumination hole concentration N = 1
( p ' ) = p + ∆p −19
D
0.1 × 1.6 × 10 × 0.38
p ' = 1016 + 10 20 ×10 −6 ×100 N D = 16.44 × 10 19
= 2 ×1016 cm3 N D = 1.64 × 1020 m −3

After illumination electron concentration ( n ' ) = n + ∆n 263. What will be the resistivity of an n-type
−6 Germanium sample at 300K? The sample has a
= 10 + 10 × 10 × 100
4 20
donor density of N d = 10 20 atoms/m3. Assume
1016 cm3
all donors to be ionized and take µ n = 0.38
Product of electron and hole concentration = n '× p '
q = 1.6 ×10–19 Coul.
= 2 ×1032 cm 6 = 2 × 1032 cm −6
(a) 0.194 Ωm (b) 0.164 Ωm
260. A Si wafer is doped with 1016 P atoms/cm3. (c) 0.184 Ωm (d) 0.124 Ωm
Calculate the equilibrium hole concentration p0 at UPPCL AE-05.11.2019
300K. Assume n i = 1.5×1010 cm -3 and Nd >>ni. 1
Ans. (b) : resistivity ρ =
(a) 2.5 × 105 cm −3 (b) 2.55 × 10 4 cm −3 e ⋅ N D ⋅ µn
(c) 2.55 × 105 cm −3 (d) 2.5 × 10 4 cm −3 1
UPPCL AE-05.11.2019 ρ= −19
1.6 ×10 ×1020 × 0.38
Ans. (b) : Hole concentration (np) =

n2
i
=
(1.5 ×10 )10 2
ρ=
1
ne 1016 1.6 × 3.8
ρ = 0.164 Ω − m
Hole concentration = 2.25 × 10 4

264. The band gap in eV of Ge at 300K is: Ans. (a) : Given that,
(a) 1.68 eV (b) 0.66 eV Vd = 60m/sec, µ = 1600m2/V-sec
(c) 0.56 eV (d) 1.12 Ev E=?
UPPCL AE-05.11.2019 We know that
Ans. (b) V
Material Energy gap µ= d
E
0K 300K Vd 60
Si 1.17 1.11 E= =
µ 1600
Ge 0.74 0.66
E = 0.0375V/m
265. A block of Silicon is doped with a donor atom
E = 37.5mV / meter
density N D = 3 ×1014 atoms/cm 3 , and with an
269. Which type of temperature dependent resistor
acceptor density of N A = 0.5 ×1014 atoms/cm 3 exhibits a positive temperature coefficient of
find the resultant density of electrons. resistivity?
(a) 4.5 × 1014 electrons / cm3 (a) Thermistor (b) Sensistor
(c) Insulator (d) Semiconductor
(b) 3.5 × 10 electrons / cm
14 3
Nagaland PSC CTSE (Diploma)-2017, Paper-I
(c) 2.5 × 10 electrons / cm
14 3
Ans. (b) : Sensistor is a temperature dependent device
(d) 5.5 × 1014 electrons / cm 3 whose resistance is dependent upon temperature. It has
UPPCL AE-05.11.2019 direct variation with respect to change in temperature
Ans. (c) : we know that– and hence usually appropriate for bias condition.
2 270. The impurity atoms is semiconductors
ND − NA  ND − NA  (a) inject more charge carriers
No = +   + ni
2
2  2  (b) reduce the energy gap

(c) increase the kinetic energy of valence
N D − N A >> n i2 electrons
No ≈ ND − NA (d) increase the energy gap
N o = 3 × 1014 − 0.5 ×1014
Ans. (b) : The impurity atoms in semi conductor
N o = 2.5 × 1014 electrons cm3 reduces the energy gap so there is decrement occurs
between conduction band and valence band. Hence
266. To obtain the P-type semiconductor : conductivity increase.
(a) A pentavalent Impurity is added 271. The forbidden gap in an insulator is
(b) A trivalent Impurity is added (a) Large (b) Small
(c) Both are added (c) Nil (d) Moderate
(d) None of these Nagaland PSC CTSE (Diploma)-2017, Paper-I
RRB SSE 21.12.2014, (Red) Ans. (a) : Forbidden gap in insulator is large. Its value
Ans. (b) : When a trivalent impurity is doped in an is more than 5 eV.
intrinsic semiconductor then we get a P-type 272. The minority carrier concentration is largely a
semiconductor. Indium, Gallium Aluminium and function of
Boron. The number of holes for exceeds the number of (a) forward biasing voltage
free electrons. (b) reverse biasing voltage
267. When donor type impurity is added to a semi- (c) temperature
conductor material (d) the amount of doping
(a) electrons are generated and material is N-type Nagaland PSC CTSE (Diploma)-2017, Paper-I
(b) electrons are generated and material is P-type Ans. (c) : The minority carrier concentration is depend
(c) holes are generated and material is called upon temperature.
P-type 273. Consider silicon at T = 300 K doped with
(d) holes are generated and material is called phosphorus at a concentration of Nd = 1016 cm-
3
. The intrinsic concentration is given as ni = 1.5
N-type
× 1010. Calculate the thermal equilibrium hole
RRB SSE 21.12.2014, (Yellow) concentrations.
Ans. (a) : Arsenic, Antimony, Bismuth and (a) 2.25 ×104 cm-3 (b) 5×104 cm-3
4 -3
Phosphorous are also called donor impurities because (c) 25 × 10 cm (d) 2 × 104 cm-3
the element whose atom has five valance electron and RPSC LECTURER-10.01.2016
donate an extra electron. Ans. (a) : Given, ND = 1016cm–3
268. Given drift velocity Vd = 60m/sec, mobility ni = 1.5×1010
2
µ = 1600 m /V-sec. Find electric field E Concentration of holes in n-type semiconductor
(a) 37.5 mV/m (b) 35.8 mV/m n2
(c) 375 mV/m (d) 3.59 mV/m NA = i
BARC Scientific Officer-2016 ND

279. Addition of pentavalent impurity to a
NA=
(1.5 ×10 )
10 2
semiconductor creates many……….
1016 (a) Free electrons (b) Holes
2.25 × 1020 (c) Valence electrons (d) Bound electrons
NA= = 2.25 × 104 cm −3 Nagaland PSC CTSE (Diploma)-2017, Paper-I
1016
Ans. (a) : In N-type semiconductors, electrons are the
274. An electron-volt (1eV) is a unit of majority carriers while holes constitute the minority
(a) Energy (b) Potential difference carriers. Hence, N-type semiconductor conducts
(c) Charge (d) Momentum
principally by electrons in the nearly empty conduction
band and the process is called excess conduction.
Ans. (a) : Electron volt, unit of energy commonly used
in atomic and nuclear physics, equal to the energy 280. An n-type semiconductor is………
gained by an electron when the electrical potential at the (a) Positively charged (b) Negatively charged
electron increases by one volt. (c) Electrically neutral (d) None of the above
1 eV = 1.602 × 10–19 joules Nagaland PSC CTSE (Diploma)-2017, Paper-I
275. When doping increases, __________of a Ans. (c) : In N-type semiconductor has excess number
semiconductor decreases of electron but these extra electron were supplied by
(a) Impurity (b) Conductivity the atom's donor impurity and each atom of donor
(c) Bulk resistance (d) Minority carrier impurity is electrically neutral. When the impurity is
Nagaland PSC CTSE (Diploma)-2017, Paper-I added, the term 'excess electron' refers to an excess with
Ans. (c) : Doping is the process of adding impurities to regard to the number of electron to fill the covalent
a semiconductor. Depending on the impurity, either free bonds in the semicondutor crystal. Same condition
electrons or holes are created as charge carriers. These apply for P-type semiconductor.
carriers enhance the conductance of the material. By So both N & P-type semiconductor are electrically
adding more impurity, more charge carrier are created neutral.
which further increase the conductance and decrease 281. The random motion of holes and free electrons
resistance. due to thermal agitation is called………
276. What is the charge of the hole? (a) Diffusion (b) Pressure
(a) Equal to that of a proton (c) Ionization (d) None of the above
(b) Equal to that of an electron Nagaland PSC CTSE (Diploma)-2017, Paper-I
(c) Equal to that of a neutron Ans. (a) : Diffusion is the movement of electrons and
(d) Equal to zero holes from a region of higher concentration to lower
Nagaland PSC CTSE (Diploma)-2017, Paper-I concentration. The drive which causes diffusion is the
Ans. (a) : Unlike an electron which has a negative thermal agitation of the atoms or molecules or electrons
charge, holes have a positive charge that is equal in and holes. On the other hand-drift current is a function
magnitude but opposite in polarity to the charge on of both electric field and charge density.
electron. 282. Two initially identical samples A and B of pure
The charge on holes is positive. Hence, the charge on a
germanium are doped with donors to
hole is equal to the charge of proton.
concentrations of 1 × 1020 and 3×1020
277. The forbidden energy gap in semiconductors : respectively. If the hole concentration in A is 9
(a) Is located just above valence band × 1012, then the hole concentration in B at the
(b) Is located just below the valence band
same temperature will be
(c) Is located between conduction band and
(a) 3 × 1012 m–3 (b) 7 × 1012 m–3
valence band 12 –3
(c) 11 × 10 m (d) 27 × 1012 m–3
(d) None of these
MPPSC Forest Service Exam.-2014 Nagaland PSC CTSE (Diploma)-2017, Paper-I
Ans. (c) : Forbidden gap is a energy gap between the Ans. (a) : For sample A;
conduction band and valence band of semiconductor. If n = 1 × 1020 m–3
forbidden gap is high, conductivity is low. p = 9 × 1012 m–3
278. When a pentavalent impurity is added to a By Mass action law-
pure semiconductor, it becomes……….. np = n i2
(a) An insulator n i2 = 1 ×10 20 × 9 ×1012
(b) An intrinsic semiconductor
(c) p-type semiconductor n i2 = 9 × 1032 ...... (i)
(d) n-type semiconductor For sample B;
Nagaland PSC CTSE (Diploma)-2017, Paper-I n = 3 × 1020 m–3
Ans. (d) : When a small amount of pentavalent impurity n i2 = 9 × 1032 = np
(Antimony, phosphorous or arsenic) is added to a pure
9 ×1032
semiconductor crystal during the crystal growth, the p= = 3 ×1012 m −3
resulting crystal is called as N-type extrinsic semiconductor. 3 ×1020

283. Electric field E in Hall Effect is equals to Given µ n = 0.36m 2 / V.sec , VT = 26mV
(a) hall voltage × semiconductor thickness
(b) hall voltage / semiconductor thickness t n = 340 µs = 340 × 10 −6 sec
(c) hall voltage + semiconductor thickness Now L n = 0.36 × 26 × 10−3 × 340 ×10−6
(d) hall voltage - semiconductor thickness
Nagaland PSC CTSE (Diploma)-2017, Paper-I L n = 178.39 × 10−5
Ans. (b) : Electric field E in Hall Effect is equals to Ln = 1.78mm 1.77mm
Hall voltage/semiconductor thickness. 287. Most commonly employed pentavalent
VH = Ed impurities used for semiconductor doping are
V phosphorous, Antimony and
E= H (a) Boron (b) Indium
d (c) Arsenic (d) Aluminium
Where, Nagaland PSC CTSE (Diploma)-2018, Paper-I
VH= Hall voltage
Ans. (c) : When a small amount of pentavalent impurity
E= Electric field
(Antimony, Phosphorous or Arsenic) is added to a pure
d= Semiconductor thickness
semiconductor crystal during the crystal growth, the
284. If the doping level of a crystal diode is resulting crystal is called as N-type extrinsic
increased, the breakdown voltage………… semiconductor.
(a) remains the same (b) is increased
288. In an N-type semiconductor material, the
(c) is decreased (d) none of the above
majority and minority carriers are
(a) Electrons and holes respectively
Ans. (c) : Width of the depletion layer is inversely (b) Holes and electrons respectively
proportional to the doping concentration hence the (c) Electrons
width will decrease when the doping is increased, hence (d) Holes
the breakdown voltage is decreased. Nagaland PSC CTSE (Diploma)-2018, Paper-I
285. A thin P-type silicon sample is uniformly Ans. (a) : In N-type semiconductor, the electrons are
illuminated with light which generates excess the majority carriers while holes are minority carriers.
carriers. The recombination rate is directly In N-type an energy level very near the conduction band
proportional to in Ge or Si. Such an impurity level is called a donor
(a) The minority carrier mobility level impurity.
(b) The minority carrier recombination lifetime
289. Doping of semiconductor is
(c) The majority carrier concentration
(a) The process of purifying semiconductor materials
(d) The excess minority carrier concentration
(b) The process of adding certain impurities to
Nagaland PSC CTSE (Degree)-2017, Paper-I
the semiconductor material
Ans. (d) : The Recombination rate is defined as the (c) The process of converting a pure
ratio of the excess minority carrier concentration to the semiconductor material into some form of an
minority carrier life time active device like diode, transistor, FET etc.
Excess minorityCarrier Concentration (d) one of the processes used in the fabrication of
R=
Minority Carrier lifetime Ics
∆P Nagaland PSC CTSE (Diploma)-2018, Paper-I
R= TNTRB AE-2017
τP Ans. (b) : In addition to the intrinsic carriers generated
Consider a P sample with hole concentration P0 and thermally, it is possible to create carriers in
electron concentration n0 semiconductors by purposely introducing impurities
Where, into the crystal. This process, called doping. It is the
P0 ≅ N A most common technique for varying the conductivity of
n 0 = n i2 / N semiconductors.
ni = Intrinsic carrier concentration 290. Which one of the following is used as a passive
When illuminated with light excess electron hole pairs component in electronic circuit?
are generated. (a) Resistor (b) Vacuum Tube
(c) Transistor (d) Tunnel diode
286. Electron mobility and life time in a Nagaland PSC CTSE (Diploma)-2018, Paper-I
semiconductor at room temperature are
Ans. (a) : A passive element is an electrical component
respectively 0.36 m2/(Vs) and 340 µs. the
that does not generate power, but instead dissipates,
diffusion length is
stores, and/or releases it. Passive elements include
(a) 3.13 mm (b) 1.77 mm
resistances, capacitors, and coils.
(c) 3.55 mm (d) 3.13 cm
Nagaland PSC CTSE (Degree)-2017, Paper-I 291. For an intrinsic semiconductor, ni = 1×1010/cm3
Ans. (b) : We know that and q = 1.6 x 10–19 C electron and holes drift
nobilities at room temperature are 1350 and
L n = D n t n = µ n VT t n 450 cm2/v-s, the intrinsic resistivity is:
(a) 106 Ω - cm (b) 103 Ω - cm If the charge of an electron is q, then the
(c) 3.5 × 10 Ω - cm
5
(d) 3.5 × 104 Ω - cm magnitude of the electric field developed inside
LMRC AM (S&T)-13.05.2018 this semiconductor bar is
2∆
Ans. (c) : The formula for the conductivity (σ) of the (a) (b) ∆
semiconductor qL 2qL
σ = niq(µn+µh)
1 (c) ∆ (d) 3∆
resistivity ∝ qL 2qL
condutivity GATE-2021
1 Ans. (c) : In the case of non-uniform doping
f=
n i q(µ n + µ h ) relationship between the electric field and slope of
energy.
1
= 1 dE v
1× 10 × 1.6 × 10−19 (1350 + 450 )
10
| E x |=
q dx
1
= 1 ∆−0
1× 1010 × 1.6 × 10−19 × 1800 Ex =  
q L−0
109 108
= = 1∆
16 × 180 16 ×18 ∴ E=
= 3.5 × 105 Ω - cm qL
292. The hall coefficient RH for an extrinsic 295. N-type materials are the type of materials
semiconductor formed by adding group_____ elements to the
(a) increases with increase in temperature semiconductor crystals.
(b) decreases with increase in temperature (a) three (b) four
(c) is independent of temperature (c) two (d) five
(d) changes with magnetic field DMRC AM S&T-2020
Nagaland PSC CTSE (Diploma)-2018, Paper-I Ans. (d) : N-type material:- An n-type semiconductor
Ans. (b) : In an extrinsic semiconductor, the hall effect is an extrinsic semiconductor doped with phosphorus
(p) Arsenic (As), or antimony (sb). Which are belong
coefficient is inversely proportional to temperature.
group V is periodic table and group V elements have
Hence it decrease with increase in temperature. five valence electrons.
293. Even though carbon is in IV group of the 296. The effective mass of an electron in a crystal is
Periodic Table, it is not used as a (a) Same as electron mass
semiconductor because it has (b) Different from electron mass
(a) High dielectric constant (c) Sum of electron and hole mass
(b) Large energy gap > 5eV (d) Difference of electron and hole mass
(c) Low temperature coefficient Nagaland PSC CTSE (Diploma)-2018, Paper-I
(d) Low thermal conductivity Ans. (a) : The effective mass of an electron in a crystal
Nagaland PSC CTSE (Degree)-2017, Paper-I is same as electron mass. The mass of an electron in the
Ans. (b) : Carbon is not a semi conductor because the periodic potentials of a crystal is different from the free
forbidden energy gap in carbon is around 7eV, this is electron mass and is usually referred to as the effective
much higher for it to be a conductor or even mass. Mass of an electron is 9.11×10–31kg.
semiconductors which has lower forbidden energy gaps. 297. The number of semi-conductor in periodic
294. The energy band diagram of a p-type table is
(a) 3 (b) 5
semiconductor bar of length L under
(c) 7 (d) 13
equilibrium condition (i.e., the Fermi energy Nagaland PSC CTSE (Diploma)-2018, Paper-I
level EF is constant) is shown in the figure. The
Ans. (c) : In periodic table have 7 semi-conductor
valence band EV is sloped since doping is non- element.
uniform along the bar. The difference between
298. The diffusion length of free electrons Le and
the energy levels of the valence band at the two
holes Lh as charge carriers in a semiconductor
edges of the bar is ∆ . is respectively given by
(a) Le = ( De / τ e ) , L h = ( D h / τ h )
(b) Le = ( De τ e ) , L h = ( D h τ h )
(c) Le = ( τe / De ) , Lh = ( τh / Th )
(d) Lh = ( D h + τ h ) , L e = ( De + τ e )
UPPCL AE-16.11.2013
Ans. (b) : Diffusion length L = D.τ Ans. (c) : An intrinsic semiconductor (such as pure Ge
For electron or Si), has only four electrons in the outermost orbit of
bits atoms. When atoms bond together to form
L e = D e .τ e molecules of matter; each atom attempts to acquire
For holes eight electrons in its outermost shell.
L H = D H .τ H This is done by sharing one electron from each of the
four neighbouring atoms. This sharing of electrons in
299. For germanium the forbidden energy gap is semiconductor is known as covalent bonding.
(a) 0.15 eV (b) 0.3 eV 305. Assuming the Fermi level EF to be independent
(c) 0.5 eV (d) 0.7 eV of temperature, EF may be defined as the level
Mizoram PSC IOLM -2018, Paper I with an occupancy probability of
Nagaland PSC CTSE (Diploma)-2017, Paper-I (a) 0% (b) 50%
Ans. (d) : The energy difference between the top of (c) 75% (d) 100%
valence band and bottom of conduction band in material Mizoram PSC Jr. Grade-2015, Paper-I
known as forbidden energy gap. For Germanium it is Ans. (b) : In an intrinsic semiconductor, the Fermi level
equal to 0.7eV. lies midway between the conduction and valence bands.
300. One eV is equal to_______J. Fermi-dirac probability function F ( E ) is given by-
(a) 6.02 × 1023 (b) 1.6 × 10–19 1
(c) 6.25 × 10 18
(d) 1.66 × 10–24 F( E) =
1 + e( F )
E − E / KT
Mizoram PSC Jr. Grade-2015, Paper-I
If E = E F then,
Ans. (b) : The electron volt (eV) is a unit of energy
1
whereas the volt (v) is the derived SI unit of electric F( E) =
potential. 1 + e0
1 eV = 1.602 × 10–19 Joule 1
=
301. An open circuit can have any voltage across its 2
terminals, but the current is always______. F ( E ) = 50%
(a) 5A (b) 0A
306. If a sample of germanium and a sample of
(c) 1A (d) ∞ silicon have the same impurity density and are
Mizoram PSC Jr. Grade-2015, Paper-I kept at room temperature
Ans. (b) : Two points are said to be open-circuited (a) both will have equal value of resistivity
when there is no direct connection between them. (b) both will have equal negative resistivity
(i) resistance between the two points is infinite. (c) resistivity of silicon will be higher than that
(ii) There is no flow of current between the two points. of germanium
302. For insulators, the forbidden gap is of the (d) resistivity of germanium will be higher than
order of that of silicon
(a) 5 eV (b) 1 eV Mizoram PSC Jr. Grade-2015, Paper-I
(c) 0.1 eV (d) zero Ans. (c) : When a sample of germanium and silicon
Mizoram PSC Jr. Grade-2015, Paper-I having same impurity density are kept at room
temperature then resistivity of silicon will be higher
Ans. (a) : Insulators– It has a very wide forbidden-
than that of germanium.
energy gap ( ≥ 5eV ) separating the filled valence band 307. Which of the following are donor impurities?
from the vacant conduction band. Because of this; it is 1. Gold 2. Phosphorus
practically impossible for an electron in the valence 3. Boron 4. Antimony
band to jump the gap, reach the conduction band. 5. Arsenic 6. Indium
303. In an intrinsic semiconductor, the number of (a) 2, 4, 5 (b) 3, 4, 5, 6
electrons is equal to the number of holes at (c) 1, 2, 4, 6 (d) 1, 2, 3
which temperature? Mizoram PSC Jr. Grade-2015, Paper-I
(a) 0ºK (b) 0ºC Ans. (a) : N-type extrinsic semiconductor is obtain
(c) high temperature (d) at all temperature when a pentavalent material like phosphorous, Arsenic
Mizoram PSC Jr. Grade-2015, Paper-I Antimony etc. is added to pure germanium crystal. It is
called donor impurity and makes the pure germanium
Ans. (a) : In an intrinsic semiconductor, the number of an N-type extrinsic semi-conductor.
electrons is equal to the number of holes at 0ºK.
308. With an increased in temperature, the Fermi
n = Pi = ni
level in an intrinsic semiconductor
where ni is called the intrinsic concentration. (a) Moves closer to the conduction band edge
304. The nature of crystal binding in Germanium is (b) Moves closer to the valence band edge
(a) ionic (b) metallic (c) Moves to the conduction band
(c) covalent (d) Van-der-wall type (d) Remain at the centre of the forbidden gap.
Mizoram PSC Jr. Grade-2015, Paper-I Mizoram PSC Jr. Grade -2018, Paper-I
Ans. (d) : The Fermi level of an intrinsic semiconductor 313. Which one of the following condition is true for
is unchanged and remains at the center of the forbidden minimum conductivity (σmin) in an extrinsic
bandgap. semiconductor-
As temperature increases both electron and holes are (a) σmin = (2ni/q) µn / µp
produced in equal number keeping the semiconductor
intrinsic and Fermi level stays at the center. (b) σmin = ( 2n i / q ) µn .µ p
309. The electron hole concentrations in an intrinsic (c) σmin = 2qn i µn .µ p
semiconductor are ni per cm3 at 300 k. If
acceptor impurities are introduced with (d) σ min = 2qn i µ n / µ p
concentration of NA per cm3 (where NA >> ni) UPPCL AE-16.11.2013
the electron concentration per cm3 at 300 k will Ans. (c) : σ = 2qn µ .µ
min i n p
be
2 314. The specific heat of silicon monoxide at high
(a) ni (b) ni /NA
(c) NA + ni (d) NA – ni temperatures, as compared to silicon dioxide is
Mizoram PSC Jr. Grade -2018, Paper-I (a) Larger
(b) Smaller
Ans. (b) : The electron concentration per cm3 at 300K
(c) Equal
ni2 (d) Dependent on other parameters not specified
will be- N D = here
NA
Mizoram PSC IOLM-2010, Paper-I
310. The frequency spectrum of an aperiodic signal Ans. (a) : H2 specific heat of SiO2 = 680 J/Kg.K
is H1 specific heat of SiO = 1000 J/Kg.K H1 > H 2
(a) Continuous
(b) Discrete 315. Effectively, how many valence electrons are
(c) Both Continuous & Discrete there in each atom within a silicon crystal?
(d) None (a) 2 (b) 4
(c) 8 (d) 16
Mizoram PSC Jr. Grade -2018, Paper-I
Mizoram PSC IOLM -2018, Paper I
Ans. (a) : The frequency spectrum of a signal consists Ans. (b) : Each silicon atom has four valence electrons
of the plots of the amplitudes and phases of the which are shared forming covalent bonds with the four
harmonics versus frequency. surrounding Si atoms.
The spectrum of an aperiodic signal has a continuous 316. The formula that determines the number of
spectrum. electrons which can be accommodated in any
311. If the drift velocity of electrons is 2×107 cm/s, level is
through the active region of length 10×10-4 cm, (a) 2n2 (b) n2
then the natural frequency of the diode will be (c) 4n (d) 4n2
(a) 30 GHz (b) 20 GHz Mizoram PSC IOLM-2010, Paper-I
(c) 40 GHz (d) 50 GHz Ans. (a) : From Pauli Exclusion principle, the
RPSC LECTURER-10.01.2016 maximum no. of electron in a shell is given by 2n , n ⇒
2
Ans. (b) : The natural frequency of diode No. of shell.

Vd 317. Rutherford’s atomic model based on
= experimental observations could not be
active region of length accepted. This is because
2 × 10 7 (a) It does not take into consideration the
= −4
= 2 ×1010 = 20 × 109 = 20GHz quantization condition of angular momentum
10 × 10 of an electron
312. In a single crystal of an intrinsic (b) It does not consider orbital motion of an
semiconductor, the number of free carrier at electron
the Fermi level at room temperature is: (c) It does not explain hydrogen spectrum
(a) Half the total number of electrons in the (d) The statement is false
crystal Mizoram PSC IOLM-2010, Paper-I
(b) Zero Ans. (a) : The Ruther Ford atomic model failed to
(c) Half the number of atoms in the crystal explain about the stability of electrons in a circular path.
(d) Half the number of free electrons in the 318. Fermi level is the
crystal (a) Highest occupied energy level at 0 K
RPSC LECTURER-10.01.2016 (b) Highest occupied energy level at 0° C
(c) Energy level at which electron emission
Ans. (d) : In a single crystal of an intrinsic
occurs
semiconductor, the number of free carrier at the Fermi (d) Minimum energy level in the conduction
level at room temperature is half the number of free band
electrons in the crystal. Mizoram PSC IOLM -2018, Paper I
Ans. (a) : The highest energy level that an electron can 323. A silicon wafer 13 is doped with phosphorus of
occupy at the absolute temperature is known as Fermi concentration 10 atoms/cm3. If all the donor
level. Fermi level lies between the balance band and are active, what is its resistivity at room
conduction band. temperature? The electron mobility is 1200
319. Boron is implanted into an n-type Si sample cm2/volt-sec-charge on the electron is 1.6× 10–19
coulomb
with a concentration of Nd = 1016 cm−3 forming
(a) 3.2 Ω-cm (b) 9.2 × 102 Ω-cm
an abrupt junction of square cross-section with
(c) 7.2 × 10 Ω-cm
5
(d) 5.2 × 102 Ω-cm
an area of 2×10−3 cm2. If the acceptor RPCS Lect.-2011
concentration in the p-type material is Na =
18 −3 Ans. (d) :
4×10 cm , the built-in potential Vbi at 300K is
1
given by ρ=
(a) 0.85V (b) 0.24V nq µn
(c) 0.38V (d) 0.6V 1
Mizoram PSC IOLM-2010, Paper-II ρ = 13 −19
10 × 1.6 × 10 × 1200
Ans. (a) : Nd = 1016 Na = 4 × 1018 cm–3 T = 300K 10 4
A = 2 × 10–3 cm2 ni = 1⋅5 × 1010 ρ=

12 ×1.6
KT  Na Nd  ρ = 5.208 × 10 2 Ω cm
V0 = ln  2 
q  ni  324. An intrinsic semiconductor at absolute zero
 16  temperature:
 10 × 4 × 1018  (a) has only a few holes and few electrons
V0 = 0⋅0259 ln
 (1 ⋅ 5 × 1010 )2  (b) has very large number of holes and electrons
  (c) behaves like a good conductor
V0 = 0⋅8498 (d) behaves like a good insulator
V0 = 0 ⋅ 85 Volt RPSC Vice Principal ITI-2016
Ans. (d) : An intrinsic semiconductor is a raw
320. The maximum number of electrons which the semiconductor which behaves like a good insulation or
valence shell of an atom can have is insulator.
(a) 6 (b) 8 325. Which of the following statements is not true
(c) 18 (d) 2 for hole?
Nagaland PSC CTSE (Diploma)-2017, Paper-I (a) Holes may constitute an electric current
Ans. (b) : The maximum number of electrons which the (b) Holes can be considered as a net positive
valence shell of an atom can have is 8. charge
321. Consider the following statements: pure (c) Holes can exist in any material including
germanium and pure silicon are examples of conductors
(i) direct band-gap semiconductors, (d) Holes can exist in certain semi-conductor
(ii) indirect band-gap conductors material only
(iii) degenerate semiconductors Nagaland PSC CTSE (Degree)- 2016, Paper-I
Of these statements Ans. (c) : Holes are formed when electrons in atom
(a) (i) alone is correct move out of the valence band. Hence it exists in certain
(b) (ii) alone is correct semiconductor it provide the conduction and it consider
(c) (iii) alone is correct as +ve change.
(d) (i) and (iii) are correct 326. Fermi level for potassium is 2.1 ev, the velocity
Mizoram PSC IOLM-2010, Paper-II of electron at. Fermi level equals to
Ans. (b) : Pure Germanium and pure silicon are the (a) 3.2 ×105m/s (b) 4.9×104m/s
(c) 8.6×105m/s (d) 9.7×104m/s
example of indirect band gap semiconductor the
Nagaland PSC CTSE (Degree)- 2016, Paper-I
difference between direct band gap and indirect band
gap is 140 MeV. Ans. (c) :
1
322. The covalent bond is formed by E = mv 2
(a) transfer of electrons between atoms 2
(b) sharing of electrons between atoms 2E 2 × 2.1× 1.6 × 10−19
(c) sharing of variable number of electrons by a v = =
m 9.11×10−31
variable number of atoms
(d) sharing of holes v = 8.6 × 105 m / s
Nagaland PSC CTSE (Diploma)-2017, Paper-I 327. An N-type semiconductor having uniform
Ans. (b) : A covalent bond consist of the mutual doping is biased as shown in the figure.
sharing of one or more pair of electron between atoms.
These electrons are simultaneously attracted by the two
atomic nuclei.

If EC is the lowest energy level of the 1
conduction band, EV is the highest energy level f (E) =  E C + kT– EC 
 
of the valence band and EF if the Fermi level, 1+ e  KT 
which one of the following represents the 1

energy band diagram for the biased N-type f (E C + kT) =
1 + e1
semiconductor? f (E C + kT) = 0.268
f (E C + kT) 0.27
330. Electronic distribution of an Si atom is
(a) 2, 10, 2 (b) 2, 8, 4
(c) 2, 7, 5 (d) 2, 4, 8
14
Ans. (b) : Si z = 1s 2 2s 2 2p 6 3s 2 3p 2
28.09
GATE-2014 = 2, 8, 4
Ans. (a) : 331. A 10 V power supply would use…………as
filter capacitor.
(a) paper capacitor (b) mica capacitor
(c) electrolytic capacitor (d) air capacitor
• For an n-type semiconductor, there are more electrons Ans. (c) : A filter capacitor is a capacitor which fillers out
in the conduction band than there are sides in the a certain frequency or range of frequencies from a circuit.
valence band. This is due to the doping of donor A 10 volt power supply would use electrolytic capacitor
impurity to from n-type semiconductor. as filter capacitor.
This leads to formation of donor energy level below 332. For an n-type Ge specimen, width = 4 mm,
conduction band in forbidden energy gap, which implies length = 1 mm, current (along the length of
that the probability of finding an electron near the specimen)= 1 mA, magnetic field
conduction band edge is larger than the probability of (perpendicular to the current flow direction) =
finding a hole at the valence band edge. 0.1 Wb/m2 and Hall voltage magnitude = 0.005
• Therefore, the Fermi level is closer to the conduction V. Calculate the majority carriers density.
band in an n-type. semiconductor and it lies in the (a) 3×1019 cm–3 (b) 3×1019 m–3
19 –3
forbidden energy gap nearer to the conduction band. (c) 6×10 cm (d) 6×1019 cm–3
328. The Hall co-efficient has the unit of ISRO Scientist Engg. -2020
(a) c/m3 (b) m3/c Ans. (b) : W = 4 mm, l = 1 mm, B = .1 Wb/m2,
3
(c) c /m (d) c/m VH= .005 V, I = 1 mA
Mizoram PSC AE/SDO 2012-Paper-I B.I
Ans. (b) : The two most widely used SI unit for the hall VH =
e× W×ρ
co-efficients are m3/A-sec or m3/C and hybrid unit is
1× 10−3 × 0.1
Ω-cm/G. Concentration ρ =
1.6 ×10−19 × 4 × 10−3 × .005
329. In semiconductor device, if Fermi level (EF) is
positioned at conduction band (Ec). Determine ρ 3 ×1019 m −3
the approximate probability of finding 333. Find µ, Given Vd=50m/sec, E=5V/m
electrons in states at (Ec + kT) (a) 1 m2/V-sec (b) 0.5 m2/V-sec
2
(where k is Boltzmann constant and T is device (c) 0.02 m /V-sec (d) 10 m2/V-sec
temperature in Kelvin) AAI-2015
(a) 0.18 (b) 0.27 Vd 50m / sec
(c) 0.38 (d) 0.52 Ans. (d) : Carrier mobility µ = =
E 5V / m
ISRO Scientist Engg. -2020
Ans. (b) : The approximate probability of finding µ = 10m / V − sec
2
electron in semiconductor device at an energy level E is Its SI unit is m2/V-sec

1 334. When we switch on an electric bulb or a fan in
f (E) =  E– E F 
................(i)
  our house, the appliance starts almost
1 + e KT  immediately. The drift velocity of electrons in
(i) Condition according to question EF=EC the wires would be close to-
(ii) Condition according to question the probability of (a) 1 mm/sec (b) 1 m/sec
finding electron E = E C + kT (c) 3 × 10 m/sec
8
(d) None of these
Now put these values in equation (i) RRB SSE 21.12.2014, (Green)
Ans. (c) : The drift velocity of electrons in the wires 339. What is the forbidden energy gap in a pure
wound be closed to 3×108m/sec. conductor?
Drift velocity- A drift velocity is the average velocity (a) 0 eV (b) 1.1 eV
attained by charged particles, such as electrons, in a (c) 0.7 eV (d) 6 eV
material due to an electric field. RRB JE-01.09.2019, 3:00 PM – 5:00 PM
Ans. (a) : 0 eV forbidden energy gap in a pure
335. The band gap in eV of Si at 300K is:
conductor
(a) 0.56 eV (b) 1.68 eV
(c) 0.66 eV (d) 1.12 eV
UPPCL AE-05.11.2019
Ans. (d) : Band gap for Si at 300K is 1.12 eV
Material Bandgap
Energy (E g )
Silicon (Si) 1.12
Germanium (Ge) 0.66
Silicon carbide(Sic) 3.3
Gallium Arsenid(GaAs) 1.4
336. In a p-type Si sample the hole concentration is (•) For pure conductor forbidden energy gap always
2.25×1015/cm3. The intrinsic carrier zero.
concentration is 1.5 ×1010/cm3 the electron 340. The drift of a hole in a semiconductor is
concentration is brought by-
(a) Zero (b) 1010/cm3 (a) The vacancy being filled by an ion
(c) 105/cm3 (d) 1.5×1025/cm3 (b) The vacancy being filled by a valence
Nagaland PSC CTSE (Degree) -2015, Paper I electron from a neighbouring atoms
Ans. (c) : From the Mass action law we know- (c) The vacancy being filled by a free electron
n×p = ni2 (d) The movement of an atom in the solid
RRB JE- 31.08.2019, 10 AM-12 PM
n i2 (1.5 ×10 )
10 2
Electron concentration = = Ans. (b) : When breaking of covalent bond. Electron

p ( 2.25 × 1015 ) and holes pair is formed. Its electrons moved elsewhere
in the crystal but holes remains there. This holes
= 105 /cm3 neighbourhood attracts the valence electron of the atom
337. Which of the following is a solderless device for and it fills this hole by breaking the covalent bond his
temporary prototype with electronics and test place but a new holes is formed and the process goes
circuit designs? on continuously.
(a) Lug board (b) Bread board 341. Name the PCB side on which the components
(c) Eyelet board (d) Printed circuit board are mounted.
RRB JE-01.09.2019, 3:00 PM – 5:00 PM (a) Component side (b) Solder side
Ans. (b) : Bread board is a solderless device for (c) Copper side (d) Track side
temporary prototype electronics and circuit designs. RRB JE- 31.08.2019, 10 AM-12 PM
• It does not require soldering to connect the Ans. (a) : The top side of a PCB is usually the side
components on board where the components are placed and hence sometimes
• When circuit is not working properly then, we can called component side. Most of the components are
placed or mounted on both sides of the PCB.
easily check and rectify
342. Find the diffusion current density if the
338. The circular rings of copper on the PCB for
concentration gradient is 1.6×1019 diffusion
making solder connections of component leads
constant Dn is 50 electron/cm4
are called− (a) 128 (b) 228
(a) Patches (b) Blind Via (c) 350 (d) 168
(c) Pads (d) Cutout BEL-2015
RRB JE-01.09.2019, 3:00 PM – 5:00 PM Ans. (a) : Given,
Ans. (c) : To establish the connection of the  dn 
components leads. For this, the circular rings made by Concentration gradient   = 1.6 ×1019
the solder connection of copper on the PCB are called  dx 
4
pads. There is a circular copper sphere around the Diffusion constant (D n = 50 electron/cm
)
circular ring. Electrical connection are lousily stabilized dn
J n = q Dn
from one connection trace through the field to other dx
connection trace on the inner layer or another outer = 1.6 ×10–19 × 50 ×1.6×1019
layer. = 128A/ cm2

343. The ratio of diffusion constant to mobility is 348. The mean free path for electron drift...... with
kT q purity.
(a) (b) (a) Increases
q kT (b) Decreases
(c) kTq (d) None (c) First increases then decreases
BEL-2015 (d) Remain same
Ans. (a) : The ratio of diffusion constant to mobility is RRB SSE 01.09.2015, Shift-III
D Ans. (a) : The mean free path for electron drift
VT = and VT = kT / q . increases with purity. The phenomenon of mean free
µ
path as the average distance an electron travels between
344. The material not having a negative two successive collisions.
temperature coefficient of resistivity are The electron suffers more collisions when impurity
(a) Metals (b) Semiconductors increases because impurity atom.
(c) Insulators (d) None of these 349. The intrinsic concentration of silicon sample at
Mizoram PSC IOLM -2018, Paper I 300K is 1.5 × 1016/m3. If after doping, the
Ans. (a) : A material which have negative temperatures number of majority carrier is 5 × 1020/m3, the
coefficient is known as semiconductor and insulator. And minority carrier density is
which has positive temperature coefficient is called metals. (a) 4.50×1011/m3 (b) 3.33×104/m3
345. The concentration of minority carriers in an (c) 5.00×1020/m3 (d) 3.00×10–5/m3
extrinsic semiconductor under equilibrium is Nagaland PSC CTSE (Degree) -2015, Paper I
(a) Directly proportional to the intrinsic Ans. (a) :
concentration n i2
(b) Inversely proportional to the intrinsic Minority carrier density =
concentration Majority carrier density
(c) Directly proportional to the doping (1.5 ×1016 )2
concentration =
5 ×1020
(d) Inversely proportional to the doping
concentration = 45 × 1010
RRB SSE 01.09.2015, Shift-II = 4.5 ×1011 / m3
Ans. (d) : The concentration of minority carriers in an 350. At absolute zero temperature, an intrinsic
extrinsic semiconductor is given by the law of mass semiconductor behave like an insulator because
action, according to which, of
n ⋅ p = n i 2 , n = concentration of electron in the (a) Low electron energy
(b) Low drift velocity of free electron
conduction band P = Concentration of holes in the (c) Non-availability of free electron
valence band. (d) Non-recombination of electron with hole
n i = intrinsic carrier concentration. RRB SSE 02.09.2015, Shift-II
Hence the minority carriers concentration is inversely Ans. (c) : An intrinsic semiconductor at 0K, has
proportional to the doping concentration. electrons only in the valence band. Forbidden gap– 3eV,
346. The current flow in a semiconductor is due to as a result, electrons do not have sufficient energy to
1. Drift current 3. Displacement current excite to the conduction band. Since there are no free
3. Diffusion current electrons in the conductions band, so it behaves as an
(a) 1,2 and 3 (b) 1 and 2 only insulator at 0K.
(c) 1 and 3 only (d) 2 and 3 only 351. If the drift velocity of holes under a field
RRB SSE 01.09.2015, Shift-II gradient of 400 V/m is 200 m/s, their mobility
Ans. (c) : Drift current- When an electric field is in SI unit is
applied to the diode there is more number of covalent (a) 0.05 (b) 0.55
bond break and the concentration of charge carriers also (c) 0.5 (d) 2
increases in p-type and n-type both region and hence RRB SSE 02.09.2015, Shift-II
they affect the drift current in diode. Ans. (c) : Given that
Diffusion current- The diffusion current can be defined Vd = 200m/sec
as the flow of charge carriers within a semiconductor E = 400 V/m
travels from a higher concentration region to a lower V 200
Carrier mobility µ = d = = 0.5
concentration region. E 400
347. _____ has the greatest mobility. µ = 0.5m 2 / V − sec
(a) Hole (b) Electron
(c) Positive ion (d) Negative ion 352. 5 × 1016 electrons pass across the section of a
RRB SSE 01.09.2015, Shift-III conductor in 1 minute 20 sec. The current
flowing is -
Ans. (b) : The electron mobility is greater than hole (a) 1 mA (b) 0.1 mA
mobility because the electron effective mass is smaller (c) 0.01 mA (d) 10 mA
than holes effective mass. RRB SSE 02.09.2015, Shift-III
Ans. (b) : Given that 358. The conductivity σ as a function of 1/T, where
Number of electrons (n) = 5×1016 T is the temperature, for a semiconducting
Time (t) = 80 sec material varies as shown in the figure. Using
We know that Q = ne = it this information, state whether a resistance
5× 1016 ×1.61 ×10–19 = 80 ×i made from intrinsic semiconductor will have
5 ×1016 × 1.61×10−19
i=
80
I = 0.1 ×10–3
i = 0.1mA
(a) Positive temperature coefficient of resistance
353. Charge carriers move in semiconductor via: (b) Negative temperature coefficient of resistance
(a) Diffusion mechanism (c) Zero temperature coefficient of resistance
(b) Floating mechanism (d) Initially positive and later negative
(c) Drift mechanism temperature coefficient of resistance
(d) Both drift and diffusion mechanism BSNL (JTO)-2001
UPMRC AM - 2020 Ans. (b) : Intrinsic semiconductor has negative
Ans. (d) : Charge carriers can move in a semiconductor temperature coefficient of resistance. An intrinsic
because of two phenomena:- semiconductor also called an undoped semiconductor or
a) Drift mechanism b) Diffusion mechanism intrinsic-type semiconductor, is a pure semiconductor
without any significant dopant species present. The
354. The band gap energy is the _______ required to number of charge carriers is therefore determined by the
dislodge an electron from its covalent bond properties of the material itself instead of the amount of
(a) electron density (b) minimum energy impurities.
(c) maximum energy (d) hole density 359. A semiconductor is uniformly doped with NA
UPMRC AM - 2020 acceptors and ND donors. Let the free electron
Ans. (b) : The band gap energy is the minimum energy and hole concentrations be n and p
required to dislodge an electron from its cruelest band. respectively. Assume that the semiconductor is
at thermal equilibrium and that 100%
ionisation has taken place. Then which of the
following is true?
(a) N A + N D = p + n (b) N A − N D = n − p
For band gap of conductor is – 0 eV at 300ºK
(c) N A + N D = pn (d) N D − N A = n − p
For semiconductor – Si – 1.12 eV at 300º K
For Insulator > 5 eV at 300ºK BSNL (JTO)-2002, 2001
Ans. (d) : A semiconductor is uniformly doped with
355. Drift current is :
NA acceptors and ND donors, and the free electron and
(a) Directed movement of charged particles hole concentrations be n and p respectively and assume
under the application of electric field. that the semiconductor is at thermal equilibrium and
(b) directed movement of charged particles due that 100% ionization has taken place. If the material is
to concentration gradient. to remain electrostatically neutral, the sum of positive
(c) random movement of charged particles due to charges must balance the sum of negative charge i.e.
thermal energy. P + ND = NA +n
(d) None of the above ND − NA = n − p
MPSC HOD Govt. Poly. -2013
Ans. (a) : Drift current is the electric current caused by 360. An intrinsic semiconductor at the absolute zero
particles gating by an electric field. temperature
(a) Has a large number of holes
J = σE (b) Behaves like an insulator
356. The band gap of silicon at 300k is (c) Has a few holes and the same number of
(a) 1.36 eV (b) 1.10 eV electrons
(c) 0.08 eV (d) 0.67 eV (d) Behaves like a metallic conductor
Mizoram PSC IOLM -2018, Paper I MPPSC Forest Service Exam.-2014
Nagaland PSC CTSE (Degree) -2015, Paper I Ans. (b) : An intrinsic semiconductor at 0°K, has
electron only in valence band. There is no electron in
Ans. (b) : The band gap of silicon at 300ºK is 1.10 eV conduction band. Hence at 0°K, it behaves like an
357. N-type silicon is obtained by doping silicon insulator.
with 361. At room temperature, which one of the
(a) Germanium (b) Aluminum following band gap energy Eg corresponds to
(c) Boron (d) Phosphorus that of a semiconductor?
Nagaland PSC CTSE (Degree) -2015, Paper I (a) Eg = 0 eV (b) Eg = 1.2 eV
Ans. (d) : N-type silicon is obtain by doping silicon (c) Eg = 5 eV (d) Eg = 9 eV
with Phosphorus. DRDO-2009
Ans. (b) : At room temperature band gap energy (Eg) < 3.6 ×10−4
5eV corresponds to a semiconductor. Energy band gap ⇒ µ=
of silicon is 1.12 eV and germanium is 0.7 eV. 9 × 10−3
⇒ µ = 0.04 m2V–1S–1
362. Which one of the following represents a direct
1
band-gap material? n=
(a) Si (b) Ge R H .e
(c) GaP (d) GaAs 1
BSNL(JTO)-2009 n=
3.6 ×10 × 1.6 ×10−19
−4
Ans. (d) : Direct band gap semiconductor are those N = 1.74 ×1022 m–3
semiconductor materials which produce light after 365. GaAs has bandgap energy of 1.42 eV. The
recombination instead of heat. material would produce photon output at a
One of famous material used is GaAs which wavelength of (Planck's constant
contain mixed bonding i.e. covalent bond necessarily -34 -19
= 6.625 ×10 J - s , q = 1.6 ×10 C )
one any other bond.
(a) 0.553 µm (b) 0.653 µm
363. Which one of the following statements is NOT (c) 0.875 µm (d) 0.953 µm
true? Mizoram PSC IOLM-2010, Paper-I
(a) In an intrinsic semiconductor, concentration BSNL(JTO)-2009
of electrons in the conduction band is same as Ans. (c) : Bond energy (Eg) = 1.42eV
the concentration of holes in the valence
1.24
band. Eg =
(b) The probability of an energy state at the λ (µm)
Fermi level being occupied by an electron is 1.24
1/2. λ=
1.42
(c) Mobility of electrons is higher than that of λ = 0.875µm
holes.
366. A common LED is made up of
(d) In an n-type semiconductor, concentration of
(a) intrinsic semiconductor
holes is equal to that of the intrinsic (b) direct semiconductor
concentration. (c) degenerate semiconductor
BSNL(JTO)-2009 (d) indirect semiconductor
Ans. (d) : • In an intrinsic semiconductor, DRDO-2008
concentration of electrons in the conduction band is Ans. (b) : LED's are made up from Direct bandgap
same as the concentration of holes in the valence band. semiconductor, It is a widely used standard source of
• The probability of an energy state at the Fermi Level light in electrical equipment.
being occupied by an electron is 1/2. 367. The electron density profile in a piece of
• Mobility of electrons is higher than that of holes is semiconductor at equilibrium is such that
true. n(x1) = 10n(x2). The hole density profile will be
In an n-type semiconductor, concentration of holes is such that :
equal to that of the intrinsic concentration. This (a) p(x1) = 10p(x2)
statement is not true. (b) p(x2) = 10p(x1)
364. A doped semiconductor specimen has Hall (c) p(x1) = 100p(x2)
coefficient 3.6 × 10–4 m3C–1 and the resistivity (d) insufficient information to answer
9×10–3Ωm. Assuming single carrier conduction, BSNL(JTO)-2002
the mobility and density of carriers in the Ans. (b) : Given,
specimen, respectively, are (approximately) Electron density n(x1) = 10 n(x2) hole density =?
At equilibrium
(a) 0.04 m 2 V −1s −1 and 1.74 × 10 22 m −3 n1p1 = n2p2
(b) 0.4 m 2 V −1s −1 and 1.74 × 10 22 m −3 so hole density p(x2) = 10p(x1)
(c) 0.04 m 2 V −1s −1 and 1.74 × 1018 m −3 368. The semiconductor used for LEDs emitting in
(d) 4.0 m 2 V −1s −1 and 1.74 × 1018 m −3 the visible range is
BSNL(JTO)-2009 (a) GaAs (b) GaAlAs
(c) GalnAs (d) GaAsP
Ans. (a) : Given in question- BSNL (JTO)-2006
Hall coefficient = 3.6 ×10–4 m3c–1
Ans. (d) : Visible LED have been available
Resistivity = 9×10–3Ωm commercially since the 1960s. The early LEDs utilized
µ  1 the gallium arsenide phosphide (GaAsP) material
RH = Q ρ = 
σ  σ system. They were direct energy-gap devices with near
⇒ µ = RH. σ band edge emission, which limited them to the red-
spectral region with an emission wavelength of 650 nm.
R GaAsP semiconductor is used for LED emitting in the
⇒ µ= H
ρ visible range light.

369. The polar bonds existing in III-V compound (a) 2.5 × 1013 cm–3 (b) 6.25 × 1013 cm–3
semiconductor, may be considered as (c) 6.25 × 10 cm 15 –3
(d) 2.5 × 1016 cm–3
equivalent to DRDO-2009
(a) 1 ionic bond and 3 covalent bonds Ans. (c) : Given,
(b) 1 ionic bond and 4 covalent bonds ρ = 0.625Ωcm, µ n & µ p = 1600cm 2 V − S
(c) 2 ionic bonds and 2 covalent bonds
1 1 1
(d) 2 ionic bonds and 4 covalent bonds σ = = eN Dµ n , N D = =
BSNL (JTO)-2006 ρ ρµ n e 0.625 ×1600 × 1.6 × 10−19
−3
Ans. (a) : The polar bonds existing in III-V compound N D = 6.25 × 10 cm 15
semiconductor, may be considered as equivalent to 1 373. The diffusion constant and mobility for
ionic band and 3 covalent bonds. electrons in a semiconductor material at a
370. In order to generate electron-hole pairs, the given temperature are 20 cm2/s and 1600
maximum wavelength of radiation for Silicon cm2/V-s, respectively. The thermal voltage VT
(Band gap = 1.1 eV) is for a diode made of this material at the same
(a) 1.88 µm (b) 1.68 µm temperature is :
(c) 1.13µm (d) 1.54 µm (a) 125 mV (b) 32 mV
BSNL (JTO)-2006 (c) 12.5 mV (d) 3.2 mV
DRDO-2009
Ans. (c) : Photon energy ( E g = hν)
Ans. (c) : Given, diffusion constant D = 20cm 2 s
C
h. = E g [ V = C / λ ] and mobility µ = 1600cm 2 / V − S
λ
D 20
hC 6.62 ×10−34 × 3 × 108 Thermal voltage VT = =
λ= = = 1.13µm µ 1600
Eg 1.1× 1.6 × 10−19
VT = 12.5mV
371. What is the change of barrier height of p-n 374. If n, n , µ and µ , respectively denote electron
i n p
junction of 300º K when doping in n-side is concentration, intrinsic concentration,
increased by a factor of 1000 and doping in p- mobility of electrons and mobility of holes, the
side remain unchanged? minimum conductivity of a semiconductor
  kT  sample occurs at
 Hint : at 300º K  = 0.026 V  
  q  µ µ
(a) n = n i p (b) n = n i n
(a) 0.18 V (b) 1.8 V µn µp
(c) 0.018 V (d) 0.14 V
BSNL (JTO)-2006 (c) n = n i µ n , µ p (d) n = n i µ n + µ p
Ans. (a) : BSNL(JTO)-2009
kT NA ND Ans. (a) : The conductivity of semiconductor is :
V0 = log e mV σ = nqµ n + Pqµ p
q n i2
Mass action law-
 N A1 N D1 
VB1 = 26 ln   mV n i2 = np
2
 ni  n i2
 NA ND  P =
n
VB2 = 26 ln  2 2 2 
 ni  n2
 2  σ = nqµ n + i qµ p
 N A 2 N D2  n
VB2 − VB1 = 26 ln   dσ
For the minimum conductivity =0
 N A1 N D1  dn
 ND   −1 
{
= 26 ln  2  Q N A2 = N A1 } qµ n + n i2  2  qµ p = 0
n 
 N D1  2
n
= 26ln (1000 ) mV n 2 = i ⋅µ p
µn
= 179.60 mV 0.18V
372. Resistivity of an n-type Si material at a n = n µ p
µn
i
particular temperature is 0.625 Ω cm. The
electron and hole mobilities in that material at 375. At a given temperature a semiconductor with
the same temperature are µn = 1600 cm2/V-s intrinsic carrier concentration ni = 1016/m3 is
and µp = 1600 cm2/V-s respectively. Which one doped with a donor of dopant concentration ND
of the following best represents the donor = 1026/m3. Temperature remaining the same the
dopant concentration ND? hole concentration in the doped semiconductor is
(a) 1026/m3 (b) 1016/m3 378. Resistivity of p-type specimen is 0.12Ω-m hole
(c) 1014/m3 (d) 106/m3 mobility is 0.048 m2 V-1 s-1 (electron charge =
DRDO-2008 1.6×10-19 Coulomb) and intrinsic concentration
Ans. (d) : Given- is 5.9×1010 cm-3 Then the electron
16 3
Intrinsic carrier concentration ni = 10 /m concentration in the specimen is
Dopand concentration N D = 10 26 m3 (a) 1.085 × 1015 cm −3 (b) 3.206 × 106 cm −3
−3
n i2 (c) 5.9 × 10 cm
10
(d) 1.085 × 106 cm −3
∴ Hole concentration N P = BSNL (JTO)-2006
ND
Ans. (b) : Gives as :-
1032 Resistivity of p type δ n = 0.12Ω − m
N P = 26
10 holes mobility µ p = 0.048m 2 V −1S−1
N P = 10 m
6 3
intrinsic carrier concentration n i = 5.9 × 1010 cm −3
376. At room temperature the diffusion and drift 1
constants for holes in a P-type semiconductor resistivity ρ =
were measured to be D = 10 cm /s and µ =2 pq µp
p p
1200 cm2/V-s, respectively. If the diffusion 1 1
constant of electrons in an N-type P = ρqµ = 0.12 × 1.6 × 10−19 × 0.048
p
semiconductor at the same temperature is Dn =
2
20 cm /s, the drift constant for electrons in it is P = 108.507 × 1019 / m 3 =1.085×1021/m3=1.085×1015/cm3
(a) µ n = 2400 cm / V − s
2 according to mass action low-
( )
2
(b) µ n = 1200 cm / V − s
2
n i2 5.9 ×1010
n= = 3.206 × 106 cm −3
(c) µ n = 1000 cm 2 / V − s p 1.085 ×10 15
(d) µ n = 600 cm 2 / V − s 379. GaP were used as light emitter to achieve pale
DRDO-2008 (a) red light (b) yellow light
Ans. (a) : Given- Dp = 10 cm /s 2 (c) green light (d) blue light
µ P = 1200cm V − S
2
Ans. (c) : GaP (Gallium phosphide) has been used to
D n = 20cm 2 S achieve green light.
µn = ? 380. Which element has 10 electrons?
Dn D P (a) Na (b) Ne
= (c) Ar (d) He
µn µ P RRB JE- 31.08.2019, 10 AM-12 PM
20 10 Ans. (b) : Ionic structure 1s 2 , 2s 2 , 2p6
⇒ =
µ n 1200 so Ne (Neon) has 10 electron.
⇒ µ n = 2400 cm 2 V − S Na has11 electron.
377. Let EFn and EFp' respectively, represent the He has 2 electron.
effective Fermi levels for electrons and holes Ar has 18 electrons.
during current conduction in a semiconductor. 381. Drift current in semiconductors depends upon
For lasing to occur in a P-N junction of band- (a) only the electric field
gap energy 1.2 eV. (EFn – EFp) should be (b) only the carrier concentration gradient
(a) greater than 1.2 eV (b) less than 1.2 eV (c) both the electric field and the carrier
(c) equal to 1.1 eV (d) equal to 0.7 eV concentration
DRDO-2008 (d) both the electric field and the carrier
Ans. (b) : concentration gradient
Ans. (c) : Drift current in semiconductors depends upon
both the electric field and carrier concentration. Drift
current density in a material can be given by
J = Jn +Jp
J = qnµnE + qpµpE
J = q(nµn+pµp)E
µ = Ability of mobile charge to acquire drift velocities
When the crystal unbiased condition, E Fn − E FP = 0 in the presence of the electrical field.
382. In an extrinsic semiconductor, the Hall
After crystal biased condition, E Fn − E FP < E G coefficient RH
Therefore E Fn − E FP < 1.2 eV (a) Increases with increase of temperature
(b) Decreases with increase of temperature
(c) Is independent of the change in temperature 388. Which of the following impurity is doped into
(d) Changes with the change of magnetic field an intrinsic semiconductor to obtain p-type
Nagaland PSC CTSE (Degree)-2018, Paper-I semiconductor?
Ans. (b) : In an extrinsic semiconductor, the Hall (a) Antimony (b) Arsenic
coefficient. RH decrease with increase of temperature. (c) Gallium (d) Phosphorus
Hall coefficient (RH) depend on the mobility carriers KVS TGT (WE)- 2014
and concentration of hole and electron. Ans (c): If we have to obtain P-type semiconductor ,
383. Hall effect device can be used to− doping of third group element (B, A l , Ga, In) is done
(a) Subtract one signal from another in intrinsic semiconductor.
(b) Add two signals 389. The band gap energy (Eg) is the minimum
(c) Divide one signal by another on an energy required to break a covalent bond and
instantaneous basis
thus, generates :
(d) Multiply two signals
(a) bound charge only
RRB JE-01.09.2019, 3:00 PM – 5:00 PM
(b) an electron – hole pair
Ans. (d) : Hall effect device can be used to multiply (c) electrons only
two signals. A Hall effect sensor is device which
(d) holes only
measuring the magnitude of a magnetic field and
KVS TGT (WE)- 2017
voltage is reciprocal strength of the magnetic field.
384. The number of proton in Silicon atom are Ans. (b) : The minimum energy required to break a
covalent bond is 0.72 eV for germanium (Ge) and
(a) 12 (b) 14
1.1eV for silicon (Si). At higher temperature, the
(c) 8 (d) 2
number of electrons passing over to the conduction
TNPSC AE-2013
band is higher, leaving equal no. of holes in the valence
Ans. (b) : band. When a covalent bond break it generates an
The atomic no. of silicon = 14
electron and hole pair.
Hence number of proton = 14
385. The barrier capacitance CT 390. Energy band gap of an insulating materials is:
(a) Increases with the width of the space charge (a) 0 eV (b) greater than 5 eV
layer (c) less than 5 eV (d) equal to 1 eV
(b) Increase with increasing reverse voltage LMRC AM- 16.07.2021
(c) Is due to the immobile charges at the junction KVS TGT (WE)- 2018
varying with the applied voltage Ans. (b) : An insulating materials has large band gap, or
(d) Can be defined as Q/V a large energy difference between the valence and
Nagaland PSC CTSE (Degree)- 2016, Paper-I conduction band. Energy band gap of insulating
Ans. (c) : The capacitance that exists between the p- material is greater than 5eV.
type and n-type semiconductor material in a semi- (ii) Semiconductor – Si– 1.1eV
conductor. It is due to immobile charge at the junction – Ge – 0.7eV
varying with the applied voltage. (iii) Conductor ≅ 0eV
386. The diffusion current is proportional to 391. Under low level injection assumption the
(a) Applied electric field injected minority carrier current for an
(b) Square of applied electric field extrinsic semiconductor is essentially the
(c) Concentration gradient of charge carrier (a) Diffusion current
(d) A constant value given by Fermi level (b) Drift current
Nagaland PSC CTSE (Degree)- 2016, Paper-I (c) Recombination current
Ans. (c) : The diffusion current density is directly (d) Induced current
proportional to the concentration gradient. Nagaland PSC CTSE (Degree) -2015, Paper I
Concentration gradient is the difference in concentration Mizoram PSC Jr. Grade-2015, Paper-I
difference of electrons or holes in a given area.
Ans. (a) : Under low level injection assumption the
387. Ratings on a capacitor are 25µF , 12V symbol injected minority carrier current for an extrinsic
for plus is also drawn near one of its terminals. semiconductor is essentially the diffusion current.
Which type of capacitor is it? 392. According to the Einstein relation, for any
(a) Mica capacitor
semiconductor the ratio of diffusion constant to
(b) Ceramic capacitor
mobility of carrier :
(c) Electrolytic capacitor
(d) Air gang capacitor (a) depends upon the temperature of the
KVS TGT (WE)- 2014 semiconductor
(b) depends on the type of semiconductor
Ans. (c) : A capacitor rated 25 µF , 12V has a positive (c) varies with life time of the semiconductor
symbol drawn on one terminal then it will be an electrolytic (d) is a universal constant
capacitors consider polarity and operate on DC. Nagaland PSC CTSE (Degree) -2015, Paper I
Ans. (a) : According to the Einstein relation, for any Ans. (c) : since, Nd >> ni, we can approximate
semiconductor the ratio of diffusion constant to no = Nd and ni = 1.5 × 1010
mobility of carrier depends upon the temperature of the n i 2 2.25 × 1020
semiconductor. Einstein equation . po = = = 2.25 × 103 cm −3
n0 1017
Dn Dp T(K)
= = VT = n0
µn µp 11600 E F − Ei = kT l n
ni
393. Which of the following statements is true for an
‘N-type’ semiconductor?  1017 
= 0.0259l n  10 
(a) Only electrons are the carriers.  1.5 × 10 
(b) Holes are majority carriers and electrons are
= 0.407eV
minority carriers.
(c) Only holes are the carriers. 397. Which one of the following statements is not
(d) Electrons are majority carriers and holes are correct regarding carrier lifetime in
minority carriers. semiconductors?
LMRC AM- 16.07.2021 (a) Carrier lifetime ranges from nanoseconds to
Ans. (d) : In N-type semiconductor electrons are hundreds of microseconds.
majority carriers and holes are minority carriers. We (b) On an average, a hole (an electron) will exist
can get a N type semiconductor adding impurity of for τp sec before recombination.
pentavalent to a intrinsic semiconductor. (c) τp is the time, it takes the total concentration to
394. Which of the following is a true comparison of fall to approximately 63% of its initial value.
P and N type semiconductors? (d) τp is the time, it takes the injected
(a) Conductivity of P-type semiconductor is concentration to fall to approximately 37% of
greater than that of the N-type semiconductor its initial value.
because of hole as majority carrier. ESE-2022
(b) Conductivity of N-type semiconductor is
Ans. : (c) :
greater than that of the P-type semiconductor
Carrier lifetime ranges from nanoseconds to
because of hole as majority carrier.
hundreds of microseconds.
(c) Conductivity of P-type semiconductor is
greater than that of the N-type semiconductor On an average a hole (an electron) well exist for τp
because of electron as majority carrier. sec before recombination.
(d) Conductivity of N-type semiconductor is τp is the time, it take the Injected concentration to
greater than that of the P-type semiconductor fall to approximately 37%, of its initial value.
because of electron as majority carrier. Hence option (c) not correct.
LMRC AM- 16.07.2021 398. At what condition does the Fermi energy level
Ans. (d) : Conductivity of N-type semiconductor is (EF) lie exactly between the band gap for
greater than that of the p-type semiconductor because of intrinsic semiconductor?
electron as majority carriers. (a) The effective masses of a hole and a free
395. In which of the following materials does electron are the same
conduction happen due to thermal excitation or (b) The effective mass of a free electron is less
crystal defects? than the effective mass of a hole
(a) Insulator (c) The effective mass of a free electron is
(b) Intrinsic semiconductor greater than the effective mass of a hole
(c) Extrinsic semiconductor
(d) The effective mass of a hole is always in the
(d) Metal
centre of the forbidden energy band
LMRC AM- 16.07.2021
ESE-2022
Ans. (b) : In intrinsic semiconductor material
(a) : The Fermi energy level (EF) lie exactly between
conduction happen due to thermal excitation or crystal
the band gap for intrinsic semiconductor. The effective
defects.
masses of a hole and a free electron are the same.
396. A Si sample is doped with 1017 Arsenic
atoms/cm3. Displacement of EF relative to Ei is 399. If temperature will increase, the conductivity of
_____. semiconductor will:
(a) Positive, 0.589 eV (a) Increase
(b) Negative, 0.589 eV (b) Remains the same
(c) Positive, 0.407 eV (c) Decrease
(d) Negative, 0.407 eV (d) Decrease rapidly
DFCCIL Executive (S&T) 11.11.2018, 4:30 to 6:30PM DFCCIL Executive S&T-17.04.2016, Shift-II

Ans. (a) : The conductivity of an intrinsic (a) 4396 cm2/V-s (b) 3 × 104 cm2/V-s
semiconductor depends upon the numbers of hole (c) 6 × 104 cm2/V-s (d) 52 cm2/V-s
electron pairs and mobility. The numbers of hole UPRVUNL AE– 11.06.2014
electrons pairs increase with increase in temperature, Ans. (d) : Given that,
while its mobility decreases. Semiconductor has length ( l ) = 4cm
negative temperature coefficient of resistance, so when
temperature increases, conductivity increases and Voltage ( V ) = 8Volt
resistivity decreases. drift velocity – (Vd) = 104 cm/s
400. If f(E) is Fermi dirac distribution function then V
1-f(E) is the probability: µ = d …………..(i)
E
(Where Ef is Fermi level)
V 8
(a) That a state is empty below Ef E = = = 2 Volt cm
(b) That a state is filled below Ef l 4
(c) That a state is empty above Ef putting the value E in equation (i)
(d) That a state is filled above Ef 104
µ= = 52cm 2 V − S
UPRVUNL AE– 11.06.2014 2
Ans. (a) : The probability that an electron occupies an 403. The maximum number of electrons the N shell
energy level E is given the Fermi-Dirac probability can have is _______.
function and it can be expressed by (a) 8 (b) 18
1
f (E) = (c) 32 (d) 16
 E − EF  KVS TGT (WE)- 2016
1 + exp 
 KT  Ans. (c) : The maximum number of electrons the N
the probability that the energy level is not filled with an shell can have is 32 according to 2n2 rule.
electron i.e., empty = 1–f (E) K  → 2
1 L  → 8
= 1−
 E − EF  M  → 18
1 + exp  
 KT  N  → 32
1  → 50
1− f (E) = O
 − ( E − EF ) 
1 + exp   P  → 72
 KT  404. The number of electrons in the M shell of
1
1− f (E) = germanium is _______.
 − ( E − EF )  (a) 4 (b) 18
1 + exp  
 KT  (c) 8 (d) 2
An energy state being empty is equivalent to the KVS TGT (WE)- 2016
presence of a hole, i.e. positively charged particle. Ans. (b) : The number of electrons in the M shell of Ge
401. In a p-type silicon sample, the hole is 18 The atomic number of Ge = 32
concentration is (1.5 × 1010)/cm3. If the intrinsic K = 2 
carrier concentration is 3.0 × 1010/cm3, the L = 8 
electron concentration would be _____ .  
(a) 0 (b) 6 × 1010 /cm3  M = 18
 
N = 4 
5 3
(c) 6 × 10 /cm (d) 1.5 × 105 /cm3
UPRVUNL AE– 11.06.2014
405. Which of the following is referred to as
Ans. (b) : given that,
majority carriers in a p-type material?
hole concentration(p) =1.5×1010/cm3
(a) Electrons
Intrinsic carrier concentration (ni) =3.0×1010/cm3
(b) Donor impurities
We know that
(c) Discrete energy
mass action law n ⋅ p = n 2i (d) Holes
DFCCIL Executive S&T 29.09.2021, 12:30 to 2:30PM
n 2 ( 3.0 × 10 )
10 2
9.0 ×1020 Ans. (d) : In P-type semiconductor holes are majority
n= i = = = 6 × 1010 / cm 3
p 1.5 ×10 10
1.5 × 1010 charge carriers and electrons are minority carriers. P-
402. A semiconductor bar having a length of 4 cm is type semiconductor is formed by third group element
subjected to a voltage of 8 Volts. If the average like Boron, Gallium, Indium etc.
drift velocity is 14 cm/s, then electron mobility N-type semiconductors are formed by fifth group
would be: elements.
Ans. (b) : Relation of wavelength (λ) and Band gap
(ii) p-n junction diode and Opto- (Eg) of LED light-
Electronics Eg =
hc
1. A p-n junction diode has a built in potential of λ
0.8 V. The depletion layer width at reverse bias 1
i.e E g or Vbi ∝
of 1.2 V is 2 µm. For a reverse bias of 7.2 V, the λ
depletion layer width will be Hence, band gap and wavelength both have inverse
(a) 4 µm (b) 4.9 µm relation, i.e- λ increase, the bandgap, and built in
(c) 8 µm (d) 12 µm potential decreases.
BPSC Asst. Prof. - 12.04.2022 Colour Wavelength (λ) Built-in potential
Nagaland PSC CTSE (Degree)-2017, Paper-I Red 650 nm 1.8 V
IES-2010 Blue 450 nm 5V
Ans. (a) : Depletion layer width, w ∝ VB Green 550 nm 2.2V
from the above data–
where, VB = V0 + V
V R< V G < V B
w1 V0 + V1 4. Consider a long rectangular bar of direct band-
=
w2 V0 + V2 gap p-type semiconductor. The equilibrium
hole density is 1017 cm–3 and the intrinsic
2µ 0.8 + 1.2 carrier concentration is 1010 cm–3. Electron and
=
w2 0.8 + 7.2 hole diffusion lengths are 2 µm and 1 µm,
respectively.
2µ 2
= The left side of the bar (x = 0) is uniformly
w2 8 illuminated with a laser having photon energy
w2 = 4 µm greater than the band-gap of the
2. For a diode in a reverse bias region, we have semiconductor. Excess electron-hole pairs are
_____ capacitance, while in the forward bias generated ONLY at x = 0 because of the laser.
The steady state electron density at x = 0 is 1014
region, we have ______capacitance.
cm–3 due to laser illumination. Under these
(a) Transition, Diffusion
conditions and ignoring electric field, the
(b) Diffusion, Depletion
closest approximation (among the given
(c) Transition, Depletion
options) of the steady state electron density at x
(d) Diffusion, Storage
UPPSC ITI Principal/Asstt. Director-09.01.2022
= 2 µm, is _________.
(a) 0.37 × 1014 cm–3 (b) 0.63 × 1013 cm–3
Ans. (a) : A diode in a reverse bias region, known as
‘transition capacitance’ while in forward bias region (c) 3.7 × 10 cm
14 –3
(d) 103 cm–3
known as ‘diffusion capacitance’. GATE-2022
Diffusion capacitance (CD)- Diffusion capacitance is Ans. (a) : Given as:
due to the transfer of minority carriers during the Hole density Po = 1017 cm −3
forward bias. Steady state electron density n 'p0 = 1014 cm −3
Transition capacitance (CT)- When a p-n junction is in
reverse bias then the depletion region acts like a Diffusion length L = 2µm
insulator. n i2 1020
Note: CD>CT i.e. diffusion capacitance is greater than ∴ no = = = 103 cm −3
transition capacitance. Po 1017
3. Red (R), Green (G) and Blue(B) Light Emitting Excess electron concentration at any distance x is
Diodes (LEDs) were fabricated using p-n ∴δn p ( x ) = n 'p0 ⋅ e − x Ln
junctions of three different inorganic
semiconductors having different band-gaps. = 1014 × e −2 2
The built-in voltages of red, green and blue = 1014 × e −1
diodes are VR, VG and VB, respectively Assume δn p = 0.367 ×1014 cm −3
donor and acceptor doping to be the same (NA
and ND respectively) in the p and n sides of all 5. If a certain Zener diode has a Zener voltage of
the three diodes. 3.6 V and reverse bias voltage of 5 V is applied
Which one of the following relationships about across it, the Zener operates in .
the built-in voltages in TRUE? (a) forward conduction
(a) VR > VG > VB (b) VR < VG < VB (b) avalanche breakdown
(c) VR = VG= VB (d) VR > VG < VB (c) regulated breakdown
BPSC Asst. Prof. - 12.04.2022 (d) Zener breakdown
GATE-2018 UPRVUNL AE -19.07.2021, Shift-II
Ans. (d) : Zener breakdown is observed in the zener Ans. (c) : We know that, emitter injection efficiency
diodes having breakdown voltage less than 5V or of doped npn transistor
between 5 to 8 volts. 1 1
When a reverse voltage is applied of a zener diode, it γ= =
cause a very intense electric field to appear across a 1+
D E N BX B 8 × 10 × 0.3 ×10−8
17
1+
narrow depletion region. By breaking covalent bonds DB N E X E 20 × 2 × 1018 × 0.5 ×10−8
electrons become free, which are available for 1 1
conduction. γ= = γ = 0.988 γ 0.99
0.3 1.012
1+
25
9. The advantage of ILD over LED is
(a) ILD emits incoherent light where as LED
emits coherent light
(b) In ILD is it difficult to couple light whereas in
6. The semiconductor material not used in LED LED it is easy to couple light
is: (c) In ILD coupling loss is more whereas in LED
(a) sillicon carbide (b) Si coupling loss is less
(c) GaAsP (d) GaAs (d) ILD emits coherent light whereas LED emits
UPRVUNL AE -19.07.2021, Shift-II incoherent light
Ans. (b) : IES-2020
Ans. (d) : ILD (injection laser diode) emits coherent
radiation in which the waves generated by the ILD are
at the same frequency.
LED (Light emitting diode) emits incoherent radiation
• LED works on Electro-luminescence principle. It is a which having spontaneous emission.
P-N junction device which is mainly made by gallium 10. The quantum efficiency η for the photo
arsenide (GaAs). L.E.D work in forward biasing mode. detector is
• It can also made by silicon carbide (SiC), Gallium
I ph I ph / e
arsenide phosphate (GaAsP) etc. (a) (b)
• Silicon (Si) and Germanium (Ge) are not suitable as P0 P0 /(hc / λ)
for LED materials because those junctions produce heat P P /(hc / λ)
and no appreciable infrared or visible light. (c) 0 (d) 0
I ph I ph / e
7. A P-N diode is in the _______ state if the
current established by the applied input is such Where,
that its direction matches that of the arrow in Iph = Average photocurrent
the diode symbol and diode voltage is greater Pe = Average incident optical power
than 0.7 V. hc/λ = Incident photon energy
(a) OFF (b) Reverse IES-2020
(c) ON (d) Transition Ans. (b) : quantum efficiency (η)
UPRVUNL AE -19.07.2021, Shift-II No. of electron − hole pairs regenerated
=
Ans. (c) : No. of incident − absorbed photons
Iph / e I ph / e
= =
Po / h f Po / ( hc / λ )
11. The voltage required to forward bias a P-N
When we applied input voltage (VD) greater than junction-based on silicon is :
diode's cut-in voltage or barrier voltage (0.7) the barrier (a) 0.15V (b) 0.32V
of diode breaks and electrons flow from N-region to P- (c) 0.55V (d) 0.70V
region, So the current flow from p-region to N-region APPSC POLY. LECT. 14.03.2020
through the junction. Ans. (d) :
At this condition P-N diode is in the ON state.
8. For a uniformly doped npn transistor, find the
approximate emitter injection efficiency.
Given that :
NE = 2×1018 cm–3 , NB = 1017 cm–3 , NC = 4×1019
cm–3 , DE = 8 cm2 /s , DC = 28 cm2/ s,
DB = 20 cm2/s , XE = 0.5 µm , XB = 0.3 µm.
(a) 0.95 (b) 0.92
(c) 0.99 (d) 0.94 If diode is silicon (PN junction)
ISRO Scientist Engg. -2020 forward biased voltage 0.7 V.
12. The typical forward bias voltage of an LED is : Ans. (d) : Photodetector also called photo sensor and it
(a) 1.6V (b) 3.3V sense of light or other electromagnetic radiation. When
(c) 0.82V (d) 0.68V used as a photo detector a photodiode should be reverse
APPSC POLY. LECT. 14.03.2020 biased.
Ans. (a) : A light-emitting diode is a semiconductor 18. The efficiency of energy conversion of a solar
light source that emits light when current flow through cell______with an increase in the ambient
it. The forward voltage rating of MOS LEDs is from 1V temperature.
to 3V and forward current rating range from 20 mA to (a) decrease
100 mA. (b) remains the same
(c) increase
13. For a maximum output power, the solar cell (d) Decreases first and then increases
must be operated at : APPSC POLY. LECT. 14.03.2020
(a) short circuited condition I0 = 0.
Ans. (a) : The efficiency of energy conversion of a
(b) open-circuited condition V0 = 0. solar cell deceases with a an increase in the ambient
(c) the knee of the V-I characteristics. temperature.
(d) the peak load of V-I characteristics.
19. A reverse-biased diode placed in series with the
APPSC POLY. LECT. 14.03.2020 emitter of the transistor makes the circuit
Ans. (c) : A solar cell is an electrical device that insensitive to variations in______with changes
converts the energy of light directly into electrical is the in the temperature.
photovoltaic effect. For maximum output power, the (a) VBE (b) ICO
solar cell must be operated at the knee at of the V-I (c) β (d) α
characteristics. APPSC POLY. LECT. 14.03.2020
14. An illuminated photo-diode without an Ans. (a) : A reverse biased diode placed in series with
external bias operates as a_____device. the emitter of the transistor makes the circuit insensitive
(a) photovoltaic (b) phototransistor to variation in VBE with changes in the temperature.
(c) photoresistor (d) photomultiplier 20. For an abrupt junction varactor diode, the
APPSC POLY. LECT. 14.03.2020 dependance of device capacitance (C) on
Ans. (a) : An illuminated photo-diode without an applied reverse voltage (V) is given by
external bias operated as a photovoltaic device. (a) C ∝ V1/ 3 (b) C ∝ V −1/ 3
15. The epitaxial growth allows the wafers to (c) C ∝ V 1/ 2
(d) C ∝ V −1/ 2
be_____by the diffusion process. Nagaland PSC CTSE (Degree)-2018, Paper-I
(a) passivated (b) oxidised Nagaland PSC CTSE (Degree)-2017, Paper-I
(c) doped (d) neutralised IES-1996
APPSC POLY. LECT. 14.03.2020 Gate-1995
Ans. (d) : Relation of space charge carrier capacitance
Ans. (c) : The epitaxial growth allows the wafers to be
and applied bias voltage is →
doped by the diffusion process.
C ∝ V−m
16. Within Fresnel diffraction range, the minimum
Where- m is constant
resolvable feature size is of the order
of_____when a proximity exposure system is • For an abrupt junction (or) step junction m should be
1/2 so-capacitance will be-
operating with a 10 µm gap and a light source
with a wavelength of λ = 365 nm. C ∝ V −1/ 2
(a) 1.91µm (b) 2.94µm 21.
In an abrupt p-n junction, the doping
(c) 2.56µm (d) 3.65µm concentrations on the p-side and n-side are
APPSC POLY. LECT. 14.03.2020 NA=9×1016/cm3 and ND=1×1016/cm3
Ans. (a) : g = 10 µm respectively. The p-n junction is reverse biased
Wavelength (λ) = 365 nm and the total depletion width is 3 µm. The
minimum resolvable feature size depletion width on the p-side is
Wmin = λg (a) 2.7 µm (b) 0.3 µm
(c) 2.25 µm (d) 0.75 µm
Wmin = 10 ×10 × 365 × 10
−6 −9
RPSC VP/Suptd. ITI 05.11.2019
Wmin = 365 ×10−14 Punjab PSC Poly. Lect. 20.08.2017
Nagaland PSC CTSE (Degree) - 2017, Paper-I
Wmin = 1.91 µm KVS TGT (WE)- 2014
17. When used as a photo detector, a photodiode GATE-2004
should be : Ans. (b) : In the abrupt p-n junction diode by using
(a) open-circuited (b) short-circuited charge density condition or charge neutrality condition-
(c) forward biased (d) reverse biased Wn N A
APPSC POLY. LECT. 15.03.2020 =
Wp N D
APPSC POLY. LECT. 14.03.2020
Given- Ans.(c): Given,
NA = 9×1016/cm3 R = 100 Ω, IF = 100 mA, VR = 10V, IR = ?
ND = 1×1016/cm3 For forward bias at t < 0
WT = 3 µm
Wp = ?
NA
Wn = × Wp
ND
9 × 1016 / cm3 For reverse bias at t = 0
Wn = × Wp
1 × 1016 / cm3
Wn = 9Wp µm
WT = Wp + Wn
3µm = Wp + Wn VR
Reverse current I R =
3µm = Wp + 9Wp R
10
3µm = 10Wp = Amp = 0.1Amp
100
Wp = 0.3 µm
= IR = 100mA
22. Avalanche breakdown is primarily depend on
25. A crystal diode is used as………….
the phenomenon of
(a) an amplifier (b) a rectifier
(a) Collision (b) Doping
(c) an oscillator (d) a voltage regulator
(c) Ionization (d) Recombination Nagaland PSC CTSE (Diploma)-2017, Paper-I
Nagaland PSC CTSE (Diploma)-2018, Paper-I Nagaland PSC CTSE (Degree)-2016, Paper-I
Mizoram PSC Jr. Grade-2015, Paper-I Mizoram PSC AE/SDO 2012-Paper-I
TNPSC AE-2008 Ans. (b) : A crystal diode is used as a rectifier to convert
Ans. (a) : Avalanche Breakdown- A thermally the AC into DC. As it conducts only in one direction and
generated carrier falls down the junction barrier and blocks the current flow in the reverse direction as similar to
acquires energy from the potential. This carrier collides the normal diode it can be used to design the half wave,
with a crystal ion and imparts sufficient energy to full wave and bridge rectifier circuits.
disrupt a covalent band. 26. A PIN diode is frequently used as a
23. Which of the following is NOT associated with (a) Peak clipper
a p-n junction ? (b) Voltage regulator
(a) Junction Capacitance (c) Harmonic generator
(b) Charge Storage Capacitance (d) Switching diode for frequencies up to GHz
(c) Depletion Capacitance range
(d) Channel Length Modulation Nagaland PSC CTSE (Degree)-2017, Paper-I
GPSC Asstt. Prof. 11.04.2017 Nagaland PSC CTSE (Degree)- 2016, Paper-I
TSPSC Manager (Engg.) -2015 Ans. (d) : A PIN diode is frequently used as a switching
GATE-2008 diode for frequencies upto GHz range. It is a microwave
switch. In PIN diode the intrinsic semiconductor is
Ans. (d) : The junction capacitance is also referred to as sandwiched in between high doped P and high doped N
charge storage capacitance and Depletion capacitance, it regions.
is formed when a P-N junction is in reverse bias This property is used in fields of light sensors, images
condition, Hence, channel Length Modulation is not scanners, artificial retina systems.
associated with p-n junction diode. 27. LEDs fabricated from GaAs and GaAsP emits
24. An ideal p-n junction diode in series with a radiation in the
100 Ω resistor is forward biased such that the (a) Ultraviolet region and Infrared region respectively
forward current flowing through the diode is (b) Infrared region and Visible region respectively
100 mA. If voltage across this circuit is (c) Visible region and Infrared region respectively
instantaneously reversed to 10 V at time instant (d) Infrared region and Ultraviolet region
t = t0, then the reverse current flowing through respectively
the diode at time instant t = to is approximately TNPSC AE – 2018, 2008
given by Ans. (b) :
(a) 0 mA (b) 200 mA
(c) 100 mA (d) 2 mA
ISRO Scientist Engg.-2011 • LED emits the light visible spectrum or invisible
Gate-1992 spectrum of light.
• In the invisible spectrum of light LED emits infrared 31. Heavy doping is tunnel diode results is
light and in the visible spectrum of light, LED emits (a) an indefinite depletion region
different colors of light i.e. (Red, Green, Orange, (b) an extremely narrow depletion region
Yellow, blue etc). (c) avoiding the formation of depletion region
• LED is fabricated from GaAs and GaAsP emits (d) slow growth of depletion region
radiation in the infrared region and visible region TNPSC AE - 2018
respectively. Ans. (b) : Tunnel diode (or Esaki diode)-
28. Diodes are used to clip voltages in circuits
because they act as
(a) Dependent current sources whose current is
clipped by the load resistor value
(b) Inductors that can remove current spikes
(c) Current sources under certain bias conditions
(d) Voltage source under certain bias conditions
TNPSC AE - 2018
Ans. (d) :
The concentration of impurities in tunnel diode is nearly

a thousand time greater than normal P-N junction diode.
When used heavily doped material in a diode, the
majority concentration are increases more than normal
diode and the impurities in tunnel diode is nearly a
If Vf1 = Vf2 = 0.7V ( for Si ) thousand time greater than that in the normal P-N
then Vi = VD − Vf1 = VD − 0.7 and junction diode.
Hence depletion region becomes extremely narrow in a
V2 = VD − Vf2 = VD − 0.7 tunnel diode.
Hence, diodes are used to clip voltages in circuits 32. The number of minority carrier crossing the
because they acts as voltage source under certain bias junction of a diode depends primarily on the
conditions. The value of clipping voltage is equal to the (a) Concentration of doping impurities
knee voltage of given diodes. (b) Magnitude of the potential barrier
29. A laser diode has a relative spectral width of 2 (c) Magnitude of the forward bias voltage
× 10–3 and it's emitting a mean wavelength of 1 (d) Rate of thermal generation of electron hole
µm. What is its spectral half-width? pairs
(a) 1 µm (b) 0.2 µm KVS TGT (WE)- 2014
(c) 20 µm (d) 2 nm TNPSC AE - 2018
TNPSC AE - 2018 Ans. (d) : The number of minority carriers crossing the
Ans. (d) junction of a diode depends primarily on the rate of
thermal generation of electron hole pair. Thermal
Given, relative spectral width ( λ 0 ) = 2 × 10 −3 m generation is always present whenever the temperature
Mean wavelength ( λ ) = 1µm = 10 −6 m of material is greater than zero Kelvin.
33. Compared to field effect photo transistor,
Spectral half-width ( ∆ λ ) = λ 0 .λ bipolar photo transistors are
= 2×10–3×10–6 (a) More sensitive and faster
λ = 2 × 10 −9 m (b) Less sensitive and slower
(c) More sensitive and slower
λ = 2nm (d) Less sensitive and faster
30. A LED is emitting a mean wavelength of λ = ISRO Scientist Engg.-2016
0.90 µm and its spectral half-width ∆λ = 18 nm. ISRO Scientist Engg.-2008
What is its relative spectral width? Ans. (a) : In terms of sensitivity and speed, bipolar
(a) 0.02 (b) 0.05 photo transistors have better performance as compared
(c) 0.90 (d) 18 to field effect photo transistor because of internal
amplification.
TNPSC AE - 2018
The frequency response of these bipolar photo
Ans. (a) : Given, λ = 0.90µm, ∆λ = 18nm transistors are much lower than field effect photo
∆λ 18 × 10 −9 transistor because of the charge storage effects.
Relative spectral width ( λ 0 ) = = Hence, bipolar photo transistors are more sensitive and
λ 0.9 × 10 −6
−2
faster as compared to field effect photo transistor.
λ 0 = 2 × 10 m 34. What is the typical value of the ratio of current
λ 0 = 0.02 m in a p-n junction diode in the forward bias and
that in the reverse bias?
(a) 1 (b) 10 39.
In an unbiased P-N junction, thickness of
(c) 0.10 (d) 1000 depletion layer is of the order of
GPSC Asstt. Prof. 11.04.2017 (a) 0.005 µm (b) 0.5 µm
IES-2008 (c) 5 µm (d) 1nm
Ans. (d) : In P-N junction diode, the forward biased Mizoram PSC AE/SDO 2012-Paper-I
current is in milli ampere and reverse biased current is Ans. (b) : Thickness of depletion layer in an unbiased
in microampere. P-N junction is of the order of 0.5 µm.
So, the ratio of forward current and reverse current 40. The reverse saturation current of a silicon
mA 10 −3 diode doubles for every
= = 1000 (a) 10ºK rise in temperature
µA 10 −6
(b) 10ºC rise in temperature
35. At higher forward voltages, a junction diode is (c) 2ºC rise in temperature
likely to (d) 10ºF rise in temperature
(a) burnout (b) get saturated LMRC AM (S&T)-13.05.2018
(c) suffer break down (d) become noisy KVS TGT (WE)- 2018
Mizoram PSC AE/SDO 2012-Paper-I Mizoram PSC AE/SDO 2012-Paper-I
Ans. (a) : At higher forward voltage, the velocity of Ans. (b) : The reverse saturation current is only due to
mobile ions is very high. So there is a black spot occursminority carriers. It flows only in reverse biased
on the layer. Hence at higher forward voltage, a connection. It is highly sensitive to temperature. For
junction diode may be burn out. 1ºC reverse saturation current approx increases by 7%
36. A general purpose diode is more likely to suffer and doubles for every 10ºC rise in temperature.
avalanche breakdown rather than zener 41. There is a small amount of current across the
breakdown because barrier of a reverse-biased diode. This current
(a) its leakage current is small is called
(b) it has strong co-valent bond (a) Forward-bias current
(c) it is lightly doped (b) Reverse breakdown current
(d) it has how reverse resistance (c) Conventional current
Mizoram PSC AE/SDO 2012-Paper-I (d) Reverse leakage current
Ans. (c) : A zener diode is a highly doped diode. So a Mizoram PSC IOLM -2018, Paper I
general purpose diode is more likely to suffer avalanche Ans. (d) : There is a small amount of current across the
breakdown rather than zener breakdown because of it is barrier of a reverse biased diode. The current is called
a lightly doped. reverse leakage current. It is very less as compare to
37. The turn on voltage of a Ge junction diode is load current.
(a) 0.1 V (b) 0.3 V 42. Increase in the applied reverse voltage to a p-n
(c) 0.7 V (d) 1.0 V junction results an increase in the
Mizoram PSC AE/SDO 2012-Paper-I (a) Depletion width
Ans. (b) : Turn on voltage or knee voltage is the (b) Barrier height
minimum voltage to turn ON the diode (c) Depletion width and barrier height
For Ge - VON = 0.3 V (d) Junction temperature
For Si - VON = 0.7 V UJVNL AE-2016
38. The depletion region of a P-N junction is one Ans. (c) : When reverse voltage across the p-n junction
that is depleted of diode increases, current flow through diode decrease
(a) atoms (b) mobile charges because it's depletion width increase.
(c) electrons (d) immobile charges 43. When a metal and semiconductor is joined the
Mizoram PSC AE/SDO 2012-Paper-I diode formed is
Ans. (d) : (a) Zener (b) PIN Diode
(c) Schottky (d) Tunnel
UJVNL AE-2016
Ans. (c) : When a metal piece and a semiconductor are
joined together then it is a schottky diode. The schottky
diode is also known as schottky barrier diode or also
known as hot carrier diode. It has fast recovery time so
it is used in high-speed switching. It can also operate
high frequency. It has high current density.
A depletion layer in P-N junction is layer which contain 44. Typically silicon transistors are operated over
immobile ions which are not movable. temperature range extending from
Electrons and holes in depletion layer are not free for (a) –25ºC to +175ºC (b) –65ºC to +75ºC
depletion layer consist of a large number of ions and (c) –65ºC to +175ºC (d) –25ºC to + 75ºC
covalent bands. TNPSC AE-2014
Ans. (c) : Typically silicon transistors are operated over Ans. (c) : Barrier potential or depletion region, At the
temperature range extending from –65ºC to + 175ºC. instant of the P-N junction formation free electrons near
Peak inverse voltage (PIV) rating is the maximum the junction diffusion across the junction into the p-
reverse biased voltage at which the diode can withstand. region and combine with holes.
45. What is the approximate breakdown current 48. The breakdown voltage of Zener diode ranges
that burns out the diode, if it has a breakdown from ________ to ________.
voltage of 150 V and maximum power (a) 2 V to 800 V (b) 4 V to 900 V
dissipation of 0.5 W (c) 6 V to 1000 V (d) 0.8 V to 800 V
(a) 3.33 MA (b) 3.33 mA TNPSC AE-2013
(c) 3.33 nA (d) 3.33 A Ans. (a) : The zener voltage refers to reverse
TNPSC AE-2014 breakdown voltage between 1.2 V to 200 V can go upto
P 1000 V or 1kV while maximum for surface mounted
Ans. (b) : Breakdown current (I) =
V device (SMD) is about 47 V.
0.5 • Maximum current rating at rated zener voltage
= = 3.33 mA 200µA − 200A
150
• Zener diode are used for voltage regulation, as
46. A given silicon avalanche photodiode has a reference elements, surge suppressors, and in
quantum efficiency of 65% at a wavelength of switching applications and clipper circuit.
900 nm. Suppose 0.5 µW of optical power 49. A photo-diode is used in reverse-biased because
produces a multiplied photocurrent of 10 µA. (a) majority swept are reverse across the junction
What is the multiplication M? (b) only one side illuminated
(a) 33 (b) 38 (c) reverse current is small as compared to photo
(c) 43 (d) 48 current
TNPSC AE-2014 (d) reverse current is large as compared to photo
Ans. (c) : Given, current
Quantum efficiency (η) = 65% TNPSC AE-2013
wavelength (λ) = 900 nm Ans. (d) : A photo diode is used in reverse biased
optical power (P0) =0.5 µW because reverse current is large as compare to photo
photo current I = 10 µA current. Reverse biasing of photo diode also known as
ηeλ photo conductive mode.
Responsivity (R) = 50. P – N junction diode is not used for
hc
(a) Rectification
Where h = plank's constant = 6.62 ×10–34Js
(b) Maximum power transfer
c = 3 ×108 m/s
(c) Cliper circuit
e = 1.6 ×10–19 coulomb
(d) Clamper circuit
So,
MPPSC Forest Service Exam.-2014
0.65 × 1.6 × 10 −19 × 900 ×10 −9 Ans. (b) : Maximum power transfer is applicable for
R=
6.62 × 10 −34 × 3 × 108 linear and bilateral circuit, diode is a non-linear and
R = 0.47129 unidirectional. Hence it is not used for maximum power
Q I P = P0 R = 0.5 × 10−6 × 0.47129 transfer.
= 0.2356 ×10–6 51. The light emitting diode
(a) Has a very short life span
I (b) Is made of silicon
So, multiplication (M) =
IP (c) depends on the recombination of holes and
10 × 10−6 electrons
(M) = (d) Uses a reverse biased junction
0.2356 × 10 −6 MPPSC Forest Service Exam.-2014
M = 42.44 UPRVUNL AE– 11.06.2014
M ≅ 43 Ans. (c) : The light emitting diode is a semiconductor
47. The potential barrier existing across a P-N light source that emits high when current flow through
junction it. Hence the light emitting diode depends on the
(a) Prevents flow of minority carriers recombination of holes and electrons.
(b) Prevents neutralization of acceptor and 52. The electrons can tunnel through a P–N
donor ions junction mainly because
(c) Prevents total recombination of holes and (a) Barrier potential in very low
electrons (b) Depletion layer is extremely thin
(d) Facilitates recombination of holes and (c) Impurity level is low
electrons (d) They have high energy
Mizoram PSC IOLM -2018, Paper I MPPSC Forest Service Exam.-2014
Ans. (b) : When the depletion layer is extremely thin, 57. The depletion region of a semiconductor diode
then electrons can easily pass through it. Hence it is is due to
conduction mode of any diode known as forward (a) reverse biasing
conduction mode. (b) forward biasing
Depletion layer width → In the range of nanometer or (c) crystal doping
10–9m. (d) migration of mobile charge carriers
53. A diode in which the change in reverse bias Nagaland PSC CTSE (Diploma)-2017, Paper-I
voltage varies the capacitance is called as TNPSC AE-2008
(a) Varactor diode (b) Switching diode Ans. (d) : The recombination of free and mobile
(c) Tunnel diode (d) Zener-diode electrons and holes produces the narrow region at the
RPSC LECTURE-10.01.2016 junction called depletion layer. It is so named because
Ans. (a) : A P-N junction diode which acts as variable this region is devoid of free and mobile charge carriers
voltage capacitor under the reverse applied voltage is like electrons and holes.
called varactor diode. 58. The ratio of reverse resistance and forward
resistance of a germanium crystal diode is
about………..
(a) 1 : 1 (b) 100 : 1
54. A schottky diode clamp is used along with a
(c) 1000 : 1 (d) 40,000 : 1
BJT for
(a) Reducing the power dissipation
(b) Reducing the switching time Ans. (d) : The forward resistance of a germanium
(c) Increasing the value of B crystal diode is in the order of ohms whereas the order
(d) Reducing the base current of reverse resistance is in several thousand ohms.
Nagaland PSC CTSE (Degree)-2016, Paper-II • The ratio of reverse to forward resistance is for
germanium crystal diode is output 40000:1
Ans. (b) : A schottky diode clamp is used along with a
BJT for reducing the switching time. • The ratio of reverse to forward resistance is 1,00,000
In a semiconductor metal junction diode also known as : 1 for silicon diodes.
hot carrier diode. • This implies reverse resistance of Si is more than that
of Ge and that is leakage current is low in Si.
55. The diffusion potential across P-N junction
(a) Decreases with increasing doping 59. For heavily doped diode
concentration (a) Zener breakdown is likely to take place
(b) Increases with decreasing band gap (b) Avalanche breakdown is likely to take place
(c) Does not depend on doping concentrations (c) Either (a) or (b) will take place
(d) Increases with increase in doping (d) Neither (a) nor (b) will take place
concentration Nagaland PSC CTSE (Degree)-2017, Paper-I
Nagaland PSC CTSE (Degree) -2015, Paper I Ans. (a) : Avalanche breakdown occurs in lightly doped
Ans. (d) : We know that diffusion or junction potential diodes at a reverse voltage more than 6 Volt. Zener
is given as. breakdown occurs in heavily doped diodes at a reverse
voltage 2V → 6V.
KT  N A N D 
VT = ln 2  60. The capacitance of a reverse-biased PN
q  ni  junction
Or VT ∝ doping concentration. (a) Increases as the reverse bias is decreased
(b) Increases as the reverse bias is increased
In a P-N junction, if the doping concentration increases,
(c) Depends mainly on the reverse saturation
the recombination of electrons and holes increases,
current
thereby increases the voltage across the barriers.
(d) None of these
56. A region of negative differential resistance is Nagaland PSC CTSE (Diploma)-2018, Paper-I
observed in the current voltage characteristics
Ans. (a) : Transition capacitance (CT) or space-charge
of a silicon PN junction if capacitance when a P-N junction is reverse-biased, the
(a) Both the P-region and the N-region are
depletion region acts like an insulator or as a dielectric
heavily doped
material essential for making a capacitor.
(b) The N-region is heavily doped compared to
K
the P-region CT =
(c) The P-region is heavily doped compared to ( VK + VR )n
the N-region where,
(d) An intrinsic silicon region is inserted between VR = applied reverse voltage
the P-region and the N-region VK = knee voltage
Nagaland PSC CTSE (Diploma)-2017, Paper-I 61. The depletion region in an open circuited p-n
Ans. (a) : A negative differential resistance region is junction contains
observe if both the P and N regions are heavily doped. (a) Electrons
One such example is the tunnel diode. (b) Holes
(c) Uncovered immobile impurity ions 65. Practically, in order to create an electron-hole
(d) Neutralized under reverse bias pair in a P-N junction diode, the energy of the
Nagaland PSC CTSE (Diploma)-2018, Paper-I incident photon should be
Ans. (c) : The space charge region on either side of the (a) Less than the band gap
junction together is known as the depletion region as the (b) Equal to the band gap
electrons and holes taking part in the initial movement (c) Greater than the band gap
across the junction deplected the region of its free charges. (d) None of the above
62. A silicon p-n junction has a reverse saturation Mizoram PSC IOLM-2010, Paper-II
current of 1.8 × 10–9 A, the value of VT = 26 Ans. (c) : In order to create an electron hole pair in a p-
mV. The current in the junction when the n junction diode, the energy of the incident photon
forward bias is 0.6V will be should be greater than the band gap for recombination
(a) 0.148 mA (b) 0.159 mA energy of electron and hole must to greater than the
(c) 0.184 mA (d) 0.215 mA energy in band gap.
Nagaland PSC CTSE (Diploma)-2018, Paper-I 66. Avalanche breakdown in a semiconductor
Ans. (c) : Forward current diode occurs when
(a) the potential barrier is reduced to zero
 Vd 
If = I0  e ηVT − 1 (b) forward current exceeds a certain value
  (c) forward bias exceeds a certain value
 
(d) reverse bias exceeds a certain value
VT = 26 mV
RPCS Lect.-2011
I0 = 1.8 × 10–9 , Vd = 0.6 , η = 2 ( Si )
Ans. (d) : Avalanche breakdown in a diode occurs
 0.6×103  when we apply high reverse voltage across the diode
I = 1.8 × 10  e 2×26 − 1 = 0.184 mA.
–9 which is higher than the zener break down voltage.
  It is used in rectifier.
 
67. In a forward biased photo diode with increase
63. Two P-N junction diodes are connected back to
in incident light intensity the diode current
back to make a transistor. Which one of the (a) Increases
following is correct? (b) Remains constant
(a) The current gain of such a transistor is high
(c) Decreases
(b) The current gain of such a transistor is
(d) Remaining constant, the voltage across the
moderate
diode increases
(c) It cannot be used as a transistor due to large
base width
(d) It can be used only for PNP transistor Ans. (c) : In a forward biased photodiode with increase
Mizoram PSC Jr. Grade -2018, Paper-I in incident light intensity, the diode current decrease
from equation
Ans. (c) : BJT–
• In consist of either two n-type and one p-type layers  ηVVd 
of material called npn transistor or two p-type and n- I = I th e T − 1 − Iop
 
type material called pnp transitor.
• A transistor represented by two diode connected when Iop ↑, I ↓
back to back can not work as transistor as there is no 68. The photo-electric effect occurs only when the
bonding between base and collector. incident light has more than a certain critical
64. A photocell is illuminated by a small bright (a) Intensity (b) Speed
source placed 1m away. When the same source (c) Frequency (d) Wavelength
of light is placed 2m away. The electrons Nagaland PSC CTSE (Degree)- 2016, Paper-I
emitted by the photocathode Ans. (c) : The photoelectric effect of any material
(a) Each carry one quarter of their previous depends on frequency. When the incident light has more
energy
frequency than a certain critical frequency, then photo
(b) Each carry one quarter of their previous
moments electric effect occurs.
(c) as half as numerous 69. The applications of photomultiplier are seen in
(d) are one quarter as numerous (a) night vision equipment, medical equipment
Mizoram PSC Jr. Grade -2018, Paper-I (b) mechanical counters, timers
(c) translational, optical instruments
I (d) ultrasonic transducer, infrared imaging
Ans. (d) : Illumination E = 2
d IES-2019
I = illumination intensity Ans. (a) : photomultiplier are used in
d = distance 1. Medical equipment design
hence, when distance becomes two times, illumination 2. Flying – spot scanner
becomes one-fourth, i.e. electrons emitted by photo 3. Gamma Camera
cathode are one-quarters as numerous. 4. Night Vision equipment
70. Consider the following statements regarding V'
the formation of P-N junctions: Protective Resistance (R) =
I
1. Holes diffuse across the junction from P-
side to N-side. V'
=
2. The depletion layer is wiped out. 12 × 10−3
3. There is continuous flow of current across Apply VDR–
the junction. 10 × R
4. A barrier potential is set up across the V’ =
20 + R
junction.
Which of the above statements are correct? 10R
=
(a) 1 and 3 (b) 2 and 3 20 + R
(c) 1 and 4 (d) 2 and 4
R (12 ×10−3 ) =
10R
IES-2018 20 + R
Ans. (c) : Diffusion is the process of movement of 10 × R
charge carrier due to concentration gradient along the R=
PN Junction diode. ( )
12 × 10−3 ( 20 + R )
N-side has excess of electrons and hence electrons (12 × 10-3) (20+ R) = 10
diffuse from n-side to p-side. Similarly, holes diffuse 0.24 + 12R × 10-3 = 10
from p-side to n-side. 12R × 10-3 = 10 –0.24
Barrier potential is the potential drop which is formed R(12 × 10-3) = 9.76
as a result of diffusion of ions and then formation of 9.76
depletion layer. This potential across the P-N Junction. R=
Hence statement 1, 4 are true. 12 × 10−3
71. In tunnel diode, the Fermi level lies R = 813 Ω
(a) inside valance band of p-type and inside 73. Consider the following statements :
conduction band of n-type semiconductors The main contribution to photo conduction is
(b) in the energy band gap but closer to valence by
band of p-type semiconductors 1. the generation of electron and hole pair by
(c) in the energy band gap but closer to valence a photon
band of p-type and below conduction band of 2. a donor electron jumping into the conduction
n-type semiconductors. band because of a photon's energy
(d) in the energy band gap but above valence 3. a valence electron jumping into an
band of p-type and below conduction band of acceptor state because of a photon's energy
n-type semiconductors. Which of the above statements is/are correct?
IES-2018 (a) 1 only (b) 2 only
Ans. (a) (c) 3 only (d) 1, 2 and 3
IES-2017
Ans. (a) : In photoconduction electron & hole pair
generated by photon.
According to question statement (II) & (III) related to
donor & acceptor ions.
Tunnel diode is a highly doped semiconductor diode So, option (I) is correct.
the fermi level lies inside the conduction band on n-side
and inside the valance band on p-side, because of this 74. In a photoconductive cell the resistance, of the
heavy doping. semiconductor material varies with intensity of
incident light.
72. A low resistance LDR of 20W, operated at a (a) directly (b) inversely
certain intensity of light, is to be protected (c) exponentially (d) logarithmically
through a series resistance in such a way that IES-2017
up to 12 mA of current is to flow at a supply
Ans. (b) : Photoconductive cells are based on the
voltage of 10 V. What is the nearest value of the
protective resistance ? principle that the resistance of certain semiconductor
materials decreases when they are exposed to radiation.
(a) 873 Ω (b) 813 Ω
The resistance of the semiconductor material varies
(c) 273 Ω (d) 81 Ω inversely with the incident light.
IES-2017
75. Which of the following materials is used in
Ans. (b) : light-emitting diodes?
(a) Gallium arsenide sulphate
(b) Gallium arsenide phosphide
(c) Gallium chromate phosphide
(d) Gallium phosphide sulphate
IES-2017, 2014
Ans. (b) : The material used most often in LEDs is (a) 1 only (b) 2 only
gallium arsenide phosphide, though there are many (c) 3 only (d) 1 and 3 only
variation on the basic compound, such as aluminum IES-2016
gallium arsenide or aluminum gallium indium phosphide. Ans. (b) : Varactor diode is a Varicap diode which also
76. In a semiconductor diode, cut-in voltage is the called voltage variable capacitance.
voltage:
(a) upto which the current is zero
(b) upto which the current is very small
(c) at which the current is 10% of the maximum Varactor diode used in a reverse bias i.e. reverse bias
rated current diode behaves like as a capacitor.
(d) At which depletion layer is formed When a diode is reverse bias, the width of depletion
IES-2016 layer increase with the reverse voltage.
Ans. (b) : The cut-in voltage of semiconductor diode is εA
the voltage up to which the current through the diode is C= 0
very small d
Where–
C→ Capacitance
1
A→ area C∝
V
In above graph diode Current is very small up to cut – ε0→ Absolute permittivity
in voltage.
77. Necessary condition for photo-electric emission
is:
(a) hν ≥ eφ (b) hν ≥ mc
1 d→ Distance between two plates
(c) hν ≥ eφ2 (d) hν ≥ mc
2 V→ Reverse voltage
IES-2016 80. Swept-out voltage in PIN diode happens when
Ans. (a) : In a photoelectric emission, the minimum PIN diode is
condition required for emission of electrons from the (a) Forward biased and the thickness of the
outermost shell of an atom is the frequency of incident depletion layer decreases till I-region
rays should be very high to provide energy to the becomes free of mobile carriers
electron so that it can leave from their outermost shell. (b) Reverse biased and the thickness of the
(hν ≥ eφ ) . depletion layer increases till I-region becomes
78. Maximum energy of electrons liberated photo free of mobile carriers
electrically is: (c) Forward biased and the thickness of the
(a) Proportional to light intensity and depletion layer increases till I-region becomes
independent of frequency of the light free of mobile carriers
(b) Independent of light intensity and varies (d) reverse biased and the thickness of the
linearly with frequency of the light depletion layer decreases till I-region
(c) Proportional to both, light intensity and becomes free of mobile carriers
frequency of the light IES-2015
(d) Independent of light intensity and inversely Ans. (b) : Swept - out voltage-
proportional to frequency of the light When the PIN diode is reverse biased the reverse
IES-2016 voltage will keep on increasing the width of depletion
Ans. (b) : K.E. max = hν − W0 region at N-I junction because reverse biasing increases
the width of depletion region.
Where – The value of reverse voltage at which the whole
W0→ Materials property of cathode. Which is known as
intrinsic layer is swept of charge carriers is called
work function.
swept-out voltage. This value is-2V.
W0 = hf0
Where :- 81. A tunnel-diode is best suited for
f0→ threshold frequency of the metal. (a) Very low frequencies
So we can say that– (b) 50 Hz
Kinetic energy independent of light intensity and kinetic (c) 100 kHz
energy E = hf0 varies linearly with frequency of the (d) Microwave frequencies
light. IES-2015
79. The varactor diode has a voltage-dependent: Ans. (d) : Tunnel diode is also known as Esaki
1. Resistance 2. Capacitance microwave diode.
3. Inductance It is used in many microwave application where it can
Which of the above is/are correct? be used in oscillator and amplifier.

82. Small recovery time of a diode is most Ans. (c) : The diffusion potential in pn-Junction
significant for
(a) Line-frequency rectification K.T  N A N D 
V= ln  
(b) Switching operations q  ( n )2 
 i 
(c) High-frequency rectification and switching
operations Where
K→ Boltzmann constant (1.38×10-23 J/K)
(d) Low-frequency rectification and switching
T → temperature (in Kelvin)
operations q→ Electron charge (1.6× 10-19 C)
IES-2015 NA→ Concentration of acceptor atom
Ans. (c) : Fast recovery diode is a semiconductor device ND→ Concentration of donor atom.
which possesses small/short reverse recovery time for ni→ Intrinsic semiconductor.
rectification purpose at high frequency. • If doping concentration Increases
A quick recovery time is crucial for rectification of
K.T  N A N D ↑ 
high-frequency A.C. signal diode are mostly used in ↑V= ln  
rectifiers because they possess ultra- high switching q  ( n )2 
 i 
speed.
• If temperature is Increases
83. The basic structure of avalanche photodiode is
(a) p+ - i - p - n+ (b) p+-i- n+ KT ↑  N A N D 
+ –
(c) p - p - n +
(d) i -p–- n+ ↑V= ln  
q  ( n )2 
IES-2015  i 
Ans. (a) : The Basic structure of APD is:- E0 = E1 + E2
N  N 
E0 = KT ln  D  + KT ln  A 
In given structure:- n
 i   ni 
P+→ Highly doped p-type semiconductor. Built in potential in p-n junction is equal to the
i→ Intrinsic semiconductor without doping difference in the fermi level of the two sides, expressed
P→ P- type semiconductor. in volts.
n+→ Highly doped n-type semiconductor. 86. Consider the following statements regarding
84. In a pn junction diode, dV/dT is equal to optocouplers:
(a) 2.3 mV/ºC (b) 3.5 mV/ºC 1. Optocouplers are LEDs driving
photodiodes in a single package to provide
(c) 10.0 mV/ºC (d) 12.5 mV/ºC
electrical isolation between input and
IES-2015 output
Ans. (a) : In a P-N- Junction diode (at Room temp. 2. Optocoupler is LED driving a
300oK) phototransistor in a single package that
dV replaces pulse transformers working at
For Germanium -: = −2.1mV / o C input zero crossing
dT
dV 3. Optocouplers are used as temporary non
For silicon -: = −2.3mV / o C fixed joints between optical fibre
dT terminations.
dV Which of the above statements are correct?
is the derivative of the voltage with respect to
dT (a) 1, 2 and 3 (b) 1 and 2 only
temperature. (c) 1 and 3 only (d) 2 and 3 only
In other word -: IES-2015
The voltage across diode (Si & Ge) decreases by (–2.1 Ans. (a) : Optocoupler (also called opto-isolator photo
mV & –2.3mV) per oC rise in temperature respectively. coupler and optical isolator)
85. The built-in potential (diffusion potential) in a
p-n junction
1. is equal to the difference in the Fermi-level
of the two sides, expressed in volts.
2. increases with the increase in the doping
levels of the two sides.
• Optocoupler is a electronic component which
3. increases with the increase in temperature.
transfers electrical signal between two isolated
4. is equal to the average of the Fermi-levels
circuit by using light
of the two sides.
• Optocoupler are consist of an LED and photo
transistor in a single package.
(a) 1 and 2 only (b) 1 and 3 only
(c) 1, 2 and 3 (d) 2, 3 and 4 • Optocoupler is the coupling device used to as
IES-2015 temporary non fixed joint between optical fiber
UPRVUNL AE– 11.06.2014 terminations.
87. The maximum depletion layer width in silicon Ans. (d) :In case of photoelectric emission, high speed
is electron that are often emitted from a filament strike a
(a) 0.143 µm (b) 0.857 µm copper target to emit photoelectric, thus in photoelectric
(c) 1 µm (d) 1.143 µm emission of electron does not take place it is known as
IES-2014 critical wavelength.
Ans. (b) : The maximum depletion layer width in 92. The I-V characteristics of a tunnel diode
silicon is → 0.857 µm. exhibit
88. A Zener diode has the following properties: (a) current-controlled negative resistance
1. It is properly doped crystal diode with (b) voltage-controlled negative resistance
sharp breakdown (c) temperature -controlled positive resistance
2. It is reverse biased (d) current-controlled positive resistance
3. Its forward characteristics are just that of IES-2013
ordinary diode DRDO -2008
4. Its reverse characteristics are like ordinary Ans. (b) : The maximum current that a tunnel diode
diode reaches is IP and voltage applied is VP.
(a) 1, 2, 3 and 4 (b) 1, 2 and 4 only the current value decreases, when more amount of
(c) 1, 2 and 3 only (d) 3 and 4 only voltage is applied.
IES-2014
Ans. (c) : Zener diode-
Zener diode is a special type p-n junction diode which is
specially design in breakdown region.
• It is a heavily doped and its work in reverse bias.
• Zener diode work as a normal diode when it is a
forward bias.
• It is mainly used in a voltage regulation.
93. With the increase of reverse bias in a p-n diode,
the reverse current
(a) decreases
(b) increases
(c) remains constant
(d) may increase or decrease depending upon
doping
RPSC Vice Principal ITI-2016
89. A tunnel diode is a p-n junction in which ISRO Scientist Engg.-2016
(a) n-region is degenerately doped IES-2013
(b) p-region is degenerately doped Ans. (c) : In a reverse bias, Current flow due to
(c) either n or p-region is degenerately doped minority charge carrier.
(d) both n and p-regions are degenerately doped Minority charge carries is highly sensitive to
IES-2013 temperature. So this is temperature dependent current
Ans. (d) : A Tunnel diode is a P-N junction diode not a voltage dependent.
which the electric current decreases as the voltage So reverse saturation current is remain constant.
increase because it is heavily doped p-n junction. 94. The efficiency of an LED for generating light is
90. Which is the diode used for measuring light directly proportional to the
intensity? (a) applied voltage (b) current injected
(a) Junction diode (b) Varactor diode (c) temperature (d) level of doping
(c) Tunnel diode (d) Photodiode IES-2012
IES-2013 Ans. (b) : For generating light the efficiency of LED is
Ans. (d) : Photodiode are often used for accurate directly proportional to the current injected. By radiate
measurement of light intensity in science and industry recombination rate also LED efficiency will be determined.
they generally have more linear response than 95. The relative values of the forward conduction
photoconductor. voltage for a p-n junction diode, a Red LED
91. The wavelength beyond which photoelectric and a Schottky barrier diode are
emission cannot take place is called (a) Schottky voltage drop > p-n junction diode
(a) long wavelength drop > Red LED drop.
(b) optical wavelength (b) Red LED drop > p-n junction diode drop >
(c) photoelectric wavelength Schottky voltage drop.
(d) critical wavelength (c) p-n junction diode drop > Schottky voltage
IES-2013 drop > Red LED drop.
(d) Schottky voltage drop > Red LED drop > p-n Now P2 = 5mW/ºC ×40ºC
junction diode drop. P2 = 200mW.
IES-2012 We know that-
Ans. (b) P = V. I
• The forward conduction voltage for P-N junction P
I=
diode is (0.3 to 0.7) V V
• The forward conduction voltage for schottky Barrier P1 − P2
diode is (0.15 to 0.45) V =
• The forward conduction voltage for light emitting V
diode is 700 − 200 500
= =
for Red → (1.6Vto2V)  0.7 0.7
for Violet → (2.8V to 4V)  I = 714mA
 
for Green → (1.9V to 4V)  98. Match List-I with List-II and select the correct
  answer using the codes given below the list:
for Blue → (2.5Vto3.7V)  List-I List-II
for Yellow → (2.1V to 2.2V)  A. LED 1. Electrical isolator
  B. LCD 2. Forward biased
for orange → (2V to 2.1V)  C. Optocouplers 3. Light reflectors/
so voltage drop- transmitters
Red LED > P-N Junction diode > Schottky barrier D. Photodiode 4. Reverse biased
diode. Codes:
96. A potential barrier of 0.50 V exists across a p-n A B C D
junction. If the depletion region is 5.0 × 10–7m (a) 4 1 3 2
wide, what is the intensity of the electric field in (b) 2 1 3 4
this region ? (c) 4 3 1 2
(a) 1.0 × 106 V/m (b) 2.5 × 10–7 V/m (d) 2 3 1 4
7
(c) 2.5 × 10 V/m (d) 2.5 × 108 V/m IES-2011
IES-2012 Ans. (d) : LED (Light emitting diode)-
Ans. (a) : Given, this diode emit light when connection is in forward bias
Potential barrier voltage (V) = 0.5V • LCD (Liquid crystal display)-LCD panels use
width of depletion layer (d) = 5×10–7m reflective technology (light reflector)
Potential barrier voltage • Optocoupler - optocouplers, also called opto-
Electric field (E) =
Width of depletion layer isolated, are semiconductor devices that isolated
unwanted signal by optically couple circuit.
0.5
= V/m • Photo diode- this device that convert light into an
5 × 10−7 electrical signal when connection is reverse bias.
5 99. LED is a
= V/m
5 × 10−6 (a) p-n diode (b) Thermistor
E = 1 ×10 V/m6 (c) Gate (d) Transistor
97. A 700 mW maximum power dissipation diode GPSC Asstt. Prof.-11.04.2017
at 25ºC has 5 mW/ºC de-rating factor. If the IES-2011
forward voltage drop remains constant at 0.7 Ans. (a) : A-light emitting diode is a semiconductor
V, the maximum forward current at 65ºC is light source that emits light when current flows through
(a) 700 mA (b) 714 mA it.
(c) 1 A (d) 1 mA 100. Consider the following statements:
IES-2011 1. The radiation falling on a photodiode is
Ans. (b) : De-rating factor- primarily a minority carrier injector.
In electronics de-rating is the operation of a device at 2. The short-circuit current of a reverse biased
less than its rated maximum capability in order to photodiode under illumination varies
prolong its life. exponentially with light intensity.
3. The photo voltage emf of an open-circuited
given-
photodiode varies logarithmically with the
 dP  light generated short-circuit current.
De-rating factor   5mW /º C
 dT  4. The spectral response of a photodiode does
Power (P1) = 700mW not depend upon the frequency of the
dP incident light.
Power (P2) = × dT Which of these statements are correct?
dT (a) 1, 2, 3 and 4 (b) 3 and 4 only
dT = (T2–T1) ºC (c) 1 and 2 only (d) 1 and 3 only
= (65–25)ºC = 40ºC IES-2011
Ans. (d) : Photo diode is a P-N junction diode that 103. The minimum energy of a photon required for
consumes light energy to produce electric current. intrinsic excitation is equal to
• It works in a reverse bias mode. When light strikes in (a) energy of bottom of conduction band
a diode, the charge carriers will be generated, e − from (b) energy of top of valence band
(c) forbidden gap energy
P-side jumps to N-side while holes from N-side travels
(d) Fermi energy
to P-side.
IES-2009
• Short circuit current In photo diode- It is generated
by a photo diode into a short circuit when diode is Ans. (c) : From Relation-
illuminated. E pn ≥ E G
Short circuit current depends strongly on the intensity Photon energy much greater or equal then the bandgap
and spectral distribution of the light. are efficiently absorbed photon for intrinsic excitation
• Open circuit voltage of photo diode- should be at least equal to Eg, therefore the number of
Voc is the voltage generated by a photo diode across a minority carrier in an illuminated solar cell can be
very large load resistor when the diode is illuminated. approximated by the number of light generated.
Voc is desirable to have the voltage drop (VL) across the 104. The 'voltage stability with time' of reference
resistor proportional to the light level. diodes incorporating Zener diodes is
101. Consider the following statements: comparable to that of which of the following.
1. The efficiency of a light emitting diode (a) Dry cells
(LED) decreases with the injected current. (b) Nickel-cadmium cells
2. The efficiency of a LED increases with a (c) Lead-acid accumulator batteries
decrease in temperature. (d) Conventional standard cells
3. The light emitted is concentrated near the IES-2009
junction because most of the carriers are Ans. (d) : The 'voltage stability with time' of reference
with in a diffusion length of the junction. diodes incorporating Zener diodes is comparable to, that
4. Light is emitted in LED when electrons of Conventional standard cells.
move from the valence band to the 105. What current does
conduction band.  DP Dn  2
Which of these statements are correct? I = Aq  +  n i , represent in p-n
(a) 1, 2 3 and 4 (b) 1 and 2 only  L P N D Ln N A 
(c) 3 and 4 only (d) 2 and 3 only junction diode? (Where the symbols have their
IES-2011 usual meaning)
Ans. (d) : (a) Forward current
• When injected carrier concentration increase then (b) Diffusion current
injected current will increase, so recombination (c) Drift current
increase. (d) Reverse saturation current
i.e. light emitting due to recombination increase IES-2009
so, Ans. (d) : The saturation current is more accurately
known as reverse saturation current or leakage current.
ηLED ∝ I F The Reverse bias saturation current for an Ideal p-n
• When operation temperature increase from 327K to
 DP DN  2
380K efficiency of LED decreases 20%. diode, is given by- Is = Aq  +  .n i
the temperature rising, the radiation at the potential will  LP N D L N N A 
decreases, so as to decreases the luminous efficiency. Where,
A→ Cross-sectional Area.
q→ Electron charge (1.6×10-19C).
DP →Diffusion Constants for holes.
Dn → Diffusion Constants for electrons.
LP → Diffusion length for Holes.
Ln → Diffusion length for electrons.
when electrons move from conduction to valance band
ND → Donor concentration.
then it release energy in form of light.
NA → Acceptor Concentration.
102. Which one of the following is not LED ni → Intrinsic concentration.
material? 106. The doping concentration on the n-side of a p-n
(a) GaAs (b) GaP junction diode is enhanced. Which one of the
(c) SiC (d) SiO2 following will get affected?
IES-2009 (a) Width of the depletion region on n-side
Ans. (d) : Generally, optical device are fabricated using (b) Width of the depletion region on p-side
direct bandgap semiconductor like as GaAs and Normal (c) Width of the depletion region on both side
P-N junction diode is made by using silicon. (d) No change in width of depletion regions
so SiO2 is not LED fabrication materials. IES-2008
Ans. (a) : Depletion region is depends upon doping. If 109. Consider the following statements pertaining to
doping is more, then depletion width decrease and if tunnel diodes:
doping is less then depletion width is increases. 1. Impurity concentration is high
1 2. Carrier velocities are low.
Depletion width ∝ 3. They have current-controlled V-I
doping characteristic.
Hence Depletion width region on N-side gets affected Which of the statements given above is/are
as doping concentration on N-side of P-N junction correct?
enhanced. (a) 1 only (b) 2 and 3 only
107. In step-graded p-n junction diode, what is the (c) 1 and 3 only (d) 1 and 2 only
ratio of the depletion-region penetration depths IES-2008
into p and n regions (if the ratio of acceptor to Ans. (a) :
donor impurity atom densities is 1 : 2)? • A tunnel diode is a heavily doped p-n junction diode
(a) 2 : 1 (b) 4 : 1 i.e. heavily doped means impurity concentration is
(c) 1 : 2 (d) 1 : 4 high. due to tunneling effect; the quantum mechanical
IES-2008 phenomenon some time exhibited by moving carriers
Ans. (a) : As we know that velocity is fast that succeed in passing from one side
Depletion width and doping concentration are on a potential barrier to the other although of
inversely proportional to each other. insufficient energy to pass over the top.
1 • tunnel diode has voltage controlled V–I characteristics.
Depletion width ∝ 110. Consider the following statements for a photo
Doping concentration
conducting material :
1 1. Its dark conductivity is small.
W∝
D 2. With the absorption of radiation, equal
W1 D 2 numbers of electrons and holes are
= produced.
W2 D1
Which of the statements given above is/are
more precisely for P-N Junction- correct?
WP D n (a) 1 only (b) 2 only
=
Wn D P (c) Both 1 and 2 (d) Neither 1 nor 2
IES-2008
 DP 1 
given − =  Ans. (c) :
 Dn 2  • When light is absorbed by a material such as a
semiconductor, the number of free electrons and
WP 2
= holes increases, resulting in increased electrical
Wn 1 conductivity.
108. Consider the following statements for a p-n • Dark conductivity of photo conducting material is
junction diode: very small.
1. It is an active component. 111. Match List-I (Diode) with (List-II)
2. Depletion layer width decreases with (Application) and select the correct answer
forward biasing. using the codes given below the lists:
3. In the reverse biasing case, saturation List-I List-II
current increases with increasing A. Gunn diode 1. Mixers
temperature. B. Zener diode 2. Microwave
Which of the statements given above are oscillators
correct? C. Varactor diode 3. Frequency
(a) 1, 2 and 3 (b) 1 and 2 only modulation
(c) 2 and 3 only (d) 1 and 3 only D. Schottky diode 4. Voltage
IES-2008 comparison
Ans. (c) : Codes:
• In P-N junction diode, the width of the depletion A B C D
region decrease in forward bias this is due to the (a) 2 4 3 1
electrons being attracted by the positive terminal of (b) 3 1 2 4
the battery and hence the negative ions disappear, (c) 2 1 3 4
thus forward bias narrows the Depletion region, due (d) 3 4 2 1
to the carriers from the battery terminals. IES-2008
• Saturation current depends on minority carrier Ans. (a) :
concentration & minority carrier concentration is • Gunn diode is based on "Gunn effect" It have
Highly sensitive to temperature so this current is Negative Resistance, used in high frequency
also called temperature dependent current. (Microwave oscillation).

• Zener diode are widely used as a voltage reference 10 = e ∆VD / 2× 26mV
an as shunt regulator or voltage comparison to 10 = e ∆VD / 52mV
regulate the voltage across small circuit. taking loge both side-
Zener diode conducts when voltage reaches the
diode's reverse breakdown voltage.  ∆VD 
log e 10 = log e e 52mV 
• Varacter diode is a varicap diode which also called  
as voltage variable capacitance. it is used in FM
∆VD
signal in analog communication. log e 10 = log e e
• A Schottky diode is one of the popular options 52mV
among non-linear device for mixer. mixer produced ∆VD = 52 × log e 10 mV
the original frequency as well as their sum and their ∆VD = 52 × 2.302
difference.
∆VD = 119.704
112. Assuming an operating temperature T = 300 K
and corresponding VT = 25 mV, what is the ∆VD 120mV
change in semiconductor silicon diode forward 113. The depletion layer in a p-n junction is made of
voltage VD to produce a 10 : 1 change in diode which of the following?
current ID, while operating in the forward bias (a) Ionized donors in p-side and ionized
region (< 25 mA)? acceptors in n-side
(a) 60 mV (b) 120 mV (b) Ionized acceptors in p-side and ionized
(c) 180 mV (d) 240 mV donors in n-side
IES-2008 (c) Accumulated holes in p-side and accumulated
Ans. (b) : Current and voltage Relationship of diode electrons in n-side
qVD (d) Accumulated electrons in p-side and
I D = I0 (e ηkT − 1) accumulated holes in n-side.
Where, Mizoram PSC Jr. Grade -2018,Paper-I
ID → diode current IES-2007
I0 → Reverse saturation current Ans. (b) : The schematically figure of P-N junction
diode under unbiased condition.
VD → Voltage across diode
k → Boltzmann's constant (1.38×10–23J/k)
η→ Recombination factor
η = 2 for Si 
 
η= 1 for Ge  the region have uncovered positive and negative ions or
T → Temperature (in kelvin) uncompensated ions is called depletion region due to
→ As we know that- the depletion of carrier in this region.
kT It has positive ions (Donor ions) on N-side and
VT = Negative ions (Acceptor ions) on P-side.
q
114. Match List-I (Diode) with List-II (Common
VT → thermal voltage
Application) and select the correct answer
VT → 26 mV (at 300ºk) using the codes given below the lists:
→ Now Current of diode will be (for Si)- List-I List-II
( )
I D = I0 e VD / 2VT − 1 A. Tunnel diode 1. Reading of film sound
track
e VD / 2VT >> 1 B. PIN diode 2. High frequency oscillator
so, 1 can be Neglected. C. Zener diode 3. Very high frequency
→ Now ID becomes- switching circuits
qVD
D. Photo diode 4. Reference voltage
I D = I0 (e − 1)
nkt
Codes :
given In question- A B C D
I D1 10 (a) 4 3 2 1
= (b) 2 1 4 3
I D2 1 (c) 4 1 2 3
I D1 I0 e
=
( ) VD1 / 2VT (d) 2 3 4 1
IES-2007
V / 2V
I D2 I0 (e D2 T ) Ans. (d) :
 VD1 − VD2  • Tunnel diode helps in generating a very high
 
 2V


 frequency signal of nearly 10GHz, so it is used in
10 = e T
high frequeny oscillator.

10 = e ∆VD / 2VT • PIN diode are used in the RF and also for High
10 = e ∆VD / 2× 26mV frequency switching circuit.
• The zener diode is widely used as a voltage • If we increase temperature, reverse saturation
reference, where its reverse breakdown. current will be increase and the reverse resistance
Characteristic provided a stable voltage across the and will be decrease with increase temperature.
diode over for a range of currents flowing through it. • Reverse saturation current in Si (nA) and Reverse
• For sound reproduction we used a photo diode, a saturation current in Ge (µA)
beam of light is passed through an amplifier, to a I0 (Si ) < I0 (G e )
loud speaker.
• Cut-in voltage of Si is 0.7V
115. Consider the following statements used in
Cut - in voltage of Ge is 0.3V
respect of the phenomenon- Population
Inversion: 118. Consider a Ge diode operating at 27ºC and just
1. It means population in a higher state is beyond the threshold voltage of Ge.
higher than that in a lower state What is the value of dV/dT?
2. It is observed under thermal equilibrium (a) – 1.9 mV/ºC (b) – 2.0 mV/ºC
3. It increases the rate of spontaneous (c) – 2.1 mV/ºC (d) – 2.3 mV/ºC
emission IES-2006
4. It increases the rate of stimulated emission Ans. (c) : If the temperature is increased at fixed
Which of the statements given above are voltage, saturation current is increase. If current is
correct? constant with temperature variation, It is found at Room
(a) 1, 2, 3 and 4 (b) 2 and 3 only temperature voltage should be decrease as
(c) 1 and 3 only (d) 1 and 4 only dV
= −2.1mV /º C for Ge-Material.
IES-2007 dT
Ans. (d) : Population Inversion- In this, the population 119. Match List-I (Device) with List-II (Application)
of atoms in upper Energy level (Excited state) E2 is and select the correct answer using the codes
greater than that of lower energy level (Ground state) E1 given below the list:
i.e. E2> E1 this condition in called population inversion. List-I List-II
General Population Inversion A. Hall element 1. Power control
(E1 > E2) (E1 < E2) B. Varactor diode 2. Microwave mixer
• Stimulated emission takes place only when the gain C. SCR 3. Tuning element
medium is pumped strongly enough and population in tank circuit
inversion is created. D. Schottky barrier 4. Sensor
i.e. population Inversion increase the rate of stimulated diode
emission. Codes:
116. Which one of the following is an example of A B C D
electroluminescent devices? (a) 2 3 1 4
(a) Liquid crystal display and photodiode (b) 4 1 3 2
(b) Liquid crystal display and photo transistor (c) 2 1 3 4
(c) Electroluminescent panel
(d) 4 3 1 2
(d) Light emitting diode and photo transistor
IES-2007 IES-2006
Ans. (c) : Electroluminescence- Ans. (d) :
It is a process by which photons are generated when the • Hall element are used in sensor to time the speed of
excess electron-hole pair are created by an electric wheels and shafts.
current caused by an externally applied bias. • Varactor diode or varicap diodes are used mainly in
e.g.- Electroluminescent panel. radio frequency to provide voltage controlled
117. Which one of the following statements is not variable capacitor tunning in tank circuit.
correct? • SCR are mainly used in device where the control of
(a) Reverse saturation current in a BJT high power application.
approximately doubles for every 10ºC rise in • Schottky barrier diode is widely used in different
temperature application like a microwave mixer.
(b) The reverse resistance of a junction diode 120. When a positive d.c. voltage is applied to the n-
increases with increase in temperature side relative to p-side, a diode is said to be
(c) Reverse saturation current of a silicon diode is given a
much smaller than that of a germanium diode. (a) forward bias (b) reverse bias
(d) The Cut-in voltage of silicon diode is larger
(c) zero bias (d) neutral bias
than that of germanium
IES-2007 IES-2006
Ans. (b) : Reverse saturation current is more sensitive Ans. (b) :
to temperature.
For every 1ºC rise temperature reverse saturation
current is increased by 7% for both Si & Ge.
In other word we can say every 10ºC rise temperature
reverse saturation current will be double.

1.24
Ans. (c) C-A-B : Photon energy Eg (eV) =
λ (µm)
∴ photon energy is inversely proportional to
A diode connected in reverse bias is one in which the wavelength.
positive voltage of a d.c. voltage source is connected to
the cathode of the diode and the Negative or ground of
the voltage source is connected to the anode.
Note-In Reverse bias connection diode behaves like as
open circuited.
Sequence of Eg (300K) →
121. Photons of energy 1.53 × 10–19 Joule are
GaAs > Si > Ge
incident on a photodiode which has a
responsivity of 0.65 A/W. If the optical power Sequence of λ →
level is 10µW, what is the photocurrent GaAs < Si < Ge
generated? given-
(a) 64 µA (b) 1.5 µA A → GaAs
(c) 2.1 µA (d) 6.5 µA B → Si
IES-2006 C → Ge
Responsivity (R) = 0.65 A/W
Incident optical power (P0) = 10µW
I
Responsivity, R = Ph
P0
IPh = R ×P0
= 0.65 A/W ×10µW So, According to graph →
IPh = 6.5µA λC > λB > λA
Hence correct sequence of Ge, GaAs, and Si in order of
122. Which one of the following is the correct ABC
relationship between the band gap of a C-A-B
material used in a photo detector and the 124. A tunnel diode is
energy of the incident photon? (a) High resistivity p-n junction diode
(The symbols have usual meanings) (b) A slow switching device
(a) E g ≥ hc / λ (b) hν 2 / λ ≥ E g (c) An amplifying device
(c) hν ≥ E g (d) 1/ 2 hν ≤ E g (d) A very heavily doped p-n junction diode
IES-2006 KVS TGT (WE)- 2014
Ans. (c) : Energy of incident photon is equal or slightly IES-2005
greater than of forbidden energy gap (Eg) to cross the Ans. (d) : A tunnel diode or Esaki diode is a type of
gap semiconductor diode that has effectively "Negative
hc Resistance" due to the quantum mechanical effect is
≥ E g or hν > E g
λ called tunneling.
123. Tunnel diode have a very heavily doped P-N junction.
correct in respect of the use of Direct Gap (DG)
and Indirect Gap (IG) semiconductors in
fabrication of Light Emitting diode?
(a) Both DG and IG semiconductors are suitable
(b) Only DG semiconductor is suitable
(c) DG semiconductor is suitable and some IG
Photovoltaic devices may be made from various materials having proper dopants are also used
semiconductors as optical materials for which (d) Only IG semiconductors are suitable
the transmission coefficient (Tr) is shown in the IES-2005
figure given above as a function of photon Ans. (b) : Direct band gap-
wavelength. During recombination most of the energy is released in
Which one of the following is the correct the form of light.
sequence of A, B and C pertaining to Ge, GaAs Ex - GaAs
and Si, respectively? Indirect band gap-
(a) A – B – C (b) B – A – C During recombination most of the energy is released in
(c) C – A – B (d) C – B – A the form of heat.
IES-2006 Ex- Si, Ge.
LED is the example of Direct band gap because most of 128. Which one of the following statements is
the free electron will be directly falling from conduction correct?
band to valance band & energy is directly released by Under small signal operation of a diode,
falling electrons in the form of light. (a) its bulk resistance increases
126. Consider the following statements in relation to (b) its junction resistance predominates
a semiconductor laser diode. (c) it acts like a closed switch
1. The material should be a direct gap (d) it behaves as a clipper
semiconductor IES-2005
2. Some form of wavelength selective Ans. (b) : When diode connection is in forward bias
structure or resonator must be present. and we applied very small signal across diode, it acts
3. Light output increases linearly with bias like as a closed switch in this case, its junction
current. resistance predominates.
4. Light output increases significantly when For +Ve Half cycle it acts as closed switch and for –ve
bias current exceeds a threshold value. Half cycle it acts as open switch.
Which of the statements given above are 129. Match List-I (Diode) with List-II (Application)
correct? and select the correct answer using the codes
(a) 1, 2 and 4 (b) 1 and 3 given below the lists:
(c) 2 and 4 (d) 2 and 3 List-I List-II
IES-2005 A. Varactor diode 1. To charge auxiliary
Ans. (a) : storage batteries
• Laser diode is made of two doped gallium arsenide B. Tunnel diode 2. Reference voltage
(GaAs). Its example of direct band gap so electron C. Photodiode 3. High frequency
can directly emit a photon. tuning circuits
so we can say that laser diode, direct band gap D. Zener diode 4. High frequency
semiconductor material is used. switching circuit
Codes:
• The output light of laser diode varies as a function A B C D
of the current passing through the diode, when (a) 2 1 4 3
biased below a threshold current (Ith), the output (b) 3 1 4 2
light is low, But as Current increases over the (c) 3 4 1 2
threshold (Ith), the output light power increase. (d) 2 4 1 3
• Laser diode vary widely used in their wavelength IES-2004
selective structure.
Ans. (c)
They share two fundamental components with all other
• Varactor diode is a varicap diode which also called
lasers.-
as voltage variable capacitor used for high
an optical amplifier and a resonator that Contains and
frequency tuning circuit.
recalculate light through the amplifying element.
• Tunnel diode a heavily doped p-n- junction diode
127. The junction capacitance of a p-n junction which have negative resistance characteristics and
depends on used in high frequency switching circuit.
(a) Doping concentration only • It is most widely used in high frequency switching
(b) Applied voltage only application.
(c) Both doping concentration and applied
• When light falling in photodiode then it gives some
voltage
output voltage. Hence it can be used to charge
(d) Barrier potential only auxiliary batteries.
IES-2005
• Zener diode used in voltage regulation, so it acts like
Ans. (c) : The junction capacitance is directly a reference voltage when it work reverse bias.
proportional to the diffused area and Inversely
proportional to the width, of the depletion region. 130. Which one of the following statements is
In addition, higher resistivity substrates have lower correct? A tunnel diode is always biased
(a) by a d.c. source
junction capacitance, further more the capacitance is
(b) in the middle of its negative resistance region
dependent on the reverse bias as follows: (c) in the positive resistance region nearest to zero
εsi q  N A N D  1 (d) in the reverse direction
CJ =  . IES-2004
2  NA + ND  V0 Ans. (b) :
Where-
εsi → Permittivity of semiconductor material
CJ → Junction capacitance
ND, NA → Doping concentration.
V0 → applied voltage.
∴ The junction capacitance of a p-n junction diode
depends on both the doping concentration and
applied voltage.
the negative resistance region helps in the operation of 133. Which of the following statements are true for
tunnel diode. a semiconductor that is used as a
so tunnel diode is always biased in the middle of its photoconductor?
negative resistance region. 1. It should have no doping
131. In which one of the following, two optical 2. It should have large response time
polarisers, one in front and other in back are 3. It should have an energy band gap value
needed? that matches with frequency of light that is
(a) LED (b) LCD used to excite the photoconductor
(c) LDR (d) LSI Select the correct answer using the codes given
IES-2004 below:
(a) 1, 2 and 3 (b) 1 and 2
Ans. (b) : Polarizer's are used in many optical technique (c) 2 and 3 (d) 1 and 3
instruments and polarizing filter find application in IES-2004
photography and LCD technology. Ans. (a)
• In LCD technology two optical polarizers one in front • The response time of photoconductor- Photo
and other in back are needed. conductor response time as measured from photo
132. The diffusion capacitance of a p-n junction current decay ranged from a few tens of nano-
diode seconds to a few minutes so generally response time
(a) Increases exponentially with forward bias is large.
voltage • When energy of photon is equal or greater than the
(b) Decreases exponentially with forward bias band gap of material, that matched with intensity of
voltage light is absorbed by the material and excited an
(c) Decreases linearly with forward bias voltage electron into the conduction band.
(d) Increases linearly with forward bias voltage • Photo conductor have less doping or No doping.
IES-2004 134. The reverse current of a silicon diode is
Ans. (a) : Diffusion capacitance due to Holes- (a) Highly bias voltage sensitivity
τ I (b) Highly temperature sensitivity
CDP = P P (c) Decreases linearly with forward bias voltage
ηVT (d) Independent of bias voltage and temperature
Where, IES-2003
IP → Hole current Ans. (b) : Reverse saturation current depends on
τP → Carrier life time of Hole minority carrier concentration and minority carrier
Diffusion capacitance due to electrons- concentration is highly sensitive to temperature
dependent current, so this current is temperature
τ I dependent current.
CDn = n n
ηVT 135. A combination of two diodes connected in
where, parallel when compared to a single diode can
In → electron current withstand
τn → carrier life time of electron. (a) Twice the value of peak inverse voltage
(b) Twice the value of maximum forward current
total diffusion capacitance→
(c) A larger leakage current
CD = CDP + CDN (d) Twice the value of cut-in voltage
τ I τ I Nagaland PSC CTSE (Degree)-2017, Paper-I
CD = P P + n n
ηVT ηVT IES-2003
Ans. (b) :
τP I P + τn I n
CD =
ηVT
Iτ
CD =
ηVT
Where,
I → total current (electron + Hole) When the two diode are connected in parallel, the
τ → carrier life time (electron + Hole) current carrying capacity of diode increase if load
(
CD = I0 e v / ηVT − 1 ) current is greater than the diode current rating of one
V / ηVT
diode then more than one diode can be connected in
CD ∝ e parallel to increase the forward current rating.
If forward bias→Thus, diffusion capacitance of p-n Hence the maximum current that a combination can be
junction diode increases exponentially with applied with stand also double.
forward voltage. • Cut-in voltage will be same in this case.

136. In switching diode fabrication, dopant is Ans. (b) : The Depletion region has only positive ions
introduced into silicon which introduces and negative ions forms due to the diffusion of carrier
additional trap levels in the material thereby across the junction of the p-n diode.
reducing the mean life time of carriers. This 140. When a junction diode is used in switching
dopant is applications , the forward recovery time is
(a) Aluminium (b) Platinum (a) of the order of the reverse recovery time
(c) Gold (d) Copper (b) negligible in comparison to the reverse
IES-2003 recovery time
Ans. (c) : (c) greater than the reverse recovery time
• Gold is used for minority carrier life time control they (d) equal to the mean carrier life time τ for the
are used in some infrared detection application. excess minority carriers.
• Reverse Recovery of bipolar devices is more IES-2003
dependent on the low-level lifetime and its reduction
Ans. (b) : Forward recovery time is based on diffusion
is better performed by gold . capacitance and reverse recovery time is based on
so gold is preferred to dopant into silicon diode which transition capacitance,
introduced additional trap levels in the material. trr = Ts + Tt
137. The light emitting diode (LED) emits light of a Where-
particular colour because trr → Reverse recovery time
(a) It is fabricated from a fluorescent material Ts → storage time
(b) transition between energy levels of the carriers Tt → transition time
takes place while crossing the p-n junctionWhere as to get to ON condition from OFF, it take less
(c) Heat generated in the diode is converted into
time called as forward recovery time.
light Reverse recovery time is greater than forward recovery
(d) The bandgap of the semiconductor material time then diode work as a better switch if this reverse
used in the fabrication of the diode is equal to
recovery time is made less.
the energy hν of the light photon 141. The Gunn diode is made of
IES-2003 (a) Silicon (b) Germanium
Ans. (d) : The colour of light emitted in LED is determine (c) Gallium Arsenide (d) Selenium
by the semiconductor materials that forms the diode's PN IES-2003
Junction, It is due to the differences into the energy band gap
Ans. (c) : Gunn diode is made by (GaAs), which is used
structure of semiconductor material and so different number
to build oscillator in the 10GHz to high frequency range.
of photon is emitted varying frequency. 142. Match List-I with List-II and select the correct
138. Depletion capacitance in a diode depends on answer using the codes given below the lists:
1. Applied junction voltage List-I List-II
2. Junction built-in potential A. Zener Diode 1. Negative resistance
3. Current through junction device fabricated using
4. Doping profile across the junction semi-conductors like Si,
Select the correct answer using the codes given GaAs, Ge etc. can be
below: operated at a frequency
(a) 1 and 2 (b) 1 and 3 of 10 GHz.
(c) 1, 2 and 4 (d) 2, 3 and 4 B. Gunn Diode 2. Quantum mechanical
IES-2003 tunneling with very thin
Ans. (c) : In p-n junction diode, there are two types of depletion layers under
capacitance take place- reverse bias operated as
(i) Diffusion capacitance or storage capacitance (in µF) a reference voltage
(ii) Transition or depletion or space charge capacitance source
(in pF) C. Schottky Diode 3. Negative conductance
device, operates on the
A 2qε
Depletion Capacitance- CDep = Na principle of transfer of
2 ( Vbi − Va ) electron from one
where- region of conduction
Vbi → built-in potential band to another
Va → applied bias voltage D. Tunnel Diode 4. Metal-semiconductor
diode, have rectification
Na → Doping profile.
properties
139. The depletion region in a semiconductor p-n Codes:
junction diode has- A B C D
(a) Electrons and holes (a) 2 4 3 1
(b) Positive and negative ions on either side (b) 1 3 4 2
(c) Neither electrons nor ions (c) 2 3 4 1
(d) No holes (d) 1 4 3 2
IES-2003 IES-2002
Ans. (c) : Zener diode- It is in reverse bias region, with In general barrier potential of diode decreases by-
reverse bias widely used as voltage regulation or dV0
voltage reference. = −2.5 mV /º C
dT
Gunn diode- A Gunn diode, also known as a
transferred electron device (TED) is a form of diode a dV0
= 0.0025 V / º C
two terminal semiconductor electronic component with dT
negative resistance used in high-frequency electronics. 145. An one-sided abrupt junction has 1021 per m3
Schottky diode- Schottky diode, also known as of dopants on the lightly doped side, zero bias
schottky barrier diode or hot-carrier, is a semiconductor voltage and a built-in potential of 0.2V. The
diode formed by the junction of a metal semiconductor. depletion width of the abrupt junction (taking
Tunnel diode- tunnel diode or Esaki diode is a type of q = 1.6 × 10–19 C, ∈r = 16 and ∈0 = 8.875 ×
semiconductor diode that has effectively "negative 10–12 F/m) is
resistance" due to quantum mechanical effect called (a) 0.036 nm (b) 0.6 µm
tunneling. (c) 3 µm (d) 1.5 mm
143. Match List-I with List-II and select the correct IES-2002
answer using the codes given below the lists: Ans. (b) : The width of the depletion region d, is given
List-I List-II by- (Va = 0V Q zero bias)
A. Gunn Diode 1. Junction less device
B. Solar Cell 2. Single junction device 2ε r ε 0  N A + N B 
W=   Vbi
C. MOSFET 3. Double junction device q  NA ND 
D. SCR 4. Triple junction device the Depletion region is inversely proportional to the
Codes: doping concentration of the more lightly doped side of a
A B C D p-n junction.
(a) 1 2 3 4
(b) 3 4 1 2 1
W∝ If N A << N D
(c) 1 4 3 2 NA
(d) 3 2 1 4
IES-2002 1
W∝ If N D << N A
Ans. (a) : Gunn diode- NA
2ε r ε 0 V
W=
q.N D
In shown figure differ from the normal diode so as to
indicate the absence of p-n junction of junction less. 2 × 8.875 × 10−12 × 16 × 0.2
W=
Solar cell- Solar cell has a single-junction of p-n 1.6 ×10−19 × 1021
junction connection to conduct the current flow that
56.8 ×10−12
occurs when sunlight hits (falls on) a semiconductor = = 35.5 × 10−14 = 5.97×10–7
material. 1.6 × 102
144. The change in barrier potential of a silicon p-n W = 0.6µm
junction with temperature is
146. Match List-I (Operating point on the I-V
(a) 0.0025 Volts per degree C
characteristic) with List-II (Devices) and select
(b) 0.0250 Volts per degree C the correct answer using the codes given below
(c) 0.0030 Volts per degree C the lists:
(d) 0.0014 Volts per degree C List-I List-II
KVS TGT (WE)-2016 A. 1st quadrant 1. Solar cell
IES-2002 B. 2nd quadrant 2. Photo detector with
Ans. (a) : The barrier potential of p-n junction diode high sensitivity
decreases as the temperature is increases. C. 3rd quadrant 3. Photo detector with low
• For Ge→ sensitivity
dV D. 4th quadrant 4. Rectifier diode
= −2.1mV /º C Codes:
dT A B C D
dV (a) 4 3 2 1
= 0.0021 V /º C (b) 3 4 2 1
dT
(c) 3 4 1 2
• For Si → (d) 4 3 1 2
dV IES-2001
= −2.3mV /º C
dT Ans. (a) : 1St quadrant- Rectifier diode
2nd quadrant - Photo detector with low sensitivity
dV 3rd quadrant - Photo detector with high sensitivity
= 0.0023 V /º C
dT 4th quadrant - Solar cell

147. The AC resistance of a forward-biased p-n 150. A p-n junction diode's dynamic conductance is
junction diode operating at a bias voltage 'V' directly proportional to
and carrying current 'I' is (a) the applied voltage (b) the temperature
(a) zero (c) its current (d) the thermal voltage
(b) a constant value independent of V and I ISRO Scientist Engg.-2016
(c) V/I IES-2000, 1999
(d) ∆V / ∆I Ans. (c) : We know
IES-2001 ∆V
Ans. (d) : Dynamic Resistance ( rd ) =
∆I
∴ Dynamic conductance ( g m )
1
∝
Dynamic resistance (g m )
∆I
Dynamic Conductance ( g m ) ∝
∆V
148. Match List-I (Devices) with List-II (property)
and select the correct answer using the codes so g m ∝ ∆I
given below the lists: 151. In PN junction, the space charge capacitance is
List-I List-II proportional to V–n where V is the applied bias
A. Silicon diode 1. High frequency voltage and 'n' is a constant. The value of 'n'
applications for step, linearly graded and diffused junctions
B. Germanium 2. Very low reverse bias would be respectively.
diode saturation current
C. LED 3. Low forward bias 1 1 1 1 1 1
(a) , , (b) , and
voltage drop 2 3 2.5 3 2 2.5
D. PIN diode 4. Cut-off wavelength 1 1 1 1 1 1
Codes: (c) , and (d) , and
2 2.5 3 3 2.5 2
A B C D IES-1999
(a) 1 3 4 2 Ans. (a) : Given-
(b) 2 4 3 1
(c) 1 4 3 2 C ∝ V−n
(d) 2 3 4 1 Where-
IES-2000 C → space charge carrier capacitance
Ans. (d) : V → applied bias voltage
(A) Silicon diode has very low reverse bias saturation n → constant
current compare to germanium diode.  1
Si → I0 (nA) • for step junction  n = 
 2
Ge → I0 (µA)
(B) Germanium have low forward bias voltage drop  1
• for linearly graded junction  n = 
compare to silicon diode.  3
Si → 0.7V  1 
Ge → 0.3V • for diffusion junction  n = 
(C) Wavelength is used to different coloured, UV and  2.5 
IR LEDs, but not white LEDs, the wavelength of an 152. GaAs has an energy gap of 1.43 eV. The
LED is determined by the semiconductor material used optical cutoff wavelength of GaAs would lie in
within it. the
(D) PIN diodes are used in the RF and also for (a) Visible region of the spectrum
microwave and high frequency switches. (b) Infrared region of the spectrum
149. The depletion layer across a p+-n junction lies (c) Ultraviolet region of the spectrum
(a) mostly in the p+ – region (d) For ultraviolet region of the spectrum
(b) mostly in the n – region IES-1998
(c) equally in both the p+ and n – regions Ans. (b) : Wavelength and energy have an Inverse
(d) entirely in the p+ – regions relationship-
IES-2000 hc
E=
Ans. (b) : P+ → Heavily doped, n → Moderate doping. λ
1 1
Depletion region width ∝ E∝
doping level λ
As P+ is heavily doped so depletion layer is more less Where,
compare to n. E - Energy
so depletion layer is mostly in n-region. h - plank's constant
c - speed of light For ideal diode
λ - wavelength Vth = 0
hc I0 = 0
λ = VR = ∞
E
The ideal diode has with respect to practical diode-
6.62 × 10−34 × 3 ×108
λ= • It has low reverse saturation current (I0)
1.43 ×1.6 × 10−19 • It has low value of forward cut in voltage
λ = 8.68 × 10 −7 • It has large reverse breakdown voltage (VR)
λ = 0.87 µm • Silicon has low temperature sensitivity compared to
spectrum of light- Ge.
155. Germanium and silicon photo sensors have
their maximum spectral response in the
(a) infrared region (b) ultraviolet region
(c) visible region (d) X-ray region
IES-1997
So optical cut off wavelength (0.87µm) will lie in Ans. (c) : Germanium and silicon photo sensors have
infrared region. their maximum spectral response in visible region.
153. For a photo induced current of Iλ the collector 156. The wavelength of light emitted by a GaAs is
current of a photo transistor will be 8670 × 10–10m. given Planck's constant = 6.626
Iλ × 10–34 Joules. Velocity of light = 2.998 × 108
(a) (h fe + 1)Iλ (b)
h fe + 1 ms–1 and 1 eV = 1.602 × 10–19 Joules. The
energy gap in GaAs is
Iλ
(c) h fe .Iλ (d) (a) 0.18 eV (b) 0.7 eV
h fe (c) 1.43 eV (d) 2.39 eV
IES-1998 IES-1996
Ans. (a) : Ans. (c) : Given,
• Induced current due to light → (Iλ) h = 6.626×10–34 joule
collector current of phototransistor will be- c = 2.998×108 m/sec
IC = (1 + h fe ) Iλ λ = 8670×10–10 m
Wavelength and energy have an inverse relationship-
1
E∝
λ
hc
E=
λ
154. Which of the following characteristics of a Where-
silicon P-N junction diode is suitable for use as E → Energy
an ideal diode? h →Plank's constant
1. It has very low saturation current c → Speed of light
2. It has a high value of forward cut-in
voltage λ → Wavelength
3. It can withstand large reverse voltage 6.626 × 10−34 × 3 × 108
4. When compared with germanium diodes, E= J
8670 × 10−10
silicon diodes show a lower degree of
temperature dependance under reverse 19.878 × 10−26
E= J
biased condition. 8670 × 10−10
Select the correct answer using the codes given E = 0.00229×10–16J
below
(a) 1 and 2 (b) 1, 2, 3 and 4
 −19 1 
(c) 2, 3 and 4 (d) 1 and 3 1.6 × 10 J = 1eV 1J = −19
eV 
IES-1998  1.6 × 10 
Ans. (d) : 1
E = 0.00229 × 10−16 × eV
1.6 ×10−19
E = 0.00143×103 eV
E = 1.43eV
157. Match List-I (Device) with List-II (Property
use) and select the correct answer using the
codes given below the lists
List-I List-II 160. Silicon is not suitable for fabrication of light
A. Zener diode 1. High speed switching emitting diodes because it is
B. Tunnel diode 2. Multi vibrator circuit (a) An indirect bandgap semiconductor
C. Gunn diode 3. Voltage stabilizer (b) A direct bandgap semiconductor
D. PIN diode 4. Microwave oscillator (c) A wide bandgap semiconductor
Codes: (d) A narrow bandgap semiconductor
A B C D TNPSC AE-2013
(a) 3 1,2 4 1 IES-1995
(b) 4 2,4 4 1 Ans. (a) : Si is not suitable for fabrication of LED
(c) 4 1,2,3 1 3 because Si is an Indirect band gap semiconductor so
(d) 3 1,2,4 4 1 electron can't fall directly conduction band to valance
IES-1996 band in this type of transition first it come to internal
Ans. (a) : Zener diode - It is used in voltage regulator, trapped state and then goes to valance band. So falling
voltage reference and voltage stabilizer. electron releasing energy in the form of heat along with
Tunnel diode- tunnel diode is used in many light. Hence, Si is not suitable for the fabrication of
microwave application, where it can be used in LEDs.
oscillator and High speed switching. 161. Match List-II characteristics in the set of figure
Gunn diode- It is used mainly microwave frequency with devices in List-I and select the correct
and above their most common used in oscillator. answer using the codes below the lists:
PIN diode- It is used in a broad array of application List-I List-II
from limiters to phase shifters modulators attenuators, A. Silicon 1.
and switching. schottky
158. Gold is often diffused in silicon PN junction barrier
devices to
(a) Increase the recombination rate
(b) Reduce the recombination rate
(c) Make silicon a direct gap semi conductor
(d) Make silicon semimetal.
IES-1996 B. A Tunnel 2.
Ans. (b) : The presence of gold atoms in the silicon diode
lattice decreases the life time of excess electron and
hole in p-n junction material. so reduce the
recombination rate.
159. The current through a PN junction diode with
V volts applied to the P region relative to the N
region (where I0 is the reverse saturation C. A PNPN 3.
current of the diode, m is the ideality factor, K Diode
is the Boltzmann constant, T is the absolute
temperature and q the magnitude of charge on
an electron) is
 qV   − qV 
(a) I0  e mKT − 1 (b) I0  mKT 
  e −1  D. A silicon 4.
 qV   qV  PN
(c) I0  mKT 
(d) I0  mKT  junction
 1 − e   e + 1  abrupt
IES-1995 symmetri
Ans. (a) : The generalized current and voltage relation c (doped
ship of diode- to
 qV  1017/cm3)
I D = I0  e mKT − 1 Codes:
  A B C D
Where, (a) 1 24 3
ID → diode current (b) 4 23 1
I0 → Reverse saturation (c) 2 41 3
V →Voltage across diode (d) 3 41 2
q → charge of electron (1.6×10–19C) IES-1995
K → Voltage constant (1.38×10–23J/k) Ans. (c) : Schottky diode is a semiconductor formed by
m → Ideality factor the junction of a semiconductor with a metal, It has a
T → Temperature (in kelvin) low forward voltage drop and a very fast switching

kT  I L 
ln  + 1 = V
q  I0 
Where-
K → Boltzman constant
T → temperature (in kelvin)
IL → light generated short-circuit
Tunnel diode is a semiconductor diode that has
I0 → Reverse saturation current of solar cell
effectively "Negative Resistance" due to the quantum
q → Charge of electron
mechanical effect called tunneling.
V → applied bias voltage.
163. For a photoconductor with equal electron and
hole mobilities and perfect ohmic contacts at
the ends, an increase in the intensity of optical
illumination results in
(a) a change in open circuit voltage
(b) a change in short circuit current
The PNPN diode (Schockley diode) is a four -layer (c) a reduction of resistance
semiconductor diode with alternating layers of P-type (d) an increase of resistance
and N-type material. IES-1995
Ans. (c) : If intensity of optical illumination increases
the number of electron hole pair generated i.e. electron
hole pair increases so conductivity will increases.
A Si PN junction diode is the just a position of a N-type

and p-type piece of semiconductor
164. Consider the following statements about

conditions that make a metal-semiconductor
contact rectifying:
162. The reverse saturation current of a solar cell 1. N-type semiconductor with its work function
(I0) and the light generated short-circuit φs, greater than the work function φM of the
current is IL for one sun illumination. The open metal.
circuit voltage of the solar cell under one sun 2. N-type semiconductor with its work function
illumination is (K is Boltzman constant, T is the φs, smaller than the work function φM of
absolute Temperature and q is the magnitude the metal.
of the charge of an electron) is 3. P-type semiconductor with its work function
KT  IL  q  I  φs, is greater than work function φM of the
(a) l n 1 +  (b) l n 1 + L  metal.
q  I 0  KT  I0  4. P-type semiconductor with its work function
(c) KT ln (I0 + IL) (d) KT ln (IL – I0) φs, smaller than the work function φM of
IES-1995 the metal.
Ans. (a) : As we know- (a) 1 and 3 are correct (b) 2 and 3 are correct
I L = I0 (e V.q / kT − 1) (c) 1 and 4 are correct (d) 2 and 4 are correct
IES-1995
IL
= e V.q / kT − 1 Ans. (c) : In N-type semiconductor-
I0 • Contact is rectifying when φm < φs
IL • Contact is ohmic, when φm > φs
+ 1 = e V.q / kT for P-type semiconductor-
I0
taking natural log both side- • Contact is rectifying when φm > φs, contact is ohmic
when φm < φs.
I 
ln  L + 1 = l n ( eqV / KT ) 165. A good ohmic contact on P-type semiconductor
I
 0  chip is formed by introducing
(a) gold as an impurity below the contact
I 
ln  L + 1 = qV / kT (b) a high concentration of donors below the
I
 0  contact
(c) a high concentration of acceptors below the 168. V-I characteristics of a Tunnel diode is best
contact represented as
(d) a thin insulator layer between the metal and
semiconductor (a) (b)
IES-1995
Ans. (b) : Common techniques to make ohmic contacts
• Choose metal so that its work function fmetal is close
to that of semiconductor Fsemi (thermal ionic)
• Insert thin layer of narrow bandgap material
between metal and semiconductor
• Increase the doping level near the semiconductor
surface as high as possible (tunneling assisted).
166. If Vr is the reverse voltage across a graded (c) (d)
p-n junction, then the junction capacitance Cj
proportional to
(a) (Vr)2 (b) (Vr)–1/3
–n
(c) (Vr) (d) (Vr)3/2
IES-2010, 1994
Ans. (b) : Relation of junction capacitance and voltage-
C j ∝ V−m
IES-1994
• m = 1/2 for step P-N junction ( C ∝ V −1/ 2 ) Ans. (b) : Tunnel diode is not a normal diode but
• m = 1/3 for a graded p-n junction ( C ∝ V −1/ 3 ) instead exhibits a negative resistance region in the
forward direction.
167. The temperature current characteristics (I-T)
of schottky diode is best represented as
(a)
169. The diffusion capacitance of a p-n junction

(b)
(a) decreases with increasing current and
increasing temperature
(b) decreases, with decreasing current and
(c) increases with increasing current and
(c) (d) does not depend on current and temperature
Ans. (b) : The formula for diffusion capacitance-
τI
CD = D
ηkT
(d) Where,
τ → Carrier life time
ID → diode current
k → Boltzman constant
T → Temperature.
CD ∝ I D
IES-1994
1
Ans. (b) : Schottkey diode is used as fast switching CD ∝
device. T
Temperature current characteristics of schottkey diode Diffusion capacitance decreases, with decrease current
is - and Increase temperature.
170. Dominant mechanism for motion of charge
carriers in forward and reverse biased silicon
p-n junctions are
(a) drift in forward bias, diffusion in reverse bias
(b) diffusion in forward bias, drift in reverse bias

(c) diffusion in both forward and reverse bias Aε0
(d) drift in both forward and reverse bias Capacitance (C) =
ISRO Scientist December, 2017 d
Ans. (b) : Dominant mechanism for motion of charge 1
C∝
carriers, diffusion in forward bias and drift in reverse d
bias. So depletion width increases then depletion capacitance
171. In a uniformly doped abrupt p-n junction, the will decreases.
doping level of the p-side is ten times the so we can say that-
doping level of the n-side. The ratio wp/wn of C j = K / VR
the duplication layer widths in the p-and n- In p-n junction diode depletion capacitance decrease
regions respectively is with increase in reverse bias.
(a) 0.1 (b) 1
(c) 2 (d) 10 175. In PN junction diode, P side is doped with
Mizoram PSC IOLM-2010, Paper-II acceptor concentration of 2 × 1016 cm–3, N side
BSNL (JTO)-2001 is doped donor concentration of 5 × 1017cm–3.
The contact potential of diode is :
Ans. (a) : In a uniformly doped abrupt p-n junction, the (a) 0.82 V (b) 0.2 V
doping level of the p-side is ten times the doping level (c) 1.2 V (d) 0 V
of the n-side then. Assume thermal equivalent voltage equal to 26
In equilibrium condition, the net charge must be zero, mV and intrinsic carrier concentration equal to
Wp N D 1 1.45 × 1010cm–3.
= = = 0.1 MPSC HOD Govt. Poly. -2013
Wn N A 10
Ans. (a) : Given,
172. In a photo-diode, for high speed operation, the
NA = 2×1016 cm–3
depletion region must be:
ND = 5×1017 cm–3
(a) Zero (b) Thin
Carrier concentration (Ni) = 1.45 ×1010 cm–3
(c) Very large (d) Large
KVS TGT (WE)- 2018 kT  N A .N D 
Contact potential of diode = ln  2 
Ans. (b) : In a photo-diode for high speed operation the q  Ni 
depletion region must be thin. The depletion region
contains few free charge carriers and the width of the  
2 × 1016 × 5 × 1017 
depletion region can be manipulated by adding voltage = 26 mV ln 
bias.  (1.45 × 1010 )  2
 
173. Which of the following is NOT an advantage of
a photodiode?  1034 
= 26mV ln  
 (1.45 ) × 10 
(a) It has very good temperature stability. 2 20
(b) Its speed of operation is very high.

(c) It can be used as a variable resistance device.  1014 
(d) It is highly sensitive to light. = 26mV ln  
LMRC AM- 16.07.2021  2.1025 
Ans. (c) : Advantage of photo diode = 0.818 0.82V
• Fastest photo diode 176. The small signal capacitance of an abrupt P+ n
• The photo diode is linear junction is 1 nf/cm2 at zero bias. If the built-in
voltage is 1 volt. the capacitance at a reverse
• It has very good temperature stability.
bias voltage of 99 volts in
• Its speed of operation is very high (a) 10 (b) 0.1
• It is highly sensitive of light. (c) 0.01 (d) 100
174. In a junction diode GATE-1991
(a) the depletion capacitance increases with Ans. (b) : We know-
increase in the reverse bias Relation of capacitance and bias voltage
(b) the depletion capacitance decreases with
increase in the reverse bias C ∝ V −m
(c) the depletion capacitance increases with for abrupt p - n junction (m = 1/2)
increase in the forward bias C ∝ V −1/ 2
(d) the depletion capacitance is much higher than 1
the depletion capacitance when it is forward C∝
biased V
Nagaland PSC CTSE (Degree)-2015, Paper- I C1 V2
Ans. (b) : As we know → =
C2 V1
Increases the reverse bias voltage the depletion width
will increases. Given -
Where, C1 = 1nF/cm2
d → depletion width. V1 = VBR1 + V0

=1+0 178. The built-in potential (diffusion potential) in a
= 1V p-n junction
V2 = VBR 2 + V0 (a) is equal to the difference in the Fermi-level of
the two sides, expressed in volts
= 99 +1 (b) increases with the increase in the doping
= 100V levels of the two sides
1 100 (c) increases with the increase in temperature
= (d) in equal to the average of the Fermi levels of
C2 1
the two sides
1 1 ISRO Scientist Engg-2017, GATE-1993
C2 = =
100 10 Ans. (a & b) : We know-
C 2 = 0.1nF kT  N A N D 
Vbi = ln  2 
177. Referring to the below figure the switch S is in q  ni 
position 1 initially and steady state condition 1
exist from time t=0 to t=t0, the switch is Vbi ∝ 2 and Vbi ∝ N A N D
ni
suddenly thrown into position 2. The current I
through the 10 K resistor as a function of time Where-
t. from t=0 is? (given the sketch showing the Vbi → Built-in potential in volts.
magnitudes of the current at t=0, t=t0 and t = ∞). ND → N-type-donor atoms concentration
NA → P-type-acceptor atoms concentration
kT
→ Thermal voltage
q
T → Temperature in kelvin
GATE-1991 q → Charge in coulombs.
So we can say built-in potential is equal to the
Solution : (A) 0 < to < t 0+ (at switch position 1) difference in fermi level of two side.
Diode are forward bias or short ckt. E 0 = E 1+ E 2
20 = EFN –Efi +Efi –EFP
Current through 10kΩ resistor (I) = E0= EFN –EFP
10kΩ
Where-
I = 2mA EFN → Fermi level of n-side
(B) t = t +0 (at switching position- II) EFP → Fermi level of P-side.
(when diode instantaneously switched from to reverse From equation Vbi we can say that by increasing the
state so diode behave as a short circuit for a little time). doping concentration of P and n side. built-in potential
when switch position (ii) of the diode increases slightly only as it depends
diode will be reverse bias but I logrithmically on doping concentration.
flow from N to p 179. The diffusion potential across a p- n junction
trr = ts + tr (a) decreases with increasing doping
Where→ concentration
(b) increases with decreasing band gap
trr → Reverse recovery time
(c) does not depend on doping concentrations
ts → Storage time (d) increases with increase in doping
Tr → Transition time. concentration
(i) t 0+ < t < t s GATE-1995
Diode reverse bias but act short circuit. Ans. (d) : We know -
−20V kT  N A N D 
I= = −2mA Vbi = ln  2 
V
10kΩ q  (n i ) 
(ii) ts < t < trr current start reducing to I0
Vbi ∝ N A N D
exponentially.
(iii) at t = trr So we can say that increase in doping concentration
then built in potential will be increases.
current I will becomes reverse saturation current
180. A Zener diode works on the principle of
I = −I0 (a) tunneling of charge carriers across the
junction
(b) thermionic emission
(c) diffusion of charge carriers across the
junction
(d) hopping of charge carriers across the junction
GATE-1995
Ans. (a) : A zener diode work on the principle of (a) 0 mA (b) –100 mA
tunneling of charge carriers across the junction. (c) 100 mA (d) 50 mA
• Zener diode is basically like an ordinary P-N junction GATE-1998
diode but normally operated in reverse biased Ans. (b) :
condition. But ordinary P-N junction diode connected
in reverse biased condition is not used as zener diode
practically. A zener diode is a specially designed
highly doped P-N junction diode.
181. the static characteristic of an adequately
forward biased p-n junction is a straight line. If
the plot is of
(a) log I vs. log V (b) log I vs. V
(c) I vs log V (d) I vs V
GATE-1998
Ans. (b) : Current and voltage relationship of diode-
( )
I D = I0 eVd / ηVT − 1
Where,
ID → Diode current Even, if a voltage is applied suddenly (t = 0) in a
I0 → Reverse saturation current forward to reverse direction. the diode does not with
Vd → Voltage across diode stand voltage until it battery into this state. current flow
η → Recombination factor. for a certain time until transforming into this state.
VT → Thermal voltage so at t = 0 sec.
If e Vd / ηVT >> 1 I = −100 mA
then, 183. In the figure, silicon diode is carrying a
I = I0 e Vd / ηVT constant current of 1 mA. When the
temperature of the diode is 20°C, VD is found to
I
= e Vd / ηVT be 700 mV. If the temperature rises to 40°C, VD
I0 becomes approximately equal to
Taking log on both side.
 I 
(
ln   = ln e Vd / ηVT )
 I0 
V
ln(I) − ln (I0 ) = d (a) 740 mV (b) 660 mV
ηVT (c) 680 mV (d) 700 mV
Vd = ηVT ln(I) − ηVT ln (I0 ) GATE- 2002
Compare with straight line equation Ans. (b) : We know-
Y = mx + C for Si diode→
Y = Vd dV
M = ηVT −2mV /º C
dT
x = ln(I)
Current (I) through diode will be constant
C = −ηVT ln (I0 ) ∆T = T2 –T1 = 40ºC –20ºC
= 20ºC
–2×20ºmV = –40 mV
• When temperature 20ºC
VD = 700 mV
• Now 40ºC temperature
≈ VD' = ( VD − 40 ) mV = (700 –40) mV
VD' = 660 mV
184. Choose proper substitutes for X and Y to make
the following statement correct Tunnel diode
and Avalanche photodiode are operated in X
182. A pn-junction in series with a 100 ohms resistor bias and Y bias respectively.
is forwarded biased. So that a current of 100 (a) X: reverse, Y: reverse
mA flows. If the voltage across this (b) X: reverse, Y: forward
combination is instantaneously reversed at t=0 (c) X: forward, Y: reverse
current through diodes is approximately given (d) X: forward, Y: forward
by GATE-2003
0.718
Ans. (c) : Tunnel diode generally operated in forward −3
718
bias when the value of forward voltage is low. Value of I0(Ge) e 26×10 ×2
−1 e 52 − 1
= 0.143
= 143
forward current generated will be high. I0(Si)
Avalanche photodiode generally operated in reverse bias. e − 1 e 26 − 1
26×10−3 ×1
X → Forward bias e − 1 984608.1

13.8
= 5.5 = = 4040.41
Y → Reverse bias e −1 243.69
185. Match items in Group -1 with items in Group-2 ≈ 4 ×103
most suitable. 187. A particular green LED emits light of
Group-1 Group-2 wavelength 5490 Å. The energy bandgap of the
P. LED 1. Heavy doping semiconductor material used there is
Q. Avalanche 2. Coherent radiation (Plank's constant = 6.626×10–34 J-s)
Photodiode (a) 2.26 eV (b) 1.98 eV
R. Tunnel diode 3. Spontaneous emission (c) 1.17 eV (d) 0.74 eV
S. LASER 4. Current gain GATE-2003
(a) P-1; Q-2; R-4; S-3 (b) P-2; Q-3; R-1; Si-4 Ans. (a) : Given-
(c) P-3; Q-4; R-1; S-2 (d) P-2; Q-1; R-4; S-3 o
GATE-2003 λ = 5490 A
Ans. (c) : LED works on the principle spontaneous We know→
emission. In the avalanche photodiode due to avalanche  12400  o
Eg =   eV for λ in A
effect there is a large current gain. Tunnel diode has very  λ 
doped. LASER diode are used for coherent radiation.
 12400 
186. At 300 K, for a diode current of 1 mA, a certain Eg =   eV
germanium diode requires a forward bias of  5490 
0.1435 V, whereas a certain silicon diode E g = 2.26 eV
requires a forward bias of 0.718 V. Under the
conditions stated above, the closest 188. Consider an abrupt p-junction. Let Vbi be the
approximation of the ratio of reverse built-in potential of this junction and VR be the
saturation current in germanium diode to that applied reverse bias. If the junction
in silicon diode is capacitance (Cj) is 1 pF for Vbi+VR = 1V, then
(a) 1 (b) 5 for Vbi+VR= 4V, Cj will be
(c) 4×103 (d) 8×103 (a) 4 pF (b) 2 pF
GATE-2003 (c) 0.25 pF (d) 0.5 pF
GATE-2004
Ans. (c): Relation between current and voltage of
diode- Ans. (d) : Relation between junction capacitance and
voltage →
I D = I0 (eVd / ηVT − 1)
CT ∝ V–m
Where-
1
ID → Diode current for abrupt p-n junction m =
I0 → Reverse saturation current 2
Vd → Voltage across diode C J ∝ V −1/ 2
η → Recombination factor We know that,
VT → Thermal voltage  eε 0 N A N D 
1/ 2
Recombination factor (η) = η = 1 for Ge Cj =  

η = 2 for Si  2 ( Vbi + VR ) (N A + N D ) 
Vd1 / ηVT
I = I0 (si) e − 1 ..........(i) 1
  thus C j ∝
V / ηV
I = I0 (Ge) e d2 T − 1 ..........(ii)
( Vbi + VR )
  Now,
Equation (i) – (ii)
C j2 ( Vbi + VR )1
V / ηV
( )
I0 (si) e d1 T − 1 = I0( Ge ) e Vd 2 / ηVT − 1
  =
C j1 ( Vbi + VR )2
I0(Ge)
=
(e Vd1 / ηVT
−1 ) Given that,
I0(si) (e Vd 2 / ηVT
− 1) C j1 = 1pF, (Vbi + VR )1 = 1V
Given- Vd1 = 0.718 ( Vbi + VR )2 = 4V, C j2 = ?

Vd2 = 0.143 C j2 1
= ⇒ C j2 = 0.5pF
VT = 26 mV 1 4

189. A Silicon PN junction at a temperature of 20°C Ans. (c) : Tunnel diode have I-V characteristic exhibits
has a reverse saturation current of 10 pico- a negative resistance region in the forward bias.
Amperes (pA). The reverse saturation current
at 40°C for the same bias is approximately
(a) 30 pA (b) 40 pA
(c) 50 pA (d) 60 pA
GATE-2005
Ans. (b) : We know-
Reverse saturation current value Range → VP < –Ve (R) < VV
becomes double for 10ºC rise in temperature VP ≤ VD < VV
I0(20ºC) (10pA )  +10ºC
→ 2 × 10pA
192. Find the correct match between Group 1 and
= 20pA Group 2
I0(30ºC) ( 20pA )  +10ºC
→ 2 × 20pA Group 1 Group 2
E. Varactor diode 1. Voltage reference
= 40pA F. PIN diode 2. High-frequency
I0(40ºc) = 40pA switch
G. Zener diode 3. Tuned circuit
190. A Silicon PN junction diode under reverse bias H. Schottky diode 4. Current
has depletion region width 10 µm. The relative controlled
permittivity Silicon, εr=11.7 and the attenuator
–12 (a) E-4, F-2, G-1, H-3 (b) E-2, F-4, G-1, H-3
permittivity of free space ε0=8.85×10 F/m.
(c) E-3, F-4, G-1, H-2 (d) E-1, F-3, G-2, H-4
The depletion capacitance of the diode per GATE- 2006
square meter is Ans. (c) : Varactor diode-
(a) 100 µF (b) 10 µF It is used in tunned circuit
(c) 1 µF (d) 20 µF PIN diode-
GATE = 2005 PIN diode are used as current-controlled attenuator
Ans. (b) : We known → Zener diode-
It is used at voltage reference
εεA
C= 0 r Schottky diode-
d It is used at high switching frequency application.
Where- 193. In a p+n junction diode under reverse bias, the
ε0 → Permittivity of free space magnitude of electric field is maximum at
εr → Relative permittivity (a) the edge of the depletion region on the p-side
(b) the edge of the depletion region on the n-side
A → Cross sectional Area
(c) the p+n junction
d → Depletion width (d) the centre of the depletion region on the n-
Given- side.
ε0 → 8.85×10–12 F/m RPSC VP/Suptd ITI- 05.11.2019.
εr → 11.7 GATE- 2007
+
d → 10 µm Ans. (c) : In p n junction under reverse bias the
−12 magnitude of electric field is maximum at the p+n
8.85 × 10 × 11.7 × A
C= junction.
10 × 10−6
C
= 10.35 × 10−6
A
C
= 10.35µF / m 2
A
capacitance per square meter 10µF
191. The values of voltage (VD) across a tunnel- 194. Group I list four types of p-n junction diodes.
diode corresponding to peak and valley Match each device in Group I with one of the
currents are Vp and Vv respectively. The range options in Group II to indicate the bias
condition of that device in its normal mode of
of tunnel- diode voltage VD for which the slope operation.
of its I-VD characteristic is negative would be Group I Group II
(a) VD < 0 (b) 0 ≤ VD ≤ Vp P. Zener Diode 1. Forward bias
(c) Vp ≤ VD < VV (d) VD ≥ VV Q. Solar cell 2. Reverse bias
R. LASER diode
GATE-2006 S. Avalanche Photodiode
(a) P-1,Q-2,R-1,S-2 (b) P-2, Q-1,R-1,S-2 Vr1 → 1.2V
(c) P-2,Q-2,R-2,S-1 (d) P-2,Q-1,R-2,S-2
GATE-2007 Vr2 → 7.2 V
Ans. (b) W2 7.2 + 0.8
Device Bias Condition =
(1) Zener diode → Reverse bias 2 1.2 + 0.8
(2) Solar cell → Forward bias W2 8
(3) LASER diode → Forward bias =
2 2
(4) Avalanche → Reverse bias
photo diode W 2
=2
195. Group I lists four different semiconductor 2
devices. Match each device in Group I with its W2 = 4µm
characteristic property in Group II.
Group I Group II 197. Consider the following assertions.
P. BJT 1. Population inversion S1: For zener effect to occur, a very abrupt
Q.MOS capacitor 2. Pinch-off voltage junction is required
R. LASER diode 3. Early effect S2: For quantum tunneling to occur, a very narrow
S. JFFT 4. Flat-band voltage energy barrier is required.
(a) P-2, Q-1, R-4, S-2 (b) P-1, Q-4, R-3, S-2 Which of the following is correct?
(c) P-3, Q-4, R-1, S-2 (d) P-3,Q-2, R-1, S-4 (a) Only S2 is true
UPRVUNL AE– 11.06.2014 (b) S1 and S2 are both true but S2 is not a reason
GATE-2007 for S1
Ans. (c) (c) S1 and S2 are both true and S2 is a reason for
Device Its characterstic S1
(1) BJT → Early effect (d) Both S1 and S2 are false
(2) MOS capacitor → Flat band voltage GATE-2008
(3) LASER diode → Population inversion Ans. (a) : • Zener effect occurs in a reverse biased p-n
(4) JFET → Pinch-off-voltage junction diode when the electric field enable tunneling
196. A p+ n junction has a built-in potential of 0.8 V. of electron from the valance band to the conduction
The depletion layer width at a reverse bias of band of a semiconductor.
1.2 V is 2 µm. For a reverse bias of 7.2 V, the • quantum tunneling occurs with barrier of thickness
depletion layer width will be around 1 to 3 nm and smaller.
(a) 4 µm (b) 4.9 µm 198. Compared to a p-n junction with
(c) 8 µm (d) 12 µm NA=ND=1014/cm3, which one of the following
GATE-2007 statements is TRUE for a p-n junction with NA
Ans. (a) : We know- = ND =1020/cm3?
n
 2 εVJ  (a) Reverse breakdown voltage is lower and
W=  depletion capacitance is lower
 qN D  (b) Reverse breakdown voltage is higher and
where- depletion capacitance is lower
1 (c) Reverse breakdown voltage is lower and
n= (for step graded (abrupt) P-N junction) depletion capacitance is higher
2
(d) Reverse breakdown voltage is higher and
W α ( VJ )
1/ 2
depletion capacitance is higher
where, GATE-2010
VJ → junction potential Ans. (c) : We know-
W → depletion width Aε
junction potential (VJ) = Built-in potential + reverse C=
bias d
VJ = Vbi + VR NA ND
d∝
W ∝ Vbi + VR NA + ND
1
W1 = k Vbi + VR1 ↑C∝
1 1
W2 = k Vbi + VR 2 +
↑ NA ↑ ND
W2 V R2 + Vbi
If we increase doping the depletion capacitance will
= increase.
W1 VR1 + Vbi 1
Given → ↑C∝
Vr ↓
W1 → 2µm
due to increase capacitance, reverse breakdown voltage
Vbi → 0.8V
decreases.
199. A silicon PN junction is forward biased with a Ans. (d) : Built-in potential is given by-
constant current at room temperature. When
N N 
the temperature is increased by 10°C, the Vbi = VT ln  A 2 D 
forward bias voltage across the PN junction  ni 
(a) increases by 60 mV (b) decreases by 60 mV where,
(c) increases by 25 mV (d) decreases by 25 mV Vbi – Built - in potential voltage
Ans. (d) : We know- VT – Thermal voltage
dv NA – Acceptor concentration
= −2.5mV /º C
dt ND – Donor concentration
• for every 1ºC rise in temperature, the farward voltage ni – Intrinsic concentration
decrese by 2.5mV.  1× 1016 × 5 × 1018 
So, If we increase 10ºC rise in temperature forward Vbi = 26 ×10–3 ln  
 (1.5 × 10 ) 
10 2
voltage decrease by 25mV.
200. A zener diode, when used in voltage  5 × 1034 
stabilization circuits, is biased in = 26 ×10–3 ln  20 
(a) reverse bias region below the breakdown  (2.25 × 10 ) 
voltage = 26 ×10–3 ln ( 2.22 × 1014 )
(b) reverse breakdown region
(c) forward bias region = 26 ×10–3 ln ( 2.22 ) + ln(1014 ) 
(d) forward bias constant current mode
Nagaland PSC CTSE (Degree) -2018, Paper I = 26 ×10–3 [ 0.797 + 14ln(10)]
Nagaland PSC CTSE (Degree) -2015, Paper I = 26 ×10–3 [ 0.797 + 14 × 2.3]
Mizoram PSC AE SDO-2012, Paper-I = 26 ×10–3 [32.997]
GATE-2011 = 26 ×10–3 [33]
Ans. (b) : A zener diode, when used in voltage Vbi = 0.858 V
stabilization circuits is based in the reverse breakdown
region. Vbi ≈ 0.86
201. In a forward biased p-n junction, the sequence Depletion width (w) is given by
of events that best describes the mechanism of
2ε  1 1 
current flow is W=  +  Vbi
(a) injection, and subsequent diffusion and q  NA ND 
recombination of minority carriers
(b) injection, and subsequent drift and generation 2 × 1.04 × 10−12  1 1 
= −19  16 +  × 0.86
of minority carriers 1.6 ×10  10 5 × 1018 
(c) extraction, and subsequent diffusion and
generation of minority carriers 1  1 
= 1.3 ×107 × 0.86 × 1 + 5 ×10 2 
(d) extraction, and subsequent drift and 1016  
recombination of minority carriers
TANGEDCO AE-2018 = 1.118 × 10−9 (1 + 0.002 )
GATE-2013
Ans. (a) : In a forward bias P-N junction, the sequence = 1.118 × 1.002 × 10−9
of event describes the mechanism of current flow is first = 1.120 ×10−9 = 0.000033
injection, then subsequent diffusion, and recombination
of minority carriers take place. W = 3.3×10–5 cm
202. The donor and acceptor impurities in an 203. A region of negative differential resistance is
abrupt junction silicon diode are 1×1016 cm–3 observed in the current voltage characteristics
and 5×1018 cm–3, respectively, assume that the of a silicon PN junction if
intrinsic carrier concentration in silicon in (a) both the P-region and the N-region are
kT heavily doped
silicon n i = 1.5 ×1010 cm –3at 300K, = 26mV (b) the N-region is heavily doped compared to
q
the P-region
and the permittivity of silicon
(c) the P-region is heavily doped compared to the
∈si = 1.04 ×10 –12 F/cm. The built-in potential and
N-region
the depletion width of the diode under thermal (d) an intrinsic silicon region is inserted between
equilibrium conditions. respectively. are the P-region and the N-region
(a) 0.7 V and 1–10–4 cm
(b) 0.86 V and 1× 10–4 cm GATE- 2015, Set-II
(c) 0.7 V and 3.3 ×10–5 cm Ans. (a) : A region of negative differential resistance VI
(d) 0.86 V and 3.3 × 10–5 cm characteristic is found in tunnel diode and tunnel diode
GATE-2014, Set-III is having doped both P-region and N-region.

204. The electric field profile in the depletion region Ans. (c) : We know-
of a p-n junction in equilibrium is shown in the
figure. Which one of the following statements is 2ε  1 1 
NOT TRUE? W=  +  ( Vbi + VBR ) ......(i)
q  NA ND 
Where,
NA → Acceptor concentration
ND → Donor concentration
Vbi → Built in potential
VRB → Reverse bias voltage
from above relation we calculate that
1
W∝
(a) The left side of the junction is n-type and the doping
right side is p-type and W ∝ breakdown voltage
(b) Both the n-type and p-type depletion regions 1
are uniformly doped Breakdown voltage ∝
(c) The potential difference across the depletion doping
region is 700 mV So, N D × VBR = constant
(d) If the p-type region a doping concentration of
15 –3
10 cm , then the doping concentration in 206. The I-V characteristics of three types of diodes
the n-type region will be 1016 cm–3 at the room temperature, made of
GATE- 2015, Set-III semiconductors X, Y and Z, are shown in the
Ans. (c) figure. Assume that the diodes are uniformly
doped and identical in all respects except their
material. If Egx , Egy, and Egz are the band gaps
of X, Y and Z, respectively, then
Built-in potential is given as- (a) Egx>Egy>Egz

1 (b) Egx=Egy=Egz
V0 = × E peak × W
2 (c) Egx<Egy<Egz
Where (d) no relationship among these band gaps exists
V0 → Built-in potential GATE-2016, Set-III
W → Depletion width Ans. (c) : We known,
Epeak → Peak Electric field at the junction.
1 N N 
V0 = × 104 × 1.1×10−6 × 102 Vbi = VT ln  A 2D  .....(i)
2  (n i ) 
V0 = 0.55V and
V0 = 550 mV − EG
So option (c) is that Built-in potential or potential n i = A 0 T 3/ 2 e 2kT

difference across the depletion region is 700mV. so n i ∝ e− EG / 2kT ...(ii)
205. Consider avalanche breakdown in a silicon p+ n
junction. The n-region is uniformly doped with from equation (i) & (ii). If Vbi increases the Eg
a donor density ND. Assume that breakdown increases
occurs when the magnitude of the electric field Hence
at any point in the device becomes equal to the N N 
critical field Ecrit'. Assume Ecrit to be E bx = VT ln  A 2D  ....(i)
independent of ND If the built-in voltage of the  (n i ) 
p+n junction is much smaller than the and
breakdown voltage, VBR, the relationship − EG
between VBR and ND is given by n i = A 0 T 3/ 2 e 2kT
(a) VBR × N D = constant
so n i ∝ e − EG / 2kT ....(ii)
(b) N D × VBR = constant From equation (i) & (ii). If Vbi increases the Eg
(c) N D × VBR = constant increases
(d) N D / VBR = constant Hence,
GATE-2016, Set-II Egx < Egy < Egz
207. An n+-n Silicon device is fabricated with
uniform and non-degenerate donor doping
concentrations of ND1=1×1018 cm–3 and
ND2=1×1015 cm–3 corresponding to the n+ and n (c)
regions respectively. At the operatonal
temperature T, assume complete impurity
ionization, kT/q=25 mV, and intrinsic carrier
concentration to be ni=1×1010 cm–3. What is the
magnitude of the built-in potential of this
device?
(a) 0.748 V (b) 0.460 V (d)
(c) 0.288 V (d) 0.173 V
GATE-2017, Set-II
Ans. (d) : Given,
N D = 1×1018 cm −3 GATE- 2017, Set-II
1
Ans. (a) : Charge density within the transistor
N D2 = 1×1015 cm −3
ηi = 1010 cm −3
VT = 25mV
In n+ junction has more electron compare to n junction.
find Hole concentration in n-region using mass action
low→
n.p = (ni)2
= ( N D − N −A ) is linear
dE(x) q +
Electric field with
(n )2 dn ε
p= i
n distance.
10 2
(10 ) So,
1015
N A = P = 105 cm −3
 N .N 
V0 = VT ln  A 2 D 
 (n i ) 
 1018 × 105 
= 25×10–3 ln  20 
 10  209. In a p-n junction diode at equilibrium, which
= 25 × 10–3 × 6.907 one of the following statements is NOT TRUE?
(a) The hole and electron diffusion current
V0 = 0.173V components are in the same direction.
(b) The hole and electron drift current
208. An abrupt pn junction (locate at x=0) is
components are in the same direction.
uniformly doped on both p and n sides. The (c) On an average, holes and electrons drift in
width of the depletion region is W and the opposite direction.
electric field variation in the x-direction is E(x). (d) On an average, electrons drift and diffuse in
Which of the following figures represents the the same direction
electric field profile near the pn junction GATE-2018
Ans. (d) :
(a)
The hole current and electron current (diffusion) when

joining n-type material with p-type material causes
excess electron in the n-type material to diffuse to the
p-type and excess holes from the p-type material to
diffuse to the n-type side.
(b) Hence, an electric field must build up across the
junction in a such a direction that a hole drift current
will tend to flow across the junction from n-side to p-
side in order to counter balance the diffusion current.
Particle type and Flow of Current 211. The quantum efficiency (η) and responsivity
flow direction direction (R) at a wavelength λ (in µm) is a p-i-n photo
(i) electron drift detector are related by
(ii) electron 1.24 × λ η× λ
diffusion (a) R = (b) R =
η 1.24
(iii) Hole drift
λ 1.24
(iv) Hole diffusion (c) R = (d) R =
210. Which one of the following options describes η× 1.24 η× λ
correctly the equilibrium band diagram at GATE-2019
T=300 K of a Silicon pnn+p++ configuration Ans. (b) : Ratio of photon current to the optical power
shown in the figure? is called responsivity (R).
Photon current (I P )
Responsivity (R) =
Optical Power ( Popt )
If rate of electron generation is (re) and rate of photon
incident is (rp), then responsivity will be
I
R= P
Popt
quantum efficiency defined as ratio of electron
generation rate (re) to the incident photon rate (rp).
electron generation rate
η=
Incident photon rate
ηe
Responsivity(R)=
hν
we know
q × 10−6
R = ηλ×
hc
 hc 
Q −6
1.24 
 q × 10 
ηλ
R=
1.24
212. Consider the recombination process via bulk
traps in a forward biased pn homojunction
diode. The maximum recombination rate is
Umax. If the electron and the hole capture cross-
section are equal, which one of the following is
False?
(a) With all other parameters unchanged, Umax
decreases if the intrinsic carrier density is
GATE-2019
reduced.
Ans. (d) : (b) With all other parameters unchanged, Umax
• Fermi-level of N-type- increases if the thermal velocity of the
N  carriers increases.
E C − E fn = kT ln  C  (c) Umax occurs at the edges of the depletion
 ND  region in the device.
In N-side fermi-level in closer to conduction band. (d) Umax depends exponentially on the applied
for N-type material and moves into the conduction band bias.
for high dopping. GATE-2020
• Fermi-level of p-type Ans. (c) : Here is forward-biased p-n junction diode
N  which has the maximum recombination rate is-
E FP − E V = kT ln  A 
 ND  1
U max = ηi Vth σ0 e(
V / 2VT )
.N
Fermi-level is closer to valance band for p-type 2
semiconductor and moves into valance band for high Where,
doping. ηi → intrinsic concentration
for P++ region fermi-level will lie inside the valance band. VTh →Thermal velocity
σ0 → Capture cross-section. 217. The dominant operating process for LASER
V → Applied voltage diode is:
(a) Absorption
VT → Thermal voltage (b) Spontaneous emission
• Now we look that U max ∝ ηi so that option 'C' is (c) Auger recombination
correct. (d) Stimulated emission
Ans. (d) : A LASER is a device that emits a beam of
coherent light through an optical amplification process.
the dominant operating process for LASER diode is
stimulated emission.
218. Match the column I with column II and mark
the correct option:
Column I Column II
P. LED 1. Heavy Doping
Q. Avalanche photodiode 2. Coherent radiation
213. The minority carrier current in a R. Tunnel diode 3. Spontaneous
semiconductor diode is largely a function of emission
(a) Amount of doping S. LASER 4. Current gain
(b) Temperature P Q R S
(c) Forward bias voltage (a) 1 2 4 3
(d) Reverse bias voltage (b) 2 3 1 4
Kerala PSC Lecturer (NCA) 04.07.2017 (c) 3 4 1 2
(d) 2 1 4 3
Ans. (b) : Minority charge carrier is the process taking RPSC VP/Suptd. ITI 05.11.2019
place at the boundary between p-type and n-type
Ans. (c) :
semiconductor of material. The minority carrier in a
LED → Spontaneous emission
semiconductor diode is largely a function of Avalanche photo diode → Current gain
temperature. Tunnel diode → Heavy doping
214. The space-charge region contains charges that LASER → Coherent radiation
are 219. Which of the following cannot be used as mask
(a) Mostly majority carriers in MOS fabrication process?
(b) Mostly minority carriers (a) Silicon dioxide (b) Silicon nitride
(c) Fixed donor and acceptor ions (c) Photoresist (d) Boron
(d) Mobile donor and acceptor ions RPSC VP/Suptd. ITI 05.11.2019
Kerala PSC Lecturer (NCA) 04.07.2017 Ans. (d) : Silicon dioxide, silicon nitride and
Ans. (c) : The space charge region contains charges that photoresist are used as mask in NMOS fabrication
are fixed donor and acceptor ions. There is no process. Whereas boron can't be used as mask in MOS
movement in charge carrier so there is no current flow fabrication process.
through it. 220. Which of the following statement is true for a
215. The number of LED display indicators in logic Schottky barrier diode?
probes are (a) Minority carrier device
(b) Minority carrier storage time is infinite
(a) 1 (b) 4
(c) Diffusion capacitance is associated when the
(c) 1 or 2 (d) 2 device is forward biased
Kerala PSC Lecturer (NCA) 04.07.2017 (d) Majority carrier device
Ans. (d) : A logic probe is a hand held pen like test RPSC VP/Suptd. ITI 05.11.2019
probe used for analysing and troubleshooting and Ans. (d) : Schottky barrier diodes are used for their low
logical states of a digital circuit. The number of LED turn on. Voltage, fast recovery time and low loss energy
display indicator in logic probe are 2. at higher frequencies and majority carrier device.
216. The absorption coefficient of a semiconductor 221. In a p-n junction to make the depletion region
used for optoelectronic device is a very strong extend predominantly into p-region, the
function of concentration of impurities in the p-region
(a) photon energy and band-gap energy must be
(b) temperature of atmosphere (a) Much less than the concentration of
(c) phonon energy and lattice vibration impurities in n-region
(b) Much higher than the concentration of
(d) carrier diffusion length impurities in n-region
RPSC VP/Suptd. ITI 05.11.2019 (c) Equal to the concentration of impurities in n-
Ans. (a) : The absorption coefficient of a region
semiconductor used for optoelectronic device is a very (d) Zero
strong function of photon energy and band gap energy. Punjab PSC Poly. Lect. 20.08.2017
Ans. (a) : We have relation, Ans. (c) : Those elements whose V-I curves are not
x p rD straight lines are called non linear elements because
= their resistances are non linear resistances e.g. Tunnel
x n rA diode, schottky diode, P-n-junction diode.
r 226. The stable reading of the LED display is
xp = D xn (a) 06 (b) 07
rA
(c) 12 (d) 13
For xp > xn → rA < rD Nagaland PSC (Degree) 2018, Paper-II
222. Zener diode break down voltage ______with Ans. (d) : The stable reading of the LED display is 13
temperature 227. In which state, a silicon diode will have voltage
(a) decreases (b) constant drop of 0.7 V across it ?
(c) increases (d) may increase or decrease (a) No bias (b) Forward bias
TSPSC Manager (Engg.) - 2015 (c) Reverse bias (d) Zener Region
TNPSC AE- 2019
Ans. (a) : Zener breakdown voltage decreases as the
temperature increases, creating a negative temperature Ans. (b): Cut in voltage or knee voltage-
It is the minimum forword voltage required so
coefficient.
that the forward current flows through the diode.
223. An LED emitting at 1 µm with a spectral width For Si – 0.7 V
of 50nm is used in a Michelson interferometer. Ge – 0.3V
To obtain a sustained interference, the 228. The photo detector parameter that indicates
maximum optical path difference between the the number of electrons generated for each
two arms of the interferometer is photon absorbed by the photo detector is
(a) 200 µm (b) 20 µm (a) Its responsivity
(c) 1 µm (d) 50 nm (b) Its quantum efficiency
APGENCO AE- 23.04.2017 (c) Its figure of merit
Ans. (b) : Given, W = 50 nm = 50×10–9m (d) none of these
LED wavelength = 1 µm = 10–6 m Nagaland PSC- 2018, Diploma Paper-II
So, number of width- Ans. (b) : Photo detector are characterized by certain
key parameter. Among them are spectral response,
λ 10−6 photo sensitivity, quantum efficiency, dark current,
= = = 20
w 50 × 10−9 forward bias noise, noise equivalent power , terminal
Maximum optical path difference capacitance, frequency band width and cut-off frequency.
= number of width × Wavelength 229. One of the following camera tubes is based on
= 20 × 1µm = 20 µm the photo emissive principle
224. When the optical power incident on a (a) Vidicon (b) Saticon
(c) Newicon (d) Image orthicon
photodiode is 10 µW and the responsivity is 0.8
Nagaland PSC- 2018, Diploma Paper-II
A/W, the photo current generated (in µA) is
Ans. (a) : Vidicon camera tube are devices based on
(a) 6 (b) 4
cathode ray tube used in television cameras to capture
(c) 8 (d) 12 television image prior to the introduction of charge
APGENCO AE- 23.04.2017 coupled device.
Ans. (c) : In a photodiode the responsivity is given in 230. Solid state MASER is an amplifier of type
question = 0.8 A/W (a) Diamagnetic (b) Paramagnetic
I = Photo current generated (c) Ferromagnetic (d) Electromagnetic
P = Optical power incident Nagaland PSC- 2018, Diploma Paper-II
R = Responsivity Ans. (a) : Hydrogen cyanide molecules have been used
I to produced a wave length of 3.34 nm. It is used for
R=
P MASER, which is diamagnetic.
R = 0.8 A/W 231. Zener Effect is due to _______
P = 10 µW (a) Saturation (b) Breakdown
I (c) Depletion (d) Ionization
0.8 = (e) Quantum mechanical tunneling
10 × 10−6 CGPSC SO 14.02.2016
I = 8 µA Ans. (e) : Zener effect is due to quantum mechanical
225. Which of the following does not show non- tunneling. It is a electrical breakdown that occurs in a
linear V-I characteristics? reverse biased PN junction.
(a) Schottky diode 232. Critical angle of a LED is given by:
(b) Tunnel diode (a) QC = cos–1(n2/n1) (b) QC = sin(n2/n1)
(c) Thermistor, at a fixed temperature (c) QC = sin–1(n2/n1) (d) QC = cos(n2/n1)
(d) p-n Junction diode (e) QC = tan(n2/n1)
APGENCO AE- 23.04.2017 CGPSC SO 14.02.2016
Ans. (c) : Critical angle of LED is given by Ans. (a) : In He gas laser, the ratio of mixture of Ne
gases and He gases is 1 : 10 at a total pressure of about
n 
Qc = Sin −1  2  1 torr inside off a small electrical discharge.
 n1  239. In ruby laser, the host crystal is :
n1 = Incident index of media (1) (a) MnO2 (b) CaCO3
n2 = refraction index of media (2) (c) C6H18 (d) Al(OH)3
(e) Al2O3
233. Factor that limit the response time of LED CGPSC SO 14.02.2016
(a) resistance (b) deleption layer
(c) Impurities (d) high current Ans. (e) : In ruby laser the host crystal is sapphire
(e) junction capacitance Al2O3. which is dopped which small amounts of
chromium ions (Cr+3).
CGPSC SO 14.02.2016
240. How does the dynamic resistance of diode vary
Ans. (e) : Junction capacitance limit the response time
with temperature?
of LED. (a) Directly proportional
234. In AC plasma display (b) Inversely proportional
(a) The electrodes are present at a critical angle (c) Independent
(b) No electrodes are present (d) Directly to the square of temperature
(c) The electrodes are placed inside the gas ISRO Scientist Engg.-2016
chamber
dV
(d) The electrodes are placed outside the gas chamber Ans.(a): Q Dynamic resistance = =
(e) Between the dielectric layers dI
CGPSC SO 14.02.2016  ηVV 
Ans. (d) : When AC plasma display then the electrodes Diode current I = I0  e T − 1
 
are placed outside the gas chamber.  
235. Major characteristic of a liquid crystal (Where VT ∝ T )
compounds used in LCD is :
dI   1
V
(a) Circular shared molecules =  I0 .e ηVT ,
(b) Triangular shaped molecules dV  
 ηVT
(c) Rod shaped molecules V
(d) Liquid in nature ηVT
Q e >> 1
(e) Brightness V
CGPSC SO 14.02.2016 ηVT
I = I 0 .e
Ans. (c) : Rod shaped molecules characteristic of a
liquid Crystal compounds used in LCD because the rod dI I
=
shaped molecules of a crystal sandwitched between dV ηVT
ignored substrate with orthogonal orientations cause the dV ηVT
electric field of the light passing through it to rotate by 90º. R dynamic = =
dI I
236. A schottkey diode is a;
Therefore VT ∝ T
(a) minority carrier device
(b) majority carrier device 241. Which of the following is not a laser pumping
(c) fast recovery diode process?
(d) both minority and majority device (a) Optical pumping (b) Electrical pumping
(e) normal diode with pn junction (c) Thermal pumping (d) Chemical pumping
CGPSC SO 14.02.2016 (e) X-ray pumping
Ans. (b) : Schottkey diode is a semiconductor diode CGPSC SO 14.02.2016
which has a low forward voltage drop and a very fast Ans. (c) : Laser pumping is the act of energy transfer
switching action. from an external source into the gain medium of laser.
It is majority carrier device. Thermal pumping is not a laser pumping process.
237. Laser source is highly 242. Which of the following is the gas laser?
(a) Coherent (b) Incoherent (a) Ruby laser (b) CO2 laser
(c) Polychromatic (d) Colored (c) Semiconductor laser (d) Dye laser
(e) Magnetic (e) Ar-ion laser
CGPSC SO 14.02.2016 CGPSC SO 14.02.2016
Ans. (a) : Laser source is highly coherent because the Ans. (b) : CO2 laser is the gas laser. CO2 laser use for
cutting and structuring plastic, Glass pieces, Wood, die
wavelength of the laser light are in phase in space and time.
board.
238. In He-gas laser, the ratio of mixture of Ne gases 243. Measurement of wavelength or energy of
and He gases is : characteristic x-rays enables us _____analysis.
(a) 1 : 10 (b) 10 : 1 (a) qualitative (b) quantitative
(c) 11 : 10 (d) 10 : 10 (c) semi-quantitative (d) semi-qualitative
(e) 20 : 10 (e) Both qualitative and quantitative
CGPSC SO 14.02.2016 CGPSC SO 14.02.2016
Ans. (a) : Measurement of wavelength or energy of 248. Which of the following statement is true?
characteristic X-rays enables is qualitative analysis. (a) Si diodes have higher PIV and narrower
244. OLED works on the principle of : temperature ranges than Ge diodes
(a) Photoluminescence (b) Si diodes have higher PIV and wider
(b) Electroluminescence temperature ranges than Ge diodes
(c) Thermoluminescence (c) Si diodes have lower PIV and narrower
(d) Cathodoluminescence temperature ranges than Ge diodes
(e) Piezoluminescence (d) Si diodes have lower PIV and wider
CGPSC SO 14.02.2016 temperature ranges than Ge diodes
Ans. (b) : OLED stand for organic light emitting diode (e) Si and Ge diodes have equal PIV and
which works an the principle of electroluminescence. temperature range
OLED is fundamentally different from LED. An OLED CGPSC SO 14.02.2016
display works without a backlight because it emits Ans. (b) : Si diodes have higher peak inverse voltage
visible light. and wider temperature ranges than Ge diode.
245. Which is not a type of OLED? At a higher temperature silicon crystal are not easily
(a) Transparent OLED damaged but germanium crystals will be destroyed.
(b) Foldable OLED In Si diode has low reverse current compared to Ge.
(c) Bottom Emitting OLED 249. Peak inverse voltage for a diode is the
(d) White OLED (a) voltage corresponding to rated maximum
(e) Top Emitting OLED voltage
CGPSC SO 14.02.2016 (b) maximum voltage that can be applied across
Ans. (c) : Bottom Emitting OLED is not a type of the diode in the conducting direction
OLED. (c) maximum voltage that can be applied across
There are several type of OLEDs the diode in the non-conducting direction
• Transparent OLED (d) minimum voltage required for current flow in
• Foldable OLED forward direction
• White OLED (e) minimum voltage required for current flow in
• Top Emitting OLED reverse direction
• Active-matrix OLED CGPSC SO 14.02.2016
• Passive matrix OLED Ans. (c) : Peak inverse voltage (PIV) for a diode is the
246. When biasing is applied to zener diode, it? maximum voltage that can be applied across the diode
(a) do not allow the current to flow at all in any in the non conducting direction.
direction. PIV of diode = 2ESM − 0.7
(b) allows the current to flow only when it is
forward biased. 250. For every 10°C temperature increase the
(c) allows the current to flow only when it is reverse saturation current in a p-n junction
reverse biased. diode:
(d) allows the current flow in both directions in (a) Remains same (b) Increases two times
full voltage range. (c) Decreases two times (d) None of the above
(e) allows the current to flow in the forward OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
direction in the same manner as an ideal Ans. (b) : The reverse saturation current of the diode
diode and also permits the current to flow in increases with an increases in temperature. The rise is
the reverse direction when the voltage is 7%/0C for both germanium and Silicon and
above breakdown voltage. approximately double for every 100C rise in
CGPSC SO 14.02.2016 temperature.
Ans. (e) : When forward biasing is applied to zener 251. Photoconductive effects means
diode, it work as an ideal diode, which allows the (a) The decreased conductivity of an illuminated
current to flow in the forward direction and reverse semiconductor junction
biasing also permits the current to flow in the reverse (b) The increased conductivity of an illuminated
direction when the voltage in above breakdown voltage. semiconductor junction
247. What determines the colour of an LED? (c) The conversion of photonic energy to
(a) LED's semiconductor material electromagnetic energy
(b) Voltage applied to bias LED (d) The conversion of electromagnetic energy to
(c) Coloured plastic package of LED photonic energy
(d) Doping density of P and N region Nagaland PSC CTSE (Diploma)-2017, Paper-I
(e) Fabrication method used Ans. (b) : Photoconductive effect, means the increased
CGPSC SO 14.02.2016 conductivity of an illuminated semiconductor junction. The
Ans. (a) : Semicondutor material is used in LED's photoconductive effect is the result of several processes
which is determine the colour of a LED's like gallium whereby photons cause electrons to be ejected from the
arsenide (GaAs) and gallium phosphide (GaP). valence bond and injected into the conduction band.
252. The threshold wavelength for photo-electric 257. As with other two-terminal device, diode can
o be placed in series (or in parallel). Determine
emission from a material is 5200 A . photo-
which one of the following configurations can
electrons will emitted when the material is
illuminated with monochromatic radiation conduct current from A → C.
from a
(a) 50 watt infrared lamp (a)
(b) 1 watt infrared lamp
(c) 50 watt ultraviolet lamp
(d) 100 watt ordinary lamp (b)
Ans. (c) : For photo emission to take place, wave length (c)
of incident light should be less than the threshold
o (d) None of these
wavelength. Wavelength of ultraviolet light (1000 A - RPSC ACF & FRO 23.02.2021
o
4000 A ) while that of infrared radiation > 5200A°) Ans. (a) : In general, a diode is in the 'on' state if the
253. Which one of the following is a trivalent current established by the applied sources is such that
material? its direction matches that of the arrow on the diode
(a) Antimony (b) Phosphorus symbol and VD ≥ 0.7 V for silicon, VD ≥ 0.3 V for
(c) Arsenic (d) Boron germanium. and VD ≥ 1.2 V for gallium arsenide.
Nagaland PSC CTSE (Degree)-2018, Paper-I 258. Under low level injection assumption, the
Ans. (d) : Doping material with three electrons in the injected minority carrier current for an
outermost shell of the shell are known as trivalent extrinsic semiconductor is essentially the
impurities as. Indium, Gallium, Aluminium, Boron. In (a) diffusion current (b) drift current
other hands pentavalent have free electrons in outermost (c) recombination current(d) induced current
shell as- Arsenic, antimony, bismuth. Nagaland PSC CTSE (Degree)-2018, Paper-I
254. A long specimen of p-type semiconductor Ans. (a) : Under low level injection assumption, the
material injected minority carrier current for an extrinsic
(a) Is positive charged semiconductor is essentially the diffusion current.
(b) Is electrically neutral Generally is doping to use is majority carrier
(c) Has an electric field directed along its length concentration and low level injection use to minority
(d) Acts as dipole carrier concentration and drift current is negligible for
minority carrier.
Ans. (b) : A long specimen of p-type semiconductor
material is electrically neutral. 259. Diffusion current of holes in a semiconductor is
proportional to (with p = concentration of
255. For an n-type semiconductor having any
holes/unit volume)
doping level, which of the following hold(s)
good: dp dp
2 2
(a) 2
(b)
(a) PnND = n i (b) pp ND = n i dx dx
(c) nnND = n i2 (d) Pn nn = n i2 dp d2p
(c) (d)
Nagaland PSC CTSE (Degree)-2018, Paper-I dt dx 2
Ans. (a) : For an n-type semiconductor, the doping Nagaland PSC CTSE (Degree)-2018, Paper-I
n 2 Ans. (b) : The carrier moves from one side to another
level as given as Pn = i side then concentration decreases due to recombination.
ND
dp
256. The electron and hole concentration in an intrinsic J D = −qD p
semiconductor are ni per cm3 at 300ºK now, if dx
acceptor impurities are introduced with a J ∝ dp
concentration of NA per cm3 (where NA >> ni) the D
dx
3
electron concentration per cm at 300ºK will be 260. The semiconductor bar is heated at one end, a
(a) ni (b) NA + ni voltage across the bar is developed. If the
(c) NA – ni (d) n i2 /NA heated end is positive, the semiconductor is
Nagaland PSC CTSE (Degree)-2018, Paper-I (a) P-type (b) N-type
Ans. (d) : By the law of electrical neutrality- (c) Intrinsic (d) Highly degenerated
P + ND = n + NA Nagaland PSC CTSE (Degree)-2018, Paper-I
Ans. (b) : The semiconductor for is heated at one end a
As N D = 0
voltage across the for is developed. If the heated end is
N A >> n i ≅ 0 P = N A positive, the semiconductor is n-type. When heated at
n2 n2 one end the concentration of electrons for an N type
So, n = i = i semiconductor will increase at the edge than at the bulk
P NA of semiconductor.
261. Match the following for the colour of light Ans. (b) : Given that
emitted by particular material of LED V =8V, L = 2m
(I) Red (A) GaN Vd = 2×104m/sec
(II) Green (B) AlInGaP µ=?
(III) Blue (C) GaP In electric field E = ?
(IV) Yellow (D) GaAsP 8
(a) I-A, II-B, III-C, IV-D E= =4
(b) I-D, II-C, III-A, IV-B 2
(c) I-C, II-D, III-A, IV-B E = 4V/ m
(d) I-D, II-A, III-B, IV-C
RPSC ACF & FRO 23.02.2021 Vd 2 ×104 20 × 103
Mobility µ = = =
KVS TGT (WE)-2016 E 4 4
Ans. (b) : The colour of the emitted light depends on µ = 5k m / V − sec
2
the type of material
GaAs - infrared radiation (invisible) 266. Given ρn = 0.5, µn = 1250m2/V-sec, q = 1.6×10–
19
GaP - Red or green light C, Find ND ?
GaAsP - red or yellow light (a) 1×1016 (b) 2×1017
16
262. The majority carriers in an n-type (c) 2×10 (d) 5×1016
semiconductor have an average drift velocity in NPCIL-2015
a direction perpendicular to a uniform Ans. (a) : Given as,
magnetic field B. The electric field E induced ρn = 0.5, µ n = 1250, q = 1.6 × 10−19
due to Hall effect acts in the direction
(a) v × B (b) B × v 1
ρn =
(c) Along V (d) Opposite to v N Dµ n q
Nagaland PSC CTSE (Degree)-2018, Paper-I 1 1
Ans. (b) : The given semiconductor is of n-type and ND = = = 1016
average drift velocity of carriers is Vd, force is defined ρn µ n q 0.5 × 1250 × 1.6 × 10−19
as-  x
F = −qE ……………(i) 267. n = 1017  1-  cm -3 , 0≤x≤L
 L
The force for an n-type semiconductor is-
L = 10 µm, Dn = 100 cm2/s. Find diffusion
F = −q ( Vd × B ) = q ( B × Vd ) current density at x = 5µm.
F q ( B × Vd ) (a) 1.3 A/cm2 (b) 1.6 kA/cm2
E= = (c) 2.6 kA/cm 2
(d) 6.2 A/cm2
q q
NPCIL-2015
E = B × Vd Ans. (b) : Given as, L = 10µm, D n = 100cm 2 / s
263. Depletion capacitance in a diode depends upon: Find out J at x = 5µm
A. Applied junction voltage
dn 1
B. Junction built-in potential J = qD n = q × 100 × 1017 × −
C. Current through junction dx L
D. Doping profile across the junction −19 1
= 1.6 ×10 ×10 × − 19
(a) A and B (b) A and C 10µm
(c) A, B and D (d) B, C and D 1
Nagaland PSC CTSE (Degree)-2018, Paper-I J = 1.6 × 10−19 × 1019 × −
Ans. (c) : Depletion capacitance in a diode depends 10 × 10−6 × 102
upon → Applied junction voltage, junction built-in J = 1.6 × 10 A / cm
3 2
potential, Doping profile across the junction. J = 1.6kA / cm 2

264. The p-n junction depletion layer is a ______ 268. Is = 10–18A, η = 1.05, ID = 70µA, VD of a diode
(a) Ionized accepter in n-side & ionized doner in ______.
p-side (a) 1.05VT1n(7×10–13) (b) 1.05VT1n(7×1017)
(b) Both side neutral (c) 1.05VTIn(7×1013) (d) None
(c) Ionized accepter in p-side and ionized donor NPCIL-2015
in n-side Ans. (c) : Given as,
(d) None Is = 10–18, η = 1.05, I D = 70µA, VD = ?
AAI-2015
Ans. (c) : The p-n junction depletion layer is a ionized I 
VD = ηVT l n  D 
accepter in p side and ionized in n side.
 IS 
265. Given V = 8V, L = 2m, Vd = 2×104, Find the
electric field in V/m and mobility µ in m2/V-sec.  70 × 10−6 
= 1.05VT l n  −18 
(a) 16, 80k (b) 4, 5k  10 
= 1.05VT l n ( 7 ×1013 )
(c) 8, 2k (d) 4, 4k
NPCIL-2015
269. For diode I0 = 10mA, VD = 4V at 20°C, at 40°C. (a) Zener diode (b) Gunn diode
The value of ID ____. (c) IMPATT diode (d) Tunnel diode
(a) 80mA (b) 40mA BARC Scientific Officer-2016
(c) 20mA (d) 10mA Ans. (a) : Gunn diode, Tunnel diode and impact diode
NPCIL-2015 are negative resistance devices but zener diode is not
Ans. (b) : Given as 200 C I0 is 10 mA show negative resistance.
At 300C I0 is = 2 × 10mA = 20mA 274. Which one of the following statement is
At 400C I0 is = 2 × 20mA = 40mA correct? A tunnel diode is always biased
(a) By a dc source
270. For current flowing through semiconductor, (b) In the middle of its negative resistance region
which of the following statement is true? (c) In the positive resistance region nearest to
(a) Only conduction current zero
(b) Only diffusion current (d) In the reverse direction
(c) Conduction current + Diffusion current Nagaland PSC CTSE (Degree)-2018, Paper-I
(d) None of these TNPSC AE-2013
ISRO Scientist- May, 2017 Ans. (b) : A tunnel diode is always biased in the middle
Ans. (c) : For current flowing through semiconductor, of its negative resistance region.
conduction current and diffusion current, option (c) is
true.
(•) At room temperature; a semiconductor has enough
free electron to allow it to conduction current.
(•) The diffusion current can be defined as a flow of
charge carriers within a semiconductor travels from
a higher concentration region to lower concentration
region.
271. Two initially identical samples A and B of pure
germanium are doped with donors to q
concentrations of 1×1020 and 3×1020, 275. The electrodes of a semi-conductor diode are
respectively. If the hole concentration in A is known as:
9×1012, then the hole concentration in B at the (a) gate and source (b) anode and cathode
same temperature will be (c) collector and base (d) cathode and drain
(a) 3×1012 m–3 (b) 7×1012 m–3 RRB SSE-03.09.2015, Shift-III
12
(c) 11×10 m –3
(d) 27×1012 m–3 Ans. (b) : The semiconductor diode is a unidirectional
ISRO Scientist- May, 2017 device. To obtain maximum current in the low
resistance or forward direction. A diode have 2
Ans. (a) : Donor concentration in sample A = 1 × 10 20 electrodes. Anode and cathode. The anode must be at a
Holes concentration in sample A = 9 × 1012 positive potential with respect to the cathode.
As we know n i2 = 9 × 1020 × 1012 = 9 × 1032 276. What semi-conductor device glows red, yellow
Donor concentration in sample B = 3 × 1020 or green, depending upon its chemical
composition?
n i2 = N DB × PB (a) A light-emitting diode
9 ×1032 = 3 ×10 20 × PB (b) A fluorescent bulb
(c) A neon bulb
PB = 3 ×1012 m–3 (d) A vaccum diode
272. In an abrupt p-n junction diode RRB SSE-03.09.2015, Shift-III
(a) Depletion region extends further in lower- Ans. (a) : A light-emitting diode semiconductor device
doped region glows red, yellow or green, depend upon its chemical
(b) Depletion region is independent of doping composition. L.E.D made by using elements like.
concentration Gallium, Phosphorus and Arsenic. When a LED
(c) Depletion region is symmetric about junction manufactured using gallium arsenide, it will produce a
(d) Depletion region extends further in higher- red light. If the LED is made with gallium phosphide, it
doped region will produce a green light.
UPPCL AE- 31.12.2018 277. The diode is an important part of a simple
Ans. (a) : A pn junction in which the concentration power supply. It converts AC to DC, since it:
(a) has a high resistance to AC but not to DC
of impurities changes suddenly from acceptors to
(b) allows electrons to flow in only one direction
donor is known as abrupt junction. In an abrupt from cathode to anode
junction p-n diode depletion region extends further (c) has a high resistance to DC but not to AC
in lower doped region. (d) allows electrons to flow in only one direction
273. Which of the following does not show negative from anode to cathode
resistance ? RRB SSE-03.09.2015, Shift-III
Ans. (b) : AC signal is a bidirectional in other hand DC 281. In electron tube, vacuum diode is made to work in−
is a unidirectional it means current flow in one (a) Cut-off region
direction. To convert AC to DC, the diode should (b) Space charge limited current region
conduct for 1 half cycle and block for another half (c) Saturation region
cycle. This is achieved by forward biasing of the diode (d) Temperature limited region
that allows electrons to flow in only one direction from RRB JE-01.09.2019, 3:00 PM – 5:00 PM
the cathode to anode and blocking flow of electrons for Ans. (b) :In electron tube consists of a vacuum
another cycle. container with a vacuum diode cathode and anode, it
278. For a PN Junction, when the N-side is more works on the principle of thermionic emission, when it
positive than the P-side, the diode is said to be: is given a positive voltage, electrons are emitted and
(a) Forward Biased and a large current exists attracted to the anode but if the positive voltage applied
(b) Forward Biased and a small current exists
is not sufficient then it attracts the electron due to
(c) Reverse Biased and a large current exists
(d) Reverse Biased and a small current exists repulsion in negative anode, space charge builds up
RRB SSE 21.12.2014, (Red) between the anode and the cathode. The vacuum diode
allows current to flow in only one direction.
Ans. (d) :
Forward biased when p side of diode connected to 282. A silicon p-n junction at a temperature of 200C
positive side of battery and n side of connected to has a reverse saturation current of 10pA. The
negative terminal of battery called forward biased. reverse saturation current at 400C for the same
A forward-biased diode offers very small resistance bias is approximately
to the flow of current and hence a large current flow (a) 50 pA (b) 30 pA
through the diode. (c) 60 pA (d) 40 pA
Reverse biased- If the n terminal connected to higher BPSC Polytechnic Lecturer-2014
potential and p terminal connected to lower potential, Ans. (d) : Current become double for every 100C
at this condition, diode is reversed biased. A reverse- increment of temperature.
biased diode offers very large resistance to the flow 0 0
of current and hence a small minority current flow at 300 C 

+10 C
→ 20pA at 300 C + 
+10 C
→ 40pA
through the diode. 283. Group-I lists four types of p-n junction diodes.
279. A p-n junction diode’s dynamic conductance is Match each device in Group-I with one of the
directly proportional to options in Group-II to indicate the bias
(a) the applied voltage (b) the temperature condition of that device in its normal mode of
(c) Current (d) Cascade amplifier operation:
RRB SSE 21.12.2014, (Yellow) A. Zener diode 1. Forward bias
Ans. (c) : The constant conductivity of a pn junction B. Laser diode 2. Reverse bias
diode is proportional the current, calculate of kinetic C. Avalanche photodiode
resistance of a diode by the ratio ( ∆VD / ∆ID ) of a diode D. Solar cell
to the change in unit voltage ( ∆VD ) and its consequent Codes
A B C D
change in current ( ∆I D ) . (a) 2 1 2 2
(b) 2 2 1 1
(c) 1 2 1 2
(d) 2 1 2 1
BPSC Polytechnic Lecturer-2014
Ans. (d) : Zener diode is a special diode used as a
regulator in reverse biased condition.
Solar cell- Forward bias
280. Calculate the reverse resistance of a Si diode
when the reverse voltage is 50V and the current LASER diode- Forward bias
is 100 nA. Avalanche photodiode- Reverse bias
(a) 500 MΩ (b) 100 MΩ 284. Which of the following devices has the highest
(c) 50 MΩ (d) 600 MΩ photo sensitivity?
UPPCL AE-05.11.2019 (a) Photoconductive cell (b) Photovoltaic cell
Ans. (a) : Given that, (c) Photodiode (d) Phototransistor
V = 50 Id = 100 nA RRB SSE 03.09.2015 Shift-II
V 50 Ans. (a) : Photoconductive cell- A photoelectric cell
Rd = = utilizing photo conductivity (as in a layer of sternum )
Id 100 × 10−9 so that increase in illumination causes a decrease in
50000 × 106 electrical resistance and permits the flow of a greater
Rd = electrical current.
100
• Among the following photoconductive cell has
R d = 500MΩ highest photo sensitivity.

285. In PN-junction diode, if doping concentration Ans. (b) : Optocoupler (Opto-Isolator) is a component
of acceptor atoms in P-region is increased then that transfers electrical signals, between two isolated
(a) depletion width in N-region will increase and circuit by using light. It prevent high voltage from
contact potential will decrease. affecting the system receiving the signal. Optocoupler
(b) depletion width in P-region and N-region will consist of LED and a phototransistor in same package
decrease while contact potential remains as shown below.
constant.
(c) depletion width in P-region will decrease and
contact potential will increase
(d) None of the above
Ans. (c) : We know that
288. Consider a pn junction in which the p-side is
kT  N A − N 0 
∆V0 = ln 2  ten times more heavily doped than the n-side.
q  ni  The depletion region would extend :
When NA is increased, ∆V0 = will increase and (a) equally on both n- and p- sides.
depletion layer in p region will increase. (b) more towards the p-side and less towards the
n-side
286. Small-signal equivalent circuit of PN junction (c) more towards the n-side and less towards the
is: p-side
(d) cannot be predicted
BSNL(JTO)-2002
Ans. (c) : In a P-N junction diode if the P region is ten
times more heavily doped than the n-region, then the
depletion region would extended more towards the n-
side and less toward the p-side.
289. Which of the following statements is true for
silicon pn junction solar cell?
(a) It can store optical energy
(b) It can store electrical energy
(c) It converts electrical energy into optical
energy
(d) It converts optical energy into electrical
energy
BSNL(JTO)-2002
Ans. (d) : Solar cell, also called photovoltaic cell, any
Where rs is resistance of neutral region rd is device that directly convert the energy of light into
dynamic resistance, Cd is diffusion capacitance electrical energy through the photovoltaic effect.
and CT is transition capacitance. 290. A diode which resembles a voltage variable
MPSC HOD Govt. Poly. -2013 capacitor is known as
Ans. (b) : Small signal analysis, capacitor will open (a) Tunnel diode (b) Schottky diode
circuited, (c) PIN diode (d) Varactor diode
Ans. (d) : Varactor diode is a type of diode whose
internal capacitance varies with respect to the reverse
voltage. It always works in reverse bias condition and is
When f = 0 a voltage dependent semiconductor device.
Cd & CT- open circuited and current will flow through rd. 291. Which of the following is one of the functions
287. Which of the following is NOT true about opto performed by a diode?
couplers ? (a) filter (b) amplifier
(a) It is a solid state device to isolate two parts of (c) rectifier (d) inverter
a circuit RRB SSE 02.09.2015, Shift-III
(b) It can act as an input device or output device Ans. (c) : A rectifier is an electrical device that
but not both converts alternating current (AC), which periodically
(c) Combines a light emitting diode and a reverses direction, to direct current (DC) which flow is
phototransistor in a single package only one direction. As such, the diode can be viewed as
(d) It prevents electrical poise or voltage an electronic version of a check value.
transients of one circuit from integrating with
other circuit
ISRO Scientist December, 2017
292. A Zener diode works on the principle of ∆I D = 1.039mA − 1mA
(a) tunneling of charge carriers across the ∆I D = 0.039mA
junction
(b) thermionic emission ∆ ID 39µA
(c) diffusion of charge carriers across the
297. The breakdown voltage VBD has:
junction
(a) Negative temperature coefficient for zener
(d) hoping of charge carriers across the junction.
effect and positive temperature coefficient for
TRB Poly. Lect. -2012
avalanche
Ans. (a) : A zener diode works on the principle of (b) Negative temperature coefficient for both,
tunneling of charge carrier across the junction. If occurs zener and avalanche
in a reverse biased p-n junction diode when electric (c) Positive temperature coefficient for both,
field enables tunneling of electron from the valance zener and avalanche
band to conduction band. (d) No temperature coefficient for zener and
293. Tunnel diode is a pn diode with avalanche
(a) very high doping in p region UPMRC AM - 2020
(b) very high doping in n region Ans. (a) : In zener breakdown, the electric field must be
(c) Very high doping in both p and n regions sufficiently high to move an electron from the valance
(d) low doping in both p and n regions
band to the conduction band.
TRB Poly. Lect. -2012 the required breakdown voltage decreases as the
Ans. (c) : A tunnel diode is a very highly doped temperature increases. thus zener breakdown has a
semiconductor diode. The p-type and n-type negative temperature coefficient.
semiconductor is heavily doped in tunnel diode due to In avalanche breakdown, a bunch of electron knocks out
greater number of impurities. other electrons to conduction band creating electron
294. Avalanche breakdown results basically due to hole pair.
(a) impact ionization Thus avalanche breakdown has a positive temperature
(b) Strong electric field across the junction coefficient.
(c) emission of electrons 298. For the circuit shown in figure, minimum
(d) rise in temperature. current required to keep zener diode in reverse
Mizoram PSC IOLM-2010, Paper-II break down region is 4 mA. The maximum
TRB Poly. Lect. -2012 value of resistance RS to keep zener diode in
Ans. (a) : Avalanche breakdown occurs due to high reverse break when VZ = 10 V is :
energy electron colliding with lattice electrons and
feeding it for conduction. The runaway effect of such
kind is called impact ionization if causes avalanche
breakdown in the material.
295. Which one of the following is not LED
material? (a) 7 kΩ (b) 5 kΩ
(a) GaAs (b) GaP (c) 1 kΩ (d) 2 kΩ
(c) SiC (d) SiO2 MPSC HOD Govt. Poly. -2013
TRB Poly. Lect. -2012 Ans. (d) :
Ans. (d) : An SiO2 is not LED material. It is an
insulator, used as an oxide layer in MOSFET.
296. A diode is biased at a current of 1 mA. What is
the current change if VD changes by 1mV?
(a) 38.4 mA (b) 2.6 mA
I Z( min ) = 4mA
(c) 2.6mA (d) 38.4 µA
UPMRC AM - 2020 VZ = 10V
Ans. (d) : Given that, Is = I L + I Z
I D1 = 1mA, ∆VD = 1mV , ∆I D = ?
VZ = constant = 10V
We know
∆VD
Is( max ) = I L + I Z( max ) and Is( min ) = I L + I Z( min )
ηVT
I D2 = I D1 .e Vs − VZ 10
R s( max ) = , Is( min ) = + 4
1mV Is( min ) 10
I D2 = 1mA × e 26mV
Is(min) = 5mA
ID2 = 1.039mA 20 − 10
R s( max ) =
Q The change in diode current will be. 5
∆I D = ID2 − ID1 R s( max ) = 2kΩ

299. A diode for which you can change the reverse It works on the tunneling principal tunnel diode voltage
bias and thus vary the capacitance is called a- control negative resistance.
(a) Switching diode (b) Varactor diode
(c) Tunnel diode (d) Zener diode
RRB JE- 31.08.2019, 10 AM-12 PM
Ans. (b) : Varactor diode:- It is P-N junction diode whose 305. For ideal zener diode, the voltage drop across
capacitance is varied by varying the reverse voltage. the diode is equal to
(a) Zero (b) Breakdown voltage
300. If temperature increases in a diode, then VD
(c) Unity (d) 0.47 V
(a) Increases by 2.5mv/°C
(b) Increases by 1.5mv/°C
(c) Decreases by 2.5mv/°C TANGEDCO AE-2015
(d) Doesn’t change with temperature Ans. (a) : For ideal Zener diode, the voltage drop across
SAIL- 2014 the diode is equal to zero. A Zener diode always work
Ans. (c) : The temperature increased the resistance and in reverse biasing condition.
the semiconductor diode decreased, the temperature is 306. If the current across a zener diode is increased
increased, the voltage across a semiconductor diode by a factor of 2, then the voltage across the
carrying a constant current will decrease. Hence the diode
correct option (c). (a) decrease by half (b) increase twice
301. Which type of breakdown occurs in normal P- (c) increase 4 times (d) remains constant
N junction diode? Nagaland PSC CTSE (Diploma)-2018, Paper-I
(a) Zener breakdown Ans. (d) : From the characteristic of Zener diode. It is
(b) Avalanched breakdown clear that the current can change but not voltage. That's
(c) Both why it is used as a voltage regulator.
(d) None 307. In tunnel diode, Fermi level lies
SAIL- 2014 (a) in the energy band gap but closer to
Ans. (b) : The Avalanched breakdown occurs in both conduction band n-type semiconductors.
normal diode and zener diode at high reverse voltage. (b) in the energy band gap closer to valence band
When high reverse voltage is applied to the P-N junction of p-type semiconductors.
diode, the free electrons (minority carriers) gain's large (c) In the energy band gap but above valence
amount of energy and accelerated to greater velocities. band of p-type and below conduction band of
302. Negative resistance region of a silicon Esaki n-type semiconductors.
diode remains the same even at a temperature (d) inside valence band of p-type and inside
of conduction band n-type semiconductors.
(a) 50ºC (b) 100ºC Sikkim PSC SI (Mains)-2018
(c) 150ºC (d) 200ºC Ans. (c) : In tunnel diode fermi level lies in the energy
Nagaland PSC CTSE (Degree)-2018, Paper-I band gap but above valence band of p-type and below
Ans. (c) : Negative resistance region of a silicon Esaki conduction band for n-type semiconductor. The Fermi
diode remains the same even at a temperature of 150ºC. level lies inside the conduction band on n-side and
303. Write the incorrect statement. A varactor inside the valence band on p-side because of this heavy
diode doping.
(a) Has variable capacitance 308. The semiconductor diode, which can be used in
(b) Utilizes transition capacitance of a junction switching circuits at microwave range is
(c) Has always a uniform doping profile (a) PIN diode (b) Varactor diode
(d) Is often used in an automatic frequency (c) Tunnel diode (d) Gunn diode
control device Nagaland PSC CTSE (Degree)-2017, Paper-II
Nagaland PSC CTSE (Degree)-2018, Paper-I Mizoram PSC AE/SDO-2012 Paper-III
Ans. (c) : The incorrect statement. A varactor diode has Ans. (a) : PIN diode can be used in switching circuit at
always a uniform doping profile. microwave range.
304. Tunnel diode shows Application of PIN diode-
(a) Current control negative resistance These diodes are used in the RF and also for
(b) Voltage control negative resistance microwave switches and microwave variable
(c) Voltage Control positive resistance attenuator since they are said to have low
(d) Current control positive resistance capacitance.
Nagaland PSE CISE (Degree) - 2017, Paper - I They are used in photodetectors and photovoltaic
UJVNL AE - 2016 cell and the PIN photodiodes are used for fibre
AAI-2015 optics network cards and also switches.
Ans. (b) : Tunnel diode show voltage control negative These diodes are effectively used for RF protection
resistance. circuits and it can also be utilized as an RF switch.
It is a highly doped PN junction diode, used for low The PIN photodiode is also used to detect X-rays
voltage high frequency switching application. and gamma rays photons.

309. The peak inverse voltage is applied across a Ans. (a) :
diode when it is 1
(a) on (b) on a heat sink Varicap diode capacitance ∝
Reverse Bias Voltage
(c) reverse biased (d) forward biased
The reverse voltage on the varicap diode is increased,
the depletion layer increases.
Ans. (c) : Peak inverse voltage is the voltage applied in Hence capacitance decreases.
reverse direction to the diode after that the depletion 314. Laser diodes typically having response time of
layer is damaged. 1 ns and spectral width of 2 nm are capable of
310. The maximum speed of electronic switch can coupling luminescent power of
be………operations per second (a) Less than ten milliwatt
(a) 104 (b) 10 (b) Tens to hundreds of microwatts
(c) 1000 (d) 109 (c) Hundreds of watts
Nagaland PSC (CTSE) Diploma-2017, Paper II (d) Tens to hundreds of milliwatts
Ans. (d) : Electronic switch is a device that can switch TNPSC AE-2014
an electrical circuit, interrupting the current or diverting it Ans. (d) : A laser diode is a semiconductor device
similar to a light-emitting diode in which a diode
from one conductor to another. Electronic switches are
pumped directly with electrical current can create losing
considered binary devices because they can be on or off.
conditions at diode's junction. Laser diode typically
Electronic switches have maximum speed of the order having response time of 1 nsec. and spectral width of 2
of GHz (109Hz) or 109 Hz operations per second. nm are capable of coupling luminescent power of tens
311. A pin diode is to hundreds of milliwatts.
(a) A metal semiconductor point diode 315. Light color and visibility is determined in LED
(b) A microwave mixer diode by
(c) Often used as a microwave oscillator (a) microwave (b) wavelength
(d) Suitable to use as a microwave switch (c) spectrum (d) capacitance
Nagaland PSC CTSE (Degree)-2018, Paper-I Nagaland PSC CTSE (Diploma)-2017, Paper-I
Ans. (d) : A pin diode is intrinsic semiconductor is Ans. (b) : The colour of the light emitted by LED
sandwiched in between high doped P and high doped N- depends on the wavelength of the light which depends
regions. A pin diodes frequently used as a switching on the semiconductor material that form the diode's PN
diode for frequencies up to GHz range, it is a junction. It is due to the difference in the energy gap
band structure.
microwave switch.
312. The junction capacitance of a varactor diode is hC
ε=
5pF with a reverse voltage of 4V. If this bias is λ
increased to 16V then the capacitance would 316. A GaAs LED emits light with Eg = 1.478 eV.
become The wavelength of the radiated light will be
(a) 20 pf (b) 10 pf (a) 0.64 µm (b) 0.84 µm
(c) 2.5 pf (d) 1.25 pf (c) 1.64 µm (d) 2.78 µm
Mizoram PSC AE/SDO 2012-Paper-I Nagaland PSC CTSE (Diploma)-2018, Paper-I
Ans. (c) : Capacitance 1.24
Ans. (b) : E g =
CP ∝
1 λ (µm)
VR 1.24
λ= µm
C P1 VR 2 1.478
= λ = 0.84µm
CP2 VR1
5 16 correct regarding the comparison between
=
CP2 4 Avalanche and Zener effect?
CP2 = 5/2 (a) Zener effect is caused by impact ionization.
(b) Zener diodes have higher resistance.
CP 2 = 2.5PF
(c) Avalanche effect occurs at voltages usually
313. When bias is applied to a varicap diode is above 7 V.
increased, its capacitance (d) Avalanche diodes have lower resistance.
(a) decreases ESE-2021
(b) increases Ans. (c) : Avalanche breakdown occurs at low doping
(c) remains constant density and under very high reverse voltage near about
(d) increases than decreases (8-10V), and zener breakdown occurs at high doping
Mizoram PSC AE/SDO 2012-Paper-I density and high reverse voltage around 5V.
318. In which of the following device reverse Ans. (c)
recovery time is nearly zero?
(a) diode (b) tunnel diode
(c) Schottky diode (d) PIN diode Photo diode –
Mizoram PSC AE/SDO 2012-Paper-I Photodiodes are designed to work in reverse bias
Ans. (c) : Schottky diode also known as schottky barrier condition.
Used material- Silicon, Germanium, Indium,
diode or hot-carrier diode. It has a low forward voltage
Gallium, Arsenide.
drop and very fast switching section. Dark current is the unwanted leakage current of a p-
n junction photodiode in the reverse direction, when
it is exposed to light.-
322. Which of the following parameters of a Silicon
Schottky Diode is higher than that of a
corresponding PN junction diode?
(a) Forward voltage drop
In schottky diode there is no charge storage, hence the (b) Reverse recovery current
reverse recovery time is nearly zero. (c) Reverse recovery time
(d) Reverse leakage current
319. In a photodiode, light is focused to fall on ISRO Scientist Engg.-2010
(a) p-region only Ans. (d) : Compare to P-N junction Diode, the schottky
(b) n-region only diode has :
(c) Full p and n regions Less reverse recovery current
(d) Junction region only Less forward voltage drop
GPSC Asstt. Prof. 11.04.2017 Less reverse recovery time
Ans. (d) : A photodiode is a semiconductor p-n junction High leakage current
It can operate high frequency
device that converts light into an electrical current. In a It produces less unwanted noise.
photodiode, light is focused to fall on junction region High efficiency.
only. 323. ______ current is the leakage current that
320. Which statement is correct for Schottky flows through a photo diode with no input used
diode? in as light detectors.
(a) Current Voltage characteristics is totally (a) Leakage (b) Dark
different than that of a p-n junction diode (c) Saturation current (d) Detection
(b) The current is controlled by the diffusion of
Ans. (b) : Dark current- When no light is illuminated
minority carriers on to diode because minority carriers in reverse bias.
(c) The current results from the flow of minority Photo diode operation- reverse bias
carriers
(d) The storage time ts is almost zero
ISRO Scientist Engg.-2016 Used- sensing device
Ans.(d): 324. The diffusion capacitance for a silicon diode
with a 10 mA forward current when the charge
carrier transit time of 70 ns is
(a) 1 nF (b) 1 pF
Schottky diode is a type of metal semiconductor (c) 1 µF (d) 1 F
junction diode, which is known as hot-carrier diode. TNPSC AE - 2018
Formed by the Schottky diode semiconductor with a Ans. (a) : Given, Transit time τ = 70ns
metal. Vd ( si ) = 0.7V
Forward voltage drop 0.2 to 0.3 volts.
Storage time is almost zero. Id = 10mA = 10 × 10−3 A
It is a unipolar device. Q Diffusion capacitance
The conduction of current happens only due to the I × τ I.τ
Cd = DQ
movement of electrons. 2VT VT
Reverse recovery loss and reverse recovery time are 10 × 70ns ×10−3
very less. =
0.7
321. Photodiodes operate at
10 × 70 × 10−9 × 10−3 ×100
(a) Forward bias (b) Breakdown region = = 10−9
(c) Reverse bias (d) Saturation region 70
ISRO Scientist Engg.-2016 Cd = 1nF

325. If the current in a diode is 10mA at forward • Varactors are used as voltage controlled capacitors
bias voltage of 0.1V, static resistance is and it operated in reverse biased state
(a) 10Ω (b) 100Ω • It used mainly in the radio frequency or RF circuits
(c) 1kΩ (d) 0.01Ω to provide voltage controlled variable capacitance.
Mizoram PSC AE/SDO 2012-Paper-I 331. Silicon diodes are preferred for high
V 0.1 temperature operation in comparison to
Ans. (a) : R = = 10Ω germanium because
I 10 ×10−3 (a) Silicon is thermally more stable
326. For low frequency operated diode, the effects of (b) Silicon can dissipate more power
diffusion capacitance is (c) Reverse saturation current is lesser in silicon
(a) negligible (d) None of these
(b) high MPPSC Forest Service Exam.-2014
(c) More than transition capacitance Ans. (c) : At room temperature, silicon crystal has few
(d) less than transition capacitance free electron than germanium. Hence it has low
Mizoram PSC AE/SDO 2012-Paper-I saturation current than germanium.
Ans. (c) : For low frequency operated diode, the effect 332. Silicon is preferred for making zener diodes
of diffusion capacitance is greater than that of transition because
capacitance. Diffusion capacitance is the capacitance (a) It has lower breakdown voltage
that happens due to transport of charge carrier between (b) It is cheaper
(c) Needs lower doping level
two terminal of a device.
(d) Has high temperature and current capacities
327. A.C. resistance of a diode means MPPSC Forest Service Exam.-2014
(a) static resistance Ans. (d) : The silicon semiconductor devices has
(b) dynamic resistance higher peak inverse voltage rating, current rating and
(c) it does not change with V-I characteristic wider temperature range than germanium
(d) constant resistance semiconductor. Hence silicon is preferred for making
Mizoram PSC AE/SDO 2012-Paper-I zener diode.
Ans. (b) : AC or dynamic resistance is defined as the 333. For a schottky barrier diode which of the
diode resistive nature when an ac source which depends following statements is true?
on the ac polarization of the p-n junction diode is (a) Operating speed is low
connected to it. (b) Current flows due to minority carriers
328. The maximum power dissipated by a diode is (c) There is no P – N junction
(a) VDID (b) VrIr (d) Current – voltage characteristics is exactly
(c) VDID +VrIr (d) zero similar to P – N diode
Ans. (c) : A schottky barrier diode or hot carrier diode
Ans. (a) : The maximum power dissipation in diode is is a semiconductor diode formed by the junction of
given by forward voltage drop and current flowing semiconductor with a metal. It has low forward voltage
through it Pm = VD × ID drop and very fast switching action.
Schottky diode has no P-N junction because this diode
329. Under normal conditions a diode conducts formed by the junction of a semiconductor with a metal.
current when it is
334. For small ac operation, a practical forward
(a) Reverse-biased (b) Forward-biased biased diode can be modeled as
(c) Avalanched (d) Saturated (a) A resistance and a capacitance
Mizoram PSC IOLM -2018, Paper I (b) An ideal diode and resistance in parallel
Ans. (b) : When we apply positive at anode and (c) A resistance and an ideal diode in series
negative at cathode, diode is said to be in forward (d) A resistance
biased condition. Nagaland PSC CTSE (Degree) -2017, Paper I
330. ______ of the varactor-diode changes with the Nagaland PSC CTSE (Degree) -2015, Paper I
change in applied voltage. Ans. (a) : For small ac operation, a practical forward
(a) Resistance biased diode can be modeled as a resistance and a
(b) Reactance capacitance.
(c) Concentration of carrier 335. Which of the following is not associated with a
(d) Temperature pn junction diode?
UKPSC Assistant Radio Officer Screening Exam.-2011 (a) Junction capacitance
Ans. (b) : Reactance of the varactor-diode changes with (b) Charge storage capacitance
the change in applied voltage. (c) Depletion capacitance
• Varactors diodes are used in electronic tuning (d) Channel length modulation
system to eliminate the need for moving parts Nagaland PSC CTSE (Degree) -2015, Paper I

Ans. (d) : Channel length modulation is not associated  V 
with a PN junction diode. Ans. (a) : I = I0 e 2θ(t ) − 1
PN junction associated with-  
• Charge storage capacitance This current equation is given to Silicon diode
• Function capacitance Q η = 1 − For Ge
• Depletion capacitance = 2 − For Si .
336. A diode whose terminal characteristics are
v 340. Bulk resistance of a diode is
 r 
 t
related as i a = I s e where Is is the reverse (a) sum of resistance values of n-material and p-
material
saturation current, and VT is the thermal
voltage (= 25 mV) is biased at ID = 2mA. Its (b) sum of half the resistance values of n-material
dynamic resistance is and p-material
(a) 25 Ω (b) 12.5 Ω (c) equivalent resistance of the resistance value
of p and n-material in parallel
(c) 50 Ω (d) 100 Ω
(d) none of the above
Mizoram PSC IOLM-2010, Paper-II
ηVT
Ans. (a) : Dynamic resistance, R = Ans. (a) : The bulk resistance RB of a diode is the
I approximate resistance across the terminals of diode
The value of η for Ge, η =1 when forward voltage and current are applied across it
for Si, η = 2 the bulk resistance represent the resistance of the p and
here we consider as diode is made of Si n material of p–n junction of the diode
2 ( 25 ×10−3 ) 341. Regarding a Schottky diode which of the
R= following statements is incorrect?
2 ×10 −3
(a) It is a bipolar device
R= 25 Ω (b) Has fast recovery time
337. V-I characteristic of a varistor is given by (c) Has no depletion layer
(a) i = k e (b) i = k e2 (d) Has metal-semi conductor junction
(c) i = k/en (d) i = k en Nagaland PSC CTSE (Degree)- 2016, Paper-I
Ans. (a) : Schottky diode also known as Schottky
Ans. (d) : V-I characteristics of varistor is given by barrier diode or hot recovery diode is a semiconductor
i = k en diode formed by the junction of a semiconductor with a
338. The dynamic resistance of a semi-conductor metal. It has low forward voltage and very fast
diode is switching action.
(a) Its resistance when it is forward biased
342. Match List-I with List-II and select the correct
(b) Its resistance when it is reverse biased
answer using the code given below the Lists:
(c) The AC opposition to the current flow
(d) None of these List-I List-II
Nagaland PSC CTSE (Diploma)-2018, Paper-I A. Tuned circuits 1. Schottky diode
B. Voltage reference 2. Varactor diode
Ans. (a) : Dynamic resistance of a semiconductor
C. High frequency 3. PIN diode
diode is occurs when diode is in forward biased.
switch
D. Current 4. Zener diode
controlled
attenuator
Code:-
A B C D
(a) 2 4 1 3
(b) 3 4 1 2
(c) 2 1 4 3
(d) 3 1 4 2
IES-2012
Ans. (a) :
Zener diode
339. The relationship between I & V for a junction
(1) Operates on the principle of tunneling effect
 v ( 2 φt ) 
diode is given by I = I 0  e − 1  The (2) Always operated under Reverse biased
  (3) Mainly used in voltage Regulation application
junction diode is (4) Zener diode used as voltage Reference
(a) Silicon diode (b) Germanium diode Varactor diode
(c) GaAs diode (d) Palladium diode (1) Varactor are used as voltage controlled capacitor
Mizoram PSC IOLM-2010, Paper-II and its operates in a reverse biased state.

(2) Varactor diode used as Tuned circuit. Ans. (a) : Zener diode:- It is heavily doped P-N
(3) Used mainly in tuning application and in low micro junction diode which is operated in reverse bias
device condition in the break down region.
Pin diode It has very narrow depletion layer and negative
(1) It is PIN diode. I represent intrinsic material temperature coefficient like tunnel diode.
(2) In PIN diode light doped intrinsic semiconductor is 348. A light-emitting diode (LED) converts :
sandwiched between heavily doped semiconductor. (a) sound energy into optical signal
(3) It always operates under reverse biased condition.
(b) optical signal into thermal energy
Schottky diode
(c) thermal energy into electrical signal
(1) Schottky diode is used as high frequency switch.
(d) electrical current into optical signal
343. The reverse saturation current of a diode
KVS TGT (WE)- 2017
means
(a) the current under reverse bias Ans. (d) :
(b) saturated current in forward bias
(c) highest current
(d) current for full load
Ans. (a) : The reverse saturation current is that part of A light emitting diode is a semiconductor light source
the reverse current in a semiconductor diode caused by that emits light when current flows through it.
diffusion of minority carriers from the neutral regions to A light emitting diode (LED) that emits more light
the depletion region.
energy than it consume and converts into optical energy
344. In a silicon p-n junction diode with large (light) & it wastes little electricity.
forward bias current is dominated by
(a) Majority carrier diffusion current 349. In a p-n junction with no externally applied
(b) Recombination current in the depletion region voltage, the drift and diffusion components of
(c) Diffusion current outside the depletion region the hole and electron currents :
(d) Diffusion and recombination current in (a) must sum to zero separately
depletion region are almost equal (b) must sum to unity separately
UPPCL AE- 31.12.2018 (c) must sum to zero
Ans. (c) : When the p-n junction is forward biased the (d) must sum to unity
junction potential is lowered which allows the majority KVS TGT (WE)- 2017
carrier holes in the p-side of diffusion across the Ans. (c) : In a p-n junction when no external voltage is
junction because of a high concentration gradient. applied then, the net current is zero. Hence the drift and
345. The light output of LED varies as (Current)n. diffusion components of the hole and electron currents
the value of n is about must sum to zero.
(a) 0.5 (b) 1 350. The device that convert optical radiation into
(c) 1.3 (d) 2.1 electrical energy is:
KVS TGT (WE)- 2014 (a) LED (b) Photo-detector
Ans (c): The light output of the LED vary from (c) Solar cell (d) P-I-N diode
(current)n then the value of n varies from 1.2 to 1.5 KVS TGT (WE)- 2018
346. In the silicon crystal structure, the Ans. (c) : Solar cell is a device that converts optical
recombination rate is proportional to the radiation into electrical energy.
number of : "Solar cell, also called photovoltaic cell is a device that
(a) free electrons and holes
directly converts the energy of light into electrical
(b) covalent bonds
energy through the photovoltaic effect."
(c) free electrons
(d) free holes
KVS TGT (WE)- 2017
Ans. (a) : In an intrinsic semiconductor (undoped
silicon) the number of electrons and the number of
holes are equal. Hence recombination rate depends on
both the number of electrons and number of holes.
347. If a zener diode is made from heavily doped
semiconductors, its depletion region becomes 351. The visible LED are made of a material having
very narrow and the structure becomes : energy band-gap:
(a) Tunnel diode (b) Varactor diode (a) Larger than 1.8 eV (b) 1.1 eV
(c) PIN diode (d) Schottky diode (c) 0.6 eV (d) 1.42 eV
KVS TGT (WE)- 2017 KVS TGT (WE)- 2018
Ans. (a) : The variable LED are made of a material 355. In resistance level, the AC or the dynamic
having energy band-gap larger than 1.8eV. resistance of a p-n junction diode is defined by
A light- emitting diode (LED) is a semiconductor light (a) a point on the characteristics
source that emits light when it is forward biased. (b) a tangent line at the Q-point in graphical
determination
352. The depletion region consists of: (c) the straight line between limits of operation
(a) Free electrons (d) The ratio of current through load to voltage
(b) Negative and positive ions across load
(c) Holes ESE-2022
(d) Photons (b) : In resistance level the AC or the dynamic
KVS TGT (WE)- 2018 resistance of a p-n junction diode is defined by a tangent
Ans. (b) : The depletion region in a p-n junction diode line at the Q-point in graphical determination.
is formed at the junction diode where no mobile charge 356. A Zener diode voltage regulator has load
carriers are present. Depletion layer acts like a barrier requirement of 16 V and 2 Amp. The diode's
that apposes the flow of electrons from n-side and holes minimum current requirement is 2.5A. The
from p-side. minimum voltage at input is 29 V. What will be
the maximum efficiency of the circuit?
353. (a) 78% (b) 44.13%
(c) 23.99% (d) 88.90%
Ans. (b) : Given,
V0 = 16 Volt, I0 = 2 Amp
Which of the following is correct in the above Vin = 29 Volt, Imin = 2.5 Amp
figure, if I = 0?
Output
(a) Voltage across A < Voltage across B Q Efficiency (η) = × 100
(b) Voltage across A > Voltage across B Input
(c) Voltage across B = Infinite 16 × 2
(d) Voltage across A = Voltage across B = × 100 ]
29 × 2.5
LMRC AM- 16.07.2021
Ans. (a) : Voltage across A is less than voltage across B. ( η) = 44.13%
354. Diffusion capacitance of PN junction diode 357. According to the tunneling phenomenon of
_____. tunnel diode which one of the following is true?
(a) decreases with increasing current and (a) Width of the junction barrier varies inversely
increasing temperature as the square root of impurity concentration.
(b) Decreases with decreasing current and (b) Width of the junction barrier varies as the
decreasing temperature cube root of impurity concentration.
(c) Increases with increasing current and (c) Width of the junction barrier varies as the
impurity concentration.
(d) Width of the junction barrier varies as the
(d) Increases with increasing current and
square root of impurity concentration.
decreasing temperature DFCCIL Executive S&T-17.04.2016, Shift-II
DFCCIL Executive (S&T) 11.11.2018, 4:30 to 6:30PM
Ans. (a) : According to the tunneling phenomenon of
Ans. (d) : We know that, tunnel diode width of the junction barrier varies
τI inversely as the square root of impurity concentration.
CD = f Where If = forward current
ηVT 358. In varactor diode, if reverse voltage will
increase space charge width:
∴ CD ∝ I f
(a) Decreases rapidly
KT (b) Increases
Q VT = (c) Remains the same
q
(d) Decreases
Q VT ∝ T DFCCIL Executive S&T-17.04.2016, Shift-II
1 Ans. (b) : In varactor diode, if reverse voltage will
∴ CD ∝ increase space charge width increases.
T
Thus, we can say that
CD ↑  → If ↑
and CD ↓ 
→T ↑

359. Which of the following requires a centre- Ans. (a) : Due to increase in temperature atom vibrates
tapped transformer and is used in vacuum more which reduces the mean free path for electrons,
tubes? which increases the avalanche break down voltage.
(a) Two diodes full-wave rectifier circuit on the other hand in case of Zener break down when
(b) Bridge rectifier circuit temperature is increased band gap is reduced which
(c) Single diode full-wave rectifier circuit reduces Zener break down voltage as well.
(d) Inverted bridge rectifier circuit From above analysis it's clear that avalanche
DFCCIL Executive S&T 29.09.2021, 12:30 to 2:30PM multiplication is positive and Zener break down is
Ans. (a) : A full wave rectifier is defined as a rectifier negative in respect of temperature coefficient.
that converts the complete cycle of alternating current
363. A Si junction is at 100ºC, barrier potential at
into pulsating DC unlike half wave rectifiers that utilize
25ºC is 0.7V. The value of barrier potential at
only the half wave of the input AC. Full wave rectifiers
100º C will be
utilize the full cycle of AC supply.
(a) 0.7V (b) 0V
(c) 0.55V (d) 0.40V
TSTRANSCO AE- 2018
1
Ans. (c) : Barrier potential ∝
Temperature in kelvin
Given that,
360. One easy way of creating biased diode clipping T1 = 100ºC = 100 + 273 = 373 K
circuits without the need for an additional T2 = 25ºC = 25 + 273 = 298 K
EMF supply is to use______, V25ºC = 0.7 V
(a) Zener diodes (b) PIN diodes V100ºC = ?
(c) Tunnel diodes (d) Varactor diodes V100ºC T2
=
DFCCIL Executive S&T 29.09.2021, 12:30 to 2:30PM V25ºC T1
Ans. (a) : One easy way of creating biased diode 298
clipping circuits without the need for an additional EMF V100ºC = 373 × 0.7
supply is to use zener diode.
208.6
Zener diodes are used for voltage regulation, as =
reference elements surge suppressors and in switching 373
applications and clipper circuits. V100ºC = 0.55V
361. Diode junction breakdowns above 5 V are 364. Which of the following diodes operates with a
caused by: forward biased metal-semiconductor junction?
(a) Diffusion effect (a) Schottky diode (b) Tunnel diode
(b) Avalanche effect (c) Gunn diode (d) PIN diode
(c) Combination of two effects KVS TGT (WE)- 2016
(d) Zener effect UPRVUNL AE-11.06.2014
DFCCIL Executive S&T 29.09.2021, 12:30 to 2:30PM Ans. (a) : Schottky diode it is also known as barrier
Ans. (b) : Diode junction breakdowns above 5V are diode or hot carrier diode. It is a type of semiconductor
caused by avalanche effect. which have one side a metal like (Cu, Ag....) and one
Avalanche effect is a sudden increase in the flow of an side have N type semiconductor. It has low voltage drop
electrical current through a non-conducting or and high switching speed. It works in forward biasing.
semiconducting solid when a sufficiently strong
electrical force is applied.
362. Which of the following statements is correct
with respect to the temperature coefficient of Symbol of Schottky diode
breakdown in diodes 365. What happens to a diode, if the PIV rating of
(a) Temperature coefficient of avalanche the diode is exceeded?
multiplication and zener breakdown are (a) Diode behaves as zener diode
positive and negative respectively
(b) Diode conducts poorly
(b) Temperature coefficient of avalanche
(c) Diode get destroyed
multiplication and zener breakdown are
(d) Diode stops conducting
negative and positive respectively
KVS TGT (WE)- 2016
(c) Temperature coefficient of both avalanche
multiplication and zener breakdown are Ans. (c) : The maximum value of voltage in reverse
positive biasing that diode can bear without breaking the
(d) Temperature coefficient of both avalanche junction is known as peak inverse voltage. If we exceed
multiplication and zener breakdown are negative the PIV, the junction will breakdown and diode get
TSTRANSCO AE- 2018 destroyed.
366. The knee voltage of a crystal diode is Ans. (c) : As per question figure it represents piecewise
approximately equal to linear model of diode as it contains voltage source,
(a) reverse voltage (b) forward voltage resistance and ideal diode in series.
(c) barrier potential (d) breakdown voltage 370. In a forward-biased p-n diode with NA>>ND,
KVS TGT (WE)- 2016 the product of dynamic diode resistance and
Ans. (c) : diffusion capacitance CD equals :
(a) τ2P (b) –τP
(c) τP–1 (d) τP
UPPCL AE-30.03.2022
Ans. (d) : In a forward biased p-n diode with NA>> ND
the product of dynamic diode resistance (rd) and
diffusion capacitor (CD) is-
The maximum value forward voltage at which junction CD × rd = τp
breakdown and current increase rapidly. So the value of
this voltage is known as knee voltage and for crystal 371. An ideal crystal diode is one which behaves as a
diode it is approximately equal to barrier potential. perfect ________ when forward biased.
367. Which of the following devices has (a) conductor (b) Switch
characteristics very close to the ideal voltage (c) resistor (d) insulator
source? UPPCL AE-30.03.2022
(a) MOSFET (b) FET Ans. (a) : An ideal crystal diode is one which behaves as a
(c) BJT (d) Zener Diode perfect conductor when forward biased. The internal
KVS TGT (WE)- 2016 resistance of ideal diode is zero in forward biased.
Ans. (d) : Zener diode has characteristics very close to 372. The leakage current in a crystal diode is due to:
the ideal voltage source. Because Zener diode works in (a) minority carriers
reverse bias, in this condition junction breakdown (b) Both minority and majority carriers
occurs. Voltage will constant and current will increase (c) majority carriers
rapidly. (d) junction capacitance
UPPCL AE-30.03.2022
Ans. (a) : Minority carrier of each material are pushed
through the depletion zone to the junction. This action
causes a very small leakage current to occur.
373. For an abrupt P-N junction, the doping on P
Reverse
side and n side are N –A = 9 × 1016 cm–3; N +D =
Reverse
1016 cm–3. If the total width is 3 µm, what is the
368. In the P-N junction, the barrier voltage depletion layer width on p side ?
(a) decreases with increase in temperature (a) 1.7 µm (b) 0.3 µm
(b) increases with increase in temperature (c) 2.25 µm (d) 2.7 µm
(c) decreases with decrease in temperature UPPCL AE-30.03.2022
(d) is independent of temperature Ans. (b) : Given, N A– = 9×1016 cm–3, N +D = 1016 cm–3
KVS TGT (WE)- 2016
Total width = 3µm. Wp = ?
Ans. (a) : In the PN Junction if we increase the NAWP = NDWn
temperature the more number of electrons and holes 9×1016×Wp = 1016×Wn
generate and depletion width decreases, so that is why 9Wp = Wn
the barrier voltage decreases with increases in the According to question - Wp+Wn = 3µm
temperature. Wp + 9Wp = 3µm
369. 10Wp = 3µm
Wp = 0.3µm
374. The drift current is 200 mA and the diffusion
current is 2 A. What is the total current in the
semiconductor diode?
(a) 3 A (b) 2.8 A
The given figure represents which form of (c) 2.2 A (d) 2.02 A
diode equivalent circuit? UPPCL AE-30.03.2022
(a) Integrated Model Ans. (c) : Given,
(b) Differential Model Idrift = 200mA, Idifusion = 2A
(c) Piecewise Linear Model Idrift = 0.200A
(d) Ideal Model Total current (I) = Idrift + Idiffusion
LMRC AM- 16.07.2021 I = 2+0.200 = 2.2 A
375. The solar or photo voltaic cell converts: PD 0.5
(a) Chemical energy in to electrical energy ID = = = 0.5A
VD 1
(b) Solar radiation to electrical energy
(c) Solar radiation to thermal energy Breakdown voltage ( VBR ) = 150V
(d) Thermal energy to electrical energy PD 0.5
UPRVUNL AE-2016 Breakdown current ( I BR ) = = = 0.00333
VBR 150
Ans. (b) : The solar or photo voltaic cell converts solar
radiation to electrical energy . I BR = 3.33 mA
when light shines on a photovoltaic (PV) cell-also 380. The band gap energies for silicon and
called a solar cell, that light may be reflected , absorbed germanium photodiodes are 1.1 eV and 0.67 eV
or pass right through the all. The PV cell is composed of respectively, their cutoff wavelength
semiconductor material. respectively would be :
376. The diode with negative resistance (a) 1127.27 nm, 1850.75 nm
characteristics is_______. (b) 1850.27 nm, 2167.91 nm
(a) Rectifier diode (b) Rf detector diode (c) 456.12 nm, 1127.27 nm
(c) Tunnel diode (d) Laser diode (d) 1315.45 nm, 1850.75 nm
UPRVUNL AE-2016 KVS TGT (WE)- 2017
Ans. (c) : The diode with negative resistance Ans. (a) : Given, Band gap energies are - E (Si) = 1.1
g
characteristics is tunnel diode. eV, Eg(Ge)= 0.67 eV
• Tunnel diode also called Esaki diode. Photon energy-
• It is used in designing microwave oscillators as a hc
relaxation oscillator, in designing of pulse and E=
switching circuits and as parametric amplifier. λ
377. When forward bias is applied across a p-n hc 6.63 × 10−34 × 3 ×108
λSi = = = 11.2727 × 10–7 m
junction, it - E 1.1× 1.6 × 10−19
(a) increases the potential barrier λSi = 1127.27 nm
(b) decreases the potential barrier
(c) increases the depletion region width hc 6.63 × 10−34 × 3 ×108
λGe = = =18.5075×10-7m
(d) None of the above E 0.67 × 1.6 × 10−19
UPPSC Poly. Tech. Lect.-22.03.2022, Paper -I λGe = 1850.75 nm
Ans. (b) :In forward biasing the positive terminal of the 381. A photo diode have responsivity R=65 and P =
0
battery is connected to the p-side and the negative 10kW then find photo current (Ip)
terminal to the n-side of the p-n junction. (a) 600kW (b) 700kW
The forward bias voltage opposes the potential barrier.
(c) 650kW (d) 800kW
Due to this, the potential barrier is reduced and hence
AAI-2015
the depletion layer becomes thin.
Ans. (c) : Responsivity R = 65
378. A silicon diode has a bulk resistance of 2Ω and
P0 = 10 kW
a forward current of 12mA. The actual voltage
across the diode is: Photo current IP = ?
(a) 0.6 V (b) 24 V we know that ,
(c) 2.4 V (d) 0.624 V Ip
TNTRB AE– 2017
R=
P0
Ans. (d) : Given that Bulk resistance
I p = P 0R
rB = rn + rp = 2Ω IP = 65×10
If = 12mA
–3 IP = 650kW
Vd =0.6+2×12×10 = 0.6+0.024V = 0.624 V
382. When the bias in reverse biased diode is
379. A diode has maximum power dissipation of 0.5
watts (a) what is the maximum d.c. current increased beyond a certain value, the
allowed in the forward direction when the phenomenon is called?
forward voltage drop is 1 volt ?(b) what is the (a) Breakdown (b) Early Effect
break down current that burns out the diode if (c) Tunneling (d) Saturation
the breakdown voltage is 150 V? (e) Cut off
(a) 0.5A, 3.33 mA (b) 5A, –3.33 mA CGPSC SO 14.02.2016
(c) 50 A, 3.33 mA (d) 0.05A, –3.33 mA Ans. (a) : When the bias in reverse biased diode is
TNTRB AE– 2017 increased beyond a certain value. The phenomenon is
Ans. (a) : Given, called breakdown.
Maximum power dissipation (PD) = 0.5 Watts 383. Consider a pn junction diode made of silicon.
Forward voltage drop (VD) = 1 V In this case, which of the following statements
then, PD = VD I D is true?

(a) The value of current depends exponentially Ans. (b) : The wavelength and intensity of LED
on the voltage applied depends on both energy gap and bias of the diode. The
(b) The value of voltage depends exponentially wavelength of emitted light depends on the energy gap
on the current through the diode of the semiconductor.
(c) The value of current depends linearly on the 389. Which of the following is NOT a characteristic
voltage applied. of Schottky diode ?
(d) The value of voltage depends linearly on the (a) Thermionic emission of carriers across
current through the diode Schottky barrier
BSNL(JTO)-2002 (b) Current conduction in Schottky diodes is by
Ans. (a) : The value of current depends exponentially majority carriers
on the voltage applied (c) Switching speed of Schottky diodes is less
I = I0 e V / ηvT − 1 compared to p-n junction diodes
384. When operating as a voltage regulator the (d) Schottky diode comprises of metal-
breakdown in a Zener diode occurs due to the semiconductor junction
(a) tunneling effect ISRO Scientist December, 2017
(b) avalanche breakdown Ans. (c) : Schottky diode :- It is not a typical diode
(c) impact ionization because it does not have a P-N junction.
(d) excess heating of the junction The schottky diode significant characteristic is its fast
DRDO-2008 switching speed as it does not allow the diode to reach
Ans. (a) : When operating as a voltage regulator the saturation.
breakdown in zener diode occurs due to the tunneling Schottky diode useful for high-frequencies and digital
effect. application.
385. Which one of the following statements is TRUE 390. A photodiode is normally:
for an 'ideal' power diode? (a) Forward biased
(a) Forward voltage drop is zero and reverse (b) Emitting light
saturation current is non-zero. (c) Neither forward nor reverse biased
(b) Reverse recovery time is non-zero and (d) Reverse biased
reverse saturation current is zero. LMRC AM (S&T)-13.05.2018
(c) Forward voltage drop is zero and reverse Ans. (d) : A photo diode is reverse biased, the increase
recovery time is zero. in intensity of the striking light load to increase in the
(d) Forward voltage drop is non-zero and reverse reverse current.
recovery time is zero. 391. In a LED light emits from ____.
BSNL(JTO)-2009 (a) P side (b) N side
Ans. (c) : Forward voltage drop is zero and reverse (c) Both side (d) None
recovery time is zero. NPCIL-2015
386. Which one of the following diodes contains a Ans. (c) : The light emitting diode is connected in
metal-semiconductor junction? reverse bias, hence it shows the corresponding
(a) Tunnel diode (b) Zener diode characteristic the electron travel from n-side to p-side
(c) Schottky diode (d) Gunn diode crossing the large potential barrier to application of
BSNL(JTO)-2009 external potential.
Ans. (c) : Schottky diode is uses a metal semiconductor 392. In a photo diode, the light intensity increases
junction. then current _____.
387. The phenomenon of injection electro- (a) Increases (b) Decreases
luminescence is the basis of working of (c) Constant (d) Can't predict
(a) photodiodes (b) light emitting diodes NPCIL-2015
(c) photo transistors (d) solar cells Ans. (a) : Because when intensity of incident light
BSNL(JTO)-2009 increases in incident light. If number of Incident photon
Ans. (b) : Electro luminescent material are able to emit increases, then number of emitted photo electrons also
light in response to the application of an electrical increases, consequently the photo electric current increases.
current or a strong electric field.
393. Fick's second law of diffusion process is
388. The wavelength of the emitted light in LED
∂N ( x, t ) ∂ 2 N ( x, t )
depends on : (a) = D⋅
(a) voltage across LED ∂t ∂x 2
(b) energy band gap of material used to fabricate ∂N ( x, t ) ∂N ( x, t )
LED (b) = D⋅
∂t ∂x
(c) surrounding temperature
(d) none of the above ∂ N ( x, t )
2
∂N ( x, t )
(c) = D⋅
MPSC HOD Govt. Poly. -2013 ∂t 2
∂x
∂ 2 N ( x, t ) ∂ 2 N ( x, t ) 397. Cut-in voltage of a silicon diode is
(d) = D⋅ (a) 0.1 V (b) 0.2 V
∂t 2
∂x 2
(c) 0.6 V (d) 0.25 V
TNPSC AE-2014 TNPSC AE-2013
Ans. (a) : Fick's laws of diffusion describe diffusion Ans. (c) : For silicon diode the cut in voltage is 0.6 V to
and were derived by Adolf Fick in 1855. They can be 0.7 V.
used to solve for the diffusion coefficient, D. Fick's first For germanium diode the cut in voltage is 0.2 V to 0.3 V.
law can be used to derive his second law which in term 398. Avalanche photodiodes are preferred over PIN
is identical to the diffusion equation. diodes in optical communication systems
∂N ( x, t ) ∂ 2 N ( x, t ) because of
= D⋅ (a) Speed of operation
∂t ∂x 2
(b) Higher sensitivity
394. Which of the following is not a constituent of a (c) Larger bandwidth
solar lighting system (d) Larger power handling capacity
(a) Photo voltaic cell (b) Back up batteries TNPSC AE-2013
(c) Charger (d) Earth wire
Ans. (d) : Avalanche photo diodes are preferred over
RRB SSE 02.09.2015, Shift-II PIN diodes in optical communication systems because
Ans. (d) : Earth wire is not a constituent of a solar of large power handling capacity. Avalanche
lighting system. photodiode is a highly sensitive semiconductor photo
395. The diffusion capacitance of a p-n junction diode detector.
diode 399. Transformation utilization factor of a dc power
(a) Increases exponentially with forward bias supply may be defined as
voltage Transformer secondary power
(b) Decreases exponentially with forward bias (a)
Transformer primary power
voltage
(c) Decreases exponentially with forward bias Pdc
(b)
voltage Pac (rated)
(d) Increases linearly with forward bias voltage
Pdc Pac
UJVNL AE-2016 (c) (d)
Ans. (a) : Diffusion capacitance is the capacitance that Pac Pac (rated)
happens due to transport of charge carrier before the TNPSC AE-2013
terminal. Diffusion capacitance Ans. (b) : Transformation utilization factor
τI Pdc Pout
Cd = d e VD / ηVT TUF = =
ηVT Pac (rated) Pin (VA)
VT ⇒ varies with exponentially Hence it increase 400. The dynamic resistance of diode is
exponentially of a p-n junction diode with forward bias (a) the resistance of diode when forward biased
voltage. (b) the resistance of diode when reverse biased
396. The radiative and non radiative recombination (c) the AC opposition to the current flow
lifetimes of the minority carriers in the active (d) none of these
region of a double-hetero junction LED are 60 TNPSC AE-2013
nsec and 100 nsec respectively. What is the Ans. (c) : The dynamic resistance of diode is the ac
total carrier recombination lifetime? opposition to the current flow. Dynamic resistance of
(a) 37.5 psec (b) 37.5 nsec diode is also referred as ac resistance of diode.
(c) 3.75 nsec (d) 3.75 psec 401. The voltage control circuits do not use
TNPSC AE-2014 resistance potential dividers because
Ans. (b) : Given that, (a) they involve a larger power loss
Radiactive recombination life time ( τr ) = 60n sec (b) they cause distortion of waveform
(c) they do not give a smooth variation of voltage
Non-radiactive recombination life time ( τnr ) = 100n sec (d) they have non-linear characteristics
Total carrier recombination life time- TNPSC AE-2008
1 1 1 1 1 Ans. (a) : The voltage control circuit do not use resistance
= + = + potential divider because they involve large power loss.
τ τr τnr 60 100
Hence bias active device and amplifiers are used.
1 10 + 6 402. A solar cell consists of
=
τ 600 (a) P – N junction
600 (b) A semiconductor bonded to metal
τ= (c) A piece of silicon
16
(d) Photo – emission material
τ = 37.5n sec
Ans. (a) : A solar cell is a environment friendly energy (a) n-type (b) p-type
sources. A solar cell consist of p-n junction diode which (c) No doping (d) None of these
convert solar energy into electrical energy. Mizoram PSC Jr. Grade -2018, Paper-III
403. Tunnel diode is used in Ans. (a) : The Gunn diode internal construction is
unlike other diodes in that it is consist only of N-doped
(a) Rectifier (b) Filters
semiconductor material, whereas most diode consist of
(c) Digital circuits (d) Oscillator
both P and n doped material.
408. The saturation current under reverse bias
Ans. (d) : A tunnel diode is used in many microwave condition of a p-n junction is due to:
application where it can be used in oscillator and (a) Majority carriers (b) Minority carriers
amplifier. A tunnel diode is a type of microwave semi (c) Both (a) and (b) (d) None of the above
conductor diode. OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
404. A silicon PN junction at a temperature of 200C Ans. (b) : There is a certain amount of minimum
has a reverse saturation current of 10pA. The current flowing through the p-n junction under the
reverse saturation current at 400 C for the reverse bias condition.
same bias is approximately. This current is referred to as the reverse saturation
(a) 20pA (b) 30pA current (Is) and is due to the minority charge carriers in
the semiconductor devices. The reverse saturation
(c) 40pA (d) 80pA
current is independent of reverse voltage but it doubles
Nagaland PSC CTSE (Degree) -2015, Paper I
at every 100C rise in temperature
Ans. (c) : We know reverse saturation current is 409. Considering (i) Si P-N junction diode (ii) Zener
increase by factor of this 10ºC rise temperature. The diode and (iii) Avalanche diode Which of these
value of reverse saturation current at 40ºC will be will have reverse break down voltage less than
I = I0 2T2 − T1 /10 5V?
40 − 20 (a) All of these (b) Only (iii)
= 10 × 2 10 (c) Only (ii) (d) None of these
= 10 × 22 = 40 pA UPPSC ITI Principal/Asstt. Director-09.01.2022
405. In a forward biased pn junction diode, the Ans. (c) : Zener diode and Avalanche diode both works
on reverse bias while Si p-n junction diode works only
sequence of events that best describes the
on forward bias.
mechanism of current flow is
Reverse breakdown voltage for Zener diode is less than
(a) Injection, and subsequent diffusion and 5V but for Avalanche more than 5V.
recombination of minority carriers Note: Zener diode is highly doped while Avalanche is
(b) Injection, and subsequent drift and generation lightly doped.
of minority carriers 410. Thermionic emission occurs in
(c) Extraction, and subsequent diffusion and (a) Transistors (b) Ferrite cores
generation of minority carriers (c) Copper conductors (d) Vacuum tubes
(d) Extraction, and subsequent drift and Nagaland PSC CTSE (Diploma)-2018, Paper-I
recombination of minority carriers Ans. (d) : A thermionic emission is the emission of
Nagaland PSC CTSE (Diploma)-2017, Paper-I electrons from a heated metal (Cathode) as the
Ans. (a) : In a forward biased pn junction diode, the temperature increases, the surface electrons gain energy.
sequence of events that best describes the mechanism of Thermionic emission occurs in vacuum tube.
current flow is injection, and diffusion, a third 411. If the reverse voltage across a diode gets
phenomenon which occurs in semiconductors is called increased beyond a safe value, due to higher___
recombination that results from the collision of an and due to a higher ______ of minority charge
electrons with a hole. carriers colliding with atoms, a number of
covalent bonds get broken.
406. Gunn domains start near (a) repel force, potential energy
(a) Cathode region (b) Anode region (b) electrostatic force, kinetic energy
(c) Middle of the diode (d) Start of the diode (c) repel force, kinetic energy
Mizoram PSC Jr. Grade -2018, Paper-III (d) electrostatic force, potential energy
Ans. (a) : The Gunn domain starts generating after a DMRC AM S&T-2020
distance of around 1.5 m from the cathode region and Ans. (b) : If the reverse voltage across a diode gets
hence negative power could not be generated from this increased beyond a safe value, due to higher
region of the cathode end. electrostatic force and due to a higher kinetic energy of
407. Gunn effects occurs in semiconductors only minority charge carriers colliding with atoms, a number
when doped with of covalent bonds get broken.

5. A reverse-biased diode placed in parallel with
(iii) Bipolar Junction Transistors the base-emitter junction makes the circuit
(BJTs) insensitive to variations in ______ with changes
in temperature.
1. The phenomenon known as 'Early effect' in a
(a) VBE (b) ICO
bipolar transistor refers to a reduction of the
effective base-width caused by (c) β (d) α
(a) Electron-hole recombination at the base APPSC POLY. LECT. 14.03.2020
(b) The reverse-biasing of the base-collector Ans. (b) : If the diode and the transistor are of the same
junction type and material the reverse saturation current I0 of the
(c) The forward-biasing of the emitter-base diode will increase with temperature at the same rate as
junction the transistor current ICO.
(d) The early removal of stored base charge Q Reverse bias VBE = 0.2Volt
during saturation to cut off switching
TRANGEDCO AE-2018
IES-2014
Mizoram PSC IOLM 2010, Paper- II
GATE 2006
Ans. (b) : In BJT on base to collector region apply
reverse bias mode then base to collector junction is
increased and effective base width decreases. The
phenomenon known as early effect.
2. Darlington pair connection is _______
combination.
(a) CC-CB (b) CE-CE
(c) CE-CC (d) CC-CC I B = I − I0
DFCCIL Executive S&T-17.04.2016, Shift-II IC = β IB + (1 + β ) ICO = Iβ − βIo + (1 + β ) ICO
Ans. (d) : Darlington pair- If β >> 1 and
Used to two transistor. If I0 of Diode and ICO of transistor track each other over
It is high current gain the desired temperature, range, then IC remains
It's high input impedance and output impedance is low essentially constant so that the circuit becomes
Cascode = CE - CB incentive to variation in ICO with change in temperature.
Darlington pair = CC- CC
6. A silicon NPN transistor has a base width of
Cascade = CC - CE
500°A. The electron diffusivity in the base is 25
3. At room temperature for a transistor, if Ic = 1.3 cm2/sec. The fT of the transistor is :
mA, its mutual conductance is typically
(a) 100.24 GHz (b) 318.31 GHz
.
(c) 524.12 GHz (d) 220.56 GHz
(a) 100 mA/V (b) 50 mA/V
(c) 1 mA/V (d) 10 mA/V APPSC POLY. LECT. 14.03.2020
UPRVUNL AE -19.07.2021, Shift-II W2
Ans. (b) : Base transit time τ =
I 2D B
Ans. (b) : Mutual conductance = C
VT Where, W = effective width of base
DB = diffusivity in the base
1.3 ×10−3
= Given, W = 500ºA = 500 × 10–8 cm
26 ×10−3 DB =25 cm2/sec
= 50 mA/V.
500 × 10−8 × 500 × 10−8
4. In a common-emitter configuration, for the τ=
maximum output voltage swing, the collector of 2 × 25
−13
the BJT should be biased at : τ = 5 × 10 sec
(a) 0.25 VCC (b) 0.35 VCC 1
(c) 0.45 VCC (d) 0.5 VCC fT =
2πτ
APPSC POLY. LECT. 14.03.2020 1
Ans. (d) : In a common-emitter configuration for the =
2 × 3.14 × 5 ×10−13
maximum output voltage swing, the collector of the
= 318.31GHz
BJT should be biased at 0.5 VCC.
7. Ans. (a) : Ebers-Moll model is one of classical module
of BJT for small signals. This model is based on
interacting diode junction and is applicable to any
transistor operating modes.
10. In a p-n-p transistor biased in the active region,
in the n-type base, holes
(a) drift
What does the above figure represents (b) diffuse and recombine
(a) Output configuration of common emitter (c) experience avalanche multiplication
(b) Input configuration of common base (d) are injected from collector
(c) Output configuration of common base GPSC Asstt. Prof. 11.04.2017
(d) Input configuration of common emitter TRB Poly. Lect.-2012
UKPSC Assistant Radio Officer Screening Exam-2011
DMRC AM S&T-2020
KVS TGT (WE)- 2017 Ans. (b) : In a p-n-p transistor.
Ans. (c) : Above figure represent the output
characteristic of common base configuration.
Output characteristics of common emitter
configuration-
Used material in p-type & n- type-
p-type → Al, B, Ga, In
& n-type → P, As, Sb etc.
Holes drifting into the base from p-type emitter are
minority carrier in the base (n-type) they diffuse &
recombined into the collector region.
So, Diffusion of holes from high concentration to low
Note:- Output characteristic of the common collector concentration.
configuration is same as the common emitter 11. The early effect in bipolar junction transistor is
configuration. caused by
8. In the common base configuration the collector (a) fast turn-off
current is given by (b) fast turn-on
α 1 (c) large emitter to base forward bias
(a) IC = IB + ICBO (d) large collector to base reverse bias
1+ α 1− α Mizoram PSC IOLM-2018, Paper-I
α 1 Trangedco AE-2018
(b) IC = IB + ICBO Nagaland PSC CTSE (Degree)-2017, Paper-I
1− α 1+ α
α 1 IES-2014
(c) IC = IB + ICBO
1+ α 1+ α GATE-1995 & 1999
α 1 Ans. (d)
(d) IC = IB + ICBO • A large collector base reverse bias is the reason
1− α 1− α
behind early effect manifested by BJTs.
DMRC AM S&T-2020
• The depletion layer penetrates more in to the base as
Ans. (d) : In the common base configuration the the base is lightly doped increasing the
collector current. concentration gradient in the base.
IC = βIB + ICEO • As reverse biasing of the collector to base junction
 α   α  increases, depletion region penetrates more into the
IC =   I B + ICEO Q β=  base, this reduces the effective base width.
 1 − α   1 − α  • The reduction in base width cause less
 α  recombination of carriers in the base region.
IC =   I B + (1 + β ) ICBO • This is known as an early effect.
 1− α 
 α   1   1 
IC =   IB +   ICBO Q1 + β = γ = 
 1− α   1− α   1− α 
9. The Ebers-Moll model is applicable to
(a) Bipolar Junction Transistor
(b) NMOS Transistor
(c) Unipolar Junction Transistor
(d) Junction FET 12. A BJT is said to be operating in the saturation
GPSC Asstt. Prof. 11.04.2017 Region if
Nagaland PSC CTSE (Degree) -2015, Paper I (a) Both the Junctions are reverse biased.
TSPSC Manager (Engg.) - 2015 (b) Base-Emitter Junction is reverse biased and
Mizoram PSC IOLM-2010, Paper-II Base-Collector Junction is forward biased.
(c) Base-Emitter Junction is forward biased and Ans. (a) : The emitter is heavily doped so that it an
Base-Collector Junction is reverse-biased. inject a large number of charge carriers in to the base.
(d) Both the junctions are forward biased. The base is lightly doped and very thin; It passes most
TNTRB AE– 2017 of the emitter injected charge carriers to the collector.
Kerala PSC Lecturer (NCA) 04.07.2017 The collector is moderately doped. Hence doping
CGPSC SO 14.02.2016 concentration is
NPCIL-2015
Mizoram PSC IOLM-2010, Paper-I Emitter (E) > Collector (C) > Base (B)
GATE-1995 15. In a bipolar transistor at room temperature if
IES-1995, 1993 the emitter current is doubled the voltage
Ans. (d) : across its base-emitter junction is
Mode JE JC Application (a) Doubles
Saturation Forward Forward 'ON' Switch (b) Halves
bias bias (c) Increases by about 20 mV
Cut-off Reverse Reverse 'OFF' (d) Decreases by about 20 mV
bias bias Switch Nagaland PSC CTSE (Degree)-2017, Paper-I
Active Forward Reverse Amplifier KVS TGT (WE)- 2017
bias bias GATE-1997
Reverse Reverse Forward Attenuator. Ans. (c) : Given, I2 = 2I1,
Active bias bias
13. Consider the following statements S1 and S2 Q I = I E0 e VBE / ηVT − 1
S1 : The β of a bipolar transistor reduces if the base Let for transistor x =1
width is increased. V / ηV
I1 I E0  e BE1 T − 1 
S2 : The β of a bipolar transistor increases if the =  
doping concentration in the base is increased. I 2 I E0  e VBE 2 / ηVT − 1 
Which one of the following is correct V / ηV
1 e BE1 T − 1
(a) S1 is FALSE and S2 is TRUE = VBE 2 / ηVT
(b) S1 is TRUE and S2 is TRUE 2 e −1
(c) S1 is FALSE and S2 is FALSE VBE1 / ηVT
1 e
(d) S1 is TRUE and S2 is FALSE ≈
Punjab PSC Poly. Lect. 20.08.2017 2 eVBE2 / ηVT
IES-2014 1 V −V
= e BE1 BE2 ηVT
/
TNPSC AE-2013
Mizoram PSC IOLM-2010, Paper-II 2
GATE-2004 VBE1 − VBE 2
2
− 0.693 =
W WD N VT
Ans. (d) : α = 1− B2 − B E B –3
2L B L E D B N E Where, V T = 26 ×10 V
α LE DB N E VBE 2 − VBE1 = 0.693 × 26 × 10−3 V = 18.018
Now, β = ≈
1− α WB D E N B ≅ 18 mV
As β & WB are inversely proportional, therefore if β ∴ VBE increases by about 20 mV.
increases, WB decreases. 16. If for a silicon npn transistor, the base-to-
WB = Base width emitter voltage (VBE) is 0.7 V and the collector-
NB = Doping in base region to-base voltage (VCB) is 0.2 V, then the
NE = Doping in Emitter region transistor is operating in the
LE = Diffusion length of minority carriers in base (a) normal active mode (b) saturation mode
DB = Diffusion coefficient of the carrier in base (c) inverse active mode (d) cutoff mode
DE = Diffusion coefficient of the carrier in emitter Mizoram PSC Jr. Grade- 2018, Paper-II
β & NB are inversely proportional, hence if the doping ISRO Scientist Engg.-2013
concentration in base increases, then β should decrease. GATE-2004
14. In an ideal junction transistor, the impurity Ans. (a) : Given, V CB = 0.2V, V BE = 0.7V
concentration in the emitter (E), base (B) and Q VCE = VCB + VBE
collector (C) are such that VCE = 0.2 + 0.7 = 0.9 Volt
(a) E > C > B (b) B > C > E VCE (Saturation) < VCE ⇒ Active region
(c) C > E > B (d) C = E = B VCE(Saturation)' for silicon transistor is 0.3 volts.
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I So, Transistor operating in normal active region.
CGPSC SO 14.02.2016
Other method-
RRB SSE 01.09.2015, Shift-III
NPCIL-2015 VBE = 0.7 → Forward bias
IES-1993 V CB = 0.2 → Reverse bias
So, Transistor is operating in normal active region. 19. For faithful amplification by a transistor
circuit, the value of VBE should…………for a
silicon transistor?
(a) Be zero
(b) Be 0.01 V
(c) Not fall below 0.7 V
(d) Be between 0 V and 0.1 V
Mizoram PSC IOLM -2018, Paper-I
Nagaland PSC (CTSE) Diploma-2017, Paper II
Ans. (c) : For faithful amplification by transistor circuit,
17. Bipolar transistor satisfies the relation the VBE should not fall below 0.7V for silicon transistor
because for silicon, knee voltage is equal to 0.7V & for
α
(a) β = α (b) β = Ge 0.3V.
1− α 20. The leakage current in a silicon transistor is
1 about……….the leakage current in germanium
(c) β = (d) none of these
α transistor
APGENCO AE- 23.04.2017 (a) One hundredth (b) One tenth
TNPSC AE-2013, 2008 (c) One thousandth (d) One millionth
Ans. (b) : In common emitter configuration Nagaland PSC (CTSE) Diploma-2017, Paper II
I Ans. (c) : Leakage current in the silicon semiconductor
β = C ...........(i) is in the order of nano amperes. In Ge it is in the order
IB
of micro amperes.
and common base configuration,
Let for Si, Ig1 = 10−9 = IS .....(i)
IC
α= for G e , Ig2 = 10−6 = IG ........(ii)
IE
I C = αI E ....(ii) From equation (i) and (ii)
From equation (i) and (ii), Ig1 IS 10 −9
= =
αI E Ig2 IG 10 −6
β=
IB 1
IS = × IG
αI E 1000
= ( B E C)
Q I = I − I
I E − IC 21. Base thickness of modern bipolar transistors
αI E can be as small as
= (a) 1 µm (b) 0.1 µm
(1 − α ) I E
(c) 10 nm (d) 10 A0
α GPSC Asstt. Prof. 11.04.2017
β=
1− α Ans. (c) : BJT has three section emitter, base and
Other form, Collector. Base thickness of modern bipolar transistors
can be as small as 10 nm. The doping of base is just one
β tenth of that of collector and extremely thin as
α=
1+ β compared to the emitter.
Generally base thickness of modern bipolar junction
γ = 1+ β
transistor can be 10 nm.
18. For emitter-coupled logic, the switching speed
is very high because
(a) Negative logic, is used
(b) The transistors are not saturated when
conducting
(c) Emitter-coupled transistors are used
(d) Multi-emitter transistors are used
ISRO Scientist Engg.-2006 Note- It is a current controlled device and non linear,
Ans. (b) : For emitter-coupled logic (ECL), the active elements.
switching speed is very high because the transistors are Doping Sequence →Emitter > Collector > Base
not saturated when conducting. Width Sequence → Collector > Emitter > Base.
ECL is a BJT logic family. Its high-speed operation by 22. Consider an n-p-n transistor in forward active
employing a relatively small voltage swing and region. The collector current increases as we
preventing the transistors from entering the saturation increase collector emitter voltage keeping the
region. base current constant. This is due to
(a) Tunneling effect (b) Avalanche effect 26. Which of the following h parameters relation is
(c) Early effect (d) Miller effect not correct
UPPCL AE- 31.12.2018 (a) hic = hie (b) hrc = 1 + hrc
Ans. (c) : The early effect is the variation in the (c) hfc = –(1+hfe) (d) hoc = hoe
effective width of the base in a bipolar junction UJVNL AE-2016
transistor due to variation in applied base to collector Ans. (b) : The following relations can be built between
voltage. The collector current increase as collector h parameters of CC & CE.
emitter voltage is increased by keeping base current hic = hie
constant. hfc = –(1+hfe)
23. The current ICBO flows in the hoc= hoe
(a) Emitter and base leads hrc = 1
(b) Collector and base leads 27. In a uniformly doped BJT, assume that NE, NB
(c) Emitter and collector leads and NC are the emitter, base and collector
(d) None of these dopings in atoms/cm3, respectively. If the
UJVNL AE-2016 emitter injection efficiency of the BJT is close
Ans. (b) : The current ICBO is the leakage current which to unity, which one of the following conditions
flow through the collector to base. is TRUE?
(a) NE=NB=NC
(b) NE>>NB and NB>NC
(c) NE=NB and NB<NC
(d) NE<NB<NC
GATE-2010
BPSC Polytechnic Lecturer - 2014
Ans. (b)
Note-
1. IC = α IE + ICB0
2. IC = βI B + ICEO
ICBO For BJT, we know NE >> NC >>NB which is non-
3. ICEO =
1− α uniformly doped BJT.
4. ICEO = (1 + β) ICBO For uniformly doped BJT, NE>>NB and NB >>NC
28. In a BJT amplifier with the introduction of
α β
5. β = , α= feedback, the input impedance is reduced,
1− α 1+ β output impedance is increased, bandwidth is
1 increased but distortion reduced. The feedback
6. γ = 1 + β = type is
1− α (a) Voltage series (b) Current series
24. In saturation region in an N-P-N transistor (c) Voltage shunt (d) Current shunt
(a) VCB is –ve and VBE + ve UKPSC Assistant Radio Officer Screening Exam.-2011
(b) VCB is + ve and VBE – ve Ans. (d) : As current shunt configuration provide
(c) VCB is + ve and VBE + ve current sampling at the output and current mixing in the
(d) VCB is –ve and VBE – ve input of the amplifier that's why output impedance
UJVNL AE-2016 increase and input impedance reduce by the factor of (1
Ans. (c) : In saturation region of N-P-N transistor + Aβ).
VBE > 0 and VCB > 0. A transistor is said to be in In the current shunt feedback circuit a fraction of the
saturation region emitter and collector is short circuit. In output voltage is applied in series with the input voltage
other word VB should be greater than VE. through the feedback circuit this is also known as series
driven shunt feedback a series –parallel circuit
25. The Darlington pair is mainly used for
29. A bootstrap generally incorporates
(a) Impedance matching
(a) CB configuration (b) CE configuration
(b) Wideband voltage amplification
(c) Emitter follower (d) None of these
(c) Power amplification UKPSC Assistant Radio Officer Screening Exam.-2011
(d) Reducing distortion
Ans. (c) : Emitter follower or common collector circuit
UJVNL AE-2016 is sometime called bootstrap as overall voltage gain of
Ans. (a) : The darlington pair is mainly used for emitter follower circuit which approximately 1, thus it
impedance matching. The darlington pair transistor is a will resist the miller effect. This is mostly used as a last
very useful circuit in many application. It provide high stage amplifier in signal generator circuits. The
current gain. It also has high input impedance and low important features of Emitter follower has high input
output impedance. impedance. It has low output Impedance

30. The forward amplification factor of a 34.
The main use of emitter follower configuration
transistor corresponds to is as
(a) the power gain of CE amplifier (a) Impedance matching device
(b) the current gain of CB amplifier (b) Follower of base signal
(c) the voltage gain of CC amplifier (c) Low input impedance circuit
(d) the voltage gain of CE amplifier (d) Power amplifier
TNPSC AE-2013 MPPSC Forest Service Exam.-2014
Ans. (b) : The forward amplification factor of a Ans. (a) : Common collector configuration is also
transistor corresponds to the current gain of common known as emitter follower or voltage follower. It
base amplifier. provides high input impedance and low output
The forward amplification factor. impedance.
∆Ι Hence it is mostly used for impedance matching.
α= C 35. For the emitter bias, the voltage across the
∆Ι E
emitter resistor is the same as the voltage
31. Which of the following methods used for between the emitter and the
biasing a BJT in integrated circuits is (a) Base (b) Collector
considered independent of transistor beta? (c) Emitter (d) Ground
(a) Fixed biasing Nagaland PSC CTSE (Degree)-2016, Paper-II
(b) Voltage divider biasing Ans. (d) : For the emitter bias, the voltage across the
(c) Collector feedback biasing emitter resistor is the same as the voltage between the
(d) Base bias with collector feedback emitter and Ground.
TNPSC AE-2008
Ans. (b) : Voltage divider biasing method is used for
biasing a BJT in integrated circuit is considered
independent of transistor beta ( β ) .
32. For a given emitter current the collector
current in a transistor can be increased by :
(a) Reducing the recombination rate in the base
junction
36. Voltage-divider biasing is noted for its
(b) Increasing width of the base region
(a) Unstable collector voltage
(c) Reducing the minority carrier mobility in the
base region (b) Varying emitter current
(d) Doping the emitter region lightly (c) Large base current
MPPSC Forest Service Exam.-2014 (d) Stable Q point
Nagaland PSC CTSE (Degree)-2016, Paper-II
Ans. (a) : As the collector current is increased the
emitter release more number of electrons. This cause Ans. (d) : Voltage-divider biasing is noted for its Stable
more collision of electron at collector. This happens in Q point. Stability factor in voltage divider biased is
cycle and produces such a condition in which improved with respect to fixed bias.
temperature is further increase. 37. Base bias is associated with
33. The maximum junction temperature of a (a) Amplifiers (b) Switching circuits
transistor is 1500C and the ambient (c) Stable Q point (d) All of the above
temperature is 250C. Given the total thermal Nagaland PSC CTSE (Degree)-2016, Paper-II
impedance as 10C/watt, the maximum power Ans. (b) : In fixed bias circuit, the transistor base
dissipation will be current (IB) remains constant for a given value of VCC,
(a) 1/125 watt (b) 125 watt and therefore the transistor operating point must also
(c) 175 watt (d) 1/75 watt remain fixed.
Ans. (b) : Given,
Maximum junction temperature Tj = 150ºC
Ambient temperature (Ta) = 25ºC
Total thermal impedance Rth(j-a) = 1ºC/watt.
So, Maximum power dissipation,
Tj − Ta
Ploss = 38. If the emitter resistance is reduced by one-half
R th ( j− a) in a voltage-divider Biasing circuit, the
collector current will
150 − 25
= (a) Double (b) Drop in half
1 (c) Remain the same (d) Increased
Ploss = 125 watt. Nagaland PSC CTSE (Degree)-2016, Paper-II
Ans. (a) : If the emitter resistance is reduced by one- Ans. (c) : The voltage gain of CC configuration-
half in a voltage divider effect, the collector current will
double from its nominal value. V 1
A V = out =
39. As the temperature increases the current gain V r'
in
1+ e
(a) Decreases re
(b) Remain the same
1 9
(c) Increases = = = 0.9
(d) Can be any of the above 10 10
1+
KVS TGT (WE)- 2017 90
Nagaland PSC CTSE (Degree)-2016, Paper-II 44. Thermal runway of a transistor occurs when
Ans. (c) : As the temperature increases the value of (a) Heat dissipation from transistor is excessive
current gain increases. (b) Transistor joints melt due to high temperature
T ↑⇒ ICO ↑⇒ IC ↑ (c) There is excessive leakage current due
temperature rise
I
Current gain ( β ) = C (d) None of the above
IB Nagaland PSC CTSE (Degree)-2016, Paper-II
I ↑ Ans. (c) : Thermal runway of a transistor occurs when
β ↑= C there is excessive leakage current due to temperature
IB
rise.
40. The circuit with a fixed emitter current is
called IC = βI B + (1 + β ) ICBO
(a) Base bias (b) Emitter bias
(c) Transistor bias (d) Two-supply bias
Ans. (b) : The circuit with a fixed emitter current is
called emitter biasing. 45. Storage time of a transistor is the time taken
for the collector curves to fall to
∆I C
β= ( fixed I E current ) (a) 90% from maximum value
∆I B (b) 10% from maximum value
41. When the current gain increases from 50 to 300 (c) 10% to 90% from maximum value
in an emitter-biased circuit, the collector (d) 50% from maximum value
current Nagaland PSC CTSE (Degree)-2016, Paper-II
(a) Remain almost the same Ans. (c) : Storage time (ts) - The time interval between
(b) Decreases by a factor of 6 trailing edge of the input pulse to the 90% of the
(c) Increases by a factor of 6 maximum value of the output, is called as the storage
(d) Is zero time.
Ans. (c) : As current gain is directly proportional to
collector current, So, if gain increased 50 to 300, Ic also
increased by 6 times.
42. When testing an npn transistor using an
ohmmeter, the collector-emitter resistance will
be low when
(a) The collector is positive in respect to the
emitter
(b) The emitter is positive in respect to the
collector
(c) The transistor is normal Time delay (td)- The time taken by the collector
(d) The transistor is defective current to reach from its initial value to 10% of its final
Nagaland PSC CTSE (Degree)-2016, Paper-II value is called as the time delay.
Ans. (d) : The output resistance of npn biased circuit, is Rise time (tr)- The time taken for the collector current
typically very high, which is connected across collector to reach from 10% of its initial value to 90% of its final
emitter. If its very low, indicate, transistor has some value is called as the rise time.
defects on it. TON = τd + t r
43. If an emitter follower has re ' =10Ω and Fall time (tf)- The time taken for the collector current
re=90Ω, the voltage gain is approximately to reach from 90% of its maximum value to 10% of its
(a) 0 (b) 0.5 initial value is called as the 'Fall Time'.
(c) 0.9 (d) 1 Pulse width (W)- The output pulse measured between
Nagaland PSC CTSE (Degree)-2016, Paper-II two 50% pulse of rising and falling wave form.
46. The element that has the biggest size in a 51. The dc current gain (β) of BJT is 50. Assuming
transistor is………… that the emitter injection efficiency is 0.995, the
(a) collector (b) base base transport factor is
(c) emitter (d) collector-base-junction (a) 0.980 (b) 0.985
Nagaland PSC CTSE (Diploma)-2017, Paper-I (c) 0.990 (d) 0.995
Ans. (a) : Nagaland PSC CTSE (Degree)-2017, Paper-I
Ans. (b) : Given, β = 50, emitter injection efficiency
(R)=0.995 relation between CB, CE gain factor-
Emitter is heavily doped as comparison to other regions. β
α =
Collector has largest area than base and emitter. 1+ β
47. The collector of a transistor is…………doped 50
α =
(a) heavily (b) moderately 51
(c) lightly (d) none of the above α = 0.98039
Nagaland PSC CTSE (Diploma)-2017, Paper-I Q Base transport factor,
Ans. (b) : Collector–This section is moderately doped α 0.98
and has largest area than other two regions because it b= =
collects the charge carries from emitter and base. R 0.995
48. A transistor is a…………operated device b = 0.985
(a) current 52. The main current crossing the collector
(b) voltage junction in a normally biased NPN transistor is
(c) both voltage and current (a) a diffusion current
(b) a drift current
(c) a hole current
Nagaland PSC CTSE (Diploma)-2017, Paper-I (d) equal to the base current
Ans. (a) : A transistor is 3 layer, 3 terminal, 2-junction Nagaland PSC CTSE (Diploma)-2018, Paper-I
semiconductor device. Ans. (b) : Drift current is the electric current caused by
In transistor current flows due to both majority as well particles getting pulled by an electric field. The main
as minority carrier that's why called a bipolar device. current crossing the collector junction in a normally
It is a current controlled device. biased NPN transistor is a drift current.
49. At the base-emitter junctions of a transistor, 53. Emitter efficiency of a transistor depends on
one finds………….. doping in
(a) a reverse bias (a) Emitter region
(b) a wide depletion layer (b) Collector region
(c) low resistance (c) Base region
(d) none of the above (d) Does not depend on doing
Nagaland PSC CTSE (Diploma)-2018, Paper-I Nagaland PSC CTSE (Diploma)-2018, Paper-I
Nagaland PSC CTSE (Diploma)-2017, Paper-I Ans. (a) : Emitter efficiency depends on the
Ans. (c) : conductivity ratio of emitter and base. That's is way
emitter is heavily doped as compare to base. At high
currents, there is high concentration of injected carriers
in base region, thereby increasing its conductivity.
54. A biasing circuit has a stability factor of 40. if
due to temperature change, ICO changes by 1
The base-emitter junction is forward biased and the base µΑ. The change in IC will be
collector junction is reverse bias. At base emitter (a) 20 µA (b) 40 µA
junctions of a transistor, one finds low resistance. (c) 80 µA (d) none of these
50. Most of the majority carriers from the Mizoram PSC Jr. Grade -2018, Paper-II
emitter………… Mizoram PSC Jr. Grade-2015, Paper-II
(a) recombine in the base Ans. (b) : Given,
(b) recombine in the emitter S = 40 ∂ICO = 1 µA
(c) pass through the base region to the collector ∂I
(d) none of the above S= C
∂ICO
Ans. (c) : The bipolar junction transistor consists of two ∂ I C = 40 × 1 = 40µA
back-to-back P-N junctions in a single piece of a 55. For a common-base BJT configuration having
semiconductor crystal. These two junctions give rise to IC = 5 mA and α = 0.97, an AC signal of 5 mV
three regions called emitter, base and collector. is applied between the base and emitter
Most of the majority carrier from the emitter pass terminals. What is the value of output
through the base region to the collector. impedance and current gain?
(a) 0, 0.97 (b) ∞, 0.97 60. The leakage current in CE configuration may
(c) ∞, – 0.97 (d) 0, –0.97 be around
Mizoram PSC Jr. Grade -2018, Paper-II (a) Few nanoampers
Ans. (b) : Given value, (b) Few microampers
Current gain α = 0.97 (c) Few hundred microampers
(d) Few milliamperes
VBE = 5mV
In ideal case for common base transistor.
Ans. (c) : The leakage current in common emitter
Output impedance = ∞ configuration is very small. It is around few hundred
And for practically output impedance in common base micro amperes.
transistor = very high
Therefore, according to question, 61. Consider a common-emitter current gain of β =
150 and a base current of IB = 15µA. If the
Current gain ( α ) = 0.97 transistor is biased in the forward active mode,
Output impedance ( Z0 ) = ∞ the collector and emitter current will be
(a) 2.25 mA and 2.27 mA
56. The current gain of BJT is (b) 3.25 mA and 2.27 mA
(a) gmr0 (b) gm/r0
(c) 2.25 mA and 1.37 mA
(c) gmrπ (d) gm/rπ (d) 3.25 mA and 1.37 mA
Mizoram PSC Jr. Grade -2018, Paper-II IES-2019
Ans. (c) : The current gain of a BJT is gmrπ. Ans. (a) : Given that,
57. As compared to the unipolar device, the bipolar IB = 15µA, β = 150
device has
I
(a) High noise margin β= C
(b) Low transconductance IB
(c) Low packing Density IC
(d) None 150 =
15 ×10−6
IC = 2.25mA
Ans. (a) :
Bipolar device Unipolar device ∴ IE = IB +IC
1. low on –state High – on – state = (0.015 + 2.25)
voltage drop voltage drop I E = 2.265mA
2 . High switching power loss low switching power
loss IE  2.27mA
3 current controlled device voltage controlled 62. The hFE values in the specification sheet of a
device. transistor are hFE(max) = 225 and hFE(min) = 64.
4. High noise margin Low noise margin as What value of hFE is to be adopted in practice?
compare to bipolar (a) 64 (b) 100
device. (c) 120 (d) 225
58. The value of VBE(sat) in pnp Ge transistor IES-2018
typically equals
Ans. (c) : hFE of a transistor is the current gain or
(a) -0.1 Volt (b) –0.3 Volt amplification factor of a transistor.
(c) –0.8 Volt (d) +0.8 Volt In designing of a biasing network, the practical value of
RPSC Vice Principal ITI-2016 h is taken as the geometric mean of h
FE FE (max) and
Ans. (b) : VBEsat transistor typically value- hFE(min).
hFE = h FE(max) × h FE(min)
Type VBE
NPN,Si + 0.7 = 225 × 64
PNP,Si − 0.7 = 14, 400 , h FE = 120
NPN,Ge + 0.3 63. A transistor is connected in CE configuration
PNP,Ge − 0.3 with VCC = 10V. The voltage drop across the
600Ω resistor in the collector circuit is 0.6V. If
59. Transistor is usually encapsulated in
(a) graphite powder (b) enamel paint α = 0.98, the base current is nearly
(c) epoxy resin (d) Any of these (a) 6.12 mA (b) 2.08 mA
RPSC Vice Principal ITI-2016 (c) 0.98 mA (d) 0.02 mA
Ans. (c) : Transistor is usually encapsulated in epoxy IES-2018
resin because in order to prevent its fundamental Ans. (d) : Given - α = 0.98, RC = 600 Ω,
properties. Voltage drop across RC = 0.6 V
α 0.98 98 66. The leakage current in an NPN transistor is
∴ β= = = = 49 due to the flow of:
1 − α 1 − 0.98 2
(a) Holes from base to emitter
0.6 (b) Electrons from collector to base
∴ IC = = 1mA
600 (c) Holes from collector to base
(d) Minority carriers from emitter to collector
IES-2016
Ans. (c) : The leakage current in an NPN transistor is
due to the flow of holes from collector to base.
When the supply at emitter-base junction is open-
circuited, there is only reverse biasing in the base-
collector junction.
VCE is obtained by applying KVL from VCC to emitter Therefore, this sets up a small amount of current called
ground as- the leakage current.
10–0.6 –VCE = 0 67. In Early effect:
VCE = 9.4V (a) Increase in magnitude of Collector voltage
VCE > VCE(sat), the transistor is working in active mode increases space charge width at the input
So, IC = βIB junction of a BJT
I 1 (b) Increase in magnitude of Emitter-Base
IB = C = = 0.02 mA voltage increases space charge width of
β 49 output junction of a BJT
64. In a transistor, the base current and collector (c) Increase in magnitude of Collector voltage
current are, respectively, 60 µA and 1.75 mA. increases space charge width of output
The value if α is nearly junction of a BJT
(a) 0.91 (b) 0.97 (d) Decrease in magnitude of Emitter Base
(c) 1.3 (d) 1.7 voltage increase space charge width of output
junction of a BJT
IES-2017
IES-2019, 2016, 2013
Ans. (b) : Given, IB = 60µA = 0.06 mA Ans. (c) : When increase in magnitude of collector
and IC = 1.75 mA voltage increases space charge width of output Junction
∴ IE = IC + IB = 1.75 + 0.06 = 1.81mA of a BJT this phenomenon is known as the Early effect.
I 1.75 A greater reverse bias across the collector-base junction
∴ α= C = = 0.9668 increases the collector-base depletion width, thereby
I E 1.81
decreasing the width of charge carrier portion of the
α ≈ 0.97 base.
65. The n-p-n transistor made of silicon has a DC 68. The product of emitter efficiency (γ) and
base bias voltage 15 V and an input base transport factor (β*) for a BJT is equal to:
resistor 150 KΩ. Then value of the base (a) small signal current gain
current into the transistor is (b) High frequency current gain
(a) 0.953µA (b) 9.53µA (c) Power loss in the BJT
(d) Large-signal current gain
(c) 95.3µA (d) 953µA
IES-2016
IES-2017
Ans. (d) : In BJT, The product of emitter efficiency (γ)
Ans. (c) : Given, VB = 15V, RB = 150kΩ
and base transport factor (β *) is defined as:
α = β* × γ
α = large–signal current gain
69. Consider the following statements regarding an
N-P-N Bipolar Junction Transistor:
1. Emitter diode is forward biased and collector
Applying KVL from VB to Emitter grounded- diode is reverse biased
VB – IBRB–VBE = 0 2. Emitter has many free electrons
V − VBE 3. Free electrons are injected into base and pass
∴ IB = B through collector
RB
4. Depletion layers around junction J1 and J2 of
15 − 0.7 BJT are widened.
IB = [Also, VBE for a general npn silicon
150 × 103 Which of the above statements are correct?
transistor is 0.7V] (a) 1, 2 and 4 (b) 1, 3 and 4
(c) 2, 3 and 4 (d) 1, 2 and 3
∴ IB = 95.3µA
IES-2015
Ans. (d) : (c) low mobility of holes
(i) To operate the BJT in active mode it's emitter (d) higher mobility of electrons than the mobility
diode is forward bias and collector diode is of holes in p-n-p transistors
reverse biased. IES-2014
So, 1 is correct Ans. (d) : n-p-n transistor are preferred over p-n-p
(ii) Due to heavily doped, Number of free electrons transistor because high mobility of electron then the
are more. mobility of holes in p-n-p transistor.
(iii) When free electrons are injected in to base due to 74. What is the biasing condition of junctions in
narrow base width, some electrons recombine bipolar junction transistor to work as an
with holes in base and most electrons reached to amplifier?
collector region so (iii) is correct. (a) Reverse biased base to emitter junction and
(iv) Depletion layer around J1 is narrow and J2 is wide reverse biased base to collector junction
(due to biasing of emitter) (b) Forward biased base to emitter junction and
70. If an input signal ranges from 20µA – 40µA reverse biased base to collector junction
with an output signal ranging from 0.5 mA- 1.5 (c) Forward biased base to emitter junction and
forward biased base to collector junction
mA, what is the βa.c ?
(a) 0.05 (b) 20 (d) Reverse biased base to emitter junction and
forward biased base to collector junction
(c) 50 (d) 500
IES-2014
IES-2014
Ans. (c) : Given that, Ans. (b) : BJT works as amplifier (active mode), The
base-emitter Junction is forward biase and base-
I B2 = 40µA , I B1 = 20µA collector junction is reverse biased.
and IC2 = 1.5mA, IC1 = 0.5mA Mode E.B. C.B. Application
Junction Junction
∆I0 (IC2 − IC1 ) (1.5 − 0.5) × 10 −3
βac = = = Forward Forward Reverse Amplifier
∆Iin (IB2 − IB1 ) (40 − 20) × 10−6 Active bias bias
1000 Cut off Reverse Reverse OFF switch
βac = = 50 bias bias
20
Saturation Forward Forward ON switch
71. The best device for improving the switching bias bias
speeds of bipolar transistors is Reverse Reverse Forward Attenuator
(a) speed-up capacitor Active bias bias
(b) transistor with higher cut-off frequency 75. Which of the following are essentials of a
(c) clamping diode transistor biasing circuit?
(d) clamping diode with zero storage time 1. Proper zero signal collector current flow
IES-2014 2. VCE should not fall below 0.5V for
Ans. (d) : The best device for improving the switching Germanium and 1 V for Silicon
speed of bipolar transistor is a clamping diode with 3. Ensure stabilization of operating point
zero storage time. 4. Loading to the source
72. A BJT operates as a switch (a) 1, 2 and 3 only (b) 1, 2 and 4 only
(a) in the active region of transfer characteristics (c) 3 and 4 only (d) 1, 2, 3 and 4
(b) with no signal condition IES-2013
(c) under small signal conditions Ans. (a) : The biasing network associated with the
(d) under large signal conditions transistor should meet the following requirements.
IES-2014 • It should insure proper zero signal collector current.
Ans. (d) : BJT operates as a switch under cut off region
• It should insure that VCE does not fall below 0.5V for
and saturation region or under large signal condition, Ge transistor and 1V for silicon transistor at any instant.
the Application of BJT and biasing conditions are • It should insure the stabilization of operating point.
show below-
76. When a transistor is saturated,
Mode JEB JCB Application
(a) the emitter potential is more than the base-
Forward Active F.B. R.B Amplifier collector potential
Cut off R.B. R.B OFF switch (b) the collector potential is more than the base-
Saturation F.B. F.B ON switch emitter potential
Reverse Active R.B. F.B Attenuator (c) the base potential is more than the emitter-
73. n-p-n transistors are preferred over p-n-p collector potential
transistors because they have (d) the base, emitter and collector are almost the
(a) high mobility of holes same potential
(b) high mobility of electrons IES-2013
Ans. (c) : In saturation condition of transistor, emitter- 2. VBE decreases with rise in temperature.
base and collector-base will be forward biased and base 3. hFE or β changes with change of temperature
potential becomes more than emitter and collector and replacement of the transistor.
potentials. 4. hFE or β changes with change in collector
So, saturation condition - ICsat < βI B supply voltage.
Which of these statements are correct?
77. If the α value of a transistor changes 0.5% (a) 1, 2 and 3 only (b) 1, 2 and 4 only
from its nominal value of 0.9, the percentage (c) 2, 3 and 4 only (d) 1, 2 3 and 4
change in β will be IES-2011
(a) 0% (b) 2.5% Ans. (a) : Reverse saturation current ICO depends on
(c) 5% (d) 7.5% temperature i.e. increasing in temperature, ICO increases
IES-2013 • VBE decreases with increasing in temperature.
Ans. (c) : Given, α = 0.9 • β depends on temperature or structure of transistor.
α 0.9 81. The collector and emitter current levels for a
β= = =9 transistor with common base dc current gain of
1 − α 1 − 0.9
0.99 and base current of 20 µA are respectively
0.9 × 0.5 0.45 (a) 2 mA and 1.98 mA (b) 1.98 µA and 2 mA
Change in ∆α = =
100 100 (c) 1.98 mA and 2 mA (d) 2 mA and 1.98 µA
= 4.5 × 10 −3 IES-2011
α ' = α + ∆α = 0.90 + 0.0045 Ans. (c) : Given that,
= 0.9045 α = 0.99, IB = 20µA
0.9045 I & I = ?
β' = = 9.4712 C E
1 − 0.9045 α 0.99
β '− β β= = = 99
% change in β = 1 − α 1 − 0.99
β Now IC = β×IB = 99×20×10–6
9.4712 − 9 0.4712 IC = 1.98mA
= = = 0.0523
9 9 and IE = IC + IB = (1.98+0.02) mA
≅ 5% IE = 2mA
78. The output impedance of a BJT under
common-collector configuration is 82. The p-type epitaxial layer grown over an n-
(a) low (b) high type substrate for fabricating a bipolar
(c) medium (d) very high transistor will function as
IES-2012 (a) The collector of a p-n-p transistor
(b) The base of an n-p-n transistor
Ans. (a) : Common collector configuration, also known
(c) The emitter of a p-n-p transistor
as emitter follower provides high input impedance and
low output impedance. In common collector (d) The collector contact for a p-n-p transistor
configuration, the collector terminal is common to both IES-2011
input and output terminals. Ans. (a) : A monolithic circuit in which a p-type
79. Diodes are used to compensate which of the epitaxial layer is grown into an n-type substrate which
following transistor circuit parameters? help in making p-type devices formed by suitable
1. ICO 2. VBE masking and diffusion and the fabricated transistor will
have a p-type emitter and collector and n-type base.
3. β
(a) 1 and 2 only (b) 2 and 3 only 83. In a junction transistor, recombination of
electrons and holes occurs in
(c) 1 and 3 only (d) 1, 2 and 3
(a) Base region only (b) Emitter region only
IES-2012
(c) Collector region only (d) All the 3 regions
Ans. (a) : There are two types of diode compensation- IES-2010
Diode compensation due to (i) VBE and (ii) ICO
Ans. (d) : Generally transistor operates in active mode
variation. β is the characteristic of transistor and it
that is obtained by forward biasing the EB junction and
depends on construction of transistor. Transistor
reverse biasing the CB Junction. Electron diffuse from
changes, β changes. the emitter into the base and hole diffuse from the base
80. For smooth and reliable operation of an into the emitter.
amplifier using BJT, it is necessary that the
circuit must be properly designed from the
point of view of bias stabilization, because
1. Reverse saturation current ICO increases with
rise in temperature.
84. The maximum power dissipation capacity of a (c) Reduced gain
transistor is 50 mW. If the collector emitter (d) No change in gain at all
voltage is 10V, what is the safe collector IES-2008
current that can be allowed through the Ans. (c) : Transistor operates in active mode for this,
transistor? emitter base junction will be forward bias and
(a) 5 mA (b) 2.5 mA collector-base junction will be reverse bias. Now if we
(c) 10 mA (d) 25 mA the terminals are interchanged then common emitter
IES-2009 configuration will change in to common collector
Ans. (b) : Given- configuration and gain will reduce.
Pdiss(max) = 50 mW 88. For an npn bipolar transistor, what is the main
VCE = 10V stream of current in the base region?
∴ maximum power dissipation (a) Drift of holes
Pdiss = VCE ×IC (b) Diffusion of holes
50mW = 10V ×IC (c) Drift of electrons
(d) Diffusion of electrons
50mW
IC = = 5mA IES-2007
10V Ans. (d) : In an n-p-n transistor base has more
For safe operation of the transistor IC < 5mA concentration of holes, emitter has low concentration of
As per the option it is 2.5mA. holes, so the main purpose of current in the base will be
85. What is the most noticeable effect of a small diffusion of electron because diffusion occurs due to
increase in temperature in the common emitter difference of concentration and goes from higher
connected BJT? concentration to lower concentration.
(a) Increase in ICBO 89. The widths of the base in a GaAs transistor and
(b) Increase in output resistance in a Si transistor (both n-p-n type) are equal.
(c) Decrease in forward current gain GaAs transistor works at higher frequency.
(d) Increase in forward current gain Which one of the following is the correct
IES-2008 statement?
1. The band gap of GaAs is higher than that of
Ans. (a) : The leakage current is most sensitive to Si.
temperature among the given parameters. One of the 2. The base transit time is lower in GaAs.
main reasons for the shifting of the operating point is
3. The negative differential mobility in GaAs
the change in temperature. This is the relation, the
favours operation at very high frequency.
current for 1ºC increase in temperature it increases by
7% and almost doubles for every 10ºC rise in 4. Si transistor works at higher frequency
compared to GaAs transistor
temperature.
(a) 1,2 and 3 (b) 1 and 3
IC = βI B + (β + 1)ICBO
(c) 1,3 and 4 (d) only 4
ICEO IES-2006
ICBO = = (1 − α ) ICEO
1+ β W2
Ans. (a) : We know θn = IC
86. For BJT, early voltage VA is 100V. In common 2D n
emitter configuration, quiescent VCE is 10V. Where,
What percentage change in quiescent IC would
occur, if early voltage VA is made ∞? W2
Transits time of base ( τf ) =
(a) 10% (b) 20% 2D n
(c) 5% (d) 0% In GaAs the base transit will be lower because GaAs
IES-2008 transistor work at higher frequency.
Ans. (d) : Given that, The negative differential mobility in GaAs favours
VA = 100V, VCE = 10V operation at very high frequency.
Q - point does not depends upon percentage change in 90. Which one of the following is the exact
quiescent IC because early voltage does not depend on expression for ICEO (i.e. collector to emitter
bias stabilization in a temperature. current with base open) in a junction
87. While using a bipolar junction transistor as an transistor?
amplifier, the collector and emitter terminals α
(a) α ⋅ ICBO (b) ⋅ ICBO
got interchanged mistakenly. Assuming that 1− α
the amplifier is a common emitter amplifier I
and the biasing is suitably adjusted, the (c) CBO (d) (1 − α)ICBO
1− α
interchange of terminals will result into which (Where ICBO is the collector to base current
one of the following? with emitter open, and α is the common base
(a) Zero gain current gain)
(b) Infinite gain IES-2005, 1993
Ans. (c) : We know that- Ans. (d) : The relation of collector current to the emitter
Where, IC = Collector current current at constant collector base voltage VCB and
ICEO = Collector to emitter current with base open Alpha (α) is a large current gain of a common base
IB = Base current configuration.
IC = βIB +ICEO ....(i) I
α = C ( α < 1)
and IC = αI E + ICBO IE
IC = α(IC + IB ) + ICBO {IE= IB + IC} Typical numerical value of α lies in the range of 0.90 to
IC = αIC + αIB + ICBO 0.995.
IC (1 − α ) = αI B + ICBO 94. The internal resistance of a current source used
in the model of BJT while analyzing a circuit
 α  ICBO using BJT is
IC =   IB + .....(ii)
1− α  (1 − α ) (a) Very high
(b) Very low
from equation (i) & (ii)
(c) Zero
ICBO (d) Of the order of a few mega-ohms
ICEO =
(1 − α ) IES-2003
Ans. (a) : The internal resistance of a current source is
91. Which of the following pairs is not correctly very high. An independent current source with zero
matched? current is identical to an ideal open current source is
(a) The typical temperature range over which completely.
Germanium transistors are operated :- 65ºC to
175ºC
(b) In a CE amplifier, thermal runaway is
unconditionally avoided if : VCE < VCC/2
(c) The current gain of amplifier stage is lowest
in : CB configuration
(d) The voltage gain of amplifier stage is lowest
in : CC configuration 95. A bipolar junction transistor has a common
IES-2005 base forward short circuit current gain of 0.99.
Its common emitter forward short circuit
Ans. (a) : current gain will be
• For silicon transistor this temperature is in the range (a) 50 (b) 99
of 150º to 225ºC and for germanium it is between (c) 100 (d) 200
60º to 100ºC IES-2003
• Current gain of amplifier is low in CB Ans. (b) : Given, α = 0.99
configuration ( α < 1 ≈ 0.98 ) find out β ?
• Voltage gain of amplifier is lowest in common α
collector configuration and greater than CB β=
1− α
configuration ( γ > α)
0.99 0.99
92. Which among the following region is heavily β= = = 99
1 − 0.99 0.01
doped?
96. At 25ºC, the collector-emitter voltage drop of a
(a) Junction (b) Emitter
silicon transistor at saturation is approximately
(c) Collector (d) Base (a) 0.1 V (b) 0.3 V
DMRC AM S&T-2020 (c) 0.5 V (d) 0.7 V
Ans. (b) : Emitter region is heavily doped. IES-2001
Collector region is moderately doped. Ans. (b) : In saturation condition of transistor, the
Base region is lightly doped. collector to emitter voltage,
93. Which one of the following statements is VCE = 0.2V (for silicon transistor)
correct? = 0.1 V (for Germanium transistor)
The set of transistor characteristics that For silicon transistor at saturation condition, the value
enables α to be directly determined from the of VCE is not less than 0.2V.
slope is So, VCE (Sat ) = 0.3V
(a) the common-emitter output characteristics
(b) the common-emitter transfer characteristics 97. The reverse bias breakdown of high speed
(c) the common-base input characteristics silicon transistors is due to
(d) the common-base transfer characteristics (a) Avalanche breakdown mechanism at both the
IES-2004 junctions
(b) Zener breakdown mechanism at both the C. E-B junctions 3. High gain
junctions reverse bias and amplifier
(c) Zener breakdown mechanism at base- C-B junction
collector junction forward bias
(d) Zener breakdown mechanism at base-emitter D. Both E-B and C- 4. Cut-off
junction B junctions condition
IES-2001 reverse bias
Ans. (d) : The zener breakdown occurs at much lower Codes:
value of reverse voltage is due to zener breakdown A B C D
mechanism at base-emitter junction. (a) 2 3 1 4
98. Consider the following circuit configurations: (b) 3 2 1 4
1. Common emitter (c) 3 2 4 1
2. Common base (d) 2 3 4 1
3. Emitter follower IES-2000
4. Emitter follower using Darlington pair Ans. (b) : A transistor has two PN Junction. Emitter-
The correct sequence in increasing order of the base Junction and collector-base Junctions. applying
input resistances of these configurations is proper d.c. voltage to the two Junctions is known as
(a) 2, 1, 4, 3 (b) 1, 2, 4, 3 transistor biasing.
(c) 2, 1, 3, 4 (d) 1, 2, 3, 4 Emitter-Base Collector-Bas Operating
IES-2000 junction junction Region
Ans. (c) : Forward biased Reverse biased Active
• The input resistance of CB is low because IE is Reverse biased Reverse biased Cut-off
high and its order of Ω. Forward biased Forward biased Saturation
• The input resistance of CE circuit is high but low 101. A transistor with emitter base voltage (VEB) of
than CC circuit and its order of kΩ. 20 mV has a collector current (IC) of 5 mA for
• The input resistance and output resistance of CC VEB of 30 mV, IC is 30 mA. If VEB is 40 mV,
circuit are respectively high and low and its input then the IC will be
resistance order of kΩ. (a) 55 mA (b) 160 mA
• Darlington order pair is of the order of kΩ and (c) 180 mA (d) 270 mA
greater than CC mode. IES-1999
so increasing order of input resistance is- Ans. (a) :
CB < CE < CC < Darlington pair.
99. A transistor has a current gain of 0.99 in the
CB mode. Its current gain in the CC mode is
(a) 100 (b) 99
(c) 1.01 (d) 0.99
IES-2000
Ans. (a) : Given - α = 0.99
Assume slope remain constant in the given rearrange.
1
We know γ = 30 − 20 40 − 30
1− α =
30 − 5 IC − 30
1
γ= 10 10
1 − 0.99 =
25 IC − 30
γ = 100
IC − 30 = 25
100. Match List-I (Biasing of the junctions) with
List-II (Functions) and select the correct IC = 55
answer using the codes given below the lists: 102. In a junction transistor, the collector cutoff
List-I List-II current 'ICBO' reduces considerably by doping
(Biasing of the (Functions) the
junctions) (a) emitter with high level of impurity
A. E-B junction 1. Very low gain (b) emitter with low level of impurity
forward bias and amplifier (c) collector with high level of impurity
C-B junction (d) collector with low level of impurity
reverse bias IES-1999
B. Both E-B and C- 2. Saturation Ans. (a) : In a junction transistor, the collector, cut-off
B junctions condition current' ICBO' reduces considerable by doping the emitter
forward bias with high level of impurity.
as- (b) NPN silicon transistor
IC = αIE +ICBO (c) PNP germanium transistor
ICBO = IC - αIE (d) PNP silicon transistor
Now α increased ICBO reduces. IES-1995
103. The unit of a thermal resistance of a Ans. (b) : NPN silicon transistor bipolar transistors has
semiconductor device is the highest current gain bandwidth product (fr) for
(a) Ohms (b) Ohms/ºC similar geometry.
(c) ºC/Ohm (d) ºC/Watt 107. Some commonly used power devices are given
IES-1999 in List-I and the approximate maximum
frequencies to which they can be presently used
Ans. (d) : Thermal resistance (Q) for switching large currents is given in List-II.
Tj − TA Match List-I with List-II and select the correct
Q= answer using the codes given below the lists:
PD
List-I List-II
Where → Tj = Collector Junction temperature A. Power MOSFET 1. 1 MHz
TA = Ambient temperature in Kelvin B. Insulated gate bipolar 2.100 kHz
PD = Power dissipated across collector junction. Transistor
Thus, the unit of thermal resistance is ºC/watt or C. Power bipolar 3. 1 kHz
0K/watt. Transistor
104. The modulation of effective base width by D. SCR 4. 10 kHz
collector voltage is known as Early Effect, Codes:
Hence reverse collector voltage.
A B C D
(a) increases both alpha and beta (a) 1 2 3 4
(b) decreases both alpha and beta (b) 2 1 3 4
(c) increases alpha but decreases beta (c) 1 2 4 3
(d) decreases beta but increases alpha (d) 3 1 4 3
IES-1997 IES-1995
Ans. (a) : In early effect, CB Junction will be reversed Ans. (a) :
bias. Base is lightly doped and thin. The effective base
Device Frequency of operation
width becomes zero and hence, base current Ib reduce.
So β will increase and also alpha will increase. • Power MOSFET → 1 MHz
• Insulated gate bipolar → 100 kHz
105. Match List-I (Regions of bipolar transistor in
monolithic IC) with List-II (Physical transistor
properties) and select the correct answer using • Power bipolar transistor → 1kHz
the codes given below the lists: • SCR → 10kHz
List-I List-II 108. Match List-I and List-II and select the correct
A. Emitter 1. Moderate resistivity answer using the codes given below the lists:
B. Base 2. Very high resistivity List-I List-II
C. Collector 3. Large size (Characteristic of (Device)
D. Substrate 4. Very high conductivity the device)
Codes: A. Voltage 1. Bipolar
A B C D controlled junction
(a) 1 4 2 3 device Transistor
(b) 4 1 2 3 B. Current 2. Uni-junction
(c) 4 1 3 2 controlled Transistor
(d) 1 4 3 2 device
IES-1996 C. Conductivity 3. Field Effect
Ans. (c) : Emitter is heavily doped so it has very high modulation Transistor
conductivity and release charge carriers. Base is lightly device
doped so it has moderate resistivity. D. Negative 4. IMPATT Diode
Collector is moderately doped but area made larger than conductance
emitter and base and substance has very low device
conductivity hence it has very high resistivity. Code:
Substrate has very low conductivity hence it has very A B C D
high resistivity. (a) 2 3 1 4
106. Which one of the following bipolar transistors (b) 2 3 4 1
has the highest current gain bandwidth (c) 3 1 2 4
product (fr) for similar geometry? (d) 3 1 4 2
(a) NPN germanium transistor IES-1994
Ans. (d) : Bipolar junction transistor is current Ans. (d) : Given-
controlled device. Uni-junction transistor has negative α = 0.98, I B = 20µA, ICO = 0.6µA
conductance device. Field effect transistor is voltage
controlled device and IMPATT diode operates on the α 0.98
β= = = 49
principle of conductivity modulation. 1 − α 1 − 0.98
Hence option 'd' is current option. Now- IC = βIB + (1+β) ICO
109. The Ebers-Moll equation for IE in CB IC = 49 ×20 +(1+49)×0.6
configuration is given by IC = 980 +30 =1010 µA
(a) IE = αnIC + ICO IC = 1.01mA
(b) IE = αIIC + ICO 113. For a narrow base PNP BJT, the excess
(c) IE = αnIC + ICO (eqVEB / kT − 1) minority carrier concentrations (∆nE for
(d) I E = α I IC + I EO (e qVEB / kT
− 1) emitter, ∆pB for base, ∆nC for collector)
normalized to equilibrium minority carrier
IES-1994 concentrations (nEO for emitter, pBO for base,
Ans. (d) : The Ebers-Moll equation for IE in common nCO for collector) in the quasi-neutral emitter,
base configuration is- base and collector regions are shown below.
I E = α I IC + I EO (eqVEB / kT − 1) Which one of the following biasing modes is the
transistor operating in?
110. A Schottky diode clamp is used along with a
switching BJT for
(a) reducing the power dissipation
(b) reducing the switching time
(c) increasing the value of β
(d) reducing the base current
IES-1994
Ans. (b) : Schottky diode also known as schottky
barrier diode or hot-carrier diode, is a metal
semiconductor junction diode. It can be used along
with BJT for increasing switching speed decrease (a) Forward active (b) Saturation
switching time or reducing propagation delay.
(c) Inverse active (d) Cutoff
111. If a transistor is operating with both of its GATE- 2017
junctions forward biased, but with the collector
base forward bias greater than the emitter-base Ans. (c) :
forward bias, then it is operating in the • Minority carrier concentration (∆pB) is high. This is
(a) forward active mode because excess hole supplied by the collector means
(b) reverse saturation mode CB junction is forward biased.
(c) reverse active mode • The minority holes carrier concentration in a base
(d) forward saturation anode region near the emitter-base junction is low, i.e.
GATE-1996 holes are extracted from the based.
Ans. (b) : Mode of operation So mode of operation is Reverse Active.
Mode JE JC 114. An npn bipolar junction transistor (BJT) is
operating in the active region. If the reverse
Saturation Forward bias Forward bias bias across the base-collector junction is
Cut-off Reverse bias Reverse bias increased, then
Active Forward bias Reverse bias (a) the effective base width increases and
Reverse Active Reverse bias Forward bias common-emitter current gain increases
• When transistor is operating with both of its (b) the effective base width increases and
junction forward biased, but with the collector base common emitter current gain decreases
for forward bias greater than the emitter base forward (c) the effective base width decreases and
bias, then it is operating in reverse saturation mode. common-emitter current gain increases
(d) the effective base width decreases and
112. For a BJT, the common-base current gain α=
common-emitter current gain decreases
0.98 and the collector base junction reverse
bias saturation current ICO= 0.6 µA. This BJT GATE- 2017
is connected in the common emitter mode and Ans. (c) : When a BJT in active region , as the reverse-
operated in the active region with a base drive biased base-collector voltage in increased the depletion
current IB=20 µA. The collector current IC for region of the base-collector junction is increased
this mode of operation is resulting in the extension of this region more towards
(a) 0.98 mA (b) 0.99 mA base side thereby reducing the effective base width this
(c) 1.0 mA (d) 1.01 mA reducing in the effective base-width result in the
GATE-2011 increase in current gain.
115. Which of the following statements are correct 119. Transistors ratings symbols using capital letter
for the basic transistor amplifier configurations and with subscripts also in capital letters
(a) CB amplifier has low input impedance and a denotes
low current gain (a) DC parameters
(b) CC amplifier has low output impedance and a (b) AC parameters
low current gain (c) Effective values
(c) CE amplifier has very poor voltage gain but (d) Time varying values
very high input impedance Nagaland PSC- 2018, Diploma Paper-II
(d) none of the above Ans. (a) : From IEEE rule transistor ratings symbols
Kerala PSC Lecturer (NCA) 04.07.2017 using capital letters and with subscripts also in capital
Ans. (a) : Common base (CB) configuration has low letters denotes DC parameter.
input impedance and low current gain and common 120. CC amplifier has
collector (CC) configuration has low output impedance (a) High Ri and high Ro (b) Low Ri and low Ro
and higher current gain. Common emitter amplifiers has
(c) Low Ri and high Ro (d) High Ri and low Ro
high voltage gain and high current gain.
116. If a silicon BJT is in the cut-off region, then
VCE will be approximately Ans. (d) : For common collectors Amplifier -
(a) 0 V (b) minimum Rin ⇒ High and Rout = Low.
(c) 0.6 V (d) equal to VCC 121. Varactor diode is used as
RPSC VP/Suptd. ITI 05.11.2019 (a) Frequency multiplier (b) Oscillator
Ans. (d) : Cutoff- The point where the load line (c) Parametric amplifier (d) Electronic Tunner
intersects the I B = 0, curve is known as out off. At this Nagaland PSC- 2018, Diploma Paper-II
point, I B = 0, and only small collector current. At cut Ans. (d) : Varactor diode refers to the variable capacitor
diode, which means the capacitance of diode varies
off, the base emitter junction no longer remains forward linearly with applied voltage. A Varactor diode is used
biased and normal transistor action is lost.
as electronic tunner.
The collector-emitter voltage is nearly equal to Vcc i.e.
Vce (Cut off) = Vcc 122. In an ideal balanced differential amplifier, the
common mode gain is
(a) Double of that of single-ended amplifier
(b) Half of that of single-ended differential
amplifier
(c) Very low
(d) Zero
Nagaland PSC CTSE- 2015, Paper-II
Ans. (d) : Since we are currently defining ideal
117. Typical value of hie is characteristic you should remember that an ideal op-
(a) 1 kΩ (b) 1 Ω amp has a common mode voltage gain of zero.
(c) 100 kΩ (d) 50 Ω This means the output is unaffected by voltages that are
TSPSC Manager (Engg.) - 2015 common to both inputs (no difference).
Ans. (a) : Value of hie lies is 1kΩ to 20k Ω 123. The following amplifier configuration yields
the largest power gain of all transistor
V
Input resistance, h ie = h11 = 1 amplifier configuration
V2 V =0 (a) Common base (b) Common emitter
2
Typical value of parameter (c) Common collector (d) Emitter follower

h fe = 50 to 750 Nagaland PSC CTSE- 2015, Paper-II
h oe = 20µS Ans. (b) : The common emitter amplifier configuration
yields the largest power gain of all transistor amplifier
h re = 1× 10−4 configuration.
118. A transistor has parameters as hie = 10 kΩ, hre Note – CE amplifier has large voltage and current gain.
= 20 × 10–4, hfe = 100, hoe = 25 µs. The hib for 124. Which of the following configurations normally
this transistor will be used in cascading?
(a) 100 Ω (b) 99.01 Ω (a) Common-emitter (b) Common-base
(c) 5 M Ω (d) 101 K Ω (c) Common-collector (d) All of these
APGENCO AE- 23.04.2017 Nagaland PSC CTSE- 2015, Paper-II
Ans. (a) : Common emitter configuration is used in
h ie 10 × 10 3
Ans. (b) : h ib = = cascading. It is widely used in industry.
1 + h fe 1 + 100 Note – Amplifiers are cascaded to increase gain and to
= 99.01Ω get desired input and output resistances.

125. In a bipolar transistor biased in the forward-
127. The h-parameter equivalent circuit of a
active region, the base current is IB = 50 µA junction transistor is valid for:
and the collector current is IC = 2.7 mA. The (a) High frequency, large signal operation
value of α is : (b) High frequency, small signal operation
(a) 0.949 (b) 54 (c) Low frequency, small signal operation
(c) 0.982 (d) 0.018 (d) Low frequency, large signal operation
(e) 2.010 (e) Both small and large signal operation
CGPSC SO 14.02.2016 CGPSC SO 14.02.2016
Ans. (c) : Given, Ans. (c) : The h parameter use in transistor to find static
base current IB = 50 µA characteristics curves and it is valid for low frequency.
collector current IC = 2.7 mA Small signal operation.
I E = I B + IC 128. If the base width in a bipolar junction
Ι
α= C ⇒ transistor is doubled, which one of the
ΙE I E = 2700 + 50 = 2750µA following statements will be TRUE?
(a) Current gain will increase
2700
α= = 0.981 (b) Unity gain frequency will increase
2750 (c) Emitter base junction capacitance will
126. Mobility of electros varies with respect to increase
doping concentration as: (d) Early voltage will increase
GATE- 2015, Set-III
(a) Ans. (d) : As the base width is increased, the base
current will increase thus reducing the collector
current. The collector-emitter characteristics will be flat,
thus the extrapolation of collector currents will be
farther i.e. early voltage will increase.
(b) 129. Consider the emitter terminal of Si based npn
BJT is grounded. If the voltage at base and
collector terminal are 3 V and 2V respectively,
the transistor is in:
(a) Cut-off region
(b) Active region
(c) Saturation region
(c)
(d) Reverse active region
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
Ans. (b) :
Mode E-B C-B Application
junction junction
(d) Cut off Reverse Reverse
Off-switch
region bias bias
Active Forward Reverse
Amplifier
region bias bias
Saturation Forward Forward
On-Switch
region bias bias
(e) Reverse Reverse forward
Attenuator.
active bias bias
region
130. How many layers of material does a transistor
have?
CGPSC SO 14.02.2016 (a) 4 (b) 3
(c) 2 (d) 1
Ans. (e) :
Ans. (b) : A transistor has three layers of
semiconductor. An emitter, collector and base it
controls the electric conductivity across it to perform a
desired task.
131. In an intrinsic semiconductor
σ = (ne – µe + np µp) (a) CB is empty VB is full
(b) VB is empty CB is full 135. “Common Base” configuration refers to the
(c) CB & VB both are empty configuration of a -
(d) CB & VB both are full (a) Rectifier (b) Transistor
BARC Scientific Officer-2016 (c) Diode (d) Inverter
Ans. (a) : Intrinsic semiconductor- RRB SSE 21.12.2014, (Green)
• An intrinsic semiconductor is a semiconductor in Ans. (b) : Common base configuration refers to the
which no other material is doped in pure silicon, configuration of a transistor.
Germanium. Common emitter and common collector also the
• Intrinsic semiconductor behaves as an insulator at configuration of transistor.
absolute zero temperature in which conduction band
(CB) is empty and valance band (VB) is full. 136. Once ‘X’ is turned ON, even after removing the
gate voltage, ‘X’ remains ON. ‘X’ is a :
132. A transistor can be destroyed in a circuit by:
(a) excessive heat (b) excessive light (a) Transistor (b) FET
(c) saturation (d) cut-off (c) Thyristor (d) MOSFET
RRB SSE-03.09.2015, Shift-III RRB SSE 21.12.2014, (Green)
Ans. (a) : A transistor can be destroyed in a circuit by Ans. (c) : When ‘X’ is turned ON, even after removing
excessive heat. the gate voltage and X remains ON then it is a thyristor.
133. In a transistor radio, a frequency tuner circuit • Thyristors are mainly used where high currents and
that was conventionally used, would consist of- voltages are involved and are often used to control
(a) An inductor and a variable capacitor in alternating currents.
parallel 137. ______configuration has the highest voltage
(b) A bridge rectifier diode feeding the base of a gain.
transistor through variable resistance (a) Common emitter (b) Common collector
(c) A multiple coil variable (c) Common base (d) Both b and c
(d) A potentiometer with variable resistance
RRB SSE 01.09.2015 Shit-I
RRB SSE 21.12.2014, (Green)
Ans. (a) : In a transistor, a frequency tuner circuit Ans. (c) : Common base configuration have highest
would consists of an inductor and a variable capacitor voltage gain and lowest current gain among all
(tuned circuit or tank circuit) configuration.
• The purpose of variable capacitor allows for tuning to Comparison of CE, CB, and CC configuration.
the various signals. Characteristics CB CE CC
134. Based on the choice of the ‘Q’ point on the Input Low Moderate High
current voltage characteristics of the transistor, resistance
the amplifiers are classified as : Output High Moderate Low
(a) Class I, II, III and IV resistance
(b) Class A, B, C and AB Current gain Less than High Very
(c) Class A, B, C and D 1 high
(d) Class IA, IB, IIA and IIB Voltage gain Very High High Less
RRB SSE 21.12.2014, (Green) than one
Ans. (b) : Based on the choice of the ‘Q’ point on the
Power gain Low Very high Low
current voltage characteristics of the transistors
amplifiers are classified as A, B, C and AB. 138. The β of a transistor is 200, what is its α?
Class A amplifier- Class A amplifier operates in the (a) 0.969 (b) 0.928
linear portion of its characteristics curves, the single (c) 0.905 (d) 0.995
output device conducts through a full 360º of the output UPPCL AE-05.11.2019
waveform.
Class B amplifier-Class B amplifier only conducts Ans. (d) : Given,
through one half or 180º of the output wave form in β = 200 ⋅ α = ?
strict time alternation, but as the output stage has device β 200
for both halves are combined together to produce the α= ⇒α=
1+ β 201
full linear output waveform.
Class AB amplifier- The AB classification of amplifier α = 0.995
currently one of the most common used type of audio
power amplifier design. 139. Transistors used as power amplifiers are
• Conduction angle of a class AB amplifier is some generally mounted on a metallic plate so as to−
where between 180º and 360º. (a) Improve their conductivity
Class C amplifier- The class C amplifier design has the (b) Provide the additional support to them
greatest efficiency but the poorest linearity of the (c) Radiate the excessive heat developed in them
classes of amplifiers. during working
• Conduction angle for the transistor is significantly less (d) Improve their performance
than 180º degrees. RRB JE-01.09.2019, 3:00 PM – 5:00 PM
Ans. (c) : In power amplifiers, very high output in Ans. (a) : If the bypass capacitor is removed an extreme
comparison of very low input. That is why it produces a degeneration is produced in the amplifier circuit and the
large amount of heat which is to be dissipated into the voltage gained will be reduced hence stability factor
atmosphere which is essentially done by using metallic will also reduce because stability factor is directly
i.e. a heat sink. depends on gain.
140. If the reverse bias voltage increase, then what 144. Which Amplifier shows high current gain?
happen to diffusion capacitance. (a) CE (b) CB
(a) decreases (c) CC (d) None
(b) increases BEL-2015
(c) remains constant Ans. (c) : Common collector configuration has highest
(d) increases exponentially current gain, among all configuration in BJT.
BEL-2015Comparison of CE, CB and CC configuration.
Ans. (c) : Diffusion capacitance- Diffusion Characteristics CB CE CC
capacitance is due to the transfer of minority carries Input Low Moderate High
during the forward bias. Then if we increase the reverse resistance
bias voltage the diffusion capacitance remains constant.
Output High Moderate Low
141. What happen to reverse saturation current and resistance
junction voltage if temperature increases.
Current Gain Very Low Low Very
(a) increases, increases
> 10 High
(b) increases, decreases
(c) decreases, increases Voltage Gain Very High High Very
Low <1
(d) decreases, decreases
145. The stability of fixed bias circuit
BEL-2015
(a) good (b) poor
Ans. (b) : The reverse saturation current increases with
the rise of temperature of the junction diode this is (c) excellent (d) can't predict
because the minority carrier density contributing BEL-2015
proportion increase with the rise of temperature. Ans. (b) : Stability factor – The rate of change of
• Higher the temperature, greater will be the mobility collector current IC with respect to the collector leakage
current ICO at constant β and IB is called stability factor.
of charge carriers and lower potential difference across
the junction can break the potential barrier. But as the dI
S = C at constant IB and β
temperature lowers kinetic energy of charge carriers dICO
decrease and higher will be the value of potential
• Stability factor for fixed bias circuit is
barrier.
S = β +1
142. A bypassed emitter resistor giving which Thus stability factor in a fixed bias is β +1 which means
Amplifier that IC changes (β +1) times as much as any change in
(a) Voltage feedback ICO
(b) current feedback Advantages of fixed bias circuit-
(c) Negative voltage feedback
• The circuit is simple
(d) Positive current feedback
• Only one resistor RB is required
BEL-2015
• Biasing conditions are set easily
Ans. (c) : • No loading effect as no resistor is present as base.
emitter junction.
Disadvantages-
• The stabilization is poor as heat development can
not be stopped.
• The stability factor is very high so, there are strong
chance of thermal run away.
146. Given I CEO = 1mA, I CBO = 10µA then calculate β
CB, CC – blocking capacitor which block the dc value =?
CE= by pass capacitor which is used to prevent decrease (a) 100 (b) 999
in voltage gain. (c) 99 (d) 1000
Csh= shunt capacitor= bandwidth. SAIL- 2014
143. If the by-pass capacitor removed what happen Ans. (c) : Given,
to stability factor ICEO = 1mA
(a) very low (b) very high ICBO = 10 µA
(c) no change (d) Linearly increasing β=?
BEL-2015 Q We know that
ICEO = (1+β) ICBO 151. The voltage follower is commonly used as
I (a) Regulator (b) Switch
∴ 1+ β = CEO (c) Isolator (d) a and b both
ICBO
RRB SSE 02.09.2015, Shift-II
1mA Ans. (d) : The voltage follower is commonly used as
1+ β =
10 × 10−6 regulator and switch.
1× 10−3 ×106 Voltage follower- A voltage follower is also known as
1+ β = unity gain amplifier, a voltage buffer or an isolation
10 amplifier.
1+ β = 100 • In a voltage follower circuit, the output voltage is
= 99 equal to input voltage; thus it has a gain of one (unity)
147. In a uniformly doped BJT assume that NE, NB and does not amplify the incoming signal.
and NC are the emitter, base and collector 152. In Common Emitter Amplifier, voltage gain is:
doping in atoms/cm3 respectively. If the emitter (a) Independent of supply voltage VCC and
injection efficiency of the BJT is close to unity, depends on collector resistance RC
which one of the following conditions is TRUE? (b) Directly proportional to collector resistance
(a) NE = NB and NB<NC (b) NE<NB<NC RC and inversely proportional to supply
(c) NE>>NB and NB<NC (d) NE = NB = NC voltage VCC
BPSC Asst. Prof. - 12.04.2022 (c) Directly proportional to supply voltage VCC
BPSC Polytechnic Lecturer-2014 and inversely proportional to collector
resistance RC
Ans. (c) : The entire transistor action is due to the
electrons injection into the base. The holes injected into (d) Directly proportional to both supply voltage
the emitter, are useless from the point of view. VCC and collector resistor RC
The BJT doping profile are related as NE>NC>NB.
emitter injection efficiency close to unity so Ans. (c) : Common mode voltage gain refers to the
amplification given to signals that appears on both
N E >> N B and N B < N C inputs relative to the common.
148. Early effect in BJT is related to R 
(a) Base narrowing Voltage gain = β.  o 
(b) Avalanche breakdown  R in 
(c) Zener breakdown −h fe 1 
(d) Thermal runaway Av =  || R L 
h ie R oe 
Ans. (a) : Early effect in BJT is related to base 153. In BJT, collector current IC in active region is :
narrowing of the base collector junction. (a) directly proportional to the width of base
region.
• When reverse bias voltage applied at collector base (b) directly proportional to the doping of base
junction is increased then depletion region of CB region.
junction increases which reduces the effective channel
(c) directly proportional to the doping and width
width of transistor. This phenomenon of narrowing of base region.
effective width is known as early effect.
(d) inversely proportional to the doping and
149. Transistors are mostly used as width of base region.
(a) Rectifier (b) Voltage regulator MPSC HOD Govt. Poly. -2013
(c) Oscillator (d) Amplifier Ans. (d) : In active region- IC = β.I B
RRB SSE 02.09.2015, Shift-I
So, IB will increase when base width decrease. Hence IC
Ans. (d) : Transistors are mostly used as a amplifying, is inversely proportional to base width and doping.
controlling, and generating electrical signals.
154. Which of the noise type is dominant in metal
• Transistors are the active components of integrated semiconductor field effect transistor
circuits or microchips, which often contain billions of (MOSFET) when compared to bipolar junction
these devices are fabricated into their shiny surfaces transistor (BJT) ?
150. In transistor, if electrons flow into emitter, (a) Thermal noise (b) Shot noise
(a) Holes flows out of the emitter (c) Flicker noise (d) All of these
(b) Holes flows out of the collector ISRO Scientist December, 2017
(c) Electron flow into the collector Ans. (c) : Flicker noise is often characterized by the
(d) Electron flow out of the collector corner frequency fc between the region dominated by
RRB SSE 02.09.2015, Shift-II the low frequency flicker noise and high-frequency "flat
Ans. (a) : As we know that electrons and holes move in band noise."
opposite direction. So holes flow out of emitter as MOSFET'S have higher fc in GHz than JFET usually
electrons flow into emitter. below 2KHz.

155. Let β be the short circuit common emitter 159. The slope of the output characteristics of a
current gain of a BJT biased in normal active transistor in CE configuration is higher than
mode. Let IC be the collector current is this β that in CB configuration due to which one of
(a) a monotonically increasing function of IC the following effects?
(b) a monotonically decreasing function of IC (a) Zener effect (b) Early effect
(c) initially an increasing function of IC which (c) Avalanche effect (d) Transistor effect
ESE-2021
reaches a plateau, and then decreases with
increasing IC Ans.(b) : The slope of the output characteristics of a
(d) Independent of IC transistor in CE configuration is higher than that in CB
configuration due to early effect. Early effect is the
BSNL (JTO)-2001 variation in the effective width of the base in a BJT.
Ans. (c) : At starting β is increasing function of Ic 160. If the common base DC current gain of a BJT
which reaches a plateau i.e. ideas with positive slope is 0.98, its common emitter DC current gain is
and then constant after that decreasing with increase in (a) 51 (b) 49 (c) 1 (d) 0.02
Ic as slop is –1. DRDO-2008
156. If Cd and Cs represent the depletion and Ans. (b) : Common base dc current gain α = 0.98
diffusion capacitances of a diode respectively, α
which one of the following statements is NOT Common emitter DC current gain β =
1− α
correct? 0.98
(a) Cd varies inversely with the depletion width. β= = 49
(b) Cs varies directly with the rate of change of 1 − 0.98
diode current with respect to diode voltage. 161. The early effect in a BJT is modeled by the
(c) Cd varies directly with the transit time. small signal parameter
(d) Effective junction capacitance is the parallel (a) r0 (b) rπ (c) gm (d) β
combination of Cs and Cd. DRDO-2008
DRDO-2009 Ans. (b) : Early effect is the variation in the effective
Ans. (c) : width of the base in BJT due to a variation in the
applied base-collector voltage. Early effect can be
1
Diffusion capacitance Cd ∝ accounted for in small signal parameter rπ.
Depletion width 162. As compared to a BJT amplifier, an amplifier
Cd ∝ doping made using a JFET is likely to have :
(a) very high voltage gain
1 (b) very high bandwidth
Cd ∝
junction voltage (c) very high voltage swing
(d) very high input resistance
157. The band structure of a BJT is shown in figure BSNL(JTO)-2002
below. Ans. (d) : JFET Amplifier uses function field effect
transistor as its main active device offering high input
impedance characteristics.
163. Which of the following statements is true for
bipolar junction transistor?
(a) Cutoff mode operation if emitter-base
junction is forward biased and collector base
it represents : junction is forward biased.
(a) a pnp BJT biased in active mode (b) Cutoff mode operation if emitter-base
(b) an npn BJT biased in saturation mode junction is forward biased and collector base
(c) an npn BJT biased in reverse-active mode junction is reverse biased.
(d) a pnp BJT biased in cutoff mode (c) Cutoff mode operation if emitter-base
DRDO-2009 junction is reverse biased and collector base
Ans. (a) : Since EF is just above Ev hence it is a pnp junction is forward biased.
BJT biased in active mode. (d) Cutoff mode operation if emitter-base
junction is reverse biased and collector base
158. Adding a degeneration resistor RE to a common junction is reverse biased.
emitter BJT amplifier will mainly reduce BSNL(JTO)-2002
(a) the voltage gain Ans. (d) :
(b) the input impedance
Mode E-B C.B Application
(c) the amplifier bandwidth
Junction Junction
(d) the output impedance
Active region Forward Reverse Amplifier
DRDO-2009
Bias Bias
Ans. (a) : When (RE) degeneration resistance RE is Cutt off Reverse Reverse Off switch
added to common emitter amplifier following factors region Bias Bias
are affected- Saturation Forward Forward ON Switch
Voltage gain reduced by a factor of (1 + β ) R E region Bias Bias
Input impedance increases Reverse Reverse Forward Attenuator
Thermal stability also increase Active region Bias Bias
164. In figure what is value of IC if β dc = 100? 167. An emitter follower amplifier has :
Neglect VBE (a) current gain that is always less than 1
(b) voltage gain that is always less than 1
(c) very small input impedance
(d) vey large output impedance
BSNL(JTO)-2002
Ans. (b) : An emitter follower Amplifier has voltage
(a) 5 mA (b) 5 µA gain that is always less than 1 and current gain always
(c) 10 mA (d) 10 µA more than 1.
Mizoram PSC Jr. Grade-2015, Paper-II –common collector (cc) is used a voltage buffer and
Ans. (c) : Given that, called a voltage follower or emitter follower circuit.
βdc = 100, VBE is neglect Parameter CB CE CC
KVL at input side Input Low High Very high
30 − I B × 300kΩ = 0 Resistant (  100Ω ) (  750Ω ) (  750kΩ )
30
IB = Output Very high High Low
300kΩ Resistant ( 450kΩ ) (  45kΩ ) (  50Ω )
I B = 0.1mA
Current gain Less than 1 more than 1 more than 1
We know that,
IC = βI B
Voltage Very high medium Less than 1
IC = 100 × 0.1 gain
IC = 10mA 168. Which Junction Transistor is preferred for
165. For the 2N338 transistor, the manufacturer high input and low output impedances ?
specifies Pmax = 100mW at 25º C free air (a) Common Collector (b) Common Base
temperature and the maximum junction (c) Common Emitter (d) Any one of these
temperature, Tjmax= 125ºC. Its thermal Ans. (a) : Common collector configuration has
resistance is maximum input impedance and minimum output
(a) 10ºC/W (b) 100ºC/W impedance.
(c) 1000ºC/W (d) 10,000ºC/W 169. Which of the following transistor is affected by
static electricity.
Ans. (c) : Given, (a) npn Transistor (b) JFET
Pmax = 100mW (c) UJT (d) MOSFET
Tjmax = 125º C Mizoram PSC IOLM -2018, Paper I
Ta = 25º C Ans. (d) : A MOSFET is a field effect transistor with a
Find out thermal resistance = ? MOS structure. And it is a voltage controlled device. A
Tjmax − Ta MOSFET transistor is affected by static electricity.
Pmax = 170. In a transistor leakage current mainly depends on
Thermal resistance
(a) Doping of base (b) Size of emitter
−3 125 − 25 (c) Rating of transistor (d) Temperature
100 × 10 =
R th Nagaland PSC CTSE (Diploma)-2018, Paper-I
100 KVS TGT (WE)-2016
R Th = −3
= 10000 C / W Ans. (d) : The leakage current in transistor mainly
100 × 10
166. If the emitter bypass capacitor in a common depends on temperature and double forever 10°C rise in
emitter amplifier is removed, then : temperature. The leakage current dependence on
(a) input resistance will decreases temperature is responsible for thermal run away in transistor.
(b) voltage gain will increases 171. The decrease in base doping of the BJT would
(c) voltage gain will decreases result in
(d) voltage gain will remain unaffected (i) Increased emitter efficiency
BSNL(JTO)-2002 (ii) Reduced emitter efficiency
Ans. (c) : If bypass capacitor is removed, the emitter (iii) High magnitude of early voltage
resistance presents in the circuit in DC analysis. If the (iv) Low magnitude of early voltage
emitter resistance is present, the voltage drop across the (a) (i) and (ii) (b) (i) and (iv)
emitter resistance increase and it in turn decrease the (c) (ii) and (iv) (d) (ii) and (iii)
output voltage. Hence, the voltage gain decreases. RPSC ACF & FRO 23.02.2021
Ans. (b) : the decreasing in base doping of the BJT 175. How much “holes carrier” emitted by the
would result in emitter recombines with the electrons in the
(i) Increased emitter efficiency base in a PNP type transistor?
(ii) Low magnitude of early voltage (a) More than 95% (b) Less than 5%
(c) More than 50% (d) Less than 50%
172. Of the three BJT configurations CB, CE and
LMRC AM- 16.07.2021
CC :
(a) CB does not have Miller effect hence higher Ans. (b) : Less than 5% holes carrier emitted by the
emitter recombines with the electrons in the base in a
bandwidth
PNP type transistor.
(b) CC has smallest bandwidth
(c) CB exhibits reduction in bandwidth due to 176. At a constant collector current, the magnitude
of base emitter voltage decreases by 2mV for
Miller effect.
every XX rise in temperature. Here XX is
(d) CE exhibits increase in bandwidth due to
_________.
Miller effect.
(a) 3 ºC (b) 9 ºC
KVS TGT (WE)- 2017
(c) 4 ºC (d) 1 ºC
Ans. (a) : Common Base (CB) :- Commonly used as a DFCCIL Executive (S&T) 11.11.2018, 4:30 to 6:30PM
cascade stage to isolate output voltage signal from Ans. (d) : Implications of Ebers-Moll equation
feeding back to input eliminating Miller effect from Temperature effects
amplifier to increase bandwidth. It provides low input • VBE decreases by ≈ 2.1 mV*/ºC, holding
impedance and close to unity current gain. It is not IC constant
typically used as standalone amplifier due to low input • IC increases at about 9% /ºC, holding VBE constant.
impedance. CB is also used to increase output So, at a constant collector current (IC), the magnitude of
impedance of current sources to increase gain. base-emitter voltage (VBE) decreases by 2mV for every
173. In a bipolar transistor, the emitter efficiency is 1ºC rise in temperature.
(p-n-p transistor): 177. In the active region of a transistor Emitter-
Current of injected carries at J E Base junction is _______ biased and Collector-
(a) Base junction is in _________ biased.
total collector current
(a) forward, forward (b) reverse, forward
Current of injected carries at J E (c) reverse, reverse (d) forward, reverse
(b)
total emitter current DFCCIL Executive S&T-17.04.2016, Shift-II
Current of injected carries at J C Ans. (d) : In active mode of transistor Emitter Base
(c) junction is forward biased and Collector-Base junction
total collector current
is in reverse biased.
Current of injected carries at J C Mode EB Biasing Collector Application
(d)
total emitter current Base Biasing
KVS TGT (WE)- 2018 Cut off Reverse Reverse Off switch
Ans. (b) : It is the ratio of current due to emitter Active Forward Reverse Amplifier
majority carriers to the total emitter current. Saturation Forward Forward On switch
Current of injected carries at J E 178. If the______, the emitter junction is reverse
r= biased and collector junction is forward biased.
Total emitter current
(a) Inverse region of transistor operation
IP E J E
= = P (b) Saturation region of transistor operation
I P E + In E I E (c) Cut-off region of transistor operation
174. _____of electron carriers emitted by the (d) Active region of transistor operation
emitter cross over to the collector current after
recombination with the holes in the base in an
Ans. (a) : In the inverse region of transistor operation
NPN-type transistor. the emitter junction is reverse biased and collector
(a) More than 85% (b) More than 5% junction is forward biased.
(c) More than 95% (d) More than 50% Active region ⇒ Emitter base junction is forward bias
LMRC AM- 16.07.2021 and collector base junction is reverse.
Ans. (b) : More than 5% of electron carriers emitted by Saturation region ⇒ Emitter base junction is forward
the emitter cross over to the collector current after bias and collector base junction is forward bias.
recombination with the holes in the base in an NPN- Cut off region ⇒ Emitter base junction is reverse bias
type transistor. and collector base junction is reverse bias.

179. In the BJT symbol the arrow in the emitter Ans. (b) : The reciprocal of the slope of the output
shows the direction of : characteristics of a transistor in common base
(a) holes configuration gives output resistance.
(b) electrons
VCB
(c) holes in PNP and electrons in NPN R out =
(d) electrons in PNP and holes in NPN IC
TNTRB AE– 2017 184. The range of β in BJT is _____.
Ans. (a) : BJT is a bipolar current controlled three (a) 20 to 500 (b) 2 to 50
terminal device. It consists of three terminal (Base, (c) 100 to 400 (d) 5 to 100
emitter, collector). UPPCL AE-30.03.2022
emitter has an arrow which shows direction of current
Ans. (a) : The range of β in BJT is 20 to 500.
flow. Conventional flow of current is because of holes
in both PNP and NPN BJT. I α
β= C β=
180. Miller indices are same for: I B 1 − α
(a) Crystal planes β = current gain of common emitter.
(b) Parallel planes
185. A lateral pnp device has base width of 10µ and
(c) Perpendicular planes
diffusion coefficient for base region is 20
(d) Three crystallographic planes
cm2/sec. The base transit time is_______.
(a) 50 ns (b) 2 ns
Ans. (b) : Miller indices are same for parallel planes.
(c) 25 ns (d) 1 ns
The distance will be the same for all directions from the
UPRVUNL AE-2016
origin. So reciprocals of those also will be same. Hence
parallel planes, miller indices will be the same. Ans. (c) : Given, Base width ( WB ) = 10 m , Diffusion
181. A heat sink is used with a transistor to co-efficient for base region (DB) = 20 cm2/sec.
W 2 (10 × 10 )
(a) prevent excessive temperature rise −4 2
(b) increase forward current τB = B =

(c) increase reverse current 2D B 2 × 20
(d) increase forward voltage τB = 25ns
KVS TGT (WE)- 2016 186. In a normal operation of a PNP transistor:
Ans. (a) : Due to the flow of current heat produces, (a) Its both junctions are forward biased
sometimes it becomes so high that transistor can (b) Its both junctions are reverse biased
damage. To avoid thermal run away we use heat sink. It (c) Its emitter base is reverse biased and collector
is made up with conducting material, it's shape is like base is forward biased
cap. It covers whole transistor while increasing the (d) Its emitter base is forward biased and
temperature of transistor, it absorbs the temperature
collector base is reverse biased
and releases it into air, by this process heat sink saves
UPSC JWM-2016
transistor from thermal runaway.
Ans. (d) : In a normal operation of a PNP transistor its
182. In common emitter configuration, the phase
emitter base is forward biased and collector base is
difference between input and output voltage of
a transistor is ______. reverse biased.
(a) 0º (b) 90º 187. In BJT to avoid Punch through:
(c) 180º (d) 270º (a) Collector doping should be high and base
KVS TGT (WE)- 2016 doping should be low
Ans. (c) : In common emitter configuration, the phase (b) Collector doping should be low and base
difference between input and output voltage of doping should be high
transistor is 180º. In common base and common (c) Doping of both sides should be equal
collector configuration the phase difference between (d) Either "collector doping should be high and
input and output voltage of transistor is 0º. base doping should be low" or "collector
183. The reciprocal of the slope of the output doping should be low and base doping
characteristics of a transistor in common base should be high"
configuration gives LMRC AM (S&T)-13.05.2018
(a) input resistance (b) output resistance
(c) β of the transistor (d) α of the transistor
Ans. (a) : In BJT to avoid Punch through collector
KVS TGT (WE)- 2016 doping should be high and base doping should be low.

Ans. (d) : In a differential amplifier using two FETs a
(iv) Field Effect transistors (FETs) resistance has to be used to reduce the meter currents to
zero even when no voltage is applied to the circuit, this
1. In a MOSFET operating in saturation region,
is necessitated on account of both mismatches between
the channel length modulation effect causes
the characteristic of the FET's and difference between
(a) an increase in gate - source capacitance tolerance values of resistor used in circuit even though
(b) a decrease in the transconductance they are marked nominally equal.
(c) a decrease in unity gain cutoff frequency
5. A depletion mode - MOSFET is characterized
(d) a decrease in output resistance by a
(a) lightly doped channel between heavily doped
source and drain
Ans. (d) : For a MOSFET operating in saturation region (b) heavily doped channel between lightly doped
the channel length modulation effect causes a decrease source and drain
in output resistance.
(c) enhanced channel between source and drain
The drain characteristic becomes less flat. Ideally drain
(d) lightly doped channel between drain and gate.
characteristics is flat which implies infinite impedance. RPSC ACF & FRO 23.02.2021
µ W
Id = × C   ( VGS − VT )
2
Ans. (a) : A depletion mode-MOSFET is characterized
2 L by a lightly doped channel between heavily doped
2. A MOSFET made using p-type substrate, source and drain. A depletion mode MOSFET is
operating in the accumulation mode, the normally ON at zero gate-source voltage.
domain charge in the channel is due to 6. A FET is better chopper than a BJT because it
presence of has
(a) electrons only (a) Lower off-set voltage
(b) positively charged ions only (b) Higher series ON resistance
(c) negatively charged ions only (c) Lower input current
(d) holes (d) Higher input impedance
UPPSC ITI Principal/Asstt. Director-09.01.2022 IES-2020
Nagaland PSC CTSE (Degree)-2018, Paper-I APGENCO AE- 23.04.2017
Nagaland PSC CTSE (Degree)-2017, Paper-I Nagaland PSC CTSE (Degree)-2017, Paper-I
Ans. (d) : A MOSFET made by using a p-type substrate, Ans. (a) : A FET is a better chopper than a BJT because
operating in the accumulation mode, then the domain it has lower offset voltage.
charge in the channel is due to presence of hole. Because of offset voltage, the output is not zero even
In MOSFET, with p-type substrate operate in accumulation when the input is zero it is therefore considered as one
mode when gate voltage is –ve i.e. VGS= –ve. of problems when dealing with transistors.
3. A MOSFET can be used as a voltage variable 7. Which of the following holds FALSE for
resistor in MOSFETs?
(a) Saturation region (b) Triode region (a) There is no direct electrical connection
(c) Both (a) and (b) (d) None of the above between the gate terminal and the channel of
UPPSC ITI Principal/Asstt. Director-09.01.2022 a MOSFET.
Ans. (c) : MOSFET can be used as a voltage variable (b) For values of VGS less than the threshold
Resistor in saturation and triode region. level, the drain current of an enhancement
A field effect transistor (FET) works as a voltage type MOSFET is 0 mA.
variable resistor in the ohmic region. (c) It is the insulating layer of SiO2 in the
4. In a differential amplifier using two FETs, a MOSEFT construction that accounts for the
resistance has to be used to reduce the meter very desirable high input impedance of the
device.
current to zero even when no voltage is applied
(d) The arrow in the symbol of n-channel JEFTs
to the circuit. This is necessitated on account of
or MOSFETs will always point out of the
(a) Mismatches between the characteristics of the
centre of the symbol.
FETs APPSC Poly. Lect. 15.03.2020
(b) Difference between tolerance values of
Ans. (d) : Parameter of MOSFETs-
resistors used in the circuit even though they
are marked nominally equal. The transistor required the gate-source voltage (Vgs) to
(c) Variations in the operating voltage of the switch the device "OFF" The depletion mode
circuit. MOSFETs is equivalent to a Normally closed switch
(d) Both Mismatches between the characteristics For value of Vgs less than threshold voltage level the
drain current of an enhancement type MOSFETs is
of the FETs and difference between tolerance
0mA.
value of resistance used in the circuit even
though they are marked nominally equal There is no direct electrical connection between the gate
RPSC ACF & FRO 23.02.2021 terminal and the channel of MOSFET.
The arrow in the symbol of n-channel JFETs or Ans. (c) : A Junction field effect transistor is a voltage
MOSFET will not point out of the centre of the symbolcontrolled device i.e the output characteristics of the
n-channel JFET & MOSFET arrow is inside of the device are controlled by input voltage.
symbol. • JFET is a three terminal voltage control current
source device. The voltage applied across the gate is
used to control the current through the drain.
12. FET is a device which has
(a) high input impedance and is current
controlled
8. In a Common Gate MOSFET amplifier, the (b) low input impedance and is current controlled
phase shift between input and output voltages (c) high input impedance and is voltage
is : controlled
(a) 180° (b) 240° (d) low input impedance and is current controlled
(c) 0° (d) 300° RRB JE- 01.09.2019-3:00 Pm - 5:00 Pm
APPSC POLY. LECT. 14.03.2020 KVS TGT (WE)-2014
RRB SSE 21.12.2014, (Yellow)
Ans. (c) : In common source amplifier and source
follower circuits the input signal is applied to the gate of Ans. (c) : FET is a device which has high input
MOSFET. The type of amplifier is called as common impedance and voltage controlled.
gate amplifier, the phase shift between input and output Comparison of JFET and BJT-
voltage is 0º. For common source phase shift input and • JFET is better thermal stability but BJT is less
output is 1800. thermal stability.
9. The twin-well technology is usually used to • JFET is a high input impedance, BJT is a low input
fabricate : impedance.
(a) PMOS devices (b) NMOS devices • JFET is a high current gain, BJT has a low current
(c) CMOS devices (d) I2L devices gain.
APPSC POLY. LECT. 14.03.2020 • JFET has low voltage gain whereas BJT has high
voltage gain.
Ans. (c) : Twin well process provide separate
optimization of the n type and p type transistors. The • JFET has high intput impedance, BJT has high
twin well technology is usually used to fabricated in output impedance.
CMOS devices. 13. The MOSFET switch in its ON-state may be
10. MOSFET can be used as considered equivalent to
(a) resistor (b) inductor
(a) Current controlled capacitor
(c) capacitor (d) battery
(b) Voltage controlled capacitor TNPSC AE – 2019
(c) Current controlled inductor KVS TGT (WE)- 2014
(d) Voltage controlled inductor TRB Poly. Lect. -2012
Mizoram PSC IOLM -2018, Paper I Ans. (c) : In on state, there is a conducting channel
Nagaland PSC CTSE (Degree)-2018, Paper-I between drain and source. The structures of MOS like
Nagaland PSC CTSC (Degree) 2017, Paper I GATE (metal), Oxide (SiO ) layer and conductive
2
Nagaland PSC CTSE (Degree) -2015, Paper I channel. Hence it works as a capacitor.
RPCS Lect.-2011
ISRO Scientist Engg. 2009
14. In MOSFET devices the n-channel type is better
GATE-2001 than the p-channel type in the following respects
(a) it has better noise immunity
Ans. (b) : MOSFET acts like a MOS capacitor and it is
controlled by the input gate to source voltage. Hence, (b) it is faster
MOSFET, can be used as a voltage-controlled capacitors. (c) it is TTL compatible
BJT → Current controlled current source (d) it has better drive capability
JFET → Voltage controlled current source Nagaland PSC CTSE (Degree) -2015, Paper I
MOSFET → Voltage controlled capacitance source
Ans. (b) : In n-channel the current is due to electrons.
OP-amp → Voltage controlled voltage source Where is P-channel current is due to holes.
SCR → Current controlled voltage source. We know that the mobility of electron (µn)and hole (µP)
11. The JFET is a____.
(a) Current controlled current source
(b) Current controlled voltage source
(c) Voltage controlled current source
(d) Voltage controlled voltage source
Nagaland PSC CTSE (Degree)-2017, Paper-I electron mobility > hole mobility
RRB SSE 01.09.2015 Shift-I
KVS TGT (WE) - 2014 So, that n channel type faster than p channel type.

15. The threshold voltage of an n-channel Ans. (d) : According to Shockley equation
MOSFET can be increased by 2
(a) increasing the channel dopant concentration  V 
I D = I DSS  1 − GS 
(b) reducing the channel dopant concentration  VP 
(c) reducing the GATE oxide thickness
(d) reducing the channel length
GATE-1994
Ans. (a) : Threshold Voltage- The threshold voltage of
a MOSFET is defined as the value of gate to source
voltage which is sufficient to produce a surface Once, the pinch off occurs (VDS=VP), the current IDS
inversion layer when VDS= 0V saturates at a particular level IDSS, during which the
or device acts as a constant current source.
The voltage at which the surface of the semiconductor 18. The following statements are made for FETs
gets inverted to the opposite polarity is known as 1. In n-channel depletion mode MOS in the
threshold voltage active region, the control voltage VGS is
2qN A εsi ( 2φF + VSB ) negative.
Vth = VFB + 2φF + 2. NMOS in depletion mode is cut off for VGS =
Cox 0
VFB = Flat band voltage equal to φms 3. NMOS in enhance mode is cut off for VGS = 0
εsi = Permitivity of silicon 4. There is no path between source and drain in
NA = Substrate doping concentration the enhancement mode
φms = Energy difference between the fermi level and of these, the true statements are :
intrinsic fermi level in the semiconductor or fermi (a) 1 and 2 only (b) 1 and 3 only
voltage. (c) 3 and 4 only (d) 1, 3 and 4 only
Cox = oxide capacitance per unit area given by Eon/fon ISRO Scientist Engg.-2012
So, the threshold voltage of an n-channel MOSFET can Ans. (d) :
be increased by increasing the channel dopent
concentration.
16. The effective channel length of a MOSFET in
saturation decreases with increases in
(a) gate voltage (b) drain voltage
(c) source voltage (d) body voltage
Mizoram PSC Jr. Grade -2018, Paper-I in n-channel depletion mode MOS in the active Region.
TSTRANSCO AE-2018 The control voltage VGS is negative NMOS in enhance
GATE-2001 mode is cut off for VGS= 0V. There is no path between
Ans. (b) : Increase in drain voltage decreases the source and drain in the enhancement mode.
channel length. 19. If n number of MOSFETs with identical W/L
When VGS = 0 and VDS > 0 then, are connected in series, then equivalent W/L is
ID value depends at- given by:
• Number of majority carrier (a) (W/L)*n (b) (W/L)/n
• Length of channel (c) (W/L)*n2 (d) (W/L)/(n2)
• Size of channel in drain side ISRO Scientist Engg. -2015
• Drain to source voltage. Ans. (b) : 'n' MOSFET in series
ID =
VDS
=A
VDS W W
  =  /n
R pl  eq  L 
L
So, W/L is one of the major factor which decides the
Increase in drain voltage decrease the channel length in current driving capacity of the MOSFET.
saturation. When transistor are connected in series the in series the
Saturation mode VDS ≥ VGS − VTh ( VGS > VTh ) individual resistance gets added up and length becomes
n times and the resultant. W/L will be 1/n times that of
17. For a junction FET in the pinch off region, as the individual W/L
the drain voltage is increased, the drain current
(a) becomes zero (b) abruptly decreases 20. Depletion type MOSFET operates in :
(c) abruptly increases (d) remain constant (a) Depletion Model only
UPRVUNL AE-2016 (b) Enhancement Mode only
KVS TGT (WE)- 2016 (c) Both depletion and enhancement mode
MPPSC Forest Service Exam.2014
Mizoram PSC AE/SDO 2012, Papr-I
IES-1995 ISRO Scientist Engg.-2013
Ans. (c) : Depletion type MOSFET operates in P-channel enhancement MOSFET's Transfer
depletion and enhancement mode most circuit this an characteristics
enhancement mode MOSFETs, gate voltage towards its
drain voltage turns it on. in a depletion-mode MOSFET.
the device is normally on at zero gate-source voltage
such devices are used on load resistors in logic circuit.
21. For two identical n-channel JFET's connected
in parallel as shown in fig. below, the pinch-off P-channel depletion MOSFET's Transfer characteristics
voltage of equivalent JFET is:
23. For an n-channel enhancement MOSFET, ID

increases when:
(a) VGS = – VT (b) VGS = + VT
(a) Doubled (b) Becomes half
(c) VGS < VT (d) VGS > VT
(c) Remains same (d) None of the above
Ans. (d) : In N-channel E-MOSFET,ID = K(VGS–VT)2
Ans. (c) : For JFET’s connection, pinch of voltage does
not depends on connection (series or parallel). It only Drain current (ID) increases when VGS > VT
depends on its parameters as VP = qNDa2/2εs 24. The major distinction between a Field Effect
Hence, the pinch off voltage of equivalent JFET Transistor (FET) and a BJT is
remains same. (a) FET is unipolar
22. The transfer characteristic of the different (b) FET is more noisy
types of MOSFETs is shown below, where ID is (c) FET has lower input resistance
drain current and VGS is the gate-source (d) FET has very large gain bandwidth product
voltage, the correct combination of MOSFET TNPSC AE - 2018
w.r.t to transfer characteristics is Ans. (a) : The major distinction between a field effect
Type of MOSFET Transfer transistor (FET) and bipolar junction transistor is that
characteristics field effect transistor is unipolar device while BJT is a
(P) p-Channel bipolar device.
Enhancement 25. The main drawback of JFET is its
MOSFET (a) High input impedance
(Q) p-Channel (b) Low input impedance
Depletion (c) Higher noise
MOSFET (d) Lower gain
(R) n-Channel GPSC Asstt. Prof. 11.04.2017
Enhancement Ans. (c) : A JFET is a three terminal semiconductor
(S) n-channel device in which current conduction is one type of
Depletion carrier that is electrons or holes. The main drawback of
MOSFET JFET is its Higher noise.
(a) P-4, Q-2, R-1, S-3 (b) P-3, Q-2, R-4, S-1 26. Which statement about MOSFET is false?
(c) P-1, Q-3, R-2, S-4 (d) P-2, Q-4, R-3, S-1 MOSFETs can operate in
ISRO Scientist Engg. -2020 (a) depletion mode
Ans. (c) : P-1, Q-3, R-2, S-4 (b) enhancement mode
n- channel enhancement MOSFET–Transfer (c) both depletion & enhancement mode
characteristics (d) depletion only mode
Ans. (d) : A MOSFET can operate in depletion mode or
enhancement mode. It is a three terminal voltage
controlled power electronics device. MOSFET has
lower switching losses due to its unipolar nature less
n-channel depletion MOSFET– Transfer characteristics turn off time.
27. In a JFET, point of reference is
(a) drain (b) source
(c) gate (d) none of these
Ans. (b) : For JFET, the point of reference is source. 33. FET is a __________ device.
JFET operation involves the flow of majority carriers. (a) Unipolar (b) Bipolar
JFET has high input impedance. The FET is a 3 (c) Tripolar (d) None of these
terminal device consisting of source, drain and gate as Mizoram PSC IOLM -2018, Paper I
the terminals where the source is the input terminal, Ans. (a) : FET is a voltage driven/ controlled device the
drain is output terminal and the gate is mid terminal. output current is controlled by FET applied. It is a
28. Input gate current of a FET is unipolar device. It has a high input impedance.
(a) a few microampere (b) negligibly small 34. FET terminals are:
(c) a few milliampere (d) a few amperes (a) Base, Emitter, Collector
Mizoram PSC AE/SDO 2012-Paper-I (b) Gate, Base, Bulk
Ans. (b) : The input gate current of FET is closer to (c) Gate, Source, Base
negligibly smaller value. It is likely to zero. (d) Gate, Source, Drain
29. For enhancement only mode N-channel Mizoram PSC IOLM -2018, Paper I
MOSFET polarity of Vgs is Ans. (d) : A FET has three terminals named source
(a) -ve (b) +ve drain and gate. It is a voltage controlled device.
(c) zero (d) variable Source is the terminal; through which the majority
Mizoram PSC AE/SDO 2012-Paper-I charge carrier are entered in the FET. Drain is the
Ans. (b) : In case of enhancement n-channel MOSFET terminal through which the majority charge carriers exit
VGS and VDS both have positive polarity. from the FET.
Enhancement type MOSFET requires a gate-source
35. When the positive voltage on the gate of a p-
voltage (VGS) to switch the device "ON" The
enhancement mode MOSFET is equivalent to a channel JFET is increased, its drain current
normally open switch. (a) Increases (b) Decreases
(c) Remains the same (d) None of these
30. The best electronic device for fast switching is
(a) BJT (b) triac
(c) JFET (d) MOSFET Ans. (b) : Shockley's equation-
Ans. (d) : A MOSFET is operate at high frequency.
Hence MOSFET is high switching device among all
given options.
31. The pinch off voltage is
(a) VDS (max) of flat drain curve
(b) VDS (min) of flat drain curve 2
(c) VDS at VGS = 0V  V 
I D = I DSS  1 − Gs 
(d) VDS at VGS < 0V  Vp 
Mizoram PSC AE/SDO 2012-Paper-I 
According to Shockley's equation and characteristic
Ans. (a) : Pinch off voltage may refers to one of two
curves for a p-channel JFET, the drain current ID
different characteristic of a transistor. The pinch OFF
decreases with an increases positive gate source voltage
voltage is the value of VDS when drain current reaches
constant saturation value. (VGS).
36. Which of the following statement is true for an
n-MOSFET
(a) The drain and source are heavily doped p+
regions and the substrate or body is n-type.
(b) The drain and source are heavily doped n+
regions and the substance or body is p-type
32. MOSFET is used for (c) The drain and source are heavily doped n+
(a) regulator control regions and the substrate or body is n-type
(b) maintaining constant voltage (d) The drain and source are heavily doped p+
(c) automatic gain control regions and the substrate or body is p-type
(d) low input impedance UPPCL AE- 31.12.2018
Mizoram PSC AE/SDO 2012-Paper-I Ans. (b) : The construction of an n-MOSFET consist of
Ans. (a) : Power MOSFETs are commonly used in a p-type substrate and gates inverted to n-type which
automotive electronics, particularly as a switching channel is formed in strong inversion.
device in electronic control unit. It is a heavily doped n+ regions at drain and source.

37. The locus of pinch off voltage in an field Effect 42. Consider the following four common type of
Transistor (FET) is - transistors :
(a) Linearly increasing slope 1. Point contact transistor
(b) Parabolic 2. Bipolar junction transistor
(c) Linearly decreasing slope 3. MOS field effect transistor
(d) Exponentially decaying
4. Junction field effect transistor
UPPCL AE-16.11.2013
The correct arrangement of these transistors in
Ans. (b) : Pinch off voltage is the drain to source increasing order of input impedance is
voltage after which the drain to source current become
almost constant and JFET enters into saturation region (a) 1, 2, 4, 3 (b) 1, 2, 3, 4
and pinch off voltage become parabolic. (c) 2, 1, 3, 4 (d) 2, 1, 4, 3
38. Transfer characteristic of any MOSFET is TNPSC AE-2013
drawn between (VDS – drain to source voltage, Ans. (d) : MOS field effect has highest input impedance
VGS – Gate to source voltage, VGD - Gate to while BJT has lowest input impedance.
drain voltage, ID - drain current) Zin(mos) > Zin(JFET) > Zin(point) > Zin(BJT)
(a) VGD and ID (b) VGS and ID 43. When compared to a bipolar junction
(c) VDS and VGS (d) VDS and ID transistor (BJT) a junction field effect
UPPCL AE-16.11.2013 transistor (JFET)
Ans. (b) : Transfer characteristic of MOSFET is the (i) Is less noisy
graph between Gate to source voltage to drain current. (ii) Has less input resistance
For n-channel For P- channel (iii) Has a larger gain bandwidth product
(iv) Has current flow due to majority carriers only
Which of the following is correct
(a) (i) and (iv) (b) (ii) and (iii)
(c) (i), (ii) and (iii) (d) (i),(ii),(iii) and (iv)
39. Pinch-off voltage of Junction Field Effect MPPSC Forest Service Exam.-2014
Transistor (JFET) depends on Ans. (a) : A BJT is bipolar device there is a current
(a) Supply voltage flow both majority and minority charge carrier. Field
(b) Gate to source voltage effect, transistor are unipolar, only majority charge
(c) Drain to source voltage carrier flows. BJT is a current controlled device and
(d) Width of the original channel structure FET is a voltage controlled device. FET is less noisy
UPPCL AE-16.11.2013 and BJT is more Noisy.
Ans. (c) : The pinch off voltage of the JFΕT refers to 44. The N-channel MOSFET devices are preferred
the voltage applied between drain and source (with the over P-channel devices due to
gate voltage at zero volt) at which maximum current (a) N-channel devices being faster
flows. Operating with the drain/source voltage below (b) N-channel devices having higher packing
this value is closed to the "Ohmic Region" as the JFΕT density
will act rather like a resistor.
(c) N-channel devices consuming less power
40. The drain-source voltage at which drain (d) Both (N-channel devices being faster ) and
current becomes nearly constant, is called (N-channel devices having higher packing
(a) Barrier voltage (b) Breakdown voltage
density)
(c) Pick -off voltage (d) Pinch-off voltage
UJVNL AE-2016 MPPSC Forest Service Exam.-2014
Ans. (d) : The voltage at which drain current become Ans. (d) : The N-channel MOSFET device are
constant is known as drain source voltage or pinch off preferred over P-Channel devices due to N-channel
voltage. The pinch off voltage is a voltage below which device being faster and having higher packing density.
the transistor is turn off. In N-channel MOSFET, Majority of electrons as current
41. At room temperature, a possible value for the carrier.
mobility of electrons in the inversion layer of a 45. The lower turn off time of MOSFET as
silicon n-channel MOSFET is compared to BJT is due to
(a) 450 cm2/V-s (b) 1350 cm2/V-s (a) Positive temperature coefficient
2
(c) 1800 cm /V-s (d) 3600 cm2/V-s (b) Absence of minority carriers
TNPSC AE-2014 (c) On state resistance
BPSC Polytechnic Lecturer - 2014
GATE - 2010 (d) Input impedance
Ans. (b) : n-channel MOSFET is faster than the p- MPPSC Forest Service Exam.-2014
channel MOSFET. Mobility of electrons is always Ans. (b) : We know that BJT is a bipolar devices while
higher than the mobility of holes. MOSFET is unipolar. The current flow in BJT by
At room temperature, a possible value for the mobility minority and majority carrier. In MOSFET the current
of electrons in the inversion layer of a silicon n-channel flow through only majority carrier. Hence turn off time
MOSFET is 1350 cm2/V-s. will be less in MOSFET as compare to BJT.

46. When does the body bias effect occur in an n- (c) All free charges get removed from the channel
channel MOSFET? (d) Avalanche breakdown takes place
(a) When the Source voltage is less than Bulk Mizoram PSC Jr. Grade -2018, Paper-I
voltage KVS TGT (WE)-2016
(b) When the Source voltage is equal to or Ans. (c) : The channel length of a MOSFET in
greater than Bulk voltage saturation decreases with increase in drain voltage of
(c) When the Drain voltage is equal to the Bulk the MOSFET. As the Gate-voltage (–VGS) is made more
voltage negative, the width of the channel decreases until no
(d) When the Gate voltage is equal to the Bulk more current flows between the drain and the source.
voltage At this condition, the FET is said to be pinched-off. The
RPSC LECTURER-10.01.2016 voltage at which the channel closes is called the pinch-
Ans. (b) : The body bias effect occur in an n-channel off voltage (VP).
MOSFET when the Source voltage is equal to or greater The drain current remains constant with the drain voltage.
than Bulk voltage. 51. As compared to power MOSFET, a BJT has
47. The scaling factor of an MOS is α. Using (a) Lower switching losses but higher conduction
constant voltage scaling model, the gate area of losses
the device will be scaled as (b) Higher switching losses and higher
(a) 1/α (b) 1/α2 conduction losses
(c) 1/α3
(d) 1/α4 (c) Higher switching losses but lower conduction
Nagaland PSC CTSE (Degree)-2017, Paper-I losses
IES-2003 (d) Lower switching losses and lower conduction
losses
Ans. (b) : The gate area of MOSFET = LW KVS TGT (WE)-2016
1 Mizoram PSC IOLM-2010, Paper-II
The scaling factor = 2
α Ans. (c) : As compare to power MOSFET, a BJT has
48. In a JFET drain current is maximum when VGS higher switching losses but lower conduction loss
is power MOSFET is used at high frequency while BJT is
(a) zero (b) negative used at low frequency
(c) positive (d) Vpinch off 52. Choose the correct statement
TANGEDCO AE-2018 (a) MOSFET has positive temperature coefficient
Mizoram PSC Jr. Grade-2015, Paper-I (TC) whereas BJT has negative TC
MP PCS Forest Service exam-2014 (b) Both MOSFET and BJT have positive TC
Ans. (a) : Drain current, (c) Both MOSFET and BJT have negative TC
2 (d) MOSFET has negative TC whereas BJT has
 V  positive TC
I D = I DSS 1 − GS 
VP  Mizoram PSC IOLM-2010, Paper-II

where, ID = Drain current Ans. (a) : The equivalence circuit diagram of MOSFET
IDSS = Maximum value of current when can to converged into a resistance Hence MOSFET has
VGS = 0 positive temperature coefficient while BJT has negative
ID = IDSS temperature coefficient
VP = Pinch off voltage 53. Choose the correct statement
VGS = Gate to source voltage (a) Both MOSFET and BJT are voltage
49. Which of the following has the highest input controlled device (CDs)
resistance? (b) Both MOSFET and BJT are current CDs
(a) NPN transistor in CB configuration (c) MOSFET is a voltage CD whereas BJT is a
(b) PNP transistor in CE configuration current CD
(c) p-type channel MOSFET (d) MOSFET is a current CD whereas BJT is a
(d) n-type channel MOSFET voltage CD
Ans. (c) : MOSFET is a voltage controlled device while
Ans. (d) : n-type channel MOSFET has the highest
a BJT is a current controlled device MOSFET can be
input resistance.
converted into a equivalent resistance
54. The JFET can operate in
(a) depletion mode only
(b) enhancement mode only
(c) either depletion or enhancement mode at a
time
50. Pinch-off voltage for a FET is the drain voltage (d) both depletion or enhancement modes
at which simultaneously
(a) Significance drain current starts flowing RPSC Vice Principal ITI-2016
(b) Drain current becomes zero Mizoram PSC AE/SDO 2012-Paper-I
Ans. (a) : Junction gate field effect transistor (JFET) 58. For n-channel depletion MOSFET, the highest
can operate in depletion mode only. trans-conductance gain for small signal is at
JFET are three terminal semiconductor devices that can (a) VGS = 0V (b) VGS = Vp
be used as electrically controlled switches or resistors, (c) VGS = Vp (d) VGS = –Vp
JFET are exclusively voltage controlled in that they do
not need a biasing current. IES-2017
55. The output current versus input voltage Ans. (a) : Drain current equation-
transfer characteristics of an n-channel JFET 2
 V 
is such that there is I D = I DSS  1 − GS  ....(i)
(a) zero current flow at zero input voltage bias  VP 
(b) current flow only when a positive input differentiation of equation (i)
threshold voltage is crossed
(c) current flow only when a negative input cut- 2IDSS  VGS   ∂ID 
gm = 1 −  g m = 
off voltage bias is crossed VP  VP   ∂VGS 
(d) no cut-off input voltage
RPSC Vice Principal ITI-2016 the maximum value of gm occurs when VGS = 0
IES-2001 2I
g mo = DSS
Ans. (c) : The output current versus input voltage | VP |
transfer characteristic of an n-channel JFET is such that
there is current flow only when a negative input cut-off  V 
g m = g mo  1 − GS 
voltage bias is crossed.  VP 
gmo is the maximum transconductance at VGS = 0
the characteristics graph for a change in VGS is -
Transfer characteristic
56. Thermal runaway is not possible in FET
because as the temperature of the FET increase 59. The figure shown represents:
(a) mobility decreases
(b) trans-conductance increases
(c) drain current increases
(d) trans-conductance decrease
IES-2017, 2015, 2012,2001
Ans. (a) : FET contains a temperature coefficient at
high current level that prohibit the thermal runaway
phenomena that may occur in BJT.
If the temperature (T) increases, the charge carriers
mobility ( µ n or µ P ) ↓ and Ids ↓
So, Thermal runaway is not possible in FET because as (a) n-channel MOSFET
the temperature of the FET increases mobility (b) Enhanced-mode E-MOSFET
decreases. (c) p-Channel MOSFET
57. For JFET, the drain current ID is: (d) J-FET
1/ 2 IES-2016, 2000
 V   V 
(a) I DSS 1 − GS  (b) I DSS 1 − GS  Ans. (a) : The MOSFET formed in which the
 Vp   Vp  conduction is due to the channel of majority charge
 
3/ 2 2 carriers called electrons. When this MOSFET is
 V   V  activated as ON this condition results in the maximum
(c) I DSS 1 − GS  (d) I DSS 1 − GS 
 Vp   Vp  amount of the current How through the device. This
  type of MOSFET is defined as N-channel MOSFET.
IES-2017
Ans. (d) : Drain current ID for JFET
2
 V 
I D = I DSS 1 − GS 
 VP 
Where
IDSS →Drain to source saturation current
VGS → Gate to source voltage
VP → Pinch off voltage This symbol represents to n-channel MOSFET
60. In JFET, when operated above the pinch-off (d) Positive and equal to Fermi potential in
voltage, the magnitude
(a) Depletion region becomes smaller BPSC Asst. Prof. - 12.04.2022
(b) Drain current starts decreasing IES-2015, 2004
(c) Drain current remains practically constant Ans. (d) : When VGS crosses threshold voltage the
(d) Drain current increases steeply increase in depletion region width stops and charge on
IES-2015, 2014 layer is countered by mobile holes at the SiO2 interface.
This is called inversion because the mobile charges are
Ans. (c) : opposite to the type of charges found in the substrate. In
this case the inversion layer is formed by the electrons.
The Surface potential at the inversion layer is positive
due to majority carriers in the substrate which are holes.
63. What is an advantage of MOS Transistor
structure in integrated circuits?
(a) Faster switching
(b) Less capacitance
(c) Higher component density and lower cost
In JFET after pinch off the drain current becomes (d) Lower resistance
almost constant. According to Shockley’s equation and IES-2014
characteristics curves for a p-channel JFET, the Drain Ans. (c) : The main advantage of MOS transistor is that
current ID decreases with an increasing positive gate- it doesn't require input current to control the load. MOS
source voltage (VGS). The Drain current in zero when has very high packing density and lower cost reduction
VGS = VP in size, simple fabrication process etc.
Shockley's equation 64. Which of the following are the characteristics
2 of a Junction Field Effect Transistor?
 V 
I D = I DSS  1 − GS  1. High input resistance
 VP  2. Good thermal stability
When VGS = 0V 3. High current gain
then, 4. More noisy than bipolar junction transistor
ID = IDSS (Constant current) (a) 1 and 3 (b) 1 and 2
(c) 2 and 3 (d) 3 and 4
61. The zeners incorporated within the IES-2013
encapsulations of some MOSFETs are meant Ans. (b) : JFET has high input resistance because of it's
for internal biasing construction, Gate is reversed biased so
(a) Reducing the cost current flow through the gate is approximately zero. So
(b) Biasing the gate circuit input Impedance is very high. Temperature increase
(c) Self-protecting the device against transients and number of carrier increases but mobility not
(d) None of the above increase. So there is no chance of thermal runway. JFET
IES-2015 is less noisy than the BJT due to absence of minority
Ans. (c) : carriers.
• MOSFET is switch used in a circuit to provide smooth 65. A gate to drain connected enhancement mode
operation. Due to some external cause, the voltage MOSFET is an example of
across the MOSFET may suddenly rise above the (a) an active load
operating range resulting in MOSFET destruction. (b) a switching device
• To protect the MOSFET, zener diodes are connected (c) a three-terminal device
between the gate and source terminal of MOSFET This (d) a diode
is because zener diodes are voltage regulator devices. IES-2012
Nagaland PSC CTSE (Degree) 2018, paper-I
Ans. (a) :
62. In a MOS capacitance fabricated on a P-type

semiconductor, strong inversion occurs, when
potential is
(a) Equal to Fermi level
(b) Zero When drain and gate connected together, then the
(c) Negative and equal to Fermi potential in enhancement type MOSFET comes into ON state,
magnitude which act like an active load.
66. Consider the following statements related to Ans. (d) : CMOS technology is mainly used in digital
JFET: logic circuit construction, like microprocessor,
1. Its operation depends on the flow of microcontrollers, memory etc. The power dissipation is
minority carriers only. very low and it also has good speed of operation.
2. It is less noisy than BJT. 70. In a MOSFET, the transfer characteristics can
3. It has poor thermal stability
be used to determine which of the following
4. It is relatively immune to radiation.
The correct statements are device parameters:
(a) 1, 2, 3 and 4 (b) 1 and 2 only (a) Threshold voltage and output
(c) 2 and 4 only (d) 3 and 4 only (b) trans-conductance and output resistance
IES-2012 (c) Threshold voltage and trans-conductance
Ans. (c) : FET's operation depends on majority carrier (d) Trans-conductance and channel length
only. Due to this, there is less noise in FET compared to modulation parameter
BJT. JFET has high input impedance and low power IES-2008
consumption. JFETs are protected to radiation, JFET Ans. (c) : In a MOSFET the transfer characteristics can
has a negative temperature coefficient and higher be used to determine threshold voltage and trans-
temperature stability. conductance parameters of device.
67. 71. In n-channel enhancement MOSFET, at a fixed
drain voltage
(a) the drain current is maximum at zero gate
voltage and it decrease with applied negative
gate voltage
(b) the drain current has a finite value at zero gate
voltage and it increases or decreases with the
applied voltage of proper polarity
The above figure shows the symbol of (c) the drain current is zero at zero gate voltage
(a) p channel depletion MOSFET and it increases with the positive applied gate
(b) p channel enhancement MOSFET voltage
(c) complementary MOSFET (d) the drain current is zero for negative bias
(d) p channel JFET voltage to gate and it increases as the negative
IES-2009 gate bias is decreased in magnitude
Ans. (a) : Sikkim PSC SI (Mains)-2018
IES-2008
Ans. (c) : For the N-channel enhancement MOS
transistor a drain current will only flow when a gate
voltage (VGS) is applied to the gate terminal greater than
the threshold voltage (VTH). If drain voltage is fixed
The above figure shows the symbol of P channel then the drain current is zero at zero gate voltage and it
depletion MOSFET. increases with the positive applied gate voltage.
Where,
G → Gate
S → Source
D → Drain
correct for MOSFET?
(a) p channel MOS is easier to produce than n
channel MOS
(b) n channel MOS must have twice the area of p
channel MOS for the same ON resistance 72. Which one of the following is not a power
(c) p channel MOS has faster switching action MOSFET type?
than n channel MOS (a) Lateral construction (LMOSFET)
(d) p channel MOS has higher packing density
than n channel MOS (b) Lateral double diffusion construction
IES-2009 (LDMOSFET).
Ans. (a) : P-channel MOS is easier to produce than n- (c) T construction (TMOSFET)
channel MOS, Because the fabrication of p-channel (d) Enhancement mode construction
MOS is much easier than the n-channel MOS. (EMOSFET).
69. Which of the following devices is used in the IES-2008
microprocessors? Ans. (d) : EMOSFET or enhancement mode
(a) JFET (b) BJT construction is not a power MOSFET type. While
(c) MOSFET (d) CMOS LMOSFET, LDMOSFET and TMOSFET are a power
IES-2009 MOSFET.
73. How is an N-channel junction Field Effect Ans. (b) :
Transistor operated as an amplifier?
(a) With a forward bias gate-source junction
(b) With a reverse bias gate-source junction
(c) With an open gate-source junction
(d) With a shorted gate-source junction
IES-2007
Ans. (b) :
For binary 1 or binary 0 input, one transistor is on and
another is OFF
Input P-MOS N-MOS Output
0 ON OFF 1
1 OFF ON 0
76. Match List-I (Semiconductor Device) with List-
II (Symbol Used) and select the correct answer
The cross section diagram above shown an -N-type using the codes given below the lists:
semiconductor channel with a p-type region called the List-I List-II
gate diffusion in to the N-type channel forming a
reverse bias gate source junction and it is this junction A. n-p-n transistor 1.
switch forms the depletion region around the gate area
when no external voltage are applied JFET are therefore
known of depletion mode devices.
FETs when compared to BJTs have B. SCR 2.
1. high input impedance
2. current flow due to majority carriers
3. low input impedance
4. current flow due to minority carriers
Which of the statements given above are C. FET 3.
correct?
(a) 1 and 4 (b) 2 and 3
(c) 3 and 4 (d) 1 and 2
IES-2006
Ans. (d) : Comparison between FETs and BJTs D. MOSFET 4.
BJTs FETs
(i) Low input (i) high input impedance
impedance Codes:
(ii) Current flow due (ii) Current flow due to A B C D
to majority and majority charge carriers (a) 2 3 4 1
minority charge as either holes or (b) 4 1 2 3
carriers. electrons. (c) 2 1 4 3
(iii)High voltage gain (iii)Low voltage gain High (d) 4 3 2 1
low current gain current gain. IES-2005
(iv)High output (iv) output impedance Ans. (a)
impedance
Component Symbol
(v) Medium (v) High switching time
switching time (a) NPN Transistor
75. Consider the following statements related to a
CMOS (Complementary metal oxide
semiconductor) inverter:
1. It combines an n-channel and a p-channel (b) SCR
MOS transistor.
2. For binary 1 input, both transistors are
OFF
3. For binary 0 input, both transistors are (c) FET
ON.
4. Whatever is the state of input, one
transistor is ON while the other is OFF.
correct? (d) MOSFET
(a) 1, 2, 3 and 4 (b) 1 and 4
(c) 1, 2 and 3 (d) 3 and 4
IES-2005
77. A MOSFET device has both n+-type source and 80. A CMOS amplifier when compared to an N-
drain, and the drain current flows only when channel MOSFET, has the advantage of
gate to source voltage exceeds +2.0 V. Which of (a) Higher cut-off frequency
the following conclusions can be drawn about (b) Higher voltage gain
the device? (c) Higher current gain
1. The device is an n-channel MOSFET (d) Lower drain current from the power supply,
2. It is enhancement type MOSFET thereby less dissipation
3. It has threshold voltage of value +2.0 V IES-2003
4. The channel conductance is determined by
hole mobility Ans. (d) : In a CMOS, only one MOSFET is switched
Select the correct answer using the code given on at a time thus there is no path from voltage source to
below: ground so that a current can flow. Thus compared to n-
(a) 1 and 3 (b) 1, 2 and 3 channel MOSFET has the advantage of lower drain
(c) 2 and 4 (d) 1, 2, 3 and 4 current drain from the power supply thereby causing
IES-2005, 2000 less power dissipation.
Ans. (b) : 81. Match List-I with List-II and select the correct
• When a MOSFET device has both n+ type source answer using the codes given below the lists:
and drain are known as N-MOSFET device. List-I
Enhancement MOSFET can be closed as normally A. OFF
off device that is they only conduct when a suitable B. Linear region
gate to source positive voltage applied, unlike C. Non-linear region
depletion type MOSFET which are normally on d. Saturation region
device conducting when the gate voltage is zero.
List-II
• In enhancement type MOSFET drain current flows
1. Vgs > Vth, and Vds < (Vgs – Vth)
if gate to source voltage exceeds from threshold
voltage like +2.0V. 2. Vgs > Vth, and Vds > (Vgs – Vth)
• The channel conductance is determined by electrons 3. Vgs > Vth
mobility in N-MOSFET channel. 4. Vgs < Vth
78. The voltage gain of a given common source Codes:
JFET amplifier depends on its A B C D
(a) input impedance (a) 2 3 1 4
(b) amplification factor (b) 4 1 3 2
(c) dynamic drain resistance (c) 2 1 3 4
(d) drain load resistance (d) 4 3 1 2
Nagaland PSC(Degree) 2018, Paper-II IES-2002
Nagaland PSC CTSE (Degree)-2017, Paper-II Ans. (b) : Suppose that give condition is for n-
IES-2004 channel E-MOSFET-
V OFF Vgs < VTh
Ans. (b) : Voltage gain A V = i = −g m ( R o  R L )
Vo Linear region Vds < (Vgs -Vth)
Non linear region Vgs > Vth
−µR d
AV = Saturation region Vds > (Vgs -Vth)
rd + R d 82. In a MOS transistor, the gate source input
if Rd >> rd impedance is
−µR d 1. lower than the input impedance of a BJT
then AV = 2. higher than the input impedance of a BJT
Rd
3. lower than the input impedance of a JFET
A V  −µ 4. higher than the input impedance of a JFET
The voltage gain of common source JFET amplifier Select the correct answer using the codes given
depend upon its amplification factor. bellow:
79. How can the channel width in a junction field (a) 1 alone (b) 2 and 3
effect transistor be controlled? (c) 4 alones (d) 2 and 4
(a) By two back-biased p-n junctions IES-2001
(b) By the length of the source Ans. (d) : As the input current of FET is reverse-
(c) By the length of the drain biased, therefore it has higher input impedance than
(d) By the lengths of both the source and the drain
BJT whose input circuit is forward biased. The input
IES-2004
impedance of FET is of the order of 100MΩ. In
Ans. (a) : Field effect transistor is a three terminal
device electronic component that uses electric field to MOSFET, As gate forms a capacitor, therefore,
control conductivity of a channel. output current is negligible gate current flows whether positive or
proportional to the input voltage applied to its gate negative voltage applied to the gate consequently, the
terminal, channel width can be varied by changing the input impedance of MOSFET is very high, ranging
voltage applied at the gate. from 104MΩ to 106MΩ.

83. Match List-I (Structures/characteristics) with 85. In a biased JFET, the shape of the channel is as
List-II (Reasons) in respect of JFET and select shown in the given figure.
the correct answer using the codes given below
the lists:
List-I List-II
A. n-channel JFET 1. Reverse bias
is better than p- increases along
channel JFET the channel
B. Channel is 2. High electric
wedge shaped field near the because
drain and (a) it is the property of the material used
directed
(b) the drain end is more reverse biased than
towards source
source end
C. Channel is not 3. Low leakage
completely current at the (c) the drain end is more forward biased than
closed at pinch gate terminal source end
off (d) the impurity profile varies with the distance
D. Input impedance 4. Better from source
is high frequency IES-1999
performance Ans. (b) : the depletion regions are wedge-shaped,
since µn > µp being larger at the drain end than at the source end this
Codes: is because the gate to drain channel reverse bias at the
A B C D drain end of the gate is larger than the reverse bias at the
(a) 4 1 2 3 source end of the gate.
(b) 4 2 1 3 86. The threshold voltage of an n-channel
(c) 3 1 2 4 enhancement mode MOSFET is 0.5 V. When
(d) 3 2 1 4 the device is biased at a gate voltage of 3V.
IES-2000 Pinch-off would occur at a drain voltage of
Ans. (a) : (a) 1.5 V (b) 2.5 V
• In JFET, mobility of electrons is more than mobility (c) 3.5 V (d) 4.5 V
of Holes, hence n-channel JFET is better than p- IES-1998
channel JFET. Ans. (b) : Given,
• The channel is wedge shaped due to different value VT = 0.5V, VGS = 3V
of reverse biase voltage across the channel. Pinch off occurs at voltage,
• Channel is not completely closed at pinch off (IDS= VDS = VGS –VT
Constant) at high electric field near the drain and
VDS = 3 – 0.5
directed toward source.
VDS = 2.5V
• Due to input current reverse bias. Hence its input
impedance very high. 87. Consider the following statement:
84. Consider the following devices: The threshold voltage of a MOSFET can be
1. BJT in CB mode lowered by
2. BJT in CE mode 1. using a thinner gate oxide.
3. JEET 2. reducing the substrate concentration
4. MOSFET 3. increasing the substrate concentration
The correct sequence of these devices in Of these statements
increasing order of their input impedance is (a) 3 alone is correct (b) 1 and 2 are correct
(a) 1, 2, 3, 4 (b) 2, 1, 3, 4 (c) 1 and 3 are correct (d) 2 alone is correct
(c) 2, 1, 4, 3 (d) 1, 3, 2, 4 IES-1997
IES-1999 Ans. (c) : The threshold voltage of a MOSFET can be
Ans. (a) : lowered by using a thinner gate oxide and increasing the
• Input impedance of CB mode of BJT is low (approx substrate concentration.
→ 100Ω) 88. An N-channel JFET has IDS whose value is
• Input impedance of CE mode of BJT is moderate (a) Maximum for VGS = 0, and minimum for VGS
(approx → 800Ω) = negative and large
• JFET's input current is reverse biased therefore it (b) Minimum for VGS = 0, and maximum for VGS
has higher input impedance in the order of 106Ω. = negative and large
• MOSFET's gate form capacitor, therefore negligible (c) Maximum for VGS = 0, and minimum for VGS
gate current flow whether positive or negative = positive and large
voltage applied to the gate consequently, the input (d) Minimum for VGS = 0, and maximum for VGS
impedance is very high, ranging from 1010Ω to = positive and large
1013Ω. IES-1997
Ans. (a) : For an N-channel JFET has IDS whose value (c) zero drain current
is maximum for VGS= 0, and minimum for VGS = (d) gate current equal to the drain current
negative and large. IES-1994
Ans. (c) : For an n-channel JFET, having drain source
voltage constant if the gate source voltage is increased
pinch-off would occur for zero drain current
92. Consider the following statements associated
with bipolar junction transistor and junction
gate FET?
89. The output characteristics of FET is given in 1. The former has higher input impedance
the figure in which region is the device biased than the latter.
for small signal amplification? 2. The former has higher frequency
capability than the latter.
3. The latter has lower noise figure than the
former.
4. The latter has higher power rating than the
former.
Of these statements.
(a) AB (b) BC (a) 1 and 2 are correct (b) 2 and 3 are correct
(c) CD (d) BD (c) 3 and 4 are correct (d) 1 and 4 correct
IES-1995 IES-1993
Ans. (b) : Ans. (b) :
• FET is high input impedance and BJT is low input
impedance.
• BJT has higher frequency capability than FET.
• FET has low noise figure compared to BJT
• FET has lower power handling capacity due to small
in size compared.
Small signal amplifier operation is in constant current • FET has low noise level than BJT.
region or saturation region. • FET has better thermal stability than BJT.
90. The output V-I characteristics of an 93. In modern MOSFETs, the material used for
enhancement type MOSFET has the gate is
(a) only an ohmic region (a) high purity silicon
(b) only a saturation region (b) high purity silica
(c) an ohmic region at low voltage value (c) heavily doped polycrystalline
followed by a saturation region at higher (d) epitaxial grown silicon
voltages.
IES-1993
(d) an ohmic region at larger voltage values
preceded by a saturation region at lower Ans. (c) : In Modern MOSFET's material used for gate
voltages. is heavily doped polycrystalline to reduce threshold
TSPSC Manager (Engg)-2015 voltage. A MOSFET sensor comprises three layer a
ISRO Scientist Engg.2008, IES-1994 silicon semiconductor, a silicon oxide insulator and a
catalytic metal (usually palladium, platinum iridium, or
Ans. (c) : rhodiom) also called the gate.
94. The main advantage of CMOS is its
(a) Low power consumption
(b) High power rating
(c) Small signal operation
(d) Fast switching capability
Kerala PSC Lecturer (NCA) 04.07.2017
Ans. (a) : The main advantage of CMOS is the low
The output, V-I characteristics of an enhancement type power consumption. In CMOS both E-MOSFET are
MOSFET has an ohmic region at low voltage value connected in series as result at the quiescent current
followed by as saturation region of higher voltage this is comes from the non conducting device and since the
evident by figure IDSS2 is greater then IDSS1 as VGS2 > input resistance non conducting E-MOSFET is very
VGS1, IDSS3 is greater than IDSS2 as VGS3 > VGS2. high typically in mega ohm the input power
91. For an n-channel JFET, having drain source consumption is low.
voltage constant if the gate source voltage is 95. MOSFET uses the electric field of
increased (more negative) pinch-off would (a) Gate capacitance to control the channel
occur for current.
(a) high value of drain current (b) Barrier potential of PN junction to control the
(b) saturation value of drain current channel current.
(c) Both (a) and (b) (c) an increase in substrate leakage current
(d) None of these (d) an increase in accumulation capacitance
RPSC VP/Suptd. ITI 05.11.2019 Nagaland PSC CTSE (Degree)-2017, Paper-II
Ans. (a) : The metal - oxide - semiconductor. field - Ans. (a) : If fixed positive charges are present in the
gate oxide of an n-channel enhancement type MOSFET,
effect transistor, also known as metal - oxide.
it will lead to a decrease in the threshold voltage.
Semiconductor transistor (MOSFET) uses the electric
Threshold voltage- It is the minimum gate to source
field of Gate capacitance to control the channel current. voltage required at which the channel formation takes
96. In CMOS technology, shallow P-well or N-well place and a low resistance conducting path between
regions can be formed using source and drain formed.
(a) low pressure chemical vapour deposition 101. Body effect in MOSFET's results in
(b) low energy sputtering (a) Increase in the value of trans conductance
(c) low temperature dry oxidation (b) Change in the value of threshold voltage
(d) low energy ion-implantation (c) Decrease in the value of trans conductance
RPSC VP/Suptd. ITI 05.11.2019 (d) Increase in the value of output resistance
Ans. (d) : In complementary metal oxide semiconductor IES-2012
(CMOS) technology, shallow P-well or N-well regions Ans. (b) : Body effect in MOSFET’s results in change
can be formed using low energy ion implantation because in the transistor threshold voltage (VT) resulting from a
it provides independent control of close and depth. voltage source and body.
97. Flat band voltage of MOSFET is defined as the 102. Conductivity modulation is a phenomenon
applied gate voltage such that: which occur in
(a) There is no band bending in the semiconductor. (a) Power MOSFET
(b) Net space charge in this region. (b) GTO thyristor
(c) Both (a) and (b) (c) IGBT
(d) None of these (d) Power bipolar transistor
Ans. (a) : Conductivity modulation is a phenomenon
Ans. (c) : Flat band voltage MOSFET is defined as the which occurs in power MOSFET.
applied gate voltage such that, there is no band bending • Conductivity modulation is a process of doping to
in the semiconductor and net space charge in this increase conductivity of semiconductor.
region. • In MOSFET the drain current is controlled by the gate
98. When the frequency of the input signal to a voltage and only kind of charge carriers conduct in
CMOS gate is increased, the average power MOSFET hence it is a unipolar device.
dissipation 103. In FET thermal runway not occurs due to
(a) does not change (b) increases ______.
(c) decreases (d) decreases exponentially (a) Mobility increases with temperature
TSPSC Manager (Engg.) - 2015 (b) Mobility decreases with temperature
(c) Mobility remains constant
Ans. (b) : When the frequency of the input signal to a (d) Not related mobility
CMOS gate is increased the average power dissipation AAI-2015
increases. The power radiation pattern of CMOS is
Ans. (b) : The thermal runway is not possible in FET
directly proportional to the frequency. because as the temperature of the FET increases, the
99. JFET input op amps differ from Bipolar input
D 
op amps in the sense that mobility decrease  = VT  .
(a) they have much higher input impedance and  µ 
much lower input bias currents • Since the current is decreasing with an increase in
(b) they have extremely high CMRR and Slew temperature, the power dissipation at the output
rate ratings terminal of a FET decreases hence there is not possible
(c) they are capable of single supply operation of thermal runway at the output of FET.
(d) they have extremely low offset voltages 104. In JFET above pinch of voltage, if VD
increases, then ID ______.
(a) Increase (b) Decrease
Ans. (a) : A JFET amplifier has large input impedance (c) constant (d) can't predict
as compare to bipolar junction transistor. Due to high NPCIL-2015
input impedance it has lower input bias current. Ans. (c) : In JFET after pinch off the drain current
100. If fixed positive charges are present in the gate becomes almost constant. According to shockley's
oxide of an n-channel enhancement type equation and characteristics curves for a p channel
MOSFET, it will lead to JFET, the drain current ID decreases with an increases
(a) a decrease in the threshold voltage positive gate-source voltage (VGS). The drain current is
(b) channel length of modulation zero when VGS = VP

105. VT in MOSFET increases if tox _____. Ans. (b) : FET amplifiers have low gain bandwidth
(a) Increase (b) Decrease product due to the junction capacitive effects and
(c) No effect (d) 1st increases then decreases produce more signal distortion except for small signal
NPCIL-2015 operation.
Ans. (a) : VT in MOSFET increases if tox is increases. • Disadvantage of FET over BJT.
The threshold voltage can be reduced by increasing the • FET has relatively small gain bandwidth product
potential of the channel for the same gate-source compare to BJT
voltage. • FET suffers from greater susceptibility to damage
106. The two basic types of field effect transistors and hence requires careful handling.
(FET) are: • Advantages of FET over BJT-
(a) NPN and PNP • It is a high input impedance device about 100MΩ
(b) germanium and silicon • It has no offset voltage when used as switch unlike
(c) inductive and capacitive BJT
(d) N and P channel • It is a majority carriers device.
RRB SSE-03.09.2015, Shift-III • FET provides greater thermal stability compare to BJT
Ans. (d) : The two basic types of field effect transistors 110. A switched mode power supply operating at 20
(FET) are N-channel and P-channel. Due to the fact that kHz to 100 kHz range used as the main
electrons move faster than holes, n-channel JFET are switching element is
more common than p-channel JFET. (a) Thyristor (b) MOSFET
(c) Triac (d) UJT
Ans. (b) : MOSFET is a power electronics device
which is used for high frequency application.
Hence in SMPS MOSFET is used.
111. A junction FET can be used a voltage variable
resistor
107. In an FET, which of the following has the (a) at pinch-off condition
highest input impedance? (b) beyond pinch-off voltage
(a) Common source (b) Common drain (c) well below pinch-off condition
(c) Common gate (d) All junction (d) for any value of VDS.
DMRC AM S&T-2020 TRB Poly. Lect. -2012
IES-2009
Ans. (b) : Common drain configuration-
Ans. (c) : A field effect transistor works as a voltage
The common drain or source follower configuration has variable resistor in the ohmic region. It works as an
the highest input impedance and low output impedance.
amplifier in the saturation region. Hence below pinch
Common source configuration- off values it can also used as variable resistors.
• This is the most common mode of operation of the
112. To create CMOS technology, NMOS and
FET due to its high input impedance and good voltage
PMOS transistors are fabricated on:
amplification as such common source amplifiers are
(a) same metal layer
widely used.
(b) different metal layer
Common gate configuration-
(c) the same substrate
• The common gate has low input impedance but a high (d) different substrate
output impedance this type of FET configuration can be UPMRC AM - 2020
used in high frequency circuits.
Ans. (c) : To create CMOS technology NMOS and
108. Thin gate oxide in a CMOS process is PMOS transistors are fabricate on the same substrate to
preferably grown using− accommodate both NMOS and PMOS devices special
(a) Ion implantation (b) Wet oxidation regions must be created in which the semiconductor
(c) Dry oxidation (d) Epitaxial deposition type is opposite to the substrate type.
RRB JE-01.09.2019, 3:00 PM – 5:00 PM 113. MOSFET operating in the saturation region
Ans. (c) : Thin gate oxide in a CMOS process is behaves as:
preferably grown using dry oxidation. Dry oxidation (a) voltage source (b) capacitor
produces thin oxide which is for gate and wet oxidation (c) current source (d) resistor
produces fox (filed oxide) to insulated to active UPMRC AM - 2020
transistor. Ans. (c) : MOSFET acts as a constant current source in
109. In FET compare to BJT the gain BW product the saturation region. This is because after increasing
is VDS to such a level that pinch-off occurs the gate the
(a) High (b) Low drain voltage lose its control over the current following.
(c) same (d) not related So, beyond that value of VDS the current is almost
BEL-2015 constant.
114. Which type of following biasing is used in case 119. In circuits fabricated by n-tub process, for
of JFET circuit to bias the device against device electrical isolation between NMOSFETs and
parameter variation ? PMOSFETs in the IC :
(a) Fixed bias circuit (a) both p-type and n-type substrates are
(b) Self bias circuit grounded
(c) Voltage divider bias circuit (b) p-type substrate is grounded and n-type
(d) Drain to Gate bias circuit substrate is connected to the most positive
MPSC HOD Govt. Poly. -2013 part of the circuit
Ans. (c) : A voltage divider is a simple series resistor (c) n-type substrate is grounded and p-type
circuit. Its output is a fixed friction of its input voltage. substrate is connected to the most positive
This circuit is used in JFET circuit analysis. part of the circuit
115. In a MOSFET gate, voltage controls: (d) n-type substrate is grounded and p-type
(a) Drain current (b) Source voltage substrate is connected to the most negative
(c) Drain voltage (d) Threshold voltage part of the circuit
LMRC AM (S&T)-13.05.2018
DRDO-2009
Ans. (a) : MOSFET considered as a voltage controlled
device because the drain current is controlled by the Ans. (b) : In circuits fabricated by n-type process for
gate voltage. electrical isolation between NMOSFETs and
116. An N-chanel enhancement mode MOSFET PMOSFET in the ICs P-type substrate is grounded and
with threshold voltage of 1 V is biased at VGS =n-type substrate is connected to the most positive part of
2 V and VDS = 2 V. If the drain voltage is circuits.
doubled to 4 V, the drain to source current will120. In a MOSFET, the pinch-off voltage refers to
(a) double (b) more than double (a) drain-to-source voltage at which drain-to-
(c) increase only slightly (d) become half source current is zero
BSNL (JTO)-2001 (b) gate-to-source voltage at which gate-to-
Ans. (b) : Given, source current is zero
VT = 1V, VGS = 2V, VDS = 2V (c) drain-to-source voltage at which gate-to-
ID = k (VGS –VT)2 source current is zero
ID = k (2–1)2 (d) gate-to-source voltage at which drain-to-
ID = k source current is zero
When VDS = 4V BSNL(JTO)-2009
then IDS = ? Ans. (d) : Pinch-off voltage-
Q VDS > (VGS – VTH) then IDS is more then double.
• In junction field effect transistor
117. To double the drain current of an N-channel (JFTs) pinch off voltage refers to the threshold voltage
enhancement mode MOSFET biased in
below which the transistor turns off.
saturation
(a) Channel length should be doubled. •Pinch off voltage refers to gate-to source voltage at
(b) Channel width should be halved which drain to source current is zero.
(c) Channel length should be halved • If we increase the voltage Vd above pinch- off voltage
(d) Oxide thickness should be doubled then ID remains constant.
BSNL (JTO)-2002, 2001121. Consider the following statements for Poly-Si
Ans. (c) : To double the drain current of an N-channel deposition:
enhancement mode MOSFET biased in saturation then 1. Poly-Si layer is used for gate electrode of
channel length should be halved. MOSFET because it has similar lattice
118. The high-frequency C-VGS characteristics of a constants with SiO2.
MOSFET is shown in figure below (VDS = 0). 2. Poly-Si layer used for gate electrode of
MOSFET for the better mechanical
stability due to different thermal expansion
coefficients.
3. In VLSI circuits, interconnects can be
In the curve, the accumulation condition is completed in one or two metal levels.
shown by the point : 4. Poly-Si is used for short interconnects.
(a) p (b) q Which of the above statements are correct?
(c) s (d) t (a) 1 and 2 only (b) 2 and 3 only
DRDO-2009 (c) 1 and 4 only (d) 2, 3 and 4 only
Ans. (d) : ESE-2021
Ans.(d) : Poly-si layer used for gate electrode of
MOSFETs for the better mechanical stability due to
different thermal expansion coefficients.
in VLSI circuits. Interconnects can be completed in one
In the curve, the accumulation condition is shown by or two metal levels. Poly-si is used for short inter
the point at 't'. connects.
122. Which of the following statements is true? A 126. Which of the following holds FALSE for
CMOS inverter is made using : MOSFETs?
(a) Two n-MOS transistors (a) There is no direct electrical connection
(b) Two p-MOS transistors between the gate terminal and the channel of
(c) One n-channel and one p-channel JFET a MOSFET.
(d) Using one n-MOS transistor and one p-MOS (b) For values of VGS less than the threshold
transistor. level, the drain current of an enhancement
BSNL(JTO)-2002 type MOSFET is 0 mA.
(c) It is the insulating layer of SiO2 in the
Ans. (d) : A CMOS inverter is made using one n-MOS
MOSEFT construction that accounts for the
transistor and one p-MOS transistor when a high
very desirable high input impedance of the
voltage (  Vdd ) is given of input terminal (A) of the device.
inverter, the p-MOS becomes open circuits and n-MOS (d) The arrow in the symbol of n-channel JEFTs
switched OFF so the output will be pulled down to VSS. or MOSFETs will always point out of the
When a low level voltage applied to the inverter, the n- centre of the symbol.
MOS switched OFF and p-MOS switched ON. APPSC Poly. Lect. 15.03.2020
123. For IGBT, which of the following statement is Ans. (d) : n-channel JFET & MOSFET, Arrow is
true? inside.
(a) Switching speed of IGBT is more than bipolar 127. A switched mode power supply operating at 20
transistor KHz to 100 KHz range uses _____ as the main
switching element.
(b) IGBT is a current-controlled device
(a) MOSFET (b) Triac
(c) On-state collector-emitter voltage is less than (c) Thyristor (d) UJT
that of bipolar junction transistor Kerala PSC Lecturer (NCA) 04.07.2017
(d) It combines voltage control features of Ans. (a) : A MOSFET is a switched mode power
MOSFET gate and high power capability of supply that operate deliberately at the range of 20 kHz
bipolar transistor to 100 kHz as it main switching element.
BSNL (JTO)-2006 128. The variation of trans-conductance of FET is
Ans. (d) : IGBT is a voltage controlled device. proportional to
Switching speed of IGBT is Less than that of bipolar (a) IDS (b) I 2DS
transistors.
On state collector-emitter voltage is more than that of (c) I DS (d) I/IDS
bipolar junction transistor. It combine voltage control TNPSC AE-2013
feature of MOSFET gate and high power capability of Ans. (c) : The current for a MOSFET in saturation is
bipolar transistor. given by
I D = K n ( VGS − Vth )
2
124. In the saturation region, the JFET transfer
characteristics are VGS = Gate to source voltage
(a) exponential (b) linear Vth = Threshold voltage
(c) parabolic (d) hyperbolic Taking the square root of the above equation, we get
TNPSC AE - 2018 I D = K n ( VGS − Vth ) …………..(i)
Ans. (c) : In the saturation region, the JFET transfer Now, the transconductance is calculated as-
characteristics are parabolic. Between ID and VGS can be g = ∂I D = 2K ( V − V ) ………..(ii)
∂VGS
m n GS th
approximate by the parabola.
125. The speed power product for static CMOS is: Evaluating (VGS-Vth) from equation (i) and putting it in
(a) Sp = CV equation (ii), we get
(b) Sp = C2V I
(c) Sp = CV2 g m = 2K n . D
(d) Sp = dependent on frequency Kn
TNTRB AE– 2017 g m = 2 K n .ID
Ans. (c) : Speed (propagation delay) and power
∴ g m ∝ ID
consumption are the two most important performance
parameters of a digital IC. A simple way of measuring 129. Which of the following parameters are effected
and comparing the overall performance of an IC family due to short channel MOSFET geometry
is the speed-power product. I. Mobility of carriers
SP = t P D P II. Threshold voltage
For static CMOS - III. Drain Current
(a) Only I (b) Only III
P fCV 2
SP = = = CV 2 (c) Both I & III (d) I, II & III
f f UPRVUNL AE– 11.06.2014
Ans. (d) : When the source and drain depletion layer Ans. (b) : Drain resistance
widths become equal to the channel length of MOSFET, V
then the condition is known as short channel geometry rDS = DS for given VGS
of MOSFET. It effects mobility of carriers , threshold ID
voltage and drain current. VDS
130. The transit time of the current carries through rDSon = with VGS = 0
ID
the channel of a JFET decides its ______
characteristic Means rDS on is possible with VGS = 0 and VDS= 0
(a) source (b) drain For n-channel JFET-
(c) GATE (d) source and drain Offers minimum ON resistance when → VGS is +Ve
GATE-1994 and large and voltage
Ans. (b) : The transit time of the current carries through VDS is very small.
the channel of a JFET decides its drain characteristics.133. In a JFET
JFET are three terminal semiconductor devices that can List-I List-II
be used as electronically controlled switches or resistors A. The pinch-off 1. The channel
or to build amplifiers. voltage decreases doping is
reduced
B. The 2. The channel
transconductance length is
increases increases
C. The transit time of 3. The
the carriers in the conductivity
• JFET has a large input impedance (108 ohms) channel is reduced of the channel
• JFET was first patented by Heinrish welker in 1945 is increased
AD. 4. The channel
2 length is
 VGS  reduced
• I DS = I DSS 1 − 
 VP  5. The GATE
area is
2IDSS  VGS  reduced
• gm = 1 − 
| VP |  VP  GATE-1995
Where, gm = Transconductance. Solution : A - 1, B - 3, C - 4
Vp = Pinch of voltage. • The pinch-off voltage decreases → The channel
doping is reduced.
131. The break down voltage of a transistor with its
base open is BVCEO and that with emitter open • The Transconductene increases → The conductivity
is BVCBO, then of the channel is increased
(a) BVCEO = BVCBO I
(b) BVCEO > BVCBO gm = D VDS = constant
VGS
(c) BVCEO < BVCBO
(d) BVCEO is not related to BVCBO • The transit time of the carriers in the channel is
GATE-1995 reduced → The channel length is reduced.
Ans. (c) : The break down voltage of a transistor with 134. For an n-channel enhancement type MOSFET,
its base open is BVCEO is less than emitter open is if the source is connected at a higher potential
BVCBO the BVCEO < BVCBO. than that of the bulk (i.e. VSB > 0), the threshold
The given voltage ratings are reverse breakdown voltage VT of the MOSFET will
voltage BVCEO this voltage between the collector and
emitter with base open BVCBO, voltage from collector to (a) remain unchanged (b) decrease
base with emitter open. (c) change polarity (d) increase
GATE-2003
Ans. (d) : VT = VTO + γ  φS + VSB − φS 
VSB = Source to body voltage
VTO = Threshold voltage at VSB = 0
132. An n-channel JFET has a pinch-off voltage VP= φ = 2V ln N A →Surface potential
S T
–5V, VDS(max)=20V, and gm=2mA/V. The min ni
'ON' resistance is achieved in the JFET for
(a) VGS = –7V and VDS = 0V V T = Voltage equivalent of temperature
(b) VGS = 0V and VDS = 0V 2qN A εSi
(c) VGS=0 V and VDS=20V V = Body effect coefficient =
Cox
(d) VGS= –7V and VDS=20V
GATE-1992 ∴ V SB is +Ve, threshold voltage increase.
135. Consider the following statements S1 and S2. into the channel near the drain, and the effective
S1: The threshold voltage (VT) of a MOS channel are is constricted.
capacitor decreases with increase in gate oxide Hence, the inversion charge decreases from source to drain
thickness. as channel potential increases from source to drain.
S2: The threshold voltage (VT) of a MOS 138. IGFET is a
capacitor decreases with increase in substrate (a) Square - law device (b) Half power device
doping concentration. (c) 3/2 power law device (d) Linear device
Which one of the following is correct? UJVNL AE-2016
(a) S1 is FALSE and S2 is TRUE Ans. (a) : IGFET is a field effect transistor having one
(b) Both S1 and S2 are TRUE or more gate electrodes that are electrically insulated
(c) Both S1 and S2 are FALSE from the channel. It is a square - law device.
(d) S1 is TRUE and S2 is FALSE
GATE: 2004 139. For the NMOSFET in the circuit shown, the
threshold voltage is Vth, where Vth > 0, The
Ans. (c) : VT = VT0 + γ  φf + VSB − 2φf  source voltage Vss is varied from 0 to VDD.
Neglecting the channel length modulation, the
2qN A ε 2qN A ε
γ= = t ox drain current ID as a function of Vss is
Cox 3.45 × 10 −11 represented by
As
136. A MOS capacitor made using p-type substrate

is in the accumulation mode. The dominant
charge in the channel is due to the presence of
(a) Holes
(b) Electrons
(c) Positively charged ions
(d) Negatively charged ions
GATE-2005
Ans. (a) : Accumulation mode- A MOS capacitor
with P-type substrate operate in accumulation mode
when gate voltage is-Ve
• –Ve charge of SiO2 will attract holes from P-type
substrate these holes accumulate below SiO2 forming a
thin accumulation layer. The dominant charge depend
on the substrate type.
137. Consider the following two statements about
the internal conditions in an n-channel
MOSFET operating in the active region
S1: The inversion charge decreases from source
to drain
S2: The channel potential increases from source
to drain
Which of the following is correct?
(a) Only S2 is true
(b) Both S1 and S2 are false
(c) Both S1 and S2 are true, but S2 is not a reason GATE-2015
for S1 Ans. (a) : When drain and gate are shorted then VG = VD
(d) Both S1 and S2 are true, and S2 is a reason for I D = K(VGS − VT ) 2
S1
I D = K(VDD − VS − VT )2
GATE-2009
Ans. (d) : I D = K(VDD − VSS − VT ) 2
if VSS = 0V
I D = k(VDD − VT ) 2
if VSS = VDD –VT
then ID = 0
• When the drain current ID is increased, the voltage is 1
large near the drain end and small near the source end So, ↑ ID ∝ ........ (non-linearly)
(VSS )2 ↓
of the channel. As a result depletion region in trades
140. A long-channel NMOS transistor is biased in (c) The driver is depletion type and load
the linear region with VDS= 50 mV and is used enhancement type
as a resistance. Which one of the following (d) Both driver and load are depletion type
statements is NOT correct?
(a) If the device width W is increased, the Nagaland PSC CTSE- 2015, Paper-II
resistance decreases. Ans. (b) : The driver is enhancement type and load
(b) If the threshold voltage is reduced, the depletion type in the NMOS inverter.
resistance decreases. 144. The threshold voltage (VT) is negative for
(c) If the device length L is increased, the (a) an n-channel enhancement MOSFET
resistance increase.
(d) If VGS is increased, the resistance increases. (b) an n-channel depletion MOSFET
GATE- 2016 (c) a p-channel depletion MOSFET
Ans. (d) : (d) a p-channel JFET.
DRDO-2008
1
↓ Rd = Ans. (b) : For depletion mode, n MOSFET threshold
µ n Cox × ( ↑ VGS − VT )
W
voltage (VT) is negative.
L
• As W increases, the resistance decreases. 145. Identify the correct statement about MOS
• As threshold (VT) decreases, the resistance decrease. capacitor-
• As length (L) increases, the resistance increases. (a) for an N-type substrate, a negative voltage is
• However, as VGS increases, the resistance decreases. applied and P-type inversion layer is formed
141. The figure shows the band diagram of a Metal (b) for a P-type substrate a negative voltage is
Oxide Semiconductor (MOS). The surface applied and P-type inversion layer is formed
region of this MOS is in (c) for an N-type substrate a positive voltage is
applied and N-type inversion layer is formed
(d) for a P-type substrate a negative voltage is
applied and N-type inversion layer is formed
UPPCL AE-16.11.2013
Ans. (d) : A MOS capacitor with p-type substrate
operate in accumulation mode when gate voltage is –ve.
(a) Inversion (b) Accumulation –Ve charge will attract hole from p type substrate.
(c) Depletion (d) Flat band These holes accumulate below terming a thin
GATE- 2016 accumulation layer.
Ans. (a) : When VGS crosses threshold voltage the 146. Consider the following statements for a metal
increase in depletion region width stops and charge on oxide semiconductor field effect transistor
layer is countered by mobile holes at the Si-SiO2 interface (MOSFET):
this is called inversion because the mobile charges are P: As channel length reduces, OFF-state
opposite to the type charge founded in the substrate. In current increases.
case, the inversion layer is formed by the holes. Q: As channel length reduces, output
142. Match the statements in right column with the resistance increases.
name given in left column and select the correct R: As channel length reduces, threshold
answer using the code given below the lists voltage remains constant.
(a) BJT (i) Has a poly-silicon gate S: As channel length reduces, ON current
(b) JFET (ii) Works only in increases.
depletion mode Which of the above statements are
(c) MOSFET (iii) Highly sensitive to INCORRECT?
temperature and is noisy
(d) PIN diode (iv) Useful at microwave (a) P and Q (b) P and S
frequencies (c) Q and R (d) R and S
(a) (a)-i,(b)-ii,(c)-iii,(d)-iv GATE- 2016
(b) (a)-ii,(b)-iii,(c)-i,(d)-iv Ans. (c) :
(c) (a)-iii,(b)-ii,(c)-i,(d)-iv 1 W
µ n Cox × ( VGS − VT ) → sine the current
2
(d) (a)-iii,(b)-i,(c)-iv,(d)-ii • ID =
UPPCL AE-16.11.2013 2 L
Ans. (c) : inversely proportional to channel length, the current will
BJT → Highly sensitive to temperature and noisy. increase as the length will decrease.
JFET → Works only in depletion mode Hence 'P' is correct.
MOSFET → Has a poly silicon gate • Rd =
L
, As the output
PIN diode → Useful at microwave frequencies Wµ n Cox [ (VGS − VT )VDS ]
143. In the NMOS inverter resistance is directly proportional to the channel length,
(a) The driver and active load are enhancement
it reduces with a decrease in channel length so
type
(b) The driver is enhancement type and load statement Q is incorrect.
depletion type • The threshold voltage of MOSFET is-

Qd Q 151. An N-channel JFET has IDSS = 4mA and Vp = –
VT = 2φF − + φms − 1 8V, Its maximum transconductance is _____.
Ci Ci (a) 4 S (b) 0.002 S
We can conclude that the threshold voltage is also (c) 0.2S (d) 0.001 S
dependent on the channel length, Hence 'R' is also DFCCIL Executive (S&T) 11.11.2018, 4:30 to 6:30PM
current. Ans. (d) :Given:
147. FET has offset voltage of about IDSS = 4mA , Vp = –8V
(a) 0.2 V (b) 0.9 V
(c) 0.7 V (d) 0 V
Mizoram PSC IOLM -2018, Paper I 2I DSS
g mo =
Ans. (d) : Offset voltage is defined as the voltage that | VP |
must be applied to the input to cause the output voltage 2 × 4 ×10−3
to be zero. For FET offset voltage is zero. g mo =
148. Silicon crystal ingot is grown in industry by: 8
(a) Epitaxy = 10−3
(b) CVD (chemical vapour deposition) gmo = 0.001S
(c) metalization 152. Consider the following statements regarding
(d) fload-zoning (FZ) and Czochralski (CZ) comparison of FET with BJT:
process 1. BJT is less noisy than FET.
(e) Photolithography 2. FET is current-controlled device, whereas
CGPSC SO 14.02.2016 BJT is voltage-controlled device.
Ans. (d) : Silicon crystal ingot is grown in industry by 3. FETs are more temperature stable
float - zoning (FZ) and Czochralski (CZ) process. From compared to BJTs.
this process Silicon crystals are grown free of 4. FETs are simple to fabricate and occupy
dislocations with diameters of 100-300 mm and masses less area on the single chip.
up to 300 kg. Which of the above statements are correct?
149. A source follower using a FET usually has a (a) 1 and 2 (b) 1 and 3
voltage gain which is (c) 3 and 4 (d) 1 and 4
(a) greater than +100 ESE-2022
(b) slightly less than unity, but positive
(c) exactly unity but negative Ans. : (c) : • BJT is high noisy than FET.
(d) about 10 • FET is voltage-controlled device and BJT is current
KVS TGT (WE)- 2014 control device.
(b) : A source follower using a FET usually has a voltage • FETs are more temperature stable compared to BJTs.
gain which is slightly less than unity, but positive. • FETs are simple to fabricate and occupy less area on
150. The CMOS inverter can be used as an the single chip.
amplifier when: • BJT is current flow majority charge carrier and FET
(a) PMOS is in linear, NMOS is in cut-off.
(b) NMOS is in linear, PMOS is in cut-off. is current flow majority and minority charge carrier.
(c) Both PMOS and NMOS are in saturation. 153. Which one of the following statements is
(d) Both are in linear region. correct for n-channel or p-channel MOSFET?
DFCCIL Executive (S&T) 11.11.2018, 4:30 to 6:30PM (a) Drain resistance of MOSFET is very larger
Ans. (c) : The CMOS inverter can be used as an than JFET.
amplifier if properly biased in the transition region of its (b) Transconductance and inter-electrode
voltage-transfer characteristic. capacitances have comparable value for the
two types of devices.
(c) Input resistance and feedback resistance are
very smaller than JFET.
(d) Input resistance and feedback resistance are
comparable to JFET.
ESE-2022
(b) : The n-channel or p-channel MOSFET trans-
conductance and Inter-electrode capacitances have
comparable value for the two type of devices.
Region (3) : CMOS inverter can be used as an amplifier
because small change in input voltage (in mV) can 154. Which one of the following technologies
cause a large change in output voltage. consumes less power?
VDD (a) Surface-mount technology (b) CMOS
if Vi = (c) NMOS (d) PMOS
2
then both MOSFETS will be in the saturation region ESE-2022
and will act as amplifiers. (b) : CMOS technologies consume less power. CMOS
Hence, the CMOS inverter can be used as an amplifier devices have high noise immunity and low state power
when both PMOS and NMOS are in saturation. consumption.
155. What is one of the primary advantages of FET Ans. (d) : Depletion mode n-mos transistor have an n
compared to BJT? channel and are built on a p-type silicon substrate where
(a) Low input impedance P-mos depletion mode transistor are built on n-type
(b) Low output impedance substrate.
(c) High input impedance Silicon oxide is present between the source and the
(d) High output impedance drain regions.
(e) Low value of current • In Depletion mode the channel is already established
CGPSC SO 14.02.2016 due to the implant. Even when Vgs = 0V .
Ans. (c) : High input impedance is the primary
advantage of FET compared to BJT because there is no • A negative voltage ( Vtd ) must be applied between
minority carrier contribution to the flow through the the gate and the source for n-mos to remove the
device. channel.
156. The (Id-Vgs) characteristics of a MOSFET in • Similarly a positive voltage ( Vtd ) between the source
the saturation region is: and drain is required to remove the channel for p-mos
(a) Quadratic (b) Exponential
depletion mode:
(c) Logarithmic (d) Hyperbolic
DFCCIL Executive S&T-17.04.2016, Shift-II 159. Why n-type switch is not preferred over CMOS
Ans. (a) : The characteristic of MOSFET (Id – Vgs )in Switch?
(a) n type transmits a logic 0 well, but when VDD
saturation region is quadratic. is applied to the drain, the voltage at the
source is VDD –Vtn.
(b) n type transmits a logic 1 well, but When VDD
is applied to the drain, the voltage at the
source is VDD–Vtn.
(c) n type transmits a logic 0 well, but when VDD
is applied to the drain, the voltage at the
source is Vtn –VDD.
157. Which of the following statements about the (d) n type transmits a logic 1 well, but when VDD
MOS transistor is INCORRECT? is applied to the drain, the voltage at the
(a) It derives its name from materials involved in source is Vtn–VDD.
the early transistor of metal, oxide, and TNTRB AE– 2017
semiconductor Ans. (a) : •CMOS stands for complementary metal-
(b) The heart of a MOS transistor is the MOS oxide-semiconductor.
capacitor Whereas N-MOS is a metal oxide semiconductor. These
(c) In modern MOS transistors, the metal layer is are two different logic families.
often replaced by highly doped Si3 N4
• CMOS uses both PMOS and NMOS transistor for
(d) The oxide thickness, which is typically of the
design where NMOS uses only NMOS transistors.
order of 0.01 µm is crucial in determining the
CMOS is chosen over NMOS for switching operations
behavior of the MOS capacitor
in embedded system design as it propagates for both
logic 0 and logic 1. So, that's why n type transmits a
Ans. (c) : The metal-oxide- semiconductor field effect logic 0 well, but when V is applied to the drain, the
DD
transistor is a type of insulated gate field effect
voltage at the source is VDD –Vtn.
transistor that’s is fabricated by the controlled oxidation
of a semiconductor. 160. Which of the following properties does CMOS
• It derives its name from material involved in the early logic possess ?
transistor of metal, oxide and semiconductor. (a) Increased capacitance
(b) Low static power dissipation
• The heart of a mos transistor is the mos capacitor.
(c) Increased delay
• The oxide thickness which is typically of the order
(d) High noise margin
of 0.01 µm is crucial in determining the behavior of UPRVUNL AE– 11.06.2014
the MOS capacitor. Ans. (b) : Complementary metal- oxide semiconductor
158. In a n mos transistor, when Vgs = 0 and to cause uses complementary and symmetrical pair of p-type and
the channel to cease to exist a negative voltage n-type MOSFET. It has low static power dissipation.
Vtd (threshold voltage) must be applied 161. For n-channel field effect transistor running in
between gate and source. The transistor enhancement mode, a conductive channel is
operates in: formed only from:
(a) n mos enhancement mode (a) +ve gate to source voltage
(b) n mos Depletion mode (b) –ve gate to source voltage
(c) P mos enhancement mode (c) +ve source to gate voltage
(d) p mos depletion mode (d) –ve source to gate voltage
TNTRB AE– 2017 UPRVUNL AE– 11.06.2014

Ans. (a) : For the n-channel field-effect transistor (c) epitaxial growth
running in enhancement mode, a conducting channel is (d) anodisation
formed only when +Ve gate to source voltage applied. APPSC POLY. LECT. 14.03.2020
Enhancement type MOSFET-. MOSFET is a metal TSTRANSCO AE-2018
oxide semiconductor field-effect transistor in which Ans. (a) : Diffusion is a process by which atoms move
drain current varies in proportion to the VGS (Gate from a high concentration region to a low-concentration
voltage). region IC fabrication. This process is done by heating
The input resistance of a MOSFET is several order of the wafers in an atmosphere of impurities.
magnitude greater than of JFET.
6. If RA = 10k, RB = 10k and capacitance = 10µF
the total time period of the a stable
(v) Integrated circuit (ICs) multivibrator 555 is:
(a) 0.207 s (b) 0.5 s
1. For trigger voltage less than 1/3 Vcc, the output (c) 0.138 s (d) 0.069 s
of IC 555 is: UPMRC AM - 2020
(a) –1 (b) infinite
Ans. (a) : Ton = 0.693 (RA+RB).C
(c) low (d) high
Toff = 0.693 (RB.C)
Total time (T0) = Ton +Toff
Ans. (d) : A low voltage (less than 1/3 the supply = 0.693 (RA+2RB). C
voltage) applied momentarily to trigger input causes
the output pin (3) go to high. given RA = 10k, RB = 10k, C = 10µF
To = 0.693 (10k +2 ×10k) ×10×10–6
= 0.693 ×30 ×103 ×10 ×10–6
T0 = 0.207 s
7. Which type of timing violation will occur, If a
2. The nearest standard value of timing capacitor digital IC is operated at clock frequency which
to produce a 100 µs output pulse from IC 555 is higher than its specified maximum clock
frequency?
along with timing resistor of 10 kΩ is,
(a) Hold violation (b) Setup violation
(a) 100 nF (b) 1 µF
(c) Propagation delay (d) All of above
(c) 1 nF (d) 10 nF
RPSC ACF & FRO 23.02.2021 ISRO Scientist Engg.-2014
Ans. (d) : τ = RC Ans. (b) : Setup violation is type of timing violation
The width of the output is a function of only the will occur, If a digital IC is operated at clock frequency
external time constant RC which is higher than its specified maximum clock
100 µs = (10kΩ) C frequency.
8. The most popular types of ICs are……….
100 × 10−6 (a) Thin-film (b) Hybrid
C= = 10 nF
10 × 103 (c) Thick-film (d) Monolithic
3. The IC series 7805, 7806, 7912 and 7915 is Nagaland PSC (CTSE) Diploma-2017, Paper II
unique series due to Ans. (d) : Monolithic ICs are the most common types
(a) All logic gate ICs ICs are use today. Its cost of production is cheap and is
(b) All voltage regulator ICs reliable. Commercially manufactured ICs are used as
(c) All oscillator IC’s amplifiers, voltage regulators.
(d) All voltage comparator IC’s 9. The active components in an IC are………..
RPSC ACF & FRO 23.02.2021 (a) Resistors
Ans. (b) : A voltage regulator is an integrated circuit (b) Capacitors
(IC) that provide a constant fixed output voltage (c) Transistors and diodes
regardless of a change in the load or input voltage.
e.g. IC series 7805,7806, 7912 and 7915 etc.
4. The output of the IC 555 is when the
reset pin is connected to low voltage. Ans. (c) : Active component require a source of energy
(a) tri-state (b) zero typically in the form of direct current.
(c) high (d) normal Hence, In ICs transistor and diode are active
UPRVUNL AE -19.07.2021, Shift-II component.
Ans. (b) : When the timer IC is to be reset or disabled, 10. The main purpose of the metallization process is
zero pulse is applied to pin 4 (RESET PIN) (a) To supply a bonding surface for mounting the
5. The diffusion process in an IC fabrication is chip
done by : (b) To protect the chip from oxidation
(a) heating the wafers in an atmosphere of (c) To act as a heat sink
impurities (d) To interconnected the various circuit elements
(b) cooling the wafers inside an ingot TNPSC AE - 2018
Ans. (d) : Metallization is the process by which the Ans. (a) : The enhancement mode MOS are equivalent
component of IC's are interconnected by aluminium to a 'normally open' switch that requires gate-source
conductor. This process produce a thin film metal layer voltage to switch ON the device. If the positive voltage
that will serve as required conductor pattern. (+VGS) is applied to an n-channel gate terminal, then only
For the interconnection of the various components on the channel will conduct and the drain current start to flow
the chip. through the channel. If the bias voltage is zero then the
11. The type of transistor preferred in IC transistor switch OFF and the channel stay in the
technology is nonconductive state resulting in the drain current to be zero.
(a) pnp (b) pnpn 16. Czochralski method is used in
(c) npn (d) pnp-npn (a) Mask making (b) Wafer cleaning
Mizoram PSC IOLM -2018, Paper I (c) Ion implantation (d) Etching
Ans. (c) : The npn type of transistor is preferred in IC Nagaland PSC CTSE (Diploma)-2018, Paper-I
technology. Ans. (b) : The Czochralski method is a method of
12. Capacitance of any CMOS transistor is- crystal growth used to obtain single crystal of
(a) Proportional to the width of CMOS transistor semiconductor. The Czochralski method is the
channel relatively high growth rate.
(b) Inversely proportional to the width of CMOS 17. Dry etching is done by
transistor channel (a) HF acid (b) Inert Gas
(c) Inversely proportional to the length of CMOS (c) HCL acid (d) O2 Gas
transistor channel Nagaland PSC CTSE (Diploma)-2018, Paper-I
(d) proportional to the length of CMOS transistor Ans. (d) : Dry etching refers to the removal of material
channel typically a masked pattern of semiconductor material by
UPPCL AE-16.11.2013 exposing the material fluorocarbons oxygen, chlorine,
Ans. (b) : Capacitance of any CMOS transistor is boron trichloride are used.
Inversely proportional to the width of CMOS transistor 18. Ultraviolet radiation is used in IC fabrication
channel. process for
εA (a) Diffusion (b) Masking
C= (c) Isolation (d) Metallization
d Mizoram PSC Jr. Grade -2018, Paper-I
13. In a free running multivibrator, each stage is UJVNL AE-2016
cut off for 1 µs. What is the oscillator Ans. (b) : Masking–To protect some area of wafer
frequency? when working on another area, a process called
(a) 10 MHz (b) 5 MHz photolithography is used. The process of
(c) 1 MHz (d) 0.5 MHz photolithography includes masking with a photographic
Nagaland PSC CTSE (Degree)-2016, Paper-II mask and photo etching. Ultraviolet radiation is used in
Ans. (d) : In a free running oscillator, each stage is cut IC fabrication process for masking.
off for duration of 1 µs. Therefore the output wave 19. IC 741 operational amplifier has typical gain of
1 1 (a) 110 dB (b) 100 dB
frequency will be = = = 0.5 × 106 Hz (c) 106 dB (d) 90 dB
2T 2 ×10−6
= 0.5MHz RPCS Lect.-2011
Ans. (c) : For IC 741, typical gain (A)
14. The JFET is called square law device because
its: = 200000 = 2 × 105
(a) Transconductance curve is parabolic 20 log (A) = 20 log (2 × 105)
(b) A. resistance from drain to source varies (A)dB= 20 log10 2 + 100 log10 10
inversely as square of the drain current (A)dB = 6.02 +100
(c) Drain current varies as square of drain voltage (A)dB = 106.02 dB
for a fixed gate to source voltage 20. When the photoresist coating (during IC
(d) Reverse gate leakage current varies as a fabrication) is exposed to ultraviolet light the
square of reverse gate voltage photoresist becomes
TNTRB AE– 2017 (a) oxidized (b) ionized
Ans. (a) : The JFET is known as square law device (c) polymerized (d) brittle
because its transconductance curve is parabolic. Drain IES-2013
current varies as square of the gate source voltage. Ans. (c) : Photoresist coating becomes polymerized
15. The n-channel MOS and p-channel MOS is when it is exposed to ultraviolet light.
turned off: Photo resist is a material that is continuously worked
(a) If gate source voltage is zero with this light sensitive material has two types
(b) If gate to source voltage is positive positive and negative.
(c) If gate to source voltage is negative With negative resists, exposure to ultraviolet light
(d) If gate to drain voltage is positive causes the chemical structure of the photoresist to
TNTRB AE– 2017 polymerize.

21. For a sheet with resistivity ρ, width w, length l Select the correct answer using the code given
and thickness y, the resistance per square below:
(sheet resistance) Rs is (a) 1 and 2 only (b) 2 and 3 only
ρ (c) 3 and 4 only (d) 1 and 4 only
(a) (b) ρy IES-2008
y
ρl ρ Ans. (a) : MOS capacitor and collector substrate.
(c) (d) Capacitors are widely used in monolithic IC fabrication.
y ly
25. Why is silicon dioxide (SiO2) layer used in ICs?
IES-2013 (a) To protect the surface of the chip from
Ans. (a) : external contaminants and to allow for
selective formation of the n and p regions by
diffusion
(b) because it facilitates the penetration of the
desired impurity by diffusion
where, (c) To control the concentration of the diffused
ρ → resistive of sheet impurities by diffusion
w → width (d) Because of its high heat conduction
y → thickness IES-2008
l → length of sheet Ans. (a) : During ion implantation, SiO2 is used as a
∴ A = wy (w = l) masking layer to protect the surface from damage the
oxide layer is patterned by the photolithographic process.
ρl ρl ρ
∴R = = = 26. Why is the term 'planar technology' for
A w.y y fabrication of devices in ICs used?
22. The maximum concentration of the element (a) The variety of manufacturing processes by
which can be dissolved in solid silicon at a which devices are fabricated, takes place
given temperature is termed as through a single plane
(a) Solid solubility (b) The aluminium contacts to collector, base and
(b) Dissolution coefficient emitter regions of the transistors in the ICs
(c) Solidification index are laid in the same plane
(d) Concentration index (c) The collector, base and emitter regions of the
IES-2009 transistors in ICs are laid in the same plane
Ans. (a) : The solid solubility is defined as the (d) The devices looks like a thin plane wafer
maximum concentration of the element which can be IES-2008
dissolved in the solid silicon at a given temperature. Ans. (a) : Planar technology is a primary process used
The solid solubility limit prevents the excessive doping to built the integrated circuit. In this method, the variety
needed to reduces the depletion width below the mean free of manufacturing process by which devices are
path, or in general, the coherence length of the electrons. fabricated, takes place through a single plane.
Solid dissolved in liquid water, the solubility increases
with temperature. 27. In integrated circuits, the design of electronic
circuits is based on the approach of use of
23. The process of extension of a single-crystal
(a) maximum number of resistors in the circuit
surface by growing a film in such a way that
(b) large sized capacitor
the added atoms form a continuation of the
single-crystal structure is called (c) minimum chip area irrespective of the type of
(a) Ion implantation components in the design
(b) chemical vapour deposition (d) use of only bipolar transistors
(c) Electroplating IES-2006
(d) Epitaxy Ans. (c) : The design of IC is based an minimum chip
IES-2009 area irrespective of the type Components in the design.
Ans. (d) : Epitaxy refers to a type of crystal growth or In an IC, the active and passive components are made
material deposition in which new crystalline layers are in a single crystal. The IC consist of silicon crystal chip
formed with one or more well defined orientations with with a cross-sectional area of 1.27 mm×1.27mm or less.
respect to the crystalline seed layer. The deposited Ex an IC chip of area 1.65 mm×1.65 mm may contain
crystalline film is called an epitaxial film or epitaxial layer. about 35 transistor, 30 resistor and some capacitor and
24. Which of the following capacitors are made use their inter connections integrated.
of widely for a capacitance application in 28. Diffusion of impurities in a semiconductor is
monolithic ICs. carried out in a furnace through which a steady
1. MOS capacitor stream of impurity atoms is passed during the
2. Collector Substrate capacitor entire diffusion process. What would be the
3. Collector-Base capacitor type of the profile of the impurity atoms inside
4. Base-Emitter capacitor the semiconductor?
(a) Linear Codes:
(b) Gaussian A B C D
(c) Complementary error function (a) 4 1 2 3
(d) Exponential (b) 2 3 4 1
IES-2005 (c) 4 3 2 1
Ans. (c) : A semiconductor is carrier diffusion of (d) 2 1 4 3
impurities out in a furnace through which a steady IES-2005
stream of impurity atom is passed during the entire Ans. (a) :
List-I List-II
diffusion process. The profile of impurity item inside
A. Reverse bias p-n 4. Introduces bias-
the semiconductor is complementary error function. junction isolation dependent parasitic
29. The basic function of buried n+ layer in an n-p- capacitance
n transistor in IC is to B. Resistive isolation 1. Requires large area of
(a) Reduce the magnitude of the base spreading using the bulk the wafer, thereby
resistance resistivity of the increasing the IC size
(b) Reduce the collector series resistance layer
(c) Reduce the base width of the transistor C. Native oxide 2. Best choice for silicon
(d) Increase the gain of the transistor isolation ICs with low parasitic
IES-2005 capacitance
Ans. (b) : The buried n+ layer provide a low resistance D. Oxide (other 3. Suitable for ICs of III-
path in active collector region to the collector contact. than native V semiconductors
In effect, the buried layer provides a low resistance isolation)
shunt path for the flow of current. 32. Consider the following
1. Cheaper method
30. Consider the following statements: 2. Low residual oxygen content in the grown
X-rays are used for lithography in IC crystal is possible
technology because 3. Uniform doping is possible
1. high resolution is achievable 4. Larger diameter crystals can be grown
2. scattering effects are small. Which of the above are the advantages of the
3. they can be focused easily float zone (FZ) method over the Czochralski
4. they can be deflected easily. (CZ) method in single crystal growth of silicon?
Which of the statements given above are (a) 1 and 2 (b) 2 and 3
correct? (c) 3 and 4 (d) 1 and 4
(a) 1 and 2 (b) 1 and 3 IES-2004
(c) 1 and 4 (d) 2 and 3 Ans. (b) : The main advantages of the float zone (FZ)
IES-2005 method over the Czochralski (CZ) method is the very
Ans. (a) : Lithography is the heart of the low impurity concentration in the silicon crystal. In
semiconductor fabrication process. It is use as scattering particular the oxygen and carbon concentration are
effect are small and high resolution is achievable. much lower as compared to CZ silicon, since the melt
does not come into contact with a quartz crucible and no
31. Match list-I (Isolation Technique in IC ) with
hot graphite container is used.
List-II (Related Characteristic) and select the
In FZ method uniform doping is possible as compared
correct answer using the code given below: to CZ method.
List-I List-II
A. Reverse bias p-n 1. Requires large
correct?
junction area of the wafer, In the context of IC fabrication, metallization
isolation thereby means
increasing the IC (a) connecting metallic wires
size (b) formation of interconnecting conduction
B. Resistive 2. Best choice for pattern and bonding pads
isolation using silicon ICs with (c) doping SiO2 layer
the bulk low parasitic (d) covering with a metallic cap
resistivity of the capacitance IES-2004
layer Ans. (b) : In metallization process the components of
C. Native oxide 3. Suitable for ICs ICs are interconnected by aluminium conductor. This
isolation of III-V process produces a thin-film metal layer that will serve
semiconductors as the required conductor pattern for the interconnection
D. Oxide (other 4. Introduces bias- of the various components on the chip. It produces
than native dependent metalized areas called bonding pods around the
isolation) parasitic periphery of the chip to produces metalized areas for the
capacitance bonding of wire leads from the package to the chip.

34. In fabricating silicon BJT in ICs by the (a) 2, 4, 3, 1 (b) 4, 2, 1, 3
epitaxial process, the number of diffusions used (c) 2, 4, 1, 3 (d) 4, 2, 3, 1
is usually RPSC Vice Principal ITI-2016
(a) 2 (b) 3 IES-2001
(c) 4 (d) 6 Ans. (d) : Following processes involved in the
IES-2003 fabrication a buried layer n-p-n transistor
Ans. (b) : There are 3 diffusion isolation diffusion, 1. Lithography
Base diffusion and Emitter diffusion are used in 2. Oxidation
epitaxial process in fabricating silicon BJT in ICs. 3. Epitaxy
35. In the fabrication of n-p-n transistor in an IC, 4. Diffusion
the buried layer on the p-type substrate is 39. Almost all resistors are made in a monolithic
(a) p+ –doped integrated circuit
(b) n+ –doped (a) during the emitter diffusion
(c) Used to reduce the parasitic capacitance (b) while growing the epitaxial layer
(d) Located in the emitter region (c) during the base diffusion
IES-2003 (d) during the collector diffusion
IES-2000
Ans. (b) : In fabrication of n-p-n transistor in an IC, the
buried n+-doped layer on the p-type substrate is used to Ans. (c) : Almost resistors are farmed during the base
reduce the collector series resistance. diffusion of the integrated transistor because it is the
highest resistivity region for low resistance values,
36. Match List-I with List-II and select the correct emitter region is used as it has much lower resistivity
answer using the codes given below the lists: another diffusion technique is also used for the growth
List-I List-II of resistors.
A. Super buffers 1. Bi-CMOS technology
40. In an integrated circuit, the SiO2 layer provides
B. Drivers 2. CMOS technology (a) electrical connection to external circuit
C. Logic gates 3. n-MOS technology (b) physical strength
D. High speed 4. ECL technology (c) isolation
Codes: (d) conducting path
A B C D IES-1999
(a) 3 4 2 1
Ans. (c) : In an integrated circuit, SiO2 layer is used to
(b) 2 1 3 4
provide isolation. And also SiO2 to mask the silicon
(c) 3 1 2 4 surface during the diffusion or ion implantation
(d) 2 4 3 1 process. Oxide layer is patterned by the
IES-2002 photolithographic process.
Ans. (b) :
• Super buffer uses CMOS technology. It has lowest
speed comparison to n-MOS and p-MOS
technology.
• Bi-CMOS technology is used to make drivers.
• For making logic gates, n-MOS and p-MOS are 41. What is the correct sequence of the following
widely used. steps in the fabrication of a monolithic, bipolar
• ECL has highest speed of operation, so it has lowest junction transistor?
propagation delay. 1. Emitter diffusion
2. Base diffusion
37. Moore's law relates to 3. Buried layer formation
(a) speed of operation of bipolar devices 4. Epi-layer formation
(b) speed of operation of MOS devices Select the correct answer using the codes given
(c) power rating of MOS devices below
(d) level of integration MOS devices (a) 3, 4, 1, 2 (b) 4, 3, 1, 2
IES-2002 (c) 3, 4, 2, 1 (d) 4, 3, 2, 1
Ans. (d) : It states that the number of transistor per IES-1998
square inch on IC will roughly double every year sine the Ans. (c) : The fabrication of monolithic transistor
invention of IC's. Moore's low is related to the level of includes the following steps.
integration of MOS devices it predicted that this trend 1. Buried layer formation (Epi layer formation)
would continue in the future also. Moor's law means even- 2. Oxidation
more powerful computers for less and less money. 3. Photolithography
38. In the fabrication of a buried layer n-p-n 4. Isolation diffusion
transistor, the processes involved are 5. Base diffusion
1. diffusion 2. oxidation 6. Emitter diffusion
3. epitaxy 4. lithography 7. Contact mask
The correct sequence in which these processes 8. Aluminium metallization
are to be carried out, is 9. Passivation
42. Consider the following statements: • Leakage problem because dielectric is present
In the fabrication of an integrated circuit, the between the plates of the capacitor.
advantages of ion-implantation over diffusion • The speed of operation is reduced because the
doping are that capacitor is an energy storage device.
1. It is low temperature n-process • The cost of fabrication increased.
2. Point imperfections are not produced 46. If fixed positive charges are present in the gate
3. Shallow doping is possible oxide of an n-channel enhancement type
4. Previous steps in fabrication are not affected MOSFET, it will lead to
Of these statements (a) a decrease in the threshold voltage
(a) 1, 2 and 3 are correct (b) channel length modulation
(b) 2, 3 and 4 are correct (c) an increase in substrate leakage current
(c) 1, 3 and 4 are correct (d) an increase in accumulation capacitance
(d) 1, 2 and 4 are correct GATE- 2014, Set-I
IES-1994 Ans. (a) : The threshold voltage commonly abbreviated
Ans. (c) : The advantages of ion implantation include as VTh of a field-effect transistor is the minimum gate to
precise control of does and depth of the source voltage (VGS) that is needed to create a
profile/implantation. It is low temperature process, so conducting path between the soure and drain terminal
there in no need for heat-resistant equipment. Other
advantage, include a wide selection of masking material
and excellent.
43. If P is Passivation, Q is n-well implant, R is
metallization and S is source/drain diffusion,
then the order in which they are carried out in
a standard n-well CMOS fabrication process, is
(a) P-Q-R-S (b) Q-S-R-P
(c) R-P-S-Q (d) S-R-Q-P If we apply a potential source between the drain and the
GATE- 2003 source, no current flow as there is no conducting path
Ans. (b) : Some important CMOS fabrication processes between drain and source.
1. Create n-well region and channel stop region. To provide conducting path we apply a positive voltage
2. Growing field oxide and gate oxide at the gate. If positive charge is present in the gate
3. Deposite and pattern polysilicon layer oxide, lesser voltage will be required at the gate for the
4. Implant source and drain region formation of channel, which is nothing but the
5. Create contact windowsthen deposite and pattern threshold voltage. So the threshold voltage will
metal layers. decrease if there is already an oxide charge stored.
6. Passivation 47. In CMOS technology, shallow P-well or N-well
7. Packasing regions can be formed using
44. Thin gate oxide in a CMOS process is (a) low pressure chemical vapour deposition
preferably grown using (b) low energy sputtering
(a) wet oxidation (c) low temperature dry oxidation
(b) dry oxidation (d) low energy ion-implantation
(c) epitaxial deposition GATE- 2014, Set-II
(d) ion implantation Ans. (d) : In CMOS technology shallow powder N-well
Nagaland PSC CTSE (Diploma)-2018, Paper-I region can be formed by using energy ion implantation,
GATE- 2010 because it is provide independent control of close and
Ans. (b) : Dry oxidation is used to achieve high quality depth ion implantation deposits controlled amount of
oxide growth dry oxidation produces a very good charge species in a specific region of a semiconductor.
quality of oxide that's why dry oxidation is preferred 48. In MOSFET fabrication, the channel length is
over wet oxidation to grow thin gate oxide in CMOS defined during the process of
fabrication dry oxidation is used to form thin oxide (a) isolation oxide growth
films and give better electrical properties. It is slow (b) channel stop implantation
compare to wet oxidation and the reaction resolve is - (c) poly-silicon gate patterning
Si+O2 → SiO2. (d) lithography step leading to the contact pads
GATE-2014, Set-III
45. Which of following is most difficult to fabricate
Ans. (c) : The channel length is defined during the
in IC?
process of poly-silicon gate patterning.
(a) Resistor (b) Transistor While gate patterning of poly-silicon etching is done to
(c) FET (d) Capacitor the rest of poly-silicon and SiO2 to remove and the
UPRVUNL AE-2016 channel length is fixed at the same time.
Ans. (d) : Capacitor is most difficult to fabricate in IC. 49. Which one of the following processes is
• A large area is required on the chip for a large value preferred to from the gate dielectric (SiO2) of
of the capacitor (in mF or µF) MOSFETs?
(a) Sputtering The diode is connected between base and collector, base
(b) Molecular beam epitaxy is P-type, collector is n++ type. Hence collector will be
(c) Wet oxidation of n type and base will be p-type.
(d) Dry oxidation 51. In a linear IC voltage, series pass transistor
GATE-2015, Set-III always operates in ______ region.
Ans. (d) : Dry oxidation method is preferred of form (a) Active (b) Saturation
the gate dielectric (SiO2) of MOSFET. (c) Cutoff (d) All of the above
Epitaxy in IC fabrication is a layer grown over a layer in Kerala PSC Lecturer (NCA) 04.07.2017
this process, the formation of SiO2 does not take place.
Dry oxidation is superior to wet oxidation which is Ans. (a) : In a linear IC voltage, series pass transistor
clearly observed in comparison. always operates in active region. A transistor series
50. The correct circuit representation of the voltage regulator can be defined as a device that kept
structure shown in the figure is the output voltage at constant level.
52. Arsenic and Boron are most important doping
species in VLSI technology because of their:
(a) highest ionization energy
(b) highest solid solubility value
(c) lowest ionization energy
(d) lowest solid solubility limit
Ans. (b) : Arsenic and Boron are most important doping
species in VLSI technologies because of their highest
solid solubility value.
53. In IC technology, dry oxidation (using dry
oxygen) as compared to wet oxidation (using
steam or water vapour) produces
(a) superior quality oxide with a lower growth rate
(b) superior quality oxide with a higher growth rate
(c) inferior quality oxide with a lower growth rate
(d) inferior quality oxide with a higher growth rate
TSPSC Manager (Engg.) - 2015
GATE-2013
Ans. (a) : Dry oxidation-
Si + O 2 → SiO 2
(solid) (gas) solid
• Excellent electrical characteristics act as best
dielectric to from thin oxide or gate oxide
• Lower growth rate.
Wet oxidation-
Si + 2H2O → SiO2 + 2H2
• Higher grown rate
• Poor electrical characteristics.
Hence,
In IC technology, dry oxidation as compared to wet
oxidation is superior with a slower growth rate dry
oxidation is a slow process but the electrical properties
is better than wet oxidation.
GATE-2019
54. Photo masking
Ans. (b) : (a) controls the depth of diffusion
(b) is used to prevent ambient light shining on the
silicon slice
(c) is used in the process to remove selected
regions of silicon oxide
(d) reduce the size of the circuit elements
Ans. (c) : When a sample of silicon is covered with (a) slows down as the oxide grows
silicon dioxide, the oxide layer acts as a barrier to the (b) is independent of current oxide thickness and
diffusion of impurities so that impurities separated from temperature
the surface of the silicon by a layer of oxide do not (c) is zero as the existing oxide prevents further
diffuse into silicon during high temperature processing oxidation
& p-n junction can thus be formed in a selected location (d) is independent for current oxide thickness but
on sample by finite covering the sample with a layer of depends on temperature
oxide removing the oxide in the selected region. BPSC Polytechnic Lecturer-2014
GATE-2008
55. The main purpose of oxidation in the IC
fabrication process using silicon is : Ans. (a) : Since the silicon required for formation of the
(a) diffusion (b) epitaxial growth SiO2 film is form the substrate, the growth rate slows
(c) passivation (d) packaging down or oxidation rate slows down as film gets thicker.
APPSC POLY. LECT. 14.03.2020 So oxidation rate slows down as the oxide grows.
Ans. (c) : Oxidation is a process which converts silicon 60. The Integrated Circuit used in computers is
on the wafer in silicon dioxide. The main purpose of made of which element?
(a) Silica (b) Chromium
oxidation in the IC fabrication process using silicon is
(c) Iron Oxide (d) Silicon
passivation. Silicon dioxide layers are used as high-
quality insulation or masks for ion implantation.
Ans. (d) : Integrated circuits (IC) chips used in
56. Which among the following do/does not computers are made with silicon. An IC is small chip
support/s the soot formation process? that can function as an amplifier, oscillator, timer,
(a) OVPO (b) MCVD microprocessor or computer memory.
(c) PCVD (d) All of the above
61. Which type of the MOSFET is exclusively used
by MOS digital ICs?
Ans. (c) : Formation of soot is a complex process, on (a) Enhancement MOSFET
evolution of matter in which a number of molecules (b) Depletion MOSFET
undergo many chemical and physical reactions within a (c) Either enhancement or depletion MOSFET
few milliseconds. (d) None of these
57. The technique used to produce small-device KVS TGT (WE)- 2016
pattern on silicon wafer is Ans. (a) : Enhancement MOSFET is exclusively used
(a) Photolithography (b) Oxidation by MOS digital ICs. Enhancement mode MOSFET is
(c) Diffusion (d) epitaxy mostly used as a switch in electronic circuits.
RPCS Lect.-2011 62. Consider the following statements regarding
Ans. (a) : Photolithography, also called as optical Epitaxial Growth:
lithography or lithography, is a process used in 1. Thin layers are grown on a substrate wafer,
microfabrication to pattern parts on a thin film or the this technique is known as epitaxial growth.
bulk of a substrate (also called a wafer). This method 2. Physical vapour deposition is also called
can create extremely small patterns, down to a per tens vapour phase epitaxy.
of nanometer in size. 3. OMCVD is a technique to grow epitaxial
58. The second harmonic distortion is defined as layers from metal organic compounds.
the 4. High throughout and slow deposition rate
(a) Ratio of amplitude of second harmonic are the disadvantages of the CVD
component in the output in the output to the technique.
fundamental frequency Which of the above statements are correct?
(b) Harmonic distortion due to only second (a) 2 and 3 only (b) 1 and 3 only
harmonic component (c) 1, 2 and 3 only (d) 1, 3 and 4 only
(c) Sum of distortion of first and second IES-2021
harmonic components in the output Ans.(b) : Thin layers are grown on a substrate wafer,
(d) Ratio of amplitude of fundamental component this technique is known as epitaxial growth.
in the output to that of second harmonic OMCVD is a technique to grow epitaxial layer, from
component at the input metal organic components.
RPSC LECTURE-10.01.2016 Chemical vapour deposition is also called vapour phase
epitaxy.
Ans. (a) : The second harmonic distortion is defined as
the ratio of amplitude of second harmonic component in 63. Consider the following statements regarding
555 timer:
the output to that of the fundamental frequency.
1. It operates on – 5 V to + 18 V supply
59. A silicon wafer has 100 nm of oxide on it and is voltage in both free running and one-shot
inserted in a furnace at a temperature above modes.
10000C for further oxidation in dry oxygen. 2. It has a high current output and it can
The oxidation rate. source or sink 500 mA.
3. The output can drive TTL and has a Ans. (b) : In an 741 Op-amp PIN 2 & PIN 3 is the input
temperature stability of 80 parts per pin and PIN 6 is output pin there are total 8 pin in IC
million (ppm) per degree Celsius change in 741.
temperature or equivalently 0.008% º C.
Which of the above statements are not correct?
(c) 1, 2 and 3 (d) 2 and 3 only
IES-2021
67. Which of the following is used in integrated
Ans.(c) :
circuits?
(a) microstrip line (b) coaxial line
(c) twin wire line (d) shielded cable
Mizoram PSC AE/SDO-2012 Paper-III
Ans. (a) : Micro strip line is used in integrated circuit.
555 timer- The 555 timer chip is extremely robust and For design the Micro strip line substrate should be
stable 8-pin device. grounded. Typical characteristic impedance of micro
For 555 timer IC
strip line is 50 Ω .
VCC = 5V to 18V
higher output current (Imax) = 200mA 68. In the process of fabricating monolithic
Temperature stability = 0.005% /ºC integrated circuits :
64. Which one of the following statements is (a) Only passive components are fabricated on
correct regarding integrated circuit the same chip
fabrication? (b) Active and passive components are fabricated
(a) IC offers increased reliability, improved on the separate chips
performance, high speed and lower power (c) The active and passive components are
consumption. fabricated on the same chip
(b) IC is a miniature, low cost electronic circuit (d) Only active components are fabricated on the
fabricated on a multi crystal chip of silicon. chip
(c) IC is a miniature, high cost electronic circuit KVS TGT (WE)- 2017, 2016
fabricated on a multi crystal chip of silicon. Ans. (c) : The monolithic fabrication process consist of
(d) IC offers decreased reliability, improved water preparation, epitaxial growth, diffused isolation, base
performance, low speed and higher power and emitter diffusion, pre-ohmic etch and final testing.
consumption. All the active and passive components required for the
IES-2021 circuit are fabricated on same chip.
Ans.(a) : Major advantage of integrated circuit- 69. Which one of the following requires additional
IC offers increases reliability, improved performance process steps in their fabrication?
high speed and lower power consumption. (a) Thin film resistor (b) Epitaxial resistor
More reliable because of the elimination of soldered
(c) Pinched resistor (d) Junction resistor
joints and the need for fewer interconnection.
ESE-2022
Increased operating speed because of on absence of
parasitic capacitance effect. Ans. (a) : Structure wise there are two types of resistors
IC is low cost electronic circuit fabricated on a like thin film and thick film resistors. The thin film
single crystal chip. resistors are a type of resistor that possess a thin
resistive layer sat on top of ceramic base. Thin film
65. Silicon has a preference in IC technology
because resistors are generally much more accurate, precise and
(a) it is an indirect semiconductor stable than thick film resistors.
(b) it is a covalent semiconductor 70. In monolithic integrated circuits, the
(c) it is an elemental semiconductor concentration of acceptor atoms in the region
(d) of the availability of nature oxides SiO2 between isolation islands will be
BSNL (JTO)-2006 (a) much higher than in the p-type substrate
Ans. (d) : Silicon has a preference in IC technology (b) much lesser than in the p-type substrate
because of the availability of nature oxide SiO2. (c) equal to the p-type substrate
66. In op-amp IC741, output is taken from the pin (d) not equal to the p-type substrate
number ESE-2022
(a) 3 (b) 6 Ans. (a): In monolithic integrated circuits the concentration
(c) 7 (d) 8 of acceptor atoms in the region between isolation Islands
Mizoram PSC Jr. Grade-2015, Paper-II will be much higher than in the p-type substrate.

02.
Analog Electronics
Vs − Vz
(i) Diode Circuit = 10mA + IL
100
10 − 5
1. Determine the current I for the Network shown = 10mA + IL
below. 100
5
= 10mA + IL
100
50 mA = 10mA + IL
IL = 40mA
V 5
R L = z = × 103
IL 40
R L = 125Ω
(a) 5.45 mA (b) 6.95 mA Now
(c) 8.95 mA (d) 7.45 mA IS = Izmax +ILmin
where ILmin →0
Ans. (b) : IS = Izmax
Pmin = Pmax
Pmax = Iz max × Vz max
Pmin = Pmax = 50mA × 5V
= 250 mW
3. Using a dc and ac voltmeter to measure the
output signal from a filter circuit, we have
obtain readings of 25 V dc and 1.5 V rms.
E1 − IR − 0.7 − 4 = 0
Calculate the ripple of the filter output voltage.
20 − 0.7 − 4 15.3 × 10−3 (a) 12% (b) 6%
I= = = 6.95mA (c) 4.24% (d) 8.48%
2.2 × 103 2.2
I = 6.95mA
Ans. (b) : Ripple of the filter output voltage
2. In the circuit shown below, the knee current of V ( rms )
the ideal zener diode is 10 mA. To maintain 5V (γ) = r × 100
across RL, the minimum value of RL in Ω and Vdc
minimum power rating of the zener diode in 1.5
mW, respectively, are = ×100
25
=6%
4. What are the output voltage levels for the given
circuit? (Assume Si diode)
(a) 125 and 250 (b) 125 and 125

(c) 250 and 125 (d) 250 and 250
GATE-2013 (a) – 16 V, 3.3 V (b) 16 V, 3.3 V
Ans. (a) : Iz = knee current = 10 mA (c) 16 V, – 3.3 V (d) –16 V, – 3.3 V
Vs = 10V, Vz = zener voltage = 5V UPRVUNL AE -19.07.2021, Shift-II
RL = min? Ans. (b) : When
Pmin = ? Vi = +ve voltage → Diode R.B → V0 = Vi = 16V
Is = Iz + IL Vi =–ve voltage → Diode F.B → V0 = 4–0.7 = 3.3.
Analog Electronics 199 YCT

5. For given clamper circuit (Fig.1), find the value
of output voltage, between t1 to t2, Assume the
input as shown in (fig.2) and diode is Silicon
diode.
Now, apply KVL in loop-2

V2 = Vm + V0 .......... (ii)
Putting the value of V0 from equation (i) in equation
(ii) V2 = Vm + Vm V2 = 2Vm
(a) V0 (t1 - t2 ) =9.3 (b) V0 (t1 – t2) = 5.3 Parameter Half Centre Bridge
(c) V0 (t1 – t2) =2.0 (d) V0 ( t1 – t2) =1.3 wave wave
RPSC ACF & FRO 23.02.2021 Average voltage Vm 2Vm 2Vm
Ans. (d) : Diode in on for the negative half cycle π π π
10 - VC + 2 - 0.7 = 0 RMS voltage Vm Vm Vm
VC = 11.3 2 2 2
V0 = V I - VC = 10 - 11.3 PIV Vm 2Vm Vm
= - 1.3 No. of diode 1 2 4
Hence, V0 (t1 - t2) = 1.3 7.
6. In a centre-tap full wave rectifier, Vm is the
peak voltage between the centre-tap and one of
the secondary. The maximum voltage across
the reverse biased diode is
(a) Vm (b) 2 Vm
(c) Vm/2 (d) 3 Vm
APPSC POLY. LECT. 14.03.2020 For the circuit in above figure the zener
current Iz and power dissipation are
(a) 20.16mA and 151 mW
Nagaland PSC CTSE (Diploma)-2017, Paper-II
(b) 20.16A and 151 W
(c) 2.016 mA and 151 W
CGPSC SO 14.02.2016
(d) 20.16mA and 151 W
APPSC Poly. Lect. 15.03.2020
TNPSC AE-2014
Mizoram PSC AE/SDO 2012-Paper-I UPPCL AE-05.11.2019, TNPSC AE- 2019
GATE-2004 CGPSC SO 14.02.2016
IES - 2002, 1993 Ans. (a) :
Ans. (b) :
20 − 7.5
IZ = = 20.16 mA
620
Pz = Vz Iz = 20.16 × 10−3 × 7.5
Peak inverse voltage :- It is a voltage across the diode Pz = 151.2mW
when it is reversed biased. 8. Which of the following is the main application
for +ve half cycle. of Zener diode?
(a) Voltage regulator (b) Rectifier
D1 → F.B. (c) Multivibrator (d) Amplifier
D 2 → R.B. APPSC Poly. Lect. 15.03.2020
Apply KVL in loop-1 RRB JE-01.09.2019, 3:00 PM – 5:00 PM
RRB SSE-03.09.2015, Shift-III
V0 = Vm ...........(i)
RRB SSE 21.12.2014, (Red)
Ans. (a) : Zener diode are used for voltage regulation as Ans. (b) : Given data can be represented by circuit,
reference elements, surge suppressors and in switching
application and clipper circuits. The load voltage equals
breakdown voltage VZ of the diode.
9. Schottky diodes drop about 0.3 V when
conducting. This diode is connected in series
with a resistor of 1 kΩ and forward biased with
a battery of 1 V. Calculate the diode current. Here, Vs = 17V, f = 50 Hz
(a) 0.5 mA (b) 0.7 mA Now applying KVL.
(c) 0.3 mA (d) 1 mA VA = V S Vk = 12V
NLC GET -24.11.2020 So,
Ans. (b) : VAK > 0 ⇒ VA –VK > 0
VS – 12 > 0
17 2 sin ωt – 12 ≥ 0
Now, at ωt = 0
Diode ON .
17 2 sin θ = 12
 12 
By using KVL– θ = sin–1  
−1V + 1k × I + 0.3 = 0  17 2 
= 29.943
1000I = 0.7
So, Vs is greater than 12V only in the period of 29.943º
0.7 to 150.05.
I=
1000 So, the conduction period of diode is
I = 0.7mA π – 2θ = π – 2 × 29.943
= 120º
10. The efficiency of half-bridge rectifier under 12. The ripple frequency in a full-wave rectifier is
best condition is: (a) double the input frequency
(a) 25.5% (b) 35% (b) equal to the input frequency
(c) 40.6% (d) 81.2% (c) half of the input frequency
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I (d) none of these
Mizoram PSC IOLM -2018, Paper II Nagaland PSC CTSE (Diploma)-2018, Paper-I
Nagaland PSC (CTSE) Diploma-2017, Paper II Nagaland PSC- 2018, Diploma Paper-II
RRB SSE 01.09.2015 Shit-I Mizoram PSC IOLM -2018, Paper II
TNPSC AE-2014 Nagaland PSC (CTSE) Diploma-2017, Paper II
IES - 2013 APGENCO AE- 23.04.2017
Ans. (c) : TNPSC AE-2013
BSNL(JTO)-2002, 2001
Parameters Half-wave Full-wave
Ans. (a) : The ripple frequency in a full-wave rectifier
Average Vm 2Vm is double the input frequency. fr = 2fi.
Voltage π π 13. The ripple factor in case of a full-wave rectifier
RMS Voltage Vm Vm is:
(a) 1.21 (b) 0.50
2 2 (c) 0.48 (d) 1.0
Voltage ripple 1.21 0.482 OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
factor Mizoram PSC IOLM -2018, Paper II
Rectifier 40.6% 81.06% Nagaland PSC (CTSE) Diploma-2017, Paper II
efficiency TSPSC Manager (Engg.) - 2015
11. A half-wave rectifier is used to charge a 12 V TSPSC (Manager) - 2013
battery through a resistance 'R'. The input IES - 2013, 2010, 1998
transformer is fed by 34 V AC with turns ratio Ans. (c) :
2 : 1. Calculate the conduction period of the Ripple factor :-
diode. The amount of AC present in the output the signal is
(a) 136º (b) 120º called as Ripple
(c) 173º (d) 137º •The ripple factor indicates the number of ripple present
ISRO Scientist December, 2017 in d.c output
• Center taped full wave rectifier (PIV) = 2Vm
AC voltage or current for all Q Given, Vm = 300 (full wave rectifier)
components rms value Therefore, center tapped full wave rectifier,
Ripple factor =
Average (DC)value of voltage PIV =2Vm= 2×300 = 600V
or current
16. As compared to a full wave rectifier using 2
diodes, the four diode bridge rectifier has the
2
V  dominant advantage of
γ =  rms  − 1 (a) Higher current carrying
 VDC  (b) Lower peak inverse requirement
Full wave Rectifier γ = 0.48 (c) Lower ripple factor
For half wave Rectifier = 1.21 (d) Higher efficiency
14. A Zener diode in the circuit shown in below Nagaland PSC (CTSE) Diploma-2017, Paper II
figure has a knee current of 5 mA, and a GPSC Asstt. Prof. 11.04.2017
maximum allowed power dissipation of 300 ISRO Scientist Engg.-2011, 2008
mW. What are the minimum and maximum IES - 1993
load currents that can be drawn safely from the Ans. (b) : Given,
circuit, keeping the output voltage V0 constant Full wave rectifier (Center tapped) using number of
at 6 V? diode = 2
And bridge rectifier using diode = 4
Then advantage-
Bridge rectifier peak inverse voltage = Vm
full wave rectifier (Center tapped) PIV = 2Vm
17. The form factor for half wave rectified sine
wave is
(a) 0 mA, 180 mA (b) 5 mA, 110 mA (a) 1.0 (b) 1.11
(c) 10 mA, 55 mA (d) 60 mA, 180 mA (c) 1.44 (d) 1.57
TNPSC AE - 2018 Nagaland PSC (CTSE) Diploma-2017, Paper II
BARC Scientific Officer-2016 TNPSC AE-2014
ISRO Scientist Engg.-2011, 2007 ISRO Scientist Engg. - 2011
GATE-2002, 1996 BSNL (JTO)-2006
Ans. (c) : Given, RMS value V0 (rms)
Iz = 5mA, V0 = Vz = 6V Iknee = 5mA. Ans. (d) : Form Factor = =
Average value V0 (avg )
Rs = 50Ω, Vi = 9V
∴ Max power dissipation 300mW. For Half wave Rectifier
Pz( max ) 300 V /2
∴ I z(max) = = = 50mA FF = m = π/ 2
VZ 6 Vm / π
Vi − Vz 9 − 6 3 FF = 1.57
Q Is = = = = 60mA
Rs 50 50 18. Bridge rectifier are preferred because
Q I L(min) = Is − I z(max) = 60 − 50 = 10mA. (a) They require small transformer
And, I z(max) = Is − I z = 60 − 5 = 55mA (b) Less peak inverse voltage
(c) (a) and (b) both
15. In a full wave rectifier circuit with centre tap (d) None of these
transformer, if voltage between one end of
secondary winding and centre tap is 300V Nagaland PSC CTSE (Diploma)-2018, Paper-I
peak, then PIV (Peak inverse voltage) is RRB SSE 02.09.2015, Shift-I
(a) 300 V (b) 150 V Mizoram PSC IOLM-2010, Paper-II
(c) 600 V (d) 900 V Ans. (c) : Bridge rectifier requires comparatively small
TNPSC AE - 2018 transformers as required for centre tap full wave
Mizoram PSC Jr. Grade-2015, Paper-II rectifier and this is due to no requirement of centre
RRB SSE 01.09.2015, Shift-III tapping at all. Also PIV for diodes in bridge rectifier is
UPPCL AE-16.11.2013 Vm while in centre tap full wave rectifier it is 2Vm, so
ISRO Scientist Engg.-2012 less peak inverse voltage.
Ans. (c) : Q Peak inverse voltage- Peak inverse 19. A 5V reference is drawn from the circuit shown
voltage means that max voltage appears across the in the figure. Zener diode of 400mW and 5V
diode when it is in non conducting. with firing current of 5mA is used. The value of
• Half wave rectifier (PIV) = Vm RS is

Given,
Voltage across AB is 6.2V
Q VAB = VAC + VCB
at 25º C:-
VAB (6.2V) = VAC (0.7V) + VCB(5.5V) at 65ºC
(a) 50 ohms (b) 500 ohms ∵ VCB = 100 × 55mA 
(c) 75 ohms (d) 470 ohms  
 VCB = 5.5V 
Ans. (a) : For every one degree rise in temperature - 2.5mV
decrease across AC (i.e. base to emitter junction).
2.5mV
VAC = 0.7 − × 40º C
1º C
VAC = 0.7V−0.1 V = 0.6 V
VAB = VAC + VCB
VCB = VAB − VAC
⇒ VCB = 6.2 − 0.6
Given Vz = 5V VCB = 5.6
Load current (IL) = 95 mA Current through - 100Ω
Q Unregulated input V = 10V V
I = I Z + IL I L = CB
R
I = 95mA + 5mA 5.6
I = 100mA IL =
100
Voltage drop across Rs, = 56 × 10 −3
Vs = 10 − 5 = 5V
I L = 56mA
5 5000
Therefore , R s = = = 50Ω 21. In this circuit, V is a sinusoid input with
100mA 100
frequency f, current I contains :
20. The zener diode shown in following figure is I
temperature compensated and current gain β
of transistor is very high. If current through
100 ohm resistor is 55 mA at 25ºC, what is the
approximate current through it at 65ºC
(a) Only f
(b) All harmonics of f
(c) Only even harmonics of f
(d) Only odd harmonics of f
Ans. (b) :
(a) 55 mA (b) 54 mA
(c) 56 mA (d) 100 mA
Ans. (c) :
Operation –
If D1 = forward bias
D2 = Reverse bias
Then D1 = diode will be allow the current flow.
If D1 = Reverse bias
D2 = Forward bias
Then, D2 diode will be allow the current flow.
Therefore, current I contain all harmonics of frequency.

22. Determine the Voltage transfer characteristics having the following periodical input signal
of the following circuit comprising of Zener 'Vi(t)'?
diodes having identical characteristics with
Zener Breakdown voltage Vz and Diode cut-in
voltage VT.
(Assume cut-in voltage of the Diode=0V;

Forward resistance of the Diode=2Ω)
(a) 1.25 V (b) 2.5 V
(c) 0 V (d) 0.1 V
Vp Np 1
Ans.(b): = =
Vs Ns 2
Vs = 2Vp
When diode is in forward bias then replaced by forward
resistance of diode = 2Ω
Voltage across 2Ω is
2
V2Ω = × 2 × 5.2 = 0.4V
50 + 2
ISRO Scientist Engg.-2018 Q voltage is connected is reverse polarity
So, V01 = –0.4V
Ans.(a): → ( VT + VZ ) > Vi > 0
When diode D1 is reverse biased
since VZ > Vi
therefore
V0 = Vi
When diode is reverse bias then
→ ( VT + VZ ) < Vi
D1 is reverse breakdown region
D2 is in forward biased with cut in voltage VT
∴ V0 = VZ + VT
→ 0 > Vi > − ( VT + VZ ) V02 = ( −2 × 5.2 ) = +10.4V
D2 acts as zener diode, D1 is in forward biased
So, V0 = − ( VT + VZ )
23. What will be the voltage reading of DC

Voltmeter placed across the terminals of the The DC voltage roads only average value of voltage,
Diode in the given circuit, VDC = Average value of V0,
1  π 2π
= ∫ V01dt + ∫ V02 dt 
2π  0 π 
1 1 1 
= × π× ( −0.4 ) + × π×10.4
2π  2 2 
1
= × 10π = 2.5V
4π

24. The output voltage (V0) of the circuit shown in IE = 0.93 A
the given figure is IE = IC + IB = (β + 1) IB
I
IB = E
1+ β
0.93 0.93
= =
1 + β 101
= 9.2 mA
So, the current through the 10 V zener diode is.
(a) Zero (b) 5.7 V
(c) 6.9 V (d) 12.6 V I Z = ( 20 − 9.2 ) mA
ISRO Scientist Engg.-2006 I Z = 10.8mA ≈ 10.3mA
IES - 1995 26. What could be the output current rating of
Ans. (c) : following shunt regulator?
IZ
IL
Zener diode will be forward bias and other will behave (a) 0 < IL < 100mA
as normal diode. (b) 20mA < IL < 100mA
So, voltage drop is 0.6 V and other zener diode will be (c) 0 < IL < 50mA
reverse bias and voltage drop will be 6.3V (d) 10mA < IL < 100mA
V0 = 6.3 + 0.6 ISRO Scientist Engg.-2013
V0 = 6.9 V Ans. (b) : Zener diode operate reverse is reverse bias,
25. Common emitter DC current gain of the Power rating of the diode,
transistor is 100. The current through the 10 V 0.4W = 5 × I (Where IZ = Imax)
max
Zener diode (assuming VBE of the transistor is
0.7 V) is: 0.4
I m ax = = 80mA
5
Q Apply KCL at circuit,
10 − 5
= IZ + IL
50
I Z + IL = 100mA
I L = 100 − 80 = 20mA
Since, IL will not be below 20 mA, the power rating of
(a) 10.3 mA (b) 19.3 mA diode will be broken and I will not be above 100 mA.
(c) 20 mA (d) 40 mA (no longer be in reverse bias).
ISRO Scientist Engg. -2015 So, 20 mA<IL<100mA.
Ans. (a) : Given β = 100 27. A PN junction is series with a 100 ohm resistor
is forward biased so that a current of 100 mA
flows. If the voltage across the combination is
instantaneously reversed to 10V at time t = 0,
the reverse current that flows through the
junction at t = 0 is approximately given by.
(a) 0 mA (b) 200 mA
IB
(c) 50 mA (d) 100 mA
IE Ans. (d) : The diode is forward biased so that a current
flow = 100 mA.
Applying KVL When immediately switched will be Reversed bias for
20 − 10 short time then allow the flow reverse current and
= I1 forward voltage. This is called reverse recovery time.
0.5 ×103 During this time diode allow current to flow in reverse
I1 = 20mA direction.
10 − 0.7 So t = 0, In reverse bias,
= IE
10 I = 100 mA.

28. Output response of a diode clipper circuit
shown in figure will be
(a) 1.2 k ohms (b) 80 ohms

(c) 50 ohms (d) 0 ohms
GATE-1992
Vz = 6V, IZK = 5mA
10 − 6 4
I= = = 80mA
50 50
IL max = I–IZK
= (80 – 5) mA
IL max = 75 mA
VL 6V
ISRO Scientist Engg.-2016 So, R L min = = = 80Ω
IL max 75mA
Ans.(a): Condition-
(i) If diode is off, then output 30. The voltages at V1 and V2 of the arrangement
VB shown in the figure will be respectively
R
V0 = Vi − VB − IR
( Vi − VB − IR > 0 )
(ii) If diode is on
Vi − VB − IR < 0
V0 = 0
If R>>>0 then, ( I  0 ) , (R = very large)
IR  0 (a) 6 V and 5.4 V (b) 5.4 V and 6 V
(c) 3 V and 5.4 V (d) 6 V and 3 V
Vi − VB > 0
V0 = Vi − VB Ans. (d) : If we consider given diodes are ideal, then,
Vi − VB < 0 (
voltage VD2 = VD1 = 0 )
V0 = 0
Therefore, only option (b) valid, if IR  0
And option (a) is correct, because V0 never follows Vi
in the given circuit.
29. The 6V Zener diode shown in the figure, has
zero zener resistance and a knee current of
5 mA. The minimum value of R so that the
voltage across it does not fall below 6 V is

VA 2 − VC2 = 3 – 6 = –3 < 0 R o × Vi 20 × 20
V0 = =
Hence D2 is off R o + R L 20 + 20
VA1 − VC1 = 6 – 3 = 3 > 0 20 × 20
V0 = = 10V
40
Therefore zener diode across voltage-
Vz = 10 + 0.2 = 10.2
V0 < 10.2
∴ Diode branch can not operate,
So, V0 = 10V
32. What is the output voltage across the 900 ohm
Hence, D1 is ON and V1 = 6V load in the circuit given below?
If we consider given diodes are practical, then cut-in
voltage across diode, = 0.6 V
(a) 10 V (b) 14.67 V

(c) 20 V (d) 9.47 V
Ans. (d) : When 20V D1 is ON AND 10V D2 is OFF.
Ω
V1 = 6V, V2 = 3 V
31. The Zener regulator circuit shown below
consists of Si based Zener diode and Ge diode. Ω
The cut-in voltage of Ge diode is 0.2 volts,
whereas cut-in voltage of Si-diode is 0.7 volts.
20 × 900
V0 = = 9.47V
900 + 1000
Output voltage V0 is less than breakdown voltage of D2,
that is 10V, therefore, our assumptions right if D2 is
OFF.
33. In the Voltage regulator circuit as shown
below, the maximum load current iL that can
be drawn is :
(V0) of the Zener regulator circuit is
(a) 10.2 V (b) 10 V
(c) 9.8 V (d) 0.2 V
Ans. (b) :
(a) 1.4 mA (b) 2.3 mA

(c) 1.8 mA (d) 2.5 mA
(e) 2.8 mA
CGPSC SO 14.02.2016
Operation- Ans. (a) :
Zener off in reverse bias and on in break down
condition.
Or
Vi < Vz = zener diode off
And Vi ≥ Vz = zener diode on
Apply voltage division

30 − 9 Ans. (c) :
IS =
15 × 103
21
IS =
15 × 103
IS = 1.4mA
IS = IL +IZ
I L max = IS max − I Z min Apply KVL in loop,
I L max = IS Q( Iz min = 0 ) 12 − 0.3 − 0.7
RL = = 5.55 × 103 Ω = 5.5kΩ
2 × 10 −3
I L max = 1.4mA
38. If the input applied to circuit is sine waveform
34. In a half wave rectifier, the load current flows
for what part of the cycle. with amplitude 12 Vp-p sine waveform, then
(a) 40º (b) 90º output voltage is .(Assume ideal diode)
(c) 180º (d) 360º
Mizoram PSC IOLM -2018, Paper II
Ans. (c) : In Half wave rectifier we know that the
current flow when diode in ON state. diode ON for
180º. (a) +6 Vp-p (b) +12 Vp
Hence current will flow for 180º (c) – 12 V p-p (d) +12 Vp-p
35. In a full wave rectifier, the current in each UPRVUNL AE -19.07.2021, Shift-II
diode flows for Ans. (b) :
(a) Whole cycle of the input signal
(b) Half cycle of the input signal
(c) More than half cycle of the input signal
(d) None of these
Ans. (b) : In full wave rectifier, either bridge or centre
tapped, the current through each diode will flow for
half cycle. while load current will flow through over full
cycle.
36. To get a peak load voltage of 40V out of a
bridge rectifier. What is the approximate rms
For Vi = + Ve Diode F.B V0 = Vi = +12Vp
value of secondary voltage?
(a) 0V (b) 14.4V For Vi = – Ve Diode R.B V0 = 0.
(c) 28.3V (d) 56.6V 39. The RMS value of load current in a half-wave
Nagaland PSC (CTSE) Diploma-2017, Paper II rectifier is
Ans. (c) : Vm= 40V
(a) I m / 2 (b) Im/2
Vm
V0 (rms) = I I
2 (c) 2 m (d) m
π π
40
V0 (rms) = TNPSC AE - 2018
2
Ans. (b) : For Half wave rectifier–
V0 (rms) = 28.3V
37. What is the value of load resistance used in
circuit shown in the given figure?
Im 2 × π Im 2 I m
I rms = = =
2 × 2π 4 2
(a) 2k ohms (b) 7.5k ohms Im
(c) 5.5k ohms (d) 9k ohms Io( rms ) =
2
40. The percentage regulation of Half-wave Vo = 11volt
rectifier is
11
V − Vload I D = Vo / R =
(a) no load × 100% 5.6 × 103
Vno load
I D = 1.96 mA
Vload − Vno load
(b) × 100% 43. When the input waveform and circuit of a
Vload Clamper is given as shown in figure and a dc
volt meter indicating the voltage across the
Vno load − Vload
(c) × 100% output A and B (Grounded) – will show
Vload
Vload − Vno load
(d) × 100%
Vno load
TNPSC AE - 2018
Vn − Vf (a) + 10 V (b) – 10 V
Ans. (c) : Voltage regulation = ×100%
Vf (c) + 20 V (d) –20 V
Vno load − Vload TNPSC AE - 2018
For rectifier ⇒ %V.R = × 100% Ans. (d) : Voltage contain by one capacitor = Vm
Vload Vo = – Vm – Vm = –2Vm
41. The output DC voltage of a full-wave rectifier Vo = – 2 × 10
is Vo = −20V
2Vm Vm
(a) Vdc = − Idc R f (b) Vdc = − Idc R f 44. The equivalent dc output voltage of a half wave
π π rectifier is ________ the equivalent dc output
(c) Vdc = 2Vm − Idc R f (d) Vdc = Vm − Idc R f voltage of a full wave rectifier.
TNPSC AE - 2018 (a) equal to (b) half
(c) double (d) not related to
Ans. (a) : For full wave rectifier–
TNPSC AE - 2018
2Vm
Vo(avg) = Ans. (b) : DC output voltage-
π V
When diode resistance is consider– For half wave rectifier VDC = m
π
2Vm 2Vm
V0(avg ) = − I dc × R f For full wave rectifier VDC =
π π
Hence dc output voltage of half wave rectifier is half of
42. For the circuit shown in Figure 1, the Vo and ID
full wave rectifier dc output voltage.
will be
45. For a 20V Zener diode, if temperature is
increased to 100ºC (boiling point of water).
The change in Zener potential will be
(Assume temperature coefficient = 0.072/ºC
and Room temperature = 25º C.)
(a) 0.51V (b) 4.12 V
(c) 1.08 V (d) 7.20 V
(a) Vo = 12 V and ID = 2.1 mA
RPSC ACF & FRO 23.02.2021
(b) Vo = 11.3 V and ID = 2.0 mA
T V
(c) Vo = 11 V and ID = 1.96 mA Ans. (c) : ∆VZ = C Z (T1 − T0 )
(d) Vo = 11.7 V and ID = 2.1 mA 100º C
TNPSC AE - 2018 (0.072/ºC) × 20
= × (100 − 25)
Ans. (c) : Equivalent circuit diagram – 100
∆VZ =1.08 V
46. RC time constant of a clamper circuit should
be
(a) Small enough that the capacitor will not
discharge during non-conducting period of
diode
(b) Large enough that the capacitor will
V0 = Vin – VSi – VGe discharge during non-conducting period of
= 12 – 0.7 – 0.3 diode.
(c) Small enough that the capacitor will −5 + .7 + .7 + 2 ( I1 + I2 ) + 5 = 0
diode 2I1 + 2I2 = −1.4 ………(ii)
(d) Large enough that the capacitor will not 2I1 + 2I 2 = −1.4
diode. 2I1 + 4I 2 = 4.3
RPSC ACF & FRO 23.02.2021 −2I 2 = −10
Ans. (d) : τ = CR I 2 = −5 mA
Values of R and C should produce a time constant 2I1 + 2I2 = −1.4
which us large enough in ensure that capacity remains
almost fully charged during the time period of the 2I1 + 10 = −1.4
signed for good damping action, the RC time constant 2I1 = –11.4 mA
should be at least ten times the time period of the what I1 = –5.7 mA
signed voltage. According to above value
47. The diodes are used in series to
I1 = − ve No possible.
(a) increase current carrying capacity
(b) increase PIV D2 is on and D1 is off
(c) reduce PIV Hence diode D2 is off so
(d) reduce resistance
Ans. (c) : Diodes are connected together in series to
provide a constant DC voltage across the diode
combination the output voltage remain constant and it
decrease the PIV.
48. Consider the circuit shown below. Find the
output voltage V0 for input voltage Vi = 5V. Apply KVL – –10 + 2I2 + 0.7 + 2I2 + 5 = 0
Assume the voltage drop across a conducting 4I2 = 4.3
diode is 0.7 V. I2 = 1.075 A
V0 = 10 – 2I2
V0 = 7.85 Volt
49. In the circuit shown below the diodes are ideal.
Value of V0 is
(a) 8.65 V (b) 6.5 V

(c) 7.85 V (d) 5 V
UPPCL AE- 31.12.2018
(a) –0.8 V (b) 0.5 V
Ans. (c) : Consider both diode are ON
(c) 0.0 V (d) 0.6 V
UPPCL AE- 31.12.2018
Ans. (b) : From the circuit, it is clear that at a time only
diode is conduct, either both will be off.
Apply ground to ground KVL

Loop-1
−10 + 2I2 + 0.7 + 2 ( I1 + I 2 ) + 5 = 0 0.5 − 100I1 − 0.6 = 0 −0.8 − 100I 2 − 0.5 = 0
−10 + 2I2 + 0.7 + 2I1 + 2I2 + 5 = 0 −0.1 = 100I1 −1.3 = 100I2
4I 2 + 2I1 = 4.3 …….. (i) 0.1 1 1.3
I1 = − =− A I2 = −
Loop-2 100 1000 100

I1 = − ve Not possible I 2 = − ve Not possible 53. In a diode clamping, when Rs = 0, the result is
(a) good impedance matching
Hence both diode will OFF so (b) the magnitude of discontinuity in input and
V0 = 0.5 V equal to source voltage. output waveforms is same
50. The circuit shown in the figure is best (c) large source current into the clamping circuit
described as a (d) no clamping operation
TNPSC AE-2014
Ans. (b) : A clamper is a network constructed of a
diode, a resistor, and a capacitor that shifts a waveform
to a different dc level without changing the appearance
of the applied signal.
In a diode clamping, when Rs = 0, the result is the
magnitude of discontinuity in input and output
(a) Bridge rectifier (b) Voltage doubler
waveforms is same.
(c) Ring modulator (d) Clamper
TNPSC AE-2014 54. Clamping circuit theorem is mathematically
GATE-2003 expressed in the standard notation as
Ans. (b) : Voltage Doubler– Af R Af R f
(a) = (b) =
Ar R f Ar R
Ar R f Ar R
(c) = (d) = 1+ f
Af R Af R
TNPSC AE-2014
Ans. (b) : The clamping circuit theorem states that
under steady state conditions, for any input waveform,
the ratio of the area under the output voltage curve in
the forward direction to that in the reverse direction is
If Vi = +Vm
equal to the ratio of Rf/R.
Then VAG = Vm + Vm = 2Vm
D2 operates in forward bias and C2 charges through D2 Af R f
=
upto voltage 2Vm. Ar R
51. At the break point of a clipping circuit, a diode
behaves as 55. A sinusoidal wave of amplitude Vm is applied as
(a) Short circuit and open circuit simultaneously an input to the parallel diode clipping circuit
(b) Short circuit shown in fig. What is its output voltage?
(c) Open circuit
(d) It is difficult to decide
TNPSC AE-2014
Ans. (a) : A clipping circuit requires a minimum of two
components i.e. a diode and a resistor, the input
waveform can be clipped at different levels by simply
changing the battery voltage and by interchanging the
position of various elements. We will use an ideal diode
which acts like a closed switch when forward-biased (a) Output is allowed in between VR and +Vm
and as an open switch when reverse biased. (b) Output is allowed in between –VR and +Vm
52. In the break region of clipping circuit, a diode (c) Output is allowed in between –VR and –Vm
behaves as (d) Output is allowed in between –Vm and VR
(a) fully on
TNPSC AE-2014
(b) it is difficult to decide
(c) fully off Ans. (a) :
(d) neither fully on nor fully off
TNPSC AE-2014
Ans. (d) : Clippers are networks that employ diodes to
"dip" away a portion of an input signal without
distorting the remaining part of the applied waveform.
At the break region of a clipping circuit, a diode
behaves as neither fully on nor fully off.

59. Circuit shown in fig. is a basic
(a) clipping circuit (b) clamping circuit

(c) two level clipper (d) none of these
TNPSC AE-2013
Ans. (b) : This figure is a clamping circuit. A clamping
So, output is allowed in between VR and +Vm. circuit is a circuit that adds a dc level to an ac signal.
56. The effect of dc saturation in a rectifier
transformer is
(a) to decrease the output
(b) to increase the output
(c) to decrease the ac components of the output
(d) none of these 60. What will be the average value of V(t) in the
TNPSC AE-2013 circuit given below
Ans. (a) : A rectifier transformer is a transformer which
include diode or thyristor in the same tank. Voltage
regulation also be include the effect of dc saturation in a
rectifier transformer is to decrease the output.
57. The rectifier, which requires minimum amount
of filtering is (a) – Vm/π (b) – Vm/2π
(a) half-wave rectifier (c) – Vm/ 2 (d) 0
(b) full-wave rectifier MPPSC Forest Service Exam.-2014
(c) voltage doubler circuit Ans. (a) :
(d) SCR half-wave rectifier
TNPSC AE-2013
Ans. (b) : A full wave rectifier produce more output
voltage hence it requires minimum amount of filtering
circuit as compare to other single phase rectifier.
58. In the following circuit diagram, if the input
V1 ≤ VR1, the O/P V0 is Diode is connected from load to source. Hence
V
V0(avg) = − m
π
61. What type of diode circuit is used to add or
restore a dc level to an electrical signal?
(a) Clipper (b) Clamper
(c) Voltage Regulator (d) None of these
Ans. (b) : A Clamper is a network used to reinsert or
(a) VR1 (b) VR2
restore dc component into a waveform which has been
(c) V1 (d) VR2 – VR1 lost after passing through a processing network such as
TNPSC AE-2013 an amplifier. Hence a clamper is also called dc restorer.
Ans. (a) : When V1 ≤ VR1 diode D1 is ON and D2 is 62. Which type of diode circuit is used to clip off
portions of signal voltages above and below
OFF.
certain levels?
(a) Clipper (b) Clamper
(c) Voltage Regulator (d) None of these
Ans. (a) : Clippers are networks which employ diodes
to "clip" away a portion of an input signal without
distorting the remaining part of the applied waveform.
63. The RMS value of a half-wave rectified
V0 = VR 1
symmetrical square wave current of 2A is
(a) 2A (b) 1A 40µF capacitor in parallel with a 250Ω resistor.
The diode and transformer resistances and
1 leakage reactance are neglected. If the power
(c) A (d) 3 A
2 line frequency is 50 Hz, the dc current in the
TRB Poly. Lect. -2012 circuit will be
Ans. (a) : (a) 132 mA (b) 144 mA
(c) 156 mA (d) 168 mA
IES-2020
Ans. (a) : Given value
Vrms = 35V, C = 40 µF
RL = 250Ω, f0 = 50 Hz
1 2π 2
2π ∫0
I 2rms = i dt
1  π 2 2π
= ∫ i dt + ∫ 0dt 

2π  0 π 
1 π Q DC output voltage in VDC = IDC × R L
2π ∫0
= 22 dt
VDC = 250 × IDC ......(i)
4π ∴ Single phase full wave rectifier,
= =2
2π I DC
I rms = 2 A VDC = Vm − .......(ii)
4f 0C
64. The circuit shown in the figure is a So,
From equation (i) and (ii)
I
250 × I DC = Vm − DC
4f 0C
I DC
I DC × 250 = 35 2 −
( 4 × 50 × 40 ×10 )
−6
(a) positive clamper (b) negative clamper I DC × 250 = 35 2 − 125I DC

(c) positive clipper (d) negative clipper
DMRC AM S&T-2020 35 2
I DC = = 0.132A
RPCS Lect.-2011 375
Ans. (a) : The circuit shown is a positive clamper. IDC = 132mA
67. A three-phase full wave rectifier with resistive
load has a ripple factor
(a) 0.482 (b) 1.000
(c) 0.055 (d) 0.500
IES-2020
The positive clamper is made up of a voltage source Vi
capacitance C, diode D and load resistance RL, in the Ans. (c) :
above circuit diagram the diode is connected in parallel Ripple factor single phase full wave Rectifier = 0.482
with the output load. So the positive clamper passes the Ripple factor three phase half wave Rectifier = 0.17
input signal to the output load when the diode is reverse Ripple factor for single-phase half-wave rectifier =1.21
biased and blocks the input signal when the diode is Value of ripple factor in three phase Rectifier with
forward biased. resistive load is very less than single phase Rectifier
65. In a zener diode Hence, correct option (c)
(a) Only the P region is heavily doped 68. Crest factor for an alternating current source
(b) Only the N region is heavily doped is the ratio of
(c) Both P and N regions are heavily doped (a) Maximum value of RMS value
(d) Both P and N regions are lightly doped (b) RMS value to maximum value
Nagaland PSC CTSE (Degree)- 2016, Paper-I (c) RMS value to average value
Ans. (c) : A zener diode is a silicon semiconductor (d) Maximum value to average value
device that permit current in reverse direction. It is a IES-2020
heavily doped p-n junction diode.
Peak Value
66. A single phase full wave rectifier uses Ans. (a): Crest factor =
semiconductor diodes. The transformer voltage RMS Value
is 35V rms to center tap. The load consists of a Crest factor for an alternating current source is ratio

of maximum value of RMS value. 70. The components of full-wave voltage doubler
Maximum value of crest factor is half wave Rectifier circuit are
is (a) 2 diodes and 1 capacitor
Type Wave R.M.S Crest (b) 4 diodes and 1 capacitor
wave form value factor (c) 2 diodes and 2 capacitors
(1) Sine (d) 4 diodes and 2 capacitors
1
= 0.707 2 = 1.414
wave IES-2019
2
Ans. (c) :
(2) Full- Full wave voltage doubler circuit diagram
1
= 0.707 2 = 1.414
wave
2
Rectifier
(3) Half 1 2
wave = 0.5
2
Rectifier
69. The input to a bridge rectifier is 230 V (r.m.s),
50 Hz. The d.c. output voltage and the ripple
factor with RL of 100Ω and capacitor filter of
1000µF are
(a) 207 V and 0.028 (b) 325 V and 0.028 Half wave Full wave
(c) 207 V and 0.020 (d) 325 V and 0.020 Parameters
voltage doubler voltage doubler
IES-2019 Ripple content High Low
Ans. (a) : Given, Better than
VS = 230 (rms) Voltage
Poor half-wave •
f = 50 Hz regulation
voltage doubler
C = 1000 µF
PIV Rating 2Vs max 2Vs max
RL = 100Ω
The maximum
voltage across 2Vs max Vs max
each capacitor
The circuit consists of 2 capacitor and 2 diode
71. The peak-to-peak ripple voltage for a half-
wave rectifier and filter circuit operating at 60
Hz, which has a 680 µF reservoir capacitor, an
Vm average output of 28 V and 200Ω load
Bridge rectifier, Vrms = resistance, will be nearly.
2 (a) 2.5 V (b) 3.4 V
Vm = 2 Vrms .....(i) (c) 4.3 V (d) 5.2 V
IES-2019
2Vm
Q VDC = Ans. (b) Given-
π
2 × 2 × Vrms
=
π
2 × 1.41× 230
=
3.14 R L = 200Ω
= 206.56 Volt f = 60Hz
VDC = 207 Volt C = 680µF
Ripple factor, Vdc = 28V
1
Rf = • Peak to peak ripple voltage-
4 × 3f CR L I Vdc 28
Vr = dc = =
1 f C f C ⋅ R L 60 × 680 × 10−6 × 200
=
4 × 3 × 50 × 1000 × 10−6 ×100 28
Vr = = 3.43Volt
Ripple factor (Rf) = 0.0288 6 × 104 × 68 × 10−6 × 2
72. The voltage transfer characteristics as shown in 75. A full wave rectifier uses 2 diodes. The internal
the figure will relate to a resistance of each diode is 20Ω. The
transformer RMS secondary voltage from
centre tap to each end of secondary is 50 V and
the load resistance is 980Ω. Mean load current
will be
(a) 45 A (b) 4.5 A
(c) 45 mA (d) 45µA
IES-2015
1. Voltage regulator Ans. (c) : Given,
2. Half-wave rectifier
3. Full-wave rectifier
Which of the above is/are correct?
(a) 1 only (b) 2 only
(c) 1 and 2 (d) 1 and 3
IES-2018
Ans. (a) : Voltage Regulator- A transformer having its
primary winding in shunt and its secondary winding in RL = 980Ω , Rf = 20Ω
series with alternating-current circuit the voltage of
which may be regulated by varying of which may be Vrms = 50V Vm = 50 2
regulated by varying the voltage ratio of transformation. Vm1 = Vm2 = Vm = 50 2
73. The capacitance of a full wave rectifier, with
rectifier, with 60 Hz input signal, peak output Vm 50 2 2
Im = = =
voltage Vp = 10 V, load resistance R = 10kΩ R f + R L 20 + 980 20
and input ripple voltage Vr = 0.2V, is
2 Im 2 × 2
(a) 22.7µF (b) 33.3µF IDC = = = 45mA
(c) 41.7µF (d) 83.4µF π 20 × π
IES-2016 76. A full wave rectifier with a centre tapped
transformer supplies dc current of 100 mA to a
Ans. (c) Given
load resistance of 20Ω. The secondary
f = 60Hz, Vp = 10V, R = 10kΩ resistance of transformer is 1Ω. Each diode has
Ripple voltage Vr = 0.2V a forward resistance of 0.5Ω. What are rms
Full-wave rectifier with capacitor filter values of signal voltage across each half of the
secondary as well as dc power supplied to the
VP 10
Ripple voltage = = load ?
2fCR 2 × 60 × 10 ×103 × C (a) 2.39 V and 0.2 Watt
(b) 23.9 V and 2 Watts
10 10 (c) 0.239 V and 20 Watts
0.2 = ,C = = 41.67µF
120 × 10 × 103 × C 0.2 × 120 × 10 ×103 (d) 2.39 V and 2 Watts
74. A power supply uses bridge rectifier with TSGENCO AE-2015, IES - 2014
capacitor input filter. If one of the diodes is Ans. (a) :
defective, then Given,
1. The dc load voltage will be lower than its Rf = 0.5Ω , IL = 100 mA RL = 20Ω
expected value.
I = 100mA
2. Ripple frequency will be lower than its DC
expected value I m = 157mA
3. The surge current will increase manifold. load resistance(R L ) = 20Ω
R F = 0.5Ω
(c) 1 and 3 only (d) 1, 2 and 3 R sec = 1Ω
IES-2015
Ans. (d) : Power supply uses bridge rectifier with
capacitor input filter if one of the diodes is defective
then results occurs.
• DC load voltage will be lower than its expected value.
• Ripple frequency will be lower.
• Surge current will increase manifold.
All of the above statements are correct.
2I m When diode is forward biased, if can be Replaced by
Idc = dynamic resistance Rd
π In a half-wave Rectifier, an output d.c voltage is given
π Idc by
Im =
2 Vdc = Idc × R L
I π Idc π × 100 
I rms = m = = mA Im Vm 
2 2 2 2 2 Vdc = × RL ∵  Im = 
π  Rd + RL 
I rms = 111.072 mA
Vm
Vrms = I rms × ( R L + R I + R sec ) Vdc = × RL
π (Rd + RL )
= 111.072 × ( 20 + .5 + 1) Where,
= (111.072 × 21.5) mV R L → load Resistance
= ( 2388.048 ) mV R d → forward diode Resistance
Vrms = 2.39 Volt Vm → maximum supply voltage
PDC = D.C power supply to the load Idc → output d.c current
= IDC 2 × R L Given,
= 100 × 100 × 10 −6 × 20 R d = 25Ω, R L = 800Ω, Vdc = 50V
= 10 −2 × 20 V
Output dc voltage = m ×
800
20 π 800 + 25
= = 0.2W
100 V 800
50 = m ×
PDC = 0.2W π 825
77. A bridge rectifier uses a 9 V a.c. input voltage. 50 × π × 825
The diodes are ideal. What is the d.c. output Vm = 800
voltage ?
(a) 12.726 V (b) –12.726 V V m = 51.562 π Volt
(c) 9 V (d) 8.1 V 79. A 40 V dc supply is connected across - the
IES – 2016, 2014 network comprising of Zener and silicon diodes
as shown. The regulated voltages V01, V02 and
Ans. (d) : Given, source current Is are
Input voltage ( Vrms ) = 9V
Vm
Vrms =
2
Vm = Vrms × 2 = 9 2
2Vm
Output voltage =
π
(a) 2.4 V, 5.1 V and 21.7 mA
2× 9 2 (b) 3 V, 6 V and 22.7 mA
= = 8.1V
π (c) 33 V, 9.3 V and 20.5 mA
78. A half-wave rectifier is used to supply 50 V d.c. (d) 4 V, 10 V and 20 mA
to a resistive load of 800Ω. The diode has IES - 2012
resistance of 25 Ω. What is the required a.c. Ans. (d) :
voltage ?
(a) 50π (b) 51.5π
(c) 25.7π (d) 25π
IES - 2014
Ans. (b) : Given,
RL = 800Ω , Rd = 25Ω
Cut in voltage of Si = 0.7 V
V01 = ( Si + Zener ) in cuting voltage
= 0.7V + 3.3V = 4.0 Volt
V02 = 4V + 6V
= 10V

40 − V02 82. Consider the following statements :
IS = When compared with a bridge rectifier, a
1.5 × 10 3
centre-tapped full wave rectifier:
40 − 10 30
IS = = = 20 mA 1. Has larger transformer utilization factor.
1.5 ×103 1.5 × 103 2. Can be used for floating output terminals i.e.
80. For a full wave rectifier, with sinusoidal input no input terminal is grounded.
and inductor as filter, ripple factor for
maximum load current and minimum load 3. Needs two diodes instead of four.
current conditions are respectively 4. Needs diodes of a lower PIV rating.
(a) 0.1 and 1 (b) 0.1 and 0.47 Which of the above statements are correct ?
(c) 0 and 0.47 (d) 0 and 0.22 (a) 1 and 2 only (b) 1, 2, 3 and 4
IES-2012 (c) 3 only (d) 3 and 4 only
Ans. (c) (For full wave Rectifier) Ripple factor of the IES - 2010
inductor filter is given Ans. (c) :
2 1 (1) Bridge Rectifier are needed four diode but center
γ= × (RL )
3 2  1 + 4ω2 L2  tapped FWR only two diodes
  (2) Center tapped PIV is 2Vm but bridge it is only Vm.
 R2  We need PIV as small as possible.
(1) For maximum load current should be o For center tapped and bridge (FWR)
Put R L = 0, in equation (i) Ripple factor = 0.482%
γ=0 (ii) efficiency = 81.2%
(2) For minimum load current 83.
R L = ∞ open circuit
2
γ=
3 2
2
γ= = 0.4714
4.2426
81. For the circuit shown below, using ideal diode,
the values of voltage and current are The output Vdc from the above circuit is:
(a) 12 2 (b) 12/π
(c) 24/π (d) 12 / 2
IES - 2010
Ans. (a) :
(a) –3 V and 0.6 mA (b) 3 V and 0.0 mA

(c) 3 V and 0.6 mA (d) –3 V and 0.0 mA
IES-2011
Ans. (a) : As diode is forward biased then it will act
like a short circuit (S.C)
For Vi = VmSinωt
Vin = 12V ( Rms value )
Here Vo = Vm
Vm
Vrms =
+3V − ( −3V ) 2
I=
10k Vm = Vrms 2
=
( ) V = 6 = 0.6mA
3 + 3
= 12 2
10 × 103 10 × 103
V = −3V and I = 0.6 mA Vo = Vm = 12 2

84.
IES - 2010
Ans. (a) : For (+) half cycle D1 will behave as a open
Consider the above circuit, for Vi = Vm sin ωt, circuit and D2 will behave as a short circuit.
the output voltage V0 for RL → ∞ will be : +Ve half cycle
(a) Zero (b) Vm
(c) 2Vm (d) –Vm
IES - 2010
Ans. (c) :
6.6 || 2.2
Vo = Vi
2.2 + ( 6.6 || 2.2 )
6.6 × 2.2
= 6.6 + 2.2 Vi
6.6 × 2.2
Given circuit is voltage doubler. 2.2 +
6.6 + 2.2
Hence, V0 = 2 Vm
1.65
85. = Vi
2.2 + 1.65
= 0.4285 ×10
V0 = 4.3sin ωt
-Ve half cycle Q for (–) half cycle D2 will behave as a
open circuit while D1 will behave as a short circuit.
Now V0
The correct wave form for output (Vo) for the

above network is :
Vo =
( 6.6 || 2.2 ) V
2.2 + ( 6.6 || 2.2 )
i
= .4285 × 10
V0 = 4.3sin ωt
86. Which of the following does not show non-

linear V-I characteristics ?
(a) Schottky diode
(b) Tunnel diode
(c) Thermistor, at a fixed temperature
(d) p-n junction diode
IES-2009
Ans. (c) : Thermistor, At a fixed temperature → It is Positive half cycle-
shows linear V-I characteristics as it simply behaves as Capacitor C1 will charge to Vm
a resistor.
→ Schottky diode, tunnel diode, p-n junction diode are
shows non-linear V-I characteristics.
87. Which of the following components are chosen
to construct a d.c. power supply to supply 6 V
d.c. voltage from 230 V a.c. to operate a tape
recorder ? Negative half cycle-
Capacitor C2 will be charge upto Vm
1. Step down transformer
2. Diodes
3. Resistors and capacitors
4. Three-pin voltage stabilizer
Select the correct answer using the code given
below :
(a) 1, 2 and 3 only (b) 1 and 4 only
(c) 3 and 4 only (d) 1, 2, 3 and 4 Vo = VC1 + VC2 = Vm + Vm = 2Vm
IES - 2008 89. The figure given below shows the transfer
Ans. (d) : characteristics of which one of the following
(1) Step-down Transformer

A step-down transformer is type of transformer that
convert high voltage and low current from the primary
(a) Peak clipper (b) Bottom clipper
side of the transformer to the low voltage and high
(c) Clamper (d) Two level clipper
current on the secondary side.
IES - 2008
(2) Rectifier – A Rectifier is an Electrical device that
converts alternating current (A.C), to rippled D.C. Ans. (a) :
(3) Voltage Stabilizer –Three pin voltage stabilizer
used to convert pulsating d.c. voltage into constant d.c.
voltage to the load.
88. The figure shown is a circuit of which one of
the following ?
Supper position of the wave form is clipped.

if Vin > Vi
Vo = Vf
• So the circuit is a peak clipper.
(a) Bridge rectifier (b) Voltage doubler • Clipper circuit can remove certain portions of an
(c) Rectifier with filter (d) Comparator arbitary wave form near the positive or negative peaks.
IES - 2008 90. Silicon diodes are less suited for low voltage
Ans. (b) : rectifier operation because.
(a) it cannot withstand high temperatures
(b) its reverse saturation current is low
(c) its cut-in voltage is high
(d) its breakdown voltage is high
IES - 2009
Ans. (c) : For Ge = 0.3V cut- in voltage
Si = 0.7 V cut-in voltage

93. A half-wave rectifier having a resistance load
of 1kΩ rectifies an a.c. voltage of 325 V peak
value and the diode has a forward resistance of
100Ω. What is the RMS value of the current ?
(a) 295.4 mA (b) 94.0 mA
(c) 147.7 mA (d) 208.0 mA
IES - 2005
Ans. (c) :
Since cut-in voltage of Ge is low as compare to Si,
while silicon is high cut-in voltage. So it is not suitable
for low voltage Rectifier.
91. In the given circuit, D1 is an ideal germanium
diode and D2 is a silicon diode having its cut-in
voltage as 0.7 V, forward resistance as 20Ω and Given,
reverse saturation current (Is) as 10 nA. What R = 1000Ω
L
are the values of I and V for this circuit,
respectively ? ( Vin )P = 325V, R d = 100Ω
For half wave rectifier Vo
( Vin )max ( Vin )p  325 
( Vo )rms = =  V = 162.5V
2 2  2 
( Vo )rms 162.5 162.5
( Io )rms = = = = 147.7mA
Rd + RL 100 + 1000 1100
94. Select the correct output (Vo) wave shape for a
(a) 60 mA and 0 V (b) 50 mA and 0 V given input (Vi) in the clamping network given
(c) 53 mA and 0.7 V (d) 44 mA and 1.58 V below :
IES - 2006
Ans. (a) :
D1 is Ideal germanium diode.

Hence Vf = 0 when D1 is ON (FB)
Hence voltage across D2 is 0V
And V2 can not be ON, because (as it requires 0.7 V to
be ON)
IES - 2005
Ans. (d) : Positive half cycle-
6 6 ×1000 Vi = +10V, diode is F.B
V = 0, I= = = 60mA
100 100 × 1000 Therefore, Vo = 2V
92. In a half-wave rectifier, if an a.c. supply is 60
Hz, then what is the a.c. ripple at output ?
(a) 30 Hz (b) 60 Hz
(c) 120 Hz (d) 15 Hz
IES - 2005
Ans. (b) : (1) Half wave Rectifier input frequency fin is Here resistance became open because current always
60 Hz, then output frequency fo = 60 Hz. follow shortest path
Then full wave Rectifier frequency Fo = 2 fin Apply KVL in output loop-
• Half wave rectifier ripple factor = 1.21
V0 = 2V
• Full wave rectifier ripple factor = 0.482
Negative half cycle- 10 × Vi
Vo =
Vi = −10V 10 + 10
Diode is Reverse bias. Apply KVL at the given 10 × Vi
Vo =
20
Vi
Vo =
2
96. For a full-wave rectifier with shunt capacitor
filter, the peak to peak ripple voltage is
–Vi + VC + Vo = 0 (where f = fundamental power line frequency,
IDC = DC current)
− ( −10 ) + 8 + Vo = 0 (a) 2IDC/f C (b) IDC/f C
Vo = −18V (c) IDC/2f C (d) IDC/4f C
IES - 2003
Ans. (c) : For full wave Rectifier: Capacitor charge
and discharge once half cycle of the time period.
Total charge Transfer
∴ Ripple voltage =
Capacitor
 I ( T 2) 
=  DC 
95. Consider the following circuit  C 
I DC ⋅ T 1
= ∴ T=
2C f
Put value
I DC
Vr =
2fC
For the circuit shown above, which one of the
following is a correct statement ? 97. The average value of the full-wave rectified
(a) D2 does not conduct for any value of Vi. sine wave with period π, and a peak value of
(b) Vo = 10 V for all values of Vi > 10 V. Vm is
(a) 0.707 Vm (b) 0.500 Vm
(c) Vo = 0 V for all values of Vi < 0 V
(c) 0.637 Vm (d) 0.318 Vm
(d) Vo = 10 V for all values of Vi > 0 V
IES - 2003
IES - 2004
Ans. (c) : Full wave Rectifier sine wave
Ans. (c) : Case (I)
2Vm 2 × Vm
When Vin < 0 Average value = =
π 3.14
= 0.637 Vm
→ Ripple factor full wave Rectifier = 0.482
→ Efficiency of full wave rectifier = 81.2% .
98. Consider the following statements :
The function of bleeder resistance in filter
circuit is to
Case (II) 1. maintain minimum current necessary for
When 0 < Vin < 10 optimum inductor filter operation.
2. work as voltage divider in order to provide
variable output from the supply.
3. provide discharge to capacitors so that
output becomes zero when the circuit has
been de-energized
Which of these statements are correct ?
(a) 1 and 2 (b) 2 and 3 Ans. (c) Full wave rectifier circuit with capacitor filter:
(c) 1 and 3 (d) 1, 2 and 3
Nagaland PSC (Degree) 2018, Paper-II
IES - 2001, 1995
Ans. (d) : Bleeder resistor : Bleeder resistor is
connected in parallel with the output of a high voltage
power supply circuit for purpose of discharging the
electric charge stored in power supply’s filter capacitors
when the equipment is turned off, for safety regions. the shunt capacitor filter used with half-wave rectifier
It provides safety to operator by providing discharge prolongs the time period during which the current
path to the capacitor. passes through the load resistance and the ripple is very
much reduced. This situation is further improved
towards the reduction of ripple level Vr when the shunt
capacitor filter is used with a full wave rectifier circuit.
in a full wave rectifier some use a large value of
capacitor filer-
99. Consider the following rectifier circuits : • Low conduction period for the diode rectifier.
1. Half-wave rectifier without filter • Increased peak current rating of the diode.
2. Full-wave rectifier without filter
3. Full-wave rectifier with series inductance 102. The input voltage of Zener regulator varies
filter from 20 V to 30 V. The load current varies
4. Full-wave rectifier with capacitance filter. from 10 mA to 15 mA. If the Zener voltage is 5
The sequence of these rectifier circuits in V, the value of series resistor will be
decreasing order of their ripple factor is (a) 1 kΩ (b) 1.5 kΩ
(a) 1, 2, 3, 4 (b) 3, 4, 1, 2 (c) 1.66 kΩ (d) 2.5 kΩ
(c) 1, 4, 3, 2 (d) 3, 2, 1, 4 IES - 2000
IES - 2001
Ans. (a) :
Ans. (a) : Ripple factor in HWR is greater than in
FWR. Full wave Rectifier does not clip negative cycle
again series inductance or parallel capacitance are used
as filter.
For full wave Rectifier = 0.48
For half wave Rectifier = 1.21 Given,
100. The use of rectifier filter in a capacitor circuit Vin( max ) = 30V I L( max ) = 15mA
gives satisfactory performance only when the
load Vin( min ) = 20V, IL( min ) = 10mA
(a) current is high (b) current is low
I = I Z( min ) + I L( max )
(c) voltage is high (d) voltage is low
IES - 2001 = 0 + 15
Ans. (b) : The use of rectifier filter in a capacitor circuit = 15mA
gives satisfactory performance only when the load
Vin ( min ) − VZ
current is low. Series Resistance Rs =
The minimum ripple factor capacitor filter is used for I
high load resistance so load current will be low. 20 − 5 15
101. Consider the following statements in relation to = = = 1kΩ
15 15mA
a large value of capacitor filter used in a full-
wave rectifier : 103. In order to rectify sinusoidal signals of mili volt
It gives the : range (< 0.6 V).
1. low conduction period for the diode rectifier (a) Bridge rectifier using diodes can be employed
2. increased peak current rating of the diode (b) Full - wave diode rectifier can be used
3. large peak inverse voltage rating of the (c) A diode is to be inserted in the feedback loop
diode.
of an OP-AMP
Which of these statements are correct ?
(a) 1, 2 and 3 (b) 2 and 3 (d) A diode is to be inserted in the input of an
(c) 1 and 2 (d) 1 and 3 OP-AMP
IES - 2000 IES - 1998
Ans. (c) D3 will not conduct because this diode is Reverse bias
only D2 diode conduct
eo = 5V
The input voltage exceeds 0V, there is a small 105. For an input of Vs = 5 sin ωt, (assuming ideal
difference between the inverting input (which is diode), circuit shown in the figure will behave
as a
grounded) and the non inverting input. The Op-Amp
very high gain causes the output to saturate at the
positive cycle for this purpose, diode is used in
feedback of op-amp.
This configuration is also known as super diode.
104. In the circuit shown in the figure, if e1 = 2 V,
e2 = 5V, e3 = 1 V and E = 2V, then which one of
the diodes will be conducting and what will be
(a) clipper, sine wave clipped at – 2 V
the e0 ?
(b) clamper, sine wave clamped at – 2 V
(c) clamper, sine wave clamped at zero volt
(d) clipper, sine wave clipped at 2 V
IES - 1997
Ans. (b) :
(a) D3;1V (b) D1;2V

(c) D2;5V (d) D1;5V
IES - 1998 Positive half cycle-
Ans. (c) :
= − VS + VC − 2V = 0
VC = VS + 2V
= 5V + 2V
= 7V
Negative half cycle-
Let us assume, one of the diode are conducting then

Vo = 2V
Q current flow only when there exist a potential Vo = VS − VC
difference. V0 = 5sin ωt –7
∴ D1 does not conduct Clamper, sine wave clamped at –2V

106. If the input ac is 10V (rms), the maximum I = I
Z( max ) I L( min )
voltage that will appear across the diode of a
half-wave rectifier with a capacitor input filter V − VZ 32 − 24
I = in =
will be R R
(a) 10 V (b) 14 V
8
(c) 20 V (d) 28 V I =   ……………………………..(i)
IES - 1997 R
Ans. (b) : Q PZ( max ) = VZ( max ) ⋅ I Z( max )
600mW = VZ(max ) ⋅ I Z(max )
600mW 600 × 10−3

I Z( max ) = =
VZ( max ) 24
I Z(max) = 25mA ……………………(ii)
Case(I) I = I Z(max ) + I L( min )
Negative half cycle
8
= 25mA + 0
R
8 8 × 103
R= = = ⋅32 × 103 Ω
as we know that 25mA 25
PIV of half wave rectifier is Vm = 320Ω
Again
PIV = Vm
I = I Z(min ) + I L(max )
Vm
Vrms = I L(max ) = I − I Z( min )
2
Given, Vrms = 10V = 25 − 10
Vm = 10 2V I L( max ) = 15mA
= 10 ×1.414 108. Consider the following statements :
= 14.14V A clamper circuit
107. A 24 V, 600mW Zener diode is to be used for 1. adds or subtracts a dc voltage to or from a
providing a 24 V stablized supply to a variable waveform.
load. Assume that for proper Zener action, a
2. does not change the shape of the waveform.
minimum of 10 mA must flow. What is the
value of series resistance and maximum value 3. amplifies the waveform.
of load current ? Which of the statements give above are
correct?
Of these statements
(a) 1 & 2 are correct (b) 1 & 3 are correct
(c) 2 & 3 are correct (d) 1, 2 & 3 are correct
Mizoram PSC Jr. Grade-2015, Paper-II
(a) 300 Ω, 10 mA (b) 400 Ω, 15 mA IES - 1996
(c) 400 Ω, 10 mA (d) 320 Ω, 15 mA Ans. (a) : Clamper is a circuit, it is made with the help
IES - 1996 of resistor, a diode, and a capacitor, which is shift the
Ans. (d) : input signal into difference D.C level, that means the
clamper circuit adds the positive or negative dc value in
the input signal, it cannot amplify the wave form.
Given – 109. The piecewise linear V-I characteristic of a

Input voltage = 32 V diode is shown in the given figure. When the
Zener voltage = 24 V supplied voltage is 6V, the current through the
I → total current diode will be

(a) 42 mA (b) 48 mA
(c) 51 mA (d) 54 mA
IES - 1996
Ans. (d) : IES - 1995
Ans. (d) :
When Vin > 5V then

Slope of V.I characteristics,
diode is forward biased
I −I 34mA − 14mA 20mA
M= 2 1 = =
V2 − V1 ( 4 − 2) 2V
= 10mA / volt
given, supply voltage = 6V
I − I 2 = m ( V − V2 )
I = M ( V − V2 ) + I 2
10mA
= ( 6V − 4V ) + 34mA
volt
10mA
= × 2V + 34mA
volt Vo = 5V
I = 54mA
When Vin < 5V then, diode is Reverse biased
110. For the circuit given in figure below, assuming
ideal diode, the output waveform V0 is
Vo = Vin = Vo = 10V
111. In an L-Section filter, a bleeder resistance
connected across the load
(a) provides good regulation for all values of
load.
(b) ensures lower PIV of the diodes.
(c) ensures lower values of Capacitance in the
filters.
(d) reduces ripple content.
IES - 1994
Ans. (a) : (i) L-section filter : Choke filter consists of
an inductor in series with rectifier output circuit and
capacitor connected in parallel with load Resistor.
(ii) The input is fed through the inductor, so it is also
known as the choke input filter.

Bleeder Resistor :- A bleeder resistor is a resistor
connected in parallel with the output of a high-voltage
power supply circuit.
Hence a bleeder resistor provides good regulation for all
value of load and improves voltage regulation.
112. Consider the following statements regarding
the circuit given in the figure, where the output
voltage is constant;
1. Vin > the Voltage at which the Zener breaks
down.
2. IL < the difference between I and Iz the
current at which the Zener breaks down. V0 + 0.01R 2
(a) Greater than
3. Rs < the Zener normal resistance. ( Vin − V0 ) R 2
(b) Greater than
( Vin − V0 ) R 2
V0 + 0.01R 2
(c) Less than

( Vin − V0 ) R 2
V0 + 0.01R 2
Of these statements V + 0.01R 2
(d) Less than 0
(a) 1, 2 and 3 are correct (b) 1 and 2 are correct ( Vin − V0 ) R 2
(c) 2 and 3 are correct (d) 1 and 3 are correct IES - 1993
IES - 1994 Ans. (c) :
Ans. (b) :
Given, I z = 10mA
Q Vin > then zener voltage at which the zener break
down, I ≥ I z + I L .............(i)
Vin > V0 Vo
KCL apply At node A. IL =
R2
I = IZ + IL
IL = I − IZ Vin − Vo  V 
OR ≥ 10mA + o 
R1  R 2 
Rs and zener normal resistance have no relation.
113. The ideal characteristic of a stabilizer is V − Vo V
OR in ≥ 10×10 –3 + o
(a) Constant output voltage with low internal R1 R2
resistance.
Vin − Vo V
(b) Constant output current with low internal ≥ 0.01 + o
resistance. R 1 R 2
(c) Constant output voltage with high internal

resistance. R1 ≤
( Vin − Vo ) R 2
(d) Constant internal resistance with variable ( 0.01R 2 + Vo )
output voltage.
115. The wave shape of V0 in figure is
IES - 1994
Ans. (a) : Ideal characteristics of a stabilizer-
• Ideal, Rz = 0
• Voltage stabilizer is always connected in parallel with
load, so ideally its internal resistance must be zero.
• Lower the value of Rz gives better constant voltage.
114. The Zener diode in the circuit shown in figure-I
has the characteristics shown in figure-II. If R2
is the lowest load resistance to be used in the (a)
regulated supply, then to get load regulation,
R1 must be
Ans. (a) : Ebers-Moll Model:- It is an Ideal model for
(b) BJT that can used in forward or Reverse active Mode
operation, as well as in both saturation and cut-off mode
also. Analysis the two diode represent Base emitter and
base collector diode.
(c) ●The Ebers-Moll equation are based on two exponential
diode plus two current-controlled current source.
117. For small signal ac operation, a practical
(d) forward biased diode can be modeled as
(a) A resistance and a capacitance
GATE-1993 (b) An ideal diode and resistance in parallel
(c) A resistance and an ideal diode in series
Ans. (a) :
(d) A resistance
GATE-1998
Ans. (d) : For small signal ac operation, a practical
forward biased diode can be modeled as resistance
Case (I) positive half cycle

Diode DA is Forward bias, so D A is short circuit Diode
D B is Reverse bias so D B is conducting 118. For full wave rectification, a four diode bridge
rectifier is claimed to have the following
VO = 10 − 4.1 advantages over a two diode circuit.
= 5.9 V 1. Less expensive transformer
Vin > 4.1 2. Smaller size transformer and
3. Suitability for higher voltage application
of these
(a) only (1) and (2) are true
(b) only (1) and (3) are true
(c) only (2) and (3) are true
(d) (1), (2), as well as (3) are true
Case (II) Negative half cycle GATE-1998
Diode D B is forward bias so D B is short circuit. Ans. (d) : A four diode bridge rectifier uses the smaller
Diode D A is Reverse bias so D A is conducting state size of transformer, which is less expensive transformer
and these rectifiers are suitable for higher voltage
Vin > 4.1 applications, because of low PIV rating of each diode.
VO = −10 + 4.1 119. A dc power supply has a no-load voltage of 30
= −5.9 V V, and a full-load voltage of 25 V at a full-load
current of 1 A. Its output resistance and load
regulation, respectively, are
(a) 5 Ω and 20% (b) 25 Ω and 20%
(c) 5 Ω and 16.7% (d) 25 Ω and 16.7%
GATE-1999
Ans. (a) : Given, VNL = 30
Then total output voltage from DA and DB is VFL = 25 V
VNL − VFL
Voltage regulation = ×100
VFL
30 − 25 1
= × 100 = ×100 = 20%
25 5
116. The Ebers Moll model is applicable to V − VDCFL
(a) Bipolar junction transistors R D = DCNL
I DC
(b) NMOS transistors
(c) Unipolar junction transistors 30 − 25
=
(d) Junction field-effect 1
GATE-1995 = 5Ω
120. The transistor shunt regulator shown in the IC = 99 I Z
figure has a regulated output voltage of 10V, = 99 × 0.01
when the input varies from 20V to 30V. The
= .99A
relevant parameters for the zener diode and
PC = VC ⋅ IC
the transistor are: VZ = 9.5, VBE = 0.5 V, β = 99.
Neglect the current through RB. Then the = 10 × 0 ⋅ 99
maximum power dissipated in the zener diode PC = 9.9 watt
(PZ) and the transistor (PT) are
121. A.C. is converted into D.C. by
(a) Dynamo (b) Motor
(c) Transformer (d) Rectifier
Ans. (d) : The electric power available is usually an ac
supply. The supply voltage varies sinusoidal and has a
(a) PZ = 75 mW, PT = 7.9 W frequency. Frequency of 50Hz. It is used for lighting,
(b) PZ = 85 mW, PT = 8.9 W heating and electric motors when a dc supply is
(c) PZ = 95 mW, PT = 9.9 W required.
(d) PZ = 115 mW, PT = 11.9 W The mains ac supply is rectified by using semiconductor
GATE-2001 diodes. This is known as rectification.
Ans. (c) : (i) Half –wave rectifier
(ii) Full wave rectifier
122. The output voltage of the regulated power
z
supply shown in the figure is
Vin( max ) − Vo
I1max =
20
30 − 10
= = 1 Ampere
20
( i.e. when Iz = 0 )
(a) 3 V (b) 6 V
I E = IB + IC ............(1) (c) 9 V (d) 12 V
IB = I Z ( as no current flow ) GATE-2003
Ans. (c) :
IC = βI B
IC IC
β= =
IB I Z
From equation (i)
I E = βI Z + I Z
= I Z ( β + 1)
Zener diode voltage is 3V,
= I Z ( 99 + 1) Non inverting terminal voltage is 3V according to Zener
= 100I Z diode voltage at importing terminal will be 3V because
of virtual ground.
I E = I1 = 100 I z So, current in 20kΩ
I1 = 100 I Z 3 3
I= = mA
I1 20kΩ 20
IZ = RT = 40kΩ + 20 kΩ
100
= 60kΩ
PZ = VZ I Z 3
V0 = × 60kΩ
= 9.5 × .01 20kΩ
PZ = 95m watt V0 = 9V

123. In the voltage regulator shown in the figure, Given V = 5.8V
Z
the load current can vary from 100 mA to 500
I Z( min ) = 0.5mA
mA. Assuming that the Zener diode is ideal
(i.e., the Zener knee current is negligibly small 20 − 5.8
and Zener resistance is zero in the breakdown I = 1kΩ
region), the value of R is = 14.2mA
I = I Zmin + I L(max)
14.2 − 0.5mA = I L( max )
(a) 7 Ω (b) 70 Ω I L( max ) = 13.7mA

70 125. For the circuit below, assume that the zener
(c) Ω (d) 14 Ω
3 diode is ideal with a breakdown voltage of 6
GATE-2004 volts. The waveform observed across R is
Ans. (d) :
Given, zener voltage Vz = 5V

Load current I L = (100 to 500 ) mA (a)
Input voltage
Vin = 12V (b)
I = I Z + IL
= I Zmin + I Lmax
(c)
= 0 + 500mA
I = 500mA
V − Vz 12 − 5 (d)
R = in =
I 500mA
= 14Ω GATE-2006
Ans. (b) :
124. The Zener diode in the regulator circuit shown
in the figure has a Zener voltage of 5.8 volts
and a Zener knee current of 0.5 mA. The
maximum load current drawn from this circuit
ensuring proper functioning over the input
voltage range between 20 and 30 volts, is
Given, VR = 12sin ωt
Zener voltage VZ = 6V
Zener diode work as normal diode in forward bias
When Vin < 0, VR = Vin
For positive half cycle diode in reveres bias so it will be
(a) 23.7 mA (b) 14.2 mA
in conduction ⇒ VR = Vin − Vz
(c) 13.7 mA (d) 24.2 mA
GATE-2005 VR = 12 − 6 = 6V
Ans. (c) : For Negative half cycle diode in forward bias so it will
be worked like normal diode
( VR = −Vin )
VR = −12V
z
I = I Z + IL

126. The correct full wave rectifier circuit is Ans. (c) :
(a)
(b)
I z knee = 0
Zener resistance rz = 10Ω
Vz = 7 Volts
(c)
Vin − Vz Vin − 7
I= =
R s + rz 210
Vo = Vz + I ( rz )
Vin − 7
Vo = × 10 +7
210
(d) V −7
Vo = in +7………(i)
21
When Vin = 10V
GATE-2007
10 − 7 3
Ans. (c) : In positive half cycle- Vo min = + 7 = + 7 = 7.14 Volts
D2 , D4 are ON 21 21
D1, D3 are OFF When Vin = 16V
And Vout = Vin 16 − 7 9
Vo max = + 7 = + 7 = 7.42 Volts
In negative half cycle- 21 21
D2 , D4 – OFF Range of Vo = 7.14 to 7.42 Volts
D1, D3 – ON 128. In the following limiter circuit, an input voltage
Vout = –Vin Vi = 10 sin 100 πt is applied. Assume that the
diode drop is 0.7 V when it is forward biased.
The zener breakdown voltage is 6.8 V
127. For the Zener diode shown in the figure, the

Zener voltage at knees is 7V, the knee current The maximum and minimum values of the
is negligible and the Zener dynamic resistance output voltage respectively are
is 10Ω. If the input voltage (Vi) range is from (a) 6.1 V, –0.7 V (b) 0.7 V, –7.5 V
10 to 16V, the output voltage (V0) ranges from (c) 7.5 V, –0.7 V (d) 7.5 V, –7.5 V
GATE-2008
Ans. (c) :
(a) 7.00 to 7.29 V (b) 7.14 to 7.29 V

(c) 7.14 to 7.43 V (d) 7.29 to 7.43 V
GATE-2019, 2007
Given, Vi = 10sin100πt 130. The diodes and capacitors in the circuit shown
are ideal. The voltage v(t) across the diode D1 is
Zener breakdown voltage = 6.8V
(1) For positive half cycle Vi
Zener diode is break down state and D1 is forward
Biased and D2 is Reverse bias
Vo = 0.7 + 6.8
= 7.5V
(2) Negative half cycle of Vi,
D2 is forward, D1 is reverse biased so we got the total (a) cos(ωt) – 1 (b) sin (ωt)
output voltage (c) 1–cos (ωt) (d) 1–sin (ωt)
Vo = −0.7 volt GATE-2012
Ans. (a) :
129. In the circuit below, the diode is ideal. The
voltage V is given by
When supply is +Ve half cycle then capacitor C1 is

charged in maximum Vm voltage =1V and Diode D2 is
open circuit. When – Ve half cycle then diode D1 is
(a) min (Vi' 1) open circuit and replace the output voltage Vt.
(b) max (Vi' 1)
(c) min (–Vi' 1)
(d) max (–Vi' 1)
GATE-2009
Ans. (d) :
(i) Let Vi = +Ve − cos ωt + 1 + Vt = 0
Diode reverse bias, then
Vt = cos ( ωt ) − 1
Q V = 1×1 = 1Volt
131. A voltage 1000 sin ωt volts is applied across YZ.
Assuming ideal diodes, the voltage measured
across WX in volts, is
When Vi = Negative
(ii) Diode will be forward bias, diode short circuit
Using KVL,
–Vi –V– Vd = 0
–Vi = V (Vd = 0)
(a) sin ωt
(b) (sin ωt + |sin ωt|)/2
(c) (sin ωt – |sin ωt|)/2
(d) 0 for all t
GATE-2013
Ans. (d) :

Case-I ABCDEF apply kvl
During the positive half cycle, then all diode is OFF −10V + 1000I + 20I + 0.3V = 0
1020 I= 10 − 0.3
Hence
9.7
I= = 0.0095
1020
= 9.5mA
ABEFA
Apply KVL
−10V + 1000 × 9.5mA + VD1 = 0
−10V + 9.5V + VD1 = 0
VD1 = 10 − 9.5
VD1 = 0.54V
V1 = V2 We got VD1 value is 0.5V, but we need more voltage
than 0.7V to turn on the D1 so that’s why D1 is off and
V = 0 Volt D2 is ON.
Case-II 133. The diode in the circuit shown has Von = 0.7 V
Negative half cycle; diode is short circuit but is ideal otherwise. If Vi = 5 sin( ωt) volts, the
minimum and maximum values of V0 (in volts)
are, respectively,
V = 0 Volt
132. In the figure, assume that the forward voltage

drops of the PN diode D1 and Schottky diode
D2 are 0.7 V and 0.3 V, respectively. If ON
denotes conducting state of the diode and OFF
denotes non-conducting state of the diode, then (a) –5 and 2.7 (b) 2.7 and 5
in the circuit, (c) –5 and 3.85 (d) 1.3 and 5
GATE-2014, Set-II
Ans. (c) :
(a) Both D1 and D2 are ON

(b) D1 is ON and D2 is OFF
(c) Both D1 and D2 are OFF
(d) D1 is OFF and D2 is ON
GATE-2014, Set-I
If Vin = −5V ⇒ diode is OFF
Ans. (d) :
Vin = −5V = Vo
When Vin = 5V then, diode is ON
Vo =
( Vi − 0.7 − 2 ) ×1K + 0.7 + 2
Assume D1 = OFF, D 2 = ON
(1 + 1) ×103
=
( 5 − 2.7 ) ×1×103 + 2.7
2 ×103
= 1.15 + 2.7 = 3.85 V
134. Two silicon diodes, with a forward voltage drop
of 0.7 V, are used in the circuit shown in the
figure. The range of input voltage Vi for which
the output voltage V0 = Vi' is

Ans. (c) :
(a) –0.3 V < Vi < 1.3 V (b) –0.3 V < Vi < 2V

(c) –1.0 V < Vi < 2.0 V (d) –1.7 V < Vi < 2.7 V
GATE-2014, Set-IV
Ans. (d) :
Case (I)
Positive half cycle, both diode are forward biased and
Negative half cycle both diode are Reverse biase.
(1)
Case (I)
Vi <-1.7V, D1 is ON, D 2 is OFF
(2)
V0 = 0V
Case (II)
−1.7 < Vi < 2.7
Diode D1 and D 2 both are OFF
136. If the circuit shown has to function as a
clamping circuit, then which one of the
following conditions should be satisfied for the
sinusoidal signal of period T?
Vi = Vo
135. For the circuit with ideal diodes shown in the
figure, the shape of the output (Vout) for the (a) RC << T (b) RC = 0.35 T
given sine wave input (Vin) will be
(c) RC ≈ T (d) RC >> T
GATE-2015, Set-II
Ans. (d) :
(a) (b)
Where R is resistance, C is capacitance, T is time period
of the input signal.
(c) (d) The voltage at the capacitor during discharge is given as
t
−
GATE-2015, Set-I VC ( t ) = Vo e RCdis

Suppose at t = T 2 138. The circuit shown in the figure is used to
T 2 provide regulated voltage (5V) across the 1 kΩ
−
VC ( t ) = Vo = Vo e RC
............(1) resistor. Assume that the zener diode has a
constant reverse breakdown voltage for a
and at t = T at the voltage will be
current range, starting from a minimum
−T
VC ( t ) = 0.99Vo =Vo e ⋅ RC ..........(2) required Zener current, IZmin = 2 mA to its
maximum allowable current. The input voltage
Q From equation (2), we get V1 may vary by 5% from its nominal value of 6
−T
V. The resistance of the diode in the
0.99 = e RC
breakdown region is negligible.
T
−0.01 = −
RC
RC = 100T
This implies that
RC >> T
The value of R and the minimum required
137. The I-V characteristics of the zener diodes D1 power dissipation rating of the diode,
and D2 are shown in figure I. These diodes are respectively, are
used in the circuit given in figure II. If the (a) 186 Ω and 10 mW (b) 100 Ω and 40 mW
supply voltage is varied from 0 to 100 V, then
breakdown occurs in (c) 100 Ω and 10 mW (d) 186 W and 40 mW
GATE-2018
Ans. (b) :
(a) D1 only (b) D2 only Given

(c) Both D1 and D2 (d) None of D1 and D2 Zener voltage VZ = 5V
GATE-2016, Set-III
load resistance R L = 1kΩ
Ans. (a) :
R =?
Vi = 6V ± 5%
= 6V ± .3V
= ( 5.7 to 6.3) V
5
IL = = 5mA
1kΩ
Is( min ) = IL + I Z( min )
Breakdown voltage of D1 = 80V
Breakdown voltage of D2 = 70V = 5mA + 2mA
When Vin exceed 80V then D1 is in breakdown region = 7mA
the circuit become VI( min ) − VZ
Is( min ) =
R
VI( min ) − VZ ( 5.7 − 5 ) V 0.7V
R= = =
Is( min ) 7mA 7mA
700
So, R = = 100Ω
7
∴ Vin max = 100V, then VD2 = (100 − 80 ) V
When R = 100Ω
VD2 = 20V 6.3 − 5
Is( max ) = A = 13mA
= 20 < Vbreakdown 100
∴ So only D1 enters into Breakdown region. Is( max ) = I z( max ) + I L

So I z( max ) = Is( max ) − I L 141. Calculate the maximum current that can be
passed through a 1N755 Zener Diode at a
= 13mA − 5mA
temperature of 50°C. For 1N755 Zener Diode,
= 8mA VZ = 7.5V and PD = 400 mW at 50°C.
Pz( min ) = Vz I z( max ) (a) 53.33mA (b) 63.33mA
= ( 5 × 8 ) m watt (c) 73.33mA (d) 93.33mA
= 40mW APPSC POLY. LECT. 14.03.2020
139. As with other two terminal devices, diodes can Ans. (a) : VZ = 7.5 V
be placed in series (or in parallel). Determine Power of Zener = 400 mW
which one of the following configurations can Maximum power (P) = V Imax
conduct current from A → C ? 400 mW
I max =
7.5V
Imax = 53.33 mA
142. The equivalent DC output voltage of a full-
wave rectifier is ______ the equivalent DC
output voltage of a half-wave rectifier.
(a) equal to (b) not related to
(c) half of (d) double
RPSC VP/Suptd. ITI 05.11.2019 APPSC POLY. LECT. 14.03.2020
Ans. (a) : As with other two terminal devices, diode can Ans. (d) : DC output voltage-
be placed in series
V
For half wave rectifier VDC = m
π
In this type of configurations diode can conduct current 2Vm
from A → C. For full wave rectifier VDC =
π
140. The circuit shown in figure is a Hence dc output voltage of full wave rectifier is double
(a) positive peak clipper (b) positive clamper of half wave rectifier dc output voltage.
(c) differentiator (d) negative clamper
143. When a capacitor is connected across the
output terminals of a full-wave rectifier, the
output voltage :
(a) nearly becomes a DC voltage.
(b) becomes sinusoidal.
(c) exhibits sharp spikes.
TSPSC Manager (Engg.) - 2015 (d) is shifted up and down.
Ans. (b) : APPSC POLY. LECT. 14.03.2020
Ans. (a) : Rectifier convert AC voltage into DC
voltage. When a capacitor is connected across the
output of a full wave rectifier, the output voltage nearly
becomes a DC voltage.
144. Diodes are used to clip voltages in circuits
because they act as :
Let Vi = ± Vm (a) current sources under certain bias conditions.
(i) If Vi is − Vm : (b) voltage sources under certain bias conditions.
Diode is in F.B. (c) inductors that can remove spikes.
C charges upto −Vm (d) dependent current sources.
(ii) If Vi is + Vm APPSC POLY. LECT. 14.03.2020
Diode is in R.B Ans. (b) : Diodes are used to clip voltages in circuits
Capacitor can discharge through R because they act as : Voltage sources under Certain bias
conditions.
Vi V0 max 145. A half-wave rectifier made with a single diode
and a load resistor converts an AC voltage into :
+ Vm 0V
(a) a constant DC voltage.
−Vm 2Vm (b) a sinusoidal voltage that has a DC offset.
(c) a waveform that has only the positive or
negative half-cycle of the input sinusoidal.
(d) Another AC voltage that is phase shifted by
180° (c) (d)
Ans. (c) : A half wave rectifier made with a single
diode and a load resistor converts an AC voltage into a APPSC Poly. Lect. 15.03.2020
waveform that has only the positive or negative half Ans. (b) : Diode Transfer the voltage below the
cycle of the input sinusoidal. (reference level) (–V)
146. Circuits that are used to eliminate portions of a
signal that are above or below a specified level
are called:
(a) Clampers (b) Clippers
(c) Voltage doublers (d) Detectors
UPSC Poly.Lect.10.03. 2019
Ans. (b) : The circuit that are used to eliminate the
portion of a signal that are above or below a specific
level are called limiter or clipper circuit.
147.
149. Without a dc source, a clipper acts like a
(a) Clamper (b) Chopper
(c) Rectifier (d) Demodulator
LMRC AM (S&T)-13.05.2018
For the series diode configuration of above Ans. (c) : In a clipper circuit, If the dc source is set to
figure, employing the diode characteristics zero voltage, then the circuit acts as a rectifier.
shown below :
ID (mA)
20
18
16
14
12 • Basic clipping devices is the half-wave rectifier
10
8
6
4
2
0.5 0.8 VD (V)
The value of VR is :
(a) ≈ 9.2V (b) ≈ 0.7V
(c) ≈ 2.5V (d) ≈ 12V
APPSC Poly. Lect. 15.03.2020 150. The tunneling process in a Tunnel diode is due
to
Ans. (a) : From graph :- VD = 0.8V
(a) Physical behavior (By possession of large
VR = E − VD = 10 − 0.8 = 9.2V energy)
(b) Quantum-mechanical behaviour
(c) The presence of smaller amounts of impurity
148. atoms
(d) Subjecting to very large voltage (in forward
and reverse biases)
The output of the given circuit, assuming ideal TNPSC AE- 2019
diode, is :
Ans. (b) : Tunneling is an effect that is caused by
quantum mechanical effect when electrons pass through
(a) (b) a potential barrier. The tunneling only occurs under
certain conditions. It occurs within tunnel diodes
because of the very high doping levels employed.

151. The capacitance of a Varactor diode can be Vm I
changed by I= So, IDC = m
(a) Increasing its doping level R F + R L π
(b) Changing its forward bias Vm
(c) Changing its barrier potential I DC =
π(R F + R L )
(d) Changing the reverse voltage
TNPSC AE- 2019 155. The diode in circuit has cut in voltage V cut in
Ans. (d) : The capacitance of varactor diode can be is 0V. Choose the option for the waveform of
changed by changing the reverse voltage. Varactor output voltage Vo
diode is known as varicap or voltcap or voltage variable
capacitance. It always works in reverse bias condition.
152. The current of a certain Si-diode, when
measured with a large reverse bias is found to
be 10nA. What would be the current be if a
forward bias of 2V is applied ? Assume that
T=3000K, η = 2.
(a) 6.2×108A (b) 6.2×10-8A (a)
(c) 0.62×10 A8
(d) 0.62×10-8A
TNPSC AE- 2019
Ans. (a) :
 VD 
I = I0  e ηVT − 1 (b)
 
 
 VD  T
I = I0  e ηVT  Q VT =
  11600
  (c)
 2
 300
I = 10 × 10−9  e 2× 0.02586
 VT =
  11600
(d)
I = 6.2 ×108 A VT = 0.02586
153. The biggest disadvantage of the IMPATT diode
is its
(a) high noise
(b) lower efficiency (e)
(c) inability to provide pulsed operation
(d) low power-handling capability
TNPSC AE- 2019 CGPSC SO 14.02.2016
Ans. (a) : It has high noise figure due to avalanche
Ans. (e) :
process and higher operation current. The shot noise is
generated in the device due to high operation current. +ve Half cycle
Typically noise figure of IMPATT diode is about 30dB.
154. A half-wave rectifier uses a diode with a
forward resistance Rf. The voltage is
Vm sinωt and the load resistance is RL. The d.c.
current is given by
Vm V –20 + 2.2I + 5 = 0
(a) (b) m
2R L RL 2.2I = 15
2Vm Vm 15
(c) (d) I=
π π(R f + R L ) 2.2
BPSC Polytechnic Lecturer-2014 Vo = IR + 5
I 15
Ans. (d) : For a half wave rectifier the IDC = Iavg = m Vo = × 2.2 + 5
π 2.2
V sin ωt Vo = 20V
I= m = I m sin ωt
( F L)
R + R –Ve Half cycle

Diode is reverse bias For negative half cycle
Vin Diode Vout
0 − 16V ON 4V
So Vo = 5V
157.
156. Which of the five waveforms of Vout predicts
the correct output of circuit for Vin as shown
below:
Vin (Volts)
For the above given waveform as input Vi to

the given circuit of a clipper. Maximum and
minimum values of output V0 will be
(a) +16V and +4V (b) +16 and -4V
(c) +4V and -16V (d) +16V and -12V
Vout (Volts) UPPSC ITI Principal/Asstt. Director-09.01.2022
Vout (Volts)
Ans. (a) :
Vi = +16 V0 = 16 diode off

Vout (Volts) Vout (Volts)
V0 max = 16 V
Vi = –16 then diode on V0 = +4V
V0min = 4V
158. The zener diode breakdown voltage is 2.5V.
Find voltage across 2kΩ
Vout (Volts)
(e)
(a) 2.14V (b) 2.2V
(c) 2.5V (d) 3V
CGPSC SO 14.02.2016 BARC Scientific Officer-2016
Ans. (e) : For positive half cycle Ans. (a) : If we calculate voltage across 3 kΩ .
10
Vin Diode Vout V3kΩ = 3k × = 3V
10k
0 − 4V ON 4V
So it is greater than VZ in this situation Zener diode
4V − 16V OFF 16V will be behave like battery.

V0 = −5V
At the graph screen we will get this type of wave shape.

160. Which of the Current (i) – Voltage (v) graphs
10 − 2.5 15 represents a p-n junction diode characteristics?
I= = mA
7 14
15 (a) (b)
V2kΩ = 2k × mA
14
15
V2kΩ = V
7
V2kΩ = 2.14V (c) (d)
159. Find V0 if Vi = 5sin 200πt

Ans. (c) : PN junction diode V-I characteristics
(a) 161. Assume that D1 and D2 in figure are ideal

diodes. The value of current-l is
(b)
(a) 0.58 mA (b) 0.5 mA

(c) 0. mA (d) 0.633 mA
(c) RRB SSE 01.09.2015 Shit-I
Ans. (c) : D1 and D2 are ideal diodes so in this
condition D1 in forward bias and behaviour short
circuited. On the other hand D2 will in reverse bias and
(d) None behave as a open circuited. Circuit so in this situation
TNPSC AE- 2019 current flow from D2 will 0mA. We can redraw circuit
BARC Scientific Officer-2016 like this.
Ans. (a) :
Q When Vin > 2 than diode forward bias and output

voltage V0 = +2V
–Ve half cycle diode is open circuit and output voltage
V0= –Vin

162. A __________ is an electronic circuit that 2I1+I2 = 2……….. (ii)
changes the DC level of a signal to the desired By solving (ii) & (iii)
level without changing the shape of the applied
signal.
(a) Rectifier (b) Clamper
(c) Slicer (d) Limiter
RRB JE- 31.08.2019, 10 AM-12 PM −4
I2 =
Ans. (b) : A clamper is an electronic circuit that uses a 3
signal without changing the shape of the signal applied put the value I in equation (ii)
2
to the DC level changes to desired level. There are two
type of clamper- 2I 1 + ( −4 / 3 ) = 2
(i) Positive clamper 4 10
(ii) Negative clamper 2I1 = 2 + =
3 3
10 5
I1 = =
6 3
5 4 1
I= − =
3 3 3
1
V0 = −2 × = −0.671
3
165. The zener diode shown in the circuit has a
reverse breakdown voltage of 10 volts. The
power dissipation in Rs would be
163. Gun diode is made of-
(a) Gallium Arsenide (b) Germanium
(c) Silicon (d) Selenium
RRB JE- 31.08.2019, 10 AM-12 PM
Ans. (a) : Gun diode are fabricated from a single piece
of n-type semiconductor, the most common material are
gallium Arsenide, (GaAs) and Indium Phosphide, (InP).
However other materials including Ge, CdTe, InAs, In
Sb and others have been used.
164. For the circuit shown in the figure below, the
voltage V0 is (here D is an ideal diode) (a) 4W (b) 2W
(c) 3.5W (d) 1W
Zener voltage =10 volts
(a) –1V (b) 1V I L = 50mA
(c) 2V (d) None of the above R S = 100Ω
VS = 30V
Ans. (d) :
VS − VZ
Source current IS =
RS
30 − 10
=
100
20
Let diode in ON- IS =
100
I1+I2 =I Power dissipation in Rs
4 = 2I1 + 2I 2+2I2+2I = 0
P = IS 2 × R S
I 2 + I = −1
20 20
I1 + I = 2 …………….. (i) I2+I1+I2 = –1 = × ×100
100 100
I1 + I1 + I 2 = 2 I1+2I2 = –1 ………..(iii) P = 4W

166. Assuming that diode in the given circuit is (c) The instantaneous current depends only on
ideal, the voltage V0 is the diode
(d) The energy stored in the capacitor can never
decreases with time
BSNL (JTO)-2001
Ans. (d) : A peak detector comprises a capacitor and an
ideal diode and an ac source in series then the energy
stored in the capacitor can never decreases with time
(a) 2V (b) 3V because the capacitor gets charged to the most positive
(c) 3.5 V (d) 1 V value of the input.
RRB SSE 02.09.2015, Shift-I 169. A diode D1, under certain biasing conditions,
Ans. (a) : Positive half circuit diode is reverse bias then has a forward voltage drop VDi = 0.7 V and IDi
output voltage. = 5.6 mA. Under the same external conditions,
another diode D2 whose doping levels NA and
ND are both twice that of D1 has the same
forward voltage VD2 = .7 V. Assuming the same
ideality factor for both the diodes ID2 is :
(a) 1.4 mA (b) 2.8 mA
(c) 5.6 mA (d) 11.2 mA
2 DRDO-2009
V0 = × 4 = 2.64V Ans. (b) : We know that,
2 +1
When diode is forward bias then if is behaves as a short Reverse saturation current-
circuit.  Dp Dn  2
I0 = Aq  +  n i
L N
 p D Ln N A 
Diode current
 V 
I D = I0  e ηVT − 1
 
The voltage forward biase-  
Output voltage- Q Ideality factor is same for both diode.
1 I
V0 = × 4 = 2V So, I D2 = D1 because the doping NA and ND in diode
1+1 2
D2 are twice as that in diode D1.
167. What is the voltage across the 1Ω register?
I 5.6
So, I D2 = D1 = = 2.8mA
2 2
170. The correct match between the following two
columns is :
(A) Tunnel diode 1. Microwave ampli-
fication
(B) Zener diode 2. Voltage regulation
(a) 4.7 V (b) 4.3 V (C) PIN diode 3. Photo detection
(c) 4 V (d) 5 V (D) Schottky diode 4. High speed switch-
RRB SSE 02.09.2015, Shift-II ing
Ans. (a) : Given- A B C D
V = 5, R = 1Ω, Ge = 0.3 (a) 1 4 2 1
(b) 1 3 2 4
5 − 0.3
I= = 4.7 (c) 4 2 1 3
1 (d) 1 2 3 4
I= 4.7 Amp DRDO-2009
V = IR = 4.7 ×1 Ans. (d) :
V = 4.7 Volt (A) Tunnel diode → Microwave amplification
168. A peak detector comprises a capacitor and an (B) Zener diode → Voltage regulation
ideal diode and an ac source in series. (C) PIN diode → Photo detection
The following is true of the circuit. (D) Schottky diode → High speed switching
(a) The instantaneous current depends only on 171. The I-V characteristics of devices can be
the instantaneous source voltage divided into quadrants as shown in figure
(b) The diode voltage is always zero below.
0.4 0.8
(a) mA (b) mA
π π
0.4 0.8
(c) mA (d) mA
2 2
BSNL(JTO)-2009
Ans. (a) :
Photodiodes and solar cells are normally
operated in quadrants :
(a) Q3 and Q4, respectively
(b) Q1 and Q1, respectively
(c) Q1 and Q3, respectively
(d) Q2 and Q3, respectively
DRDO-2009
Ans. (a) : Photodiodes and solar cells are normally
operated in quadrants Q3 and Q4, respectively.
172. The cut-in voltage Vγ and thermal voltage VT
for the diode D in figure shown below are 0.498
V and 2 mV, respectively. Im
Iavg =
π
0.4
= mA
π
174. Assume D1 and D2 to be ideal diodes
If the value of resistor R is 20 Ω, the current

flowing through the diode is :
(a) 275 mA (b) 250 mA
(c) 200 mA (d) less than 200 mA
DRDO-2009
Ans. (b) :
Which one of the following statements is true?

Given Vr = 0.498 (a) Both D1 and D2 are ON
R = 20Ω (b) Both D1 and D2 are OFF
Here VT has no use then, (c) D1 is ON and D2 is OFF
(d) D2 is ON and D1 is OFF
5.5 − Vr
I= DRDO-2008
R
Ans. (d) : As D2 anode has more potential, it will ON
5.5 − 0.498
I= first and D1 the become OFF.
20
I = 250.1mA 175. If cut-in voltage and forward resistance of each
diode (in the adjoining figure are 0.7 V and
I  250 mA
1ohm respectively, the current through the 48
173. In the circuit shown in figure, assume the ohm resistor is
diodes are ideal and the ammeter is an average
indicating meter with zero internal resistance.
The ammeter reading is
(a) 132 mA (b) 160 mA

(c) 0 mA (d) (1/6) A
BSNL (JTO)-2006
Ans. (a) : In this circuit only two diodes ON rest two
diodes OFF.

–Vi + Vc +V0 = 0
– 10 + (–25)+V0 = 0
V0 = 35V
Hence, V0 = +35V, + 5V
So, current through 48Ω resistance
8 − 0.7 − 0.7 177. What is the value of current I through the ideal
I= diode in the circuit?
1 + 48 + 1
8 − 1.4
I=
50
6.6
I= = 0.132
50
I = 132 mA
176. Find VO for the given circuit. (Assume ideal (a) 100 mA (b) 150 mA
diode) (c) 200 mA (d) 250 mA
IES-2016
Ans. (c) : Note → (i) Higher positive potential and
negative potential will decided the behaviour of diode.
In given circuit ideal diode will be forward bias/short
circuit/ON state.
Now circuit becomes-
(a) +35 V, 0 V (b) +35 V, +5 V

(c) 0 V, –5 V (d) –35 V, –5 V
Ans. (b) : Condition -I
10
If Vi = –20V, then I=
50
Diode is forward biased and circuit is short circuited.
= 0.2 A
Apply KVL in the circuit = 200 mA.
–Vi + VC +V = 0
178. What is the output voltage V0 for the circuit
– (–20) +VC + 5 = 0 shown below assuming an ideal diode?
VC = –25V
then –Vi + VC +V0 = 0
–(–20) + (–25) +V0 =0
V0 = 25 –20
V0 = 5V
18 18
(a) − V (b) V
5 5
13 13
Condition - II (c) − V (d) V
5 5
If Vi = 10V then diode is reverse biased and
circuit is open circuited. IES-2016
Ans. (a) : Note → (i) Higher positive potential and
negative potential will decide the behaviour of diode.
In the given circuit diode behaviour will decide 5V
potential (due to Negative sign)
Then diode will be forward bias/ON state/ short circuit.
Apply KVL in the circuit, Now circuit becomes–

Apply Nodal analysis. (a) VR = –5 (b) VR=+5
V0 + 5 − 1 V0 + 3 (c) 0 ≤ VR < 5 (d) –5 <VR< 0
+ =0
2kΩ 3kΩ GATE-2006
V0 + 4 −V0 − 3 Ans. (a) : at t < 0
=
2kΩ 3kΩ
3V0 +12 = –2V0 – 6
5V0 = –18
at 0 < t < ts
−18
V0 = V
5
179.
When switch is instantaneously position 1 to 2 then

diode is instantaneously switched from a conduction
state it needs some time to return a non-conduction state
at this time reverse current starts flow through the
diode. so behaviour of diode is short circuit for a small
time is reverse direction.
apply KVL at (0 < t < ts)
The light Emitting diode (LED), shown in the
above figure has a voltage drop of 2 V. The –VR – 5 = 0
current flowing through LED is VR = −5V
(a) 11.8 mA (b) 0.0147 mA
181. The i-v characteristics of the diode in the
(c) 2.941 mA (d) 0.0176 mA circuit given below are
IES-2013  v - 0.7 
 A V ≥ 0.7V 
Ans. (a) : i =  500 
 0 A V < 0.7V 
The current in the circuit is

Apply KVL- (a) 10 mA (b) 9.3 mA
−10 + 680I + 2 = 0 (c) 6.67 mA (d) 6.2 mA
680I – 8 = 0 OPSC Poly. Lect. (Instrumentation)-2018, Paper I
8 GATE-2012
I=
680 Ans. (d) : Apply kirchhoff's voltage law-
= 0.01176 –10+1000I +V = 0
V = 10 – 1000I .......(i)
I = 11.74 mA  11.8mA
there is 10V is greater then 0.7V
180. In the circuit shown below, the switch was
then diode current will be-
connected to position 1 at t < 0 and at t = 0, it is
changed to position 2. Assume that the diode V − 0.7
I= .....(ii)
has zero voltage drop and a storage time ts. For 500
0 < t ≤ t s .VR s given by (all in Volts) put value equation (ii) in equation (i)

( V − 0.7 ) 184. In half wave rectifier, if Vi to the diode is 20
V = 10 − 1000 × sin ( ωt), Vdc is
500
(a) 6.37 V (b) 10 V
V = 10 –2 (V– 0.7)
(c) 14.2 V (d) 20 V
V= 10 – 2V + 1.4
3V = 11.4
Ans. (a) : For half wave rectifier-
11.4 V 20
V= V = 3.8V Vdc = Vo(avg ) = m =
3 π 3.14
3.8 − 0.7 = 6.37 Volt
I=
500 185. Which rectifier requires four diodes?
3.1 (a) full-wave bridge circuit
= (b) half-wave voltage doubler
500
(c) voltage quadrupler
I = 6.2mA (d) full-wave voltage doubler
182. In the following limiter circuit, an input voltage Mizoram PSC IOLM -2018, Paper II
V1 = 10 sin 100 πt applied. Assume that the RRB SSE 01.09.2015, Shift-II
diode drop is 0.7 V when it is forward biased. Ans. (a) : Full wave bridge rectifier requires four diode
The Zener breakdown voltage is 6.8 V. as shown in fig.
The maximum and minimum values of the output

voltage respectively are
(a) 6.1 V1 – 0.7 V (b) 7.5 V1 – 0.7 V
(c) 7.5 V1 – 0.7 V (d) 7.5 V1 – 7.5 V
NIELIT Scientists- 2017 186. An AC supply of 230 V is applied to a half-
Ans. (c) : during +ve part of Vi wave rectifier circuit through a transformer
D1 will be forward biased zener will be reverse biased. having primary to secondary turn's ratio 12:1.
Net voltage = 6.8 + 0.7 = 7.5 V The peak inverse voltage is
during –Ve Half cycle. (a) 8.62 V (b) 12 V
D1 will reverse D2 will be forward (c) 19.17 V (d) 27.11 V
biased thus net voltage = 0.7 V RPSC LECTURER-10.01.2016
183. Which is the correct waveform across capacitor Ans. (d) :
in the following circuit?
N 2 V2
(a) =
N1 V1
(b) 1 V
= 2
12 230
(c) V2 = 19.1667
∴ Vm = 19.1667 × 2
(d)
In half wave rectifier PIV = Vm= 27.11V
ISRO Scientist Engg.-2013 187. If the PIV rating of a diode is exceeded,………
Ans. (d) : This diagram show the full wave rectifier (a) the diode conducts poorly
with capacitor filter. For positive half cycle capacitor (b) the diode is destroyed
charged to the peak value and negative half cycle it (c) the diode behaves like a zener diode
discharged but not zero and charged again. (d) none of the above
From the given option correct option is (d) Nagaland PSC CTSE (Diploma)-2017, Paper-I

Ans. (b) : Peak inverse voltage rating of a diode may be 192. Transformer utilization factor of half wave
defined as the maximum value of the reverse voltage rectifier is
that a P-N-junction can withstand without damaging. (a) 0.287 (b) 0.693
When the voltage applied to a diode is more than PIV, it (c) 0.812 (d) 0.48
is likely to result in breakdown at the junction and the TNPSC AE- 2019
diode gets destroyed. Ans. (a)
188. The r.m.s. value of half wave rectified current Type of rectifier Half Centre Bridge
is 50A. Its r.m.s. value for full wave wave tapped full
rectification would be wave
(a) 100A (b) (50/π)A Ripple factor 1.21 0.482 0.482
(c) (100/π)A (d) 70.7A Transformer 0.287 0.693 0.812
utilization factor
Ripple f 2f 2f
I frequency
Ans. (d) : For half wave rectifier I rms = m
2 193. The disadvantage of half wave rectifier circuit
Irms = 50 A is that
Im = 100 Amp (a) Diode must have high PIV rating
I m 100 (b) Diode must have high power rating
For full wave rectifier I rms = = = 70.7 A (c) Output voltage is difficult to filter
2 2
(d) Diode must have high current rating
189. Ripple factor of an ideal rectifier is
(a) Zero (b) Unity
Ans. (c) : An half wave rectifier has more ripple in
(c) Infinity (d) None of these output. Hence it is difficult to filter these ripple in
Mizoram PSC Jr. Grade-2015, Paper-II output.
Ans. (a) : In ideal rectifier has constant dc voltage, 194. Precision diode can be used as
hence there is no ripple in output voltage. So ripple (a) Half wave rectifier (b) Full wave rectifier
factor will be zero. (c) Clipper and clamper (d) all of the above
190. If one of the diode in a full wave bridge Nagaland PSC (Degree) 2018, Paper-II
rectifier opens, the output is Nagaland PSC CTSE (Degree)-2017, Paper-II
(a) 0 V Ans. (d) : Half wave rectifier is a diode circuit which is
(b) One-fourth the amplitude of the input voltage used to transform alternating voltage (ac supply) to
(c) A half wave rectifier voltage direct voltage (dc supply). Half wave rectifier circuit
(d) 120 V allows the one half cycle of the ac supply wave form to
pass and blocks the other half cycle.
Full wave rectifier is defined as a type of rectifier that
Ans. (c) : If one of the diodes is a full wave bridge converts both halves of each cycle of an alternating
rectifier opens, the output is a half wave rectified wave (ac signal) into a pulsating dc signal. Full wave
voltage. rectifiers are used to convert ac voltage to dc voltage
requiring multiple diodes to construct. Clipper and
clamper circuits are electronic circuits used for the
modification of ac signals. The clipper circuit can clip a
portion of the ac waveform while the clamper shifts the
191. The dc voltage of a Half-wave rectifier is dc level of the ac signal.
I R I R 195. The main advantage of a bridge rectifier over
(a) Vdc = dc L (b) Vdc = m L full wave rectifier with centre tapped
π π transformer is
I R I R (a) less ripple
(c) Vdc = m L (d) Vdc = dc L (b) No transformer is needed
2π 2π
(c) peak inverse voltage of each diode is half
TNPSC AE- 2019 (d) PIV of each diode is double
Ans. (b) : Half –wave rectifier RRB SSE 21.12.2014, (Yellow)
VLm I m R L Ans. (c) : The main advantage of a bridge rectifier over
VL(dc) = = = 0.318VLm
π π full wave rectifier with centre tapped transformer is the
PIV is one-half that of the centre. Tap (for same I/P,
IL O/P) and the output is twice that of the centre tap circuit
I L = m = 0.5 I Lm
2 for the same secondary voltage.

Ans. (b) : CB CE and CC configuration
(ii) BJT Amplifiers voltage gain and current gain
Voltage gain Current gain
1. The configuration of cascode amplifier is CB High Less than unity
(a) CE – CC (b) CE – CB CE Medium high
(c) CC – CB (d) CC – CC CC low High
UPPSC ITI Principal/Asstt. Director-09.01.2022 5. The voltage gain of amplifier stage is lowest in
TNPSC AE - 2018 (a) CB
Nagaland PSC (Degree 2018, Paper-II) (b) CE
GPSC Asstt. Prof. 11.04.2017 (c) CC
RPSC Vice Principal ITI-2016 (d) Same in all configurations
UPRVUNL AE-19.07.2021, Shift-II
DRDO-2008
GATE-2005, 1997 UPPCL AE-05.11.2019
Ans. (b) : TNPSC AE-2019
The configuration of cascode amplifier = CE –CB Nagaland PSC- 2018, Diploma Paper-II
The configuration of cascade amplifier = CE – CC Nagaland PSC- 2018, Diploma Paper-I
The configuration of Darlington pair = CC – CC IES-2007, 2006, GATE-2003
• The cascode connection is used to obtain large Ans. (c) :
output Impedance. Characteristic CB CE CC
• Darlington connection used to obtain high current Input impedance Low Medium High
gain.
output impedance High Medium Low
• The Voltage gain of Amplifier can be increased by
using cascading connection of individual stages. Voltage gain High Medium Low
2. The addition of the emitter resistor to the dc Current gain Low Medium High
bias of the BJT ____stability of the circuit. Phase shift 0º 180º 0º
(a) Degrades (b) Does not affect 6. Common collector transistor configuration in
(c) Improves (d) Destabilize used for
UPPSC ITI Principal/Asstt. Director-09.01.2022 (a) voltage amplification
Ans. (c) : The addition of the emitter resistor to the dc (b) current amplification
bias of the BJT improves stability of the circuit. (c) impedance matching
3. In CE configuration of transistor, the output (d) rectification
"Volt-amp." characteristics is plotted as
UPPCL AE-16.11.2013
(a) VCB Vs IC for constant values of IE Mizoram PSC AE/SDO 2012-Paper-I
(b) VCC Vs IC for constant values of IB
Ans. (c) : Used for the purpose of impedance
(c) VCE Vs IC for constant values of IB matching.
(d) VCB Vs IC for constant values of IB
Parameter Common Common Common
UPPSC ITI Principal/Asstt. Director-09.01.2022 base emitter collector
Ans. (c) : CE configuration at transistor 1 output Current I I I
gain α dc = C βdc = C γ= E
IE IB IB
Voltage high medium <1
gain
7. In order to operate a CE amplifier in
saturation region, which of the following
conditions should be satisfied?
(a) The emitter resistor must be connected
(b) IB > IC(sat)/ β(DC)
(c) IB = IC(sat)
(d) Vcc must be at least 10 V
VCE v/s IC for constant value of IB TNPSC AE- 2019
4. Among CB, CE and CC configurations of the Ans. (b) : Condition to operate CE amplifier in
amplifiers, which is having low voltage gain saturation region
and high current gain?
(a) All of the above (b) Only CC IC( sat )
(c) CB and CC (d) Only CE IB >
β ( DC )
8. An ideal value of input resistance of trans 14. For a single stage CE amplifier, if Ai = –49.32,
resistance amplifier is. R1 = 1093 ohms, RC = 1k Ω and RL = 1.2 kΩ ,
(a) infinity (b) zero then the voltage gain is .
(c) low (d) high
Ans. (b) : Input resistance of transresistance amplifier
should be zero & the output resistance of transresistance
amplifier should be infinite.
9. What is the typical range of the output
impedance of a common-emitter configuration?
(a) 40 KΩ to 50 KΩ (b) 1 KΩ to 5 KΩ
(c) 500 KΩ to 1 KΩ (d) 10 Ω to 100Ω
UPRVUNL AE -19.07.2021, Shift-II (a) – 24.61 (b) – 20
Ans. (a) : Output impedance of CE configuration, (c) 20 (d) 24.6
ZO = RC Range (40 KΩ to 50 KΩ)
Ans. (a) : Voltage gain,
10. If α DC = 0.99, I C = 6mA and I CBO = 15µA, what
A R'
is the value of IB ? Av = i L R'L = R L R C
(a) 45 µA (b) 60 µA Ri
(c) 50 µA (d) 55 µA 6
−49.32 × × 103
11 1.2kΩ ×1kΩ
Ans. (a) : α dc = 0.99, IC = 6mA and ICBO = 15µA = R 'L =
1093 1.2kΩ + 1kΩ
I C = α dc I E + ICBO 6
= A v = −24.61 R 'L = kΩ
⇒ I C = 0.99 ( I B + I C ) + 0.015 11
⇒ 6 = 0.99 ( I B + 6 ) + 0.015 15. Stability factor S of a self bias circuit depends
on
⇒ 6 − 0.015 = 0.99 ( I B + 6 )
(a) β alone (b) β, Rb and Re
⇒ I B + 6 = 6.045 (c) β, Rb and Rc (d) Rb and Rc
⇒ I B = 6.045 − 6 = 0.045 mA APPSC Poly. Lect.14.03.2020
Nagaland PSC CTSE (Diploma)-2017, Paper-II
⇒ I B = 45 µA
IES-2016
11. An amplifier using transistor has a voltage gain Mizoram PSC AE/SDO 2012-Paper-I
of 100. If the input voltage is 65 mV, the output Ans. (b) : The stability factor should be as low as
voltage is: possible so that collector current does not get affected.
(a) 6.5 V (b) 1.33 V
β +1
(c) 13.3 V (d) 4.15 V S=
UPRVUNL AE -19.07.2021, Shift-II  ∂I 
1− β B 
Ans. (a) : Av = 100, Vi = 65 mV, V0 = ?  ∂IC 
Av = 0
V 1+ β
The stability factor of self bias is s =
Vi  RE 
1+ β 
⇒ V0 = 100×65×10–3 = 6.5 V
 R th + R E 
12. For an amplifier, which parameter is In self bias, stability factor is depend to R , R , β
E th
calculated with VS = 0?
(a) A1 (b) R0 According to above definition option ‘(b)’ is correct.
(c) Ri (d) AV IB and IC depends on RB and RE so S depends on β, RB
UPRVUNL AE -19.07.2021, Shift-II and RE .
Ans. (b) : To find output Resistance of an amplifier, 16. Which of the following holds FALSE for BJTs?
source voltage should be short circuited or VS = 0. (a) The quantity beta (β ) provides an important
13. What is the collector current for a CE relationship between the base and collector
configuration with a β of 100 and a base currents, and is usually between 50 and 400.
current of 30 µA? (b) The impedance between terminals of a
(a) 4.330 mA (b) 3 mA forward-biased junction is always relatively
(c) 6 µA (d) 330 µA large, whereas the impedance between
UPRVUNL AE -19.07.2021, Shift-II terminals of a reverse-biased junction is
Ans. (b) : IC = βIB usually quite small.
= 100×30µA (c) The dc beta is defined by a simple ratio of dc
IC = 3mA currents at an operating point.
(d) The quantity alpha (α) relates the collector 20. Introducing a resistor in the emitter of a
and emitter currents and is always close to common emitter amplifier stabilizes the dc
one. operating point against variation in
APPSC Poly. Lect. 15.03.2020 (a) only the temperature
Ans. (b) : In forward Bias → Rf (Small) (Ω) (b) only the β of the transistor
(c) both temperature and β
Reverse Bias → Ro (Very large) (MΩ) (d) none of the above
17. Current amplification factor for a common Nagaland PSC (Degree) 2018, Paper-II
base connection is 0.5. What is the value of base UPSC JWM-2016, BPSC Poly. Lect-2014
current if emitter current 1 mA?: GATE-2000
(a) 0.5 mA (b) 0 mA Ans. (c) : DC operating point or quiescent point or Q
(c) 0.1 mA (d) 1 mA point depend on the following parameter-
APPSC Poly. Lect. 15.03.2020 1. ICBO or ICO
Ans. (a) : Given as- 2. Temperature
Current amplification factor, α = 0.5 3. Current gain factor ( β )
Emitter current IE = 1 mA As temperature increases, the values of ICE, β , VBE gets
IC affected
0.5 =
IE T ↑ ICBO↑ ICEO ↑ IC↑ T ↑
0.5 × 1 = IC • I CBO gets doubled for every 10ºC rise.
• VBE decrease by 2.5mV every 1ºC rise.
IC = 0.5 mA
21. A transistor works in three regions:
I B = I E − IC 1. Cut-off 2. Active
= 1 − 0.5 = 0.5mA 3. Saturation
18. For a transistor amplifier to be inherently While used as switch in digital logic gates, the
stable against thermal runaway, the condition regions it works in are:
is (a) 1 and 2 only (b) 2 and 3 only
(a) VCE < (VCC/2) (b) VCE > (VCC/2) (c) 1 and 3 only (d) 1, 2 and 3
(c) VCE = (VCC/2) (d) none of these Mizoram PSC Jr. Grade-2015, Paper-I
RPSC VP/Suptd. ITI 05.11.2019 ISRO Scientist May-2017, IES-2010
Mizoram PSC Jr. Grade -2018, Paper-II Ans. (c) : In digital circuit, transistor works on two
Nagaland PSC CTSE (Degree)-2017, Paper-II levels
IES-2000 1- high logic
Ans. (a) : Thermal runaway takes place when 0- low logic
1 These high and low logic obtained by switching the
VCE > Vcc . So to eliminate thermal runaway we transistor ON and OFF mode.
2
Transistor work in OFF mode in cut-off region, and
1 ∂P ∂P
should have VCE < VCC and C < D work is ON mode in saturation mode.
2 ∂TJ ∂TS Saturation - ON mode
19. A transistor is operating in the active region. Cut-off - OFF mode
Under this condition In saturation region both EB and CB is forward biasing,
(a) both the junction are forward-biased. in cut-off region both EB and CB is reverse bias.
(b) both the junction are reversed biased. 22. In a common emitter amplifier, the unbypassed
(c) Emitter-base junction is forward biased and emitter resistor provides
collector-base junction is reversed biased. (a) voltage-shunt feedback
(d) None of these (b) current-series feedback
Nagaland PSC CTSE (Diploma)-2018, Paper-I (c) negative-voltage feedback
Mizoram PSC IOLM-2018, Paper-I (d) positive-current feedback
GPSC Asstt. Prof. 11.04.2017 TNPSC AE-2018
Mizoram PSC Jr. Grade-2015, Paper-I GPSC Asst. Prof.- 11/04/2017, TNPSC AE-2008
IES-2016, 2015, 2009 Ans. (c) : In an common emitter amplifier, the un-
Mizoram PSC AE/SDO 2012-Paper-I bypassed emitter resistor provides the negative voltage
Ans. (c) feedback. It decrease the gain to a desired value.
Mode Emitter base Collector-base 23. The emitter follower configuration is an
junction junction example of
Cut-off Reverse bias Reverse bias (a) Voltage-series feedback
Active Forward bias Reverse bias (b) Current series feedback
(c) Current shunt feedback
Saturation Forward bias Forward bias
(d) Voltage shunt feedback
Reverse active Reverse bias Forward bias Nagaland PSC CTSE (Diploma)-2018, Paper-I
ISRO Scientist Engg.2018 IP
RPSC LECTURER-10.01.2016 I rms =
Ans. (a) : It has voltage series negative feedback. Its 2
voltage gain is less than 1 and current gain is high, due I P = 2 I rms
to its high input impedance and low output impedance,
its impedance matching. Common collector is also 12.5
IP = 2 × = 2.4899
known as emitter follower. 4
24. If α = 0.98, I CO = 6 µA and I B = 100µA for a IP = 2.50 A
transistor, then the value of IC will be 2
Idc = I P
(a) 2.3 mA (b) 3.1 mA π
(c) 4.6 mA (d) 5.2 mA Pdc = VCC Idc
2
Ans.(d): Given value, α = 0.98 = 15 × × 2.5
ICO = 6µA π
P
I B = 100µA, ICO = ICBO η = ac ×100
Pdc
Q IC = βI B + (1 + β ) ICBO
12.5
α 0.98 = × 100
β= = = 49 2
15 × × 2.5
1 − α 1 − 0.98 π
(Where, IC = collector current, ICBO = leakage current) η = 52.36%
IC = 49 × 100 × 10 −6 + 50 × 6 × 10−6 η 52%
= 4.9 × 10 −3 + 300 × 10 −6 26. In the circuit given below, assume that
VCC = 15V; Z1, Z2, Z3 & Z4 are identical Zener
IC = 4.9 ×10 −3 + 0.3 × 10 −3
diodes with breakdown voltage of 5V; R1 = R4
IC = 5.2 × 10 −3 = 5kΩ, R2=R3=10kΩ
IC = 5.2 mA Find V0 when Q1 is OFF.
25. It is required to design a class B output stage
(as shown below) to deliver an average output
power of 12.5W to a load of 4Ω. The power
supply is selected so that VCC is 5V greater than
the peak output voltage. Determine the power
conversion efficiency of the circuit.
(a) 7.5 V (b) 5V

(c) 10V (d) 8.33V
(a) 48% (b) 50% Ans. (c) : Given,
(c) 52% (d) 54% VCC = 15V
ISRO Scientist Engg.-2010 Z1, Z2, Z3, Z4 are identical zener diodes
Q1 is off (∴ IC = 0)
Ans. (c) : V rms = P × R = 12.5 × 4 = 50
2
Apply KCL at collection node-
Vrms = 50V
V0 − 15 V − 5 V0 − 5
VP = 2 × 50 = 10V +0+ 0 + =0
5kΩ 10kΩ 10kΩ
 VL  2V − 30 + V0 − 5 + V0 − 5
Q Vrms =  = 0
 2 10kΩ
VCC = 5 + VP = 5 + 10 = 15V ⇒ 4V0 = 40
12.5 12.5 V0 = 10V
I 2 rms = = 27. The base resistor method is generally used in
R 4
(a) Amplifier circuits (b) Switching circuits
12.5
I rms = (c) Rectifier circuits (d) None of the above
4 Nagaland PSC (CTSE) Diploma-2017, Paper II

Ans. (b) : The base resistor method is generally used in (a) 20 (b) 30
switching circuit. Base bias is not suitable for high (c) 40 (d) 50
emitter current. Nagaland PSC (CTSE) Diploma-2017, Paper II
28. In a particular biasing circuit, the value of RE Ans. (c) :
is about……….
(a) 10 kΩ (b) 1 MΩ
(c) 100 kΩ (d) 800 Ω
Ans. (d) : In a particular biasing circuit, the value of RE
is about to few hundred ohms. Alone option (d) 800Ω is
correct option.
29. In voltage divider bias, operating point is 3 V, 2
mA. If VCC = 9 V, RC = 2.2 kΩ, what is the
value of RE? β=∞
(a) 2000 Ω (b) 1400 Ω IC = IE
(c) 800 Ω (d) 1600 Ω VE = 500 × 1× 10−3
VE = 0.5V
Ans. (c) : For voltage divider circuit-
VCE = VCC − IC (RC + RE) VB = 0.7 + 0.5
3 = 9 −2mA (RC+RE) VB = 1.2V
6 For Thevenin theorem
= RC + RE R2
2 3× = 1.2
3 = 2.2kΩ + R E 60 + R 2
R E = 0.8kΩ R 2 = 40KΩ
R E = 800Ω 33. In the circuit, current gain of the ideal
30. In a transistor amplifier circuit VCE = VCB +…. transistor, is 10. The operating point of the
(a) VBE (b) 2 VBE transistor (VCC, IC) is
(c) 5 VBE (d) None of the above
Ans. (a) : VCE = VCB + VBE
VCE = VC −VB + VB−VE
VCE = VC − VE
31. What is the main factor governing the
maximum power rating (PTOT) of a (a) 40 V, 4 A (b) 40 V, 5 A
transistor?
(c) 0 V, 4 A (d) 15 V, 4 A
(a) The maximum collector voltage.
TNPSC AE - 2018
(b) The temperature of the base/emitter junction
(c) The maximum collector current Ans. (b) : IB = 0.5 A IC = β.IB
(d) The temperature of the base/collector junction IC = 10×0.5
Nagaland PSC (CTSE) Diploma-2017, Paper II IC = 5A
Ans. (d) : The maximum power rating of a transistor is
largely governed by the temperature of collector to base And VCC = 40V
junction.
32. In the circuit shown below, the silicon npn 34. In the circuit given, collector to ground voltage
transistor Q has a very high value of β. The is +20V. Which of the following is the probable
required value of R2 (in kΩ) to produce Ic = 1 error?
mA is
(a) Collector – Emitter terminals shorted

(b) Emitter to ground connection open
(c) Base resistor open
(d) Collector base terminal shorted
TNPSC AE - 2018
Ans. (b) : VB = 10 V, VCC = 20V 0.995 995
10 − 0.7 β= = = 199
IB = = 0.19 mA 1 − 0.995 5
47kΩ ICEO = (1 + β) ICBO
= (1 + 199) × 0.5 × 10–6
= 200 × 0.5 × 10–6
ICEO = 100 µA
38. Emitter bypass capacitors cause a
(a) High frequency pole in the transfer function
(b) A high pass response
(c) A low pass response
(d) A high frequency zero in the transfer function
Hence the probable error is to emitter ground GPSC Asstt. Prof. 11.04.2017
Ans. (b) : The major function of emitter by pass
connection open. because when emitter ground is open
than IE = 0 IC ∝ IE IC = 0 so, IB = 0 Capacitance is to increase gain.
Emitter bypass capacitors cause a high pass response.
35. The current gain and voltage gain of the 39. The common emitter short circuit gain β of a
Emitter follower circuit given in figure are transistor
(Assume that RS = 500 Ω, R1 = R2 = 50 KΩ, (a) Increases with collector current IC
RL = 2KΩ, hfe = 100 and hie = 1.1 KΩ) (b) Decreases with collector current IC
(c) Increase, become maximum and decrease
with increase of IC
(d) Is not a function of IC
GPSC Asstt. Prof. 11.04.2017
Ans. (c) : The common emitter short circuit Current
(a) 101, 0.1146 (b) 0.9946, 101 gain (β) of a transistor, increasing with IC. For low
(c) 101, 0.9916 (d) 0.9946, 105 value of IC, reaches a maximum value and then
TNPSC AE - 2018 decreases with further increase in IC.
Ans. (c) : Current gain = 1 + hfe 40. Reverse saturation current in the collector
= 1 + 100 region of a transistor
(a) Increases with temperature
β = 101 (b) Decreases with temperature
Now we know that for emitter follower circuit voltage (c) Is not affected by temperature
gain is about to unity. (d) Is affected by base current
Hence α = 0.9946 GPSC Asstt. Prof. 11.04.2017
Ans. (a) : An ideal diode equation-
36. Two transistors have the same value of α but
different gain bandwidth products. One of  ηqVKTD 
I = I S e − 1
them is a germanium transistor and the other is D  
a silicon transistor. Both the transistors have  
similar geometries and base width. The Where IS − reverse saturation current
transistor with lower GB product q − is the charge on the electron
(a) Is the germanium
VD − applied forward-bias voltage across diode
(b) Is the silicon
(c) Both are same η = Ideality factor
(d) Cannot be identified unless more information K = Boltzmann' constant
is available T = temperature in Kelvin
ISRO Scientist Engg.-2008 KT
Ans. (b) : Compare to germanium, silicon transistors = VT also known as thermal voltage
q
having less gain bandwidth product.
KT
37. If α = 0.995, IE = 10 mA and ICO = 0.5 µA, then at 300K= 25.9 26mV
ICEO will be q
(a) 100 µA (b) 10.1 mA  VD 
(c) 25µA (d) 10.5 mA Now, I D = IS  e ηVT − 1
 
ISRO Scientist Engg.-2008  
Ans. (a) : Given, Note- that the saturation current is not a constant for a
given device, it varies with temperature: this variance is
α = 0.995, IE = 10 mA, ICO = 0.5 µA the dominant term in temperature coefficient for a
α diode. A common rule of thumb is that it double for
β=
1− α every 10ºC rise in temperature.

41. For the lower Q-point operation of a diode ac 45. The emitter resistor RE is bypassed by a
resistance is capacitor in order to
(a) high (b) low (a) Stabilize the Q point
(c) very low (d) reduced (b) Cause thermal runaway
Mizoram PSC AE/SDO 2012-Paper-I (c) Increase the voltage gain
ηVt (d) Reduce the voltage gain
Ans. (a) : Dynamic resistance rd =
ID Mizoram PSC IOLM -2018, Paper II
from the given graph, for a lower Q-point operation, do Ans. (a) : The main function of the emitter resistor RE
will be lower. bypassed by a capacitor is to improve the stability of the
transistor.
46. The current ICBO flows in the
(a) Emitter and base leads
(b) Collector and base leads
(c) Emitter and collector leads
1 (d) None of these
rd ∝ , for lower Q-point, rd will be high. Mizoram PSC IOLM -2018, Paper I
ID
Ans. (b) : The ICBO is a collector to base reverse
42. For 1 volt emitter bias what is RE if saturation current. This current is amplified by I
CBO to
IE = 300mA
Produced additional collector current.
(a) 1Ω (b) 3.33Ω
(c) 6.667Ω (d) 33.3Ω 47. For what kind of amplifications can the active
region of the common-emitter configuration be
used?
Ans. (b) : VE = IE. RE
(a) Voltage (b) Current
VE (c) Power (d) All of these
RE =
IE Mizoram PSC IOLM -2018, Paper I
1 Ans. (d) : Voltage, current and power amplification can
RE = be used in active region of the common emitter.
300 mA
48. BJT is three terminal device which stands for
10
RE = bipolar junction transistor. Which of the
3 following are true about BJT.
R E = 3.33Ω 1. Base has smallest area to reduce the transit
time.
43. In a amplifier, variation in β causes 2. collector is provided with the largest area to
(a) Bias unstability (b) Bias stability withstand heat dissipation.
(c) Zero bias (d) None of these 3. BJT is a current controlled device.
Mizoram PSC IOLM -2018, Paper II 4. BJT is a voltage controlled device.
Ans. (b) : In fixed biased circuit, β is dependent there (a) 1, 2 and 3 (b) 1, 2 and 4
is any change in circuit parameter the value of β will be (c) only 1 and 2 (d) only 2 and 4
change, hence β will change due to change in bias UPPCL AE-16.11.2013
stability.
Ans. (a): A BJT is stands for Bipolar junction transistor
44. In a transistor circuit IB remains constant but it is a three terminal device. It's base has smallest area
β increases
to reduce the transit time and it is a CC device.
(a) Operating point will go down
49. A Silicon BJT has leakage current ICBO of 10
(b) Operating point will go up
nA at 30ºC. If the temperature rises to 60ºC,
(c) Operating point will not change it position calculate the leakage current-
(d) Operating point will shift as per value of base
(a) 80 nA (b) 40 nA
current IB
Mizoram PSC IOLM -2018, Paper II (c) 60 nA (d) 20 nA
UPPCL AE-16.11.2013
I B = constant Ans. (a) : For an increment of 10º, current will be
double. Hence.
β = increases
at 30º → current 10 nA
IC at 40º → current 20 nA
β= ↑ β ∝ IC ↑
IB at 50º → current 40 nA
So operating point will go up. at 60º → current 80 nA

50. Operating point 'Q' of the given circuit in Ans. (c) : In CE configuration its power gain is the
figure is- highest.
It is only configuration providing phase inversion.
It provides voltage and current gains more than unity.
52. What is the Q-point for a fixed-bias transistor
with IB = 75 µA; βDC = 100, VCC = 20 V, RC =
1.5 kΩ
(a) VC = 20.25 V (b) VC = 11.25 V
(c) VC = 8.75 V (d) VC = 2.75 V
UPSC JWM-2016
Ans. (c) : IB = 75 µA βDC = 100
VCC = 20 V RC = 1.5 kΩ
VC = VCC – β IB × RCC
= 20 − 100 × 75 × 10 −6 × 1.5 × 103
(a) (4.833V, 1.03 mA) (b) (6V, 1.03 mA)
(c) (5V, 2mA) (d) (4.833V, 1mA) = 20 − 11.25
UPPCL AE-16.11.2013 V C = 8.75 V
Ans. (a) : Apply KVL in base loop. 53. The voltage across load resistor of a capacitor
coupled CE amplifier is
(a) DC & AC (b) DC only
(c) AC only (d) Neither DC nor AC
Ans. (c) : For capacitor coupled CE amplifier the
output voltage is cascaded to the next step via capacitor
coupling with ensure DC biasing point should not be
effected for the next state site where as input is given in
–10 + 900 IB + 0.7 = 0 base terminal.
9.3 54. Under steady state, thermal runaway in a CE
IB = amplifier is avoided if
900 ×103
∂Pc 1 ∂Pc 1
I B = 0.01033 mA (a) = (b) <
∂Tc θ ∂Tc θ
9.3
IC = β.I B = 100 × ×10−3 ∂Pc 1 ∂Pc
900 (c) > (d) =θ
∂Tc θ ∂Tc
9.3
IC = mA = 1.033mA TNPSC AE-2014
9 IES-2001
IE = IB + IC = 1.03 + 0.0103 Ans. (b) : We know obtain the restrictions to be met if
IE = 1.043mA thermal runaway is to be avoided. The required
Apply kVL in collector loop condition is that the rate at which heat is released at
–10 +1.03 × 5 + VCE = 0 collector junction must not exceed the rate at which heat
can be dissipated;
VCE = 4.83V
∂Pc ∂PD
Q point (VCE, IC) = (4.83, 1.03 mA) < ( ∆T = θPD )
∂Tj ∂Tj
51. Consider the following statements about CE
configuration: ∂Pc 1
1. Its power gain is highest <
∂Tj θ
2. It is only configuration providing phase
inversion 55. In the transistor clipping circuit, the transistor
3. Its output resistance is very high is operated in its
4. It provides voltage and current gains more (a) Break down region
than unity (b) Either in cut-off or in saturation or in both
Which of the above statements are correct? regions
(a) 1, 2 and 3 only (b) 3 and 4 only (c) Along the load line
(c) 1, 2 and 4 only (d) 1, 2, 3 and 4 (d) Active region
UPSC JWM-2016 TNPSC AE-2014
Ans. (b) 60. If the base current of a BJT is 250 µA and
emitter is 15 mA, then the common base
current gain will be
(a) 0.98 (b) 0.41
(c) 59 (d) 55
RPSC LECTURER-10.01.2016
Ans. (a) : QI E = IB + IC
In the transistor clipping circuit, the transistor is 15×10-3 = 250 ×10-6 +IC
operated in its either in cut-off or in saturation or in IC = 15×10-3 - 250 × 10-6
both regions. IC= 5×10-3 (3 - 50×10-3)
56. While using a bipolar junction transistor as an 5 295
amplifier, the collector and emitter terminals IC = ×
got interchanged mistakenly. Assuming that 1000 100
the amplifier is a common emitter amplifier IC = 0.01475 A
and the biasing is suitably adjusted, the IC
interchange of terminals will results into which Common base current gain ( α ) =
one of the following? IE
(a) Infinite gain 0.01475
α=
(b) Zero gain 15 ×10−3
(c) No change in gain at all α = 0.98
(d) Reduced gain
TNPSC AE-2014 61. The signal handling capacity of an amplifier
Ans. (d) : While using a bipolar junction transistor as will be high when the operating point is
selected
an amplifier, the collector and emitter terminals get
interchanged mistakenly. Assuming that the amplifier is (a) Close to saturation region
a common emitter amplifier and the biasing is suitable (b) Close to cut-off region
adjusted, the interchange of terminals will result into (c) At the extremities of the active region
reduce gain. (d) In the middle of the active region
57. The Q point of a voltage divider bias circuit is Nagaland PSC CTSE (Degree)-2016, Paper-II
(a) sensitive to change in current gain Ans. (d) : The signal handling capacity of an amplifier
(b) totally insensitive to change in current gain will be high when 'Q-Point' lies in the middle of active
(c) insensitive to change in temperature region.
(d) insensitive to change in emitter resistor 62. For good stablised biasing of the transistor of
TNPSC AE-2013 the CE amplifier we should have
Ans. (b) : The Q-point of a voltage divider bias circuit (a) R e << 1 (b) R e << h FE
is totally insensitive to change in current gain. Q point Rb Rb
is the point on the output characteristic that shows the
Re Re
DC collector emitter voltage and collector current (Ic) (c) >> 1 (d) >> h FE
with no input signal applied. Rb Rb
58. Unique features of a CC amplifier circuit is Nagaland PSC CTSE (Degree)-2016, Paper-II
that it Ans. (c) : For good stabilized biasing of transistor of the
(a) steps up the impedance level R
(b) does not increase signal voltage CE amplifier we should have e >> 1
Rb
(c) acts as an impedance matching device
(d) all the above 63. In a transistor if β = 100 and collector current
TNPSC AE-2013 is 10 mA, then IE is…………
Ans. (d) : Common collector (CC) amplifier provide (a) 100 mA (b) 10.10 mA
the stepping up to the impedance level and does not (c) 110 mA (d) none of the above
increase signal voltage and common collector is used Nagaland PSC CTSE (Diploma)-2017, Paper-I
for impedance matching.
Ans. (d) : β = 100
59. The power dissipation of the transistor equals
IC = 10 mA IE = ?
the collector-emitter voltage times the
(a) Base Current (b) Load Current I
α= C
(c) Zener Current (d) Fold back Current IE
Mizoram PSC Jr. Grade-2015, Paper-II β 100
TNPSC AE-2013 α = = = 0.99
1 + β 101
Ans. (b) : Power dissipation in transistor
I 10 × 10−3
P = VCE × IL IE = C = = 10.10 mA
α 0.99
64. The relation between β and α is……….. 68. In BJT, DC load line joins
(a) β = 1/ (1 − α) (b) β = (1 − α)/α (a) IC(more) and VCC (b) IC and VCE
(c) β = α / (1 − α) (d) β = α / (1 + α) (c) IC(Max) and VBE (d) IB and VCE
Nagaland PSC CTSE (Diploma)-2017, Paper-I Ans. (b) : The gap between collector current and
Ans. (c) : As we know - collector to emitter voltage is known as load line
I E = IC + I B characteristic.
I E IC I B
= + (Both side divided IC)
IC IC IC 3
2
1 1  IC IC 
= 1+  α = I ,β = I  1
α β  E β 
IB0
1 β +1
=
α β 69. The early effect in a bipolar junction transistor
is caused by
β (a) Fast turn-on
α=
1+ β (b) Fast turn-off
(c) Large collector base reverse bias
α
or β= (d) Large emitter-base forward bias
1− α Nagaland PSC CTSE (Diploma)-2018, Paper-I
65. The Q point in a voltage amplifier is selected in Ans. (c) : The early effect in a bipolar junction
the middle of the active region because transistor is caused by large collector base reverse bias
(a) it gives a distortion less output due to early effect there is an increment of collector
(b) the operation point then becomes very stable. current.
(c) the circuit requires less number of resistors 70. The dc current gain of BJT is 50. Assuming
(d) none of these that the emitter injection efficiency is 0.985, the
Nagaland PSC CTSE (Diploma)-2018, Paper-I base transport factor is
MPPSC Forest Service Exam.-2014 (a) 0.980 (b) 0.985
Ans. (a) : Q-point is the operating point of the (c) 0.990 (d) 0.995
transistor. It is selected in the middle of the active Nagaland PSC CTSE (Diploma)-2018, Paper-I
region because Ans. (d) : β = 50 Base transport factor
(1) It gives or provides maximum possible amplification
to input sinusoidal signal without any distortion. β α
α= B=
(2) The stability of the operating point depends on the 1+ β y
type of bias used and not on the Q point. Voltage 50 50 1
divider bias has better stability than a simple fixed bias α= B= ×
circuit. 51 51 0.985
V1 = 0.985 B = 0.995
66. Largest current flow of a bipolar transistor
occurs 71. A voltage divider biased amplifier has its Q
(a) In emitter point at the middle of the DC load line. What is
the maximum unclipped peak to peak output
(b) In base
voltage?
(c) In collector (a) VCEQ (b) ICQ RC
(d) Through emitter - collector (c) 2 I R (d) 2 V
CQ C CEQ
Ans. (a) : We know that for both transistor (npn or pnp) Ans. (a) : The voltage polarities and current are show
IE=IB+IC for the input voltage.
Hence current through emitter is more as compare to
base and collector current.
67. If the temperature increases then the Q point in
dc load line will be moving towards
(a) Cut-off region
(b) Saturation region
(c) Active region
(d) does not depend on temperature 72. In a BJT, the Ic = 30mA. If β = 100, the base
Nagaland PSC CTSE (Diploma)-2018, Paper-I current approximately equals
Ans. (b) : If the temperature increases then the Q point (a) 0.03 mA (b) 300 mA
in dc load line will be moving towards saturation (c) 0.3 mA (d) 30 mA
region. RPSC Vice Principal ITI-2016

Ans. (c) : For BJT IE = IC + IB Tj − TA
I Pd =
and IB = C θ j− A
β 200º −50º
Pd =
30 mA 100º C
So, IB = = 0.3mA
100 150
Pd =
73. Consider the following circuit configurations 100
1. Common emitter Power dissipation Pd = 1.5 watt
2. Common base 76. An amplifier has a signal input voltage Vi of
3. Emitter follower 0.25 V and draws 1 mA from the source. If the
4. Emitter follower using Darlington pair amplifier delivers 8 V to a load of 10 mA, the
The correct sequence in increasing order of the power gain is
input resistances of these configuration is (a) 340 (b) 320
(a) 2, 1, 4, 3 (b) 1, 2, 4, 3 (c) 250 (d) 150
(c) 2, 1, 3, 4 (d) 1, 2, 3, 4 IES-2019
RPSC Vice Principal ITI-2016 Ans. (b) : The ratio of output power and ratio of input
Ans. (c) : Increasing order of the input resistance is power is called as power gain,
mainly depend on type of configuration, so order is So the given,
Common base < Common emitter < Emitter follower < Vi = .25V
Emitter follower using Darlington pair. Ii = 1mA
74. The voltage gain of CE amplifier circuit can be and Vo = 8V
approximated for an ideal input ac source and
is given by Io = 10mA
re' re' VI
(a) A Vs = (b) A Vs = − Power gain = o o
(RC × RL ) (RC RL ) Vi Ii
8 × 10 × 10−3
(c) A Vs = −
( RC RL )
(d) A Vs = −
( RC × RL ) Po =
25 × 10−3
× 100
' '
re re
8 × 10 × 100
Where: RL = Load resistance Po =
25
RC = Collector resistance
Po = 320
re = Effective resistance at input of transistor
from emitter resistance RE 77. In the case of small BJT model with common
IES-2020 emitter, the collector current ic is 1.3 mA,
Ans. (c) : The most common amplifier configuration for when the collector-emitter voltage is vce of 2.6
V. The output conductance of the circuit is:
an NPN transistor is that of the common emitter
amplifier circuit. (a) 2.0 mΩ (b) 2.0 m
(c) 0.5 mΩ (d) 0.5 m
R C || R L IES-2017
A Vs = −
re' Ans. (d) : Conductance is the ratio of current and
voltage so the output conductance of the BJT circuit is,
Where R L = Load resistance
i
R C = Collecter Resistance gm = c
v ce
re' = effective resistance at input of transistor from
The given as, i c = 1.3 mA
emitter resistance RE
I ≤ I Bβ given ( β=50 )
75. If TA = 50ºC, Tj = 200ºC and θj – A = 100ºC/W, C(sat )
the power that a transistor, 2N1701 can safely i
dissipate in free air will be So, g m = c
(a) 0.5 W (b) 1.5 W v ce
(c) 2.5 W (d) 3.5 W 1.3 × 10−3
IES-2020 =
2.6
Ans. (b) : Given, TA = 50º C g m = 0.5 m
Tj = 200º C and θj – A = 100ºC/W 78. Assuming VCE(Sat) = 0.3 V for Silicon transistor
So we know that at ambient temperature of 25ºC and hFE = 50,
Tj − TA the minimum base current IB required to drive
θ j− A = the transistor into saturation for the circuit
Pd shown is
β = 250
and find αdc
β h
α dc = = fe
1 + β 1 + h fe
(a) 64µA (b) 78µA 250
(c) 94µA (d) 140µA =
1 + 250
IES-2016 250
Ans. (c) : = = .996
251
81. A transistor circuit is shown in the figure
Assume β = 100 RB = 200 kΩ, RC = 1kΩ, VCC =
15V, VBEact = 0.7V, VBEsat = 0.8V and
VCEsat = 0.2V.
Applying KVL in CC to EB
5 − 1kΩ × IC − VCE ( sat ) = 0
5 − VCE ( sat ) 5 − 0.3
IC = =
1kΩ 1×103
IC = 4.7mA
For transistor operate in saturation The transistor is operating in
IC(sat ) ≤ I Bβ given ( β=50 ) (a) Saturation (b) Cut-off
4.7 (c) Normal active (d) Reverse active
IB = mA IES-2016
50
Ans. (c)
I B = 0.094mA
I B = 94µA
79. Which of the following regions of operation are
mainly responsible for heating of the transistor
under switching operation?
1. Saturation region
2. Cut-off region
3. Transition from saturation to cut-off
4. Transition from cut-off to saturation According the question
Select the correct answer using the codes given β = 100, R B = 200kΩ, R C = 1kΩ
below:
(a) 1, 2 and 4 only (b) 1, 3 and 4 only VCC = 15V, VBE( act ) = 0.7V VBE sat = 0.8V
(c) 2 and 3 only (d) 1 and 3 only VCE(Sat ) = 0.2V
IES-2016
Ans. (b) : Saturation region transition from saturation to Appling KVL in 1.
cut-off and transition from cut-off to saturation region VCC − IB R B − VBE = 0
of operation are mainly responsible for heating of the
V − VBE
transistor under switching operation. I B = CC
80. The value of hFE (the hybrid parameters) of a RB
Common-Emitter (CE) connection of a Bipolar 15 − 0.7
Junction Transistor (BJT) is given as 250. I B =
200k
What is the value of αdc (ratio of collector
current to emitter current), for this BJT? I B = 71.5µA ........(i)
(a) 0.436 (b) 0.656 I
(c) 0.874 (d) 0.996 β= C
IB
IES-2016
IC
Ans. (d) : For a BJT the value of αdc=? 100 =
hfe = forward current gain is 250 71.5 × 10−6
IC IC = 100 × 71.5 × 10−6
= h fe = 250 ( h fe = β ) IC = 7.15mA
IB

VCC − VCEsat 25 ×103
= VCCsat − IC R C − VCE = 0, IC = 1.9 = I B + ( I B + IC ) ×103 ( I E = I B + IC )
RC 3
1.9 25
VCC − VCEsat = IB + ( I B + IC )
ICsat = 103 3
RC 28I B
15 − 0.2 1.9 ×10−3 = + IC
IC(sat ) = = 14.8 mA. 3
1kΩ I B << IC
ICsat > IC IC 1.9 × 10 −3
So the transistor is work in normal active region. IC 1.9mA
82. A transistor used potential divider method of
83. In biasing of BJT, the slope of load line can be
biasing. R1 = 50 kΩ, R2 = 10 kΩ and RE = 1 kΩ. calculated using
If VCC = 12V and VBE = 0.1 V, then IC is
(a) Operating base current
(a) 19 mA (b) 2 mA (b) Operating collector current
(c) 1.9 mA (d) 0.19 mA (c) Operating point co-ordinates
IES-2015 (d) Minimum and maximum values of collector
Ans. (c) : current
IES-2015
Ans. (d) : In biasing of BJT, the slope of load line can
be calculated using minimum and maximum value of
collector current.
I −I
Slope = c max cmin
VCC
84. Leakage current approximately doubles for
every 10ºC increase in temperature of a silicon
transistor. If a silicon transistor has ICBO = 1000
nA at 30ºC, what is its leakage current at 90ºC?
(a) 32 µA (b) 64 µA
(c) 16 µA (d) 128 µA
IES-2015
IC = ? Ans. (b) : Leakage current of BJT
 t 2 − t1 
 
R2 10 I t 2 = I t1.2  10 
Vth = VCC = × 12
R1 + R 2 50 + 10
I t1 = 1000 × 10 −9
10
Vth = ×12 t 2 = 90
60
t1 = 30
Vth = 2V
I t 2 = leakage current at temperature t2
R th = R 1 || R 2
I t1 = leakage current at temperature t1
1 1 1
= + 90 −30
R th 10 50 I t 2 = 1000nA.2 10
1 5 +1 6 I t 2 = 1000 ×10 −9 × 64
= ⇒
R th 50 50 I t 2 = 64 µA
50 25 85. Which of the following statements are correct?
R th = = kΩ
6 3 1. ICO for germanium is much greater than
for silicon.
2. The steady-state temperature rise at the
collector junction is proportional to the
power dissipated at the junction.
3. To avoid thermal runaway the required
condition is that the rate at which heat is
released at the collector junction must
exceed the rate at which the heat can be
dissipated under steady-state conditions.
(a) 1, 2 and 3 (b) 2 and 3 only
25 (c) 1 and 3 only (d) 1 and 2 only
2 − 0.1 − ×103 × I B − IE ×103 = 0
3 IES-2015

Ans. (d) : • ICO of germanium is much greater than 5 − 0.2 4.8
Silicon. IC = = × 10−3
1.2kΩ 1.2
• The steady state temperature rise at the collector IC = 4 mA
junction is proportional to the power dissipated at the
IC
function both (1) and (2) are correct. β=
Leakage current in germanium is µA and leakage IB
current in silicon is nA. IC 4
IB = = ×10−3
86. Transistor is in saturation when β 120
I I B = 0.0333 ×10 −3
(a) IB = IC (b) I B > C
βdc I B = 33.3 × 10−6
IC I B = 33.33 µA
(c) I B = 0 (d) I B <
βdc 88. Thermal runaway in a transistor biased in the
Mizoram PSC IOLM -2018, Paper I active region is due to
IES-2015 1. heating of the transistor.
Ans. (b) : In saturation mode both EB and CB is 2. change in β due to increase in temperature.
forward bias so, if collector voltage drops below the 3. change in reverse collector saturation current
base voltage and emitter voltage is below the base due to rise in temperature.
voltage. The transistor is in saturation mode.
4. base emitter voltage VBE which decreases with
IC rise in temperature.
IB >
βDC Which of the above statements is/are correct?
This is the saturation region. Saturation region when its (a) 1 and 2 (b) 2 and 3
collector current is not dependent on the base current (c) 3 only (d) 4 only
and it reached a maximum value. IES-2014, 2012
87. The transistor switch as shown in figure has Ans. (c) : Thermal runaway in transistor is due to
β = 120, VCE(sat) = 0.2V, RC = 1.2 kΩ, and change reverse collector saturation current (ICO).
VCC = 5V This current ICO gets doubled with every 10ºC rise in
temperature.
IO = IS 2( T2 −T1 ) /10
And if transistor heated, which is known as thermal
runaway.
89. If VCC = 18 V, voltage divider resistances R1=
4.7 kΩ and R2 = 1500Ω, what is the base bias
voltage?
(a) 8.70 V (b) 4.35 V
(c) 2.90 V (d) 0.70 V
The output voltage when transistor switch is
IES-2014
closed and the minimum base current needed
to close the switch are, respectively Ans. (b)
(a) 0.2 V and 3.33µA (b) 2 V and 3.33 µA
(c) 0.2 V and 33.3 µA (d) 2 V and 33.3 µA
IES-2014
Ans. (c)
R2
According to question, Vth = VCC
R1 + R 2
Given as,
1500
Transistor in saturation = × 18
4700 + 1500
VO = VC = VCE (sat ) = 0.2v
1.500
= ×18
VCC − V0 6.200
IC =
RC Vth = 4.35V

90. The rise time of a transistor switch is the time 5 − 0.7
for the current to rise from : IB = = 430 µA
(a) Zero value to peak value 10 × 103
(b) 10% of peak value to peak value I 0.96 ×10−3
β= C =
(c) 10 % of peak value to 90% peak value I B 430 × 10−6
(d) 10% of peak value to 80% peak value β = 2.232
IES-2013
Ans. (c) : 10% of peak value to 90% peak value. β is less than 50.
Rise time (tr)- The time taken for the collector current So, transistor is working is saturation region.
to reach from 10% of its initial to 90% of its final value 93. If I
CEO = 410µA, ICBO = 5µA and IB = 30µA
is called as the rise time.
then the collector current is:
91. A CE amplifier has a resistor RF connected
(a) 415µA (b) 440µA
between collector has a resistor RF = 40 kΩ, RC
= 4 kΩ. Given hfe = 50, rπ = 1kΩ, the output (c) 445µA (d) 2.84mA
resistance is: IES-2013
(a) 40 kΩ (b) 20 kΩ Ans. (d) : Given in question
(c) 4 kΩ (d) 0.66 kΩ ICEO = 410µA
IES-2013 I
CBO = 5µA
Ans. (c) : Given- IB = 30µA
R f = 40kΩ , R c = 4kΩ , h fe = 50 , rπ = 1kΩ
ICEO = (1 + β ) ICBO
R o = R c || R f
I
4 × 40 160 1 + β = CEO
= = ICBO
4+4 44
R o = 3.64k R o ≃ 4kΩ 410
1+ β =
5
92. The transistor as shown in the circuit is
operating in: 1 + β = 82
β = 82 − 1
β = 81
Take the value β
We know
IC = βI B + ICEO
IC = 81 × 30 × 10 −6 + 410 × 10 −6
IC = ( 2430 + 410 ) × 10−6
(a) Cut-off region
(b) Saturation region IC = 2840 × 10−6
(c) Active region 2840 × 10−3
IC =
(d) Either in active or saturation region 1000
IES-2013
IC = 2.84 mA
Ans. (b) :
94.
The trans-conductance gm of the transistor

used in the CE amplifier shown in the above
According to figure
circuit, operating at room temperature is
R C = 5kΩ , R B = 10kΩ , VB = 5V , VCC = 5V (a) 92 mA/V (b) 46 mA/V
5 − 0.2 4.8 × 10−3 (c) 184 mA/V (d) 25 mA/V
IC = = = 0.96mA
5 × 103 5 IES-2013

Ans. (a) 97. A bipolar junction transistor with forward
current transfer ratio α = 0.98, when working
in CE mode, provides current transfer ratio β
as
(a) 98 (b) 0.02
(c) 49 (d) 0.49
IES-2012
Ans. (c) : According to question,
Given α = 0.98
Given that, β=?
β = 100 α
β=
VBE = 0.7 1− α
VT = 25mV ( at room temperature) β=
0.98
VBB − VBE 3 − 0.7 1 − 0.98
IB = = 0.98
RB 100 × 103 β= = 49
0.02
I B = 2.3 × 10 −5 98. A BJT is biased with a power supply of 12V.
I B = 23 µA For minimum heat dissipation, the drop across
the transistor will be
IC
We know that β = (a) 6 V (b) 9 V
IB
(c) 12 V (d) > 9V but < 12 V
IC = 100 × 23 × 10 −6 = 2.3mA IES-2012
IC −3
2.3 × 10 Ans. (a) : Thermal runaway in transistor is due to
∴ transconductance (gm) = = = 92mA/V reverse collector saturation current (ICO)
VT 25 × 10−3
When transistor heated, which is known as thermal
95. If an npn silicon transistor is operated at runaway.
VCE = 5V and IC = 100 µA and has a current To avoid thermal runaway
gain of 100 in the CE connection, then the input V
resistance of this circuit will be VCE ≤ CC
2
(a) 250 Ω (b) 25 kΩ
12
(c) 250 kΩ (d) 2500 kΩ VCE ≤
IES-2013 2
Ans. (b) : VCE = 5V VCE ≤ 6
IC = 100 µA VCE = 6V
Current gain (hfe) = 100 99. For the transistor circuit shown in the figure,
h fe h fe .VT  IC  when:
Ri = =  gm = 
gm IC  VT 
100 × 25 × 10−3
= (VT = 25 mV at room temperature)
100 ×10−6
R i = 25kΩ
96. A transistor is said to be useful to be
configured as an amplifier when its β is
(a) Less than 0 (b) Between 0 and 1
(c) Between 1 and 50 (d) > 50 1. Vin > 0, transistor is OFF
IES-2012 2. Vin ≤ 0, transistor is OFF
Ans. (d) : For the current gain of the common emitter I
3. I B > C , transistor is ON
amplifier to be large the value of β needs to be very h FE
high. IC
4. I B ≤ , transistor is ON
I h FE
β= C
IB Which of the statements are correct?
(a) 1, 2, 3 and 4 (b) 1 and 2 only
Thus the β > 50 in CE amplifier in thus cases, we can
(c) 2 and 3 only (d) 3 and 4 only
say that it work as a current amplifier. IES-2011
Ans. (c) : Vin ≤ 0 transistor is off 102. The collector and Emitter current levels for a
I transistor with Common base dc current gain
I B > C , transistor in ON of 0.99 and base current of 20µA are
h FE respectively.
Above both condition turn on the transistor. (a) 2 mA and 1.98 mA (b) 1.98 µA and 2 mA
When IC = hfe.IB then transistor operate in active region. (c) 1.98 mA and 2 mA (d) 2 mA and 1.98 µA
And IC < h fe .I B then transistor operate saturation region. IES-2011
100. A small signal voltage amplifier in common Ans. (c) : According to question
emitter configuration was working Given,
satisfactorily. Suddenly its emitter- bypass α = 0.99
capacitor (CE) got disconnected. Its: I B = 20 × 10−6 = 20 µA
1. Voltage gain will decrease
2. Voltage gain will increase α 0.99
β= =
3. Bandwidth will decrease 1 − α 1 − 0.99
4. Bandwidth will increase 0.99
Which of these statements are correct? β= = 99
0.01
(a) 1 and 4 only (b) 2 and 3 only β = 99
(c) 3 and 4 only (d) 1, 2, 3 and 4
IES-2011 IC
BSNL (JTO)-2001 β = I
B
Ans. (a) : When emitter bypass capacitor is
disconnected, we used feedback connection for 99 × 20 ×10 −6 = IC
established to emitter resistance 1980 × 10 −6 = IC
Also we know
1.98 mA = IC
Gain ×Bandwidth = constant
Thus, the gain of the feedback amplifier decrease the IC = 1.98 mA
above formula For common collector
When we decrease gain, then Bandwidth increase. I E = IB + IC
101. What is the name of the circuit shown below?
I E = 0.020 + 1.98
IE = 2mA
103. The biasing of an IC in BJT is done by the
following biasing scheme.
(a) Potential-divider biasing scheme
(b) Fixed biasing scheme
(c) Current mirror biasing scheme
(d) Collector to base feedback biasing scheme
(a) Miller sweep
IES-2011
(b) Bootstrap sweep
Ans. (c) : In IC amplifiers BJT biasing is used by the
(c) Schmitt trigger
current mirror scheme. Since the output current is a
(d) Triangular wave generator mirror image of the input current, the circuit is known a
IES-2011, 2004, 1996 current mirror.
Ans. (a) : A current mirror biasing scheme is used in an IC BJT
to reduce the fabrication spacing.
A current mirror is also used as an active load in IC
amplifiers to achieve greater voltage gain.
104. Biasing is used in transistor amplifiers to
1. Stabilize the operating point against
temperature variations
2. Place the operating point in the linear
The above given circuit is a miller sweep circuit region of the characteristics.
application.
3. Make α, β and ICO of the transistor
Miller sweep circuits are the most commonly used independent of temperature variations.
integrator circuit in many devices. It is a widely used 4. Reduce distortion and increases dynamic
saw tooth generator. range.
The transistor miller time base generator circuit is the (a) 1, 2, 3 and 4 (b) 1, 2 and 4 only
popular miller integrator circuit that produce a sweep (c) 1, 2 and 3 only (d) 2, 3 and 4 only
wave form. IES-2011
Ans. (b) : Biasing is used in transistor to- 108. Consider the following statements:
● Stabilize the operating point against temperature To draw a.c. equivalent circuit of a transistor, all
variations. 1. d.c. sources are shorted
● Place the operating point in the linear region of the 2. a.c. sources are shorted
characteristics . 3. d.c. sources are opened
• Reduce distortion and increases dynamic range. 4. a.c. sources are connected to d.c. sources
Which of the above statements is/are correct?
105. Why npn-transistors are preferred over pnp-
(a) 2 and 4 (b) 1 and 2
transistors?
(c) 1 only (d) 3 and 4
(a) Leakage current in npn-transistors is less than IES-2009
pnp-transistors
Ans. (c) : To draw a.c equivalent circuit of a transistor
(b) Mobility of majority carrier in npn-transistors d.c source are shorted.
is greater than the mobility of majority carrier
109. Operating point shift can occur in an amplifier
in pnp-transistors.
due to which one of the following?
(c) Bias voltage required in npn is less than in (a) Input frequency variation
pnp-transistors (b) Noise at the input
(d) Bias voltage required in npn is greater than in (c) Parasitic capacitances
pnp-transistors. (d) Power supply fluctuation
IES-2009 IES-2008
Ans. (b) : A NPN transistor has electrons as majority Ans. (d) : Operating point of a device, also known as a
charge carriers where as the PNP transistor has holes as bias point, quiescent point or a point.
majority charge carriers the mobility of electron is Operating point which is obtained from value of the Ic
better than holes, NPN transistor is faster than PNP and Vce when no signal is given to the input operating
transistor so we preferred npn transistor over pnp point shift can occur in an amplifier due to lower supply
transistor. fluctuation. If the power supply change the operating
106. Consider the following statements: point change.
The bias stability of an emitter-bias amplifier The operating point can be easily obtained by dc load
circuit improves by line method.
1. decreasing the value of RB
2. increase the value of RE
3. decreasing the value of RE
4. increasing the value of RB.
5. Increasing the value of RC.
Which of the above statements are correct? 110. Consider the following statements:
(a) 1 and 2 (b) 2 and 3 Bias stabilization in a BJT circuit is very
(c) 3 and 4 (d) 4 and 5 important, because it
IES-2009 1. provides high voltage and current gain
Ans. (a) : The bias stability of a emitter bias circuit can 2. ensures large bandwidth of the amplifier
be improved by decreasing the value of RB and increase 3. keeps the operating point unchanged with
the value of RE. change of temperature.
Because RE is used for negative in Amplifier. Which of the above statements (S) is/are
107. Which of the following will be true for a CE correct?
transistor amplifier if the emitter resistor value (a) 1 and 2 (b) 2 and 3
is made equal to zero? (c) 3 only (d) 1 and 3
IES-2008, 2007
1. Its gain will increase
2. Its stability will increase Ans. (c) : Bias stabilization is a process to making Q-
point or operating point independent/unchange of
3. Its gain will decrease changes in temperature and change in transistor
4. Its stability will decrease. parameter.
Select the correct answer from the codes given 111. CE configuration is the most preferred
below: transistor configuration when used as a switch
(a) 1 and 2 (b) 2 and 3 because
(c) 3 and 4 (d) 1 and 4 (a) it requires only one power supply
IES-2009 (b) it requires low voltage or current for
Ans. (d) : In CE transistor amplifier, if the emitter operating the switch
resistor value is made equal to zero the value of gain (c) it is easily understood every one
will increase and stability will be decrease RE provide (d) it has small ICEO
negative feedback and improved the stability IES-2016, 2008, 2000

Ans. (b) : CE configuration is the most preferred Ans. (a) : The d.c load line of CE amplifier is drawn in
transistor because it require low voltage and current for
IC versus VCE for a given value of (RC+RE)
operating the switch. CE has low input impedance and D.C. load line analysis significance-
high output impedance. It is used for audio frequency • By using the direct correct load line concept. We can
application. In CE configuration phase shift between obtain the linear analysis of the circuit for non-linear
input and output is 180º. elements such as diodes or transistors.
I • The D.C load line analysis main intention is find the
β is the ratio of IC and IB β = C quiescent point (Q-point).
IB
112. Cascode amplifier when compared with a 115. Consider the following parameters of a hybrid-
simple common-emitter amplifier provide π equivalent circuit of BJT:
which of the following? 1. Trans conductance (gm)
(a) Higher voltage gain and same bandwidth 2. hfe
(b) Same voltage gain but higher bandwidth 3. hie
(c) No change in either voltage gain or Which of the above parameters vary with
bandwidth temperature in similar manner (all of them
(d) Voltage gain less than one but bandwidth decrease or all of them increase)? Select the
equal to fT. correct answer using the code given below:
IES-2007 (a) Only 1 and 2 (b) Only 2 and 3
Ans. (b) : Cascode amplifier when compared with a (c) Only 1 and 3 (d) 1, 2 and 3
simple common-emitter amplifier provide same voltage IES-2006
gain but high band width. h
Application of cascode amplifier- Ans. (b) : Trans-conductance (gm) = fe
h ie
• This amplifier is used in tuned RF amplifiers with
V
television circuit. re = T = α g m
• The isolation offered among input & output with IE
these amplifiers is extremely high. When temperature increase, α increase thus hfe also
113. Which of the following features are offered by increases.
a bipolar junction transistor amplifier in 116. When a voltage divider biased amplifier has its
Darlington connection? Q-point near to the middle of the dc-load line,
1. High voltage gain what is the maximum unclipped peak-to-peak
2. High input impedance output voltage?
3. High current gain (a) VCEQ (b) ICQrL
Select the correct answer using the code given (c) 2ICQrL (d) 2VCEQ
below: IES-2005
(a) 1 and 2 only (b) 2 and 3 only Ans. (d) :
(c) 1 and 3 only (d) 1, 2 and 3
Nagaland PSC (Degree)-2018, Paper-II
IES-2015, 2007, 1992
Ans. (b) :
It is consist of two common collector transistors in

cascade connection. It has unit voltage gain. Very high
input resistance low output resistance and high current
gain. It is used as a buffer amplifier.
114. For a CE amplifier, d.c. load line is drawn in if Q-point is at the middle of D.C load line.
which one of the following plots? V
(a) IC versus VCE for a given value of (RC + RE) VCEQ = CC
2
and VCC Maximum (peak to peak) unclipped voltage = 2VCEQ
(b) IB versus VEE for a given value of (RC + RE) 117. Consider the following statements:
and VCC
1. To achieve wide bandwidth, a transistor
(c) IB versus VCE for a given value of IB with a small Cbc is chosen.
(d) IC versus VCB for a given value of IE 2. To achieve wide bandwidth, a transistor
IES-2007 with a small Cbe is chosen.
3. To achieve wide bandwidth, a transistor 119. Consider the following circuit:
with a small base spreading resistance is
chosen.
correct?
(a) 1 and 2 (b) 2 and 3
(c) 1 and 3 (d) 1, 2 and 3
IES-2005
Ans. (a) : To achieve wide bandwidth, a transistor with
What is voltage difference between collector
a small Cbc and Cbe is used.
and emitter (VCE) in the above circuit?
118. Consider the following circuits: (a) 10/3 V (b) 0 V
(c) 5 V (d) 3 V
IES-2004
Ans. (c) : Given, VCC = 5V
Which one of then following statements is

correct?
(a) Circuit 1 is parallel connection and Circuit 2
is Darlington connection.
(b) Circuit 1 is cascode connection and Circuit 2 According to figure
is Darlington connection IB = 0
(c) Circuit 1 is Darlington connection and Circuit
we know IC = βI B
2 is cascode connection
(d) Circuit 1 is cascode connection and circuit 2 IC = β × 0 {IB = 0}
is parallel connection. IC = 0
IES-2004, 1997 ∴ V = V − I R − I R
CE CC C C E E
Ans. (b) : VCE = VCC − 0 − 0
VCE = VCC
VCE = 5 V
120. A bipolar junction transistor is in saturation
region. Given VCC = 10 V, RC = 1 kΩ, hFE = 100
and VCEsat = 0.3 V. What is the collector
current in saturation?
(a) 10 mA (b) 9.7 mA
(c) 0 mA (d) 1 mA
IES-2004
From the above figure, Ans. (b) : Given,
VCC = 10V
Circuit 1- is a cascode connection and circuit-2 is a
RC = 1kΩ
Darlington connection.
hFE = 100
In cascade amplifier is a cascode of CE and CB VCE(sat) = 0.3
amplifiers yet Darlington is a cascade of two common
collector amplifier.
Darlington Amplifier used in buffer amplifier cascode
amplifier provide both voltage and current amplification
therefore preferred over common base amplifier in radio
frequency amplification and wideband amplification.
So the option (b) circuit 1 is cascode connection and Applying KVL-
circuit 2 is Darlington connection. VCC – ICRC – VCE(sat) = 0
10 – IC ×1 ×103 –0.3 = 0 The given above circuit is a boot strap circuit. Bootstrap
10 – 0.3 = IC ×1 ×103 biasing network is a special biasing circuit used in
9.7 Darlington amplifier to prevent the decrease in input
= IC resistance due to the biasing network being used.
1× 103 Capacitor and resistance are added to the circuit to
IC = 9.7mA prevent it from happening.
121. Match List-I (Circuit) with List-II (Property) 123. Which of the following main properties of a
and select the correct answer using the codes bipolar junction transistor make it necessary
given below the lists: for the transistor to have bias stabilization ?
List-I List-II 1. Variation of VBE with temperature.
A. R-C coupled single 1. Beta multiplier 2. Variation of hFE with temperature
stage amplifier 3. Variation of ICO with temperature
B. Emitter follower 2. Constant current 4. Variation of hFE with transistor
source replacement
C. Common base 3. Very high input 5. Variation of VBE with transistors
amplifier impedance replacement
D. Darlington amplifier 4. phase inverter 6. Variation of ICO with transistor
with voltage gain replacement
Codes: Select the correct answer using the codes given
A B C D below:
(a) 3 4 1 2 (a) 1, 2 and 6 (b) 1, 3 and 4
(b) 4 3 1 2 (c) 2, 3 and 5 (d) 3, 4, 5 and 6
(c) 3 4 2 1 IES-2003
(d) 4 3 2 1 Ans. (c) : Bipolar junction transistor make it necessary
IES-2003 for the transistor to have bias stabilization
Ans. (d) • Variation of hFE with temperature
R-C coupled single stage amplifier is a phase • Variation of ICO with temperature
inverter. • Variation of VBE with transistors replacement
Emitter follower source is used in impedance The process of making the operating point independent
matching. Emitter follower has low output of temperature charges or variation in transistor
impedance and high input impedance. parameter is known as stabilization.
Common base amplifier has constant current it 124. In the circuit shown below, if R1 >> Rp and the
current gain is equal to very low. impulses can completely saturate transistor Q1.
Darlington amplifier is a two transistor multiplier it is then the output voltage V0 will be
a beta multiplier. It is used in buffer.
122. The biasing shown in the below circuit is
(a) Emitter bias (b) Self bias

(c) Potential divider bias (d) Bootstrap bias (a) (b)
IES-2003
Ans. (d)
(c) (d)
IES-2002
Ans. (d) : There is a CE transistor in a circuit so output
has phase shift of 180º gain due to charging and
discharging of capacitor find output ramp positive and
negative.

125. In the circuit shown, 4.3
IB =
100 × 103
4.3
IB = 5
10
I B = 0.043 mA
IC = β× I B (Assume β = 100 )
the transistor is biased at = 100 × 0.043
(a) 0 mA (b) 5 mA IC = 4.3mA
(c) 3.9 mA (d) ∞
IES-2002 Vc = 5 − 5 × 103 × Ic
Ans. (c) : Vc = 5 − 5 × 4.3
Vc = −16.5
VE = 0
If VC < VE {then we know transistor is in saturation
region}
If Vc > VE {Transistor is in active region}
So the option is in saturation region.
the bootstrap biasing arrangement for a BJT
For saturation emitter follower:
VCE = 0.2V 1. The input impedance is very high
VCC –ICRC–VCE = 0 2. The voltage gain is exactly equal to one
10 –2.5 ×103×IC –0.2 = 0 3. The output impedance is equal to zero
9.8 = 2.5 ×103 × IC Which of these statements is correct?
(a) None (b) 2 alone
9.8
IC = (c) 3 alone (d) 1 alone
2.5 ×103 Kerala PSC Lecturer (NCA)-04.07.2017
IC = 3.92mA IES-2000
126. The transistor in the circuit of the given figure Ans. (d) : Transistor Bootstrapping circuit using BJT-
is operating Boot strapping is a technique used in the design of
transistor amplifier circuit to increase the input
impedance and thereby reduce the loading effects on the
input source. It typically involves the use of bootstrap
capacitor, which provides positive feedback of ac signal
to the base junction of a transistor in an emitter follower
circuit.
128. In the circuit shown in the given figure, the
(a) in the cut-off region approximate voltage at the transistor
(b) in the active region
(c) in the saturation region
(d) either in the active or the saturation region.
IES-2001
Ans. (c)
(a) base and emitter respectively are –8V and –

7.3 V.
(b) base and collector respectively are –8 V and –
5V
(c) collector and emitter respectively are –8V
and –7.3 V
VBB = 100 ×103 × I B + 0.7 (d) base, emitter and collector respectively are –
8V, –7.3 and –5V.
5 = 100 ×103 × I B + 0.7 IES-2000
Ans. (a) 130. Consider the following statements:
A totem pole configuration used in the output
stage of an op-amp has the advantage of using
1. only n-p-n BJTs
2. complementary symmetrical pair of
transistors
3. only one transistors
Which of these statement is/are correct?
The give figure is (voltage divider Biasing) we know (a) 1 alone (b) 2 alone
that (c) 3 alone (d) 1 and 3
16 IES-2000
Vth = × −10 Ans. (a) : A totem pole configuration used in the output
4 + 16
stage of an op amp has the advantage of using only n-p-
16
Vth = × −10 n BJT.
20 131. The collector voltage VC of the circuit shown in
Vth = −8v the given figure is approximately
R th = 4 ||16
16
R th = = 3.2kΩ
5
VCE = 0.7 (Assume)
VE = VB + VCE
= –8 + 0.7
VE = –7.3V (a) 2 V (b) 4.6 V
(c) 8 V (d) 8.6 V
129. A common emitter amplifier circuit is shown in IES-1999
the given figure Ans. (c) :
The slope of AC load line is

 1 1   1 
(a) −  +  (b) −  
 RL RC   RL + RC 
1 1  
(c) − (d) − 20 kΩ
RL RC VB = 10  
 20 kΩ + 20 kΩ 
IES-2000
VB = 5V
Ans. (a) : Formula-
VE = VB − VBE
1
=− = 5– 0.7
R C || R L VE = 4.3V
−1 V 4.3
= IE = E = = 1mA
 RC × RL  R E 4.3 kΩ
 
 R L + RC  (IE= IC = 1mA). IB is very low.
 R + RC  VCC –ICRC = VC
= − L  10 – 1×10–3 ×2×103 = VC
 RC × RL  VC = 10 – 2
 RL RC  VC = 8V
= − + 
 R C .R L R C .R L  132. Thermal runaway will take place if the
quiescent point is such that
 1 1 
Slope of A.C load line. = −  +  1
R
 C R L 
(a) VCE > VCC (b) VCC < VCC
2
1 Thevenin's equivalent circuit-
(c) VCE < 2VCC (d) VCE < VCC
2
IES-1999
Ans. (a) : The condition for thermal runaway to occur is
in-
V
VCE > CC
2
133. In a transistor amplifier, the reverse saturation
current ICO.
(a) Doubles for every 10ºC rise in temperature
(b) Doubles for every 1ºC rise in temperature
R 1R 2
(c) Increase linearly with temperature R th = R1 || R 2 =
(d) Doubles for every 5ºC rise in temperature R1 + R 2
IES-1998 1+ β
Ans. (a) : In a transistor amplifier, the reverse Stability factor (s) = ………….(i)
 dI B 
saturation current (ICO) is doubles for every 10ºC rise in 1− β 
temperature.  dIC 
 T2 – T1  dIB dI
  0 = R th + RE + RE B
I0 (T2 ) = I0 ( T1 ) .2 10 
dIC dIC
dI B
134. A transistor is operated as a non-saturated −R E = ( R th + R E )
switch to eliminate dIC
(a) Storage-time (b) Turn-off time 1+ β
(c) Turn-on time (d) Delay time s=
RE
IES-1998 1+ β
R th + R E
Ans. (a) : A transistor switching speed is very crucial
parameter in high speed operation. Lower the switching
s=
(1 + β )( R th + R E )
speed better the performance in speed.
Switching speed depends on storage time and transient
( R th + R E ) + β ( R E )
time. Mainly depends in storage time, if storage time is (1 + β )( R th + R E ) R th << R E (1 + β )
less switching speed is fast the storage time depends on s =
R th + R E (1 + β )
current lower the on current the storage time.
135. For transistor amplifier with self-biasing R + RE
network, the following components are used: s = th …………………(ii)
RE
R1 = 4kΩ, R2 = 4 kΩ and RE = 1 kΩ
The approximate value of the stability factor 4 × 4 16
R th = = =2
'S' will be 4+4 8
(a) 4 (b) 3 Put value at equation (i)
(c) 2 (d) 1.5
2 +1 3
IES-1998 s = = =3
Ans. (b) : Self bias circuit in the given circuit 1 1
R 1 = 4KΩ, R 2 = 4 KΩ R E = 1 KΩ 136. In the circuit shown in the figure, if RL = RC =
Self bias circuit (voltage divider circuit) 1 kΩ, then the value of V0 will be
(a) 4.55 V (b) 2.5 V

(c) 1 V (d) zero
IES-1998

Ans. (b) 138. Match List-I (Transistor parameter) with List-
II (Typical value) and select the correct answer
using the codes given below the lists:
List-I List-II
A. rbb 1. 80 kΩ
B. rbe 2. 1 kΩ
C. rce 3. 100Ω
D. Cbe 4. 100pF
5. 3 pF
IC Codes:
Current gain, β =
IB A B C D
(a) 3 2 1 4
IC = βI B
(b) 3 2 1 5
IC = β× 0 (c) 1 3 2 4
IC = 0 (d) 1 3 2 5
∴ IE = IB + IC IES-1997
Ans. (b) : According to question.
=0+0
Typically II- model parameter force is-
=0
rbb is of the order of - 100Ω
Q IE, IB, IC value is zero so, transistor operate in cut-off
region. rbe is the order of - 1kΩ
rce is order of- 80kΩ
cbe is order of - 3pF
139. In the case of the circuit shown in the figure,
the collector current Ic will be
5× RL 5 ×1kΩ
V0 = =
R C + R L 1kΩ + 1kΩ
5
V0 = = 2.5V
2
137. The 'h' parameters of the BJT shown in the
figure are: hib = 25Ω ; hfb = 0.999 and hob = 10–6
The voltage gain is
(a) 2.26 mA (b) 1.85 mA
(c) 0.375 mA (d) 0.185 mA
IES-1997
Ans. (b) :
(a) 0.999 (b) 1.98

(c) 2.0 (d) 400
IES-1997
Ans. (d) : The following question given as
h ib = 25Ω h fb = 0.999 h ob = 10 −6
12
Voltage gain (AV) = ? Vth = × 12
12 + 20
h 0.99 0.99
Current gain = fe = = Vth = 4.5V
1 + h fe 1 + 0.01 1.01
R th = R1 R 2
A i = 0.98 1
Ai R L 1× R L 1 1 1 4 + 12 32
Voltage gain = = = + = =
Zi h il R th 12 20 12 × 20 240
1 4
10 × 103 =
Voltage gain = = 400 R th 30
25
R th = 7.5kΩ Ans. (c) :
• Input at base point and output from collector point→
Applying KVL in input loop- Amplifier in CE mode with no feedback.
• Input at base point and output from Emitter point →
Amplifier in CC mode with feedback.
• Input at Emitter point and output from collector point
→ Amplifier in CB mode with no feedback.
• Input the base point and output from collector point
→ Amplifier in CE mode with feedback.
141. If α = 0.995, IE = 10 mA and ICO = 0.5µA, then
VTh = IBRTh + VBE + IE. RE ICEO will be
VTh = I B R Th + VBE + (1 + β) IB × 2 × 103 (a) 100 µA (b) 25 µA
(c) 10.1 mA (d) 10.5 mA
4.5 = 7.5 ×103 I B + 0.7 + (1 + 100) IB × 2 × 103
IES-1996
3.8 = 103 × IB (7.5 + 202) Ans. (a) : Given,
3.8 = 103 × I B × 209.5 α = 0.995 IE = 10mA ICO = 0.5µA
IB = 0.0181mA ICEO = ?
IC = βIB β
IC = 100×0.0181mA α=
1+ β
IC = 1.81mA ≅ 1.85mA
β
140. The circuit shown in the given figure is 0.995 =
modified according to List-I. Match List with II 1+ β
and select the correct answer using the codes 0.995 + 0.995β = β
given be the lists:
0.995 = β − 0.995β
0.995 = β (1 − 0.995 )
0.995
β=
0.005
β = 199
ICEO = (1 + β ) ICBO
List-I List-II
A. CB = 0, CC = 0, CE = 1. Amplifier in CC ICEO = (1 + 199 ) × 0.5 ×10−6
∞. Input at base mode with ICEO = 200 × 0.5 × 10−6
point and output feedback
ICEO = 100µA
from collector point
B. CB = 0, CE = 0, CC = 2. Amplifier in CB 142. The circuit shown in the given figure is a
∞. Input at base mode with no
from emitter point
C. CB = ∞, CE = 0, CC = 3. Amplifier in CE
0. Input at Emitter mode with
from collector point (a) Constant voltage source
D. CB = 0, CE = 0, CC = 4. Amplifier in CE (b) Constant current source
0, Input the base mode with no (c) Common emitter amplifier
point and output feedback (d) Common base amplifier
from collector point IES-1995
Codes: Ans. (b)
A B C D
(a) 1 2 3 4
(b) 4 3 2 1
(c) 4 1 2 3
(d) 2 3 4 1
IES-1996

IB = 0 Ans. (c) : Self biasing (voltage Divider circuit) will give
the best performance in preventing the variation of
then I E ≃ IC = I L collector current against change in ambient temperature.
VZ • Self bias circuit has least stability factor among all
IC = biasing circuit.
RC
• Stability factor is independent of Rc.
VZ • Self biasing circuit can be used to bias BJT for any
IL = There is RC value is constant then the circuit
RC configuration.
behave like a constant current source.
Drift in direct coupled amplifiers may be
reduced effectively by use of
1. A diode as thermal compensating element.
2. Another active device, making it a
differential amplifier.
3. Bypass capacitors.
4. Choppers.
Of these statements R2
Vth = VCC
(a) 1 and 3 are correct R 1 + R2
(b) 1, 2 and 3 are correct R th = R1 || R 2
(c) 2 and 4 are correct
145. In the circuits shown in the following figure,
(d) 1, 2 and 4 are correct the feedback causes
IES-1995
Ans. (d) : A direct coupled amplifier is a type of
amplifier in which the output of one stage of the
amplifier is coupled to the input of the next state in such
away as to permit signal with zero frequency also
referred to as direct current, to pass from input to
output. Drift in direct coupled amplifier may be reduced
effectively by use of (a) an increase in both the input and output
• A diode as thermal compensating element. impedance
• Another active device, making it a differential (b) an increase in the input impedance but a
amplifier. decrease in the output impedance
• Choppers. (c) a decrease in both input and output
impedances
144. Which one of the following biasing will give the (d) a decrease in the input impedance but an
best performance in preventing the variation of increase in the output impedance
collector current against change in ambient IES-1994
temperature?
Ans. (b) : In this circuit fraction of the output voltage is
applied in series with the input voltage through the
feedback circuit. So this is a voltage series feedback
(a) (b) circuit.
Due to voltage series feedback input resistance
increases and output resistance decreases.
146. What should be the Collector-Emitter
breakdown voltage BVCEO of the transistors
used in the circuit shown in the given figure?
(d)
(c)
(a) βVCEO ≥ VCC (b) βVCEO ≥ VCC/2

(c) βVCEO ≥ 2VCC (d) βVCEO ≥ (VCC + E)
IES-1994 IES-1993
Ans. (b) : The collector Emitter breakdown voltage I E I B IC
β VCEO ≥ VCC / 2 . = +
IB IB IB
147. For the circuit shown in the given figure, the γ = 1+ β
quiescent point is
1  1 
= 1+ β γ = 
1− α  1 − α
1
−1 = β
1− α
1 − (1 − α )
=β
1− α
1−1+ α
=β
1− α
(a) 12 V, 5mA (b) 12V, 2mA α
(c) 10V, 2mA (d) 10V, 5mA =β
1− α
IES-1993
149. Match List-I with match List-II and select the
Ans. (c) Assume β is very high then I B = 0 correct answer using the code given below:
List-I List-II
A. Darlington 1. The output current is the
connection same in both the
devices in the circuit
B. Cascade 2. The output current of the
connection first device becomes the
input current of the
second device
So, IBRB= 0 C. Differential 3. The collector of the first
amplifier device is connected to the
then IC I E
base of the second device
Applying KVL in E-B loop without using capacitor
0–IBRB– VBE – IERE = –30 D. Direct coupled 4. Output voltage depends
0 – 0.7 – IE × 15×103 = –30 amplifier on the relative values of
29.3 the two input voltages
IE = 2mA
15 × 103 Codes:
KVL applying in C-E loop- A B C D
Vcc − Ic R c − VCEQ − I E R E + 30 = 0 (a) 1 2 3 4
(b) 3 4 1 2
20 − 2 ×10−3 × 5 × 103 − VCEQ − 2 ×10−3 × 15 × 103 + 30 = 0 (c) 2 1 4 3
20 − 10 − VCEQ − 30 + 30 = 0 (d) 4 3 2 1
IES-1991
− VCEQ + 10 = 0
Ans. (c) : Darlington Amplifier- Darlington amplifier
VCEQ = 10V is used for buffer. In this amplifier first transistor output
The value of quiescent point current second transistor input current connect.
= (VCEQ, IC)
= (10V, 2mA)
148. For the junction transistor, which of the
following relation is true?
β
(a) α = (b) α = β(1 + β)
β −1
α α
(c) β = (d) β =
1− α 1+ α Common collector configuration
IES-1992 • Cascade connection– Cascade connection is the
Ans. (c) : Basic formula of transistor process the first device output current for the second
I E = IB + IC .............. (i) device input current is called cascading.
In equation (i) divided by IB A = A1 × A 2 × A 3 ..........

• Differential Amplifier– Differential amplifier is a 151. In the BJT amplifier shown in the figure is the
type of electronic amplifier that amplifies the transistor is biased in the forward active region
difference between two input voltage putting a capacitor across RE will
In differential amplifier output voltage depends on the

relative value of the two input voltage.
• Direct coupled Amplifier:-
(a) Decrease the voltage gain and decreases the
input impedance
(b) Increase the voltage gain and decreases the
input impedance
Direct coupled amplifier the collector of the first device (c) Decrease the voltage gain and increase the
is connected to the base of the second device without input impedance
using capacitor. (d) Increase the voltage gain and increase the
150. For the amplifier circuit of figure. The input impedance
transistor has a β of 800. The mid band voltage GATE-1997
gain V0/Vi of the circuit will be. Ans. (b) :
(a) 0 (b) < 1

(c) ≈ 1 (d) 800
GATE-1993 1
Ans. (c) : Given, β = 800 Q X CE =
2πfC
• If f→ low, then X CE → High, then current Ie will not
be pass.
• If f→ High, X CE → low
then current Ie will be pass.
Putting a capacitor across common emitter resistance CE
which voltage gain will be increase and decreased the
Input impedance. Capacitor CE act as by pass. Thus
The circuit is PNP transistor, collector coupled 'AC' signals will pass through capacitor CE. Eliminated
amplifier. The voltage gain is unity for a CC amplifier. the feedback effect, it is used to emitter resistance
Equivalent circuit, across capacitor CE. Reduced the input voltage drop.
RE
X CE ≤ ( Pratically conditions )
10
152. The circuit of the figure is an example of
feedback of the following type
V0 V0
Voltage gain = A V = = (Vbe is very small,
Vi V0 + Vbe
let neglected)
V0
≅1
V0 (a) current series (b) current shunt
So, Vi = V0 = Ve ⇒ Emitter always following to input (c) voltage series (d) voltage shunt
Hence, This is condition emitter follower. GATE-1998
Ans. (d) So,
Ad
CMRR =
Ac
R E ↑→ A c ↓ CMRR ↑ but A d has not effected.
154. In the circuit of the figure, assume that the
This is figure represented voltage shunt feedback. transistor is in the active region. It has a large
In the voltage shunt feedback circuit a traction of the β and its base-emitter voltage is 0.7 V. The
output voltage is applied in parallel with the input value of Ic is
voltage through the feedback.
Voltage shunt feedback characteristics-
1. Voltage gain – Decreases
2. Bandwidth – Increases
3. Input Resistance – Decreases
4. Output Resistance – Decreases
5. Harmonic distortion – Decreases
6. Noise – Decreases
(a)
Indeterminate since Rc is not given
153. In the differential amplifier of the figure, if the (b)
1 mA
source resistance of the current source IEE is (c)
5 mA
infinite, then the common-mode gain is
(d)
10 mA
GATE-2000
Ans. (d) : Given,
β = large value
VBE = 0.7V
Apply potential divider at point B
(a) zero (b) infinite

V + Vin 2
(c) indeterminate (d) in1
2VT
GATE-2000
10 × 5 10
Ans. (a) : R th = = Ω
15 3
R V
Vth = 2 CC
R1 + R 2
5 × 15
= = 5V
15
Q β = large value
IC I IC
So, β = ⇒ IB = C = ≅0
IB β large value
Q Differential mode gain, I E = IB + IC
Ad = gm (RC || r0) I E = IC (Q IB = 0 )
where r0 = output impedance of BJT
Vth − VBE
and common mode gain IE =
RE
−R C
Ac = R E ↑→ A c ↓ Vth − VBE
2R E So, IC = I E =
RE
Q Differential mode gain Ad independent of RE
Vth − VBE 5 − 0.7 4.3
for ideal transistor amplifier, ∴ IC = = = = 0.01A = 10mA
RE = ∞, then, Ac = 0 RE 430Ω 430Ω

155. If the transistor in the figure is in saturation,
then
1 1
because, X C = = =∞
2πf c 0
So, KVL at collector-Emitter loop
(a) IC is always equal to β dcIB VCC = IC R C + VCE
(b) IC is always equal to –β dcIB 6−3
(c) IC is greater than or equal to βdcIB RC = = 2kΩ
1.5mA
(d) IC is less than or equal to β dcIB IC 1.5mA
GATE-2002 And I B = = = 10µA
β 150
Ans. (d) : βdc = denotes the dc current gain. Apply KVL at base-emitter loop
IE = IB + IC VCC = IBR1+VBE
6 − 0.7
I R1 = = 530kΩ
β= C 10µA
IB
Q Transistor will be changed, then β = 200
∴ KVL apply Base-emitter loop
VCC − VBE
IB =
R1
For transistor in saturation,
6 − 0.7
I
I B ≥ C and VCE = 0 = = 10µA
β 530kΩ
then, IC = βI B = 200 × 10µA = 2mA.
156. In the amplifier circuit shown in the figure, the
Again, KVL apply at common-emitter loop
values of R1 and R2 are such that the transistor
is operating at VCE = 3V and IC = 1.5 mA when VCE = VCC − IC R 2 = 6 − 2 × (2)
its β is 150. For a transistor with β of 200, the = 6 – 4 = 2Volt.
operating point (VCE' IC) is for β = 200, ( VCE , IC ) = ( 2V, 2mA )
157. Assuming VCEsat = 0.2 V and β = 50, the
minimum base current (IB) required to drive
the transistor in the figure to saturation is
(a) (2 V, 2 mA) (b) (3 V, 2 mA)

(c) (4 V, 2 mA) (d) (4 V, 1 mA) (a) 56 µA (b) 140 µA
GATE-2003 (c) 60 µA (d) 3 µA
Ans. (a) : Given, VCE = 3V GATE-2004
IC = 1.5mA Ans. (a) : Given,
β = 150 VCE(Sat ) = 0.2V
Q For D.C. signal (f =0), β = 50
then C act as open circuit, Apply KVL at collector to emitter,

IC
and β (current gain) =
IB
IC IC
IB = = ≅ 0, then IC = 1mA
β Very l arg e
(Q IE = IB + IC , IE = 0 + IC , IE = IC )
Q Apply KVL at collector to emitter,
V − VCE 3 − 0.2 VCE = VCC – ICRC –IERE (IC=IE)
IC = CC = = 2.8mA
RC 1kΩ = 5 –1mA (2.2 + 0.3)
I I 2.8mA = 5– 2.5
β = C then, I B = C = = 56µA = 2.5V
IB β 50
159. For an npn transistor connected as shown in
IC the figure, VBE = 0.7 volts. Given that reverse
Q Saturation condition - IB ≥ satisfy.
β saturation current of the junction at room
temperature 300°K is 10–13 A, the emitter
158. Assuming that the β of the transistor is current is
extremely large and VBE = 0.7 V, IC and VCE in
the circuit shown in the figure are
(a) 30 mA (b) 39 mA
(c) 49 mA (d) 20 mA
GATE-2005
(a) IC = 1 mA, VCE = 4.7 V
Ans. (c) : Given,
(b) IC = 0.5 mA, VCE = 3.75 V
(c) IC = 1 mA, VCE = 2.5 V VBE = 0.7
(d) IC = 0.5 mA, VCE = 3.9 V
GATE-2004
Ans. (c) : Given,
Reverse saturation current

IS = 10–13A (Room temp. At 300ºk)
VT =26mV (T = 300ºk)
 kT 
 Where VT = = 26mV 
β = Very large  q 
Transistor acting as forward bias,
VBE = 0.7V
Q Apply voltage divider point B, I E = IS ( e VBE / ηVT − 1) (where η=1)
5 ×1 5  0.7 
VB = = = 1V = 10−13  e1× 26mV − 1
1+ 4 5
 
Q Apply KVL at base to emitter,
IE = 49mA
I E R E = VB − VBE
160. The circuit using a BJT with β = 50 and VBE
1 − 0.7 = 0.7 V is shown in the figure. The base current
IE = = 1mA
300Ω IB and collector voltage VC are respectively

Ans. (b) : Given,
β = 50
Emitter injection efficiency =0.995
β
Qα =
1+ β
( α = γ*β* )
γ* .β* =
50
51
( γ* = Emitter injection efficiency )
(a) 43 µA and 11.4 volts (b) 40 µA and 16 volts 50
β* = = 0.9852
(c) 45 µA and 11 volts (d) 50 µA and 10 volts 51× 0.995
GATE-2005 (β* = Base transport factor )
Ans. (b) : Given,
162. For the BJT circuit shown, assume that the β of
β = 50, VBE = 0.7V the transistor is very large and VBE = 0.7 V.
Q D.C. signal f = 0 The mode of operation of the BJT is
then C act as open circuit.
IE = IC +IB
= βIB + I B
IE = ( β + 1) IB
(a) cut-off (b) saturation

(c) normal active (d) reverse active
GATE-2007
Ans. (b) : Given,
β = Very large
I IC
IB = C = ≅0
β Very l arg e
Apply KVL at base,
VBE = 0.7V
VCC = IB R1 + VBE + (1 + β) I B R E ( IE = (β + 1)IB )
20 = I B × 430kΩ + 0.7 + 51× I B × 1kΩ
20 − 0.7
IB =
(430 + 51) × 103
19.3
=
481× 103
Q During cut-off region,
= 0.401mA
I B = 0, IC = 0
= 40 µA
Q Condition for saturation I B ≥ I B(min)
I
Q Current gain ( β ) = C ⇒ IC = I Bβ IC ≥ IC(sat)
IB
VCE(sat ) = 0.2V(si) and 0.1(Ge)
IC = 40µA × 50
Step 1→IC(sat)=
IC = 2mA
10 − VCE (sat) 10 − 0.2 9.8
Apply KVL at collector loop, = = mA = 0.891mA
VCE = VCC − R 2 IC (10 + 1) × 103 11× 103 11
Step 2→ IC(expected)
VCE = 20 − 2 ×103 × 2 × 10 −3
2 − VBE(sat ) − IC(exp) × 1× 103 = 0
VCE = 16V
161. The DC current gain (β) of a BJT is 50. 2 − 0.8 − IC(exp) ×103 = 0
Assuming that the emitter injection efficiency is IC(exp) = 1.2mA
0.995, the base transport factor is
(a) 0.980 (b) 0.985 then from step-1 and step-2
(c) 0.990 (d) 0.995 IC(exp ected) > IC(sat )
GATE-2007 So, transistor is in saturation region.

163. A small signal source vi(f) = A cos 20 t + B sin So,
106 t is applied to a transistor amplifier as A Cos 20t is suppressed at output.
shown below. The transistor has β = 150 and hie
And for ω2 = 106 ,
= 3 kΩ. Which expression best approximates
v0(t) ? 1 1
then X C2 = = 6 = 10Ω
ω2 C 10 × 100 × 10−9
X C2 = Very small (act as short circuit).
So,
B sin 106 t will appeared at output.
∴ From equation (i),
V0 (t) = −150Bsin106 t
(a)v0(t) = –1500(A cos 20t + B sin 106t) 164. In the silicon BJT circuit shown below, assume
6 that the emitter area of transistor Q1 is half
(b)v0(t) = –150(A cos 20t + B sin 10 t)
(c)v0(t) = –1500 B sin 106t that of transistor Q2.
(d)v0(t) = –150 B sin 106t
GATE-2009
Ans. (d) : Given,
Vi (f ) = A coas 20t + Bsin106 t
β = 150
hie = 3kΩ
The value of current Io is approximately
Q Ac analysis, CE = 10µF (given) as a short circuit and
emitter resistance can be removed (AC analysis). (a) 0.5 mA (b) 2 mA
Q Common emitter amplifier without RE:(No feedback) (c) 9.3 mA (d) 15 mA
A1 = h fe = −β = −150 GATE-2010
Zi = h ie = 3kΩ Ans. (b) : Given, Assume area (emitter) of transistor Q1
is half that of transistor Q2. It is a current mirror circuit
R 'L in which the output current is a mirror image of the
A V = A1.
Zi input current if both the transistor are identical.
Apply KVL Transistor Q1 (Transistor act as a Diode)

− I1R − VBE = −10
−10 + 0.7
R 'L 3k − I1 = = 1mA
A V = A1 = −150 × = −150 9.3
Zi 3k
I1 = 1mA = Isi e VBE / ηVT .....(i)
V0 (t) = A V Vin (t) = −150[A cos 20t + Bsin106 t] ....(i)
Q I0 = IC2 = I E2 ≅ IS2 .e VBE / ηVT ....(ii)
ω1 = 20
ω2 = 106
I0 = IS2 .eVBE / ηVT = 2ISi e VBE / ηVT = 2I1 = 2 ×1
then,
I0 = 2mA
1  ω
XC = f =  165. The amplifier circuit shown below uses a
2πfc  2 π
silicon transistor. The capacitance CC and CE
for ω1 = 20,
can be assumed to be short at signal frequency
2π 1 and the effect of output resistance r0 can be
X C1 = = = 500000Ω
2π× ω1C 20 ×100 ×10−9 ignored. If CE is disconnected from the circuit,
which one of the following statements is
X C1 = very large TRUE?

Ans. (a) : Given, C1 and C2 are very large and shorts at
V0
the input frequency The gain magnitude at 10 M
Vi
rad/s.
(a) The input resistance Ri increases and the

magnitude of voltage gain Av decreases
(b) The input resistance Ri decreases and the
magnitude of voltage gain Av increases
(c) Both input resistance Ri and the magnitude of Q C1 and C2 act as a short circuit and RE can be
voltage gain Av decrease removed.
(d) Both input resistance Ri and the magnitude of Q AC equivalent,
voltage gain Av increase ZL = ZP || RL
GATE-2010 So, V0 = ic (ZL)
Ans. (a) : Given, CE is disconnected from the circuit.
V0 = −i c [ ZP || R L ] .....(i)
Without considering the emitter capacitor-
Where ZP = Parallel RLC circuit.
Q Voltage across the base-emitter junction,

V ×r 1 1
VBE = s π fr = = rad / sec
R E + rπ 2 LC × π LC
So, VBE is less than the above case where the emitter 1
capacitor is not considered gain is reduced. fr = = 10M rad / s
Input impedance when capacitor is removed, 10 × 10 × 1× 10−9
−6
RB From equation (i)

Ri = .....(i)
R B + rπ V0 = −i c (ZP || R L ) (where ZP will be maximum)
So, Input resistance is increased. V0 = icRL = Maximum output and maximum gain
Therefore, capacitor is not considered then input at resonance frequency.
resistance is increased but gain will be reduced to 167. For the BJT Q1 in the circuit shown below, β =
emitter resistance.
∞, VBEon = 0.7 V, VCEsat = 0.7 V. The switch is
166. In the circuit shown below, capacitors C1 and initially closed. At time t = 0, the switch is
C2 are very large and shorts at the input opened. The time t at which Q1 leaves the active
frequency vi is a small input. The gain
region is
magnitude | v0/vi | at 10 M rad/s is
(a) Maximum (b) Minimum (a) 10 ms (b) 25 ms

(c) Unity (d) Zero (c) 50 ms (d) 100 ms
GATE-2011 GATE-2012
Ans. (c) : Given,
β = ∞, VBEon = 0.7, VCEsat = 0.7V
So, IE = IB +IC = 0+IC

Q When transistor are active region, IE = 1mA.
Apply KVL at Base to emitter loop, Q VE = I E R E = 1× 10 −3 × 500
− VB − VBE − I E R E = −VCC VE = 0.5V
−5 − 0.7 − 4.3k × I E = −10 And VBE +VE = 0.7 + 0.5
VR 2 = 1.2V
10 − 5.7 4.3
IE = = = 1mA From voltage divider rule,
4.3 4.3
R2
We know that, IE = IC + I1 VR 2 = VCC
R1 + R 2
I1 = 1 − 0.5 = 0.5mA
R2
Q When transistor are saturation region, Apply KVL at 1.2 = 3 ×
60k + R 2
collector to emitter loop,
72 + 1.2R2 = 3R2
VCC − VCEsat − IE R E = − VCC
72
VC − 0.7 − 4.3 × 1 = −10 R2 = = 40Ω
1.8
VC = –5V 169. A good current buffer has
Q q = CVC = −5 ×10 −6 × 5V (a) Low input impedance and low output
–6 impedance
= –25×10
(b) Low input impedance and high output
and q = i × t impedance
At time t = 0, the switch is opened, that t = (0–t) upto, (c) High input impedance and low output
I1 (0 − t) − 25 × 10 −6 impedance
(d) High input impedance and high output
−I1 t = −25 ×10−6 impedance
t = 25 ×10 −6 / 0.5 ×10 −3 ⇒ t = 50mSec GATE-2014, Set-I
Punjab PSC Poly. Lect. - 20/08/2017
168. In the circuit shown below, the silicon npn
Ans. (b) : For a good current buffer has-
transistor Q has a very high value of β. The • Unity current gain
required value of R2 in kΩ to produce IC = 1 • Low input impedance, Ideal R = 0
i
mA is • High output Impedance, Ideal R0 = ∞
• Very large voltage gain.
For a good voltage buffer-
• Unity voltage gain.
• Very large current gain
• High input impedance, Ideal, Ri = ∞
• Low output impedance, Ideal, R0 = 0
170. In the circuit shown, the silicon BJT has β = 50.
(a) 20 (b) 30 Assume VBE = 0.7 V and VCE(sat) = 0.2 V. Which
one of the following statements is correct?
(c) 40 (d) 50
GATE-2013
Ans. (c) : Given,
β = Very high then
I B ≅ 0(ignored)
IC =1mA

(a) For RC = 1 kΩ, the BJT operates in the
V0 −g m R i'
saturation region =
(b) For RC = 3 kΩ, the BJT operates in the Vi 1 + g m R E
saturation region V0 −g m R i'
(c) For RC = 20 kΩ, the BJT operates in the cut- A V = = → R E↑→ A V ↓, R i ↑
Vi 1 + g m R E
off region
(d) For RC = 20 kΩ, the BJT operates in the Q R i = βre + (1 + β) R E
linear region AR
GATE-2014 Set-III AV = I L
Ri
Ans. (b) : Given,
⇒ If the emitter is not by passed voltage gain decreases
β = 50 VCE(sat ) = 0.2V and input resistance increases.
VBE = 0.7 172. Consider the common-collector amplifier in the
Assume the transistor is in active region, figure (bias circuitry ensures that the transistor
operates in forward active region, but has been
omitted for simplicity). Let IC be the collector
current, VBE be the base-emitter voltage and VT
be the thermal voltage. Also, gm and ro are the
small-signal trans-conductance and output
resistance of the transistor, respectively. Which
one of the following conditions ensures a nearly
constant small signal voltage gain for a wide
range of values of RE?
Apply KVL in Base to emitter loop,
VB − VBE = IB R B
5 − 0.7 4.3
IB = = × 10−3 = 0.086mA
50kΩ 50
Q Isolator current, IC = β IB = 4.3mA .....(i)
Q Saturation condition, β IB ≥ IC(sat ) .....(ii)
(a) gm RE << 1 (b) IC RE >> VT
Q KVL across CE loop, (c) gm ro >> 1 (d) VBE >> VT
10 − IC(sat ) .R C − VCE(sat ) = 0 GATE-2014 Set-IV
10 − 0.2 9.8 Ans. (b) : Transistor operates in forward bias region,
IC(sat) = = Assume,
RC RC
Assume, (According to option)
9.8
(i) R C = 1kΩ, IC(sat) = = 9.8mA .....(iii)
1KΩ
9.8
(ii) R C = 3kΩ, IC(sat ) = = 3.266 ....(iv)
3
From equation i, ii, iii and (iv),
β IB ≥ IC(sat ) → BJT operate in saturation
gmVbe >>ib
region for R = 3kΩ. Q Voltage gain
171. If the emitter resistance in a common-emitter V g V .R
voltage amplifier is not by passed, it will A V = 0 = m be B
(a) Reduce both the voltage gain and the input V i Vbe + V0
impedance g m R E Vbe
(b) Reduce the voltage gain and increase the AV =
Vbe + g m R e Vbe
input impedance
(c) Increase the voltage gain and reduce the input gmR E
= ≅1
impedance 1 + gm R E
(d) Increase both the voltage gain and the input Q g R >> 1 then
m E
impedance
UPPSC ITI Principal/Asstt. Director-09.01.2022 IC R E
>> 1 [T-model equivalent circuit]
GATE-2014 Set-IV VT
Ans. (b) : If the emitter in a common - emitter voltage
IC R E >> VT
amplifier is not by passed then voltage gain,
173. An increase in the base recombination of a BJT then, capacitor act as a short circuit.
increase
(a) The common emitter dc current gain β
(b) The breakdown voltage BVCEO
(c) The unity-gain cut-off frequency fT
(d) The trans-conductance gm
GATE-2014 Set-II
Ans. (b) : An increase in recombination will cause a
decrease in ICBO which ICEO will decrease.
ICEO = (1 + β) ICBO
But power rating constant so,
Q Emitter current
Break down voltage ↑→ ICEO ↓
10 − 0.7
174. The Ebers-Moll model of a BJT is valid IE = = 0.465mA
20
(a) Only in a active mode
Q Transconductance,
(b) Only in active and saturation modes
I 0.465
(c) Only in active and cut-off modes gm = E = = 17.88mA / V
(d) In active, saturation and cut-off modes VT 26
GATE-2016 Set-II V0
Ans. (d) : It is used for BJT, can be used in forward or Q Voltage gain A V = V = −g m k(R C || R L )
i
reverse active mode of operation, as well as in both
saturation and cut-off mode.  10 × 10 
A V = −17.88mA /×  
Ebers-moll equation for the emitter current  10 + 10 
( )
IE = a11 ( e VE / VT − 1) + a12 e VC / VT − 1 = –17.88×10–3×5×103
= –89.42
kT |AV| = –89.42
Where, VT = (Thermal voltage)
q 176. The load impedance ZL of common emitter
VT =26 mV (Room temperature) amplifier has R and L in series. The phase
175. For the BJT in the amplifier shown below. VBE difference between output and input will be
= 0.7 V, kT/q = 26 mV. Assume the BJT output (a) 180º
resistance (ro) is very high and the base current (b) More than 180º but less than 270º
is negligible. The capacitors are also assumed (c) 0º
to be short circuited at signal frequencies. The (d) More than 90º but less than 180º
input Vi is direct coupled. The low frequency Punjab PSC Poly. Lect. 20.08.2017
gain Vo/Vi of the amplifier is Ans. (b) : The load impedance ZL of common emitter
amplifier has R and L in series. The phase difference
between output and input will be more than 180º but
less than 270º.
177. The self bias is used in amplifiers to
(a) reduce the cost of the circuit
(b) reduce the dc base current
(c) make the operating point almost independent
of β
(d) limit the input ac signal going to the base
(a) –178.85 (b) –256.42 terminal
(c) –128.21 (d) –89.42 TSPSC Manager (Engg.) - 2015
GATE-2020
Ans. (c) : Self bias provides stable IC collector current
Ans. (d) : Given, irrespective of variation in temperature of β.
VBE = 0.7V
178. A biasing circuit has a stability factor of 40. If
kT due to temperature change, ICO changes by 1
VT = 26mV =
q µA. Then IC will change by
BJT output resistance (r0) = Very high (a) 20 µA (b) 40 µA
IB = Negligible. (c) 80 µA (d) 10 µA
for AC analysis, f = ∞ , XC = 0 Nagaland PSC (Degree) 2018, Paper-II

Ans. (b) : Given S =40, Ico = 1µA 181. A given transistor has an α of 0.98. If the
device is connected with its emitter grounded,
∂Ic
Stability factor (s) = What will be the change in the collector current
∂Ico for a change of 0.2mA in the base current ?
∆I c (a) .98mA (b) 9.8mA
∴ 40 =
1µA (c) 98mA (d) .0 98mA
∴ ∆Ic = 40 µA TNPSC AE- 2019
179. What is the thermal runway in a bipolar Ans. (b) : Given,
junction transistor biased in active region due α = 0.98
to? I B = 0.2mA
(a) Heating of the transistor emitter region.
α 0.98
(b) Changes in β which increases with β= = = 49
temperature. 1 − α 1 − 0.98
(c) Base emitter voltage VBE which decreases I
β= C
with rise in temperature. IB
(d) Increase in reverse collector-base saturation IC = βI B = 49 × 0.2
current due to rise in internal device
temperature = 9.8 mA
Nagaland PSC (Degree) 2018, Paper-II 182. A certain transistor has αdc of 0.98 and a
Ans. (d) : Thermal runaway occurs in BJT due to collector leakage current Ico of 1µA. When
increase in reverse collector-base saturation current due IE = 1mA, the collector and base currents will
to rise in internal device temperature. be
180. In the base biased transistor circuit, the (a) Ic = 0.981mA and IB = 0.019mA
junction temperature may vary from 250C to (b) Ic = 0.981µA and IB = 0.019µA
750C. If β increase from 100 to 150 with raising (c) Ic =9.81mA and IB = 0.19mA
temperature, percentage change in VCE point (d) Ic = 9.81µA and IB = 0.19µA
will be TNPSC AE- 2019
Ans. (a) : Given,
αdc = 0.98
Ico= 1 µ A and IE=1mA
Ic = .αIE + ICEO
= 0.98 × 1× 10-3 + 10-6
Ic= .0.98 mA
(a) 40% (b) -44.57% IB = (1-α) IE – ICEO
(c) -46.57% (d) -48%
= (1 – 0.98) 1×10-3 -1×10-6
TNPSC AE- 2019
= 0.02×10-3 – 1×10-6
V − VBE 12 − 0.7 = 20 × 10–6 – 1×10-6
Ans. (b) : I B = CC = = 0.113mA
RB 100 × 10 3
IB = 19×10-6 = 0.019 mA
IC = β IB = 100 × ( 0.113) = 11.3mA 183. The transistor shown in figure in specified to
have β in the range of 50 to 150. Find the vlaue
VCE = VCC − IC R C = 12 − (11.3 × 10−3 × 500 )
of RB that results in saturation with an
= 5.35V overdrive factor of atleast 10.
0
At 75 C
I B = 0.113mA
IC = β IB = 150 × 0.113 = 16.95mA
VCE = 12 − (16.95 × 10−3 × 500 )
= 3.32V (a) 2.2 K Ω
16.75 − 11.3 (b) 3.2 K Ω
∆I C = ×100 = 50% ( Increase )
11.3 (c) 3.4 K Ω
3.52 − 6.35 (d) 2.8 K Ω
∆VCE = × 100 = −44.57% ( decrease )
6.35 TNPSC AE- 2019
Ans. (a) : 187. The circuit shown below is a–
Given,
VC = VCE = 0.2V
(a) Constant voltage source
10 − 0.2
ICSat = (b) Constant current source
1 (c) Common emitter
= 9.8 mA (d) Oscillator
To saturate the transistor with the lowest B, Nagaland PSC CTSE- 2015, Paper-II
I 9.8 Ans. (a) :
I B = Csat = = 0.196mA
βmin 50
For an overdrive factor of 10.
IB = 10× 0.196 = 1.96 mA
5 − 0.7
= 1.96
RB
5K × 5K
4.3 RB = = 2.5 KΩ
RB = = 2.2KΩ 10K 2
1.96
10 × 5K
184. Transistors ratings symbols using capital letter VB = = 5V
and with subscripts also in capital letters 10K 2
denotes Given circuit is common constant voltage source.
(a) DC parameters (b) AC parameters 188. Current stability of a CC amplifier can be
(c) Effective values (d) Time varying increased by
values (a) Reducing both emitter and base resistance
(b) Increasing both emitter and base resistance
Nagaland PSC- 2018, Diploma Paper-II (c) Reducing emitter resistance and increasing
Ans. (a) : DC parameter of transistor always represent base resistance
in capital letter used for DC analysis of transistor. For (d) Increasing emitter resistance and decreasing
ac analysis all parameter represent in small letters. base resistance
185. CC amplifier has (e) Keeping emitter resistance and base
resistance to same value
(a) High Ri and high Ro (b) Low Ri and low Ro
CGPSC SO 14.02.2016
(c) Low Ri and high Ro (d) High Ri and low Ro
Ans. (d) : Current stability factor of CC amplifier
R R E = emitter resistance
Ans. (d) : For common collector amplifier Rin (input S= E
RB R B = base resistance
impedance) ⇒ High
Rout (output impedance) ⇒ Low. If we increase the emitter resistance and decreasing base
resistance current stability factor increased.
186. In class B amplifier, with sinusoidal input
189. Which of the following statements are correct
signal, the output current flows for for basic transistor amplifier configuration?
(a) Half the cycle (a) CB amplifier has low input impedance and a
(b) Full cycle low current gain
(c) Less than half cycle (b) CC amplifier has low output impedance and a
(d) More than half cycle low current gain
(c) CE amplifier has very poor voltage gain but
Nagaland PSC- 2018, Diploma Paper-II very high input impedance
Ans. (a) : In a class a amplifier with a sinusoidal input (d) The current gain of CB amplifier is higher
signal the output current flow for full cycle i.e. 360º than the current gain of CC amplifier
where as class B amplifier with a sinusoidal input (e) CC amplifier has highest voltage gain
signal, the current flow for 180º half cycle. CGPSC SO 14.02.2016
Ans. (a) : The basic transistor amplifier configuration is 192. In the circuit shown below, if RC = 10 kΩ, RL =
common base CB. 10 kΩ, β = 100, input signal voltage is 1mV
r.m.s. The output voltage is:
β
Which has current gain α = very low.
β +1
input impedance Zin = R E || re very low.

190. To set the operating point at 2V, 1mA by
biasing a silicon transistor with collector
feedback resistor RB. If β = 100, the value of
RB is : (a) 100 V (b) 150 V
(c) 250 V (d) 350 V
(e) 200 mV
CGPSC SO 14.02.2016
Ans. (e) : Voltage gain = (RC || RL) β =(10 || 2.5) × 100=
Vo
= 200
Vin
Vo = 200 × Vin = 200 mV
(a) 130 Ω (b) 13 KΩ Vo = 200mV
(c) 130 KΩ (d) 13 Ω 193. When a a.c. signal is applied to an amplifier,
(e) 200 KΩ the operating point ______?
CGPSC SO 14.02.2016 (a) moves along d.c. load line
Ans. (a) : Given, (b) moves along a.c. load line
(c) moves along both d.c. and a.c. load lines
IC = 1mA β = 100 VCE = 2V VBE = 0.7V
(d) does not moves at all
I 1
IB = C = = 0.01 mA (e) shifts along dc load line by peak amplitude of
β 100 a.c. signal
VCE = VBE + VCB CGPSC SO 14.02.2016
2 = 0.7 + VCB VCB = 1.3V Ans. (b) : When an AC signal applied to an amplifier
the output will vary from its dc bias operating voltage
V 1.3 and current the operating point moves along a.c. load
R B = CB = = 130Ω
IB 0.01 line.
194. The main use of an emitter follower is as:
191. In the circuit shown below, β = 60 and input
(a) Amplifier
resistance Rin = 1 kΩ.
(b) Low input impedance circuit
(c) Buffer stage
(d) Follower of base signal
Ans. (c) : Emitter follower is a negative current
feedback circuit.
Emitter follower configuration, also known as common
What is the voltage gain? collector, provides high input impedance and low output
(a) 12 (b) 24 impedance.
(c) 36 (d) 48 So they are used for the purpose of impedance
(e) 60 matching. The main use of an emitter follower is as
CGPSC SO 14.02.2016 buffer stage.
Ans. (b) : Given, 195. In a transistor switch application, the operating
β = 50 Rin = 1kΩ Rc = 2kΩ point moves between following region:
(a) Cut-off and saturation
Vo  R L × R c   0.5 × 2  (b) Cut-off and active
= ×β =   × 60
Vin  R L + R c   0.5 + 2  (c) Active and saturation
Vo = 24

Ans. (a)
→ This configuration is used for impedance matching

i.e. driving a low impedance load from a high
196. From measurement of the rise time of the impedance source.
output pulse of an amplifier whose input is a → This configuration circuit is such less temperature
small amplitude square wave, one can estimate dependent.
the following parameter of the amplifier.
199. The dc current gain in common collector
(a) Gain-bandwidth product
configuration is given by;
(b) Upper-3-dB frequency
(a) β + 1 (b) β
(c) Lower-3-dB frequency
(d) Slew-Rate (c) α + 1 (d) α
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
Gate-1998 Ans. (a) : Common collector configuration, also known
Ans. (b) : as emitter follower provides high input impedance and
low output impedance.
I 1
γ = E = 1+ β =
IB 1– α
200. For a common emitter. BJT configuration with
collector terminal resistance R, the slope of the
D.C. load line can be given by:
(a) 1 (b) R
upper-3-dB frequency can estimate from measurement
(c) 1/R (d) –1/R
of the rise time of the output pulse of an amplifier
whose input is a small amplitude square wave.
Ans. (d) : VCC = IC R L + VCE
197. The CE amplifier circuits are preferred over
CB amplifier circuit because they have: V V
(a) Larger amplification factor ∴ IC = CC – CE
RL RL
(b) Lower amplification factor (i) When
(c) High input resistance and low output
IC = 0 , VCE=VCC
resistance
(d) None of the above Cut-off point A
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I (ii) V
VCE=0, IC= CC
Ans. (a) : CE amplifier- This transistor configuration RL
is probably the most widely used. The circuit provides → Saturation point B
a medium input and output impedance levels. Both Slope of load line AB = –1/RL
current and voltage gain can be described as medium,
but the output is the inverse of the input i.e. 180 0 201. The maximum peak to peak output voltage
phase change. The provides a good overall swing is obtained when Q point of a circuit is
performance and as such it is often thought of as the located:
most widely used configuration or can be said as that (a) Center of the load line
we get a good amplification factor here in CE (b) Near saturation point
amplifier compared to CB amplifier. (c) Near cut off point
198. The following transistor configuration circuit is (d) Any point on the load line
much less temperature dependent: OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
(a) Common base (b) Common emitter Ans. (a) : The Q-point is located at the centre of the
load line. In this condition, we get the maximum
(c) Common collector (d) None of these
possible output signal. The point gives the optimum Q-
point. The maximum undistorted signal= 2 VCEQ .
Ans. (c) : cc configuration- It the Q-point is located near saturation point, The
IE maximum negative swing= VCEQ
γ=
IB 202. The d.c. collector current in a BJT is Ic=1 mA.
If thermal voltage at room temperatures given
1
γ = 1+ β = as 25 mV and β=100, the value of small single
1– α parameter gm is:

(a) 0.4 mA/V (b) 0.04 mA/V 205. If the α value of a transistor changes 0.5%
(c) 4A/V (d) 40 mA/V from its nominal value of 0.9, the % change in
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I β will be
Ans. (d) : IC=1 mA (a) 0% (b) 2.5%
VT=25 mV (c) 5% (d) 7.5%
β=100 Sikkim PSC SI (Mains)-2018
I Ans. (c) : α1 = 0.9
transconductance (gm) = c
VT α 0.9
β1 = 1 = =9
1× 10 –3 1 − α 1 − .9
= Change α 2 = 0.9 × 0.005 +0.9
25 × 10–3
gm = 40 mA/V = 0.0045 + 0.9
α 2 = 0.9045
203. If α for the BJT lies between 0.9 to 0.98, the
corresponding range for β is: α2 0.9045
β2 = = = 9.47
(a) 9 to 98 (b) 9 to 49 1 − α 2 1 − 0.9045
(c) 50 to 100 (d) 90 to 98 β = 9.47
2
β −β
Ans. (b) : Given Change % β = 2 1 ×100
α = 0.90 to 0.98 β1
α 0.90 9.47 − 9
β= = = × 100
1 – α 1 – 0.90 9
0.90 0.47
β= =9 = × 100
0.1 9
0.98 0.98 β = 5.2%
β= = = 49
1 – 0.98 0.02 206. In the case of small BJT model with common
204. The amplifier circuit shown below uses a emitter, the collector current ic is 1.3 mA, when
silicon transistor. The capacitors CC and CE the collector-emitter voltage is Vce of 2.6 V. The
can be assumed to be short at signal frequency output conductance of the circuit is.
and the effect of output resistance r0 can be (a) 2.0 mΩ (b) 2.0 m
ignored. If CE is disconnected from the circuit, (c) 0.5 mΩ (d) 0.5 m
which one of the following statements is Sikkim PSC SI (Mains)-2018
TRUE? Ans. (d) : The conductance of an amplifier is defined as
the ratio of the collector to emitter voltage to the
collector current of the BJT, i.e.
I
g0 = c
Vce
Ic = Collector current
Vce = Collector to emitter voltage
(a) The input resistance Ri increases and voltage 1.3
gain Ai decreases g0 = = 0.5m℧
2.6
(b) The input resistance Ri decreases and voltage
gain Ai increases 207. In the case of BJT amplifier, bias stability is
achieved by
(c) Both input resistance Ri and voltage gain Av
(a) Keeping the base current constant
decreases
(b) Charging the base current in order to keep IC
(d) Both input resistance Ri and voltage gain Av
and VCE constant
increases
(c) Keeping the temperature constant
NIELIT Scientists- 2017
(d) Keeping the temperature of base current
Ans. (a) : Input Resistance- constant
rin = RB β re Nagaland PSC CTSE (Degree)-2017, Paper-II
rin ≈ βre Ans. (d) : The stabilization of operating point is very
Voltage gain, important to get the distortion free out. It is possible to
r –
r –
r – get stabilized operating point by keeping the temperature
Av = β ⋅ 0– = β 0 = 0 and base current so, stabilization can be achieved by
rin βre re keeping temperature and base current constant.
208. The voltage divider bias circuit is used in 211. The transistor in the circuit of the given figure
amplifiers quit often because it is operating
(a) Limits the ac signal going to the base
(b) Makes the operating point almost independent
of β
(c) Reduce the dc base current
(d) Reduces the cost of the circuit
Ans. (b) : The voltage divider bias circuit is used in
amplifiers quite often because it makes the operating
point almost independent of β. (a) In the cut-off region
(b) In the active region
209. In voltage amplifiers the load resistance should
be (c) In the saturation region
(a) As large as possible (d) Either in the active or the saturation region
(b) As small as possible Nagaland PSC CTSE (Degree)-2017, Paper-II
(c) Equal to output impedance Ans. (c) :
(d) Equal to input impedance
Ans. (a) : • A voltage amplifier is any simple circuit
that produces a large voltage at its output and also that
amount of power coming out from the circuit.
• In a voltage amplifier the load resistance should be as
a large as possible.
210. In the amplifier circuit shown in the figure, the
values of R1 and R2 are such that the transistor Assume, VCE = 0.2V, hFE= β = 30
is operating at VCE = 3V and IC = 1.5 mA when Apply KVL at the collector side,
its β is 150. For a transistor with β of 200, the
5 − 0.2
operating point (VCE, IC) is IC = = 0.96mA
5
I 0.96
Q IB = C = = 0.032mA …………….(i)
β 30
5 − 0.7 4.3
| IB |= = = 0.043mA …………..(ii)
100k 100k
(a) (2 V, 2 mA) (b) (3 V, 2 mA) From equation (i) and (ii)
(c) (4 V, 2 mA) (d) (2 V, 1 mA) 0.043 > 0.032mA
Nagaland PSC CTSE (Degree)-2017, Paper-II IC
Ans. (a) : We know that, Given that, VCC = 6V IB >
β
VCC = IC R C + VCE ∵ RC = R 2 VCE = 3 Hence, transistor is in the saturation region.
6 = 1.5 × R 2 + 3 IC = 1.5mA 212. In common emitter BJT amplifier, the
R 2 = 2kΩ β = 150 maximum usable supply voltage is limited by
(a) Avalanche breakdown of Base-Emitter
IC 1.5
IB = = = 0.01mA junction
β 150
(b) Collector-Base breakdown voltage with
When β = 200 emitter open (BVCBO)
Now (c) Collector-Emitter breakdown voltage with
IC = β × I B base open (BVCBO)
= 200 × 0.01 (d) Zener breakdown voltage of the Emitter–Base
IC = 2mA junction
VCC = IC R 2 + VCE Nagaland PSC CTSE (Degree)-2017, Paper-II
6 = 2 × 2 + VCE Ans. (c) : In common emitter BJT amplifier the
maximum usable supply voltage is limited by collector-
VCE = 2V emitter breakdown voltage with base open (BVCBO).

213. In a common emitter amplifier, the un
bypassed emitter resistance provides
(a) Voltage shunt feedback
(b) Current series feedback
(c) Negative voltage feedback
(d) Positive current feedback
Ans. (c) : In a common emitter unbypassed resister
provides negative voltage feedback.
(a) Impedance matching
I ref I ref
(b) Wideband voltage amplification (a) (b)
 (1 + N)   N 
(c) Power amplification  1 + β(β + 1)   1 + β(β + 1) 
(d) Reducing distortion    
Nagaland PSC CTSE (Degree)-2017, Paper-II βI ref βI ref
(c) (d)
 (1 + N)   N 
 1 + β(β + 1)   1 + β(β + 1) 
Ans. (a) :
   
ISRO Scientist- May, 2017
Ans. (a) : For given figure,
Q R ,Q1 ,Q 2 ......Q N have perfectly equal VBE
I ref = IC +
( N + 1) I B
( β + 1)
 N +1 
I ref = I B  β + 
 β +1 
I ref
IB =
 N +1 
A Darlington pair configuration has high input β + 
impedance and low output impedance so, it is mainly  β +1 
used for impedance matching. Q I0 = βIB
215. IB=10mA, ICEO=150 µA, ICBO= 5µA Find β βI ref
∴ I0 =
(a) 29 (b) 30  N +1 
β + 
(c) 50 (d) 40  β +1 
AAI-2015 I ref
Ans. (a) : ICEO = Reverse leakage current in the or I0 =  N +1 
1 + 
common emitter configuration of BJT when the base is
 β (β + 1) 
open.
ICBO = Reverse leakage current in the common base 217. Match the following :
1. Rectifier a. Power electronics,
configuration of BJT when the emitter is open.
Motor speed control,
Battery charging,
Given that ICBO = 5µA ICEO = 150µA Phase control
from ICEO = (1 + β ) ICBO 2. Transistor b. Rectifiers, Wave
clipper circuits
150 = 5 (1 + β ) 3. SCR c. Amplifier, Switches
So, β = 30 − 1 (a) 1-a, 2-c, 3-b (b) 1-b, 2-a, 3-c
(c) 1-b, 2-c, 3-a (d) 1-c, 2-a, 3-b
β = 29
216. All transistor in the N output current mirror in Ans. (c) : Diode- rectifier, wave clipper
the figure are matched with a finite gain β and Transistor- Amplifiers , switches
early voltage VA = ∞. The expression for load SCR- power electronics, motor speed control, battery
current is charging, phase control.

218. In a NPN transistor, if the base current is 100 (a) 3 µA (b) 56 µA
µA and the current gain, β = 200, the collector (c) 60 µA (d) 140 µA
current will be: BPSC Polytechnic Lecturer-2014
(a) 2 mA (b) 100 mA Ans. (b) :
(c) 10 mA (d) 20 mA
UPPCL AE-05.11.2019
Ans. (d) : For NPN transistor-
IC = β ⋅ I B
IC = 100 ×10 −6 × 200
IC = 20000 × 10−6
VCEsat = 0.2V, β = 50
IC = 20 × 10−3
IB = ?
IC = 20mA
3 − IC − 0.2 = 0
219. Calculate the value of IE for a BJT with I = 2.8 mA
C
α dc = 0.99 and I B = 0.99.
IC = β IB
(a) 8.0 mA (b) 5.0 mA
(c) 4.0 mA (d) 9.9 mA 2.8mA
IB = = 56µA
UPPCL AE-05.11.2019 50
Ans. (c) : For a transistor 222. An npn transistor operated at lc=5mA has a
I E = IB + IC ∵ IC = βI B collector load resistor of 2 kΩ and its emitter is
grounded. The voltage gain of this stage is
I E = IB + βI B about. Where VT = 25 mV(npn)
I E = IB (1 + β ) (a) 100 (b) 400
Given that α = 0.99, I B = 40µA (c) 25 (d) 10
0.99
β= = 99 Ans. (b) : Given,
1 − 0.99 IC = 5mA, R L = 2kΩ
I E = ( 99 + 1) × 40µA
VT = 25mV
I E = 4mA I R
Voltage gain = C L
220. Calculate the value of IE for a transistor that VT
has α dc = 0.98 and I B = 100µA.
5 × 10−3 × 2 × 103
(a) 5.0 mA (b) 4.8 mA Voltage gain =
(c) 4.9 mA (d) 6.4 mA 25 × 10−3
Voltage gain = 400
UPPCL AE-05.11.2019
223. For the circuit shown in the below figure, by
Ans. (a) : Given,
assuming β = 100 and VBE = 0.7 V, the best
α 0.98 approximation for the collector current Ic in
α = 0.98 β= =
1-α 1 − 0.98 the active region is
0.98
β= = 49
0.02
I E = (1 + β ) ⋅ I B
I E = 50 × 100µA
I E = 5mA
(a) 2.5 mA (b) 3 mA
221. Assuming VCEsat = 0.2V and β = 50 , the (c) 5 mA (d) 3.5 mA
minimum base current ( I B ) required to drive RRB SSE 02.09.2015, Shift-II
the transistor shown in the figure below to Ans. (a) : Apply KVL base to emitter,
saturation is −12 + IB ×10k + 0.7 + 450 × (1 + β ) IB = 0

−11.3 + I B10k + 450I B = 0 12 − 0.7 11.3 11.3 ×10
Ans. (c) : I B = = = = 113 × 10−6
46.450kIB = 11.3 100 × 103 105 105 × 10
= 113 µA
11.3
IB = = 0.024327mA 227. For the silicon transistor shown in the figure
46.45 × 103
IC = 100 × 0.0243 below, the value of IB is
2.53mA
224. A microphone is connected between the base
and the ground of a BJT. A 1kΩ resistance is
connected between the collector VCC. If
Is = 6 ×10–16 A and the peak value of the
microphone signal is 20mV, what is the peak
value of the output signal?
(a) 1.29 ×10–16V (b) 1.29 ×10–6V (a) 26.47 µA (b) 52.94 µA
–12
(c) 1.29 ×10 V (d) 1.29 × 10–14V (c) 13.235 µA (d) 30.11 µA
UPMRC AM - 2020 ISRO Scientist December, 2017
Ans. (c) : Given, Is = 6 × 10−16 A, R C = 1kΩ Ans. (d) :
VBE = 20mV, VT = 26mV

Q In BJT collector current,
IC = ISe VBE / VT
 20×10−3 
 
−16  26×10 
−3
= 6 × 10 e
= 6 × 2.158 × 10−16 Given, VEE = −8V, VCC = 10V
= 1.29 × 10 −15 kVL in base to emitter loop,
Q peak output voltage, − VBE − I E R E + VEE = 0
Vo = IC R C
−0.7 − ( 2.4 ×103 × IE ) + 8 = 0
Vo = 1.29 × 10 −15 × 103
7.3
Vo = 1.295 ×10 −12 V IE = = 3.042 mA
2.4 × 103
225. A transistor has a base current of 200 μA and We know that,
a collector current of 50 mA. Find its β. I E = IB + IC
(a) 200 (b) 150 I E = IB + βI B
(c) 500 (d) 250 −3
NLC GET -24.11.2020 I B = I E = 3.042 × 10 = 30.11µA
Ans. (d) : Given IC = 50mA, I B = 200µA 1+ β 100 + 1
228. As compared to a BJT amplifier, an amplifier
I 50 × 10−3 made using a JEET is likely to have
β= C =
I B 200 × 10−6 (a) very high voltage gain
1000 (b) very high bandwidth
β= = 250 (c) very high voltage swing
4
(d) very high input resistance
226. Determine the base current of the amplifier by
taking the base-emitter junction voltage into BSNL (JTO)-2001
account. Ans. (d) : As compared to a BJT amplifier, an amplifier
made using a JEET is likely to have very high input
resistance.
229. The voltage gain of a common emitter
amplifier is
(a) directly proportional to collector bias current
(b) inversely proportional to collector bias
current
(c) independent of collector bias current
(a) 113 mA (b) 213 µA (d) proportional to square of collector bias
(c) 113 µA (d) 313 µA current
NLC GET -24.11.2020 BSNL (JTO)-2001
Ans. (a) : We know that (a) 2.73 Ω (b) 6.83 Ω
V −I R (c) 17 Ω (d) 22.5 Ω
Av = 0 = C L BSNL(JTO)-2009
Vi Vi
Ans. (a) : Given, VCC = 100, β = 9, VCE(sat ) = 1V
So, A v ∝ IC
230. In the circuit shown in figure below, β is the VBE(sat ) = 1.5V
same for both the BJTs. VCC − IC R C − VCE(sat ) = 0
100 − IC × 10 − 1 = 0
10IC = 99
IC = 9.9
IC = βI B
IC 9.9
IB = =
β 9
I2 Q Over drive factor = 2.5
Neglecting early effect, is : 9.9
I1 So, IB = × 2.5 = 2.75A
9
1+ β 1
(a) (b) Now, Vi − IB R B − VBE(sat ) = 0
2 1+ β
9 − 2.75R B − 1.5 = 0
1+ β β
(c) (d) 2.75R B = 7.5
2+β 2+β
BSNL JTO-2009, 2006 R = 7.5 = 2.73Ω
B
DRDO-2009 2.75
Ans. (d) : Q β is same for both BJT because both are 232. For the circuit shown in figure, the transistor
identical transistor. parameters are VBE = 0.7 V , β = 99. If VC is to
Suppose collector current of transistor Q1 is IC1 , be set at 7.5 V, the required value (in kΩ) of RB
is
So IC1 = I 2 (Q β same for both transistor )
IC1 I 2
I1 = IC1 + +
β β
I I
Or I L = I 2 + 2 + 2 (QIC1 = I 2 )
β β
2I2  2
I1 = I2 + = I 2 1 + 
β  β
(a) 172 (b) 136
β+2
I1 =   I2 (c) 100 (d) 82
 β  BSNL(JTO)-2009
I2 β Ans. (a) :
= → [known as current mirror]
I1 β + 2
231. For the power transistor circuit shown in
figure, VCE(sat) = 1.0 V, VBE(sat) = 1.5 V and β=9.
With an overdrive factor of 2.5, the required
resistance RB for saturation is
given VBE = 0.7

β = 99
VC = 7.5V
10 − 7.5
IC =
1k
IC = 2.5 mA

IC = βI B 236. Determine the change in collector current,
∆I C due to change in base emitter voltage VBE
2.5 mA
IB = from 25°C to 100°C for a Silicon Transistor in
99 Fixed Bias Configuration having β = 100.
I B = 25 µA
(Consider following variation in Silicon
I E = IC + I B transistor parameters with temperature-At
I E = 2.5mA + 25 µA T=25°C, VBE =0.65 V and At T= 100°C. VBE =
0.5V)
I E = 2.5 + 0.025
I E = 2.525 mA
kVL in collector to base loop-
VC − R B I B − 0.7 − IE ×1kΩ = 0
7.5 − R B × 25µA − 2.5 = 0.7
4.3 = R B × 25µA
4.3
RB =
25 × 10−6 (a) 60µA (b) 30µA
R B = 172 kΩ
(c) 15µA (d) 120µA
233. An NPN Bipolar Transistor with a current gain ISRO Scientist Engg.-2018
of 100 is biased in saturation mode. If the base
Ans.(a):
current is increased by ∆Ib, then :
(a) ∆IC > 100∆Ib (b) ∆IC = 100∆Ib
(c) ∆IC < 100∆Ib (d) ∆IC = ∆Ib
BSNL(JTO)-2002
Ans. (c) : In saturation mode h fe I B ≥ Ics .
So, ∆IC < 100∆Ib.
234. Let β be the short-circuit common-emitter
current gain of a BJT biased in normal active
mode. Let IC be the collector current. Is this β: Given,
(a) a monotonically increasing function of IC? At T = 25ºC, VBE = 0.65V
(b) a monotonically decreasing function of IC? And At T = 100ºC,
(c) Initially an increasing function of IC, which VBE = 0.5V
reaches a plateau and then decreases with β = 100
increasing IC? KVL Apply at input terminal
(d) Independent of IC? VCC = IBRB+VBE
BSNL(JTO)-2002 V − VBE
I B = CC
Ans. (c) : At low injection levels β is degraded by poor RB
emitter injection efficiency. At high currents, β So,
decreases due to excess majority charge in the base. At T = 25ºC,
235. A BJT has α = 0.99, I B = 25 µA and 10 − 0.65
IB =
I CBO = 200nA. The collector current is 250kΩ
(a) Ic = 2.5 mA (b) Ic = 1.5 mA 9.35
= mA
250
(c) Ic = 3.5 mA (d) Ic = 4.5 mA
BSNL (JTO)-2006
( Where, IC = β IB )
α 0.99 9.35
Ans. (a) : β = = = 99 IC1 = 100 ×
1 − α 1 − 0.99 250
IC = βI B + ICEO = 3.74mA
10 − 0.5
= βIB + (1 + β ) ICBO IC2 = 100 ×
250kΩ
= 99 × 25 × 10 −6 + 100 × 200 × 10 −9 = 3.80mA
= 10−6 ( 99 × 25 + 10 × 200 × 10−3 ) So, Change in collector current,
2.5mA ∆IC = IC2 − IC1 = 0.06mA = 60µA

237. Common-base current gain of a p-n-p bipolar 239. Which one plot gives the closest resemblance to
transistor is 0.99. The common emitter current the stability factor S(ICO) of emitter bias
gain of the transistor is: R
configuration of BJT with respect to E ? (RE
(a) 101 (b) 0.01 RB
(c) 99 (d) 1.0 is emitter resistance and RB is base resistance)
Ans. (c) : Given : α = 0.99 , β = ?
α
β=
1− α (a)
0.99
= = 99
1 − 0.99
238. A BJT is having common emitter current gain
100. Considering 10V supply and VBE = 0.7V
what will be the value of RC and RB to set the
quiescent point at IC = 10 mA and VCE = 8V? (b)
(c)
(a) RC = 200Ω , RB = 93 kΩ
(b) RC = 2 kΩ, RB = 100 kΩ
(c) RB = 83 kΩ, RC = 100Ω
(d) RC = 20Ω, RB = 93 kΩ (d)
Ans. (a) :
Ans. (b) : For saturation region
VCC
IC (sat) =
RE + RL
β=100, IC = 10mA, VCE = 8V

Applying KVL output circuit,
10–IC RC – VCE = 0
10 − 8
RC =
10 × 10−3
= 200Ω
KVL apply at the input circuit,
10 – IBRB – VBE = 0 Apply KVL
10mA − IB R B − VBE − I E R E + VCC = 0
IB = IC /β =
100 Q I E = IB + IC
= 0.1 mA − IB R B − VBE − ( I B + IC ) R E + VCC = 0
10 − 0.7
RB = − IB ( R B + R E ) − VBE − IC R E + VCC = 0
0.1×10−3
= 93 kΩ Where I B = IC / β, I E = IC

IC R B Ans. (a) :
VCC = + VBE + IC R E
β
Q Stability factor,
1+ β
S= .......(i)
dI
1− β B
dIC
VCC − VBE − IC R E
Q IB =
RB + RE
dI B −R E
= ....(ii)
dIC R B + R E | VA |
r0 = ( VA = early voltage )
IC
1+ β
S= 50 ×103 =
50
βR E
1+ IC
RB + RE
IC = 1mA
If RE = 0, then S = 1+β Note- Increase IC with a increase VCE is called 'Early
R effect'.
If RE >> RB then E → Very large
RB 241. If an emitter follower has VCEO = 6V,
ICQ =200mA, and re= 10Ω, the maximum peak
to peak unclipped output is
(a) 2V (b) 4V
(c) 6V (d) 8V
Ans. (b) : For an emitter follower effect given that,
VCEO = 6V, ICQ =200mA, and re= 10Ω, the maximum
peak to peak unclipped output 2 × (ICQ × re)
=2×2
= 4V
then, 242. In the circuit shown V1=2.7 V, VBE = 0.7V and
 RE  β >> 1. the gm of the transistor is
(1 + β ) 1 + 
 R B 
Stability factor (S) =
R
1 + (1 + β) E
RB
 RE 
S ≅1  >> 1
R
 B 
240. Output characteristics of a BJT amplifier is
given. Find the minimum collector current (a) 200 m mho (b) 400 m mho
required for r0 = 50 kΩ. (r0 is output (c) 200 ohms (d) 400 ohms
resistance)
Ans. (b) :
(a) 1 mA (b) 5 mA
(c) 10 mA (d) 100 mA
Applying KVL at input side Ans. (d) :
2
⇒ IE = = 0.01A = Ie
200
I 0.01
So, gm = e = = 0.4 = 400 mA/V
VT 25 × 10−3
= 400 m mho Apply KVL, –10 + ΙB × 106 + 0.7 = 0
243. The value of Rb required to drive the transistor 9.3
in the circuit below into saturation is IB = 6
10
IB = 9.3 µA
245. The self bias provides
(a) stable Q point
(b) large voltage gain
(c) high input impedance
(d) high base current
Ans. (a) : Voltage divider bias or self bias-
(a) 1 kΩ (b) 110KΩ
(c) 20 KΩ (d) 30 KΩ
Ans. (c) : Transistor in saturation mode.
VCE = 0, IC = max
VCC 10
IC(sat ) = = = 10mA
R C 1kΩ
IC(sat ) 10mA
IB = = = 500 µA
βDC 20 R1R 2
R in = R B =
This is the value IB necessary to drive the transistor to R1 + R 2
the point of saturation. Any further increase in IB will
R 2 VCC
drive the transistor deeper into saturation but will not Vin =
increases IC. when the transistor is on, VBE = 0.7V the R1 + R 2
voltage across RB is VCE = VCC − IC (R E + R C )
VRB = Vin − VBE = 10 − 0.7 = 9.3V So, operating point not depend upon β. In this kind of
The value of RB needed to allow a IB of 500 µA is- biasing, IC is resistant to the changes in both β as well
as VBE, which results in a stability.
VRB 9.3
RB = = = 0.0186 × 106 246. The configuration of the transistor in the
IB 500 ×10−6
circuit shown is
R B = 18.6 kΩ
RB 20 kΩ
244. In figure what is the base current if VBE = 0.7
V?
(a) 10 µA (b) 10 mA (a) CB (b) CE

(c) 4 mA (d) 9.3 µA (c) CC (d) Both CC and CE
Mizoram PSC Jr. Grade-2015, Paper-II Mizoram PSC IOLM-2010, Paper-II

Ans. (b)  
(a) 2 log10  V2 R 1 
 V1 R 2 
 
(b) log10  V2 R 1 
 V1 R 2 
 
(c) 2.3 log10  V2 R 1 
V R
 1 2
 
(d) 4.6 log10  V2 R 1 
Such a common – emitter or grounded – emitter V R
 1 2
configuration
247. Voltage gain of BJT amplifier is
(a) AIRL (b) AI (Ri/RL) Ans. (b) : Given that,
(c) A (RL/Ri) (d) none of these β >> 1
Mizoram PSC AE/SDO 2012-Paper-I VT = 0.026V
Ans. (c) : The voltage gain for BJT
for Transistor Q1 :
RL
A V = A. V
Ri IC1 = 1
R1
248. The cascade amplifier is a multistage IC
configuration of VBE1 = VT ℓn 1
(a) CC-CB (b) CE-CB IS
(c) CB-CC (d) CE-CC for transistor Q 2 :
V
Ans. (d) : CE–CC→ Cascade connection I C2 = 2
R2
CE-CB→ Cascode connection
CC-CC→ Darlington pair IC
VBE 2 = VT ℓn 2
The voltage gain of amplifier can be increased by IS
using cascading connection of individual stages.
output voltage ⇒
The cascade connection is used to obtain high
current gain. 333  V2 R 1 
In a cascade amplifier, the overall gain is equal to V0 = 20 × VT ℓn  R × V 
 2 1 
product of gain of individual amplifier.
For n-amplifier in cascade connection overall 333 V R  V R 
bandwidth will be- = × 0.026ℓn  2 × 1  ≃ log10  2 × 1 
20 R
 2 V1   R 2 V1 
= fH ( 2) − 1
1/ n
250. The gain of a single stage BJT amplifier in the
249. Transistors Q1 and Q2 are identical and β >> 1 Emitter follower configuration, when
in the circuit shown in the figure below. The R c = 22kΩ and R E = 2.2kΩ is:
output voltage is (VT = 0.026 V)
(a) 8.0
(b) 10.0
(c) 5.0
(d) 100.0
UPPCL AE-05.11.2019
Ans. (b) : For emitter follower circuit-
RC
Gain =
RE
22
AV =
2.2
A V = 10

4. The hybrid-pi model is used for:
(iii) Frequency response of BJT (a) analysis of BJT for feedback
amplifiers (b) analysis of BJT for large signal
(c) analysis of BJT at low frequency
(d) analysis of BJT at high frequency
1. For the equivalent circuit of a CE amplifier
shown, lower cut off frequency will be Mizoram PSC AE/SDO 2012-Paper-I
Ans. (d) : There are two types of model is used in high
frequency.
(i) Hybrid π-model
(ii) Hybrid T-model
5. The resistance rbb' in the hybrid-pi model is
know as .
b (a) base part resistance
1 1 (b) base speeding resistance
(a) (b)
2πR s C 2πR1C (c) base portion resistance
(d) base spreading resistance
1 1 UPRVUNL AE -19.07.2021, Shift-II
(c) (d)
2π ( R s + R i ) C  RsRi  Ans. (d) : The resistance rbb’ in the hybrid-pi model is
2π  C
 s
R + R i 
know as base spreading resistance, which acts as a
feedback network for the flow of minority carrier
UPPSC ITI Principal/Asstt. Director-09.01.2022 current form emitter to collector.
Ans. (c) : 6. For a transistor, gm = / V T.
(a) IB (b) IE
(c) IC (d) VCE
Ans. (c) : gm is the reciprocal of the emitter impedance
VT IC
Re which is , i.e. g m =
Ic VT
1
Lower cut off frequency fc = 7. If rb'e= 1000 ohms and rbb' = 100 ohms for the
2π ( R S + R i ) C hybrid pi-model, what is the value of hie?
2. The coupling capacitor used in CE amplifier (a) 10 ohms (b) 1000000 ohms
(c) 1100 ohms (d) 900 ohms
offers reactance in mid and high
frequency region.
Ans. (c) : hybrid Pi model, hie = rb'e + rbb'
(a) high (b) low
= 1000Ω + 100Ω
(c) very high (d) medium
= 1100Ω
UPRVUNL AE -19.07.2021, Shift-II hie = 1100Ω
Ans. (b) : In practical coupling capacitor are large 8. In a hybrid π model, which terminal is NOT
capacitor (µF) because they should offer low accessible?
(negligible) reactance at frequency of AC input. (a) Emitter (b) Collector
3. If 3 amplifiers are connected in cascade and fL (c) Induced base (d) Virtual base
of each is 120 Hz, then fL of cascaded amplifiers UPRVUNL AE -19.07.2021, Shift-II
is: Ans. (d) : hybrid π model is only used for BJT and in
BJT, there are three terminals i.e Emitter, Collector &
(a) 59.98 Hz (b) 253.43 Hz
Base (Induced). It is also called Giacoletto model.
(c) 235.37 Hz (d) 254.33 Hz ∴ Virtual base is not accessible
UPRVUNL AE -19.07.2021, Shift-II 9. An amplifier has midband gain of 100 a lower
Ans. (c) : Given, N = 3 3dB frequency 23Hz. What is the value of
fL of cascaded amplifier frequency at which gain is 99?
(a) 161.41 Hz (b) 2.37 kHz
fL 120
= = (c) 166.89 Hz (d) 19.87 Hz
2 −1
1/ N
21/ 3 − 1 UPRVUNL AE -19.07.2021, Shift-II
120 Ans. (a) : Given-
= = 235.37 Hz
0.5098 A mid = 100, f L = 23Hz, A LF = 99, f = ?

Ans. (b) : In multistage amplifier, there are two types
A mid amplifier i.e. Darlington & Cascade amplifier. In
A LF =
2 Darlington amplifier-
f 
1+  L  rπ + (1 + β1 )rπ 2
f  R 0 = R E ||
(1 + β2 )(1 + β1 )
100
99 = R0 = output Resistance of final stage in Cascade
2
 23  amplifier
1+   R0 = RC = output resistance of final stage.
 f 
2
12. What is the formula of lower cut-off frequency
100  23  of an RC coupled amplifier?
= 1+  
99  f  1 π
(a) f L = (b) f L =
 100 
2
 23 
2 2πRC 2RC
  −1 =   R C
 99   f  (c) f L = (d) f L =
2
2πC 2 πR
1 199  23  UPRVUNL AE -19.07.2021, Shift-II
× = 
99 99  f  Ans. (a) : Voltage gain at low frequencies
199 23 V A vm
= A VL = O =
V 1
99 f I 1 − ω×
14.106 23 CC (R C + R L )
= 1
99 f ∴ ωL =
f = 161.41Hz CC (R C + R L )
10. A transistor amplifier has poles at 1
⇒ fL =
S1 = – 0.00245 × 109 rad/s 2πRC
S2 = – 0.0748 × 109 rad/s (R = RC + RL)
S3 = – 0.670 × 109 rad/s 13. In a single stage amplifier, if hoe = hre = 0, then
S4 = – 4.38 × 109 rad/s output impedance is if Zo=2kΩ||2kΩ.
The upper 3 dB frequency of the amplifier will (a) 2 kΩ (b) infinity
be (c) 1 kΩ (d) 10 kΩ
(a) S1 (b) S1 + S2 + S3 + S4 UPRVUNL AE -19.07.2021, Shift-II
(c) S1+S4 (d) S4 Ans. (c) : If hoe = hre = 0,
IES-1998
Then output impedances Zo = 2kΩ || 2kΩ
Ans. (a) : In a transistor amplifier, when there are many
poles, we consider only the pole which is near the 2× 2
Zo =
origin. 2+2
The nearest pole of the given question is S1. Zo = 1kΩ
S1= –0.00245×109 rad/sec.
Hence, S1 will be the upper 3 dB frequency of the 14. When voltage gain Av is greater than 1, the
amplifier. voltage gain in dB is .
(a) zero (b) positive
(c) negative (d) one
V 
Ans. (b) : Voltage gain in dB = 20 log10  out 
 Vin 
For voltage gain = 1 → dB = 0 dB
voltage gain = 1.1 → dB = 1 dB (positive).
15. For a single stage amplifier, if Ai = – 48.54,
11. The output resistance of a multistage amplifier Ri = 1085.44 ohms and Rs=1k ohms, what is the
is equal to the: value of A?
(a) addition of output resistance of individual (a) – 20 (b) 20
stages (c) – 23.28 (d) 25
(b) output resistance of final stage UPRVUNL AE -19.07.2021, Shift-II
(c) product of output resistances of individual
A .R −48.54 × 1085.44
stages Ans. (c) : A = v i = = −25.26
(d) input resistance of first stage Ri + Rs 1085.44 + 1000
UPRVUNL AE -19.07.2021, Shift-II = –23.28.

16. A BJT has Ce=1pF. If gm is 50 mA/V, calculate
Ans. (c) : In a cascaded amplifier, the transformer
the fT of a common-emitter amplifier. coupling method which is capable of providing the
(a) 20 MHz (b) 80 MHz highest gain. Transformer coupled amplifier are used as
(c) 8 GHz (d) 2 GHz power amplifier to drive high power speaker load.
APPSC POLY. LECT. 14.03.2020 19. An npn transistor has beta cut-off frequency
mA fβ of 1 MHz, and common emitter short circuit
Ans. (c) : Ce = 1 pF gm = 50 low-frequency current gain βo of 200 at unity
V gain frequency fT and the alpha cut-off
g 50 × 10 −3
fT = m = frequency f α to respectively are-

2πCe 2π× 10−12 (a) 200 MHz 201 MHz (b) 200 MHz 199 MHz
= 7.9 GHz (c) 199 MHz 201 MHz (d) 201 MHz 202 MHz
f T = 8 GHz Nagaland PSC CTSE (Degree)-2017, Paper-II
Kerala PSC Lect. (NCA) - 04/07/2017
17. Generally, the gain of a transistor amplifier
falls at high frequencies due to the GATE-1996
(a) Internal capacitances of the device Ans. (a) : fβ = 1MHz β = 200
(b) Coupling capacitor at the input f T = β × fβ f α = (1 + β ) fβ
(c) Skin effect
(d) Coupling capacitor at the output fT = 200 × 1 f α = (1 + 200 ) × 1
GATE – 2020, 2003, IES-2018 f = 200 MHz f α = 201 MHz
T
Nagaland PSC CTSC (Degree)- 2017, Paper-II
GPSC Asstt. Prof.-11.04.2017 20. In a multi-stage RC-coupled amplifier the
TSPSC Manager (Engg.)-2015 coupling capacitor.
Ans. (a) : The current gain of a bipolar transistor drops (a) Limits the low frequency response
at high frequencies because of the transistor (b) Limits the high frequency response
capacitances. (c) Does not effect the frequency response
If frequency will be high then, (d) Blocks the d.c. components without effecting
the frequency response
GPSC Asstt. Prof.-11.04.2017
GATE-1993
Ans. (a) : The low frequency response of an Amplifier
is effected by coupling capacitors and bypass
capacitors.
The high-frequency response of the amplifier is affected
1
XC = or f ↑→ X C ↓ by junction capacitors.
2πfC 21. Input voltage applied to a circuit is 1Vrms and
So, XC will be very small therefore it behaves like a the output is 1mVrms. Net gain of the circuit is:
short circuit. The loading effect of next stage increases, (a) +30dB (b) –30dB
which reduces the voltage gain. It is increases the Ib.
(c) –60dB (d) +60dB
So, current gain are reduces.
Hence, the voltage gain rolls at high frequency.
Internal capacitances of the BJT are Cbc, Cbe, Cce. Ans. (c) : Given that,
For Cce → Shunting effect at high frequency in the Input voltage (Vin) = 1Vrms
output side and reduces the gain of the amplifier. Output voltage (Vout) = 1mV = 10–3Vrms
I V
Current gain ( β ) = C Net gain (G) = 20log out
Vin
I
B
So, IC ↓→ β ↓ 10−3
Net gain (G) = 20log
18. In a cascade amplifier, the coupling method 1
which is capable of providing highest gain is Net gain (G) = –60log1010
(a) RC coupling = –60 dB
(b) Direct coupling 22. For a directional coupler, the quantities
(c) Transformer coupling I (isolation in dB), D (directivity in dB),
(d) Impedance coupling C (coupling in dB) are related by
RRB JE-31.08.2019, 10AM – 12PM (a) I = C/D (b) I = D – C
Nagaland PSC CTSE (Diploma)- 2018, Paper-I (c) I = D + C (d) I = D/C
Nagaland PSC CTSE (Diploma)- 2018, Paper-II ISRO Scientist Engg.-2013
Ans. (c) : Given that, VBE1 = VB − VE
I = Isolation in dB. 0.3V = VB − ( −10 )
D = Directivity
Direction coupler C = Coupling in dB VB = −9.7V
VCE − VB 10 − ( −9.7 )
So, I1 = =
R 20kΩ
P  19.7
Q Coupling = 10log  1  …………..(i) = = 0.985mA
20kΩ
 P3  β of the transistor is very high
P 
Isolation = 10log  1  …………..(ii) So, β =
IC
, ∴ IB = 0
 P4  IB
P  I B1 = I B2 = 0
Directivity = 10log  3  …………..(iv)
 P4  I1 = IC1 = 0.985mA
P P P I = 3.IC1
Therefore, 1 = 1 . 3
P4 P3 P4 = 3 × 0.985mA
= 2.955mA
P  P  P 
10log  1  = 10log  1  + 10log  3  24. Each Transistor in Darlington pair (as shown
 P4   P3   P4  in Fig.) has hfe = 100. Overall hfe of composite
I = C+D transistor neglecting leakage current is,
23. For the current mirror circuit shown below, if
the emitter area of Q2 is thrice of Q1, the
current I is :
(a) 10000 (b) 10001

(c) 10100 (d) 10200
Ans. (d)
(a) 0.328 mA (b) 2.955 mA

(c) 0.105 mA (d) 0.012 mA
Ans. (b)
Q Given transistor (each) in Darlington pair h fe = 100

IC
h fe = and IC = βI B
IB
I E = IC + IB = βI B + I B
= (1 + β ) I B
IC1
For transistor Q1 = h fe1 = = β1
I B1
Given Q2 = 3Q1 I C2
And Q2 = h fe2 = = β2
So, β2 = 3β1 i.e. collector current of ( Q 2 ) is three time I B2
of collector current of Q1 Q h fe = h fe1 = h fe2
Assume, transistor is Ge
IC
So, cut-off For full circuit h fe =
VBE = 0.3V IB

IC = IC1 + IC2 = h fe1 IB1 + h fe2 I B2 26. The following circuit represents the low
frequency model of
I B2 = I E1 = ( β + 1) IB1 = ( h fe + 1) I B1
IC = h fe  IB1 + ( h fe + 1) IB1 
IC = h fe I B1 [1 + h fe + 1]
IC = h fe I B1 [ 2 + h fe ] (I B = IB1 )
IC
= 2h fe + h fe2 = h fe (a) RC coupled amplifier
IB
(b) Phase shift oscillator
h fe = 1002 + 2 ×100 (c) Darlington circuit
h fe = 10200 (d) Single stage common emitter amplifier
TNPSC AE - 2018
25. Find the approximate output impedance of the
Ans. (a) : RC coupled coupling is the most widely used
VCCS (voltage-controlled current source) method of coupling in multistage amplifier. Give circuit
based circuit at port V0. is a multistage connection of amplifier.
27. h-parameter indicating input resistance in a
common emitter circuit is
(a) hfe (b) hre
(c) hoe (d) hie
Ans. (d): h–parameters are one system for
characterizing bipolar transistor. h parameter indicating
input resistance in a common emitter circuit is hie.
28. The lower cut-off frequency of the transistor
(a) 0.01 Ω (b) 100 Ω stage in the adjoining figure is
(c) 100 kΩ (d) 10 MΩ
Ans. (b) :
(a) 7.95 Hz (b) 13.25 Hz

(c) 5.30 Hz (d) 3.18 Hz
BSNL (JTO)-2006
Ans. (c) : Given R1 = 3k , C1 = 1µF
Lower cut-off frequency
1 1
V = –VT fL = = = 5.30 Hz
2πR1C1 2π × 3 × 103 × 10 ×10−6
Apply Nodal at node output-
VT V 29. For a directional coupler the power is in the
IT + g m V = + T ratio of
100KΩ R in (a) 40dB (b) 30dB
 1 1  (c) 20dB (d) 10dB
IT = VT  + + 0.01
 100KΩ 10MΩ  Ans. (c) : For a directional coupler the power is in the
ratio of 20 dB.
VT 10MΩ 10 × 106
=  30. In an amplifier, the coupling capacitors are
IT 100 + 1 + 105 105 employed for
= 100Ω (a) Limiting the bandwidth
VT (b) Matching the impedance
So, Impedance = (c) Controlling the output
IT
(d) Preventing of dc mixing with input or output
= 100Ω Mizoram PSC IOLM -2018, Paper II
Ans. (d) : Coupling capacitors are essential component
The cascode is a two stage amplifier that consist of a
in amplifier circuits, they used to prevent interference of
common-emitter stage feeding in to a common-base
a transistor's bias voltage by AC signals. stage. Cascode have many advantage over single stage
31. Consider the amplifier model shown below amplifier like better output isolation, high input and
output impedance and high bandwidth.
V
The voltage gain 0 of the amplifier is 34. If the value of hfe increases, the
Vs (a) value of input impedance decreases and the
value of current gain increases
(b) values of both the input impedance and the
current gain decrease
(c) values of both the input impedance and the
current gain increase
(a) 150 (b) 50 (d) value of input impedance increases and the
(c) 200 (d) 100 value of current gain decreases
UPPCL AE- 31.12.2018 TNPSC AE-2014
Ans. (c) : Apply voltage division rule- Ans. (a) : β for A.C analysis of the CE circuit (hfe)
1× Vs i2 β ib
Vi = [ Vs = 2Vi ] hfe = = =β
1+1 i1 ib
Apply KCL - If the value of hfe increases, the value of input
V0 V0 impedance decreases and the value of current gain
0.1Vi + + =0
20 × 10 5 ×103
3 increases.
V  1 1 35. The h-parameter model is more commonly
0.1Vi = − 03  +  used because
10  20 5 
(a) h-parameter can be measured more easily
V 1 + 4 
0.1Vi = − 03  (b) h-parameter does not vary with frequency
10  20  (c) the analysis, with h-parameter gives the same
V0 expression for the performance for all
0.1Vi = − configurations
4 × 103
(d) h-parameter model is an accurate
V0 = −4 × 10 2 Vi
representation
V0 4 ×102 Vi TNPSC AE-2013
=−
Vs 2Vi Ans. (a) : The h-parameter model is more commonly
used because h-parameter can be measured more easily.
= 2 × 10 2 = 200 h-parameter can not used for high frequency model.
32. In the Hybrid-pi model for the BJT small 36. In an amplifier the increase in gain is 12 dB if
signal analysis, rπ denotes the frequency is doubled. What will be the gain
(a) Input resistance (b) Trans conductance if frequency is increased 10 times?
(c) Output resistance (d) Trans impedance (a) 20 dB (b) 40 dB
UPPCL AE- 31.12.2018 (c) 2.4 dB (d) 60 dB
Ans. (a) : In BJT small-signal models there are both re MPPSC Forest Service Exam.-2014
and rπ parameter. They both represent the dynamic
resistor between the base and emitter terminals. Ans. (b) : When frequency is double gain K = 12dB
Now when frequency is 10 times increase
33. Which of the following configuration provides
maximum gain bandwidth product? Gain K = 40 dB
(a) Common base amplifier 37. If a CE stage is directly coupled to an emitter
(b) Differential amplifier follower
(c) Cascode amplifier (a) Low and high frequencies will be passed
(d) Cascade amplifier (b) Only high frequencies will be passed
UJVNL AE-2016 (c) High-frequency signal will be blocked
Ans. (c) : (d) Low-frequency signals will be blocked
Ans. (a) : An emitter follower delivers maximum power
to a low impedance load. It acts as a buffer between
input and output. Therefore, if a CE stage is directly
coupled to an emitter follower, there will be maximum
power delivered or all the frequencies from low to high
will be passed.
38. A three stage amplifier with identical stages Double-tuned circuit - A double tuned circuit, which
with lower cut off frequency per stage = f1 is consisting of two magnetically coupled, identical high-
given overall negative feedback Depending on quality factor tuned circuit.
the overall gain, the system may oscillate at a It operated at the same resonant frequency will have the
low frequency fc given by magnitude response always high.
f f 1 Stagger-tuned amplifier -
(a) 1 = 1 (b) 1 = In these two single tuned cascaded amplifiers having
fc fc 3 certain bandwidth are taken and their resonant
f1 f1 1 frequency are so adjusted that they are separated by an
(c) = 3 (d) = amount equal to B.W of each stage.
fc fc 2 41. A CE amplifier has an unbypassed emitter
Nagaland PSC CTSE (Degree)-2016, Paper-II resistance of 0.5 kΩ and a collector load of
Ans. (c) : A three stage amplifier with identical stages 5k Ω. The β of the transistor is 100 and it is
with lower cut off frequency per stage is "f1", then operating at 1 mA. The voltage gain of the
system may oscillate at a low frequency given by stage at mid band will be of the order of
f1 (a) 200 (b) 100
= 3 (c) 10 (d) 50
fc
IES-2011
39. When two identical stages with upper cutoff Ans. (c) : Given R =0.5 kΩ, Rc = 5kΩ
frequency ωH are cascaded, overall cutoff
e
gmR c 1 −R C
frequency is at: Av = = Q R E >>> | A V |=
(a) 1ωH (b) 2ωH 1 + gm R E gm Re
(c) 0.5ωH (d) 0.64ωH 5
AV =
Nagaland PSC CTSE(Degree) - 2016,Paper II 0.5
IES-2013 A V = 10
Ans. (d) : Given that, 42. Which of the following components control the
N=2 high frequency response of the R-C coupled
1 amplifier?
fH = fH × 2 − 1
* N
1. Parasitic capacitances of the transistor
f H* = 0.64f H 2. Coupling capacitance
3. Stray capacitance
40. In order to increase the bandwidth of tuned 4. Wiring capacitance
amplifiers, one can use: Select the correct answer using the code given
1. Tuned circuit with inductance having high below:
Q factor (a) 1 and 2 only (b) 2 and 3 only
2. Double tuned amplifier with two tuned (c) 3 and 4 only (d) 1, 3 and 4
circuits coupled by mutual inductance
IES-2009
3. Staggered tuned amplifiers in which
different tuned circuits which are cascaded Ans. (d) : Parasitic capacitances of the transistor, or
stray capacitance or wiring capacitance components
are tuned to slightly different frequencies
control the high frequency response of the R-C coupled
(a) 1, 2 and 3 (b) 1 and 2 only amplifier.
(c) 2 and 3 only (d) 1 and 3 only RC coupled amplifier of pertaining to frequency
IES-2013 response-
Ans. (c) : The tuned amplifier is capable of amplifying Coupling capacitance effects low frequency
a signal over a narrow band of frequencies centered at response.
By pass capacitance effect low frequency response.
Both statements is correct.
Frequency response curve is graph that indicates and
relationship between voltage gain and function of
frequency.
The quality factor is the ratio of resonant frequency of

band width
fr
Q=
B.W.

43. Consider the following statements: f H = 2.02MHz
Tuned amplifiers
1. are wide band amplifiers BW
fL = f c − = 2MHz − 0.02MHz
2. are used in radio transmitters and receivers 2
3. performance is determined by Q of the circuit f L = 1.98MHz
correct? 46. The two stages of a cascade amplifier have
(a) 1 and 2 only (b) 2 and 3 only individual upper cut-off frequencies f1=5 MHz
(c) 1 and 3 only (d) 1, 2 and 3 and f2=3.33 MHz. What is the best
IES-2009 approximation for the upper cut-off frequency
of the cascade combination?
Ans. (b) : Tuned amplifier are the amplifiers that are
(a) 4.16 MHz (b) 3.33 MHz
employed for the purpose of tuning. Tuning means
selecting among a set of frequency available, if there (c) 2.5 MHz (d) 5.00 MHz
occurs a need to select a particular frequency, the tuned IES-2006
amplifiers are used in ratio transmitters and receivers Ans. (c) : Given that
and performance is determined by Q of the circuit. f1 = 5 MHz and f 2 = 3.33 MHz
44. Which one of the following statements is 1 1 1
correct? = +
The rise time of an amplifier is f UCF f1 f 2
(a) Directly proportional to the upper 3-dB 1 1 1
frequency = +
f UCF 5 3.33
(b) Inversely proportional to the upper 3-dB
1 1
frequency =
(c) Directly proportional to the lower 3-dB f UCF 2
frequency f UCF = 2 MHz
(d) Inversely proportional to the lower 3-dB
frequency Best approximation fUCF = 2.5 MHz
IES-2007 47. A cascaded amplifier comprises N identical
non-interacting stages, each having a lower
Ans. (b) : Rise time of an amplifier is measured with
respect to time, i.e. , 3dB frequency of fL. If fL* is the lower 3 dB
0.35 frequency of the cascaded amplifier, then
tr = which one of the following is correct?
B.W.
1 (a) f L* = f L (b) f L* = f L 21/ N − 1
tr ∝
B.W. fL fL
(c) f L* = (d) f L* =
Since bandwidth is taken to be the upper 3dB cut-off 2 −1 1/ N N
frequency. IES-2012, 2005
Hence Bandwidth ≈ higher cut off frequency.
Ans. (c) : N-identical non-interacting amplifiers are
45. A tuned amplifier has peak output at 2 MHz cascaded and each amplifier has an individual cut-off
and quality factor 50. The bandwidth and 3-dB frequency f L1 & FH1 then the overall cut-off frequency of
frequencies shall be at what values
respectively? the cascaded amplifier will be -
(a) 40 kHz, 2.02 MHz, 1.98 MHz f L1
(b) 40 kHz, 2.04 MHz, 1.96 MHz f L* =
1
(c) 80 kHz, 2.04 MHz, 1.96 MHz 2 N −1
(d) 80 kHz, 2.08 MHz, 1.92 MHz 1
f H* = f H1 × 2 N
−1
Sikkim PSC SI (Mains)-2018
IES-2014, 2011, 2007 1
for 2 N − 1 < 1
Ans. (a) : Given that, fc = 2 MHz
Note - Cascading increases lower cut-off and decreases
Q = 50
higher cut-off frequency hence bandwidth decreases.
f 2 × 106
B.W = c = = 40 kHz 48. A transistor RC coupled amplifier is designed
Q 50 for a voltage and band gain of 20. But a
Upper and lower 3 db frequency will be respectively- measurement at a particular frequency shows
BW the gain to be only 14.What is the likely phase
fH = fc + shift at this frequency?
2 (a) 180º (b) 135º
40kHz (c) 90º (d) 45º
f H = 2MHz + = 2MHz + 0.02MHz
2 IES-2005
Ans. (b) : Given, 51. Which one of the following statements is
A0 = 20 correct?
A = 14 If in a doubled-tuned voltage amplifier, the
mutually coupled secondary and primary are
A0 f
A= Where , 1 ≈ 1 synchronously tuned with equal Q values then
1 + i  1 
f fº for the over-coupled case the maximum voltage
 f0  amplification
20 (a) is greater than that for critical coupling and
14 = the amplifier characteristic is double peaked
1
1+ i  (b) is less than that for critical coupling and the
1 amplifier characteristic has a single peak
40 (c) is same as that for critical coupling and the
A=
1+ i amplifier characteristic is double peaked
(d) is less than that for critical coupling and the
1
φ = − tan −1   = −45º amplifier characteristic is doubled peaked.
1 IES-2004
φ = 180º – 45º = 135º Ans. (d) : A doubled-tuned voltage amplifier, the
49. A tuned amplifier has a voltage gain of 100 and mutually coupled secondary and primary are
a bandwidth of 10 kHz. It is required to synchronously tuned with equal Q values is less than
increase the bandwidth to 20 kHz. This can be that for critical coupling and the amplifier characteristic
achieved by which one of the following ways? is doubled peacked.
(a) By doubling the gain 52. An amplifier has two identical cascaded stages.
(b) By doubling the resonant frequency Each stage has a bandwidth of 20 kHz. The
(c) By halving the Q of the coil overall bandwidth shall approximately be
(d) By halving the power supply voltage equal to
(a) 10 kHz (b) 12.9 kHz
IES-2004
(c) 20 kHz (d) 28.3 kHz
Resonant frequency IES-2003
Ans. (c) : B.W =
Quality factor Ans. (b) : Given, N = 2
where, fr = Resonant frequency Bandwidth = 20 kHz
Q = Quality factor 1
Over all bandwidth = B.W × 2 2 − 1
since bandwidth is increase from 10kHz to 20 kHz,
1
means doubled, Hence the value of Q will be halved. = 20 × 2 2 − 1
50. The transfer function of a transistor amplifier = 20 × 1.414 − 1
is given by
= 20 × 0.64
V 4240 = 12.9 kHz
AV = 0 =
VS  f  f  53. The common emitter current gain-bandwidth
1 + j  1 + j 
 4 ×105  4 ×106  product of a transistor (fT) is defined as the
Which one of the following gives the frequency at which
approximate upper 3-dB frequency fH of the (a) Alpha of the transistor falls by 3 dB
amplifier? (b) Beta of the transistor falls by 3 dB
(a) 4 × 105 Hz (b) 2.2 × 106 Hz (c) Beta of the transistor falls to unity
6
(c) 4 × 10 Hz (d) 4.4 × 406 Hz (d) Power gain of the transistor falls to unity
IES-2004, 1997 LMRC AM (S&T) 13.05.2018
IES-2005, 2003
Ans. (a) : Given,
Ans. (c) : Unity gain frequency (fT) is the frequency at
1 1
= 4 ×105 Hz and = 4 ×106 Hz which (CE) common emitter short circuit current gain
f1 f2 (β) of the transistors falls to unity, it is expressed by -
1 1 1 gm
= + fT =
f H f1 f 2 2π ( Cµ + C π )
1 1
= + 54. Which of the following components control the
4 × 105 4 × 106 low frequency of the R-C coupled amplifier?
4 × 105 1. Wiring capacitance
fH = 2. Parasitic capacitances of transistor
1.1
3. Coupling capacitances
f H = 3.63 × 105 ≃ 4 ×105 Hz 4. Emitter bypass capacitance
Select the correct answer using the codes given Ans. (a) : Beta cut-off frequency given by -
below: gm / β
fβ =
2π ( Cµ + C π )
(a) 1 and 2 (b) 2 and 3
(c) 3 and 4 (d) 1, 2 and 4
IES-2015, 2013, 2009, 2003, 2000 1
=
Ans. (c) : Coupling capacitances and emitter bypass 2π ( Cµ + C π ) r
capacitance are the components which can control the For fβ to be higher, and Cµ should be smaller.
low frequency of the RC coupled amplifier.
55. For a BJT in common emitter mode, base to 58. An RC amplifier stage has a bandwidth of
emitter capacitance (Cπ) is ten times the 500 kHz. What will be rise time of this
amplifier stage?
collector to base capacitance (Cµ). Transistor is
biased at quiescent collector current ICQ = 1 (a) 0.35 µs (b) 0.7 µs
mA and its short circuit unity gain frequency is (c) 1.0 µs (d) 2.0 µs
0.909 M (rad/s). What is the (Cπ) value? IES-2007, 2002
(a) 6.45 nF (b) 44 nF Ans. (b) : Given,
(c) 40 nF (d) 7.1 nF Bandwidth = 500 kHz
IES-2003 0.35
Rise time, tr =
Ans. (a) : Unity gain frequency - Bandwidth
gm 0.35
fT = =
2π ( Cµ + C π ) 500 ×103
= 0.7 µs
given, Cπ = 10Cµ 59. In a single-stage RC coupled common emitter
Trans conductance - amplifier, the phase shift at the lower 3 dB
I frequency is
g m = CO (a) zero (b) 135º
VT
(c) 180º (d) 225º
ICO
fT = Nagaland PSC-2018, Diploma Paper-II
2π × 11Cµ × VT IES-2001
1× 10 −3 Ans. (d) : The phase shift can be given by -
0.909 = f 
2 × 3.14 ×11× Cµ × 26 × 10−3 φ ( f ) = 180 + 90 − tan −1  
1× 10−3  f1 
Cµ = Transfer function is of the form A(if)
6.28 × 11× 26 × 10−3 × 0.909
Cµ = 0.0006125 A 0 ( jf )
Aif =
Cµ = 0.64 nF 1 + j  f 
 f1 
and Where f1 is the lower 3 db frequency
C π = 10Cµ ⇒ 6.45 nF f 
φ ( f1 ) = 180º +90º − tan −1  1 
56. Which one of the following is a wide band  f1 
amplifier? = 180º + 90º – 45º
(a) RF amplifier (b) IF amplifier φ ( f1 ) = 225º
(c) Video amplifier (d) AF amplifier
IES-2003 60. An amplifier using BJT has two identical stages
Ans. (a) : Wide band amplifier- An amplifier that will each having a lower cut-off (3 dB) frequency of
pass a wide range frequency with substantially uniform 64Hz due to coupling capacitor. The emitter
amplification RF amplifier is a wide band amplifier. bypass capacitor also provides a lower cut-off
(3 dB) frequency due to emitter degeneration
57. A BJT is to be used in a high frequency circuit alone of 64 Hz. The lower (3 dB) frequency of
in common emitter amplifier. For a higher the overall amplifier is nearly
upper cut-off frequency Cµ, Cπ and r0 have their (a) 100 Hz (b) 128 Hz
usual meanings) (c) 156 Hz (d) 244 Hz
(a) Cµ should be as small as possible IES-2000
(b) r0 and Cµ should be as large as possible Ans. (a) : Given -
(c) Cπ and Cµ should be as large as possible. Number of stages N = 2
(d) r0, Cπ and Cµ should be as large as possible. Lower 3dB frequency, fL = 64 Hz
IES-2002 Lower (3dB) frequency of the overall amplifier =
fL Codes:
f L* = A B C D
21/ N − 1 (a) 1 3 1 2
64 (b) 3 4 2 1
=
1 (c) 3 4 1 2
22 −1 (d) 4 3 2 1
64 IES-1997
=
0.414 Ans. (c) :
64 List-1 List-II
= = 100 Hz (A) R.C- coupled – Flat frequency with an
0.64 Amplifier Upper and a lower cut-
f L* = 100 Hz off frequency
(B) Tuned Amplifier – Peak in gain frequency
61. If the Q of a single-stage tuned amplifier is response response.
doubled, then its bandwidth will
(C) Chopper stabilized – Very low drift.
(a) remain same (b) become half
response Amplifier
(c) become double (d) become four times
frequency
IES-2016, 2000
(D) Direct coupling – Flat frequency
Ans. (b) : The quality factor (Q) of a single-stage tuned capacitor response from zero
amplifier is doubled, then its bandwidth will become
frequency onwards
half.
64. For a bipolar junction transistor, if the current
Resonant frequency amplification factor and cut-off frequency in
Bandwidth =
Quality factor the CB mode are αCB and f αCB respectively,
then the cut-off frequency in the CE mode is
62. The input resistance of a common emitter stage equal to
can be increased by :
(a) fαCB (b) f αCB (1 – αCB)
1. un bypassing emitter resistance
(c) f αCB/(1 – αCB) (d) f/αCB
2. bootstrapping
IES-1997
3. biasing it at low quiescent current
4. using compounded BJTs Ans. (c) : For a bipolar junction transistor, if the current
The correct sequence in descending order of amplification factor and cut-off frequency in the CB
the effectiveness of these methods is mode are αCB and f αCB respectively, then the cut-off
(a) 2, 4, 1, 3 (b) 4, 3, 2, 1 frequency in the CE mode is equal to
(c) 2, 4, 3, 1 (d) 4, 2, 3, 1 Cut-off frequency of CB mode.
IES-1999 fα CB
=
Ans. (a) : The input resistance of a common emitter (1 − α CB )
stage can be increased by bootstrapping then using
compounded BJTs after that unbypassing emitter 65. In the case of an amplifier, the normalized
resistance then it is correct sequence of descending voltage gain is given by
order of the effectiveness. f
Hence correct order of effectiveness 2 > 4 > 1 > 3. 1+ j
Av 1 f0
63. Match List-I (Circuit) with List-II = .
A R f
(Characteristic) and select the correct answer 0 1+ 1 1+ j
using the codes given below the Lists: R 2 f p
List-I List-II Where f0 is the zero frequency and fp is the pole

A. RC-coupled 1. Very low drift frequency. For a standard frequency response
amplifier of the amplifier,
(a) fp >> f0 (b) fp = f0
B. Tuned amplifier 2. Flat frequency
response from (c) fp << f0 (d) f0 = 2 fp
zero frequency IES-1997
onwards Ans. (a) : For standard frequency response, pole
C. Chopper 3. Flat frequency frequency must be more than zero frequency.
stabilized response f p >> f 0
amplifier with an upper and
a lower cut- 66. Of the various capacitances associated with a
off frequency junction transistor, the gain-band width
product is affected to a maximum extent by
D. Direct coupling 4. Peak in gain
capacitor frequency (a) Base-collector parasitic capacitance
response (b) Base-collector space charge layer capacitance

(c) Base-emitter space charge layer capacitance 68. Match List-I with List-II and select the correct
(d) Base-emitter diffusion capacitance answer using the codes given below the lists:
IES-1997 List-I List-II
Ans. (d) : A. RC coupling 1. Higher voltage gain &
Gain-bandwidth product is a transistor affected to a impedance matching
extent by- B. Inductive 2. Ability to amplify dc and
(i) Base- collector parasitic capacitance. coupling low frequency signals.
(ii) Base- emitter space charge layer capacitance. C. Transformer 3. Minimum possible
(iii) Base- collector space charge layer capacitance and coupling non-linear distortion
maximum affected by Base- emitter diffusion D. Direct coupling 4. Low collector supply
capacitance. voltages can be used
67. Consider the following statements: Codes:
In order to increase the bandwidth of tuned A B C D
amplifier, one can use (a) 4 1 3 2
1. Tuned circuit with inductance having high Q (b) 3 4 1 2
factor. (c) 1 2 3 4
2. Double-tuned amplifier with two tuned (d) 4 3 2 1
circuits coupled by mutual inductance. IES-1996
3. Staggered tuned amplifiers in which Ans. (b) :
different tuned circuits which are cascaded are List-I List –II
tuned to slightly different frequencies. RC- coupling - Minimum possible non-linear
Of these statements distortion
(a) 1 alone is correct Inductive coupling - Low collector supply voltage
(b) 1 and 2 are correct can be used
(c) 2 and 3 are correct Transformer coupling - High voltage gain and
(d) 1, 2 and 3 are correct Impedance matching.
IES-1997 Direct coupling - Ability to amplify dc and low
Ans. (c) : frequency signal
Double tuned Amplifier- 69. The upper 3 dB frequency in a Common
In double tuned Amplifier, voltage gain remains Emitter amplifier is given in terms of the
approximately constant inside pass band and it falls hybrid parameters as
rapidly out side pass band- g g
(a) b 'e (b) b 'e
2πC C
h g
(c) fe (d) m
g b 'e h fe
IES-1995
Ans. (a) :
Hybrid parameter-
fo
Bandwidth = 2 × ( for double tuned ) AI =
h fe
Q 2
Double-tuned amplifier with two tuned circuits coupled f 
1+  T 
by mutual inductance. f 
Staggered tuned- it is cascade of tuned Amplifier  β
having unequal resonant frequencies it is used to The upper 3 dB frequency in a common emitter
increased Bandwidth. Amplifier is-
g b 'e
=
2 πC
70. The bandwidth of an RC-Coupled Amplifier is
limited by
(a) Coupling Capacitors at the low-frequency end
and bypass Capacitors at high frequency end.
(b) Coupling Capacitors at high frequency end
and bypass Capacitors at the low frequency
Staggered tuned amplifiers in which different tuned end.
circuits which are cascaded are tuned to slightly (c) Bypass and Coupling Capacitors at the low
different frequencies. frequency end and shunt capacitors at the
So the statement 2, 3 are correct. high frequency end.
(d) Shunt Capacitors at the low frequency end V Z
and bypass as well as Coupling Capacitors at i
=
the high frequency end. I i 1 − K
IES-2011, 1994 Z
Zi =
Ans. (c) : To limit the Bandwidth of an RC-coupled 1− K
Amplifier we use bypass and coupling capacitors at the
low frequency end and shunt capacitor (or junction 73. The fT of a BJT is related to its gm' Cπ and Cµ
capacitor) at the high frequency end. as follows
71. A two-stage amplifier is required to have an C π + Cµ 2π(C π + Cµ )
(a) fT = (b) fT =
upper cut-off frequency of 2MHz and a lower gm gm
cut-off frequency of 30 Hz. The upper and
lower cut-off frequencies of individual stages g m gm
(c) fT = (d) fT =
are respectively approximately C π + Cµ 2π(C π + Cµ )
(a) 4 MHz, 60 Hz (b) 3 MHz, 20 Hz GATE-1998
(c) 3 MHz, 60 Hz (d) 4 MHz, 20 Hz Ans. (d) The unity gain bandwidth frequency of a BJT
TNPSC A.E-2019 is related to its g C and C by Relation-
m' π µ
IES-1993
g
Ans. (b) : We known- fT = m
2π ( C π + Cµ )
fH = fH 2 −1
' 1N
74. An npn transistor (with C = 0.3 pF) has a

2 × 106 = f H 21 2 − 1 unity-gain cut-off frequency fT of 400 MHz at a
2 ×10 6 dc bias current Ic = 1 mA. The value of its
fH = Cµ (in pF) is approximately (VT = 26 mV)
0.414
(a) 15 (b) 30
f H = 3.1 MHz (c) 50 (d) 96
fL TNPSC AE-2019
f L' = TNPSE AE-2014, GATE-1999
21 2 − 1 Ans. (a) : Given-
f L = f L' 21 N − 1 ⇒ 30 21 2 − 1 =19.30 Hz  20 Hz C = 0.3 pF
72. In the circuit shown in figure is a finite gain f T = 400 MHz
amplifier with a gain of K, a very large input I = 1 mA
C
impedance, and a very low output impedance.
The input impedance of the feedback amplifier VT = 26 mA
with the feedback impedance Z connected as Cµ = ?
shown will be
1 1 I
fT = Where, = gm = C
2πRC R VT
IC 1 mA
fT = ⇒ Cµ =
2πVT × Cµ 2π × 26mV × 400 × 106
Cµ = 15pF
75.An amplifier is assumed to have a single-pole
 1
(a) Z 1 −  (b) Z (1 – K) high-frequency transfer function. The rise time
 K of its output response to a step function input is
 Z   Z  35 nsec. The upper 3dB frequency (in MHz) for
(c)  (d) 
 K − 1   the amplifier to a sinusoidal input is
1 − K  approximately at
GATE-1996 (a) 4.55 (b) 10
Ans. (d) : (c) 20 (d) 28.6
V GATE-1999
Zi = i
Ii Ans. (b) : Given-
(tr) step function input is = 35 nsec.
Vi − Vo
Ii = t r × BW = 0.35
Z
0.35
 V  B.W =
Vi 1 − o  35 × 10−9
= 
Vi 
Z B ⋅ W = 10 MHz

76. An npn BJT has gm = 38 mA/V, Cµ = 10–14 F, 78. Which one of the following statements is
Cπ = 4×10–13F, and DC current gain β0 = 90. correct about an ac-coupled common-emitter
For this transistor fT and fβ are amplifier operating in the mid-band region?
(a) fT = 1.64 × 108 Hz and fβ = 1.47 × 1010 Hz (a) The device parasitic capacitances behave like
(b) fT = 1.47 × 1010 Hz and fβ = 1.64 × 108 Hz open circuits, whereas coupling and bypass
capacitances behave like short circuits.
(c) fT = 1.33 × 1012 Hz and fβ = 1.47 × 1010 Hz
(b) The device parasitic capacitances, coupling
(d) fT = 1.47 × 1010 Hz and fβ = 1.33 × 1012 Hz capacitances and bypass capacitances behave
GATE-2001 like open circuits.
Ans. (b) : Given- (c) The device parasitic capacitances, coupling
npn BJT gm = 38 mA/V capacitances and bypass capacitances behave
Cµ = 10–14 F like short circuits.
Cπ = 4×10–13F (d) The device parasitic capacitances behave like
β0 = 90 short circuits, whereas coupling and bypass
fT = ? capacitances behave like open circuits.
fβ = ? GATE-2016, Set-II
gm Ans. (a) : The device parasitic capacitances behave like
fT = open circuits, whereas coupling and bypass
2π ( C π + Cµ ) capacitances behave like short circuits when an AC-
coupled common-emitter amplifier operating in the
38 × 10−3
= mid-band region.
2π ( 4 × 10−13 + 10−14 ) 79. The Miller effect in the context of a common
emitter amplifier explains
f T = 1.47 × 1010 Hz
(a) An increase in the low-frequency cutoff
f T 1.47 × 1010 frequency
fβ = = (b) An increase in the high-frequency cutoff
βo 90
frequency
fβ = 1.64 ×108 Hz (c) A decrease in the low-frequency cutoff
frequency
77. A bipolar transistor is operating in the active (d) A decrease in the high-frequency cutoff
region with a collector current of 1 mA. Assuming frequency
that the β of the transistor is 100 and the thermal GATE-2017, Set-I
voltage (VT) is 25 mV, the transconductance (gm) Ans. (d) : Miller effect makes dominant increase in the
and the input resistance (rπ) of the transistor in the input capacitance of CE amplifier.
common emitter configuration, are
1
(a) gm = 25 mA/V and rπ = 15.625 kΩ Upper cut-off frequency (fh) ∝
(b) gm = 40 mA/V and rπ = 4.0 kΩ Cinput
(c) gm = 25 mA/V and rπ = 2.5 kΩ Hence, there is reduction in upper cut-off frequency and
(d) gm = 40 mA/V and rπ = 2.5 kΩ bandwidth of common emitter amplifier
IES-2014 80. The overall bandwidth of two identical voltage
GATE-2004 amplifiers connected in cascade will be:
Ans. (d) : Given that - (a) same as single stage
IC = 1mA (b) higher than single stage
(c) lower than single stage
VT = 25mV (d) higher if stage gain is low and lower if stage
β = 100 gain is high
IC 10−3
gm = = Ans. (c) : the overall bandwidth of two identical voltage
VT 25 × 10−3 amplifiers connected in cascade will be lower than
g m = 40mA / V single stage.
81. In a transistor hfe = 50, hie = 830Ω, hoe = 10-4
1 1
re = = mho. Its output resistance when used in CB
g m 40 × 10−3 configuration is about
re = 25Ω (a) 2 MΩ (b) 2.5 MΩ
The hybrid parameter rπ will be- (c) 500 Ω (d) 500 kΩ
rπ = β × re = 100 × 25 TSPSC Manager (Engg.) - 2015
Ans. (d) : Given that-
rπ = 2.5kΩ hfe = 50, hie = 830Ω, hoe = 10 −4 
h oe 10−4 86. A single stage amplifier has a voltage gain of
h ob = = 60. The collector load Rc = 500 Ω and the input
1 + h fe 1 + 50 impedance is 1kΩ. The overall gain when two
10−4 such stages are cascaded through R-C coupling
h ob = is:
51
(a) 60 (b) 3600
1 51
R ob = = −4 = 510 kΩ  500kΩ (c) 120 (d) 1200
h ob 10 (e) 2397
82. Consider the following data for common- CGPSC SO 14.02.2016
emitter hybrid equivalent circuit of BJT Ans. (e) : gain of single stage = 60
transistor, IE = 2.5 mA. hfe = 140, hoe = 20 µS Rc = 500Ω
and hob = 0.5 µS
Rin = 1000Ω
The values of hie and r0 will be nearly:
(a) 1.46 kΩ and 30 kΩ (b) 1.46 kΩ and 50 kΩ Effect load = Rc || Rin = 333Ω
(c) 1.64 kΩ and 50 kΩ (d) 1.64 kΩ and 30 kΩ 333
Gain of second stage = 60 × = 39.96
UPSC Poly.Lect.10.03. 2019 500
Total gain = 60 × 39.96 = 2397.6  2397
1 1
Ans. (b) : ro = = = 50kΩ 87. A three-stage amplifier has a first stage voltage
h oe 20 ×10−6 gain of 100, second stage voltage gain of 200
V 26mV and third stage voltage gain of 400. The total
re = T = = 10.4Ω voltage gain in dB is:
Ie 2.5mA
(Given that log10 100=2, log10 200=2.3, log10
β β
rπ = = = β.re = 140 ×10.4 = 1.456kΩ 400=2.6)
g m 1 re (a) 400 (b) 700
rπ  1.46kΩ (c) 350 (d) 138
83. The current gain of a bipolar transistor drops (e) 276
at high frequencies because of CGPSC SO 14.02.2016
(a) Transistor capacitance Ans. (d) : A1 = 100 A2 = 200 A3 = 400
(b) High current effects in the base Total Gain (A) = A1 A2 A3
(c) Parasitic inductive element = 100 × 200 × 400 = 8 × 106
(d) The early effect Gain in dB = 20 log A = 20 log (8 × 106)
Nagaland PSC (Degree) 2018, Paper-II = 138.0 dB
UPRVUNL AE 2016 88. A multistage amplifier employs five stages each
Ans. (a) : The current gain at high frequencies drop in of which has a power gain of 30? The total gain
BJT due to transistor (inter-electrode) capacitances. of the amplifier in dB is _____
84. Cascading amplifier stages to obtain a high (log10 30 = 1.477)
gain is best done with------ (a) 150 dB (b) 75 dB
(a) Common-emitter stages (c) 73.85 dB (d) 100 dB
(b) Common-base stages (e) 147.7 dB
(c) Common-collector stages TNPSC AE 2019
(d) (b) and (a) CGPSC SO 14.02.2016
TNPSC AE- 2019 Ans. (c) : Gain of each stage = 30
GPSC Asstt. Prof.-11.04.2017 Number of stages = 5
Ans. (a) : In cascaded amplifiers, the output as voltage Power gain of each stage in dB = 10 log10 30 = 14.77
of the first stage becomes the input voltage of the Total power gain = 5 × 14.77 = 73.85 dB
second stage and the ac output of the second stage
becomes the input of the third stage and so on. 89. The current ib through base of a silicon npn
Cascading amplifier stages to obtain a high gain is best transistor is 1+0.1 cos (100πt) mA. At 300K, the
done with common-emitter stages. rπ in the small signal model of the transistor is:
85. In a tuned circuit, the secondary circuit has a
capacitor of 100pF. The reflected value of this
25pF. The turn ratio is
(a) 2 : 1 (b) 1 : 2
(c) 4 : 1 (d) 1 : 4
Ans. (c) : Given as- C1 = 100pF & C2 = 25pF
(a) 25 Ω (b) 27.5 Ω
C1 100
turn ratio a = , a= = 4 :1 (c) 125 Ω (d) 250 Ω
C2 25
Ans. (a) : rπ = β / g m rb'c or gb'c Resistance of reverse 4M Ω
baised P-N junction 0.25 × 10−6 mho
Ic
gm = between base and
VT collector conductance
of reverse biased P-N
β
rπ = junction between base
( Ic / VT ) and collector
VT rce or gce Output resistance 80k Ω
rπ = β between collector and 12.5 × 10−6 mho
IC
emitter. Conductance
VT
rπ = ( β / Ic ) VT = between base and
Ib emitter
25mV Ce Junction capacitance 100pF
rπ = , between base and
1mA emitter
rπ = 25Ω Cc Junction capacitance 3pF
90. The common emitter model is shown below between base and
collector
92. Bootstrap voltage sweep generator uses
(a) negative feedback
(b) positive feedback
(c) both negative and positive feedbacks
simultaneously
The h-parameters of this model are (d) no feedback
8 1   5 1 RPCS Lect.-2011
(a)   (b)   Ans. (b) : A bootstrap sweep generator is a time base
0.8 0.25 0.8 1 generator circuit whose output is feedback to the input
8 0.8  5 0.8 through the positive feedback. This will increase or
(c)   (d)   decrease the input impedance of the circuit. The process
1 0.25 1 1  of bootstrapping is used to achieve constant charging
NIELIT Scientists- 2017 current.
Ans. (a) : Write input KVL and output KCL equation 93. Which component can amplify a small signal
V1 = h11I1 + h12 V2 but must use high voltages?
I 2 = h 21I1 + h 22 V2 (a) A vacuum tube
(b) A transistor
V1 = 8I1 + V2
(c) An electrolytic capacitor
V (d) A multiple-cell battery
I2 = 0.8 I1 + 2
4 RRB SSE-03.09.2015, Shift-III
 8 1 Ans. (a) : Vacuum tubes are used to amplify very small
 h11 h12  8 1 
h  =  1  =   signals and use them at high voltages.
 21 h 22   0.8 0.8 0.25
 4  94. A BJT differential amplifier with matched
transistors is having hfe of 200 and hie of
91. Which one of the following is not an element of 1.2kΩ and Rc of 3.3kΩ. Find the differential
a hybrid π model gain, AV.
(a) rbb (b) CC (a) -350 (b) 300
(c) Ce (d) hfe (c) -275 (d) 295
Nagaland PSC CTSE (Degree)-2017, Paper-II UPPCL AE-05.11.2019
Ans. (d) : hfe is not an element of a hybrid π model. Ans. (c) : Given R c = 3.3kΩ
Hybrid- π parameter element and value:- h fe = 200
Parameter Meaning Value h ie = 1.2kΩ
Im Mutual conductance 50mA/V Rc
rbb' Base spreading 100Ω AV = − × h fe
resistance 2h ie
rb'e or Ib'e Resistance between 1k Ω AV = −
3.3
× 200
base and emitter 1m mho 2 × 1.2
conductance between
base and emitter A V = −275

95. For the base bias circuit, R B = 470kΩ, (a) 20 dB (b) 10 dB
R C = 2.2kΩ, and VCC = 18V and the transistor (c) –40 dB (d) –20 dB
NLC GET -24.11.2020
has an hfe of 100. Find VCE .
Ans. (c) : For % THD, the dB distortion will be
(a) 8.548 V (b) 10.246 V
x%
(c) 12.602 V (d) 9.902 V = 20log10
100
UPPCL AE-05.11.2019 for 1% THD, the dB distortion will be
Ans. (d) : Given- 1
R B = 470kΩ , R C = 2.2kΩ , VCC = 18V = 20log10 = 20log1010–2
100
β = h fe = 100 = 20×(–2)log1010
Base bias circuit is represented as = −40dB
98. Following is the small-signal high-frequency
equivalent circuit of a common source
amplifier. V0/Vi will be of the form (K, z1, a0, a1,
a2, a3 are constants containing circuit
elements).
Or
Fixed bias circuit
V − VBE
I B = CC , with IC = β IB
R BE
18 − 0.7
IB = = 0.036mA (a) K ( s − z ) / ( a 0 + a1s + a 2s 2 )
470kΩ
The value of the collector current is (b) K.s / ( a 0 + a1s + a 2s 2 + a 3s3 )
IC = βI B
(c) K ( s − z1 )( a 0 + a1s )
= 100 × 0.036mA
The value of the collector current is VCE = VCC − IC R C (d) K / ( a 0 + a1s )
= 18 − 3.68 × 2.2 ISRO Scientist December, 2017
= 9.902V Ans. (a) : General gain equation for small signal high
frequency common source amplifier is-
96. A two stage capacitor coupled CE amplifier has
( )( 0 1 2 )
stages having a voltage gain of 100 each. It is G = Vo = K s–z a + a s + a s 2
known that the gain of each stage drops by 3dB Vi
at lower cutoff frequency. What is the overall
gain of the multistage amplifier at lower cutoff 99. A BJT Darlington pair has :
frequency? (a) high input impedance and high β
(a) 74 dB (b) 34 dB (b) high input impedance and low β
(c) -74 dB (d) -34 dB (c) low input impedance and high β
UPPCL AE-05.11.2019 (d) low input impedance and low β
Ans. (a) : For two stage amplifier- DRDO-2009
A = A ×A
V V1 V2
Ans. (a)
A V ( dB ) = A V1 ( dB ) + A V2 ( dB )
When gain is 100,
A V1 = 20log (100 ) = 40dB.
It is given that the gain of each stage drops by 3dB
Gain of first stage (Av1) = (40–3)dB = 37dB
Gain of output of second stage (Av2) = 37 dB
The over all gain will be
A v = A v1 + A v2 A Darlington pair is a two-transistor circuit with the
= 37 + 37 emitter of one transistor is connected to the base of the
= 74 dB other transistor, while both collector terminals are
97. What is the dB distortion for an amplifier with connected to the common terminals. it has high current
1 percent THD? gain β and it also has high input impedance.

100. In the circuit shown in figure below, β for the Ans. (b) : As compared to CE amplifier, the frequency
BJTs is 99. response of an emitter follower is Better because its
bandwidth is larger.
103. If two stages of a cascaded amplifier have
decibel gains of 60 and 30, then overall gain is
............. dB.
(a) 90 (b) 1800
(c) 2 (d) 0.5
TNPSC AE-2008
Ans. (a) : The overall gain in dB can be written as,
Assuming the thermal voltage to be 50 mV, the
input resistance Ri is : A V (dB) = A V1 (dB) + A V2 (dB) + ........ + A n (dB)
(a) 650 Ω (b) 25 kΩ A v (dB) = 30 + 60
(c) 40 kΩ (d) 65 kΩ
DRDO-2009 A v (dB) = 90 dB
Ans. (d) : Given β = 99 104. For a transistor
hie = 1kΩ, hfe = 30Ω, hre = 0
I 0.8
Sol. Io = 0.8, mA IC1 = IC2 = o = = 0.4mA hoe = 20 × 10–6  , and RL = 2.5 kΩ
2 2 The transistor is used in a single stage CE
β β amplifier. The voltage gain and power gain,
rπ = = = β re
g m 1 re respectively, are
V 50mA (a) 75 and 1750 (b) 25 and 2250
re = T = = 125Ω (c) 75 and 2250 (d) 25 and 1750
IC 0.4mA IES-2019
loop equation.
Ans. (c) : Given that, h ie = 1× 10 Ω = Rb
3
− Vi + rπi b + 200i e + 200i e + rπi b = 0
h fe = 30Ω
2rπi b + 400i e = Vi
hre = 0
2rπ + 400 ( β + 1) i b = Vi h oe = 20 × 10 −6 
V
2  reβ + 200 ( β + 1)  = i R L = 2.5kΩ
ib If (hoe×RL)< 0.1
R i = 2 [125 × 99 + 200 × 100] AI  β = h fe = 30
= 64.75KΩ
 65KΩ
101. Consider a diode with reverse saturation
current Is = 9.5 × 10–15 A and thermal voltage
VT = 26 mV, ideality factor n = 1. For voltage
0.65 V across the diode, the diode current is
approximately
(a) 0.032 mA (b) 1.22 mA Single stage CE amplifier voltage gain
(c) 0.68 mA (d) 4.87 mA  RL 
UPPCL AE- 31.12.2018 A v = β  R 
 b
 VηBE   2.5 
Ans. (c) : I D = IS e VT − 1 = 30 ×   = 75
   1 
 0.65  Power gain = Av.Ai
I D = 9.5 × 10−15  e 26 mV − 1
  = 75×30 (β = Ai )
I D = 6.84 ×1011 ×10 −15 = 2250
105. Except at high frequencies of switching, nearly
I D = 6.84 × 10 −4 all the power dissipated in the switch mode
ID = 0.684 mA operation of a BJT occurs, when the transistor
is in the
102. As compared to CE amplifier, the frequency (a) Active region
response of an emitter follower is (b) Blocking state
(a) Worse (b) Better (c) Hard saturation region
(c) Similar (d) None of these (d) Soft saturation region
UJVNL AE-2016 IES-2016
Ans. (c) : In the hard-saturation region, the on time Therefor it behaves like a short circuit, it increase the
duration is more. So, the power dissipation occurs in base current of the transistor due to which the current
large amounts as the current is maximum. gain ( β ) reduces.
In the cut-off region current is zero. So, no power
dissipation occurs in this region during the switched
mode operation of BJT.
106. Upper 3 dB cut-off common emitter amplifier
depends on
(a) E-B junction capacitance
(b) C-B junction capacitance
(c) Capacitances of both junctions
109. To get higher cut-off frequency in a BJT, base
(d) Coupling capacitor capacitance sheet resistance should be
IES-2015 (a) low
Ans. (c) : Upper 3dB cut-off common emitter amplifier (b) high
depends on capacitances of both junction. (c) equal to cut-off frequency
(d) zero
IES-2014
Ans. (a) : To get higher cut-off frequency the base sheet
resistance should be low.
1 1
f= ,f ∝
2πRC RC
R = resistance and C = capacitance
Large area bipolar transistor can have a very non-
107. Consider the following statements in respect of uniform current distribution due to the sheet resistance
an R-C coupled transistor amplifier: of the base layer.
1. The low frequency response is determined 110. For common-collector amplifier, the current
by the transistor junction capacitors. gain (A1) is
2. The high frequency response is limited by 1 + h fe
coupling capacitors. (a) 1 + hfe (b)
1 + h oe R L
3. The Miller capacitance reduces the gain at
high frequencies. 1 + h fe 1 + h fe
(c) (d)
4. As the gain is increased the bandwidth gets h oe h ie 1 + h ie R L
reduced. IES-2012
Which of the above statements are correct? Ans. (b) : The general equation for the current gain of
(a) 1 and 2 (b) 2 and 3 small signal analysis of a transistor amplifier.
(c) 3 and 4 (d) 1 and 4 −h f
IES-2015, 2003 A I = .............(i)
1 + h oe R L
Ans. (c) : R-C coupled transistor amplifier-
The Miller capacitance reduces the gain at high For common collector amplifier
frequencies h f = − (1 + h fe ) ...............(ii)
As the gain is increased the bandwidth gets reduced. Put the value equation (ii) in equation (i)
The low frequency response is determined by 1 + h fe
coupling capacitor and bypass capacitor. AI =
The high frequency response is determined by shunt 1 + h oe R L
capacitor (junction capacitor). 111. In the below circuit the optimum low frequency
Above both statements is correct. compensation is obtained when
108. The current gain of bipolar transistor drops at
high frequency because of
(a) Transistor capacitances
(b) High current effects in the base
(c) Parasitic inductive elements
(d) The early effect
IES-2014
Ans. (a) : The gain of a bipolar transistor, drops at high (a) C1R1 = RE CE (b) C1R1 = CCRi
frequency because of the interelectrode capacitances. (c) C1 ( R C R1 ) = CC R i (d) C1 ( RC R1 ) = RECE
As we know that at high frequency range, the reactance
of CC becomes quite small. IES-2011
Ans. (c) : Above circuit the optimum to frequency
compensation is obtained when-
It is used to extensively to improve the bandwidth of the
system.
Condition for low frequency compensation,
CL R L = Ci R i .............(i)
According to given circuit
CL = C1
R L = R1 || R C
(a) CS, CE, internal junction capacitance of
Put the value in equation. transistor
C L R L = Ci R i , Ci = CC (b) Strong wiring capacitance (CW), CC
C1 ( R1 || R C ) = CC R i (c) CS, CE, CC
(d) CS, CE only
112. A common emitter transistor amplifier has a
IES-2007
collector load of 10 kΩ. If its hfe = 100 and
Ans. (c) :
hie = 2 kΩ(hre ≈ hoe ≈ 0), the voltage
amplification of the amplifier is nearly equal to
(a) 500 (b) 200
(c) 100 (d) 50
IES-2011
Ans. (a) : In common emitter transistor h-parameter
given as,
R L = 10 kΩ, h fe = 100
h ie = 2 kΩ = Ri
h fe R L Lower cut off frequency depend on CE emitter bypass
CE amplifier voltage gain, A v = −
h ie capacitor, CS source capacitance and CC coupling
capacitor. “3 dB less than at midrange is called the
−100 × 10 × 103 lower cutt of frequency”
=
2 × 103 115. A CE-amplifier has RL = 10kΩ. Given
A v = −500 hie = 1kΩ, hfe = 50, hre = 0 & 1/hoe = 40 kΩ.
A v = 500 What is the voltage gain?
(a) – 500 (b) – 400
113. Which of the transistor models is most (c) – 50 (d) – 40
preferred for the analysis of a transistor circuit IES-2015, 2006
both at mid-band at high frequencies?
Ans. (b) : The general equation for the current gain of
(a) h-parameter model (b) y-parameter model
small signal analysis of transistor amplifier
(c) s-parameter model (d) hybrid π-model According to given question
R L = 10kΩ h ie = 1kΩ h fe = 50
IES-2009
1
Ans. (d) : Hybrid π model is the most preferred for the h re = 0 and = 40kΩ
analysis of the transistor circuit both at mid-band at h oe
high frequency. Av = ?
The hybrid- π-model used for analyzing the small signal − h fe 50
behaviour of BJT and FET Ai = =−
1 + h oe R L 1× 10 × 103
Hybrid π model – 1+
40 ×103
−50
= = −40
5
4
Z −40 × 10k
A v = Ai ⋅ L =
114. For the amplifier shown in the figure given Zin 1k
below, the lower cut-off frequency depends on
A v = −400
which of the following?
116. An amplifier circuit is shown in the given figure:117. In a junction transistor biased for operation at
emitter current 'IE' and collector current 'IC'
the trans conductance 'gm' is
(a) kT/qIE (b) qIE/kT
(c) IC/IE (d) IE/IC
IES-1999
Ans. (b) : Trans-conductance mathematically defined as
the ratio of the change in collector current to thermal
The voltage gain (V0/Vs) is: voltage
(a) 4/3.33 (b) 100 I
(c) 150 (d) 160 gm = E
VT
IES-2000
I E = Emitter current
Ans. (d) : D.C analysis
Capacitor work as open circuit- VT = Thermal voltage
IE
gm =
kT
q
qI
gm = E Where, k= [ Boltzmann constant ]
kT
118. If Rs is the source resistance, the output
30 × 103 × 60 × 103
R Th = = 20kΩ resistance of an emitter-follower using the
90 × 103 simplified hybrid model would be
12 × 30 ×103 R s + h ie h + Rs
VB = = 4V (a) (b) ie
90 × 103 1 + h fe h fe
V − VBE 4 − 0.7 1 1
IE = B = = 1mA (c) R s + (d)
RE 3.3k h fe h 0e
h FE = 150 = β IES-1998
β is very Ans. (a) : Emitter follower also known as common
IC = β IB collector configuration.
It is used for impedance matching it is the ratio of
∴ β↑ then I B ↓ (Very low) emitter current to base current.
Assume IB is neglected, I
I E = IB + IC (I B = 0) γ= E
IB
IE = IC =1mA Phase shift between input and output is 0º
Trans-conductance CC configuration
I 1mA
gm = C = (at room temperature VT =25mV)
VT 25mV
gm = 40mA/V
Output resistance of an emitter follower using the

V0 = −g m .Vπ .R L simplified hybrid model would be
V0 = −g m .VS .R L {Vπ = VS } R + h ie v o
Ro = S =
1 + h fe io
V0
= −40 × 10−3 × 4 ×103 119. A trans conductance amplifier has
VS
(a) High input impedance and low output
V0 impedance
= −40 × 4
Vs (b) Low input impedance and high output
impedance
V0
= −160 (c) High input and output impedances
VS (d) Low input and output impedance.
Voltage gain = 160 IES-1998
Ans. (c) : The trans-conductance amplifier convert an Vi
=  h ie + (1 + h fe ) R e 
input of voltage to an output of current. It is also called Ib 
a current to voltage converter. V
A trans-conductance amplifier has high input and output Where, i = R i
Ib
impedance.
output current R i = h ie + (1 + h fe ) R e
gm =
output voltage 122. Consider the following statements regarding
It is used in bipolar junction transistor in order to the time-base voltage of an oscilloscope: It can
measure its sensitivity. be generated using
1. Miller sweep circuit
120. Match List-I (Models of BJT) with List-II
2. boot-strap integrator circuit
(Applications) and select the correct answer
3. time-delay circuit
4. a controlled circuit
List-I List-II Of these statements
A. Hybrid model 1. Microwave (a) 1, 2 and 3 are correct (b) 1 and 2 are correct
measurements (c) 2, and 4 are correct (d) 1, 3 and 4 are correct
B. Hybrid pi-model 2. Coupled diode IES-1997
C. S-parameter 3. Low frequency Ans. (a) : The generator which is used for generating the
D. Ebers-Moll model 4. High frequency linear variable voltage concerning time is known as the
Codes: time base generation these wave are used in cathode ray
tube for deflecting the beam in a horizontal direction.
A B C D
It can be generated by.
(a) 4 3 1 2
Miller sweep circuit.
(b) 3 4 2 1 Boot strap integrator circuit
(c) 3 4 1 2 Time-delay circuit
(d) 4 3 1 2 123. In the circuit shown in the given figure, assume
IES-1998 that the capacitor C is almost shorted for the
Ans. (c) : Hybrid model is used for low frequency. frequency range of interest of the input signal.
Hybrid π model is used for high frequency because it Under this condition, the voltage gain of the
amplifier will be approximately.
provides more accurate result than other two models.
hfe = 100, hie = 1 kΩ
S-parameters applicable for microwave frequency
measurement. S-parameter are frequency domain
quantities which are commonly used to model
behavior of RF circuit components.
Ebers-moll model is used coupled diode.
121. The approximate value of input impedance of a
common emitter amplifier with emitter
resistance Ri is given by
(a) 0.33 (b) 0.5
(a) hie + A1Re (b) hie + (1 + hfe) Re
(c) 0.66 (d) 1
(c) hie (d) (1 + hfe) Re
IES-1996
IES-1997
Ans. (d) : Given,
Ans. (b) :
hfe = 100, hie = 1kΩ
Re = RL=0.66 kΩ
V −h fe × R L
AV = 0 =
VB h ie + (1 + h fe ) R e
−100 × 0.66k
=
1k + (1 + 100 )(1k )
−100 × 0.66 × 103
Applying KVL =
1× 103 + (1 + 100 ) 0.66 ×103
Vi − h ie I b − Ie R e = 0
Vi = h ie Ib + ( I b + h f e I b ) R e 66 × 103 1
= =
66.66 × 10 1.01
3
Vi =  h ie + (1 + h f e ) R e  I b Av ≃ 1

124. For the transistor amplifier in the given figure, hie hre hfe hoe
the voltage amplification is approximately. (a) 100 Ω 10–1 50 1 ms
(b) 5 kΩ 10–4 200 20 ms
(c) 5 kΩ 0 20 3 ms
(d) 100 kΩ 102 100 10 ms
IES-1995
Ans. (b) : At 1mA collector current, for small signal
Audio transistor in the CE configuration.
The h-parameter for CE configuration value-
Input impedance (hie)- order is of 5 kΩ
(a) 100 (b) 84
Reverse voltage gain (hre)- order in 10–4
(c) 0.723 (d) –2
Current gain (hfe)-High value (200)
IES-1995
Output admittance (hoe)-order is 20 ms
Ans. (d) : Given,
hfe = 100, hie = 1kΩ 127. The equivalent circuit of a CE transistor is
Re = 0.5kΩ represented by
V −h fe × R L
AV = 0 =
VB h ie + (1 + h fe ) R e
−100 ×1k
= (a)
1k + (1 + 100 )( 0.5k )
−100
Av =
1 + 50.5
−100
Av = ≃ −2
51.5
125. The small signal input impedance of a (b)
transistor when the output is shorted for the
measuring signal, is (where the symbols have
their usual meaning).
V1 V1
(a) h11 = (b) h12 =
i1 v 2 =0
i 2 i =0
1
(c)
i i
(c) h 21 = 2 (d) h 22 = 2
i1 v 2 =0
v2 i1 = 0
IES-1995
Ans. (a) : Small signal input impedance of a transistor
when the output is shorted,
The hybrid parameter model (d)
The h-parameter model of BJT is defined by two port
network as.
IES-1994
Ans. (b) : CE transistor represented by-
V1 = h11I1 + h12 V2 .......... (i)
I 2 = h 21I1 + h 22 V2 ............ (ii)
The input impedance h11 / I1
V1
h11 =
I1 V2 = 0
126. Typical values of h parameters, at about 1 mA VB = I B h ie + h re VC

collector current, for small signal audio
IC = h f e I b + h oe VC
transistors in the CE configuration are
128. The 'h' parameter equivalent circuit of a 131. α cut-off frequency of a bipolar junction
junction transistor is valid for transistor
(a) high frequency, larger signal operation (a) Increase with the increase in base width
(b) high frequency, small signal operation (b) Increase with the increase in emitter width
(c) low frequency, small signal operation (c) Increases with the increase in collector width
(d) low frequency, larger signal operation (d) Increase with decrease in the base width
TSPSC Manager (Engg)-2015
IES-1993
GATE-1993
Ans. (c) : The h-parameter are used to analyzing
Bipolar junction Transistor or BJT. The ‘h’ parameter Ans. (d) : α = Common base dc current gain.
equivalent circuit of a junction transistor is valid for low Ic
frequency, small signal operation. α=
Ie
129. A transistor has h-parameter as
hie = 10kΩ, hre = 20 × 10–4, hfe = 100, hoe = 25 µS. for dc → f = 0
The hib for this transistor will be But take, α = α0 = at zero frequency (are at low
(a) 100Ω (b) 99.01Ω frequency and mid frequency).
(c) 5MΩ (d) 101KΩ So,
IES-1991 At low frequency and Mid frequency the value of α, a
Ans. (b) : Given, common base dc current gain is going to be constant.
h ie = 10kΩ, h re = 20 ×10 −4 But a high frequency parasitic capacitance.
At High frequency,
h fe = 100, h oe = 25µS.
α0
h ie α (t) =
h ib =  f 
1 + h fe 1+j  
 fα 
10 ×103
h ib = Where fα is the cut off frequency at which α0 drops to
1 + 100 0.707
10000 So, α are reduces then fα cut off frequency also reduces.
=
101 Q BJT act as a amplifier, when in active region.
h ib = 99.01Ω
130. The bandwidth of an n-stage tuned amplifier,
with each stage having a bandwidth of B, is
given by
(a) B/n (b) B / n
(c) B 21/ n − 1 (d) B / 21/ n − 1
As |VCB| are increases then with of potential barrier at
collector base junction is going to increases. Then Base
GATE-1993 width are reduces which base current reduces and
Ans. (c) : Given, collector current IC will be increases.
Q Bandwidth of independent stage = β
DB
n-state tuned Amplifier, such of cascaded n number, fα =
πWB2
Q By using cascading, gain will be increases but 132. A Darlington stage is shown in the figure is, if
bandwidth decreases. the trans-conductance Q1 is gm1 and Q2 is gm2,
So, then the overall trans-conductance gm is given
as a going to more and more number of stages, by
bandwidth are going to reduces further and further but
gain will be increases. Bandwidth lesser than the
previous value. If Assume that all stage connect to
identical nature,
( BW )n = B
1
2 n −1
because 21/ n − 1 < 1 For n > 1
If n = 1 1 (a) gm1 (b) 0.5 gm1
n=2 0.643 (c) gm2 (d) 0.5 gm2
n=3 0.510 GATE-1996
Ans. (c) : Given,
A 2 + A3 + .... A 22 + A32 + .....
Trans-conductance, g m1 and g m2 (a) (b)
A1 A1
IC1 I C2
Q g m1 = , g m2 = A 22 + A32 + ..... (A 22 + A32 + .....)
Vbe1 Vbe2 (c) (d)
Q Combined trans-conductance, A12 + A 22 + A 32 ..... A1
I C2 GATE-1998
g mc = Ans. (b) : Given, Distorted sinusoidal has the amplitude
Vbe1 + Vbe2
'A' Assume, A2, A3, ............
I C2 for linear circuit,
g mC = If (Vbe1 = Vbe2 )
2Vbe2
g m2
g mC = = 0.5g m2
2 And for non linear circuit,
But for ideal transistor, It is answer incorrect.
I b ∝ Vbe ⇒ I b = Ib1 e Vbe / ηVT
IC ∝ I b ⇒ IC = βI b
Q For non linear output voltage,
V0 = A1Vm sin ωt + A 2 Vin2 + A 3 Vin3 + ....
↓ ↓
2nd 3rd
So, Total harmonic distortion,
A 22 + A32 + ......
=
A1
And, Vbe2 ≠ Vbe1
134. A multistage amplifier has a low-pass response
with three real poles at s = – ω1, – ω2 and ω3. The
approximate overall bandwidth B of the
amplifier will be given by
1 1 1 1
(a) B = ω1 + ω2 + ω3 (b) = + +
B ω1 ω2 ω3
(c) B = (ω1 + ω2 + ω3)1/3 (d) B = ω12 + ω22 + ω33
GATE-1998
QβI b2 = β(1 + β)I b1 Ans. (b) : As we know, the approximate overall
bandwidth of the amplifier,
Vbe1 = I b1 R i .....(i)
1 1 1 1
Vbe2 = I b2 .R i = + +
B ω 1 ω 2 ω3
= Ie1 R i Cascading of amplifier result in decrease of higher cut
off frequency and increase in lower out-off frequency
= (1 + β ) I b1 R i ......(ii)
f H ↓ an f L ↑
If, Assume from equation (i) and (ii),
BW = f H − f L
Vbe2 = (1 + β) Vbe1
So, bandwidth will be decrease BW ↓
So, Total trans-conductance
135. In the cascode amplifier shown in the figure, if
I (Combined) the common-emitter stage (Q1) has a trans-
gm = c
Vbe (Combined) conductance gm1, and the common base stage
I C2 (Q2) has a trans-conductance gm2, then the
= ≅ g m2 overall trans-conductance g (=i0/Vi) of the
Vbe1 + Vbe2 cascode amplifier is
g m (overall) = g m2
133. A distorted sinusoid has the amplitude, A1 , A2 ,

A3 , .... of the fundamental, second harmonic,
third harmonic, ..... respectively. The total
harmonic distortion is
(a) gm1 (b) gm2
g g
(c) m1 (d) m2 (a)
2 2
GATE-1999
Ans. (a)
(b)
(c)
For Transistor Q1,

ic
gm1 = 1 .....(i)
Vi
and for transistor Q2, (d)
i
g= 0
Vi
Q Transistor are ground, i 0 = i c1 = i e1 GATE-2002
Ans. (b) : Given,
i e1
So, g = ......(ii) Three identical RC-coupled transistor amplifiers are
Vi cascaded.
from equation (i) and (ii) Cascading amplify always result in-
g = g m1 • Increases gain and
Therefore the trans-conductance of the cascode • Bandwidth will be decrease.
amplifier is g m1 . Q BW = f H − f L
136. The current gain of a BJT is So, BW ↓= (f H − f L ) ↓
gm
(a) gmro (b) Given, fL = 20H and fH= 1kHz for single stage, n = 3
ro
fL 20
gm So, f L = = = 39.2Hz
(c) gmrπ (d) 2 −1
1/ n
2 −1
1/ 3
rπ
Nagaland PSC CTSE (Degree)-2017, Paper-II f H = f H 21/ n − 1 = 21/ 3 − 1 × 1kHz = 0.5kHz
GATE-2001 138. The current ib through the base of a silicon npn
Ans. (c) : In π model, hfe is referred to β. transistor is 1 + 0.1 cos (10000 π t) mA. At 300
Q Current gain of a BJT β = ri g m K, the rπ in the small signal model of the
Where r = r transistor is
i π
β = rπ g m
137. Three identical RC-coupled transistor
amplifiers are cascaded. If each of the
amplifiers has a frequency response as shown
in the figure, the overall frequency response is
as given in
(a) 250 Ω (b) 27.5 Ω
(c) 25 Ω (d) 22.5 Ω
GATE-2012
Ans. (c) : Given,
ib = 1+0.1 cos (10000 πt) mA
DC current IB = 1mA

(c) Collector current is to be constant
(d) Base current is to be constant
Ans. (a)
rπ = small signal resistance between base to emitter,

Vbe
rπ = ....(i) Vbe = h iei b + h re Vce
ib
For a BJT amplifier mode, i c = h fei b + h oe Vce
Ic  Ie = I0 (eVbe / ηVT ) .....(ii) If d.c. base current ib=0 then, hre and hoe can be solved.
V
Total Instantaneous current (DC+AC) is, h re = be ( at i b = 0 )
i C = i C + IC = I0 (e VBE / ηVT ) = I0 (e(Vbe + VBE ) / VT ) Vce
And h oe = i c / Vce (at ib = 0)
i C = I0 .eVBE / VT .eVbe / VT = i b + IC (IC= DC collector
current) 142. The ideal value of stability factor of a biasing
Sine, Vbe << VT, circuit for transistor is:
(a) 0.7 (b) 1
 V 
IC 1 + be  = i C + IC (c) 2 (d) 10
 VT  OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
V Ans. (b) : Stabilization is about making the Q-point
IC . be = i C independent of changes in temperature and changes in
VT transistor parameters.
IC i  IC  If ICO, VBE and β changes simultaneously then net
= C Q g m =  change in IC.
VT Vbe  VT 
∂I ∂I ∂I
So, ∆IC = C ∆Ico + C × ∆VBE + C ∆β
∂ICO ∂VBE ∂B
iC I
gm = = C ............(iii) ∂IC
Vbe VT Where, = S → current stability factor
From equation (i), (ii) and (iii) ∂ICO
V VT Sideal = 1
rπ = T = (Q VT = 25mV )
I B dc current
25mV
rπ = = 25Ω
(iv) Analysis of FETs circuits
1mA
139. In the high frequency hybrid-π model of a CE 1. The source of a silicon (ni=1010 per cm3) n-
transistor, the conductance gbe is channel MOS transistor has an area of 1 sq µm
(a) hfe/gm (b) gm/hfe and a depth of 1 µm. If the dopant density in
(c) gm/hie (d) hie/gm the source is 1019/cm3, the number of holes in
the source region with the above volume is
Nagaland PSC- 2018, Diploma Paper-II approximately
Ans. (b) : For common emitter amplifier - (a) 107 (b) 100
(c) 10 (d) 0
g
the input conductance g be = m BPSC Asst. Prof. - 12.04.2022
h fe GATE-2012
140. A transistor has hfe = 50, its hfc will be Ans. (d) : Given,
(a) –50 (b) +50 ni = 1010/cm3
A = 1×10–12 m2
(c) –51 (d) +51
d = 10–6m
Nagaland PSC CTSE- 2015, Paper-II Volume of given device,
Ans. (c) : Given hfe = 50 V = A ×d
Q hfc = –(1+hfe) = – (1+50) = –51 V = 10–12×10–6
V = 10–18m3
141. The condition necessary to calculate hoe of
V = 10–12cm3
transistor is that For the semiconductor-
(a) D.C. base current is to be zero
n i2 = n 0 p 0
(b) Base to emitter voltage is to be constant
n i2 1020 Ans. (c) : According to figure we can say that drain is
P0 = = = 10 / cm3 shorted to gate so that's why both MOSFETs are in
n 0 1019 saturation region.
so total number of holes is, So,
P = P0×V I DSN = ISDP
= 10 ×10–12
µ n Cox  W  µ C W
= 10–11 ×   ( VGSN − VTN ) = P ox   ( Vgs − ( VT ) )
2 2
which is approximately equal to zero. 2  L n 2 L

2. A FET has a drain current of 4 mA. If IDSS = 8
300 × 1( V0 − 1) = 40 × 5 ( 4 − V0 − 1)
2 2
mA, VGS(off) = – 6V. The value of VGS will be
(a) – 6 V (b) – 1.76 V 3 ( V02 + 1 − 2V0 ) = 2 ( 9 + V02 − 6V0 )
(c) – 5.24 V (d) – 1.5 V
UPPSC ITI Principal/Asstt. Director-09.01.2022 V02 + 6V0 − 15 = 0
Ans. (b) : As given that, 6 ± 36 + 4 × 15
VGS( off ) = −6V = VP V0 =
2
I D = 4mA, I DSS = 8mA V0 = 1.898V, − 7.89V ( Vo can not − ve )
2
 VGS  ∴ V0 = 1.8V  2V
I D = I DSS 1 − 
4. Consider an ideal long channel nMOSFET
 VGS( OFF) 
(enhancement-mode) with gate length 10 µm
and width 100 µm. The product of electron
2
 V 
4mA = 8mA 1 − GS  mobility (µn) and oxide capacitance per unit
 −6 
2
are (Cox) is µnCox = 1 mA/V2. The threshold
1  VGS  voltage of the transistor is 1 V. For a gate-to-
= 1+
2  6  source voltage VGS = [2 – sin (2t)] V and drain-
to-source voltage VDS = 1 V (substrate
1  VGS  6 + VGS
= = 1 +  = 0.707 = connected to the source), the maximum value of
2  6  6 the drain-to-source current is _______.
4.242 = 6 + VGS (a) 40 mA (b) 20 mA
VGS = 4.242 − 6 (c) 15 mA (d) 5 mA
= –1.758V GATE-2022
 −1.76 V Ans. (c) : Given, µ n C ox = 1mA / V 2 , VT = 1V
3. Consider the CMOS circuit shown in the figure W
(substrates are connected to their respective VDS = 1V, = 10 µm
L
sources). The gate width (W) to gate length (L)
VGS = [ 2 − sin 2t ]
W
ratios   of the transistors are as shown.
 L  VGS = 2 − 1 = 1V
GSmax = 2 − ( −1) = 3V
Both the transistors have the same gate oxide V
capacitance per unit area. For the pMOSFET,
the threshold voltage is –1 V and the mobility VDS = 1V
cm 2 VDS < VGS − VT [ for linear ]
of holes is 40 .
V.s W
( VGSmax − VT ) VDS − VDS2 
1
For the nMOSFET, the threshold voltage is 1 V I D max = µ n Cox 
L 2 
cm 2
and the mobility of electrons is 300 .  1 
V.s ⇒ 1mA / V 2 ×10  2 − 
The steady state output voltage V0 is _______.  2
= 10 [1.5]
= 15mA
5. In the circuit shown in the figure, the
transistors M1 and M2 are operating in
saturation. The channel length modulation
coefficients of both the transistors are non-
zero. The transconductance of the MOSFETs
(a) equal to 0 V (b) more than 2 V M1 and M2 are gml and gm2, respectively, and
(c) less than 2 V (d) equal to 2 V the internal resistance of the MOSFETs M1
GATE-2022 and M2 are ro1 and ro2, respectively.
Replace M2 with small signal model.
Vout −g m2 Vgs ( r02 || R eq )

Ignoring the body effect, the ac small signal
 ∂V  =
voltage gain  out  of the circuit is Vin Vgs
 ∂Vin 
 1 
 1  A V = −g m2  r02 || || r01 
(a) –g m2  ro2  (b) –g m2 ( ro1 ro2 )  g m1 
 ml
g 
6. For an n-channel silicon MOSFET with 10 nm
 1   1  gate oxide thickness, the substrate
(c) –g m2  ro1 ro2  (d) –g ml  ro1 ro2 
 g ml   g m2   ∂VT 
sensitivity 
 ∂ V 
is found to be 50 mV/V at a
GATE-2021  BS 
Ans. (c) : MOSFET M2 acts as common source substance voltage VBS = 2V, where VT is the
amplifier.
threshold voltage of the MOSFET. Assume
that, VBS >> 2φB , where qφB , is the separation
between the Fermi energy level EF and the
intrinsic level Ei in the bulk. Parameters given
are
Electron charge (q)=1.6×10–19C
Vacuum permittivity ( ε 0 ) =8.85×10–12F/m
Relative permittivity of silicon ( εsi ) = 12
Relative permittivity of oxide ( εox ) = 4
The doping concentration of the substrate is
(a) 7.37×1015 cm–3 (b) 4.37×1015 cm–3
Drain to gate connected MOSFET M1 acts as load. 15
(c) 2.37×10 cm –3
(d) 9.37×1015 cm–3
Gate and drain are shorted of MOSFET, we can replace GATE-2021
directly MOSFET by resistance.
Ans. (a) :
VT = VT0 + γ ( | VBS | + | 2φB | − | 2φB | ) ....(i)
VT0 → Threshold voltage |VBS | = 0V
2εs qNa
γ= ……(ii)
ε0x
dVT γ
= = 50mV / V .....(iii)
d | VBS | 2 | VBS | + | 2φB |
For given circuit AC equivalent is as shown. γ
50 × 10−3 V / V = (Q| VBS |>>| 2φB |)
2 2
γ = 0.141
From equation (iii)
2εs qNa t ox 2εs qNa
γ= =
εox εox
t ox
t ox 2εs qNa
γ= ..(iv)
εox

t 
2 tox = 500×10–10 m = 500×10–10 ×39370mil
γ =  ox  .2εs q.Na
2
= 1.97×10–3 mil
 εox  8.99 × 10−16 F / mil
2 Cox =
ε  1 1.97 × 10−3 mil
Na = γ 2  ox  .
 ox 
t 2 ε sq = 4.56×10–13 F/mil2
= = 0.456 ×10–12 F/mil2
2
 4 × 8.854 × 10−14  1 Cox = 0.4PF / mil2
(0.14) 2 .  −9 2  −4
 10 × 10 × 10  2 × 12 × 8.854 × 10 ×1.6 × 10−19
9. For enhancement-type n-channel MOSFET
Na = 7.329 ×1015 cm −3 with drain current ID =10 mA, VGS = 8 V and
7. Maximum drain current IDSS for FET is define VT = 2 V, the device constant k is
when (a) 0.139 mA V 2 (b) 0.278 mA V 2
(a) Vgs = Vds and Vds>Vp
(b) Vgs ≠ 0 and Vds > Vp (c) 0.387 mA V 2 (d) 0.556 mA V 2
(c) Vgs = 0 and Vds > Vp ESE-2021
(d) Vgs > 0 and Vds <Vp Ans.(b) : Let us assume that MOSFET is biased in the
RPSC ACF & FRO 23.02.2021 saturation region-
2
 V  I D = K ( VGS − VT )
2
Ans. (c) : I D = I DSS  1 − GS 
 VP 
Given, I D = 10mA
For maximum drain current-
VGS = 8V
VGS = 0
ID = IDSS VT = 2V
and ID 10 × 10−3
VDS > |VP| K= =
( VGS − VT ) (8 − 2 )
2 2
The region between VP and VDS(max) (breakdown
voltage) is called the constant current region or active
K = 0.278 × 10 −3
region.
∴ This device constant K is 0.278mA V 2
10.
8. A monolithic metal oxide semiconductor

(MOS) non-polarized capacitor which is a
parallel plate capacitor with SiO2 as dielectric.
A surface thin film of metal (aluminum) is the
top plate. The bottom plate consists of the
heavily doped n* region that is formed during
emitter diffusion. What is the typical value of
capacitance for an oxide thickness of 500 Å of
this MOS capacitor?
Take the permittivity of dielectric (εr) as 4.
(a) 0.1 pF/mil2 (b) 0.2 pF/mil2
2
(c) 0.3 pF/mil (d) 0.4 pF/mil2 In the above circuit ID is
ESE-2021 2
 VGS 
εox (a) I D = I DSS 1 − 
Ans.(d) : MOS capacitor Cox =  VGS( off ) 
t ox  
ε ox = 4 × 8.85 × 10−12 F / m  VGS 
= 4×8.85×10–12 F/39370 mil (b) I D = I DSS 1 − 
{Q 1m = 39370mil}  VGS( off ) 
= 8.99 ×10–16F/mil  

 VGS 
VGS –VTh = 1–0.5 =0.5V
(c) I D = I DSS 1 −  For t > 0 S1 is open and S2 is closed so
 VDS( off ) 
  VGS = 3 – 4 = –1V
2 then Vth > VGS that MOSFET is OFF condition
 VGS 
(d) I D = I DSS 1 −  So drain current ID = 0µA
 VDS( off ) 
  12. An n-channel MOS transistor is made on a p-
DMRC AM S&T-2020 type substrate with Na = 1015 cm–3 find
2 approximate depletion charge per unit area
 V  (Qd) at strong inversion.
Ans. (a) : I D = I DSS 1 − GS 
 VGS( off ) 
  {
ln(10) = 2.3, 0.046  0.215,n i = 1010 cm −3 }
11. In the given circuit, S1 switch remains closed (a) –6.9×10–8 C/cm2 (b) 6.9×10–8 C/cm2
and S2 remains open for the long time. At t = 0, –8
(c) –3.4×10 C/cm 2
(d) 3.4×10–8 C/cm2
S1 opens and S2 closes and remain in this ISRO Scientist Engg. -2020
position for the long time. Find drain current
for t < 0 and t >> 0 respectively if, µnCox = 100 Ans. (c) : Given,
µA/ V2 and aspect ratio = 2. ln (10) = 2.3, 0.046 = 0.215, n i = 1010 cm −3
N a = 1015 cm–3
Q d = −2 εsi qN A φF
Where,
εsi = 11.7ε 0 = 11.7 × 8.85 ×10 −14 F / cm
εsi = 103.545 × 10−14 F / cm
kT  N A 
φF = ln  
q  ni 
(a) 600 µA, 0 µA (b) 600 µA, 25 µA
KT
(c) 600 µA, –25 µA (d) 0 µA, 600 µA at room temperature = 25ºC is 26mV
ISRO Scientist -2020 q
Ans. (a) : Threshold voltage (Vth) = 0.5V φF = 0.299V
µ n Cox = 100 µA/V2
W Q d = −2 103.545 × 10−14 ×1.6 × 10−19 ×1015 × 0.299V
aspect ratio   = 2
L Q d = −1.4 ×10 −8 C / cm 2
For t < 0 Q d  −3.4 ×10 −8 C / cm 2
Switch S1 is closed and S2 is open
VGS = VG–VS 13. For a p-channel Si FET, Na = 3×1016 cm–3, Nd
= 3V– 0 = 1018 cm–3. Channel thickness dimension is a =
= 3V 0.33 µm. Find approximate pinch-off voltage
VDS = 2–0 = 2V Vp. {ni = 1010 cm–3, VT = 26 mV, ln (3) = 1.098}.
VGS –Vth = 2.5V (a) 2.5 V (b) 1.7 V
VDS < (VGS–Vth) (c) 4.2 V (d) 3.6 V
MOSFET operates in linear region then current across ISRO Scientist Engg. -2020
MOSFET will be Ans. (b) : Given,
VT = 26mV
 W  V2 
I DS = µ n Cox   ( VGS − VTh ) VDS − DS  ln = 1.098
 L  2  ni = 1010cm–3
 ( 2)  Channel thickness dimension (a) = 0.33µm
2
= 100 × 2  2.5 × 2 −  N a = 3 × 1016 / cm3 = 3 × 10 22 / m3

 2 
N d = 1018 / cm3
= 200 × 3
IDS = 600µA Pinch off voltage (VP) =
That case VD = 4V, VS = 2V qN a a 2
− Vbi
VDS = VD–VS 2ε
= 4–2 = 2V N N
VGS = VG –VS Vbi = VT l n a 2 d
= 3–2 = 1V ni

3 × 1016 ×1018 Ans. (b)
Vbi = 26 × 10−3 ln
(10 ) 10 2
3 ×1034
= 26 × 10−3 ln
1020
−3
= 26 × 10 ln 3 × 1014
= 0.866V
qN a a 2 Given, gm = 4mA/V
VP = − 0.866V
2ε rds = 40kΩ
=
(1.6 ×10 ) × 3 ×10
−19 16
(0.33 × 10 −6 ) 2
− 0.866V
RD = 10 kΩ
RS = 50 Ω, Cgs = 4pF, Cgd = 2pF
2 × 8.854 × 10 −14 ×11.7 1 1 1
1.6 × 10−19 × 3 ×1022 × 0.1089 × 10−12 = +
= − 0.866V R L R D rds
17.7 × 10−12 × 11.7 1 1 1
522.72 = +
= − 0.866V R L 10 40
207.09
RL = 8 kΩ
 1.7V
Voltage gain AV = –gm. RL
14. In a MOSFET, SiO2 breaks down at electric = −4mA / V × 8kΩ
field of the order of 5×106 V/cm. For a gate = –32A/V
oxide of thickness 1000 Å and channel
thickness of 2 µm, what is the maximum VGS it Input capacitance Ci = {Cgs + (1+ | A V |)Cgd }
= {4 + (1+ | −32 |) 2}
can withstand?
(a) 5 V (b) 10 V
(c) 100 V (d) None of the above = 4+(2+64)
ISRO Scientist Engg. -2020 = 4+66
Ans. (d) : Given, = 70pF
Electric field (Eox) = 5×106 V/cm 1
input frequency f in =
o
oxide thickness (tox) = 1000 A = 1000×10–8cm 2πCin .R in
channel thickness (tchannel) = 2µm R in = R S || ∞
V 1 1 1
Electric field (Eox) = ox = +
t ox R in 50 ∞
Vox Rin = 50Ω
5 × 106 =
1000 × 10−8 f in =
1
Hz
Vox = 5 × 106 ×1000 × 10−8 2 × 3.14 × 70 ×10−12 × 50
Vox = 5 ×109 ×10 −8 1000
f in = × 106 Hz
Vox = 50V 21.98
VGS = Vox + φS f in = 45.5MHz
Q φS is surface potential is not given 16. For a MOSFET satisfying the relationship
Hence VGS cannot be calculated. VDS < VGS - VTH , where the drain voltage is VDS,
15. For the given amplifier circuit, find the input the gate voltage is VGS, and the threshold
cut-off frequency. FET parameters are gm = voltage of the transistor is VTH, then the
4mA / V, Cgs = 4 pf, rds = 40 kΩ, Cgd = 2pF. transistor is said to operate in:
(a) Pinch off (b) Saturation
(c) Cut off (d) Triode region
UPMRC AM - 2020
Ans. (d) : We know that MOSFET operation in three
regions
(i) Cut off region
(ii) Triode/ohmic region
(iii) Saturation region
(a) 35.5 MHz (b) 45.5 MHz (i) Cut off region → VGS < Vth
(c) 90.5 MHz (d) 10.5 MHz
ISRO Scientist Engg. -2020 I D = 0
(ii) ohmic/ Triode region ⇒ VGS > Vth 18. In a direct-coupled FET switching circuit, RG =
2.2kΩ and VDS(on) = 200 mV. If a 2N4856 FET
VDS < VGS − Vth
is used with a 12V supply, calculate the value of
Current equation in ohmic region is RD (for 2N4856, rDS (on) = 25Ω).
W
I D = µ n Cox (a) 3.5kΩ
L (b) 2.5kΩ
 2
VDS  (c) 5.5kΩ
( VGS − Vth ) VDS − 
 2  (d) 1.5kΩ
(iii) Saturation region : VGS > Vth APPSC POLY. LECT. 14.03.2020
VDS > VGS − Vth Ans. (d) : Given, RG = 2.2 kΩ, VDS(on) = 200mV
The current equation for MOSFET in saturation is Q Supply voltage = 12V
1 W R DS( on ) = 25Ω
I D = µ n Cox ( VGS − Vth )
2
2 L
So option (d) Triode region is correct Answer.
17. A MOSFET is biased at a drain current of
0.5mA. If µn Cox = 100µA/V2. W/L = 10, and λ =
0.1V–1, the intrinsic gain gmr0 will be:
(a) 1 (b) 10
(c) 20 (d) 0.05
UPMRC AM - 2020
Ans. (c) : In saturation region the drain current of
MOSFET is
W
I D = µ n Cox   ( Vgs − VT )
1 2
2  L VDS( on )
The trans-conductance gm Drain current ( I D ) =
R D( on )
∂I W
g m = D ⇒ µ n Cox   ( Vgs − VT ) 200mV
∂Vgs  L =
25
The O/P resistance ( r0 ) is. = 8mV
V So, when used the supply voltage 12V, then drain
r0 = A
ID resistance in 2N4856 FET.
12
 1  RD =
V =
 A λ = 10  8 × 10−3
= 1.5kΩ
Now
19. The transconductance gm of an FET in the
W
I D = µ n Cox   ( Vgs − VT )
1 2
saturation region equals
2  L 2
-2I DSS  VGS  -2I DSS  VGS 
I D = 100µ × 10 ( Vgs − VT )
1 2 (a) 1-  (b) 1- 
2 VP  VP  VP  VP 
(V − VT ) = 1 -2I DSS  VGS 

1/2
I
[ I DSS X I DS ]
gs 1/2
(c) 1-  (d)
So now gm will be VP  VP  VP
∂I W
g m = D ⇒ µ n Cox   ( Vgs − VT ) ISRO Scientist Engg.-2011
∂Vgs  L Ans. (a) : VGS( off ) = Vp ( ID = 0 )
g m = 100 ×10 −6 ×10 × 1 ⇒ 10−3 S FET-
V 10  V 
2
r0 = A = = 20kΩ
ID 0.5mA I D = I DSS 1 − GS 
 Vp 

The intrinsic gain of MOSFET = g m r0
Where, I DSS = Saturation drain current
= 10 −3 × 20 × 103
= 20 And I DS = I DSS ( When VGS=0 )

22. The given figure shown a composite transistor
consisting of a MOSFET and a bipolar
transistor in cascode
Q Trans-conductance,
ID
gm = The MOSFET has a trans conductance gm of 2
VGS
( )
VDS = constant
mA/V and the bipolar transistor has β  h fe of
Where gm unit = mA/Volt or A/V (mho)
∂  VGS  1 99. The overall trans conductance of the
gm = 1 − ×− composite transistor is
∂VGS  Vp  Vp
(a) 198 mA/V (b) 19.8 mA/V
 V  1 (c) 1.98 A/V (d) 1.98 mA/V
= 2IDSS 1 − GS  × − IES-1999
 Vp  VP
Ans. (d) :
−2I DSS  VGS 
gm = 1 − 
VP  VP 
20. For an n-channel MOSFET, if condention
parameter (k n ) is 0.249 mA/V 2 , gate to source
voltage VGS is 2VIN where VIN = 0.75V. The
current will be output current
(a) 0.160 mA (b) 0.150 mA gm =
Input voltage
(c) 0.140 mA (d) 0.170 mA
ISRO Scientist Engg.-2016 Where g m = Trans-conductance
Ans.(c): Given value, αI
Condention parameter (kn) = 0.249 mA/V2 gm = E ( I E = ID )
Vgs
Gate to source voltage VGS = 2VIN
Where VIN = 0.75V, ∵ connected Emitter to the drain of MOSFET
µ n = field-limited electron mobility  I  I
gm = α  D  ∵ D = 2m A V
Condition, VDS >> VGS − VT V  Vgs
 gs 
Then,
 β 
I D = k n ( VGS − VIN ) gm =   × 2m A V
2
 1+ β 
I D = 0.249 × 10−3 × [ 2 × 0.75 − 0.75]
2
99
= × 2 = 1.98m A V
 3 100
= 0.249 × 10 –3 × ( 0.75) =
2
 0.75 
 4 g m = 1.98m A V
9
= 0.249 × × 10 –3
 I 
16 Q IC = h fe IB = h fe  E 
I D = 0.140mA  1 + h fe 
21. The relation between ID and VGS in FET is h fe
(a) ID = IDSS (1-VGS/VP) (b) ID=IDSS (1-VGS/VP)2 IC = × (−g m VGS )
1 + h fe
(c) ID = IDSS (VGS/VP) (d) ID =IDSS (1-VP/VGS)
Mizoram PSC AE/SDO 2012-Paper-I IC h 99
= fe × g m = × 2mA / V
Ans. (b) : IDSS is drain to source current Vin 1 + h fe 1 + 99
2
 V  g m1 =
IC
=
99
× 2 = 1.98mA / V
I D = I DSS 1 − GS  Shockley’s equation
 VP  Vin 100

23. If the transconductance of MOSFET is 10 28. Consider an n-channel MOSFET with
mmho and its drain resistance is 3KΩ, its parameters Kn = 0.25 mA/V2, VTN = 1V, λ = 0,
voltage gain is Cgd = 0.04 pF and Cgs = 0.2 pF
(a) 0.3 (b) 3 If the transistor is biased at VGS = 3V, the unity
gain bandwidth of an FET will be
(c) 3.3 (d) 30
(a) 626 MHz (b) 646 MHz
Mizoram PSC AE/SDO 2012-Paper-I (c) 663 MHz (d) 683 MHz
Ans. (d) A V = g m R d IES-2020
AV = 10 ×10-3 ×3 ×103 Ans. (c) : Given- K n = 0.25mA / V 2
A V = 30 VTN = 1V
λ=0
24. gm of MOSFET is controlled by Cgd = 0.04 PF
(a) gate-source voltage
(b) drain-source voltage Cgs = 0.2 PF
(c) drain current Unity gain bandwidth FET will be-
(d) gate current gm
=
Mizoram PSC AE/SDO 2012-Paper-I 2π ( Cgs + Cgd )
Ans. (a) : Where, gm = 2k n ( VGS − VTN )
IDSS  VGS  g m = 2 × 0.25 × 10 –3 ( 3 − 1)
gm = 2 1 − 
| VP |  VP 
g m = 10−3
Hence gm can be controlled by gate to source voltage.
gm
Gain bandwidth FET =
2π ( Cgs + Cgd )
25. The drain resistance of JFET is
(a) 1/gm (b) µ/gm
(d) µ gm gm
(c) gm/µ =
Mizoram PSC AE/SDO 2012-Paper-I 2π ( 0.2 + 0.04 ) × 10–12
Ans. (a) : The drain resistance of JFET is the ratio of 10−3
∆VDS and ∆ID . = = 663.48
2π × 0.24 × 10–12
The drain-source channel resistance-
 663 MHz
∆VDS
R DS = 29. A CMOS amplifier when compared to an N
∆ ID
channel MOSFET has the advantage of
1 (a) Higher cutoff frequency
R DS = (b) Higher voltage gain
gm
(c) Higher current gain
26. As compared to transistor amplifier JFET (d) Lower power dissipation
amplifier has Nagaland PSC CTSC (Degree-2017) Paper-1
(a) Higher voltage, less input impedance IES-2015
(b) Less voltage gain, less input impedance Ans. (d) : The two important characteristics of CMOS
(c) Less voltage gain, higher input impedance device are high noise immunity and low power
dissipation.
(d) Higher voltage gain, higher input impedance
Ans. (c) : As compared to transistor amplifier JFET has
less voltage gain and higher input impedance.
27. The best location for setting a Q-point on dc
load line of an FET Amplifier is at
(a) Saturation point (b) Cutoff point
(c) Mid-point (d) None of these
Ans. (c) : The Q-point is the operating point of the CMOS devices dissipate less power than NMOS
transistor. It is selected in the middle of the active devices because the CMOS dissipates power only when
region because it gives maximum possible amplification switching, whereas N-channel MOSFET dissipates
to input sinusoidal signal without any distortion in power whenever the transistor is on because there is a
positive or negative half cycle. current path from VDD to Vss.
30. The transistors T1 and T2 shown in figure have The logic levels are not dependent upon the relative
a threshold of 1 volt. The device parameters K1 device sizes so that the transistors can be a minimum
and K2 of T1 and T2 are 36 µA/V2 and 9µA/V2 size.
respectively. The output voltage is nearly. Hence the property 1, 2 and 3 are true.
32. In a CMOS CS amplifier, the active load is
obtained by connecting a
(a) p channel current mirror circuit
(b) n channel transistor
(c) p channel transistor
(d) BJT current mirror
IES-2009
(a) 1 V (b) 2 V Ans. (a) : In a CMOS CS Amplifier, the active load is
(c) 3 V (d) 4 V obtained by connecting a P-channel current mirror
ISRO Scientist Engg.-2016 circuit.
IES-2015 33. Which one of the following gain equations is
Ans. (c) For saturation condition- correct for a MOSFET common-source
VDS ≥ ( VGS − Vth ) amplifier? (gm is mutual conductance, and RD
is load resistance at the drain)
The drain and gate are shorted for both the transistor-
(a) AV = gm/RD (b) AV = gmRD
VDS ∝ ( VGS − Vth )
2
(c) AV = gm/(1 + RD) (d) AV = RD/gm
Current is same in both transistor- IES-2007
36 ( 5 − Vo − 1) = 9 × ( Vo − 1)
2 2 Ans. (b)
−g m rd R D
6 ( 5 − Vo − 1) = 3 ( Vo − 1) AV =
rd (1 + R D rd )
30 − 6Vo − 6 = 3Vo − 3 µ=g r m d
24 + 3 = 3Vo + 6Vo g m → mutual conductance
9Vo = 27 R D → Load Resistance at drain.
27
Vo = AV = gmR D
9
Vo = 3V 34. What is the main advantage of a JFET-cascade
amplifier?
31. Consider the following statements about (a) High voltage gain
CMOS: (b) Low output impedance
1. CMOS logic inverter has maximum signal (c) Very low input capacitance
swing of 0V to VDD. (d) High input impedance
2. The output signal swing is independent of IES-2006
exact value of aspect ratio and other device Ans. (a) : There are two primary advantages of cascade
parameters. Amplifier increased gain and input, and o/p impedance
3. It is a fast switching device with the noise flexibility the need for the gain provided by cascade
margins Amplifier is paramount to the functionality of various
4. It has zero input resistance and infinite applications.
output resistance. 35. In an FET common-source high frequency
Which of these statements are correct? amplifier, which one of the following is the
(a) 1, 2, 3 and 4 (b) 1, 2 and 4 only correct expression for input capacitance?
(c) 1, 3 and 4 only (d) 1, 2 and 3 only (a) Ci = Cgs + (1 – AV) Cgd
IES-2011 (b) Ci = Cgs + (1 – 1/AV) Cgd
Ans. (d) : The main advantage CMOS over NMOS and (c) Ci = Cgd + (1 – AV) Cgs
Bipolar technology is the much smaller power (d) Ci = Cgd + (1 – 1/AV) Cgs
dissipation. The noise margins of symmetrical inverter IES-2006
(Where PMOS and NMOS transistors have equal Ans. (a) : In common source configuration, Cgd will be
current driving strength) approach VDD/2. The steady present between the input node gate and output node
state response is not affected by layout. drain. It can be therefore replaced with Cm and Cn using
When a Low-Level voltage (<Vdd ~ V) applied to the Miller’s theorem as =
Cm = Cgd (1 − A V )
inverter, the NMOS switched off and PMOS switched
on. So the output becomes VDD.
 1  Ans. (c) Given-
Cn = Cgd 1 −  g m = 3 × 10 −3 S
 AV 
R s = 3000Ω
Cm → appears parallel with Cgs
1
The input capacitance will be- Ro =
Cin = Cgs + C m 1
gm +
Rs
Cin = Cgs + Cgd (1 − A V ) 1
=
36. The drain gate capacitance of a junction FET is −3 1
3 × 10 +
2 pF. Assuming a common source voltage gain 3000
of 20. What is the input capacitance due to 3000
Miller effect? =
9 × 10−3 × 103 + 1
(a) 21 pF (b) 40 pF
3000
(c) 42 pF (d) 10 pF =
IES-2006 10
Ans. (c) Given- AV = 20 R o = 300Ω
Cgs = 2 pF 39. Consider the following statements describing
Miller capacitance is the property of a complementary MOS
Cmi = (1 + A V ) Cgs (CMOS) inverter
1. It is combination of an n-channel FET and
= (1 + 20 ) × 2 × 10 –12
a p-channel FET
Cmi = 21× 2 × 10 –12
2. There is power dissipation when the input
carries the logical 1 signal.
Cmi = 42 pF 3. There is no power dissipation when the
input carries the logical 0 signal.
4. There is power dissipation during
We would be able to achieve broad banding in
transition from 0 to 1 or from 1 to 0.
a common source FET amplifier, by
1. Resonance between the shunt capacitance correct?
and a compensating inductance.
(a) 1, 2 and 3 (b) 2 ,3 and 4
2. RC compensating network between source
(c) 1, 3 and 4 (d) 1, 2 and 4
and drain
IES-2006
3. Connecting compensating network in
series with the coupling capacitors. Ans. (c) : The property of a complementary CMOS
Which of the statements given above is/are inverter :-
correct? (i) It is combination of an n-channel FET and a P-
channel FET.
(a) Only 1 (b) 1 and 2
(ii) There is no power dissipation when the input
(c) 1 and 3 (d) 2 and 3
carrier the logical 0 signal.
IES-2006 (iii) There is power dissipation during transition from 0
Ans. (c) : Broad Banding in a common source FET to 1 or from 1 to 0.
amplifier, by resonance between the shunt capacitance So the statements 1, 3 and 4 true.
and a compensating inductance, connecting
40. What is the value of RS required to self bias an
compensating Network in series with the coupling
N channel JFET with Vp = – 10V, IDSS = 40 mA
capacitors. and VGSQ = – 5V?
38. (a) 250Ω (b) 500Ω
(c) 750Ω (d) 1500Ω
Nagaland PSC (Degree) - 2018 Paper-II
IES-2005
Ans. (b) : Given-
VP = −10V
I DSS = 40 mA
For the circuit shown if gm = 3 × 10 and RS = VGSQ = −5V
–3
3000Ω, then what is the value of R0? Formula-

(a) 3000Ω (b) 1000/3Ω 2
 V 
(c) 300Ω (d) 100Ω I DS = IDSS 1 − GSQ 
IES-2006  VP 

 ( −5 )  Ans. (a) :
2
IDS= 40 ×  1 −  (i) Cascade connection →

 −10 
2
 1
IDS = 40 ×  1 − 
 2
(ii) Cascode connection →
1
I DS = 40 ×
4
I DS = 10mA (iii) Darlington connection →
−VGSQ
RS =
IDS
− ( −5 ) (iv) Parallel connection →
=
10 × 10−3
R S = 500Ω 43. Thermal runway is not possible in FET because
as the temperature of FET increases
41. Consider the following statement : (a) the mobility decreases
In JFET amplifiers, high frequency response
(b) the transconductance increases
can be improved by using peaking circuits
containing inductors (c) the drain current increases
1. in series with drain resistance RD. (d) the mobility increases
2. in series with the coupling capacitance IES-2001
3. as a feedback element between drain and Ans. (a) : The thermal runway is not possible in FET
gate? because as the temperature of FET increases, the
Which of the statement given above are mobility decreases.
correct? Since the current is decreasing with an increase in
(a) 1 and 2 (b) 2 and 3 temperature, the power dissipation at the output thermal
(c) 1 and 3 (d) 1, 2 and 3
of a FET decreases.
IES-2004
44. An FET is a better chopper than a BJT because
Ans. (c) : The junction field effect transistor (JFET) is a
majority charge carrier device hence. It has less Noise. it has
The coupling capacitors in series with inductors will (a) lower off-set voltage
reduce the gain. (b) higher series ON resistance
So the statements 1 and 3 are true. (c) lower input current
42. Match List-I (Circuit name) with List-II (d) higher input impedance
(Circuit diagram) and select the correct answer IES-2000
Ans. (a) : FET is a better chopper than a BJT because
List-I List-II
FET typically produces less noise than a BJT.
Relatively Immune to radiation. Exhibits no offset
A. Cascade connection 1. voltage at zero drain current.
45. In a biased JFET the shape of the channel is as
shown in the given figure
B. Cascode connection 2.
C. Darlington connection 3.
because
D. Parallel connection 4. (a) it is the property of the material used
Codes: (b) the drain end is more reverse biased than
A B C D source end
(a) 1 2 3 4 (c) the drain end is more forward biased than
(b) 2 1 3 4 source end
(c) 1 2 4 3 (d) the impurity profile varies with the distance
(d) 2 1 4 3 from source
IES-2001 IES-1999
Ans. (b) : When applied gate to source voltage is zero
(0) the maximum drain current will flow through JFET.
As you increase the gate to source voltage the reverse
biasing will increase at the drain side as drain in move
positive than source. Hence penetration of depletion
region is more at the drain side.
46. A three-terminal monolithic IC regulator can
be used as (a) The amplitude as well as the frequency of the
(a) an adjustable output voltage regulator alone waveform will get doubled.
(b) The amplitude will get doubled but the
(b) an adjustable output regulator and a current
frequency will reduce to half its value.
regulator
(c) The amplitude will get doubled but the
(c) a current regulator and a power switch frequency will remain unchanged.
(d) a current regulator alone (d) The Amplitude will remain unchanged but the
IES-1999 frequency will get double.
Ans. (a) : A three-terminal monolithic IC IES-1995
regulator can be used as an adjustable output voltage Ans. (c) :
regulator alone.
answer using the codes given below the lists:
List-I List-II
(Name of the (Special
electronic circuit) characteristics)
A. Darlington amplifier 1. Low input The change in the voltage wave form across capacitor,
the Amplitude will get doubled but the frequency will
impedance
remain unchanged.
B. Cascade amplifier 2. Low output
49. The JFET in the circuit shown in figure has an
(FET) impedance
IDSS = 10 mA and VP = –5 V. The value of the
C. Common gate 3. Low input resistance RS for a drain current IDS = 6.4 mA
amplifier capacitance but is (select the nearest value)
high Rin
D. Differential amplifier 4. Large common
mode rejection
ratio.
Codes:
A B C D
(a) 1 2 3 4 (a) 150 ohms (b) 470 ohms
(c) 560 ohms (d) 1 kilo ohm
(b) 1 2 4 3
GATE-1992
(c) 2 1 3 4
Ans. (a) : Given-
(d) 2 3 1 4
I DSS = 10mA
IES-1996
Ans. (d) : VP = −5V
List-I List-II I DS = 6.4mA
Darlington Amplifier - Low output Impedance. RS = ?
Cascade Amplifier - Low input capacitance but 2
high Rin.  V 
I DS = IDSS 1 − GS 
Common gate Amplifier - Low input Impedance  VP 
Differential Amplifier - Large common mode 2
rejection ration.  V 
6.4 ×10−3 = 10 × 10−3 1 − GS 
48. In the circuit of the relaxation oscillator shown  VP 
in the given figure, what will be the change in 2
 V 
the voltage waveform across capacitor, if the 6.4 = 10 1 − GS 
voltage V is doubled?  VP 

2 51. In the MOSFET amplifier of the figure is the
 V 
6.4 = 10 1 − GS  signal output V1 and V2 obey the relationship
 −5 
2
64  VGS 
= 1 − 
100  −5 
8  VGS 
= 1 − 
10  −5 
8 V
− 1 = GS V2 V2
10 5 (a) V1 = (b) V1 = −
−2 VGS 2 2
= (c) V1 = 2 V2 (d) V1 = –2V2
10 5
GATE-1998
10
− = VGS Ans. (c) : The signal output V1 and V2 obey the
10 relationship-
VGS = −1 V1 = I D R D
−VGS IS = I D
Rs =
I DS R D I D R D V1
V2 = IS = =
1 2 2 2
= V1
6.4 × 10−3 V2 =
2
10000
Rs = ≈ 150Ω V1 = 2V2
64
50. Two identical FETs, each characterized by the 52. V0
The voltage gain Av = of the JFET amplifier
parameters gm and rd are connected in parallel. Vi
The composite FET is then characterized by shown in the figure is
the parameters.
g g r
(a) m and 2rd (b) m and d
2 2 2
rd
(c) 2gm and (d) 2gm and 2rd
2
GATE-1998
Ans. (c) : Both FET connected parallel-
Ip ID I
gm = = 1 + P
Vgs Vgs Vgs
IDSS = 10 mA Vp= –5 V
= g m 1 + g m2 (Assume C1, C2 and Cs to be very large)
Both FET identical- (a) +18 (b) –18
(c) +6 (d) –6
g m1 = g m2
GATE-2002
Overall- Ans. (d) : Transconductance
g m = 2g m 2I DSS  VGS 
gm = 1 − 
Vds −VP  VP 
rd =
I d1 + Id 2 From the question we know that
VG = 0, I DSS = 10mA R S = 2.5KΩ
1 1
= = ⇒ rd = rd  rd VS = I D R S ⇒ 1mA × 2.5KΩ
 d1   d 2 
I I 1
+
1
 +
   [ VS ⇒ 2.5V ]
 Vds   Vds  rd 1 rd 2
Both parallel rd1 = rd 2 Now VGS = VG − VS
= 0 − 2.5
rd = rd 2 [ VGS = −2.5]
2 × 10 × 10−3   −2.5  
Now ⇒ g m = 1 −  −5  
−5   
g m = 2ms
A V = −g m R D
= −2 × 10 −3 × 3 × 103
A V = −6 (a)1 V and the device is in active region
53. Consider the following statements in (b)–1 V and the device is in saturation region
connection with the CMOS inverter in the (c)1 V and the device is in saturation region
figure, where both the MOSFETs are of (d)–1 V and the device is in active region
enhancement type and both have a threshold GATE-2005
voltage of 2 V. Ans. (c) : For an n-channel MOSEFT-
Statement 1: T1 conducts when Vi ≥ 2V. If VGS < VT , I D = 0
Statement 2: T1 is always in saturation when V0 If VGS ≥ VT , I D flow
= 0 V. Condition for saturation-
VDS ≥ VGS − VT
VD − VS ≥ VG − VS − VT
VD ≥ VG − VT
5 ≥ 3 −1
=5>2
This is saturation.
56. An n-channel depletion MOSFET has following
two points on its ID – VGS curve:
(i) VGS = 0 at ID = 12 mA and
Which of the following correct? (ii) VGS = –6 volts at Z0 = ∞
(a) Only statement 1 is TRUE Which of the following Q-points will give the
(b) Only statement 2 is TRUE highest transconductance gain for small
(c) Both the statements are TRUE signals?
(d) Both the statements are FALSE (a) VGS = –6 volts (b) VGS = –3 volts
GATE-2002 (c) V GS = 0 volts (d) VGS = 3 volts
Ans. (a) : Statement 2 is false because GATE-2006
VDS will be less than- Ans. (d) : transconductance -
∂I
⇒ VGS − VT ( g m ) = D for
∂VGS
If-
VGS = constant −
Vo = 0
Plotted-
Hence, the correct option (a).
54. The action of a JFET in its equivalent circuit
can best be represented as a
(a) Current controlled current source
(b) Current controlled voltage source
(c) Voltage controlled voltage source
(d) Voltage controlled current source
GATE-2003
Ans. (d) : In JFET equivalent circuit, the output current
is controlled by the gate to source voltage and hence we
can say it is a voltage controlled current source. As I D increases VGS also increases larger VGS will have
55. For an n-channel MOSFET and its transfer high transconductance gain.
curve shown in the figure, the threshold So, according to the option the highest transconductance
voltage is is 3V.
57. In the CMOS inverter circuit shown, if the Ans. (c) : NMOS transistors M1 and M2 are connected-
transconductance parameters of the NMOS Vbias both transistors are in saturation condition-
and PMOS transistors are Kn = Kp = ∂I D1
W W g m1 =
µnCox n
= µ p Cox P 2
= 40µA/V and their ∂Vi
Ln LP
In saturation region ID = constant
threshold voltages are VTHn = |VTHp| = 1 V, the
I D1 = I D2
current I is
∂I
g m = out
∂Vi
∂I D2 ∂I D1
=
∂Vi ∂Vi
gm = gm1
So, the equivalent gm of the pair is nearly equal to the
gm of M1.
59. For the circuit shown in the following figure,
(a) 0 A (b) 25 µA transistors M1 and M2 are identical NMOS
(c) 45 µA (d) 90 µA transistors. Assume that M2 is in saturation
GATE-2007 and the output is unloaded.
Ans. (c) : Given-
VGS = 2.5V
VT = 1V
µA
K = 40
V2
K
ID = ( VGS − VT )
2
2
= 20 ( 2.5 − 1)
2
I D = 45µA
The current Ix is related to Ibias as
58. Two identical NMOS transistors M1 and M2 (a) Ix = Ibias + Is
are connected as shown below. Vbias is chosen so
(b) Ix = Ibias
that both transistors are in saturation. The
(c) Ix = Ibias – Is
equivalent gm of the pair is defined to
∂I  V 
be out at constant Vout. (d) Ix = Ibias –  VDD − out 
∂Vi  RE 
GATE-2008
Ans. (b) : Transistors M1 and M2 are identical NMOS
transistor current Ix is related to bias as-
it is a current mirror circuit
IG1 = IG2 = 0
I X = IS
I bias = IS + IG1 + IG 2
The equivalent gm of the pair is
I bias = Is + 0 + 0
(a) The sum of individual gm's of the transistors
(b) The product of individual gm's of the I x = bias
transistors
Hence, the correct option is (b)
(c) Nearly equal to the gm of M1
60. In the circuit shown below, for the MOS
(d) Nearly equal to gm/g0 of M2
transistors, µn Cox = 100 µA/V2 and the
BPSC Poly. Lect. 2014 threshold voltage VT = 1 V. The voltage Vx at
GATE-2008 the source of the upper transistor is
(a) 1 V (b) 2 V (a) Vin < 1.875 V
(c) 3 V (d) 3.67 V (b) 1.875 V < Vin < 3.125 V
GATE-2011 (c) Vin > 3.125 V
Ans. (c) : Let pull up transistor operate in saturation (d) 0 < Vin < 5 V
region- GATE-2012
W
1
( )
2
ID1 = µ n Cox   VGS1 − VT1 Ans. (a) : PMOS is in Linear region and NMOS is in
2  1
L cut-off region similarly for high V in , PMOS is in cut-off
and NMOS is in Linear region and for Vin in between
W
1
( )
2
ID2 = µ n Cox   . VGS2 − VT2 both are in saturation.
2  L 2
So PMOS will be in linear region for.
In saturation condition
Vin < 1.875 V
I D1 = ID2
4 [5 − VX − 1] = 1[ VX − 1]
2 2 63. The small-signal resistance (i.e. dVB/dID) in kΩ
offered by the n-channel MOSFET M shown in
2 [ 4 − VX ] = VX − 1 the figure below, at a bias point of VB = 2 V is
9 = 3VX (device data for M: device transconductance
parameter kN = µnC'OX(W/L) = 40 µ A/V2,
VX = 3V threshold voltage VTN = 1 V, and neglect body
61. An n-Channel JFET has effect and channel length modulation effects)
I DSS = 1µA & Vp = -5V. The maximum trans
conductance is
(a) g m = 0.4 micro mho
(b) g m = 0.04 milli mho
(c) g m = 0.04 mho
(d) g m = 0.4 mho (a) 12.5 (b) 25
BSNL (JTO)-2006 (c) 50 (d) 100
Ans. (a) : IDSS = 1µA GATE-2013
VP = –5V Ans. (b) : Given-
2I VB = 2V
maximum transconductance (gm)max = DSS
| VP |
W
2 ×1µA k N = µ n Cox   = 40µA V 2
= L
| −5 |
VT = 1V
2µA
= d vs
5V =?
d ID
µA
= 0.4. VB = VDS = VGS
V
gm = 0.4 micro mho M → is saturation condition-
62. In the CMOS circuit shown, electron and hole I D = k n ( VGS − VT )
2
mobilities are equal, and M1 and M2 are

equally sized. The device M1 is in the linear I D = 40 ×10−6 ( VDS − VT )
2
region if
∂I D K n = 0.78 mA / V
= 40 × 10−6 ( 2 − 1)
∂VDS Therefore, for-
VD = 2V
40
= 40 × 10−6 =
I D = 0.78 ( 2 − 0.8 )
2
1000 × 103
∂VDS ∂VB = 0.78 (1.2 )
2
= = 25kΩ
∂I D ∂I D
I D = 1.125 mA
Hence, the correct option (b).
66. What is the voltage Vout in the following
64. In a MOSFET operating in the saturation circuit?
region, the channel length modulation effect
causes
(a) An increase in the gate-source capacitance
(b) A decrease in the transconductance
(c) A decrease in the unity-gain cut-off frequency
(d) A decrease in the output resistance
GATE-2013
Ans. (d) : Without the channel length, modulation the (a) 0 V
drain current of a MOSEFT is given by- (b) (|VT of PMOS| + VT of NMOS)/2
Id = µ 2 × C ( W L )( VGS − VT )
2
(c) Switching threshold of inverter
(d) VDD
∴ dI/dV= 0 GATE-2016, Set-I
dv dI = ∞ Ans. (c)
Rd = ∞
If we consider channel length modulation, the value of
Rd will be always less than ∞. So the channel length
modulation decreases the output resistance.
65. For the n-channel MOS transistor shown in
figure, the threshold voltage VTh is 0.8 V.
Neglect channel length modulation effects.
When the drain voltage VD = 1.6 V, the drain
current ID was found to be 0.5 mA. If VD is
adjusted to be 2 V by changing the values of R The CMOS inverter connected in the feedback loop
and VDD' the new value of ID (in mA) is formed by connecting a 10 kΩ resister between the
output and input, goes and stays at the middle of the
characteristic-
VIR + VTH
Va =
2
Where-
Va → Switching threshold of the inverter.
(a) 0.625 (b) 0.75 67. In the circuit shown in the figure, the channel
length modulation of all transistors is non-zero
(c) 1.125 (d) 1.5 (λ ≠ 0). Also, all transistors operate in
GATE-2014, Set-I saturation and have negligible body effect. The
Ans. (c) : ac small signal voltage gain (Vo/Vin) of the
circuit is
I D = K n ( VGS − VT )
2
ID
Kn =
( VGS − VT )
2
0.5
Kn =
(1.6 − 0.8 )
2
0.5
=
0.64
(a) –gm1 (r01||r02||r03) Vth → threshold voltage
 1  The small signal equivalent circuit of MOSFET in
(b) −g m1  r01 r03 
 g m3  saturation-
 
 1  
(c) −g m1  r01 r02  r03 
 g m2  

 1  
(d) −g m1  r01 r03  r02 
 g m3  

GATE-2016, Set-III
Ans. (c) :
When the channel length modulation effect is
significant in MOSFET can be modeled as a current
source with finite output Impedance.
69. Assuming that transistors M1 and M2 are
identical and have a threshold voltage of 1 V,
the state of transistors M1 and M2 are
respectively
The small signal equivalent + model of NMOS &

PMOS is shown-
According figure, we can write-
Vin = Vgs , and Vo = −Vgs2
The small-signal equivalent of the given circuit will be-
Modal at Vo , we can write-
(a) Saturation, Saturation (b) Linear, Linear
v v v
g m1 v gs1 + o + o + o − g m2 vgs2 = 0 (c) Linear, Saturation (d) Saturation, Linear
ro1 ro2 ro3 GATE-2017, Set-II
1 1 Ans. (c) : Given the circuit-
1 
vo  + + g m2 +  = −g m1Vin VDS1 = 3
 ro ro ro3 
 1
VGS2 − Vt = 2.5 − x − 1
2
The above can be written as-

    = 1.5 − x
vo 1
= −g m1  ro1 ||  ro2 ||
 || ro3  VDS2 is always > VGS2 − Vt
vin   g m2 
 
So, M 2 will always be in saturation current calculation-
68. An n-channel enhancement mode MOSFET is
biased at VGS > VTH and VDS > (VGS – VTH), (I ) = (I )
DSat 1 DSat 2
where VGS is the gate-to-source voltage. VDS is
K n ( VGS − Vt )1 = K n ( VGS − Vt )2
2 2
the drain-to-source voltage and VTH is the
threshold voltage. Considering channel length
( 2 − 1) = ( 2.5 − x − 1)
2 2
modulation effect be significant, the MOSFET
behaves as a 1 = 1.5 − x
(a) Voltage source with zero output impedance
(b) Voltage source with non-zero output x = 0.5
impedance VDS = x − 0
(c) Current source with finite output impedance
(d) Current source with infinite output impedance VDS = 0.5
GATE-2017, Set-II and VGS − Vt = 1V
Ans. (c) : N-channel enhancement mode MOSFET is So,
biased at VGS > VTH and VDS < VGS − Vt
VDS > ( VGS − VTH ) this shows that our assumption is wrong and M1 cannot
Where- VGS → gate- source voltage be in saturation so, M1 → linear region
VDS → Drain-source voltage M 2 → saturation region

70. Two identical nMOS transistors M1 and M2 are V = I r + I r − g V r
x x 01 x 02 m 2 g 2 02
connected as shown below. The circuit is used
as an amplifier with the input connected Put –
between G and S terminals and the output Vg2 = −I x r01
taken between D and S terminals, Vbias and VD
are so adjusted that both transistors are in Vx = I x r01 + I x r02 + I x r01 r02 g m2
( )
saturation. The transconductance of this
∂i D Vx = I x ro1 + ro2 + ro1 ro2 g m2 I x
combination is defined as gm = while the
∂VGS The output Resistance-
∂V Vx
output resistance is ro= DS , where iD is the R o = I
∂i D x
current flowing into the drain of M2. Let gm1, = ro1 + ro2 + g m2 ro1 ro2
gm2 be the transconductances and ro1, ro2 be the
( )
output resistance of transistors M1 and M2' ro1 + ro2 will be very small in comparison with
respectively
g m 2 ro1 ro2 −
R o  g m2 ro1 ro2
Since M2 NMOS transistor is acting as a current buffer,
I D2 = ID1
The transconductance
∂I D2
Which of the following statements about g m2 =  g m1
estimates for gm and ro is correct? ∂Vgs
(a) gm ≈ gm1 . gm2 . ro2 and ro ≈ ro1 + ro2
(b) gm ≈ gm1 + gm2 and ro ≈ ro1 + ro2 71. An enhancement MOSFET of threshold
(c) gm ≈ gm1 and ro ≈ ro1 . gm2 . ro2 voltage 3 V is being used in the sample and
hold circuit given below. Assume that the
(d) gm ≈ gm1 and ro ≈ ro2
substrate of the MOS device is connected –10
GATE-2018
V. If the input voltage Vi lies between ± 10 V
Ans. (c) : Given-
the minimum and the maximum values of VG
∂I ∂V
g m = D , ro = DS required for proper sampling and holding
∂VGS ∂I D respectively, are
I D → drain current
g m1 , g m2 → Transconductance
Vo1 ,Vo2 → Output resistance of the transistors M1 and
M2
(a) 10 V and –13 V (b) 13 V and –7 V
Vg2 (c) 10 V and –10 V (d) 3 V and –3 V
GATE-2020
gm2 Vg2
Ans. (b) : Given-
VT = 3V
Vmin = −10V
Vmax = 10V
MOSFET sampling-
Applying KVL from Vg2 to ro1 ground- VGS > VT
We get- VG − Vmax > VT
− Vg2 − I x r01 = 0 VG − 10 > 3
Vg2 = − I x r01 .........(i)
VG > 13V
( )
Vx = ro2 I x − g m2 Vg2 + I x ro1 MOSFET should be since off for holding operation-
= ro2 I x − g m 2 Vg 2 ro2 + I x ro1 VGS < VT

VG − Vmin < VT 74.
Select the correct statement (s) regarding
CMOS implementation of NOT gates.
VG − ( −10 ) < VT
(a) Noise Margin High (NMH) is always equal to
VG < 3 − 10 the Noise Margin Low (NML), irrespective of
the sizing of transistors.
VG < −7V
(b) Dynamic power consumption during
Hence maximum and minimum value of VG required switching is zero.
for proper sampling and holding respectively are 13 V (c) For a logical high input under steady state, the
and -7V
nMOSFET is in the linear regime of
72. Using the incremental low frequency small- operation.
signal model of the MOS device, the Norton
equivalent resistance of the following circuit is (d) Mobility of electrons never influences the
switching speed of the NOT gate.
GATE-2022
Ans. (c) : NML = VIL –VOL
(a) NMH = VOH – VIH
VTN = |VTP|
Kn = Kp
V
VIT = DD
1 2
(a) rds + R + gm rds R (b) rds + +R
gm Kp
When, ↑ > 1, VIL ↑, VIH ↑
rds + R K n
(c) rds + R (d)
1 + g m rds NM H ↓ and NM L ↑
GATE-2020
Kp
Ans. (d) : When ↓ < 1, VIL ↓ .VIH ↑
Kn
NM H ↑ and NM L ↑
ie NML and NMH depends on transistor sizing and they
are equal for certain condition only.
(b) Dynamic power consumption during switching is
non-zero due to capacitive loading of next stage.
(c) For, VDD – |VTP| ≤ Vin ≤ VDD ⇒ PMOS → cut off
Norton equivalent resistance of the following circuit is – (d) Switching speed depends on charging and
Vm = −Vx discharging of load capacitor for pull up and pull
down of output voltage respectively.
Vx (1 + g m rds ) = ( rds + R ) I x Propagation delay,.
V R + rds τ + τPHL
RN = x = t p = PLH
I x 1 + g m rds 2
R + rds Where,
RN = CL VDD
1 + g m rds TPHL =
 ω
µ p Cox   ( VGS − VTP )
2
73. A JFET has got the following specifications:
VGS(OFF) = –2V, IDSS = 4 mA. When the applied L
VGS is one fourth of the VGS(OFF) to the JFET, CL VDD
then the drain current of the device would be VPHL =
 ω
µ p C→   ( VGS − VTN )
2
(a) 2.25 mA (b) 4 mA
(c) 0.25 mA (d) 1.0 mA L
TSGENCO AE-2015 using average charge model
Ans. (a) : Drain current Hence, c is only correct.
2 75. An n-channel JFET has 'IDSS' = 1 mA and
 Vgs   −2 
2
I D = I DSS 1 −  ID = 4 1 −  'VP' = –5 V. Its maximum transconductance is

 Vp   −8 
 (a) 0.4 millimho (b) 0.1 millimho
ID = 4 × 0.5625 (c) 1.0 millimho (d) 4.0 millimho
ID = 2.25 mA Kerala PSC Lecturer (NCA) 04.07.2017
2 I DSS Ans. (d) :
Ans. (a) : Maximum Transconductance gm0 =
VP
2 × 1× 10−3
gm0 =
5
gm0 = 0.4 m 
76. A source follower (using a FET) usually has a
voltage gain which is
(a) Slightly less than unity, but positive
(b) Greater than +1
(c) Exactly unity but negative
Rout = –gm1 (r01 R p ) r02
(d) About – 10
Kerala PSC Lecturer (NCA) 04.07.2017 80. An N-Channel JFET has IDSS=8mA and
Ans. (a) : A source followers usually has a voltage gain Vp = –5V. The minimum value of VDs for
slightly less than unity but always +ve. But current of pinch-off region and the drain current IDs for a
this configuration will be high. VGS = –2V are.
77. The pinch off voltage of a JFET is 5V. Its cut (a) 3V and 2.88mA (b) -5V and 1.88mA
off voltage is (c) -2V and 3.12mA (d) -7V and 1.98mA
(a) 51/2 V (b) 2.5 V TNPSC AE- 2019
3/2
(c) 5 V (d) 5.0 V Ans. (a) : Given –
IDSS = 8mA, Vp = -5V, VGS = -2V
 ( −2 ) 
2
2
Ans. (d) : VP = 5 V  VGs  -3  1 −
ID = IDSS 1 −
  = 8×10  ( −5 ) 
At cut-off the gate to source voltage of JFET is equal to
 Vp   
pinch off voltage. 2
−3  3 
Vgs = VP ≥ Vgs (off) = 8 × 10  
Vgs (off) = 5V 5
78. A certain p channel E-MOSFET has 9
= 8 × 10-3×
VGS(th) = –2V. If VGS = 0V, the drain current is: 25
(a) 0 A (b) ID(ON) = 2.88mA
(c) maximum (d) IDSS VDS ≥ VGS − Vp
= −2 − ( −5 ) = 3 V
Ans. (a) : A certain p channel E-MOSFET has a
VGS(th) = – 2V ; VGS = 0V 81. The symbol in figure 1 is
VGS(th) < VGS
E MOSFET in cutt off region
drain current is 0A.
79. During manufacturing, a large parasitic
resistor, Rp, has appeared in a cascade as
shown in the figure below. Determine the
output resistance (a) diode connected FET
(b) triode connected FET
(c) tetrode connected FET
(d) pentode connected FET
TNPSC AE- 2019
Ans. (c) : The tetrode field–effect transistor or field
effect tetrode is a solid–state semiconductor device,
constructed by creating two field-effect channels back-
to-back. It is a four–terminal device. It does not have
specific gate terminals because each channel is a gate
for the other, the voltage condition modulating the
(a) Rout = – gm2 (r01||Rp)r02 current carried by the other channel.
(b) Rout = – gm1 (r02||Rp)r01
82. Which basic FET amplifier configuration is
(c) Rout = – gm1 (r01||r02)Rp also known as the 'Source Follower' and which
(d) Rout = – gm1 (r01||Rp)r02 bipolar transistor amplifier configuration it is
RPSC VP/Suptd. ITI 05.11.2019 analogous to?
(a) Common drain amplifier, Emitter follower Ans. (a) :A junction field effect transistor can operate in
(b) Common source amplifier, common emitter depletion mode only but MOSFET can operate in
amplifier enhancement and depletion mode.
(c) Common gate amplifier, common base 87. Vp is the pinch off voltage for VGS = 0 in an
amplifier FET. When the gate is reverse biased by VGS
(d) Common source amplifier, Emitter follower the pinch off voltage
(a) Will be less than Vp
(b) Will be more than VP
Ans. (a) : Common drain amplifier configuration is also (c) Same as VP
known as the source followers. The reason for this is (d) Does not depend on VGS
that the source voltage follows that of the gate. Nagaland PSC CTSE- 2015, Paper-II
83. In a FET, transconductance gm is proportional
Ans. (a) : Vp → Pinch off voltage
to
When the gate is reverse biased by Vds, the pinch off
(a) Ids (b) Ids2 voltage will be less than one because when gate is
(c) Ids (d) I/Ids reversed biased depletion width increases which
decreases the pinch-off voltage.
88. The MOSFET switch in its on-state may be
Ans. (a) : Trans conductance for FET is given by considered equivalent to :
2I  V  (a) Resistor (b) Capacitor
gm = DSS 1 − Gs  (c) Inductor (d) Battery
Vp  Vp 
RRB SSE 21.12.2014, (Red)
IDSS ⇒ maximum drain current. Ans. (b) : The MOSFET switch in its on-state may be
84. In JFET, dynamic drain resistance rd is of the considered equivalent to capacitor. In on-state there is a
order of conducting channel between Drain and source.
(a) 1 KΩ (b) 10 KΩ The structure of MOS is like–
• GATE (metal)
(c) 10 MΩ (d) 100 MΩ
• Oxide (SiO2) layer
Nagaland PSC- 2018, Diploma Paper-II • Conductive channel
Ans. (a) : Dynamic resistance of JFET is of the order of N-channel MOSFET:-
1 kΩ. (a) Enhancement Mode :-
transconductance = 0.1 ms to 10ms
85. The parameters of an FET are gm=3mA/V,
rd = 30K. RL=3K as a source follower load, the
output impedance is given by
(a) 333 ohms (b) 2.7 K ohms
(c) 3 K ohms (d) 300 ohms
Ans. (d) :
RL (b) Depletion Mode
R0 =
1 + gmR L
R L = R 2 || rd
3 × 30
=
33
= 2.7 k Ω
 3k Ω
3k It is also a voltage-controlled resistor in which the

R0 = channel thickness depends on the gate to source.
1 + 3 × 10 –3 × 3 × 103
89. For a Common Source (CS) MOSFET
= 300 Ω
amplifier, what is the input capacitance Cin for
86. A junction field effect transistor can operate in
(a) Depletion mode only the following conditions:
(b) Enhancement mode only C gs = 4pF, C gd = 1pF, and A v = 5.
(c) Depletion and Enhancement modes (a) 10 pF (b) 16 pF

(d) Neither depletion nor Enhancement modes (c) 14 pF (d) 12pF
Nagaland PSC CTSE- 2015, Paper-II UPPCL AE-05.11.2019
Ans. (a) : Given as due to virtual ground,
Cgs = 4pF , Cgd = 1pF, and Av = 5 Va = 2.5V
As we know 2.5 2.5 − 5 2.5 − Vb
Therefore, + + =0
Cin = Cgs + Cgd(1–Av) 3.3 3 10
Q Common source Amplifier gain is always negative Vb = 1.75V
(-Ve) Time constant - τ = 100kΩ × 1nF
∴ AV = –5
Cin = 4+1 [1–(–5)] τ = 100 × 103 × 10−9 = 100µs
Cin = 4+6 = 10pF And now the gate voltage is given by
90. In a Common Drain (CD) MOSFET amplifier VG = 5 (1 − e − t τ )
with voltage divider bias with R1 and R2 equal
to 1.5 MΩ and 1 MΩ respectively, the input ⇒ 0.7 = 5 (1 − e − t 100µs )
impedance Zi is: t = 15µs
(a) 220 kΩ (b) 600 kΩ
When MOSFET ON VG > Vt ( 0.7V )
(c) 470 kΩ (d) 200 kΩ
After 15µs, VG > Vt
UPPCL AE-05.11.2019
MOSFET ON behaves as comparator for positive logic.
Ans. (b) : Given as, R1 = 1.5MΩ , R2 = 1MΩ
So, Before 15µs ( Vt > VD ) MOSFET off behaves as
R ⋅R comparator for negative logic.
R in = R1 || R 2 = 1 2 After 100µs, we have
R1 + R 2
5
1.5 ×106 × 1× 106 Vt = t
R in = T
(1.5 + 1) ×106 5
⇒ 1.75 = ×t
R in = 0.6MΩ ⇒ R in = 600kΩ 100
175
91. The ramp signal (voltage: 0 to 5 V) is compared t = = 35µs
with the soft-start signal provided by N- 3
channel MOSFET (Q1) for amplifier (A1) After 135µs, the comparator behaves for negative logic
output. If Q1 having low threshold voltage of up to 200µs
0.7 V and negligible ON resistance. What is the
Duty cycle-
duty of output signal of comparator (C1) after
100 µs ? T 35
D = ON = × 100
T 100
= 35% ≅ 34.8%
92. What is the value of Rs required to self bias N-
channel JFET with Vp = –10V, IDSS = 40 mA
and VGSQ = –5V?
(a) 250Ω (b) 500Ω
(c) 750Ω (d) 1500Ω
LMRC AM (S&T)-13.05.2018
2
 V 
(a) 17.4% (b) 34.8% Ans. (b) : We know that I D = I DSS 1 − gs 
(c) 0% (d) 50%  VP 
ISRO Scientist December, 2017 2
−3   −5  
Ans. (b) : Given I D = 40 × 10 1 −  
  −10  
[ ID = 10mA ]
Vgs 5
Rs = = = 500Ω
ID 10 × 10−3
93. A JFET has Idss = 5 mA and gmo = 5000 µS.
What is the value of VGS (off) and for VGS = –
KCL at node Va 1V gm is:
Va Va − Vcc Va − Vb (a) VGS(off) = –2V, gm = 7500 µS
+ + =0
3.3 3 10 (b) VGS(off) = –1V, gm = 7500 µS

(c) VGS(off) = –1V, gm = 2500 µS 1 1
(a) − (b) −
(d) VGS(off) = –2V, gm = 2500 µS 400 600
LMRC AM (S&T)-13.05.2018 1 1
(c) − (d) −
−2I DSS 2000 31000
Ans. (d) : VGS( off ) =
g mo DRDO-2009
Given ⇒ I DSS = 5mA g mo = 5000µS Ans. (c) :
−2 ( 5mA )
VGS( off ) =
5000µS
VGS( off ) = −2V
Use formula-
 V 
g m = g mo 1 − GS 
 VGS( off ) 
 
 1V 
g m = ( 5000µS) 1 − 
 2V  1
Slope = −
R D + RS
g m = 2500µS
1
94. A CMOS Inverter is shown below in the figure. = −
For Vin = Vout = 2.5 V, which one of the 1600 + 400
following is true if the threshold voltage of the ⇒ − 1
NMOS transistor is 1 V and that of PMOS 2000
transistor is –1 V. 96. An n-type MOSFET and an npn BJT are
biased so that IC = ID = 1 mA, VGS = 1.3 V and
VBE = 0.7 V. Threshold voltage for the
MOSFET is 0.8 V and thermal voltage at the
ambient temperature is given to be 25 mV.
Transconductances of the BJT and the
MOSFET are :
(a) gmBJT = 40 mA/V and gmMOSFET = 4 mA/V
(b) gmBJT = 40 mA/V and gmMOSFET = 2.5 mA/V
(a) NMOS is Linear region, PMOS in saturation (c) gmBJT = 80 mA/V and gmMOSFET = 2 mA/V
(b) NMOS in saturation region, PMOS in (d) gmBJT = 80 mA/V and gmMOSFET = 4 mA/V
saturation DRDO-2009
(c) NMOS is saturation region, PMOS in linear
region Ans. (a) : Trans-conductance of BJT is the ratio of
(d) NMOS in Linear region, PMOS in Linear output drain current with respect to change in the input
region gate voltage it is presented by g m
−3
BSNL (JTO)-2001 g = IC = 1× 10 = 40mA / V
VT 25 × 10−3
m
Ans. (b) : If the threshold voltage of the NMOS
transistor is 1V and that of PMOS transistor is –1V in Trans conductance of MOSFET anode current divided
this condition NMOS will be in saturation region and by the corresponding change in the cathode voltage.
PMOS will also in saturation region.
2ID 1×10-3 × 2
95. The slope (in A/N) of the ID – VDS load line for g m MOSFET = = = 4mA/V
Vgs − VT 1.3-.8
the circuit shown in figure below is :
97. In a P-well fabrication process, the substrate is
(a) N-type semiconductor and is used to build P-
channel MOSFET
(b) P-type semiconductor and is used to build P-
channel MOSFET
(c) N-type semiconductor and is used to build N-
channel MOSFET
(d) P-type semiconductor and is used to build N-
channel MOSFET
DRDO-2008
Ans. (a) : In a P-well fabrication process the substrate is Ans. (d) : Given,
N Type semiconductor and used to build P channel VGS1 = 900mV = 0.9 V
MOSFET.
I D1 = 1mA
VGS2 = 1400mV = 1.4V
VTH = 0.4V
I D ∝ ( VGS − VTH )
2
( )
2
I D1 = K VGS1 − VTH .................(i)
= K (V )
2
I D2 GS2 − VTH ……………….(ii)
98. An N-channel enhancement mode MOSFET
with threshold voltage of 1 V is biased at By equation (i) and (ii)
2
VGS = 2 V and VDS = 2V. If the drain voltage is I D2  VGS2 − VTH 
doubled to 4 V, the drain-to-source current = 
will: I D1  VGS1 − VTH 
(a) double (b) more than double
(1.4 − 0.4 )
2
ID2
(c) increase only slightly (d) become half =
BSNL(JTO)-2002 1m A ( 0.9 − 0.4 ) 2
Ans. (b) : I D = K ( VGS − VT ) (1) ×1mA

2 2
I D2
=
( 0.5 )
2
Where, 1
I D → Drain current 1
= mA
VGS = Gate source voltage 0.25
VT = Threshold voltage ID2 = 4mA
99. An n-channel JFET has IDSS =2mA and 101. The drain of an n-channel MOSFET is shorted
Vp= –4V. It's transcoductance gm (in mA/V). to the gate so that VGS=VDS. The threshold
When applied gate to source voltage VGS –2V is voltage (VT) of MOSFET is 1 V. If the drain
(a) 0.25 (b) 0.5 current (ID) is 1 mA for VGS=2V, then for VGS =
(c) 0.75 (d) 1.0 3V, ID is
GATE- 1999 (a) 2mA (b) 3mA
Ans. (b) : Given, (c) 9mA (d) 4mA
IDSS = 2mA = 2×10–3A GATE-2004
VP = – 4V Ans. (d) : Given, VGS = VDS, VT = 1V
VGS = –2V I D2 = 1mA
gm = ?
drain current ID = 1mA
2I DSS  VGS  VGS1 = 2V
gm = 1 − 
| VP |  VP 
VGS2 = 3V
2 × 2 × 10−3  ( −2 ) 
gm = 1 −  I D ∝ ( VGS − VT )
2
| − 4 |  ( −4 ) 
( )
2
I D1 = K VGS1 − VT …………………(i)
g m = 0.5mA / V
= K (V −V )
2
100. When the gate-to-source voltage (VGS) of a I D2 GS2 T ………………..(ii)
MOSFET with threshold voltage of 400 mV, By equation (i) and (ii)
working in saturation is 900 mV, the drain
( )
2
current is observed to be 1 mA. Neglecting the I D2 VGS2 − VT
channel length modulation effect and assuming =
( )
2
that the MOSFET is operating at saturation,
I D1 VGS1 − VT
the drain current for an applied VGS of
1m A ( 2 − 1)
2
1400 mV is =
( 3 − 1)
2
(a) 0.5 mA (b) 2.0 mA I D2
(c) 3.5 mA (d) 4.0 mA
ID2 = 4mA
GATE- 2003
102. The drain current of a MOSFET in saturation (a) 4.5×1011 cm–2 (b) 6.0×1011 cm–2
11 –2
2
is given by ID=K(VGS–VT) where K is a (c) 7.2×10 cm (d) 8.4×1011 cm–2
constant. The magnitude of the trans- GATE- 2016
conductance gm is Ans. (b) : Given,
K(VGS – VT ) 2 VG1 = 0.8V, VG2 = 1.3V, VG3 = 1.8V
(a) (b) 2K(VGS – VT )
VDS Q = 2 × 1011 cm −2 , Q = 4 × 1011 cm −2 , Q = ?
1 2 3
ID K(VGS – VT ) 2 We know that-

(c) (d)
VGS – VDS VGS Q ∝ (VG − VT )
GATE-2008 VG1 − VT Q1 0.8 − VT 2 × 1011
∴ = ⇒ =
Ans. (b) : Given- ID = K (VGS -VT)2 VG 2 − VT Q 2 1.3 − VT 4 × 1011
where K is constant VT = 0.3V
dId VG 2 − VT Q 2 1.3 − 0.3 4 × 1011
Transconductance gm = Now- = = =
dVGS V = Constant
ds
VG3 − VT Q3 1.8 − 0.3 Q3
d.K Q3 = 6 × 1011 / cm 2
gm = (VGS − VT ) 2
dVGS
105. Two n-channel MOSFETs, T1 and T2, are
or gm = 2K (VGS –VT) identical in all respects except that the width of
103. The measured trans-conductance gm of an T2 is double that of T1. Both the transistors are
NMOS transistor operating in the linear region biased in the saturation region of operation,
is plotted against the gate voltage VG at a but the gate overdrive voltage (VGS–VTH) of T2
constant drain voltage VD. Which of the is double that of T1, where VGS and VTH are the
following figures represents the expected gate-to-source voltage and threshold voltage of
dependence of gm on VG? the transistors respectively. If the drain
current and transconductance of T1 are ID1 and
gm1 respectively, the corresponding values of
these two parameters for T2 are
(a) 8 ID1 and 2 gm1 (b) 8 ID1 and 4 gm1
(c) 4 ID1 and 4 gm1 (d) 4 ID1 and 2 gm1
GATE- 2017
Ans. (b) : Given,
W2 = 2W1 = 2W
and (VGS – VTh)2 = 2(VGS–VTh)1 = 2(VGS –VTH)
W1 ( VGS − VTh )1
2
I D1 W1 (VGS − VTH )2
= =
8W1 ( VGS − VTh )2 8W1 (VGS − VTH )2
2
I D2
GATE-2008 I D2 = 8I D1
Ans. (c) : Drain current ID in the linear region is given Similarly
by- g m1 W (V − Vth )1
 VDS2  = 1 GS
I D = K ( VGS − VT ) VDS − g m2 W2 (VGS − Vth ) 2
 2 
g m1 W1 (VGS − Vth )
∂I D =
gm = = K ( VGS − VT ) VDS g m2 2W 1 2(VGS − Vth )
∂VGS V =Constant
DS g m2 = 4g m1
g m ∝ VDS 106. The figure shows the high-frequency C-V curve
Hence, gm is independent of VGS for linear region of a MOS capacitor (at T=300K) with
operation of N-MOS. φms = 0V and no oxide charges. The flat-band,
104. A voltage VG is applied across a MOS capacitor inversion, and accumulation conditions are
with metal gate and p-type silicon substrate at represented, respectively, by the points
T=300 K. The inversion carrier density (in
number of carriers per unit area) for VG= 0.8 V
is 2×1011 cm–2. For VG= 1.3 V, the inversion
carrier density is 4 ×1011 cm–2. What is the
value of the inversion carrier density for
VG=1.8 V?
(a) Q, R, P (b) P, Q, R 2
qN D 2  b 
(c) Q, P. R (d) R, P, Q = a 1 – 
2ε  a
GATE-2019 2
Ans. (a) : The flate band voltage where no charge VP  b
= VP 1 –  From equation (ii)
present in the oxide surface as Va increase more electrons 4  a
are attracted to the oxide semiconductor inter face a n- 2
1  b
type channel is formed the inversion takes place R for = 1 – 
negative gate voltage, mover holes are accumulated near 4  a
the gate. Accumulation takes place at P. b 1
1– =
a 2
b 1
=
a 2
a
b=
2
3
b = µm
107. Determine the channel half-width for an n- 2
channel silicon FET having Gate-to-Source b = 1.5µm where b=channel width
voltage, VGS =Vp/4, where Vp is the Pinch-off
voltage and drain current Id=0. (Consider (a) 108. A high gain MESFET packaged device of case-
Donor Concentration ND=1015 electrons/cm3 (b) to-channel thermal resistance of the device is
Channel half-width for VGS= 0 V is 3 µm ). 4.5° C/Watt provides 8W RF output power
(a) 2.25 µm (b) 3 µm taking 20W DC power. What will be the
channel temperature of the device if the case
(c) 1.5 µm (d) 0.75 µm temperature of the device maintained at 55°C?
ISRO Scientist Engg.-2018 (a) 109°C (b) 145°C
Ans.(c): Given, (c) 59.5°C (d) 91°C
VP ISRO Scientist Engg. -2015
Gate to source voltage VGS = Ans. (a) : Given,
4
drain current ID = 0 thermal resistance = 4.5°C / W
15
donor concentration ND=10 electron/cm 3 P o = 8W, Pi = 20W, Tcase = 55ºC
channel half width for VGS=0V is 3µm T – Tcase
Thermal resistance = channel
We know, Pi – P0
2εV  1 1  4.5 =
Tchannel – 55
depletion width (W) =  + 
q  NA ND  20 – 8
Acceptor concentration NA is very higher than ND then 4.5 × 12 = Tchannel – 55
1 1 Tchannel = 54 + 55
is very low so is neglected
NA NA Tchannel = 109°C
2εV  1  109. A unilateral transistor has an output
w=  
q  ND  impedance Zout = (10 – j10)Ω. Value of the
series and shunt components of the matching
2εV 1
w2 = . network for complex conjugate match at the
q ND output of the device to 50Ω load are:
qN D 2
V= w ...............(i)
2ε
2a
channel width = =a=3µm (given)
2
at pinch off voltage VP=V and VGS=VP
qN D 2
Vp = a ..........(ii) (a) X1 = –j25, X2 = +j30
2ε (b) X1 = +j25, X2 = +j30
VGS=VP/4 (c) X1 = –j25, X2 = –j3
VP qN D
= (a – b)
2 (d) X1 = +j2, = –j30
4 2ε ISRO Scientist Engg. -2015
Ans. (a) : Given,
Zout = (10–j10)Ω
(Zout + X2) || X1 = 50Ω
( Zout + X 2 ) .X1 = 50
Zout + X 2 + X1
{(10 – j10 ) + X }.X
2 1
= 50
(10 – 10 j) + X 2 + X1
(10 – j10 ) X1 + X1X 2 = 50 ...............(i)
(10 – 10 j) + X 2 + X1 (a) 3.45 V (b) 1.5 V
This equation is satisfied when (c) 2.85 V (d) 2.3 V
X1= –j25 & X2 = j30 UPPCL AE- 31.12.2018
110. For the circuit shown above if gm = 3 × 10–3 and Ans. (c) : VDS ≥ (VGs – VTh)
Rs = 3000Ω, then the approximate value of R0 is µCox W
I DS = ( VGS − VT )
2
2 L
1
VG = 10 × = 5V
2
VS = IDS × RS
I DS = 12.5µ ( 4 − i D × 50 )
2
(a) 3000 Ω (b) 1000/3Ω

I D sat = 12.5 16 + 2500 I2Dsat × 106 − 4 × 105 I DS 
(c) 300Ω (d) 100Ω
ISRO Scientist Engg.-2008 From here
Ans. (c) : Given, gm = 3×10 –3 ID = 0.043 mA or 0.1489 mA
Rs = 3000Ω for ID = 0.1489 mA VD = − ve so
1 VD = 10–0.1489mA ×75K
drain resistance (rd) =
transconductance (g m ) = –1.167V (this is not possible)
1 ID = 0.043 mA
= VD = 10 – 0.043 × 75 K
3 ×10−3
VD = 6.775 V
103
= VS = 0.043 × 50K
3
1000 Vs = 2.15V
rd = Ω
3 VDS = VD – VS
R 0 = rd || R s VDS = 6.775 – 2.15
VGS = VG–VS = 5 – 2.15
1 1 1
= + VGS = 2.85 V
R 0 rd R s
1 1 1 112. The drain of an N-channel MOSFET is shorted
= + to the gate such that VGS = VDS. The threshold
R 0 1000 3000 voltage (VT) of MOSFET is 1 volt. If the drain
3 current (ID) is 1 mA for VGS = 2V, then for
1 3 1 VGS = 3V, the drain current ID is-
= +
R 0 1000 3000 (a) 4 mA (b) 3 mA
(c) 5 mA (d) 6 mA
R 0 = 300Ω UPPCL AE-16.11.2013
111. Find the gate source voltage VGS for the given ISRO Scientist-2007
N-MOSFET with parameters VT = 1V, Kn = Ans. (a) : For n channel MOSFET-
the I D = K n [2VDS ( VGS − Vth ) − VDS ] , VDS < (VGS – Vth)
W 2
µ 0C0x = 25 µA/V 2 . Assume that
L 2
MOSFET is not operating in the cutoff mode, ID = K n  VGS − Vth  VDS > VGS – Vth.
and also assume an ideal MOSFET with gate
current equal to zero. In problem, VDS = VGS So VDS > VGS − VT

Hence this is in saturation region. Tjmax − Tamb
From the given value Pmax =
θ2 − θ1
ID = Kn [VGS – VT]2
1500º C − 300º C
1 mA = Kn (2 – 1)2 =
( 600 − 1)
0
Kn = 1 mA/V2 C/ W
Now when VD = 3V, VGS = 3V 1200º C
ID = Kn [VGS – VT]2 =
5990 C
I D = 1[3 − 1] mA
2
Pmax  2W
ID = 4 mA 115. A MOSFET in saturation has a drain current
113. The pinch - off voltage of n-channel junction of 1 mA for VDS = 0.5 V. If the channel length
FET is VP = –4V and the drain to source modulation coefficient is 0.05 V–1, the output
saturation current IDSS= 2mA. Its trans resistance (in kΩ) of the MOSFET is
conductance (gm) for an applied gate to source (a) 15 (b) 20
voltage VGS of –2V is- (c) 18 (d) 23
(a) 1.0 mA/V (b) 0.25 mA/V Nagaland PSC CTSE (Diploma)-2017, Paper-I
(c) 0.75 mA/V (d) 0.5 mA/V Ans. (b) : IDSat = 1mA , λ = 0.05
UPPCL AE-16.11.2013 VDS = 0.5V
Ans. (b) : Given, Modulation coefficient = 0.05/V
VP = –4V, IDSS = 2mA, VGS = –2V I D = I Dsat (1 + λVDS )
2
 V  dI D 1
= = λ I Dsat
ID = IDSS 1 − GS 
 VP  dVDS r0
1
r0 =
2
  −2  
I D = 2 × 10−3 1 −    λI Dsat
  −4  
1
 1
2 =
−3
I D = 2 × 10 1 −  0.05 × 1× 10−3
 2 = 20kΩ
1 116. An N-channel JFET, having a pinch-off voltage
I D = 2 × 10−3 ×
4 (Vp) of –5V, shows a trans conductance (gm) of
ID = 0.5 mA 1 mA/V when the applied gate-to-source
I voltage (VGS) is –3V. Its maximum trans
gm = D conductance (in mA/V) is
| VGS | (a) 1.5 (b) 2.0
0.5mA (c) 2.5 (d) 3.0
gm =
| −2 | Nagaland PSC CTSE (Degree)-2017, Paper-I
0.5 Ans. (c) : VP = –5V
gm = mA gm = 1mA/V
2
g m = 0.25mA / V VGS = –3V
−2I DSS  VGS 
114. A certain power MOSFET has a maximum gm = 1 − 
junction temperature specification of 1500ºC, a VP  VP 
junction-to-case thermal resistance of −2I DSS  3 
1.00 0C/W, and a junction-to ambient thermal 1= 1 − 
resistance of 600 0C/W. If the ambient −5  5 
temperature is 300ºC then the maximum 25
allowable power dissipation in the device will be. I DSS =
4
(a) 1.52 W (b) 1.75 W
−2I DSS
(c) 1.92 W (d) 2.00 W gm(max) =
RPSC LECTURER-10.01.2016 VP
Ans. (d) : Given, −2 × 25 1
= ×
Tjmax = 1500ºC 4 −5
θ1 = 1.000 C / W 10
=
θ2 = 6000 C / W 4
Tamb = 300ºC gm(max) = 2.5mA/V

117. What is the drain current for a D-MOSFET Ans. (a) :
having the characteristic values IDSS of 10 mA,
VGS(off) of –4V and VGS of + 2 V?
(a) 22.5 mA (b) 17.5 mA
(c) 12.5 mA (d) 2.5 mA
IES-2019
Ans. (a) : Given that-
IDSS = 10mA
VP = VGS( off ) = −4V
VGS = 2V
2
Given that-
 V  VTP = –1.4V
drain current ID = IDSS 1 − GS 
 VP  I DSS  VGS 
and gm = 1 −  L = 2µm, λ = 0
2
 2 VP  VP 
∴ I D = 10mA × 1 + 
 4 if IDS = –0.1mA and VDS = –2.4V
ID = 22.5mA From Circuit-
118. For an n-channel silicon JFET with a = 2 × 10–4 9–VDS–VS = 0
cm and channel resistivity ρ = 5Ω-cm, ∴ VDS = VGS → Saturation Condition
µn = 1300 cm2/V– s and ε0 = 9 × 10–12 F/m, the so, = –2.4V
pinch-off voltage, Vp, is nearly 1 W
I D = K P   ( VGS − VT )
2
(a) 2.30 V (b) 2.85 V 2  
L
(c) 3.25 V (d) 3.90 V
IES-2018 −0.1× 10−3 = × 25 × 10−6 × W
1
(–2.4+1.4)2
−6
Ans. (b) : Given that- 2 2 × 10
Channel width (a) = 2×10–4cm 1
0.1× 10−3 = × 25 × W
µn = 1300cm2/v-s 4
−12 −14
ε 0 = 9 × 10 F / m = 9 × 10 F/cm W = 16µm
ρ = 5Ω − cm applying KVL in circuit-
2 9 − VGS − I D R = 0
a
Now Vp = IDR = 9+VGS
2ερµ n
9 + VGS 9 − 2.4 6.6
a2 R= ⇒R= −3
=
ID 0.1×10 0.1×10−3
2ε0 ε r ρµ n
R = 66kΩ
=
( 2 × 10 )
−4 2
120. The data sheet for a certain JFET ( Junction
2 × 9 × 10−14 × 11.9 × 5 ×1300 Field Effect Transistor) indicates that IDSS
Where for Si, ε r = 11.7 ± 0.2 (drain to source current with gate shorted) = 15
mA and VGS(off) (Cut-off value of gate to source
VP  2.85V
voltage) = – 5V. What is the drain current for
119. The PMOSFET circuit shown in the figure has VGS = – 2V?
VTP = – 1.4 V, K P = 25 µA / V L = 2 µm, λ = 0.
' 2 (a) 58.8 mA (b) 29.4 mA
If IDS = – 0.1 mA and VDS = – 2.44 V then the (c) 9.6 mA (d) 5.4 mA
width of channel W and R are respectively: IES-2008
Ans. (d) : Given that-
I DSS = 15 mA
VGS ( off ) = −5V
VGS = –2V
VGS ( off ) = VP
(a) 16 µm and 66 kΩ (b) 18 µm and 33 kΩ  V 
2
(c) 16 µm and 33 kΩ (d) 18 µm and 66 kΩ ∴ I D = I DSS  1 − GS 

 VP 
IES-2016
123. The JFET in the circuit shown in figure has an
 −2 
2
= 15 ×10−3  1 −  IDSS = 10 mA and Vp = – 5V. The value of the

 −5  resistance Rs for a drain current IDS = 6.4 mA is
15 × 10−3 × 9 (select the nearest value)
=
5× 5
27 ×10−3
=
5
ID = 5.40 mA
121. The pinch-off voltage VP = +6 V for a P- (a) 156 Ω (b) 150 Ω
channel JFET. If VGS = +2 V, what is the value
of VDS at which it will enter into saturation (c) 560 Ω (d) 1000 Ω
region ? NIELIT Scientists- 2017
(a) – 6V (b) – 4V Ans. (a) : Given,
(c) + 8V (d) + 4V IDSS = 10 mA, Vp = –5V, ID = 6.4 mA
MIZORAM PSC Jr. Grade-2018, Paper-I Rs = ?
2
IES-2007  V 
Ans. (c) : Given that- ID = IDSS 1 – GS 
VP = 6V  VP 
2
VGS = 2V ID  V 
For saturation state = 1 – GS 
IDSS  VP 
VDS = VGS+VP
VDS = 2+6 6.4 V
= 1 – GS
VDS = 8V 10 VP
122. The trans conductance 'gm' of a JFET is equal VGS 8
1− =
2I 2 VP 10
(a) − DSS (b) I DSS I DS
VP VP VGS 8
= 1−
2I DS I DSS  VGS  VP 10
(c) − (d) 1 − 
VP VP  VP  VGS 1
=
IES-1999 VP 5
Ans. (b) : The drain current in saturation for a JFET is 1
given by: VGS = −5 × V
5
2
 V  VGS = –1V
I D = I DSS  1 − GS  ..........(i)
 VP  VGS = –ID⋅RS.
1
∂I D 2I  V  Rs =
= DSS  1 − GS  ....(ii) 6.4mA
∂VGS VP  VP 
Rs = 156 Ω
2
 VGS  ID 124. In figure T1, T2 and T3 are p-channel MOS
1 −  = transistors, and T4, T5 and T6 are n-channel
 VP  IDSS
MOS transistors. A, B and C are binary
 VGS  1D signals. The output f(A, B, C) is
1 − =
 VP  I DSS
put in equation (ii)
2IDSS ID
gm =
VP I DSS
2 I2DSS I D
gm =
| VP | IDSS
2
gm = I DSS .I D
| VP |

(a) A ( B + C ) (b) A + BC Ans.(a) : The relation between the drain current and
gate to-source voltage is defines.
(c) A (B + C) (d) ABC 2
BSNL (JTO)-2001  VGS 
I D = I DSS  1 −  this relation is a non linear
Ans. (a) : B and C are connected in series and A is  VP 
connected in parallel to BC The minimum current for JFET occurs of pinch off
then output (f ) = A + BC voltage defined by VGS = VP
2
= A.BC  V 
I D = I DSS  1 − GS 
= A(B + C)  VP 
125. Two MOSFETs M1 and M2 have channel When VGS = VP
widths and lengths of W, L and 2 W, L/2, and ID = 0
drain currents of ID1 and ID2, respectively.
Assuming that both M1 and M2 are On, under 127. The ideal long channel nMOSFET and
the same temperature and biasing voltages, pMOSFET devices shown in the circuits have
which one of the following is TRUE? threshold voltages of 1 V and –1V, respectively.
(a) ID2=ID1/4 (b) ID2=ID1/2 The MOSFET substrates are connected to their
(c) ID2=2ID1 (d) ID2=4ID1 respective sources. Ignore leakage currents and
DRDO-2009 assume that the capacitors are initially
discharged. For the applied voltages as shown,
Ans. (d) : MOSFET M1
the steady state voltage are _________.
channel width = W
length = L
drain current = ID1
MOSFET M2,
channel width = 2W
length = L/2
drain current = ID2
W
drain current I D1 ∝
L
kW (a) V1 = 5 V, V2 = 5 V
I D1 = .....(I) (b) V1 = 5 V, V2 = 4 V
L
where k is proportionality constant (c) V1 = 4 V, V2 = 5 V
k.2W (d) V1 = 4 V, V2 = –5 V
I D2 = GATE-2022
L/2
Ans. (c) : n MOSFET,
W
I D2 = 4k VT = 1V
L P MOSFET,
from equation (i) VTH = –1V
ID2 = 4 × I D1
JFET:
1. The relationship between the drain
current and gate-to-source voltage of a
JFET is a nonlinear.
2. The minimum current for JFET occurs at
pinch-off voltage defined by VGS =VP.
3. A current controlled device is one in which
a current defines the operating conditions n MOFET will provide
of the device. V1 = 5V–VT
Which of the above statements are correct? = 5V –1V
(a) 1 and 2 only (b) 1 and 3 only = 4V
(c) 1, 2 and 3 (d) 2 and 3 only P MOSFET will provide
ESE-2021 V2 = 5V
Ans. (b) : Given VCC = 24V
(v) Power amplifiers VL(P) = 22V
π VL (P)
η= ×100
1. Crossover distortion is the characteristic of 4 VCC
(a) Class A output stage π 22
(b) Class B output stage η = × ×100
4 24
(c) Class AB output stage = 71.99
(d) Common basic output stage 72%
5. The common source stage of a CMOS amplifier
Nagaland PSC (degree) - 2018, Paper-II provides:
GPSC Asstt. Prof. 11.04.2017 (a) moderate voltage gain, low input impedance
Nagaland PSC CTSE (Degree)-2017, Paper-II and moderate output impedance
TSPSC Manager Engg-2015 (b) moderate voltage gain, high input impedance
GATE-1999 and high output impedance
Ans. (b) : Crossover distortion occurs in class B (c) moderate voltage gain, low impedance
amplifiers because the amplifier is biased at its cut-off (d) moderate voltage gain high input impedance
point. and moderate output impedance
UPMRC AM - 2020
2. Circuit diagram of a transformer coupled
Ans. (d) : The common source stage of a CMOS
audio power amplifier is shown here. Max. amplifier provides–
voltage on collector of transistor will be
1. Input impedance = High ( MΩ )
2. Output impedance = moderately high ( kΩ )
3. Voltage gain = moderately high.
6. An optical amplifier has population density of
electrons in the lower state N1 and in the higher
state N2 with relationship for high
amplification as:
(a) N2 << N1 (b) N2 < N1
(c) N2 > N1 (d) N2 = N1
UPMRC AM - 2020
Vcc
(a) Vcc (b) Ans. (c) : The energy of the emitted photon is the
2 difference between energy level.
(c) 2Vcc (d) 2Vcc E = E 2 − E1
UPPSC ITI Principal/Asstt. Director-09.01.2022 and
Ans. (b) : Transfer coupled audio power amplifier
hc
V E = hν =
vmax = cc λ
2
From population inversion condition, the higher energy
3. Operating cycle of Class-C amplifier is state E2 will have a higher population of electrons than
(a) 180º the lower energy state (E1) .
(b) Less than 180º So, N 2 > N1
(c) 360º
(d) 180º to 360º 7. In a cellphone, a power amplifier delivering
1W to the antenna may pull several watts from
the battery. If the power conversion efficiency
KVS TGT (WE)- 2016 is 30% then the above cellphone translates to a
Ans. (b) : Operating cycle of class C amplifier is less power drain of:
than one - Half cycle means the conduction angle is less (a) 1 W from the battery
than 180º and its typical values is 80º to 120º. (b) 1.3 W from the battery
4. The efficiency of a Class - B amplifier for a (c) 0.3 W from the battery
supply of VCC = 24 V and peak output voltages (d) 3.33 W from the battery
VL(P) = 22 V is UPMRC AM - 2020
(a) 41.2% (b) 72% Ans. (d) : Given
(c) 19.6% (d) 29.1% Pout = 1W
Efficiency ( η) = 30%
KVS TGT (WE)- 2018

Pout Ans. (b) : BW1 = BW 21/ n − 1
Q η= × 100%
Pin BW1 = 20 × 103 21/ 2 − 1
So, 30 =
1
× 100 BW1 = 20 × 0.41 × 103
Pin BW1 ≅ 12.9 kHz
Pin = 3.33W
10. The class of amplifier operation characterized
8. A signal of 1 kHz is to be amplified, but the by highest efficiency, high distortion is:
circuit board and wires pick up and store 60 (a) Class - A (b) Class - B
Hz component from a nearby electric line. If (c) Class - C (d) Class - AB
this component is 40 dB higher than the desired Nagaland PSC CTSE (Diploma)-2018, Paper-I
signal, what filter stop band attenuation is
necessary to ensure the signal remains 20dB Nagaland PSC (Degree)-2018, Paper-II
above the interferer level? Nagaland PSC CTSE (Degree)-2016, Paper-II
(a) High pass filter with stop band attenuation of KVS TGT (WE)-2017, 2016
60 dB at 60 Hz UKPSC Assistant Radio Officer Screening Exam.-2011
IES-2000
(b) LPF with SBA of 60 dB at 1 kHz
(c) HPF with SBA of 60dB at 1 kHz Ans. (c) : Class-C amplifiers have high circuit
(d) Low pass filter with stop band attenuation of efficiency of about 90% and highest distortion.
60 dB at 60 Hz Power Conduction Maximum
UPMRC AM - 2020
amplifier angle Efficiency
Ans. (a) : Desired signal has a high frequency 1KHz
therefore we need to attenuate the low frequency 60Hz. Class A 360º 50%
They are used a high pass filter. Class B 180º 78.5%
Class AB 180º −360º 50 − 78.5%
Class C < 180º ≥ 90%
11. While designing a low noise amplifier, what is
the importance of the noise resistance of a
A transistor?
Q 20log10 = dB
B (a) It gives the effective impedance offered by
B the input with respect to noise current
Initially, 20log = 40 ……….. (i) (b) It defines the criterion for conjugate matching
A
of input impedance
And after passing through the filter
(c) It tells us the resistance that would generate
A the same amount of noise at room
20log = 20 ……….. (ii)
Bf temperature
From equation (i) and (ii) (d) It tells us how rapidly the noise figure
B A increases as we move away from the optimum
20log + 20 log = 60 source impedance
A Bf ISRO Scientist Engg. 2009
B A  Ans. (d) : On designing a low noise amplifier the
20log  ×  = 60 importance of the noise resistance of a transistor is that,
 A Bf  it tells us how rapidly the noise figure increases as we
B move away from the optimum source impedance.
20log = 60
Bf 12. Consider a 565 PLL with RT = 10kΩ and
B CT = 0.01 µF. what is the output frequency of
20log f = −60 the VCO?
B
So, Bf is the attenuated version of B, by an attenuation (a) 10 kHz (b) 5 kHz
factor of 60dB at 60 Hz. (c) 2.5 kHz (d) 1.25 kHz
9. An amplifier has two identical cascaded stages. IES-2009
Each stage has bandwidth of 20 kHz. The Ans. (c) : Given, RT = 10 kΩ, CT = 0.01 µF
overall bandwidth shall approximately be Output frequency of the VCO,
equal to - 1
(a) 10 kHz (b) 12.9 kHz f0 =
4R T CT
(c) 20 kHz (d) 28.3 kHz
LMRC Am (S & T), 13.05.2018 1
=
Punjab PSC Poly. Lect. 20.08.2017 4 ×10 × 10 × 0.01× 10 –6
3
AAI - 2015 = f0 = 2.5 KHz

13. The phase shift oscillator of fig. below operates T0 = 300 K
at f = 80 kHz. The value of resistance RF is
 2β 
Te =   T0
 NF 
Where Te = Equivalent noise temperature
T0 = ambient temperature
 2 × 50 
Te =   300K
 10 
= 3000K
16. Consider a single stage tuned amplifier having
(a) 148 kW (b) 236 kW 3 dB bandwidth of 100 kHz. Determine the
(c) 438 kW (d) 814 kW bandwidth if two such single tuned amplifiers
Mizoram PSC IOLM-2010, Paper-II are cascaded :
(a) 100 kHz (b) 10 kHz
Ans. (b) : Resistance in phase shift oscillator,
(c) 41.4 kHz (d) 64.3 kHz
1
R= ISRO Scientist Engg.-2014
2πfC 6 Ans. (d) : Given,
1 3dB BW frequency = 100 kHz
R=
2 × 3.14 × 80 × 103 × 100 × 10−12 6 n=2
1
106 106 So, over all Bandwidth = BW 2 n − 1
= =
61.5311 123.06 1
= 8.12kΩ = 100 × 103 2 2 − 1

RF = 64.34 kHz
= 29 17. In case of an ideal class-F microwave power
R
amplifier, time domain voltage and current
RF = 29R
waveform of the device have:
RF = 29× 8⋅12 = 235.48kΩ (a) 50% overlap
RF 236KΩ (b) Maximum overlap
(c) No overlap
14. Approximate equivalent noise temperature (d) Less than 80% overlap
(deg. K) of an amplifier with a noise factor of
1.04 is
Ans. (c) : In Class-F microwave power amplifier there
(a) 301.6 (b) 11.6
is no overlap of time domain voltage and current
(c) 278.4 (d) 5.8 waveform of the device.
ISRO Scientist Engg. 2009 18. DC to RF efficiency of an ideal class-F
Ans. (b) : Given, Noise factor (F) = 1.04 amplifier is:
Equivalent noise temperature Teq = T0 ( F − 1) (a) 100% (b) 78.4%
(c) 50% (d) < 80%
Where,
T0 = 290 K(standard noise temperature)
Ans. (a) : For ideal class-F amplifier
Teq = T0(F-1)
= 290×(1.04–1) ηdc / rf = 100%
= 290×0.04 Class-F amplifier are capable of high efficiency of more
Teq = 11.6 K than 90%.
19. For a class B amplifier providing a 20V peak
15. An amplifier has a gain of 50 dB, and noise
signal to 16Ω load and a power supply of VCC =
figure of 10 dB. Assuming an ambient
30V, the efficiency will be.
temperature of 300 K, what will be the total
(a) 52.3% (b) 25.65%
equivalent noise temperature at the input of the
(c) 75% (d) 78.6%
amplifier? DFCCIL Executive (S&T) 11.11.2018, 4:30 to 6:30PM
(a) 760 K (b) 360 K ISRO Scientist Engg.-2011
(c) 2700 K (d) 3000 K Ans. (a) : Given, Peak voltage Vm = 20
ISRO Scientist Engg.-2014 RL = 16Ω
Ans. (d) : Given, VCC = 30V
Gain ( β ) = 50 dB 2V 2 × 20
Idc = m = = 0.796A
Noise figure (NF) = 10dB πR L π× 16

Pdc = VCC × Idc = 30 × 0.796 = 23.9W Ans. (d) : A class-D amplifier or switching amplifier is
Q Power delivered by load an electronic amplifier in which the amplifying devices
operates as a electronic switch and this switches are
Vm2 400 mostly MOSFETs power switches.
PL = = = 12.5W
2R L 32 25. The power rating of the amplifier is 100 watts
So, the efficiency of class B amplifier- then the transistor can only operate at______
P × 100 12.5 × 100 (a) Power higher than 100 W
η(%) = L = = 52.3% (b) Power lower than 100 W
Pdc 23.9
(c) Power near to 100 W
20. Which of the following principles is applied (d) Power lower than 200 W
while designing the output matching network
for a high power Class-C amplifier?
(a) Maximum Power Transfer Theorem Ans. (b) : If the power rating of the amplifier is 100W
(b) Norton's Theorem that is maximum allowable power uses of a transistor
beyond which it may damage. If power is less than
(c) Thevenin's Theorem
100W, the circuit operates perfectly.
(d) Power = (voltage)2/RL
ISRO Scientist Engg.-2010 26. Input stage of power amplifier is also
called_____
Ans. (a) : Maximum power transfer theorem is applied
(a) First op (b) Beginning stage
while designing the output matching network for a high
power class-C amplifier. (c) Front end (d) Normal stage
21. Which device was used for the amplification of
audio signals before the invention of power Ans. (c) : Input stage of power amplifier is also called
amplifiers? the front end amplifier.
(a) Op - amp (b) Vacuum tubes 27. For a perfect power amplifier output power
(c) SCR (d) Diode rating will be______if the output impedance is
Nagaland PSC (CTSE) Diploma-2017, Paper II halved.
Ans. (b) : Before the invention of power amplifier, (a) Halved (b) Squared
vacuum tubes are used for audio signal amplification (c) Doubled (d) Square rooted
which consumes large space and costly. Nagaland PSC (CTSE) Diploma-2017, Paper II
22. Power amplifier directly amplifies______ Ans. (c) : The power is proportional to the square of the
(a) Voltage of signal voltage and inversely proportional to the resistance, if
(b) Current of the signal output impedance is halved then output power will be
(c) Power of the signal doubled.
(d) All of the mentioned 28. Transistor in power amplifier is_______
Nagaland PSC (CTSE) Diploma-2017, Paper II (a) An active device
Ans. (d) : A power amplifier is designed to increase the (b) A passive device
magnitude of power of a given input signal. Power (c) A on-amp
amplifiers increases voltage as well as current. Increase (d) A voltage generating device
in voltage or current is small as compared to normal Nagaland PSC (CTSE) Diploma-2017, Paper II
amplifier. Ans. (a) : A transistor is an active device since
23. Which of the following audio speaker will be transistor contain voltage source which are necessary
hard to be driven by a power amplifier? for amplification.
(a) 4 ohm (b) 8 ohm 29. A tuned amplifier uses…………load
(c) 12 ohm (d) 2 ohm (a) Resistive (b) Capacitive
Nagaland PSC (CTSE) Diploma-2017, Paper II (c) LC tank (d) Inductive
Ans. (d) : If the resistance of the audio amplifier is less, Nagaland PSC (CTSE) Diploma-2017, Paper II
the output power of the transistor will be high since, KVS TGT (WE)- 2017
output current is increasing. Ans. (c) : The tuning circuit can be built with various
Hence, to drive a 2 Ω speaker twice as much power is components like inductor (L) and capacitor (C). The
required as compared to a 4 Ω speaker. parallel combination of the inductor and capacitor is
24. Which of the stages listed below would drive called a tuned circuit. So, a turned amplifier uses LC
the loudspeaker, in a class D amplifier? tank load.
(a) A comparator 30. Which of the following is NOT amplified by an
(b) A low pass filter amplifier?
(c) A pulse width modulator (a) current (b) resistance
(d) A mosfet power switch (c) power (d) voltage
Nagaland PSC (CTSE) Diploma-2017, Paper II RRB SSE 03.09.2015 Shift-II
Ans. (b) : Amplifier circuit is an electronics circuit in Ans. (c) :
which input is low quality signal and gives output as
strong signal. Commonly transistors are used for the Power Conduction Maximum
process of amplification, amplify the signal current, amplifier angle Efficiency
power and voltage but can not amplify resistance.
Class A 360º 50%
31. Linear amplifier with a gain of 30 dB is fed
with 1.0µW power, the output power of the Class B 180º 78.5%
amplifier Class AB 180º −360º 50 − 78.5%
(a) 1.0 W (b) 0 dBm
(c) 30 dBm (d) -30 dBm Class C < 180º ≥ 90%
ISRO Scientist Engg.-2006 34. Harmonic generators use which amplifier?
Ans. (b) : Given, (a) class- A (b) class- AB
Pin = 1µW (c) class- C (d) class- B
gain = 30dB
Ans. (c) : Harmonic generators use class-C amplifier.
We known- Application of Class C amplifier
P • RF oscillators • Booster amplifier
gain = 10log10 out
Pin • RF amplifier • High frequency repeaters
P • FM transmitters • Tuned amplifier
30 = 10log10 out 35. A cascaded amplifier has the advantage of
1µW
(a) Low input capacitance
P
3 = log10 out (b) Low input impedance
1µW (c) High trans conductance
P (d) Large voltage gain
103 = out Mizoram PSC IOLM -2018, Paper II
1µW
Pout = 1mW Ans. (a) : A cascaded amplifier has the advantage that it
has low input capacitance.
P0 ( dBm ) = 0
36. An amplifier circuit has an overall current gain
32. An amplifier has an input power of 2 of -100 and an input resistance of 10kΩ with a
microwatts. The power gain of the amplifier is load resistance of 1 kΩ. The overall voltage
60 dB. The output power will be gain of the amplifier is
(a) 6 microwatts (b) 120 microwatts (a) 5 dB (b) 10 dB
(c) 2 microwatts (d) 2 watts (c) 20 dB (d) 40 dB
ISRO Scientist Engg.-2008 Mizoram PSC IOLM -2018, Paper II
Ans. (d) : Power gain = 10 log Ap Ans. (c) : β = 100
 P0  input impedance R1 = 10 kΩ
60 = 10 log10  
output impedance R2 = 1 kΩ
 Pi 
R
 P0  Voltage gain Av = β× 2
6 = log10   R1
 Pi 
1
P0 = 100 × = 10
10 =
6
10
Pi Voltage gain (in dB) = 20log1010
P0 = Pi × 106 = 20 dB
−6 37. Heat sink are used in the power amplifier
= 2 × 10 × 10 6
= 2W circuits
(a) To increase the output power
33. For power amplifiers, which of the statements
are correct. (b) To reduce the heat losses in the transistor
I. Class A : The output stage conducts for a full (c) To increase the voltage gain of the power
360 0 amplifier
II. Class B : The output stage conducts for 180 0 (d) To increase the collector dissipation rating of
III. Class C : The output voltage conducts for the transistor
0 Mizoram PSC IOLM -2018, Paper II
more than 180
IV. Class B : The maximum efficiency is 78.5% Ans. (d) : Heat sink are used for power transistor as the
(a) I. II and III (b) II and III power dissipated at their collector junction is large.
(c) I, II and IV (d) I, II, III and IV By using heat sink, thermal runaway can be prevented
RPSC ACF & FRO 23.02.2021 and power handling capacity can be increased.

38. An amplifier has an output signal power of 10 Ans. (d) : In Class-B amplifier, the maximum power
W and an output noise power of 0.01W. The
V2
signal-to-noise power ratio is Pmax = CC
(a) 10 dB (b) 20 dB 2.R L
(c) 30 dB (d) 60 dB 43. Conduction extends over 3600 in a class A
Mizoram PSC IOLM-, Paper-III amplifier because Q point is
Ans. (c) : Given, (a) Centred on load line
Output signal power (Ps) = 10W, (b) Located at or near cut off point
Output noise power (PN) =0.01W (c) Located on load line
(d) Located near saturation point
P  MPPSC Forest Service Exam.-2014
SNR = 10log  s  dB
P
 N Ans. (a) : In class A amplifier conduction extends over
3600 because the operating point is located in the centre
 10 
= 10 log   of load line, because it provide less distortion.
 0.01  44. The bandwidth of a Class C amplifier
= 10 log101000 decreases when the
= 10 × 3 (a) Resonant frequency increases
(SNR)dB = 30 dB (b) Q increases
39. Class - C power amplifiers are generally- (c) XL decreases
(a) Low frequency amplifier (d) Load resistance decreases
(b) Wide band amplifier Nagaland PSC CTSE (Degree)-2016, Paper-II
(c) Transformer coupled between stages 1
(d) Tuned RF amplifier Ans. (b) : We know that, Q ∝
BW
UPPCL AE-16.11.2013 So, bandwidth of class-C amplifier decreases with the
Ans. (d) : The Class-C power amplifier is one kind of quality factor(Q) increases.
amplifier, where the transistor conduct for less than 45. In class B Push-pull operation the power
180º. A Class-C amplifier is used in the applications delivered to the load RC = 8 ohms is Pac=16
like RF oscillator and RF tuned amplifier. watts. Then the Peak load current Im is given
40. Which of the following indicates 2nd harmonic by
distortion in power amplifier? (a) 16 amp (b) 2 amp
(a)
A2
(b)
A3 1
(c) 2 amp (d) amp
A1 A2 2
A4 A1 Nagaland PSC CTSE (Degree)-2016, Paper-II
(c) (d)
A2 A2 Ans. (c) : Given, Pac = 16 watt RC = 8 Ω,
SAIL- 2014 We know, Pac = I m × R C
2
nd
Ans. (a) : 2 harmonic distortion in power amplifier P 16
A2 ⇒ I m = ac = = 2 amp
indicates . R C 8
A1 46. The reason for cross-over distortion in a push-
41. Transconductance amplifier is a pull amplifier is that
(a) Voltage to current converter (a) The transistors are overdriven at the cross-
(b) Current to voltage converter over points
(c) Current controlled current source (b) Current switching from one transistor to
(d) Voltage controlled voltage source another
TNPSC AE-2014 (c) The combined transfer characteristics of the
two transistors in most non linear at zero base
Ans. (a) : Transconductance amplifier– The current
transconductance amplifier is an amplifier whose (d) The input signals rise fast at its zero
differential input voltage produces an output current. Nagaland PSC CTSE (Degree)-2016, Paper-II
Thus, it is a voltage controlled current source.
Ans. (b) : The reason for cross-over distortion in a
42. In Class-B amplifier, the maximum power Pmax push-pull amplifier is that Current switching from one
equals transistor to another.
VCC2 VCC
(a) (b)
RL 2R L
VCC2 VCC2
(c) (d)
2 RL 2R L
TNPSC AE-2013
47. Which distortion is least objectionable in case Ans. (d) : Given,
of audio amplifiers? Zero signal power dissipation, Pdc = 10Watt
(a) Phase distortion
(b) Frequency distortion A.C Power output, P0 = 4W
(c) Harmonic distortion P0
(d) Inter-modulation distortion So, collector efficiency = × 100
Pdc
4
Ans. (a) : Phase distortion is least objectionable in case = × 100
of audio amplifiers. 10
= 40%
48. Which class of amplifier has the lowest
collector circuit efficiency 53. In an amplifier, fT is the unit gain frequency. If
(a) A (b) AB gain increased by 25%, then effect on Band
(c) B (d) C Width?
Nagaland PSC CTSE (Diploma)-2018, Paper-I (a) Increased (b) Decreased by 20%
(c) No change (d) Decreased by 25%
Ans. (a) : Class A amplifier has lowest efficiency and
SAIL- 2014
the efficiency of this amplifier is 50%.
Ans. (b) : Unit gain frequency = gain × BW
Power Conduction Maximum  25 
G1 × BW1 = 100 +  G1 × BW2
amplifier angle Efficiency  100 
Class A 360º 50% 5
BW1 = BW2
Class B 180º 78.5% 4
Class AB 180º −360º 50 − 78.5% 4
BW2 = BW1
Class C < 180º ≥ 90% 5
 1
49. Crossover distortion takes place in BW2 = 1 −  BW1
(a) Tunned amplifier  5
(b) Power amplifier BW2 = Decreased by 20%
(c) Small signal amplifier Hence, bandwidth is decreased by 20%
(d) Video amplifier 54. The bandwidth for double tuned amplifier is 20
Nagaland PSC CTSE (Diploma)-2018, Paper-I kHz. Calculate the bandwidth if such three
Ans. (b) : Cross over distortion takes places in push stages are cascaded –
pull amplifier. A push pull amplifier is basically a (a) 7.14 kHz (b) 14.28 kHz
power amplifier because of it is used to supply high (c) 21.42 kHz (d) 28.56 kHz
power to the load. RPCS Lect.-2011
50. Which power amplifier can deliver maximum Ans. (b) : (BW)1 = 20 kHz
load power? If 'N' identical double tuned amplifier are cascaded then
(a) Class A (b) Class AB overall B.W. will be
(c) Class B (d) Class C BW = (BW)1 4
21/ N − 1
Ans. (d) : The efficiency of class C amplifier is high. BW = 20k 4 21/ 3 − 1
So by using class-C amplifier we can deliver the BW = 14.28 kHz
maximum load power. 55. The advantage of using a class-B push pull
51. In class-A power amplifier the collector transistor amplifier over a class-A push pull
dissipation is maximum when transistor amplifier is
(a) No signal is present (a) A negligible power loss at no input signal
(b) Signal swing is maximum (b) Harmonic distortion is lower
(c) Signal swing is (1/2) of its maximum (c) Self bias can be used
(d) None of the above (d) Supply voltages have good regulation
Mizoram PSC IOLM-2010, Paper-II IES-2020
Ans. (a) : In class-A power amplifier the collector Ans. (a) : The advantage of using a class-B push pull
dissipation is maximum when no signal is present. transistor amplifier over a class-A push pull transistor
52. A power transfer used in class A amplifier has amplifier is a negligible power loss at no input signal.
zero signal power dissipation of 10 Watts. If the The only difference is that there are no biasing resistors
AC power is 4 W. Calculate collector efficiency. for a class-B push pull amplifier. Class-A amplifier
(a) 60% (b) 30% produces least distortion in the output among all power
(c) 90% (d) 40% amplifier. In class-B amplifier, quiescent power (Q-
RPCS Lect.-2011 power) dissipation is almost zero.

56. The Class-B push-pull amplifier is an efficient 2
two-transistor circuit, in which the two IC max =
transistors operate in the following way: 12
(a) Both transistors operate in the active region IC max = 0.16667 amp, IC max = 166.7 mA
throughout the negative ac cycle
59. A power amplifier with a gain of 100 ∠0º has
(b) Both transistors operate in the active region an output of 12 V at 1.5 kHz along with a
for more than half-cycle but less than a whole second harmonic content of 25 percent. A
cycle. negative feedback is to be provided to reduce
(c) One transistor conducts during the positive the harmonic content of the output to 2.5
half-cycle and the other during the negative percent. What should be the gain of the
half-cycle feedback path and the level of signal input to
(d) Full supply voltage appears across each of the the overall system, respectively?
transistors. (a) 0.9 and 0.12 V (b) 0.9 and 12 V
IES-2016 (c) 0.09 and 1.2 V (d) 9 and 0.12 V
Ans. (c) : The class-B push pull amplifier is an efficient IES-2014
two-transistor circuit, in which the two transistors Ans. (c) : Given,
operate as one transistor conducts during the positive Gain A = 100, Output signal level = 12 V
half-cycle and the other during the negative half-cycle. 2nd harmonic distortion becomes 2.5% from 25%
25
Distortion reduced by factor = = 10
2.5
Distortion Reduced by factor = (1 + Aβ)
10 = 1 + Aβ
Aβ = 9
57. Which of the following is the principle factor
that contributes to the doubling of the 9
β= = 0.09
conversion efficiency in a transformer coupled 100
amplifier? Gain of the output signal level
(a) Reducing the power dissipated in the = Distortion Reduced by factor × Input signal level.
transistor Output signal level = (1 + Aβ) × input signal level
(b) Eliminating the power dissipation in the Output signal level
transformer Input signal level =
(c) Elimination of dc power dissipation in the (1 + Aβ)
load 12
=
(d) Impedance matching of the transformer 10
LMRC AM- 16.07.2021 Input signal level = 1.2 V
IES-2015
Ans. (c) : Elimination of DC power dissipation in the 60. An output signal of a power amplifier has
load is the principle factor that contributes to the amplitudes of 2.5 V fundamental, 0.25 V
doubling of the conversion efficiency in a transformer second harmonic and 0.1V third harmonic.
coupled amplifier. Conversion efficiency is a measure The total percentage harmonic distortion of
of the ability of a power amplifier to convert DC power the signal is
into AC power. (a) 12.8% (b) 10.8%
AC output power (c) 6.4% (d) 1.4%
η= IES-2012
DC power taken from biasing supply
Ans. (b) : Give, First Harmonic, D1 = 2.5 V
P Second Harmonic, D2 = 0.25 V
%η = AC × 100%
PDC Third Harmonic, D3 = 0.1 V
Total percentage harmonic distortion of signal -
58. A power amplifier operated from 12 V battery 2 2
gives an output of 2W. The maximum collector  D 2   D3 
current in the circuit is THD% =   +   × 100
 D1   D1 
(a) 166.7 µA (b) 166.7 mA
(c) 166.7 A (d) 16.67 mA 2
 0.25   0.1 
2
IES-2015 THD% =    +  ×100

 2.5   2.5 
Ans. (b) : Given,
VCC = 12 V, Pout = 2W 1 1
THD% = + × 100
P = VI, Pout = VCC. IC 100 625
P THD% = 10.777%
IC max = out
VCC THD% ≈ 10.8%

61. Using transistors, 64. Consider the following?
1. Class-A power amplifier has a minimum 1. Distortion
efficiency of 50%. 2. Gain
2. Class-B push-pull power amplifier gives
rise to crossover distortion. 3. Bias stabilization
3. Class AB push-pull power amplifier has 4. Sensitivity
higher efficiency than Class-B power 5. Frequency response
amplifier. Which of these properties of the Power
4. Class-C power amplifier is generally used Amplifier one should concentrate upon while
with tuned load for RF amplifications. designing a good Power Amplifier circuit?
Which of these statements are correct? (a) 1, 2 and 3 (b) 1, 3 and 4
(a) 1, 2, 3 and 4 (b) 2 and 4 only
(c) 2, 3 and 4 (d) 4 and 5
KVS TGT (WT)-2018 IES-2009
Kerala PSC Lecturer (NCA)-04.07.2017 Ans. (a) : Following properties of the power amplifier
IES-2011 should be considered while designing a good power
Ans. (b) : • Class-B push-pull power amplifier gives amplifier circuit-
rise to crossover distortion. • High gain
• Class-C power amplifier is generally used with • Bias stabilization
tuned load for RF amplifications. • Less distortion.
Power Amplifier Efficiency 65. What is the collector circuit efficiency of a class
Class -A 50% (Maximum) B push-pull amplifier if
Class-B 78.5% Vm = peak load voltage, and
Class-AB 50-78.5% VCC = collector supply voltage
Class-C 87.5% π Vm π Vm
62. Which one of the following statements is not (a) η = × 100% (b) η = × 100%
correct with regard to Power Amplifier? 4 VCC 2 VCC
(a) The collector current is large. π VCC π VCC − Vm
(b) They are used as the front end of multistage (c) η = × 100% (d) η= ×100%
2 Vm 4 Vm
Amplifiers.
(c) They are used near the end of the multistage IES-2008
Amplifiers. Ans. (a) : Efficiency of a class B push-pull amplifier
 1  Vm = Peak load voltage
(d) They have a high power rating  > W  . VCC = Collector supply voltage
 2 
IES-2009 1
AC output power PAC = Vm .I m
Ans. (b) : Power amplifiers are not used as the front end 2
of multistage amplifiers. Power amplifiers are used only 2V .I
near the end of multistage amplifier. DC input power, PDC = CC m
π
Power amplifier uses special transistor called power
transistor which has greater power rating and large AC output power
Efficiency η% = × 100
collector current. DC power taken fromsupply
63. Consider the following statements regarding PAC
the Class-B power Amplifiers (Complement- η% = × 100
ary symmetry type). PDC
1. The efficiency of the Amplifier is higher than 1
that of class-A Amplifier. Vm .I m
2. The power output is low. η% = 2 × 100
2VCC .Im
3. Cross-over distortion is present.
4. The standby power dissipation is absent. π
Which of the statements are correct? π V
η% = . m × 100%
(a) 1, 2 and 3 (b) 1, 2 and 4 4 VCC
(c) 1, 3 and 4 (d) 2, 3 and 4
IES-2009 66. In a class A amplifier, VCE(max) = 15 V and
Ans. (c) : 1. The efficiency of the amplifier is higher VCE(min) = 1V. The conversion efficiency for a
than that of class-A amplifiers. series fed load will be equal to
2. Class-B amplifier suffers from the problem of (a) 25% (b) 23.33%
crossover distortion. (c) 12.5% (d) 11.67%
3. The output of power amplifier is high. IES-2008
4. The standby power dissipation is absent. Mizoram PSC Jr.Grade 2018, Paper-II
Ans. (b) : Given, VCC = VCE(max) = 15 V 69. In an amplifier, the power output is 2W at 5
VCE(min) = 1 V kHz, and 0.5 W at 50 Hz. If the input power is
P constant at 10 mW, what is the variation
Conversion Efficiency % η = AC × 100% (approximate) of power gain in dB at two
PDC frequencies? (log102 ≈ 0.30)
1 V (a) 6 dB (b) 8 dB
%η = . m × 100%
4 VCC (c) 3 dB (d) 16 dB
∵ Vm = (VCC – Vmin) IES-2007
Ans. (a) : Given,
1 V − Vmin
%η = . max × 100 Output power, Pout = 2 W
4 Vmax Input power, Pin = 0.5 W
15 − 1 P 
= ×100 Variation of Power gain (in dB) = 10log10  out 
4 × 15
1400  Pin 
=  2 
60 = 10log10  
%η = 23.33%  0.5 
= 10log10 4
67. Match List-I (Name of the circuit) with List-II
(Property of the circuit) and select the correct = 10log1022
answer using the codes given below the lists: = 20log102
List-I List-II = 20×.30 = 6dB
A. Preamplifier 1. Non-linear circuit Variation = 6dB
B. Power amplifier 2. Lumped, linear,
passive, bilateral, 70. A power supply has a full-load voltage of 24 V.
finite circuit What is its no-load voltage for 5% regulation
C. Rectifier circuit 3. Large signal (rounded off do the nearest integer)?
amplifier (a) 12 V (b) 23 V
D. Purely resistive 4. Small signal (c) 25 V (d) 6 V
circuit amplifier IES-2007
Codes: Ans. (c) : Given,
A B C D No load voltage VNL = ?
(a) 4 2 1 3
Full load voltage VFL = 24 V
(b) 1 3 4 2
(c) 4 3 1 2 % Regulation R = 5%
(d) 1 2 4 3 V − VFL
%R = NL × 100%
IES-2008 VFL
Ans. (c) : Preamplifier is a small signal amplifier.
V − 24
Power amplifier is large signal amplifier. 5 = NL ×100
Rectifier circuit consist of non-linear circuit element. 24
Lumped, linear, passive, bilateral and finite circuits VNL = 1.2 + 24
are purely resistive circuit. VNL = 25.2 Voltage
68. In a class-B push-pull operation, the d.c. power
drawn is 28 W. What is the power delivered by VNL ≃ 25Volt
the amplifier at the ideal maximum efficiency
of power conversion? 71. Match List-I (Type of Amplifier) with List-II
(a) 28W (b) 14W (Property) and select the correct answer using
(c) 22W (d) 7W the codes given below the lists:
Ans. (c) : Given, A. Single ended 1. Medium efficiency with
We know that efficiency for class-B amplifier. class A minimum distortion
η = 78.5 % (for Class B amplifier) B. Class AB 2. High efficiency with
Pin (max) = 28 W push-pull crossover distortion
Pout(max) = η Pin (max) C. Class B 3. Harmonic generator

Pout(max) =  78.5  push-pull with highest possible
 × 28 conversion efficiency
 100 
Pout(max) = 21.98 W D. Class C 4. Poor conversion
Pout(max) ≃ 22W efficiency with minimum
distortion.
Codes: 24
A B C D =
0.8
(a) 2 3 4 1
Pin = 30 W
(b) 4 1 2 3
(c) 2 1 4 3 Current drawn from Battery,
(d) 4 3 2 1 P 30
Iin = in =
IES-2005 Vin 12
Ans. (b) : Class-A Amplifier :- In class-A amplifier, its Iin = 2.5 A
conversion efficiency is (25 to 50)%. In this power
amplifier quiescent power (Q-power) dissipation is very 74. The power input to an amplifier is 2µW. The
large. power gain of the amplifier is 40 dB. The
Class-B Amplifier - In this amplifier we get high output power of the amplifier is
efficiency (78.5%) with crossover distortion. (a) 80 µW (b) 200 µW
Class-AB push-pull amplifier - In this amplifier we (c) 20 mW (d) 80 mW
get medium efficiency (50% to 78.5%) with minimum RPSC Vice Principal ITI -2016
distortion. IES-2002
Class-C Amplifier - In this amplifier we get maximum Ans. (c) : Given,
efficiency (87.5%) with Harmonic generator class-C Input Power, P = 2µW
in
amplifiers output is heavily distorted.
Power Gain in dB, A ( dB ) = 40dB
72. An amplifier has a D.C. power supply of 15V
and draws a current of 10 mA. It produces an A ( dB ) = 10 log ( A )
output of 5V peak across a load resistance of
40 = 10log ( A )
600Ω for a signal frequency of 1 kHz. What
will be its A.C. power output? A = 104
(a) 260 mW (b) 20.8 mW A = 10000
(c) 520 mW (d) 40.6 mW
P
IES-2004 Gain, A = out
Pin
Ans. (b) : Given,
Peak voltage, VP = 5 V, P out = A × P in
Load Resistance, RL = 600Ω = 10000 × 2 × 10–6

= 10 4 × 2 × 10 −6
VP2
Po( ac ) = Pout = 20 mW
2R L
52 75. A class-B push-pull type amplifier with
Po ( ac ) = transformer coupled load used two transistors
2 × 600 rated 10W each. What is the maximum power
25 output one can obtain at the load from this
= circuit?
1200
(a) 40 W (b) 50 W
Po( ac ) = 20.8mW (c) 60 W (d) 70 W
73. A D.C. to D.C. converter has an efficiency of IES-2002
80% and is supplying a load of 24 W at 240 V. Ans. (b) : Given,
What is the current drawn from the battery if Power dissipation across each transistor = 10W
the converter is working from a battery of Total rating of transistor = 20W.
12V? Class-B push pull amplifier figure of merit (F) = 0.4
(a) 0.1 A (b) 2.0 A Pdc( max )
(c) 2.5 A (d) 10 A ∵ Figure of merit (F) =
PAC( max )
IES-2004
Ans. (c) : Given, 20
PAC( max ) = = 50Watt
Efficiency, η = 80% = 0.8 0.4
Input voltage, Vin = 12 V 76. Consider the following statements:
Output Power Po = 24 W Sziklai pair
P 1. Is also called complementary Darlington
η= o 2. Acts like a single p-n-p transistor with a
Pin
very high current gain
Po 3. Can be used in class B push-pull power
Pin =
η amplifier

Which of these statements are correct? 0.1×10−6
(a) 1 and 2 (b) 1 and 3 D% = × 100
5 × 10−6
(c) 2 and 3 (d) 1, 2 and 3 D = 0.02 × 100
IES-2000
D = 2%
Ans. (b) : Sziklai pair :-
A class-B amplifier
1. Is biased just at cut-off
2. Has a high theoretical efficiency of 78.5%
because its quiescent current is low.
3. Is biased at the mid-point of load line
of these statements
(a) 2 and 3 are correct (b) 1 alone is correct
(c) 2 alone is correct (d) 1 and 2 are correct
TSPSC Manager (Engg.)-2015
TNPSC AE-2008, IES-1998
Ans. (d) : An amplifier in which operating point is
located at an extreme end of load line (i.e. either in
Sziklai Pair transistor is also known as compound or saturation region or in cut-off region) is known as
pseudo-Darlington pair. This transistor pair consists of Class-B amplifier.
two bipolar transistor pairs, where one is npn and A Class-B amplifier has a high theoretical efficiency
another is pnp. of 78.5% because its quiescent current is low.
The Sziklai pair looks similar to the Darlington pair. 80. The dissipation at the collector is zero in the
Sziklai pair is also called complementary Darlington. quiescent state and increase with excitation in
Sziklai pair can be used in class B push-pull power the case of a
amplifier. (a) Class A series-fed amplifier
77. Which of the following contributes to (b) Class A transistor coupled amplifier
harmonics distortion in amplifiers? (c) Class AB amplifier
(a) Non-linearity in active device (d) Class B amplifier
(b) defective device IES-1997
(c) presence of noise Ans. (d) : The dissipation at the collector is zero in the
(d) positive feedback quiescent state and increase with excitation in the case
RRB SSE 21.12.2014, (Yellow) of a Class-B amplifier. In Class-B amplifier output
signal is half-sinusoidal or distorted.
Ans. (a) : Harmonics distortion in amplifier is mainly
caused by the nonlinearities of the active elements 81. Match List-I with List-II and select the correct
(transistors). answer using the codes given below the lists:
Harmonics distortion is the distortion in output List-I List-II
waveform due to the generation of harmonics. (Amplifier type) (Circuit/property)
A. Class A single 1. Requires PNP
78. If a class-C power amplifier has an input signal
ended & NPN
with frequency of 200 kHz and the width of transistor pairs
collector current pulses of 0.1 µs, then the duty
B. Class B push pull 2. Prevents cross-
cycle of the amplifier will be
transformer over distortion
(a) 1 % (b) 2 % coupled
(c) 10 % (d) 20 % C. Class AB push- 3. has maximum
IES-1999 pull efficiency
Ans. (b) : Given, among these
Frequency, f = 200 kHz amplifiers
Pulse width, τ = 0.1 µs D. Class AB 4. Has minimum
= 0.1 × 10–6sec complementary efficiency
symmetry among these
1
Time period, T = amplifiers
f Codes:
1 A B C D
=
200 × 103 (a) 4 3 2 1
T = 5 µsec (b) 4 2 3 1
T = 5 × 10–6 sec (c) 1 2 3 4
τ (d) 3 2 1 4
For class-C amplifier duty cycle D = IES-1996
T
Ans. (a) : Class-A amplifier has minimum efficiency C. Complementary 3. A Circuit with
among all amplifier. Its conversion efficiency is (0 to Symmetry overall voltage
50%). Amplifier gain close to 1
Class-B push pull transformer coupled amplifier has and very large
maximum efficiency among the given amplifiers. input
Class-AB push-pull amplifier prevents cross-over impedance.
distortion. D. Cascode 4. A Circuit with
Class-AB complementary symmetry requires PNP Amplifier low input
and NPN transistor pairs. impedance
82. A class-B push-pull power amplifier uses two mainly used in
transistor each having a power dissipation high frequency
capacity of 2 watts. The maximum power that applications.
the circuit can deliver to the load without Codes:
extending the power dissipation capacity of the A B C D
transistor is (a) 1 2 3 4
(a) 1 Watts (b) 2 Watts (b) 2 1 4 3
(c) 5 Watts (d) 10 Watts (c) 3 4 1 2
IES-1995 (d) 4 3 2 1
Ans. (b) : The push-pull amplifier is a power amplifier IES-1994
is used in the output stages of electronic circuits. It is Ans. (c) :
used whenever high output power at high efficiency is • Darlington amplifier is a circuit with overall voltage
required. In the Class-B push-pull amplifier at a time gain close to 1 and very large input impedance.
only one transistor will be conduct. Hence overall • Common base amplifier is a circuit with low input
power dissipation will be equal to that of a single impedance mainly used in high frequency
transistor Pd = 2 watt. applications.
83. Consider the following statements: • Complementary symmetry amplifier is a circuit using
A power amplifier uses bridge rectifier with two (npn and pnp) transistors used in power
capacitor input filter. If one of the diode is amplifier.
defective, then. • Cascode amplifier is a common-source amplifier
1. The dc load voltage will be lower than its driving a common gate amplifier.
expected value.
85. Match the following:
2. Ripple frequency will be lower than its
expected value List-I List-II
3. The surge current will increase many fold. (efficiency) (class of amplifier)
Which of the statements are correct A. < 50% (1) A
(a) 1 and 2 are correct B. > 50% (2) AB
(b) 1 and 3 are correct C. 78.5% (3) B
(c) 2 and 3 are correct D. 100% (4) C
(d) 1, 2 and 3 are correct Codes:
IES-1995 A B C D
(a) 2 1 4 3
Ans. (d) : A power amplifier used bridge rectifier with
(b) 1 3 4 2
capacitor input filter. If one of the diode is defective,
then the DC load voltage will be lower than its expected (c) 1 2 3 4
value. The surge current will increase many fold. (d) 4 1 2 3
84. Match List-I with List-II and select the correct KVS TGT (WE)- 2016
answer using the codes given below the lists: IES-1991
List-I List-II Ans. (c) :
(Name of the circuit) (Characteristics of Class of Amplifier Efficiency
the circuit) Class-A 50% (Maximum)
A. Darlington 1 A circuit using Class-B 78.5%
Amplifier pnp and npn Class-AB 50% - 78.5%
transistors used
in power Class-C >90%
amplifier. 86. An amplifier has an input power of 2
B. Common base 2. A Common- microwatts. The power gain of the amplifier is
Amplifier source Amplifier 60 dB. The output power will be
driving a (a) 6 microwatts (b) 120 microwatts
common gate (c) 2 milliwatts (d) 2 watts
amplifier. IES-1991
Ans. (d) : Given, Pi = 2 µW = 2 × 10–6 W 89. For a class-A FET power amplifier with 10V
Gain = 60 dB drain supply and 2A drain current bias
providing RF load current of 1A amplitude.
Gain ( dB ) = 10log ( Gain ) What is the DC to RF efficiency for load
60 = 10 log (Gain) resistance of 5Ω?
Gain = 106 (a) 50% (b) 25%
(c) 35% (d) 12.5%
Pout ISRO Scientist Engg. -2015
Gain =
Pin Ans. (d) : Given,
Pout Drain supply voltage VDD = 10V, Drain current ID = 2A
10 =
6
2 × 10−6 RF load current IL = 1A =

1
A(r.m.s value)
Pout = 2W 2
Load resistance RL = 5Ω
answer using the codes given below the lists: V ×I
% RF efficiency η = CE L × 100
List-I List-II VDD × I D
(Maximum (Amplifiers) 2
efficiency in  1 
I 2L × R L   ×5
percentage)
= × 100 =  2
×100
A. 25 1. Class-B transformer VDD × I D 10 × 2
coupled
B. 78.5 2. Class- A RC coupled 5
C. 100 3. Class- A transformer = 2 × 100 ⇒ η = 12.5%
coupled 20
D. 50 4. Class- D switching mode 90. A class – A transformer coupled, transistor
Codes: power amplifier is required to deliver a power
A B C D output of 10 watts. The maximum power rating
(a) 1 2 3 4 of the transistor should not be less than
(b) 2 3 4 1 (a) 5 W (b) 10 W
(c) 2 1 4 3 (c) 20 W (d) 40 W
(d) 3 4 1 2 GPSC Asstt. Prof.11.04.2017
Nagaland PSC (Degree)-2018, Paper-II GATE-1994
Mizoram PSC Jr. Grade- 2015, Paper-II Ans. (c) : Given,
IES-1991 Deliver a power output, PAC = 10 W
Ans. (c) : Po( max )
Class of Amplifier Efficiency ∵ = 2 (For class A amplifier FOM = 2)
PAC( max )
Class-A (for transformer 50%
coupled) Maximum power Rating of the Class-A transformer
Class-A (for RC coupled) 25% coupled amplifier
Class-B 78.5% Po( max ) = 2PAC( max )
Class-AB 50% - 78.5% = 2 × 10
Class-C >90% Po( max ) = 20W
88. An amplifier's power level is changed from
8, watts to 16 watts, equivalent dB gain is 91. Unit of thermal resistance that is used in the
design of heat sinks (for power amplifiers) is
(a) 2 dB (b) 6 dB (a) Ohms (b) ºC
(c) 3 dB (d) 5 dB (c) ºC/Ohms (d) ºC/Watt
TNPSC AE-2013 TSGENCO AE-2015
P  Ans. (d) : Thermal Resistance- Absolute thermal
Ans. (c) : Gain dB = 10log  2  resistance is the temperature difference across a
 P1  structure when a unit of heat energy flows through it in
unit time.
 16 
= 10log   It is the reciprocal of thermal conductance. SI unit of
8 thermal resistance is Kelvin per watt (K/W) or °C/W.
= 10 × 0.3010 It is used in design heat sink.
= 3.010 dB 92. The voltage gain of a common emitter
3dB amplifier is :
(a) directly proportional to collector bias current
(b) inversely proportional to collector bias Ans. (a) : Bandwidth equation of double tuned
current transformer
(c) independent of collector bias current BWdt = k.f r
(d) proportional to square of collector bias k is coupling coefficient
current fr is resonant frequency.
BSNL(JTO)-2002 97. In a common source amplifier, the mid-band
Ans. (a) : The voltage gain of a common emitter voltage gain is 40 dB and the upper cut-off
amplifier is directly proportional to collector bias frequency is 150 kHz. Assuming single pole
current. approximation for the amplifier, the unity gain
frequency fT is
Ic
β= (a) 6 MHz (b) 15 MHz
Ib (c) 150 MHz (d) 1.5 GHz
DRDO-2008
β − Rc
AV = Ans. (b) : Given,
Rb Mid-band voltage gain = 40 dB
93. Class A amplifiers are characterized by 40dB = 20log10 ( A V )
(a) Maximum efficiency and minimum distortion A = 100
V
(b) Minimum efficiency and maximum distortion
For amplifier gain bandwidth product is constant
(c) Maximum efficiency and maximum distortion
(d) Minimum efficiency and minimum distortion So, f T = 100 × 150 × 10
3
Kerala PSC Lecturer (NCA) 04.07.2017 = 15 × 10

6
Nagaland PSC CTSE 2015, Paper-II = 15MHz

Ans. (d) : Class A amplifier has minimum efficiency 98. From a measurement of the rise time of the
and minimum distortion. Class A amplifier is a high output pulse of an amplifier whose input is a
gain amplifier with high linearity. small amplitude square wave, one can estimate
94. An amplifier power level is changed from 8 the following parameter of the amplifier
watts to 16 watts, equivalent dB gains is (a) Gain-bandwidth product
(a) 2 dB (b) 3 dB (b) Slew rate
(c) Upper 3 dB frequency
(c) 6 dB (d) 5 dB
(d) Lower 3 dB frequency
 P2 
Ans. (b) : Gain in dB = 10 log   0.35
 P1  Ans. (c) : t r =
f rdB
 16  ∴ Upper 3 dB frequency can be found.
G = 10 log  
8 99. A power amplifier can safety deliver a load
G = 10 log 2 power of 10 W at an ambient temperature of
G = 10 × 0.3010 25ºC. If the maximum allowable junction
G = 3.01 dB temperature is 125ºC, how much power can be
safely delivered to the load if the ambient
95. The main function of the transformer used in temperature increase in 75ºC?
the output of a power amplifier is (a) 7.5 W (b) 2.5 W
(a) to step up the voltage
(c) 8 W (d) 5 W
(b) to step down the voltage
(c) to match the load impedance with dynamic BSNL (JTO)-2001
output resistance of the transistor Ans. (d) : Given,
(d) to increase voltage gain Delivered a load power = 10W
TSPSC Manager (Engg.) - 2015 T1 = 125, T2 = 25
Ans. (c) : An output transformer improves the 125 − 25
efficiency of the amplifier by matching the impedance K = 10 = 10 º C W
of the load with that of amplifier output impedance.
125 − 75
96. The bandwidth of a double tuned transformer Therefore, P = = 5W
10
coupled amplifier can be adjusted by varying
100. For a class-A power amplifier, supply dc
the
(a) coupling coefficient voltage is ± 12 V, the quiescent collector
current is 72 mA and the load resistance is 100
(b) value of the inductance
Ω. If the output voltage across the load is 12 V
(c) value of the emitter biasing resistance peak-to-peak, the efficiency of the amplifier is
(d) value of resistance (neglect the loss occurring in the biasing
TSPSC Manager (Engg.) - 2015 resistors) :
(a) 10.4% (b) 20.8% Ans. (b) : η = 50% for Class - A Amplifier
(c) 25% (d) 33.3%
DRDO-2009 Po( AC)
η=
Ans. (b) : Given value, PI( DC)
Supply dc voltage - 1 1.25
VCC = 12V =
2 PI(DC)
Quiescent collector current, IC = 72mA PI(DC) = 2.50 Watt
Peak-to-peak output voltage 104. Class-B amplifier has less efficiency compared
Vp− t − p = 12V to
Max output voltage- (a) Class-A
1 12 (b) Class-AB
Vm = Vp − t − p = = 6V (c) Class-C
2 2 (d) Class-A, Class-AB and Class-C
Output current-
V 6
Im = m = = 0.06A Ans. (c): Class-B amplifier has less efficiency
R L 100 compared to class-C amplifier
So, efficiency of the amplifier, Class of Amplifier Efficiency
1 Class-A (for transformer 50%
Vm Im
coupled)
%η = 2 × 100
VCC IC Class-A (for RC coupled) 25%
1 Class-B 78.5%
× 6 × 0.06 Class-AB 50% - 78.5%
%η = 2 × 100
12 × 72 × 10−3 Class-C 90%
%η = 20.8% 105. Push-pull amplifier has high power efficiency
because
101. Where does the operating point of class-B
(a) Transistors are placed in CE configuration
power amplifier lie?
(b) There is no quiescent collector current
(a) At the middle of A.C. load line
(c) Each transistor conducts on different input
(b) Approximately at collector cutoff on both the
cycles
D.C. and A.C. load lines
(d) Low forward biasing voltage is required
(c) Inside the collector cutoff on both the D.C.
and A.C. load lines MPPSC Forest Service Exam.-2014
(d) At the middle point D.C. load line Nagaland PSC CTSE- 2015, Paper-II
Nagaland PSC (Degree) 2018, Paper-II Ans. (b) : The efficiency of power push pull amplifier
ISRO Scientist Engg.-2008, IES - 2006 is much higher due to distortion keep within acceptable
limit and there is no quiescent collector current.
Ans. (b) : The operation point of class B amplifier lies
approximately at collector cut-off on both D.C. and 106. At lc=2.5 mA (at room temperature 2950 K)
A.C. load lines. rπ = 1000 Ω . β is given by
102. A Tuned amplifier cannot be used in (a) 2500 (b) 250
(a) Television receiver (b) Radio transmitter (c) 1000 (d) 100
(c) Power supply (d) Radio receiver
TNPSC AE- 2019 Ans. (d) : Given : IC = 2.5 mA, rπ = 1000 Ω
Ans. (c) : A tuned amplifier is an electronic amplifier β = gm rπ
which includes band pass filtering components within I C × rπ 2.5 × 10 –3 × 1000  IC 
the amplifier circuitry. They are widely used in a variety β = V = 25 × 10 –3 Q g m = 
VT 
T 
of wireless applications. There are several tuning
schemes in use, staggered tuning where each amplifier β = 100
stage is tuned to a slightly different frequency. So tuned 107. Which of the following statement(s) is/are true?
amplifier cannot be used in power supply. I. An amplifier must be powered and have an
input signal to develop a normal output
103. Single stage transformer coupled class A signal.
amplifier delivering the A.C. power to load of II. An amplifier has a voltage gain of 50. If the
1.25 watts. The D.C. power from the D.C. input signal is 2 mV, the output signal should
supply is be 50 mV.
(a) 1.25 W (b) 2.5 W III. The input signal to an amplifier is 100 μV,
(c) 5 W (d) 0.65 W and its output signal is 50 mV, so its voltage
Nagaland PSC CTSE- 2015, Paper-II gain is 500.
(a) II and III (b) I only 111. Class AB operation is often used in power
(c) I and III (d) I and II amplifiers in order to
NLC GET -24.11.2020 (a) get maximum efficiency
Ans. (c) : Given value, (b) remove even harmonics
Statement -I Amplifiers produces no output till a (c) overcome a cross-over distortion
signal is fed to the input. (True). (d) reduce collector dissipation.
Statement II- A V = 50, Vin = 2mV KVS TGT (WE)- 2017, BEL-2015
then output voltage will be TRB Poly. Lect. -2012
Vo = 50 × 2mV Ans. (c) : Class-A amplifier - No cross over distortion
occurs as they are biased in the centre of the load line.
= 100mV ( false ) Class-B amplifier- Large amount of cross distortion
Statement - III - Vin = 100µV due to biasing at the cut off point.
Class- AB amplifier- Crossover distortion is biasing
Vo = 50mV level is avoid the cut off.
−3
V 50 ×10 112. Which power amplifier conducts from 0° to
then A V = o = −6 180°
Vin 100 ×10
(a) Class-A (b) Class-B
A V = 500 ( True ) (c) Class-AB (d) Class-C
108. The cross-over distortion in class B push-pull AAI-2015
amplifier is eliminated by Ans. (b) :
(a) Operating the amplifier as class C 1. Class- A Amplifier conduct from full cycle (360º)
(b) Operating the amplifier as class AB 2. Class-B Amplifier conduct from 0º to 180º.
(c) Eliminating the output transformer 3. Class-C Amplifier conduct from less than half cycle
(d) Reducing the biasing of the transistors of the input signal.
Nagaland PSC CTSE- 2015, Paper-II 113. Class C amplifier operates
Ans. (d) : A simple way to eliminate crossover (a) Entire cycle of input signal
distortion in a class B amplifier is to add two small (b) Half of the cycle of input signal
voltage to the circuit to bias both the transistor at a point (c) Slightly more than half of the cycle of input
slightly above their cut off. signal
109. The output voltage two stage amplifier as (d) Less than half of the cycle of input signal
shown in figure is : ISRO Scientist- May, 2017
UJVNL AE-2016, TNPSC AE-2013
Ans. (d) : The class C power amplifier is one kind of
amplifier where the transistor conduct for less than 180º
(One-half cycle of the input signal) and its typical value
is 80º to 120º.
114. A particular amplifier circuit used for
(a) 10 V (b) 8.1 V frequency doubling is
(c) 9 V (d) 7.3 V (a) Push-push (b) Push-pull
MPSC HOD Govt. Poly. -2013 (c) Pull-push (d) Pull-pull
V ISRO Scientist- May, 2017
Ans. (a) : 0 = A v1 × A v2 Ans. (a) : Frequency doubler means Amplifier should
Vin
work like a full wave rectifier.
V0 Push-push amplifier allows for a fully active full wave
= 100 × 100
1mV rectifier. Centre tapped full wave and bridge rectifier
−3
V0 = 10 × 10 × 10 3 can work as a frequency doubler.
V0 = 10V 115. A single stage non-inverting amplifier has
R F = 220kΩ and R 1 = 10kΩ. If two such stages
110. One of the advantage of base modulation over
collector modulation of a transistor Class C are cascaded, find the mid frequency gain of
amplifier is the cascade.
(a) The lower modulating power required (a) 27.23 dB (b) 54.47 dB
(b) Higher power output power required (c) -54.47 dB (d) -27.23 dB
(c) Higher power output per transistors UPPCL AE-05.11.2019
(d) Better efficiency RF
Nagaland PSC CTSE (Degree)-2017, Paper-II (b) : A V = 1 + R
1
Ans. (a) : One of the advantages of base modulation
over collector modulation of a transistor class C A = 1 + 220
V = 23
amplifier is the lower modulating power required. 10
∴ A V 1 = A V2 = 20log 23 = 27.23 dB. Feedback factor - β = 0.008
Barkhausen criterion for oscillatory system -
A V = A V1 + A V2 = 27.23 + 27.23
Aβ = 1 ................ (i)
A V = 54.46 dB Equivalent gain A = A × A × A
116. The amplifier which retains the shape of the
A = (A)
3
input signal at the output are called−

(a) Distortion amplifier (b) Pulse transformer  A0 
3
(c) Non-linear amplifier (d) Linear amplifier A =  

RRB JE-01.09.2019, 3:00 PM – 5:00 PM  2 
Ans. (d) : The amplifier on which the given input signal A3
A = 0 ................ (ii)
does not change in the shape of the signal received at its 8
output. From equation (i) & (ii)
It is called linear amplifier. 1
In linear amplifier the signal at the output is in the same A =
β
shape as the input. When the input signal delivered to a
device is low, an amplifier is placed or used before the A 30 1
device to amplify. There are mainly four types of =
8 0.008
amplifiers.
8000
(a) Class A amplifier A 30 =
(b) Class B amplifier 8
(c) Class C amplifier A 30 = 1000
(d) Class D amplifier A 0 = 10
117. A circuit designed to increase the level of its
input signal is called: 2. For negative feedback amplifiers, which one of
(a) an amplifier (b) a modulator the following statement is true?
(c) an oscillator (d) a receiver (a) Its output impedance and distortion increases
RRB SSE 03.09.2015 Shift-II (b) Its input impedance and distortion increases
Ans. (a) : A circuit designed to increase the level of its (c) Its gain and distortion decreases
input signal is called amplifier. (d) Its gain and B.W. decreases
The only use of amplifier in a circuit is to provide UPPSC ITI Principal/Asstt. Director-09.01.2022
strength to signal. GPSC Asstt. Prof.-11.04.2017
Ans. (c) : Negative feedback amplifier
(vi) Feedback amplifiers Af =
A
1 + Aβ
1. Three amplifiers of gain Reduces the distortion
A  Reduces noise
A =  0  ∠ - 60º Increase bandwidth
 2 
Reduce the gain
are connected in tandem. The feedback loop is
closed through a positive gain of 0.008 : Increase stability
3. An amplifier has an open loop gain of 200, an
input impedance of 2KΩ and an output
impedance of 200Ω. If a feedback network
with a feedback factor 0.99 is connected in a
voltage series feedback mode, then new input
impedance and output impedance are
(a) 398 kΩ and 1 kΩ (b) 398 kΩ and 1Ω
(c) 398 Ω and 1kΩ (d) 398Ω and 1 Ω
The magnitude of A0 for the system to be
oscillatory will be
(a) 0.2 (b) 0.1 Ans. (b) : Given,
(c) 5.0 (d) 10.0 A = 200 , β = 0.99 , R i = 2kΩ , R 0 = 200Ω
UPPSC ITI Principal/Asstt. Director- 09.01.2022 So, 1 + Aβ = 1 + 200 × 0.99
IES – 2019, 2005 = 1 + 198
Ans. (d) : Given, = 199
 A0  In voltage series feedback
A=  ∠ − 60º R if = R i (1 + Aβ )
 2 

R if = 2kΩ (199 ) GATE-2009, 2005, 2004, 2002, 1998, 1995
BSNL (JTO)-2002, 2001
= 398kΩ
Ans. (d) :
R0 Feedback Input Output Gain Input Output
R of = Resistance
1 + Aβ Resistance
Voltage Voltage Voltage AV Increase Decrease
200
R of = series
199 Current Voltage Current GM Increase Increase
R of = 1.005 series
R of 1Ω Voltage Current Voltage RM Decrease Decrease
shunt
4. With reference to the negative feedback voltage Current Current Current AI Decrease Increase
- series configuration, which of the following Shunt
statements is/are correct? 7. Which of the following describe the correct
1. Bandwidth increases. properties of an emitter follower circuit ?
2. Non-linear distortion decreases. 1. It is a voltage series feedback circuit.
Select correct answer. 2. It is a current series feedback circuit.
(a) Only 1 (b) Only 2 3. Its voltage gain is less than unity.
(c) Both 1 and 2 (d) Neither 1 nor 2 4. Its output impedance is very low.
Select the correct answer from the codes given
Ans. (c) : Negative feedback voltage series below:
configuration voltage series configuration (a) 1, 3 and 4 (b) 2, 3 and 4
(1) Bandwidth increases. (c) 2 and 3 only (d) 2 and 4 only
(2) Non - linear distortion decreases. Nagaland PSC-2018 Diploma Paper-II
5. Voltage gain with feedback Avf = . KVS TGT (WE)- 2017
(a) Vo – Vi (b) Vs × Vo Nagaland PSC (CTSE) Diploma-2017 Paper-II
V Nagaland PSC (CTSE) Diploma-2015 Paper-II
(c) Vi + Vo (d) o IES - 2009
Vs
Ans. (a) : Common collector circuit is also known as
UPRVUNL AE -19.07.2021, Shift-II emitter follower. Emitter follower's voltage gain is
Xo Vo slightly less than unity. Its current gain is high. Emitter
Ans. (d) : A vf = = follower uses voltage-series feedback. Its input
Xs Vs resistance is high and output resistance is low. This
6. Match List-I (Type of Feedback) with List-II makes it an ideal circuit for impedance matching.
(Effect on Rin and Rout) and select the correct 8. Negative feedback amplifier is a –––––––
answer using the code given below the lists (a) Degenerative feedback
List-I List-II (b) Regenerative feedback
(A) Voltage series 1. Rin increase and (c) Both
Rout decreases (d) None
(B) Voltage Shunt 2. Rin and Rout SAIL- 2014
decrease
Ans. (a) : Negative feedback also referred as
(C) Current Series 3. Rin and Rout
degenerative feedback is a widely used type of feedback
increase in the control system. Here the signal at the output
(D) Current shunt 4. Rin decreases and which is out of phase with respect to the input is fed
Rout increases. back to the input.
Codes: 9. The amplifier A shown in the figure has open
A B C D loop gain of 100, input impedance Zin, of 1 kΩ
(a) 1 4 3 2 and output impedance Z0 of 100Ω. If a negative
(b) 3 2 1 4 feedback factor β = 0.99 is used, the new values
(c) 3 4 1 2 of Z1 and Z0 are respectively:
(d) 1 2 3 4
Nagaland PSC CTSE (Degree)2018, Paper-II
KVS TGT (WE)-20017
Nagaland PSC CTSE (Degree)2017, Paper-II
GPSC Asstt. Prof.-11.04.2017
Punjab PSC Poly. Lect.20.08.2017
Mizoram PSC IOLM- 2010, Paper-II
Nagaland PSC CTSE -2015, Paper-II
IES – 2009, 2008, 2007, 2003 1992
(a) 10 Ω and 1 Ω (b) 10 Ω and 10 Ω
104
(c) 100 kΩ and 1 Ω (d) 100 kΩ and 10 Ω Av =
KVS TGT (WE)-2018, BPSC Poly. Lect.-2014  2 ×106 
1+  3 
IES-2013, GATE-1999  100 × 10 
Ans. (c) : Given value – 104
Input impedance Zin = 1kΩ Av =
1 + 20
Output impedance Z0 = 100Ω A v = 2182.179
Gain A = 100
log A v = 3.33
β = 0.99
20log A v 66.66dB
Q Input resistance with feedback
12. If an amplifier with gain of -1000 and feedback
Zif = Zin (1 + Aβ ) factor of β = -0.1 had a gain change of 20% due
Zif = 1 × 103 (1 + 100 × 0.99 ) to temperature, the change in gain of the
feedback amplifier would be
= 103 × (1 + 99 ) (a) 10% (b) 5%
= 100 × 103 (c) 0.2% (d) 0.01%
= 100kΩ TNPSC AE- 2019
Q Out put resistance with feedback IES - 1997
Z0
Zof = Ans. (c) : Given,
1 + Aβ Open loop gain = –1000
Zof =
100
=
100 100
= Feedback factor, β = – 0.1
1 + 100 × 0.99 1 + 99 100 Gain change of 20%
Zof = 1Ω ∂A
= 20% = 0.20
10. The voltage gain of an amplifier is 100. A A
negative feedback is applied with β = 0.03. The Gain change with feedback
overall gain of the amplifier is: ∂A f ∂A . 1
(a) 70 (b) 25 =
Af A 1 + Aβ
(c) 99.97 (d) 3
Nagaland PSC CTSE (Diploma)-2018, Paper-I 1
= 0.20 ×
TSPSC Manager (Engg.) - 2015 1 + ( −1000 )( −0.10 )
IES - 2013
∂A f 0.20
Ans. (b) : Given, =
Gain, A = 100 Af 101
Feedback, β = 0.03 ∂A f 0.20
A %= × 100%
Overall gain, A f = A f 101
1 + Aβ ∂A f
100 % = 0.198%
= Af
1 + 100 × 0.03
∂A f
A f = 25 % ≃ 0.2%
Af
11. The voltage gain of an amplifier decreases at 20
dB/decade above 100 kHz. If the mid band 13. If each stage has a gain of 10 dB, and noise
frequency gain is 80 dB. What is the value of figure of 10 dB, then the overall noise figure of
the voltage gain at 2 MHz? a two-stage cascade amplifier will be
(a) 60 dB (b) 52 dB (a) 10 (b) 1.09
(c) 54 dB (d) 64 dB (c) 1.0 (d) 10.9
TNPSC AE-2014 ISRO Scientist Engg.-2008
Ans. (d) : 20log A v = 80dB Ans. (d) : G1 = 10dB
f1 = f2 =10 dB
80dB
log A v = f −1
20 The overall noise figure (f) = f1 + 2
A = 10 4 G1
v
10 − 1
Av ( mid ) = 10 +
Av = 10
2
 f  = 10 + 0.9
1+  2 
f  = 10.9

14. A 10dB attenuator is put at the input of a low
noise amplifier having 3dB noise figure. Now
the noise figure of the cascaded amplifier will
be
(a) 3dB (b) 12dB
(c) 7dB (d) None of the above
Q 40kΩ and 60 kΩ act as voltage dividers for V0 ,
Ans. (c) :
V × 60 60 6
( SNR )i / p Vi = 0 =
60 + 40 100
V0 = V0
Noise figure = 10
( SNR )o / p 3
Vi = V0
( N.F.)dB = (SNR )i / p  dB − ( SNR )o / p  dB 5
Q Ideal op-amp A v = ∞
Given value, ( SNR )i / p = 10dB V V
Vid = 0 = 0 = 0 = V + − V −
(SNR ) = 3dB
o/p
A v V∞
So, noise figure of the cascaded amplifier, V+ − V− = 0
( N.F.)dB = 10 − 3 = 7dB V + = V − (virtual ground)
Q Vz = Vi − VBE
15. Negative feedback in amplifiers
(a) improves the signal to noise ratio at the I/P Where VBE = 0.7V, Vz = 5.3V
(b) improves the signal to noise ratio at the O/P 3
5.3 = V0 − 0.7
(c) Doesn't affect the Signal to Noise ratio at the 5
O/P 3
(d) All of these V0 = 6
5
ISRO Scientist Engg.-2016 V = 10V
0
GATE-1993
17. The gain of an amplifier without feedback is
Ans.(b): Negative feedback-
100 db. If a negative feedback of 3 db is
A applied, the gain of the amplifier will
Af =
1 + Aβ become……..
(a) 5 db (b) 300 db
Reduces the distortion
(c) 103 db (d) 97 db
Reduces noise Nagaland PSC (CTSE) Diploma-2017, Paper II
Increase bandwidth
Ans. (d) : AV = 100 dB
Reduce the gain
β = 3dB
Increase stability
Av= [20 log AV] –[ 20 log β ]
Negative feedback in amplifiers improves the Signal to
Noise ratio at the O/P = 100 -3
16. In the given circuit, Vbe = 0.7 V, Vz = 5.3V, β = A v = 97dB
100. Vo is 18. A feedback circuit usually employs….network
(a) Resistive (b) Capacitive
(c) Inductive (d) None of the above
Ans. (a) : A feedback circuit should not vary with time.
Hence resistor is used as feedback element because it
always constant with respect to time and frequency.
19. The gain of an amplifier with feedback is
known as……….gain
(a) 5V (b) 10V
(a) Resonant (b) Open loop
(c) 15V (d) 20V
(c) Closed loop (d) None of the above
Ans. (b) : Given value,
Ans. (c) : The gain of an amplifier is known as open
Vbe = 0.7V loop gain but when feedback is connected, this loop
Vz = 5.3, β = 100, find V0 = ? gain is called close loop gain.

20. Current gain with feedback Aif = . If Vf
(c) β = (d) β =
(a) Io + Ii (b) Is – Io Vo Io
I TNPSC AE – 2018
(c) Ii × Io (d) o
Is Ans. (a) : Feedback factor ( β ) - The feedback factor
UPRVUNL AE -19.07.2021, Shift-II for a voltage shunt feedback amplifier is the ratio of
XO Vf
Ans. (d) : Gain of feedback Amplifier = feedback current and output signal voltage β =
Xs V0
I0 25. In a voltage-voltage feedback as shown below,
∴ Current gain with feedback = which one of the following statements is TRUE
Is
if the gain k is increased?
21. For a voltage series feedback topology, if β =
0.01, A = 50 and R1 = 2.87 kΩ, then the Rif is
.
(a) 4.30 kΩ (b) 3.43 kΩ
(c) 1.78 kΩ (d) 1.91 kΩ
Ans. (a) : Given, (a) The input impedance increases and output
β = 0.01 impedance decreases
A = 50 (b) The input impedance increases and output
impedance also increases
R1 = 2.87kΩ
(c) The input impedance decreases and output
In voltage series F.B, Rif = Ri × D impedance also decreases
D = 1+βA (d) The input impedance decreases and output
= 1+0.01(50) impedance increases
3 GATE-2013
D= Nagaland PSC (CTSE) Diploma -2017 paper-II
2
Ans. (a) :
Rif = Ri×D
3
= 2.87 ×
2
R if = 4.305kΩ
22. The positive feedback reduces
(a) Instability (b) Distortion
(c) Noise (d) Bandwidth A voltage-voltage feedback in the above figure is also
TNPSC AE – 2018 known as voltage-series feedback amplifier. In voltage-
UPRVUNL AE– 11.06.2014 series feedback amplifier, the input impedance increases
and output impedance decreases.
Ans. (d) : A positive feedback is used to increase gain
and phase margin. Zi = Z'i (1 + A 0 k )
Hence the band width will reduce. A positive feedback Z'0
system is used as an oscillator. Z0 =
(1 + A 0 k )
23. Which one of the following is wide band
amplifier? 26. Voltage amplifier uses feedback
(a) RF amplifier (b) IF amplifier topology.
(c) Video amplifier (d) AF amplifier (a) current series (b) voltage shunt
IES-2004 (c) voltage series (d) current shunt
Ans. (c) : Video amplifier is wide band amplifier.
Video amplifier is used in television, radar, Ans. (c) :
oscillographs and other equipment to amplify video
signal. Video amplifier has large bandwidth which is
required for video signal.
24. The feedback factor β for a voltage shunt
feedback amplifier is given by
V I
(a) β = f (b) β = f
Vo Io

Type of Negative feedback (a) Decreases (b) Becomes unity
Charact (c) Remains constant (d) Increases
eristic Nagaland PSC (Degree)-2018, Paper-II
Voltage Voltage Current Current Mizoram PSC IOLM -2018, Paper II
series shunt series shunt
Voltage Decrease Decrease Decrease Decrease
gain Ans. (c) : Cascading increase lower cut-off and
Bandwidth Increase Increase Increase Increase decrease higher cut-off frequency, decrease bandwidth.
In cascading connection, voltage gain increases which
Ri Increase Decrease Increase Decrease
in turn reduces the bandwidth to maintain a constant
R0 Decrease Decrease Increase Increase gain-bandwidth product.
Harmonic Decrease Decrease Decrease Decrease 31. If gain of positive feedback amplifier is 18 and
distortion
feedback factor is 0.5, the gain of the amplifier
Noise Decrease Decrease Decrease Decrease without feedback will be -
27. The open loop transfer function of an amplifier (a) 1.8 (b) 2
with resistive negative feedback has two poles (c) 3.6 (d) 5
in the left half s-plane. Then the amplifier. UPPCL AE-16.11.2013
(a) will always be unstable at high frequencies
Ans. (a) : Given,
(b) will be stable at all frequencies
β = 0.5
(c) may become unstable depending upon
feedback factor A f = 18
(d) will oscillate at low frequencies A
Mizoram PSC IOLM-2010, Paper-II A f = 1 − Aβ
IES-2013
A
Ans. (b) : The stability of a linear closed loop system 18 =
can be determined from the locations of closed-loop 1 − 0.5A
poles in the s-plane. 18 − 9A = A
If all the roots of the characteristics equation lie on the A = 18 A = 1.8
left half of the ‘s’ plane, i.e., if all the roots have 10
negative real parts, then the system is said to be a stable 32. Which of the following can be magnified by
system. magnetic amplifiers
28. An amplifier without feedback has a voltage (a) Voltage (b) Current
gain 50 and input resistance of 1 kΩ. The input (c) Power (d) None of the above
resistance of the current-shunt negative UJVNL AE-2016
feedback amplifier using the above amplifier
Ans. (c) : A magnetic amplifier can amplify the power.
with a feedback factor of 0.2 is Magnetic amplifiers are used to amplify electrical
(a) 1/11 kΩ (b) 1/5 kΩ signals, it can either be voltage or current amplifier, in
(c) 5 kΩ (d) 11 kΩ both cases actually power is increasing P = V ⋅ I
Punjab PSC Poly. Lect.-20.08.2017 33. The noise in a negative feedback amplifier
GPSC Asstt. Prof. 11.04.2017 (a) Increases
Ans. (a) : Input Resistance with feedback for current (b) Decreases
shunt (c) First increases and then decreases
' Ri (d) First decreases and then increases
Ri =
1 + βA TNPSC AE-2014
R i = 1kΩ β = 50 A = 0.2 Ans. (b) : The numerous advantage of negative
feedback–
1 1
R 'i = = (1) higher fidelity i.e. more linear operation.
1 + 10 11 (2) highly stabilized gain.
29. Required bandwidth of wideband amplifier to (3) increased bandwidth i.e. improved frequency
reproduce a pulse faithfully, depends upon response.
.............. of the pulse (4) Reduced noise.
(a) width (b) rise time (5) Less harmonic distortion.
(c) fall time (d) frequency 34. Three identical single tuned amplifiers are
Mizoram PSC AE/SDO-2012 Paper-III connected in cascade. The 3 dB bandwidth of
Ans. (b) : Required bandwidth of wideband amplifier to each amplifier is 100 kHz. The overall 3 dB
reproduce a pulse faithfully, depends upon Rise time of bandwidth will be approximately.
the pulse. (a) 300 kHz (b) 100 kHz
30. By increasing the number of identical stages in (c) 50 kHz (d) 33 kHz
an amplifier, the gain bandwidth product TNPSC AE-2013
Ans. (c) : n = 3, fH = 100 kHz 39. In high frequency region, an amplifier
behavior like a
'
H f = fH 2 − 1
13
(a) Band pass filter
f H = 100 2 − 1
' 1/ 3
= 100 1.25 − 1 (b) Low pass filter
(c) High pass filter
f H' = 100 × 0.25 (d) Any of the above
f H' = 50kHz Nagaland PSC CTSE (Degree)-2016, Paper-II
Ans. (b) : In high frequency region an amplifier behave
35. An amplifier has gain of 20 without feedback. like low-pass filter.
If 10% of the output voltage is feedback by
means of a resistance negative feedback circuit, A
the overall gain would be 40. For feedback amplifier with gain
1− T
(a) 16.55 (b) 19.8 feedback reduces the internally generated noise
(c) 10.85 (d) 6.67 by a factor
TNPSC AE-2013 (a) T (b) (1 – T)
Ans. (d) : New gain with negative feedback
1 1
Av 20 (c) (d)
Av =
'
=
1 + A vβf 1 + 20 × 1
T (1 − T )
10 Nagaland PSC CTSE (Degree)-2016, Paper-II
20 Nagaland PSC CTSE- 2015, Paper-II
A 'v = Ans. (b) : Noise reduced by factor of (1-T) in case of
3
Negative feedback amplifier.
A 'v = 6.67 41. One of the following types of distortions is not
36. One of effect of negative feedback in amplifier objectionable in audio amplifiers
is to (a) Harmonic distortion
(a) Decrease the harmonic distortion (b) Intermediations distortion
(b) Increase the harmonic distortion (c) Frequency distortion
(c) Decrease the bandwidth (d) Phase distortion
(d) Increase the noise Nagaland PSC CTSE (Diploma)-2018, Paper-I
MPPSC Forest Service Exam.-2014 Ans. (d) : Phase distortion has least effect on audio
GATE-1993 amplifiers. It is also known as delay distortion.
Ans. (a) : Negative feedback reduces gain of the 42. Negative feedback in an amplifier results in
amplifier. It also reduces the distortion, noise and (a) More gain, more bandwidth
instability. But increase bandwidth and improve input (b) More gain, less bandwidth
impedance.
(c) Less gain, more bandwidth
37. An amplifier without feedback has a gain of (d) Less gain, less bandwidth
1000. The gain with negative feedback of 0.009
will be
(a) 125 (b) 10 Nagaland PSC CTSE (Diploma)-2018, Paper-I, II
(c) 900 (d) 100 GATE-1999
MPPSC Forest Service Exam.-2014 Ans. (c) : In negative feedback, the feedback energy is
out of phase with input signal. Negative feedback
Ans. (d) : A = 1000 β = 0.009 reduce gain of the amplifier. It also reduce distortion,
A 1000 noise. This feedback increase bandwidth and improve
AF = ⇒ AF =
1 + Aβ 1 + 0.009 × 1000 input impedances and Output impedances decreases.
1000 43. In a push pull circuit
AF = (a) each transistor conducts for 180º
10
A F = 100 (b) each transistor conducts for more than 180º
but less than 360º
38. The unity gain bandwidth of an inverting (c) each transistor conducts for less than 180º
amplifier is 10 MHz What would be the (d) the period of conduction of each transistor
bandwidth if the gain is increased to 10V/V? depends on circuit configuration
(a) 100 MHz (b) 1 MHz Mizoram PSC Jr. Grade-2015, Paper-II
(c) 10 MHz (d) 1 kHz
Ans. (a) : In push pull circuit each transistor conducts
RPSC LECTURER-10.01.2016 for 180º. So that complete conduction for 360º occurs.
Ans. (b) : Gain × bandwidth = Constant Hence minimum distortion and maximum efficiency.
So, G1×(BW)1 = G2×(BW)2 44. What is the percentage reduction in gain of an
1×10×106 = 10×B2 amplifier due to introduction of 20 dB of
B2 = 1MHz negative feedback?
(a) 100% (b) 50% Ad 133.3
(c) 90% (d) 70% Af = =
1 + A dβ 1 + 133.3 × 0.03
Mizoram PSC Jr. Grade -2018, Paper-II
Af = 26.7
Ans. (c) : Given,
gain = 20dB 47. A negative feedback of β = 2.5 × 10-3 is applied
20 log Af = 20 to an amplifier of open-loop gain 1090. What is
the change in overall gain of the feedback
A f = 10 amplifier, if the gain of the internal amplifier is
So it will be reduced 90% reduced by 20% ?
(a) 295.7 (b) 286.7
45. The circuit shown in the figure below is an (c) 275.7 (d) 266.7
example of feedback of which of the following
types? IES - 2015
Ans. (c) : Given,
Open loop gain, A= 1090
Feedback factor, β = 2.5 ×10 −3 = 0.0025
A
A f1 =
1 + Aβ
1090
=
(a) Voltage series (b) Voltage shunt 1 + 1090 × 0.0025
(c) Current series (d) Current shunt A f1 = 292.617
BPSC Polytechnic Lecturer-2014 After 20% reduction
Ans. (b) : 80
A 2 = 1090 ×
100
= 1090 × 0.8
A2 = 872
A2
A f2 =
1 + A 2β
872
=
The circuit shown in the figure below is an example of 1 + 872 × 0.0025
feedback Voltage shunt. A f2 = 274.2
46. An amplifier, without feedback, has a gain A.
The distortion at full output is 10%. The A f2 ≃ 275.7
distortion is reduced to 2% with negative
48. An amplifier with mid band gain A = 500 has
feedback (feedback factor β = 0.03). The values
negative feedback β = 1/100. If upper cut-off
of A and A' (i.e. the gain with feedback) are,
without feedback were at 60 kHz, then with
respectively, nearly feedback it would become
(a) 133.3 and 18.5 (b) 133.3 and 26.7 (a) 10 kHz (b) 360 kHz
(c) 201.3 and 26.7 (d) 201.3 and 18.5 (c) 12 kHz (d) 300 kHz
IES - 2018 KVS TGT (WE)- 2014, IES - 2014
KVS TGT (WE)- 2016
Ans. (b) : Given,
Ans. (b) : Given, Mid band gain |A| = 500
distortion of basic amplifier Ad = 10% 1
Feedback Adf = 2% Feedback gain |β| =
100
β = 0.03 Without feedback upper cut-off frequency f = 60 kHz
u
∵ A df =
Ad Upper cut-off frequency after feedback = f u (1+ | Aβ |)
1 + A dβ
 500 
= 60 ×103 1 + 
10%  100 
2% =
1 + A d × 0.03 = 60 × 10 × 6
3
1 + 0.03A d = 5 = 360 kHz

49. The second harmonic component in the output
4
⇒ Ad = of a transistor amplifier, without feedback is
0.03 B2. The second harmonic component with
Ad = 133.3 negative feedback B'2 is equal to (where A =
∴ Negative feedback, gain reduced by ( 1+ Aβ), Amplifier gain and β = feedback factor).

B2 Ans. (b) :
(a) (b) B2 (1 + Aβ)
1 + Aβ
B2 B2
(c) (d)
β Aβ
IES - 2012
Ans. (a) : Given,
The second harmonic component in the output without
feedback, = B'2
Harmonic with feedback = B2
feedback factor = β
B2 RF is the element responsible for feedback and it is
B'2 = directly connected to the output node, so voltage
1 ± Aβ
sampling is done and it is also directly connected to the
The value of second harmonic component in output of input node, so shunt mixing is there. Hence, the
transistor with feedback is feedback is voltage shunt.
52. The given circuit represents the amplifier type
B2
B'2 = (for negative feedback) as :
1 + Aβ
50. In a transconductance amplifier, the device
output
(a) voltage depends upon the input voltage.
(b) voltage depends upon the input current.
(c) current depends upon the input voltage.
(d) current depends upon the input current. (a)
voltage-series feedback
IES - 2012 (b)
voltage-shunt feedback
(c)
current-series feedback
Ans. (c) : In a transconductance amplifier, the device (d)
current-shunt feedback
output current depends upon the input voltage. APPSC Poly. Lect. 15.03.2020
Iout Ans. (b) : From output, we take V0 as feedback which it
Transconductance = A V
Vin makes shunt at input. Hence it is voltage shunt
feedback.
51. The amplifier circuit shown in the figure is an
53. 1 dB corresponds to ________ change in power
example of level.
(a) 35% (b) 26%
(c) 50% (d) 14%
RRB JE- 31.08.2019, 10 AM-12 PM
Ans. (b) : Given that dB = 1
P
dB = 10log 0
P1
P0
1 = 10log10
P1
1 P
= log10 0
10 P1
Antilog–
(a) voltage series feedback
P0
(b) voltage shunt feedback Anti log [ 0.1] =
P1
(c) current series feedback
P0
(d) current shunt feedback 1.259 =
P1
IES - 2011
P0 = 1.1 MHz
1.26 = Lower cut-off frequency with feedback-
P1
fℓ
P0= 1.26P1 fL =
Change in power level, (1 + Aβ )
∆P P0 − P1 1.26P1 − P1 1×103
% = × 100 = × 100 =
P P0 P1 1 + −100 ( 0.1) 
(1.26 − 1) P1 1000
= × 100 = 26% = Hz
P1 11
54. A feedback amplifier has an open loop gain of - Feedback = 20 logβ
100. If 4% of the output is fed back in a = 20 log(0.1)
degenerative loop, what is the closed loop gain = –20
of the amplifier ?
(a) – 33.3 (b) – 25 56. An amplifier has an open loop gain of 1000±10.
(c) – 20 (d) + 20 Negative feedback is provided such that the
IES - 2008 gain variation remains within 0.1%. What is
Ans. (c) : Given, the amount of feedback βF ?
Open loop gain, A = –100 (a) 1/10 (b) 1/9
Feedback factor, β = –4% = –0.04 (c) 9/100 (d) 9/1000
A IES - 2006
Closed loop gain, A f = Ans. (d) : Given, A = 1000
1 + Aβ
∂A 10
−100 =
= A 1000
1 + ( −100 )( −0.04 )
∂A F
−100 = 0.1%
Af = AF
5
∂A F 1 ∂A
A f = −20 = .
A F 1 + Aβf A
55. An amplifier has gain A = 100∠180º, upper
0.1 1 10
cut-off frequency of 100 kHz and lower cut off = ×
frequency of 1 kHz. A negative feedback of 100 1 + 1000βf 1000
β=0.1 is added. Which one of the following is 1 1 1
not correct ? = ×
(a) Gain becomes 100/11 1000 1 + 1000 β f 100
(b) Lower cut off frequency becomes (1000/11) 1 + 1000βf = 10
kHz
(c) Upper cut off frequency becomes 1.1 MHz 9
βf =
(d) dB of feedback is 20log10 11 1000
IES - 2008 57. A negative feedback is applied to an amplifier
Ans. (d) : Given, with the feedback voltage proportional to the
Gain, A = –100 output current. This feedback increase the
fu = 100 kHz, f L = 1 kHz (a) input impedance of the amplifier
Feedback factor (β) = 0.1 (b) output impedance of the amplifier
A (c) distortion in the amplifier
Closed loop gain, (A f ) = (d) gain of the amplifier
1 + Aβ
DRDO-2008
−100
= Ans. (a) : In voltage series feedback the input of the
1 + ( −100 )( 0.1) system is series connected with the feedback loop
−100 therefore the input impedance will be increased.
Af = 58. The voltage gain of an amplifier without
11
feedback and with negative feedback
Upper cut-off frequency with feedback-
respectively are 100 and 20. The percentage of
f U' = f u (1 + Aβ ) negative feedback (β) would be
= 100 ×10 1 + ( −100 ) × ( 0.1) 
3 (a) 4% (b) 5%
(c) 20% (d) 80%
= 100 × 103 × 11 IES - 2002
Ans. (a) : Given, gm
g mf =
Gain without feedback, A =100 D
Gain with feedback, Af = 20 g m = −50mA / V
A For degenerative feedback
Af =
1 + Aβ D = 1 + βg m
20 =
100 50 = 1 + β× ( −50 ×10−3 )
1 + 100β
49
1 + 100β = 5 β=
−50 × 10−3
100β = 4
β = −0.98
4
β=
100 Feedback voltage R E IC
β= =
4 output voltage VO
β% = ×100 = 4%
100 −0.98
RE = = 0.98kΩ
β = 4% −1mA / V
61. The given circuit has a feedback factor of
59. The feedback amplifier shown in the figure
below :
(a) is stable for all values of R and C

(b) is stable only for R1R2 = R3 (a) -RC/RS (b) -RE/RC
(c) is stable only for R1C = R1R3 (c) -RE/RS (d) -RC/RE
(d) is stable is R1/R2 = C / R3 IES - 1999
IES - 2002 Ans. (b) :
Ans. (a) :
In given diagram voltage gain is negative. Negative

feedback tends to maintain a constant value of amplifier Given,
voltage gain against variations in transistor parameter. Output Collector Resistance, = RC
So stability increases as gain reduces hence it is stable Emitter resistance or feedback resistance = RE
for all values of R and C. Current series feedback configuration has given in
60. If a common emitter amplifier with an emitter above circuit -
resistance Re has an overall trans-conductance Output voltage, V0 = R C IC
gain of - 1 mA/V, a voltage gain of -4 and
desensitivity of 50, then the value of the emitter Feedback voltage, Vf = R E IC
resistance Re would be : Vf
Then, Feedback factor, β =
(a) 50Ω (b) 0.98kΩ V0
(c) 50kΩ (d) 0.98Ω
R E IC
IES - 2000 =
−R C IC
Ans. (b) : Given, D = 50
Basic amplifier is trans-conductance amplifier −R E
β=
A = g mf = −1mA / V RC

62. It is desired to reduce total harmonic distortion B. CE = 0, 2. Current series negative
of an amplifier from 8% to 2% by use of 5% R f1 = ∞ , feedback
feedback. What is the gain of the amplifier with
original distortion and with reduced R f2 = ∞ and
distortion? output is taken
(a) 60, 15 (b) 15, 90 from collector
(c) 6, 1.5 (d) 1.5, 6 point.
IES - 1995 C. R f2 = ∞ and 3. Voltage shunt negative
Ans. (a) : Given, feedback
output is taken
8 from collector
Initial distortion, D1 = 8% =
100 point.
2 D. CE = 0, 4. Current shunt positive
Final distortion, D2 = 2% = R f1 = ∞ and feedback
100
Feedback factor, β = 5% = 0.05 output is taken
D1 from collector
D2 = point.
1 + Aβ
Codes:
2 8 100
= A B C D
100 1 + A × 0.05 (a) 1 3 4 2
1 1 (b) 2 3 4 1
=
4 1 + 0.05A (c) 3 2 1 4
1 + 0.05A = 4 (d) 4 3 2 1
0.05A = 3 IES -1993
Ans. (b) : Given,
A = 60
Gain with feedback,
A
Closed loop gain, A f =
1 + Aβ
60
Af =
1 + 60 × ( 0.05)
60
Af =
3 +1
A f = 15
63. The given feedback amplifier circuit is List-I List-II
modified according to List-I and the possible 1. RC = 0, CE = 0, Voltage series negative
feedback is as per List-II. Match the two lists
and select the correct answer using the codes R f1 = ∞ , R f2 = ∞ feedback
given below the lists : and output is
taken from
emitter point.
2. CE = 0, R f1 = ∞ , Current series negative
feedback
R f2 = ∞ and
output is taken
from collector
point.
3. R f2 = ∞ and Voltage shunt negative
feedback
List-I List-II output is taken
A. 1. Voltage series negative from collector
RC = 0, CE = 0,
point.
R f1 = ∞ , feedback
4. CE = 0, Current shunt positive
R f2 = ∞ and R f1 = ∞ and feedback
output is taken output is taken
from emitter from collector
point. point.
64. In the circuit shown in the given figure, RF Ans. (a, c) : Given,
provides First gain = A = 1
Other gain = 20
We know that
Gain × Bandwidth = Constant
G × B.W. = Constant
Gain, (A) = 1
G × B.W1 = Constant
1 × B.W1 = Constant _________ (1)
Gain, A = 20
20 × B.W2 = Constant ________ (2)
eq.n (1) = eq.n (2)
1 × B.W1 = 20 × B.W2
(a) Current series feedback B.W1
(b) Current shunt feedback B.W2 =
20
(c) Voltage series feedback
(d) Voltage shunt feedback As compared to the unity gain amplifier, the amplifier
IES - 1991 with gain twenty has less bandwidth and less negative
feedback.
Ans. (d) :
67. Consider the following:
I. Oscillator
II. Emitter follower
III. Cascaded amplifier
IV. Power amplifer
Which of the following use feedback
amplifiers?
(a) I and II (b) I and III
(c) II and IV (d) III and IV
Rf is the element responsible for feedback and it is
directly connected to the output node, so voltage
sampling is done and it is also directly connected to the Ans. (a) : Oscillator and emitter follower circuit are
input node, so shunt mixing is there. Hence, the positive and negative feedback amplifiers.
feedback is voltage shunt. 68. Which type of negative feedback is used to
65. A two stage amplifier with negative feedback improve performance of current amplifier?
(a) Becomes unstable at very high and very low (a) Current shunt feedback
frequencies if A is very large (b) Voltage shunt feedback
(b) Can become unstable for larger values of β (c) Current series feedback
(c) Becomes unstable when the pole frequencies (d) Voltage series feedback
become complex MPSC HOD Govt. Poly. -2013
(d) Is always stable Ans. (a) : In current-shunt feedback, as the feedback
Nagaland PSC CTSE (Degree)-2016, Paper-II circuit is connected in series with the output, the output
Ans. (d) : Negative feedback amplifier subtracts a impedance is increased and due to parallel connection
fraction of its output to it’s input so that negative with the input, the input impedance decrease. So
feedback opposes the original signal. performance will be improved.
The applied negative feedback improves its’ 69. The feedback scheme used in a simple op-amp
performance namely gain stability, linearity, frequency based non-inverting amplifier is :
response, step response and reduce sensitivity to (a) series-series (b) series-shunt
parameter variations. Hence a two stage amplifier with (c) shunt-series (d) shunt- shunt
negative feedback is always stable. DRDO-2009
66. Two non-inverting amplifiers, one having a Ans. (c) : Shunt series feedback scheme used in a
unity gain and the other having a gain of simple op-amp based non-inverting amplifier.
twenty, are made using identical operational
amplifiers. As compared to the unity gain 70. Consider the following statements for negative
amplifier, the amplifier with gain twenty has feedback:
(a) Less negative feedback 1. It has more linear operation.
(b) Greater input impedance 2. It has improved frequency response.
(c) Less bandwidth 3. It has better stabilized voltage gain.
(d) None of the above 4. It has higher output impedence.
GATE-1991 Which of the above statements are correct?
(a) 1 and 2 only (b) 2 and 3 only 73. A system has 3-stage cascaded amplifier, each
(c) 1, 2 and 3 only (d) 2, 3 and 4 only stage having a power gain of 10dB and noise
ESE-2021 figure of 6 dB. The overall noise figure is
Ans.(c) : Advantage of negative feedback of op- (a) 1.38 (b) 6.8
amp- (c) 4.33 (d) 10.43.
(1) It has more linear operation. TRB Poly. Lect. -2012
(2) It has improved frequency response. Ans. (c) : Overall noise figure of cascaded device is
(3) It has better stabilized voltage gain. F − 1 F3 − 1 F −1
(4) It has reduced noise. Fn = F1 + 2 + + ...... + n
G1 G1G 2 G1G 2 .....
(5) It has less distortion.
So option (c) is the correct. Given;
71. Which one of the following statements is Gain = 10dB and noise figure F = 6dB
correct regarding shunt-series feedback 6 = 10log ( F )
amplifier topology? F = 100.6
(a) The currents are compared and the output
F = 3.98
voltages are sampled.
(b) The currents are compared and the output So, overall noise figure = 3.98 + 3.98 − 1 + 3.98 − 1
currents are sampled. 10 100
(c) The voltages are compared and the output 2.98 2.98
currents are sampled. = 3.98 + +
10 100
(d) The voltages are compared and the output = 3.98 + 0.298 + 0.0298
voltages are sampled.
= 4.3078
ESE-2021
4.33
Ans.(b) : For shunt series feedback amplifier topology
the currents are compared and the output currents are 74. In a trans-conductance amplifier, it is desirable
sampled. to have
(a) A large input resistance and a large output
72. An amplifier without feedback has a voltage
resistance
gain of 50, input resistance of 1 kΩ and output
resistance of 2.5 kΩ. The input resistance of the (b) A large input resistance and a small output
current-shunt negative feedback amplifier (c) A small input resistance and a large output
using the above amplifier with a feedback resistance
factor of 0.2 is (d) A small input resistance and a small output
(a) 1/11 kΩ (b) 1/5 kΩ resistance
(c) 5 kΩ (d) 11 kΩ Nagaland PSC (Degree) 2018, Paper-II
Punjab PSC Poly. Lect.-20.08.2017 GATE-2017, 2014, 2007, 2006
GATE-2003 Ans. (a) : In a trans-conductance amplifier, it is
Ans. (a) : Given, desirable to have a large input resistance and a large
Gain, A = 50 output resistance. It is also known as current-series
Feedback factor, β = 0.2 feedback. For ideal trans-conductance input impedance
and output impedance are infinite.
Input Resistance, Ri = 1 kΩ
Output Resistance, Ro = 2.5 kΩ 75. In the ac equivalent circuit shown in the figure,
For current shunt negative feedback amplifier input if iin is the input current and RF is very large,
1 the type of feedback is
resistance decrease with and output increase
(1 + Aβ )
with (1 + Aβ).
So, input resistance with negative feedback
Ri
R if =
(1 + Aβ )
1× 103
=
1 + 50 × 0.2
(a) Voltage-voltage feedback
1× 103
R if = (b) Voltage-current feedback
11
(c) Current-voltage feedback
1 (d) Current-current feedback
R if = kΩ
11 GATE-2014, Set-I
Ans. (b) : Ans. (d) : A good transimpedance amplifier has low
input impedance and low output impedance. It is also
known as voltage shunt feedback. In voltage-shunt
feedback amplifier input impedance and output
impedances are decreased.
78. In with a negative feedback, the system gain
and stability respectively
(a) Decreases, Increases
(b) Increases, Decreases
(c) Decreases, Decreases
Voltage current feedback is in the above figure. (d) Increases, Increases
In the given figure sampling of current and mixing of RPSC VP/Suptd. ITI 05.11.2019
voltage. Ans. (a) : With a negative feedback, the system gain
76. The feedback topology in the amplifier circuit decreases and stability increases respectively. Negative
(the base bias circuit is not shown for feedback in a control system reduces the overall gain
simplicity) in the figure is and increases stability. It reduces the sensitivity of
output to input variation, distortion and noise reduction.
79. An amplifier has gain of 800. After adding
negative feedback, the gain is measured as 25.
The feedback factor is
(a) 25 (b) 0.0412
(c) 0.0388 (d) 0.01
Punjab PSC Poly. Lect. 20.08.2017
Ans. (c) : A (open loop gain) = 800
Av (feedback gain) = 25
(a) Voltage shunt feedback β (feedback factor)
(b) Current series feedback A
(c) Current shunt feedback Av =
1 + Aβ
(d) Voltage series feedback
800
UPPSC ITI Principal Asstt. Director-09.01.2022 25 =
GATE-2014, Set-II 1 + β(800)
Ans. (b) : 25 + 25 × 800β = 800
775
β=
25× 800
β = 0.0388
80. Roll-off factor is defined as
(a) The bandwidth occupied beyond the Nyquist
Bandwidth of the filter
(b) The performance of the filter or device
(c) Aliasing effect
In given circuit it is a current series feedback. In
current-series feedback, input and output impedance are Nagaland PSC- 2018, Diploma Paper-II
high, and infinite for ideal. In a current series feedback, Ans. (a) : Roll off Factor- Roll off factor is a measure
current is sampled from the output and voltage is of the excess bandwidth of filter. For Roll off factor of
feedback to the source. zero of an ideal rectangular nyquist pulse is obtained
77. A good transimpedance amplifier has this is called as nyquist minimum band width case.
(a) Low input impedance and high output 81. When positive feedback amplifiers are used as
impedance oscillators, the condition Aβ=1 is known as
(b) High input impedance and high output (a) Barkhausen criterion of oscillation
impedance (b) Pakinson criterion of oscillation
(c) High input impedance and low output (c) Positive criterion of oscillation
impedance (d) None of the above
(d) Low input impedance and low output KVS TGT (WE)- 2016
impedance Nagaland PSC CTSE- 2015, Paper-II
GATE-2018 KVS TGT (WE)- 2014
Ans. (a) : An oscillator is naming but an amplifier with Ans. (d) : Darlington pair : CC-CC :-
positive feedback is given by Af = A/1–Aβ
If Aβ = 1 then it becomes infinite and this implies that
amplifier is capable of producing an output even when
no input is applied.
This is called Barkhausen criterion for oscillation.
(a) Reducing distortion
(b) Power amplification
(c) Wideband voltage amplification
(d) Impedance matching
Ans. (d) :
A Darlington pair consists of two npn transistors the
emitter current of Q1 is the base current of Q2 and
collector terminal is common of both transistor.
85. The configuration of the given figure is a
In Darlington pair the output of the first amplifier is

connected to the input of the second amplifier collector
of both transistor is common in this circuit.
The Darlington pair provide high input impedance and
low output impedance so it is used for impedance
matching.
83. Negative voltage feedback in amplifiers (a) Precision integrator
S1: Improves gain stability (b) Hartley oscillator
S2: Reduces non linear distortion (c) Butterworth high pass filter
S3: Improves frequency response (d) Wien bridge oscillator
S4: Increase circuit stability ISRO Scientist- May, 2017
S5: Increase Input Impedance and decrease output Ans. (d) :
impedance
(a) Only S1 and S2 are correct
(b) Only S2 and S4 are correct
(c) Only S3 and S5 are correct
(d) All except S3 are correct
(e) All are correct
BEL-2015
CGPSC SO 14.02.2016
Ans. (e) : Negative voltage feedback in amplifiers
1- Improves gain stability
2- Reduces non linear distortion
3- Improves frequency response Given figure is Wien bridge oscillator, it can generate a
4- Increase circuit stability large range of frequencies.
5- Increase Input Impedance and decrease output 86. Decibel scale is useful while measuring voltage
impedance conversing
84. In darlington pair connection we are (a) Wider frequency ratio
connecting _____. (b) Wide voltage ratio
(a) CB-CC (b) CC-CE (c) Narrow frequency range
(c) CE-CB (d) CC-CC (d) Narrow voltage range
AAI-2015 RRB SSE 01.09.2015 Shit-I
Ans. (a) : A decibel scale is used for measuring voltage Ans. (c) : Loop gain |Aβ| = 1
covering the wider frequency ratio, decibel scale widely 2. Total phase shift should be 360º or 0º
used in electronics, communication and signals. 2. What is the value of capacitor of the Wien
87. Half power frequency represent below gain of bridge oscillator operating at resonant
(a) 0dB (b) 3dB frequency of 10 kHz with resistance of 100
(c) 2dB (d) 1dB kΩ ?
BEL-2015 (a) 149 pF (b) 159 pF
Ans. (b) : Gain of half power frequency (c) 169 pF (d) 189 pF
Input power = Pi ESE-2021
Ans.(b) : The frequency of oscillation-
Output power = P0
1
For half power frequency Pi = P0 2 ω0 =
RC
Power gain = 10log ( P0 Pi ) 1
f0 =
2πRC
 P  Given that, R = 100KΩ
= 10log  0 
 P0 2  f 0 = 10KHz
2 f0 =
1
= 10log  
1 2 π RC
= 3.010 1
C=
Power gain = 3dB 2π× 100 × 103 × 10 × 103
C = 159.155 × 10−12
88. The negative feedback in an amplifier leads to C = 159pF
which one of the following?
(a) Increase in current gain 3. What do phase-shift oscillators, twin-T
(b) Increase in voltage gain oscillators, and Wien bridge oscillators have in
(c) Decrease in voltage gain common?
(d) Decrease in bandwidth (i) They use RC frequency control
RRB SSE 01.09.2015, Shift-II (ii) They have a sinusoidal output
Ans. (c) : The feedback amplification factor (iii) They use amplifier gain to overcome
feedback loss
A
Af = (a) (i), (ii) and (iii) (b) (i) and (ii)
1 + Aβ (c) (i) and (iii) (d) (ii) and (iii)
Where A – open-loop gain NLC GET -24.11.2020
Aβ – loop gain Ans. (a) : The common characteristic among phase shift
As feedback increases the gain decreases (voltage gain) oscillators, twin-T oscillators and Wien bridge
thereby bandwidth increases. oscillators have are -
Effect of Negative feedback in amplifiers– They have a Audio frequency oscillator
They use RC frequency control and they use amplifier
1. reduces the gain and increases the stability in gain.
gain to overcome feedback loss.
2. increases the bandwidth to maintain the constant gain Twin-T oscillator (also known as a parallel-T
bandwidth product. oscillator) uses two interconnected resistive capacitive
3. reduces the distortion and noise in the amplifier. (RC) network together in parallel.
4. does not affect the signal to noise ratio. 4. Which of the following statements is not true?
(a) All oscillators satisfy the Barkhausen
(vii) Oscillator criterion
(b) An oscillator is an amplifier that supplies its
own input signal
1. The basic conditions for generating sinusoidal
(c) An oscillator is a circuit that converts dc to ac
voltage in a feedback oscillator is (are)
(d) In-phase feedback is called positive feedback
(a) Total loop gain should be 1
NLC GET -24.11.2020
(b) Total phase shift should be 360º
Ans. (a) : The oscillator is an electronic device that
(c) Both (a) and (b)
produces the output wave form periodically without any
(d) None of these
input. An oscillator is an amplifier that supplies its own
UPRVUNL AE-19.07. 2021, Shift-II input signal and by converting unidirectional current
TNPSE AE-2019 flow into an alternating wave form with a specified
Nagaland PSC-2018, Diploma, Paper-II frequency oscillators convert the DC current flow to an
Nagaland PSC (Degree) 2018, Paper-II alternating current flow.

Practically oscillators are amplifier circuit that have Ans. (d) : Wien bridge oscillator –
positive or regenerative feedback where the portion of
the output is feedback to the input side.
In general oscillators follow Barkhausen criteria for
stabilized oscillations but not all oscillators.
5. A Colpitts Oscillator is having tank
capacitances of 1nF and 10 nF, and inductance
of 0.1 µH. The gain required by the circuit to
start oscillating is:
(a) 10 (b) 100
(c) 1 (d) 1000 1
ISRO Scientist Engg.-2014 f=
2πRC
Ans. (a) : Given,
Commonly used as audio frequency oscillator.
C1 = 1nF
Precision measurement of capacitance in terms of
C2 = 10 nF
resistance and frequency.
L = 0.1µH Audio frequency range- 20 Hz to 20 kHz
The gain required by the circuit to start oscillating is:-
This oscillator is free from the circuit fluctuations
C and the ambient temperature.
| Ar | ≥ 2
C1 Provides constant output.
10nF Frequency of oscillations can be changed easily.
| Ar | ≥ Good frequency stability.
1nF
= 10 9. The basic amplifier in Wien bridge oscillator
6. Oscillator requires consists of
(a) No feedback (a) CE stage followed by CC
(b) Negative feedback (b) CC stage followed by CE
(c) Positive feedback (c) CB stage followed by CE
(d) Either positive or negative feedback (d) CE stage followed by CB
Nagaland PSC (CTSE) Diploma-2017, Paper II Nagaland PSC (CTSE) Diploma-2017, Paper II
Mizoram PSC Jr. Grade-2015, Paper-II Ans. (a) : The basic amplifier in Wien bridge oscillator
TNPSC AE-2014 consist of common emitter stage amplifier followed by
Mizoram PSC AE/SDO 2012-Paper-I common collector. A Wien's bridge is a type of
ISRO Scientist Engg.-2006 electronic circuit that generate sine wave.
Ans. (c) : Oscillator requires positive feedback. 10. ……….oscillator uses a tapped coil in the LC
tuned circuit
A
+ve feedback closed loop gain = A CL = (a) Hartley (b) Armstrong
1 − βA (c) Colpitts (d) Pierce
βA = 1 is maintained to satisfy Barkhausen criteria Nagaland PSC (CTSE) Diploma-2017, Paper II
due to which high gain can be obtained which produces- Ans. (a) : Hartley oscillator uses a tapped coil in LC
oscillation in the system. tuned circuit. The Hartley oscillator is after referred to
7. The oscillator with the best frequency stability as a self-inductance oscillator because coil L is centre
and accuracy is tapped.
(a) Hartley oscillator
11. If L1 = 1 mH, L2 = 2 mH and C = 0.1 nF in
(b) Colpitts Oscillator
Hartley oscillator, then f =_____ kHz.
(c) Tickler feedback oscillator
(d) Crystal controlled oscillator (a) 45.88 (b) 290.57
Nagaland PSC (CTSE) Degree -2018, Paper II (c) 145.57 (d) 572.25
Nagaland PSC (CTSE) Diploma-2017, Paper II UPRVUNL AE -19.07.2021, Shift-II
ISRO Scientist Engg.-2007, IES-1998 TSTRANSCO AE- 2018
Ans. (d) : The oscillator with the best frequency Ans. (b) : The frequency of the Hartley oscillator is
stability and accuracy is crystal controlled oscillator. 1
Crystal oscillator parameters doesn't change with given by f = LT = L1 + L2
temperature, the output frequency is highly stable. 2π L T C
8. A Wien bridge oscillator is a 1
(a) Microwave =
2 π 3 × 10 × 0.1 × 10 −9
−3
(b) RF oscillator
(c) VHF oscillator 1
= = 290575.84Hz
(d) Audio frequency oscillator 2π 0.3 × 10 −12
Nagaland PSC (CTSE) Diploma-2017, Paper II = 290.57 kHz.
12. If C1 = 200 pF, C2 = 50 pF in Colpitts oscillator 14. Colpitts and Hartley oscillators belong to a
and frequency is 1 MHz, then what is the value general class of oscillation that ______
of inductance required? feedback.
(a) 1.25 mH (b) 0.6332 mH (a) Voltage-series (b) Current-series
(c) 0.782 mH (d) 0.432 mH (c) Voltage-shunt (d) Current-shunt
UPRVUNL AE -19.07.2021, Shift-II TNPSC AE - 2018
Ans. (b) : Frequency in Colpitts oscillator, Ans. (a) : Colpitts and Hartley oscillator belongs to
general class of oscillation that voltage series feedback.
1
f= The main difference between colpitts and Hartley
2π CT L oscillator is former uses tapped capacitance while the
latter uses tapped inductance.
C1C 2
CT = 15. For the oscillator circuit given, expression for
C1 + C 2 the time period oscillator can be given by
200 ×10−12 × 50 ×10−12
CT =
( 200 + 50 )10−12
10,000 ×10−24
CT =
250 ×10−12
CT = 40 × 10−12
1
f=
2 π CT L (a) τln 3 (b) 2τln 3
(c) τln 2 (d) 2τln 2
1
L= TNPSC AE - 2018
( 2πf )
2
CT Ans. (b) :
1
L=
( 2 × 3.14 ×1×10 ) 6 2
× 40 × 10−12
L = 0.6332mH
13. Colpitts oscillator designed with an inductor L
produces frequency f. If it has to produce
frequency 2f, then the new inductance is
________.
(a) L/2 (b) L/4
(c) 2L (d) 4L
UPRVUNL AE -19.07.2021, Shift-II Time period of oscillator
KVS TGT (WE)- 2017  R + R2 + R3 
Ans. (b) : Output frequency of colpitts oscillator, T = ( R 2 + R 3 ) Cln  1 
 R1 
Where, ( R1 = R 2 = R 3 = R )
τ = RC
T = 2RC ln 3
T = 2τln3
16. The phase shift oscillator requires
(a) 180º phase shift from RC network
(b) 360º phase shift from RC network
(c) 0º phase shift from RC network
1 (d) 90º phase shift from RC network
f= KVS TGT (WE)- 2018
2π LCT GPSC Asstt. Prof. 11.04.2017
C1C2 1 KVS TGT (WE)- 2016
CT = , L=
C1 + C2 ( ) CT
2
2 πf Ans. (a) : A phase shift oscillator is a linear electronic
oscillator circuit that produce a sine wave output. A
L phase shift requires 180° phase shift from RC network.
For L' = the frequency become 2f.
4 17. Colpitts oscillator circuit uses
(a) Two capacitors and one inductor C.C0
(b) Two inductors and one capacitor where Ceq =
C + C0
(c) One inductors and one capacitor
(d) Three inductors 1
• Series resonance frequency f(s) =
GPSC Asstt. Prof. 11.04.2017 2π L C
Ans. (a) : A colpitts oscillator is a type of LC oscillator, 19. An oscillator that consists of two
and it generates sinusoidal output signals with very high interdependent circuit such that output of each
frequency. Colpitts oscillator circuit uses two capacitors controls the input of the other is called a
and one inductor.
(a) sine wave oscillator
(b) feedback oscillator
(c) relaxation oscillator
(d) −ve resistance oscillator
Ans. (c) : An oscillator that consist of two inter-
dependent circuit such that output of each controls the
input of the other is called a relaxation oscillator.
• A Relaxation oscillator is basically a non-linear
oscillator that has the ability to generate a non-
sinusoidal periodic waveform at output.
20. The Wien bridge oscillator is
(a) a free running oscillator
(b) a square wave generator
(c) a stable sine wave generator
(d) also called cosine oscillator
KVS TGT (WE)- 2018,2017
Ans. (c) : A Wien's bridge oscillator is a type of
electronic oscillator that generates sine wave. It can
18. Frequency stability in an oscillator can be generate a large range of frequencies.
achieved by • Wien bridge oscillator
(a) adjusting the phase shift 1
(b) controlling its gain frequency of oscillation f =
2π C1C 2 R 3 R 4
(c) incorporating a tuned circuit
(d) employing automatic biasing If C1 = C2 = C and R3 = R4 = R
TANGEDCO- 2015 1
Then f =
Mizoram PSC AE/SDO 2012-Paper-I 2π RC
Ans. (c) : Crystal oscillator is a best source to obtain a 21. In VHF oscillator using butterfly capacitor
very high precise and stable frequency of oscillation. It (a) only L (b) only C
has very low frequency drift due to change in
temperature and other parameter. (c) both L and C (d) none of these
Frequency stability can be achieved by incorporating a Mizoram PSC AE/SDO-2012 Paper-III
tuned circuit in an oscillator. Ans. (c) : In very high frequency oscillator using
butterfly capacitor both L and C are used.
22. In an oscillator crystal, the parallel resonant
frequency is .............. series resonant frequency
(a) equal to (b) higher than
(c) lower than (d) none of these
Ans. (b) : In an oscillator crystal, the parallel resonant
frequency is higher than series resonant frequency
23. Reflex klystron oscillator uses
(a) one cavity resonator
(b) two cavity resonators
1
• Parallel resonance frequency f p = (c) three cavity resonators
2π L Ceq (d) both (a) & (b)
Mizoram PSC IOLM-, Paper-III

Ans. (a) : A reflex klystron is an absolute oscillator Ans. (a) : Wien bridge oscillator–It is a low-
type in which the electron beam is reflected back along frequency, low distortion, tunable, high-purity sine
its path by a high potential electrode, this oscillator uses wave generator, often used in laboratory work.
one cavity resonator. In Wien bridge oscillator, if the open loop gain of the
24. RC oscillator is basically a- op-amp is greater, then greater is the frequency stability
(a) Square wave generator of the oscillator.
(b) Pulse generator 28. When L is doubled and C is halved, the
(c) Sinusoidal wave generator frequency of oscillation is?
(d) Triangular wave generator (a) Doubled (b) Halved
UPPCL AE-16.11.2013
(c) One quarter (d) Unchanged
Ans. (c) : An RC oscillator is a basically type of TNPSC AE-2014
feedback oscillator which consist of a transistor an
amplifying device, a vacuum tube and an op-amp. An 1
Ans. (d) : f =
RC oscillator is basically a sinusoidal generator. 2π LC
25. In a phase shift oscillator, the minimum When L' = 2L
number of RC circuits required to generate a
C' = C/2
phase shift of 180º between input and output is
(a) 1 (b) 2 1 1
then, f = =
(c) 3 (d) 4 C 2π LC
UJVNL AE-2016 2π 2L ×
2
KVS TGT (WE)- 2014
29. The horizontal sweep oscillator in a TV
Ans. (c) : In a phase shift oscillator, the minimum operates at
number of RC circuits required to generate a phase shift
of 180º between input and output is 3. (a) 625 Hz (b) 1250 Hz
(c) 15625 Hz (d) 50 Hz
TNPSC AE-2014
Ans. (c) : Horizontal sweep,
Sweep rate = 15625 Hz
Sweep time = 64 µs
64 µs = 52 µs + 12 µs
52 µs = Beam travels from left to right
12 µs = Beam travels from right to left, Blanked out,
line blanking period.
30. Crystal oscillator are superior to tuned LC
oscillator because
(a) They have very high level of frequency
stability
26. The oscillator circuit (b) They have moderate level of frequency
(a) Cannot be operated in class A condition stability
(b) Can be operated in class A condition to give (c) They have a high value of Q-factor
sinusoidal waveform (d) Both (They have very high level of frequency
(c) Can be operated in class A condition to give stability) and (They have moderate level of
distorted waveform frequency stability)
(d) Can be operated in class A condition for MPPSC Forest Service Exam.-2014
better wave shape Ans. (a) : A crystal oscillator are superior to tuned LC
TNPSC AE-2014 oscillator because crystal oscillator has high level of
Ans. (b) : The essential condition for maintaining frequency stability. It has wide range of operating
oscillations and for finding the value of frequency is– temperature range.
βA = 1+ j0 or βA ∠φ = 1 ∠0
31. Wien bridge oscillator is used frequently
(i) The feedback factor or loop gain |βA| = 1
(a) When ever high feedback ratio is required
(ii) The net phase shift around the loop is 0º.
(b) When ever square output waves are required
27. In Wien bridge oscillator, if the open loop gain
(c) When ever wide range of high purity sine
of the Op-Amp is greater, then ______is the
frequency stability of the oscillator. waves are required
(a) Greater (b) Lesser (d) When ever extremely high resonant
(c) Zero (d) Constant frequencies are required

Ans. (c) : A Wien bridge oscillator is a simple circuit 37. A Hartley oscillator uses
that can be set to continuous oscillation which output is (a) A tapped inductor (b) A tapped capacitor
sine wave. Hence Wien bridge is used frequently when (c) Both (a) and (b) (d) Neither (a) nor (b)
ever wide range high sine waves are required. KVS TGT (WE)- 2018
32. Barkhausen criterion is related to Mizoram PSC Jr. Grade-2015, Paper-II
(a) Filter (b) Amplifier KVS TGT (WE)- 2014
(c) Oscillator (d) None of these Mizoram PSC AE/SDO -2012, Paper-II
MPPSC Forest Service Exam.-2014 Ans. (a) : A Hartley oscillator uses a tapped inductor.
Ans. (c) : Barkhausen criterion has two conditions first
the closed-loop gain is equal to 1, second the closed
loop phase angle is equal to 0º, with these condition the
oscillator circuit would generate a sinusoidal oscillator
signal.
33. Positive feedback is utilized in
(a) Power amplifier
(b) Low power amplifier
(c) Oscillator
(d) None of these
Ans. (c) : The condition for positive feedback is that a
partition of the output is combined in phase with the
input.
LT = L1 + L2
The use of positive feedback is useful for producing
oscillators. 1
f=
34. If 8 identical RC sections are used in the 2 π LT C
feedback path of a Phase-shift oscillator (with
non-inverting amplifier) it will oscillate at the 38. Crystals used in oscillator circuits for the
frequency at which each section shifts Phase by purpose of stabilizing frequency are made of
(a) 300 (b) 450 (a) quartz
0
(c) 60 (d) 22.50 (b) silicon
Nagaland PSC CTSE (Degree)-2016, Paper-II (c) germanium
Ans. (d) : In a 8 identical RC section, Provides phase (d) some other semiconductor material
180º Nagaland PSC 2018, Diploma Paper-II
shift in oscillator = = 22.5º
8 UPPCL AE-16.11.2013
35. What is the typical value of Q of a crystal? RPCS Lect.-2011
(a) 100 (b) 1000 Ans. (a) : Piezo-electric quartz crystal behaves like an
(c) 10,000 (d) More than 10,000 RLC circuit, composed of an inductor, capacitor and
Nagaland PSC CTSE (Diploma)-2017, Paper-I resistor, with a precise resonant frequency.
Ans. (d) : Piezoelectric effect quartz crystal has a very
39. What is the frequency of oscillation for an RC
high quality factor.
A typical Q for a quartz oscillator ranges from 104 to phase-shift oscillator with R of 10 kΩ and C of
106. The maximum Q for high stability quartz oscillator 0.001 µF in each of its three RC sections?
can be estimated as Q = 16 million/f, where f is the (a) 5.0 kHz (b) 5.5 kHz
resonance frequency in megahertz. (c) 6.0 kHz (d) 6.5 kHz
36. Quartz crystal is mostly used in crystal IES-2019
oscillator because Ans. (d) : R = 10kΩ
(a) It is easily available
C = 0.001µF
(b) It has superior electrical properties
(c) It is quite inexpensive C = 0.001× 10 −6 F
(d) It is very rugged Frequency oscillation for an RC phase-shift oscillator-
Nagaland PSC CTSE (Diploma)-2017, Paper-I 1
f0 =
Ans. (b) : This is mainly due to its low series resistance, 2πRC 6
Rs. As a result, quartz crystals make an excellent 1
component choice for use in oscillators especially in fo =
2 π × 10 × 10 × 0.001× 10−6 × 6
3
very high frequency oscillators.
1
Quartz crystal is mostly used in crystal oscillator fo =
because it has superior electrical properties. 2 × 3.14 × 0.01×10−6 × 2.45 × 103

100 ×1×106 ×100 ×100 Which of the above statements are correct?
fo = (a) 1 and 3 only (b) 2 and 4 only
628 × 245 × 103
1×106 ×106
fo = IES-2016
153860 ×103
Ans. (a) : Wien bridge has a larger bandwidth than the
f o = 6.499 kHz
phase shift oscillator.
fo 6.5 kHz Wien bridge has two capacitor while the phase shift
oscillator has 3 capacitor.
40. In the Wien bridge oscillator, the 0o phase-shift
is met by using lead-lag network and by using. Advantages of Wien bridge oscillator -
(a) Inverting op-amp i) It gives constant output.
(b) Non-inverting op-amp ii) The circuit works quite easily.
(c) Feedback op-amp iii) The overall gain is high.
(d) High-gain op-amp 43. Consider the following statements related to
IES-2019 oscillator circuits:
Ans. (b) : In the Wien bridge oscillator, the 0º phase 1. The tank circuit of a Hartley oscillator is
shift is met by using lead-lag network and by using non- made up of a tapped capacitor and a
inverting op-amp. common inductor.
2. The tank circuit of a Colpitts oscillator is
made up of a tapped capacitor and a
common inductor.
3. The Wien bridge oscillator is essentially a
two-stage amplifier with an RC bridge in
the first stage, and the second stage serving
as an inverter.
OP- Amp non-inverting Amplifier 4. Crystal oscillators are fixed frequency
The wien bridge has RC circuit in the two adjacent oscillators with a high Q-factor.
branches and determines the frequency of oscillations as Which of the above statements are correct?
well as acts as a feedback circuit. At one particular (a) 1,2 and 3 only (b) 2,3, and 4 only
frequency, the wien bridge is balanced and produces 0º (c) 1,2 and 4 only (d) 1,3 and 4 only
phase shift.
KVS TGT (WE)- 2017
41. In a sinusoidal oscillator, sustained oscillations
will be produced only if the loop gain (at the IES-2016
oscillation frequency) is Ans. (b) : The tank circuit of a colpitts oscillator is
(a) Less than unity but not zero made up of a tapped capacitor and a common inductor.
(b) Zero The Wien bridge oscillator is essentially a two-stage
(c) Unity amplifier with an RC bridge in the first-stage and the
(d) Greater than unity second stage serving as an inverter.
IES-2016 Crystal oscillators are fixed frequency oscillators
KVS TGT (WE)- 2014 with a high Q-factor.
DRDO -2008 44. For an Op-Amp phase shift oscillation, the
Ans. (c) : In a sinusoidal oscillator, sustained frequency of oscillations is
oscillations will be produced only if the loop gain (at 1 1
the oscillation frequency) is unity. (a) (b)
Barkhausen criteria for oscillation 2πRC 2πR 2C 2
i) Aβ = 1 1 1
(c) (d)
ii) ∠Aβ = 0º or 360º 2πRC 6 2πRC 3
KVS TGT (WE)- 2017
Wien bridge oscillator: IES-2015
1. It has a larger bandwidth than the phase shift Ans. (c) : In a phase shift oscillator, a phase shift of
oscillator 180º is obtained with a phase shift circuit instead of
2. It has a smaller bandwidth than the phase inductive or capacitive coupling.
shift oscillator For an Op-Amp phase shift oscillation the frequency of
3. It has 2 capacitors while the phase shift oscillation is-
oscillator has 3 capacitors.
1
4. It has 3 capacitors while the phase shift fo = Hz
oscillator has 2 capacitors. 2πRC 6

45. For various types of oscillators, the correct 47. Which one of the following oscillators is well
statement is : suited for the generation of wide range audio
(a) LC oscillators are more stable than crystal frequency sine waves?
oscillators (a) RC phase-shift oscillator
(b) Crystal oscillators have highest Q (b) Wien-bridge oscillator
(c) Phase-shift oscillators have the widest range (c) Colpitts oscillator
of frequency (d) Hartley oscillator
(d) Wien bridge oscillator is used where a single
IES-2009
frequency oscillator is required
ISRO Scientist Engg.-2012 Ans. (b) : Wien-bridge oscillator is well suited for the
generation of wide range audio frequency sine waves.
Ans. (b) : Various oscillator
Wien-bridge oscillator has wide range (5Hz to 1MHz)
Parameter LC Crystal RC phase audio frequency.
shift
Frequency It is a radio Fixed Audio
frequency frequency range
oscillator oscillator frequency
Stability Less stable More stable Stable
Quality Less Higher Less
factor
46. Which oscillator is characterized by a split
capacitor in its tank circuit?
(a) RC phase shift oscillator
(b) Colpitts oscillator 48. In a practical oscillator circuit, which one of
(c) Wien bridge oscillator the following limits the amplitude of the
(d) None of the above oscillations?
IES-2014 (a) Onset of non-linearity
Ans. (b) : Colpitts oscillator is characterized by a split (b) Power supply voltage
capacitor in its tank circuit. Colpitt’s oscillator uses two (c) Oscillation frequencies
capacitors and placed across a common inductor L and (d) Temperature of the active device
the centre of the two capacitors is tapped. The tank IES-2008
circuit is made up of C1, C2 and L.
Ans. (a) : In a practical oscillator circuit, onset of non-
The frequency of oscillation
linearity limits the amplitude of the oscillations. The
1
f= amplitude limit of sinusoidal oscillator is caused by
2 π LC T non-linearity. As the circuit element cannot have perfect
C1C 2 linear characteristics. The amplitude distortion of a
Where CT = sinusoidal oscillator is controlled by the onset of non-
C1 + C 2
linearity of the amplifying device.
49. Match List-I (Name of the oscillator) with List-
II (Characteristics) and select the correct
answer using the code given below the lists
List-I List-II
A. Colpitts Oscillator 1. RC Oscillator
B. Phase Shift Oscillator 2. LC Oscillator
C. Tunnel diode 3. Negative
Oscillator resistance
Oscillator
D. Relaxation Oscillator 4. Sweep circuits
A B C D
(a) 1 2 3 4
(b) 2 1 3 4
(c) 1 2 4 3
(d) 2 1 4 3
IES-2005
Ans. (b) : Colpitts oscillator- LC oscillator colpitt’s Ans. (a) :
oscillator uses two capacitors C1 and C2 placed across a
common inductor L and the centre of the two capacitors
is tapped.
Phase shift oscillator- RC oscillator a RC phase shift
oscillator gives 180º phase shift at output.
Tunnel diode oscillator-Negative resistance
oscillator.
Relaxation oscillator - sweep circuits.
50. Consider the following statements regarding a
common emitter amplifier it can be converted
into an oscillator by:
1. Providing adequate positive feedback An amplifier will generate stable sinusoidal oscillation
2. Phase shifting the output by 180º and if we provide feedback such that its poles lies close to
feeding this phase-shifted output to the jω -axis in the right half of s-plane.
input 52. Which one of the following circuits is most
3. Using only a series tuned circuit as a load suitable as an oscillator at a frequency of 100
on the amplifier. Hz.
4. Using a negative resistance device it’s a (a) Hartley oscillator (b) Colpitts oscillator
load on the amplifier. (c) Crystal oscillator (d) Twin-T oscillator
Which of the above statements are correct? IES-2001
(a) 1, 2, 3 and 4 (b) 1 and 2 RPSC Vice Principal ITI-2016
(c) 1, 3 and 4 (d) 3 and 4 Ans. (d) : Twin-T oscillator circuit is most suitable as
IES-2015, 2002 an oscillator at a frequency of 100Hz. Twin-T is
Ans. (b) : basically a frequency selective network. The Twin-T
network acts as the phase lead-lag network.
53. A relaxation oscillator is one which
(a) Has two stable states
(b) Oscillates continuously
(c) Relaxes indefinitely
(d) produces non-sinusoidal output.
IES-2001
Ans. (d) : A relaxation oscillator is one which produces
non-sinusoidal output.
Common Emitter Amplifier

Common emitter amplifier provides adequate positive
feedback.
Common emitter amplifier has 180º phase shift at  1+ β 
Time period of output signal, T = 2RC log  
output and feed this phase-shifted output to the input.  j−β 
51. An amplifier will generate stable sinusoidal Where,
oscillations if we provide feedback such that
R → feedback resistance
(a) Its poles lie close to jω-axis in the right half
of s-plane. β → feedback fraction
(b) Its poles lie close to jω-axis in the left half of Relaxation oscillator and UJT oscillator are non-linear
s-plane. oscillator. Non-linear oscillators or function generators
generate square-wave triangular wave, pulses etc.
(c) Its poles lie on the +ve real axis in s-plane
(d) Its poles lie anywhere in s-plane. 54. In every practical oscillator, the loop gain is
slightly larger than unity and the amplitude of
IES-2002 the oscillations is limited by the-
(a) Magnitude of the loop Ans. (c) :
(b) Onset of non-linearity Oscillator Characteristics features
(c) Magnitude of the gain of the amplifier (A) Wien Bridge RC oscillator for audio
(d) Feedback transmission factor frequency applications.
IES-2000 (B) Colpitts RF oscillator two capacitances
Ans. (b) : In every practical oscillator, the loop gain is and one inductance as the
slightly larger than unity and the amplitude of the reactance network.
oscillations is limited by the onset of non-linearity. The (C) Hartley RF oscillator two inductance and
amplitude limit of sinusoidal oscillator is caused by one capacitance on the reactance
non-linearity. As the circuit element can not have network
perfect linear characteristics. (D) Clapp LC oscillator for radio frequency
55. A Hartley oscillator is used for generating : three capacitances & one
(a) Very low frequency oscillation inductance in the reactance
(b) Radio-frequency oscillation network.
(c) Microwave oscillation 57. By proper selection of Rf and R1, the circuit
(d) Audio-frequency oscillation shown in the given figure can be used as a
IES-1999
Ans. (b) : A Hartley oscillator is used for generating
radio-frequency oscillation.
(a) Ramp generator

(b) Square wave generator
(c) Sawtooth generator
(d) Sine wave generator
IES-1996
Ans. (d) : By proper selection of Rf and R1, the circuit
shown in the given figure can be used as a sine wave
Frequency of oscillation for Hartley oscillator generator
1
f0 =
2 π C ( L1 + L 2 )
answer using the codes given below the lists :
List-I List-II
(Oscillator) (Characteristics Features)
A. Wien Bridge 1. RF oscillator two
inductance and one
capacitance on the
The sine wave generator is an excellent tool for
reactance network.
generating waves with speakers or wave drivers. Sine
B. Colpitts 2. LC oscillator for radio wave generator is a pure sine wave output variable from
frequency : three
1Hz to 1 MHz.
capacitances and one
inductance in the reactance 58. Match List-I with List-II and select the correct
network. answer using the code given below the lists :
C. Hartley 3. RC oscillator for audio List-I List-II
frequency applications (Name of the circuit) (Characteristics)
D. Clapp 4. RF oscillator : two A. Tunnel diode 1. Produces high
capacitances and one oscillators current pulses of
inductance as the reactance short duration.
network.
B. UJT oscillators 2. An LC oscillator
A B C D
used for generation
(a) 2 1 4 3
of sine wave at RF
(b) 2 4 1 3
(c) 3 4 1 2 C. Hartley oscillators 3. A negative resistance
(d) 3 1 4 2 oscillator for
IES-1996 microwave frequency

D. Blocking oscillators 4. Uses negative Differential eqn (ii) w.r.t. K
resistance property d 2 h f e 58
for the generation of = >0
saw tooth wave-form dK 2 K 3
Codes : 29
Put the value of k = in equation (i)
A B C D 2
(a) 3 2 1 4 29 29
(b) 1 2 4 3 h fe / min = 23 + + 4×
29 / 2 2
(c) 3 4 2 1 58
(d) 4 3 1 2 = 23 + + 2 29
29
IES-1995
58
Ans. (c) : = 23 + + 2 × 5.385
5.385
Sr. Oscillators Characteristics = 23 + 10.77 + 10.77
No.
h fe / min = 44.54
(A) Tunnel diode A negative resistance
oscillators oscillator for 60. Match the following
microwave frequency. List-I List-II
(p) Hartley (1) Low frequency oscillator
(B) UJT oscillators Uses negative (q) Wien-bridge (2) High frequency oscillator
resistance property for (r) Crystal (3) Stable frequency oscillator
the generation of saw (4) Relaxation oscillator
tooth wave-form. (5) Negative resistance
(C) Hartley oscillators An LC oscillator used oscillator
for generation of sine p q r
wave at RF. (a) 2 1 3
(D) Blocking oscillators Produces high current (b) 1 2 3
pulses of short (c) 2 3 1
duration. (d) 3 1 2
59. The minimum value of hfe of a transistor to be Punjab PSC Poly. Lect. 20.08.2017
used in three-section RC phase shift oscillator GATE-1994
is Ans. (a) :
(a) 54.4 (b) 45.4 (p) Hartley High frequency oscillator (10
(c) 44.5 (d) 29 kHz to 100 MHz)
UPRVUNL AE -19.07.2021, Shift-II (q) Wien-bridge Low frequency oscillator
IES-1995 oscillator (1Hz to 1 MHz)
(r) Crystal oscillator Stable frequency oscillator
Ans. (c) : The minimum value of hfe of a transistor to be
(For fixed frequency)
used in three-section RC
29 61. Value of R the oscillator shown in the given
h fe = 23 + + 4K .............(i) figure. So chosen that it just oscillates at an
K
angular frequencies of ' ω'. The value of 'ω' and
Where; the required value of R will respectively be
R
K= C
R
R C = Collector Resistance
R = Resistance of an RC section
Differential eqn (i) w.r.t. K
d h fe 29
=0− 2 +4
dK K
d hf e 29
= 4 − 2 = 0 .......(ii)
dK K (a) 105 rad/sec, 2 × 104 Ω
4K 2 − 29 = 0 (b) 2 × 104 rad/sec, 2 × 104 Ω
(c) 2 × 104 rad/sec, 105 Ω
29 105 rad/sec, 105 Ω
K= (d)
2 GATE-1996

Ans. (a) : Given, R + 1k = 21×1k
C = 0.01µF R f = 100kΩ , Rin = 5kΩ R = 21k − 1k
L = 10mH R1 = 1kΩ R = 20kΩ or R = 2 ×104 Ω
1 62. The configuration of the figure is a
Angular frequencies, ω =
LC
1
ω=
10 ×10 × 0.01×10−6
−3
ω = 105 rad/sec
(a) Precision integrator

(b) Hartley oscillator
(c) Butterworth high pass filter
According Nodal analysis–
(d) Wien-bridge oscillator
Vf − Vo Vf Vf GATE-2000
+ + + Vf X C = 0
R 1k X L Ans. (d) : Wien-bridge oscillator
Vf Vo Vf   1 
− + + Vf  j  − ωc   = 0
R R 1k   ωL 
1 1   1   Vo
Vf  +  + Vf  j  ωL − ωc   = R ......... (i)
 R 1k    
1
From equation (i) for oscillation, ωc =
ωL
1
ωc − =0
ωL
1
ωc = 1
ωL Resonant frequency, f o =
2πRC
1 1 V
Vf  +  = o Used for low frequency oscillator (1Hz to 1 MHz)
 R 1k  R 63. The oscillator circuit shown in the figure is
1
Vf 1k
β= = R = ............(2)
Vo 1
+
1 R + 1k
R 1k
Rf
A = 1+
R in
100
= 1+
5
(a)
Hartley oscillator with foscillation = 79.6 MHz
A = 21
(b)
Colpitts oscillator with foscillation = 50.3 MHz
1 1 (c)
Hartley oscillator with foscillation = 159.2 MHz
β= = (d)
Colpitts oscillator with foscillation = 159.2 MHz
A 21
From equation (2) GATE-2001
Ans. (b) : Given circuit is a colpitts oscillator
1k
β= Given, L = 10µH
1k + R
C1 = 2pF
1 1k
= C2 = 2pF
A R + 1k
1 1k C1C2 2× 2
= Ceq = =
21 R + 1k C1 + C2 2 + 2

4 βVo R 2 + βVo R1 = Vo R1
= =1
4  1
βR 2 + βR1 = R1 β = 6 
Ceq = 1pF
1 1
1 × R 2 + R 1 = R1
f= 6 6
2 π LCeq
R 2 + R1 = 6R1
1
= R 2 = 5R1
2π 10 × 10−6 × 10−12
65. The oscillator circuit shown in the figure has
1 an ideal inverting amplifier. Its frequency of
=
2 × 3.14 × 10−9 × 3.16 oscillation (in Hz) is
1
=
19.8448 ×10−9
f = 50.5MHz or f 50.3 MHz
64. The circuit in the figure employs positive
feedback and is intended to generate sinusoidal
oscillation.
V (f) 1
If at a frequency f0' B(f) = f = ∠0° then to 1 1
V0 (f) 6 (a) (b)
(2π 6RC) (2πRC)
sustain oscillation at this frequency
1 1
(c) (d)
( 6RC) 6(2πRC)
GATE-2003
Ans. (a) : Inverting Amplifier-
(a) R2 = 5R1 (b) R2 = 6R1

R R
(c) R 2 = 1 (d) R 2 = 1
6 5
GATE-2002
Ans. (a) :
The oscillator circuit shown in the above figure has an
ideal inverting amplifier. Its frequency of oscillation (in
Hz) is
1
fo = Hz
2π 6RC
In RC phase shift oscillator, the RC network consisting
of three identical RC sections determines the frequency
of oscillations as well as produces 180º phase shift.
66. The value of C required for sinusoidal
oscillations of frequency 1 kHz in the circuit of
Given, the figure is
1
β=
6
KCL at input -
βV0 − 0 βV0 − V0
+ =0
R1 R2
βVo R 2 + βVo R1 − Vo R1
=0
R 1R 2

1 67. The circuit shown in the figure has an ideal op-
(a) µF (b) 2 πµF
2π amp. The oscillation frequency and the
1 condition to sustain the oscillations,
(c) µF (d) 2π 6µF respectively, are
2π 6
GATE-2004
Ans. (a) :
1
(a) and R1 = R2
CR
1
(b) and R1 = 4R2
CR
1
Given, (c) and R1 = R2
2CR
R f = 2.1kΩ
1
R = R1 = 1kΩ (d) and R1 = 4R2
2CR
KCL at output Node
GATE-2015, Set-I
VO − V1 V1 V1
− − =0 Ans. (d) :
XC + R XC R
VO − V1  1 1
= V1  + 
XC + R  XC R 
VO − V1 (X + R )
= V1 C
XC + R XC R
VO V1 ( X C + R )
2
− =
V1 V1 XCR
1
Frequency of Wien bridge oscillator, f o =
VO ( X C + R )
2
1 2πRC
= +1 XC = −
V1 XCR ωC 1 1
Oscillation frequency, ωo = ⇒R=
VO jωC  1 2 jR  RC ω0 C
= − 2 2 + R −
2
 +1
V1 R  ωC ωC  When time constant is doubled then frequency becomes
Imaginary part is zero for oscillation. half.
−1 1
+ ωCR = 0 So, ωo =
ωCR 2RC
ω2C2 R 2 − 1 = 0 1
Z1 = 2R + = 2 ( R − jR )
1 jωC
ω2 = 2 2
CR 1 R
1 R×
ω= 2 jωC 2 jωC
Z2 = =
CR 1 2 jωCR + 1
1 R+
C= 2 jωC 2 jωC
ωR
R
1 Z2 =
= 2 jωCR + 1
2πf R
1 R2 j
= Z2 =
2π × 103 × 103 R − jR
1 R2
C= µF Z2 =
2π R + jR

R2 Ans. (a) :
Z2 R + jR
β= =
Z1 + Z2 R2
2 ( R − jR ) +
R + jR
R2 R + jR
β= ×
R + jR 2 ( R − j2 R 2 ) + R 2
2
R2
=
5R 2
1
β=
5
R1 1
1+ = Introduce amplitude stabilization by preventing the
R2 β OP-Amp from saturating and thus producing sinusoidal
R1 oscillations of fixed amplitude.
1+ =5
R2 69. In an RC phase shift oscillator using FET, for
R1 sustained oscillations, the minimum voltage
=4 gain of the FET should be
R2
(a) 29
R 1 = 4R 2 (b) 64
(c) 51
68. Consider the oscillator circuit shown in the
figure. The function of the network (shown in (d) 56
dotted lines) consisting of the 100 kΩ resistor in APPSC POLY. LECT. 14.03.2020
series with the two diodes connected back-to- Nagaland PSC CTSC (Degree)-2017, Paper-II
back is to: Ans. (a) : In an RC phase shift oscillator using FET, for
sustained oscillations, the minimum voltage gain of the
FET should be 29.
70.
(a) Introduce amplitude stabilization by

preventing the op-amp from saturating and
thus producing sinusoidal oscillations of fixed
amplitude
(b) Introduce amplitude stabilization by forcing For a Hartley Oscillator X1, X2 and X3
the op-amp to swing between positive and respectively are :
negative saturation and thus producing square (a) L.L.C.
wave oscillations of fixed amplitude (b) C.C.L
(c) Introduce frequency stabilization by forcing (c) L.C.L.
the circuit to oscillate at a single frequency (d) LC.L.C
(d) Enable the loop gain to take on a value that APPSC Poly. Lect. 15.03.2020
produces square wave oscillations Ans. (a) : X 1 = X 2 = L
GATE-2016, Set-I X 3 = C

• β = 1/ 3 for oscillation
Where β = Feedback factor
• R 2 ≥ 2R1 for oscillator
73. A beat frequency oscillator uses
(a) Two RF oscillators (b) Two AF oscillators
(c) One RF oscillator (d) One AF oscillator
Ans. (a) : Two RF oscillators.
1
f0 =
2π L T ⋅ C
LT = L1 + L 2
71. FET phase shift oscillator uses
(a) Voltage series feedback
It uses two radio frequency (RF) oscillators. One is
(b) Voltage shunt feedback
fixed frequency oscillator and other is variable
(c) Current series feedback frequency oscillator. The output of both oscillators are
(d) Current shunt feedback fed as a input to the mixer. The mixer output is the
Nagaland PSC (Degree) 2018, Paper-II signal with a frequency given by difference of two input
TSGENCO AE-2015 frequency.
Ans. (a) : Voltage series feedback- In a FET phase 74. A blocking oscillator
shift oscillator voltage series feedback is used that is (a) Is a triggered oscillator
feedback voltage proportional to the output voltage (b) Generates sinusoidal waves
(Vout) and supplied in series with the input signal at the
(c) Is an amplifier with a negative feedback
gate is used.
(d) Produces very sharp and narrow pulses
Ans. (d) : A blocking oscillators is a waveform
generator that is used to produce very sharp and narrow
pulses and are used as high impedance switches and
frequency dividers. It is simple configuration of discrete
electronic component which can produces a free
running signal.
75. Which sinusoidal oscillator is preferred
(a) Resonant circuit (b) RC phase shift
(c) Negative resistance (d) None of these
Ans. (b) : RC phase shift oscillator is preferred because
capacitor passes ac signal through it.
Application of FET phase shift oscillator :-

FET phase shift oscillator is used for generating signals
over a wide frequency range.
72. In a Wien bridge oscillator, the positive
feedback attenuation is
(a) 1/3 (b) 1/29
(c) –29 (d) 3
Ans. (a) : Wien bridge oscillator
1
• Frequency oscillator ( f ) =
2π R 3 R 4 C 2 C1

R.C shift oscillator is used to generate the signals over Ans. (a) : When a transfer function has one pair of pole
an extensive range of frequency. They are used in at imaginary axis. The system will produce oscillatory
musical instruments, GPS units & voice synthesis. output. Hence on oscillator has its pole on imaginary
76. Blocking oscillators are used as axis.
(a) Abrut pulse generator 80. The range of frequency generated by VHF
(b) Low impedance switches oscillator is-
(c) High impedance switches and frequency (a) 300 MHz - 3 GHz (b) Above 3 GHz
dividers (c) 30 MHz - 300 MHz (d) 20 kHz - 30 MHz
(d) None of the above RRB JE- 31.08.2019, 10 AM-12 PM
Nagaland PSC CTSE- 2015, Paper-II Ans. (c) : VHF (Very High Frequency) (30 MHz –
Ans. (c) : Blocking oscillators are used as high 300 MHz)
impedance switches and frequency dividers. In FM radio broadcasts, very high frequency are
Note– It is simple configuration of discrete electronic typically used for two way land mobile radio systems,
components which can produce a free running signal. long-distance data communications and maritime
communications. VHF includes radio waves ranging
77. Conditions for oscillations in oscillator circuits
from 30MHz to 300 MHz.
are:
C1: a phase shift of 0º around the feedback loop Type of Frequency Application
frequency Range
C2: a phase shift around the feedback loop of 180º
C3: a gain of 1 around the feedback loop Low frequency 30 to 300 kHz Navigation
C4: the attenuation of the feedback circuit must be Medium 300 kHz to 3 Marine/Aircraft
one-third frequency MHz navigation, AM
(a) Conditions C1 and C3 are correct broadcast
(b) Conditions C1 and C4 are correct High frequency 3 MHz to 30 Broad coasting,
(c) Conditions C2 and C4 are correct MHz Mobile radio
(d) Conditions C2 and C3 are correct Very high 30 MHz to 300 FM broad
(e) Conditions C1 alone is correct frequency MHz coasting
CGPSC SO 14.02.2016 Ultra high 300 MHz to 3 Cell phone,
Ans. (a) : An oscillation can designed so that the frequency GHz mobile radio,
oscillation frequency can be varied over some range by WLAN
an input voltage or current. Super high 3 GHz to 30 Radar TV
Conditions : 1. gain of 1 around the feedbacks loop. frequency GHz
(2) A phase shift of 0º around the feedbacks loop. 81. A high Q-quartz crystal exhibits series
78. For MHz frequency operation which type of resonance at the frequency ωs and parallel
oscillator is suitable. resonance at ωp, then-
(a) RC phase shift (b) Wien bridge (a) ωs is very close but less than ωp
(c) Hartley (d) All (b) ωs is very close, but greater than ωp
NPCIL-2015 (c) ωs >> ωp
(d) ωs << ωp
Ans. (c) : For MHz frequency operation Hartley
oscillator is more suitable. Hartley oscillator is a type of RRB JE- 31.08.2019, 10 AM-12 PM
LC oscillator that generates undamped sinusoidal BPSC Polytechnic Lecturer-2014
oscillations whose tank circuit consists of two inductors Ans. (a) :
and a capacitor.
In this oscillator
where ( L eq = L1 + L 2 )
1
fo =
2π Leq C
79. The poles of an oscillator are:
(a) lie on the imaginary axis.
(b) lie on unit circle centered at origin in s-plane
(c) lie on the left half of s-plane.
(d) lie on the right half of s-plane.
1
Mizoram PSC IOLM-2010, Paper-II fS =
UPPCL AE-05.11.2019 2π LCS

1 Ans. (c) : In a radio transmitter, the frequency of the
fS =
C C crystal oscillator will be stable for a long time if the
2π L P S
C P + CS quality factor of the crystal resonator is. > 1000
fP > fs or ωp>ωs 84. In phase-shift oscillator, a single RC network

introduces a phase change of
ωs is very close but less than ωp
(a) 360º
82. A Hartley oscillator uses L1 =2 mH and L2 = 1.5
(b) 180º
mH. The range of capacitance so that the
(c) 90º
frequency of oscillation can be varied between
1000 kHz to 2000 kHz are (d) 60º
(a) C max = 7.2pF and C min = 1.8pF UKPSC Assistant Radio Officer Screening Exam.-2011
(b) C max = 9.2pF and C min = 0.8pF SRC

Ans. (d) : Consider a RC Network H(s) =
1 + SCR
(c) C max = 7.2pF and C min = 0.8pF
π
(d) C max = 9.2pF and C min = 1.8pF ∠H(jω) = − tan −1 ( ωRC )
2
ESE-2021
π
Ans.(a) : Given that Maximum phase shift will be . If RC = 0.
2
L1 = 2mH
But this is not possible because in circuit component
L2 = 1.5mH
will take finite value, that's why phase shift by 1 section
LT = L1 + L2
π
= 2 + 1.5 less than for typically 60º.
2
LT = 3.5 mH
85. Which of the following oscillators uses a
fmin = 1000 kHz capacitive voltage divider to provide feedback?
fmax = 2000 kHz (a) Colpitts
A Hartley oscillator (b) Multivibrator
1 (c) Hartley
f=
2 π LT C (d) RC phase shift
1 RRB JE-01.09.2019, 3:00 PM – 5:00 PM
C=
( 2 πf )
2
LT Ans. (a) : Colpitts uses two capacitors and placed
1 across a common inductor L and the center of the two
C max = capacitors is tapped. The tank circuit is made up of C1,
( 2 × 3.14 ×1000 ×10 ) 3 2
× 3.5 × 10−3 C2, and L. The frequency of oscillations is determined
1 by the values of C1, C2 and L and given by-
C max =
39.4384 × 1012 × 3.5 × 10−3
Cmax = 0.0072×10-9
Cmax = 7.2 pF
1
C min =
( 2 × 3.14 × 2000 × 103 ) × 3.5 × 10−3
2
1
C min =
157.75 × 1012 × 3.5 × 10−3
= 0.0018×10-9
Cmin = 1.8 pF.
83. In a radio transmitter, the frequency of the
crystal oscillator will be stable for a long time if
the quality factor of the crystal resonator is
(a) >100 (b) >500
• The colpitts oscillator uses a capacitive voltage
(c) > 1000 (d) > 20000
divider network as its feedback source.
BSNL (JTO)-2006
Ans. (b) :
(viii) Operational Amplifiers and
Their Applications
1. In sample and hold circuit, op-amp is
connected as :
(a) Unity gain inverting voltage amplifier V0 ( s ) − Zf − ( R 2 || X C )
= =
(b) Unity gain non inverting voltage amplifier Vi ( s ) Z1 R1 + X L
(c) Unity gain inverting current amplifier
1
(d) Unity gain non inverting current amplifier (a) at f = 0, X C = = ∞ → C is open circuit
2πf C
BPSC Asstt. Prof.-12.04.2022
X L = 2πf C = 0 → L is short circuit
Nagaland PSC (Degree) 2018, Paper-II V0 ( s ) = −R 2
Nagaland PSC CTSE (Degree) 2017, Paper-II Vi ( s ) R1
GATE-2000 For small f, X C → very large, X L → very small
Ans. (b) : In sample and hold circuit, op-amp is V0 ( s ) ( R 2 || very large ) −R 2
= ≅
connected as unity gain non-inverting voltage amplifier. Vi ( s ) ( R 1 + very small ) R1
2. A circuit using an operational Amplifier shown This circuit is going to be passing zero freq. as well as
below has low freq.
(b) as frequency increases–
f ↑ ( high frequency ) : X C ↓ ( X C < R 2 ) X L ↑ ( X L > R1 )
V0 ( s ) − ( R 2 || very small ) very small X C
= =
Vi ( s ) R 1 + very large very large X L
= very small ≅ 0
(a) Voltage series feedback • For High frequency gain is zero.
(b) Voltage shunt feedback −R 2
• For the Low frequency zero frequency gain is
(c) Current shunt feedback R1
(d) Current series feedback • This circuit is going to be acting as low pass filter.
BPSC Asst. Prof. - 12.04.2022 4. Which one of the following statements
TNPSC AE- 2019 regarding slew rate is correct?
(a) It signifies how rapidly the output of an op-
IES - 2004 amp can change in response to changes in the
Ans. (b) : Voltage shunt feedback- It is also known as frequency of the input signal
shunt-driven shunt-fed feedback i.e. it is parallel- (b) It does not change with change in voltage
parallel prototype. Here, a small portion of the output gain
voltage is coupled back to the input voltage parallel (c) It should be smaller for high speed op-amp
applications
(shunt).
(d) It is not fixed for an op-amp
A shunt feedback always decreases input and output UPRVUNL AE -19.07.2021, Shift-II
impedance. IES-2020, 2016
3. The op-amp circuit shown below represents a Ans. (a) : Op-amp slew rate - The slew rate of an op-
amp or any amplifier circuit is the rate of change in the
output voltage caused by a step change on the input.
Unit of slew rate = V/µs or V/ms
(a) High pass filter (b) Low pass filter

(c) Band pass filter (d) Band reject filter Note - Generally slew rate have 10 V/µs
BPSC Asst. Prof. - 12.04.2022 dV
Slew rate = o V/µsec
GATE-2008 dt

5. An op-amplifier based zero crossing detector Ans. (a) : For general inverting summing amplifier,
converts sinusoidal waveform into a, R
(a) Triangular waveform (b) Impulse train VO = − f ( V1 + V2 + V3 ) …(i)
R
(c) Square waveform (d) Cosine waveform
Given,
Ans. (c) : If reference voltage VR is set equal to zero the ( V + V2 + V3 )
VO = − 1 …(ii)
output will respond almost discontinuously every time 3
the input passing through zero Such an arrangement is Comparing equation (i) & (ii)
called a zero-crossing detector and it convert sinusoidal Rf 1
waveform into a square waveform. =
R 3
6. The circuit shown below acts as a
⇒ R = 3R f
9.
If an averaging amplifier has five inputs; the
ratio Rf/Ri must be:
(a) 0.2 (b) 5
(c) 2 (d) 0.1
(a) Summing Integrator Ans. (a) : Average amplifier is also known as summing
amplifier.
(b) Summing Differentiator
(c) Antilogarithmic Amplifier V + V2 + V3 + V4 + V5
V0 = 1 .............(i)
(d) Logarithmic Amplifier 5
RPSC ACF & FRO 23.02.2021 R
VO = − f ( V1 + V2 + V3 + V4 + V5 ) ..............(ii)
Ans. (a) : Summing Integrator R
Comparison equation (i) and (ii)
1 Rf
= = 0.2 (consider only magnitude)
5 Ri
10. What is CMRR, if Ad = 30 dB and Ac = 2 dB?
(a) 26 dB (b) 28 dB
(c) 32 dB (d) 20 dB
1  V1 V2 V3  UPRVUNL AE -19.07.2021, Shift-II
V0 = − ∫ + +  dt
C  R1 R 2 R 3  Ans. (b) :Given,
R 1 = R2 = R3 = R Ad = 30dB, Ac =2dB
1 A 
V0 = − ∫ ( V1 + V2 + V3 ) dt CMRR = 20 log  d 
RC  Ac 
7.
( )
If we apply square wave to input to an ideal CMRR dB = 30 − 2 = 28dB
integrator, then the output is:
(a) square wave (b) triangular wave 11. The following figure is a circuit diagram
(c) cosine wave (d) sine wave of .
IES-2003
Ans. (b) : Output of Ideal integrator is
1
Vi ( t ) dt
RC ∫
V0 = −
∴ Output = Integration of input (a) comparator
Given input = Square wave (b) difference amplifier
Output = Integration of square wave (c) voltage follower
= Triangular wave (d) inverting amplifier
8. For a three-input inverting summing amplifier,
(V + V2 + V3 ) Ans. (c)
Vout = − 1 , what is the relation
3
between Rf and R?
(a) R = 3Rf (b) Rf = 0.3R
(c) R = 0.3Rf (d) Rf = 3R
V+ = Vin V– = Vout 16. If an op-amp comparator has a gain of 100,
Due to virtual short, 000, an input difference of 0.2 m V above
V+ = V– reference, and a supply of ±12 V. the output
∴ Vin = Vout will be:
Output voltage follows the input voltage (a) 15 V (b) 12 V
∴ voltage follower (c) 20 V (d) 10 V
12. Decreasing the gain in the op-amp non- UPRVUNL AE -19.07.2021, Shift-II
inverting amplifier circuit could be achieved Ans. (b) : In an op-amp comparator.
by: It i/p difference voltage is +ve and above reference then
(a) increasing the value of the feedback resistor o/p voltage is +ve supply i.e 12 V.
(b) removing the feedback resistor It i/p difference voltage is –ve and above reference then
(c) increasing the value of the input resistor o/p voltage is –ve supply i.e –12V.
(d) reducing the amplitude of the input voltage
UPRVUNL AE -19.07.2021, Shift-II 17. An operational amplifier possesses
(a) Very large input resistance and very large
Ans. (c) : Gain of non- inverting op-amp can be
decreased by the increasing the input resistance. output resistance
(b) Very large input resistance and very small
 R  output resistance
Gain = 1 + f 
 Ri  (c) Very small input resistance and very small
13. For the given circuit, if R1 = R2, then voltage output resistance
gain will be . (d) Very small input resistance and very large
output resistance
RRB JE-01.09.2019, 3:00 PM – 5:00 PM
IES-2020, 2019, 2015, 2002, 1992
(a) very small (b) – 1 OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
(c) 10 (d) 1 Mizoram PSC IOLM -2018, Paper II
UPRVUNL AE -19.07.2021, Shift-II GPSC Asstt. Prof. 11.04.2017
Ans. (b) : Given circuit is a inverting amplifier Nagaland PSC CTSE (Diploma)-2017, Paper-I
V R CGPSC SO 14.02.2016
gain = 0 = − 2
Vin R1 BEL-2015
R2 = R1 TSPSC Manager (Engg.) - 2015
Gain = –1 TNPSC AE-2014
14. If we apply square wave to an ideal MPPSC Forest Service Exam.-2014
differentiator, then we get _______ as its SAIL-2014
output. ISRO Scientist Engg.2009, 2007
(a) train of impulses (b) cosine GATE-2001
(c) ramp (d) negative cosine
Ans. (b) : Op-Amp characteristics -
• Open loop gain (ACL) = ∞ → very high
Ans. (a) : If we apply square wave to an ideal
differentiator we get train of impulses as its output. • Input resistance (Ri) = ∞ → very high
differentiation • Output resistance (R0) = 0 → very small
step function  → impulse .
• Bandwidth (BW) = ∞ → very high
15. If the gain Acl of an inverting amplifier is 4.9, • CMRR = ∞ → very high
with an input resistor value of 2.2 kΩ, what • Slew rate = ∞ → very high
value of feedback resistor is necessary?
• Offset voltage = 0 → very low.
(a) 2.4 kΩ (b) 10.78 Ω
(c) 107.8 kΩ (d) 10.78 kΩ
−R f
Ans. (d) : Gain in inverting amplifier, A CL =
Ri
Rf = –ACL Ri
Rf = 4.9×2.2k
R f = 10.78 kΩ

Function diagram of op-amp - Nagaland PSC CTSE (Degree)-2017, Paper-II
GATE-2004
Ans. (b) : For an ideal op-amp.
Vout = A × Vi
So it is a voltage controlled voltage source.
The ideal op-Amp has following characteristics
• Input impedance = infinity
• Output impedance (open loop) = 0
18. In the differential amplifier shown in the • Common-mode voltage gain = 0
figure, the magnitudes of the common-mode
• Vout = 0 when both inputs are at the same voltage
and differential-mode gains are Acm and Ad'
respectively. If the resistance RE increased, (zero "offset voltage")
then • Output can change instantaneously (infinite slew
rate)
• The purpose of bias current is to achieve the ideal
behavior in Op-Amp which has high CMRR, high
differential gain and high input impedance.
20. The inverting op-amp shown in the figure has
an open-loop gain of 100. The closed-loop gain
V0/Vs is
(a) Acm increase

(b) Common-mode rejection ratio increases
(c) Ad increase (a) –8 (b) –9
(d) Common-mode rejection ratio decreases (c) –10 (d) –11
Nagaland PSC CTSE (Degree)-2018, Paper-II APPSC Poly. Lect. 14.03.2020
GPSC Asstt. Prof. 11.04.2017 CGPSC SO 14.02.2016
Nagaland PSC CTSE (Degree)-2017, Paper-II BPSC Poly. Lect.2014, GATE-2001
Ans. (b) : Given open loop gain = 100
GATE-2014, 2005 Then, V0 = A oL ( V+ − V− )
TNPSC AE-2013 V0 = 100 ( 0 − V− ) = −100V− ………….(i)
IES-2012 Apply super position at inverting terminal-
V− = (Due to Vs only) V o =0 + (Due to Vo only) V s =0
Ans. (b) :
 –g R   10   1 
V− =   Vs + Vo  
Ad  m c
  10 + 1   10 + 1 
CMRR = =  –R c  = 2g R
A cm  2R 
m E From equation (i)

E
 −Vo 10Vs Vo
= +
100 11 11
−R C
A cm =  111 
2R E − Vo   = 10Vs
 100 
As R E ↑→ A d ↑→ A c ↓→ CMRR ↑
V −1000
When RE is increased then Acm is decreased and CMRR A CL = o = −9
increases. Vs 111
19. The ideal op-amp is an ideal Hence, closed loop gain = –9
(a) Voltage controlled current source 21. If the input to the circuit of figure is a sine
(b) Voltage controlled voltage source wave the output will be
(c) Current controlled current source
(d) Current controlled
(a) A half-wave rectified sine wave
A 
(b) A full-wave rectified sine wave CMRR = 20log  d 
(c) A triangular wave  Ac 
(d) A square wave CMRR = 20log A d − 20log A c
RPSC VP/Suptd. ITI-05.11.2019 = 48 − 2
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I CMRR = 46 dB
BPSC Polytechnic Lecturer-2014 23. If a differential amplifier has a gain of 20,000
ISRO Scientist Engg.2010 and CMRR = 80 dB, its common mode gain is:
Ans. (d) : (a) 2 (b) 1
(c) 1/2 (d) 0
TNPSC AE - 2018
IES-2013, 1992, ISRO Scientist Engg.-2007
Ans. (a) :
Q Op-amp open loop without feedback, it work as Solution –
comparator.
A 
Q CMRR = 20log  d 
 Ac 
Given value - A d = 20000
CMRR = 80dB
A 
CMRR = 20 log  d 
Ideal case,  Ac 
A OL = ∞, R i = ∞, R o = 0 20000
80 = 20log
Ac
Vo = ± VSat
20000
Vo = A OL ( Vid ) 4 = log
Ac
Vo = A OL ( V+ − V− ) = A OL ( V2 − V1 ) 20000
104 =
If V2 > V1 then, Vo = + Vsat. Ac
And V2 < V1 then, Vo = −Vsat . 20000
Ac =
Represented graph, square wave, 10000
Ac = 2
24. The large signal bandwidth of an op-amp is
limited by
(a) Its slew rate specification
(b) Its Gain-bandwidth product
(c) CMRR
(d) None of these
Nagaland PSC 2018 Diploma paper -II
22. If the differential voltage gain and the common Nagaland PSC CTSE (Diploma)-2018, Paper-I
mode voltage gain of a differential amplifier Punjab PSC Poly. Lect. 20.08.2017
are 48 dB and 2 dB respectively, then its
IES-2015
common mode rejection ratio is
(a) 23 dB (b) 25 dB Ans. (a) : The large signal bandwidth of op-amp is
limited by slew rate because
(c) 46 dB (d) 50 dB
GPSC Asstt. Prof. 11.04.2017  dV 
slew rate =   = 2πVm f V/µsec
Mizoram PSC IOLM -2018, Paper II  dt  m
Punjab PSC Poly. Lect. 20.08.2017 25. An OP-AMP has a slew rate of 5V/µs. The
GATE-2003 largest sine wave O/P voltage possible at a
Ans. (c) : Given value– frequency of 1MHz is
Differential voltage gain Ad = 48 dB. (a) 10π volts (b) 5 volts
Common mode voltage gain Ac = 2dB 5
(c) volts (d) 5/2π volts
Find out value-CMRR = ? π
A TNPSC AE-2019
CMRR = d Kerala PSC Lecturer (NCA) 04.07.2017
Ac Mizoram PSC Jr. Grade-2015, Paper-II
Ans. (d) : Slew rate = 2πf m Vm = 0.04 sec.
1
5 × 10 = 2π × 10 Vm
6 6
Q Feedback frequency f =
τ
5
Vm = f=
1
= 25Hz .....(ii)
2π 0.04
26. Compare to equation (i) and (ii),
Source frequency > feedback frequency
Since capacitor becomes short circuit. So, output
voltage is equal to voltage at inverting and non-
inverting terminal of op-amp.
Therefore, Output signal V0 = 1 Vrms
28. A high gain OpAmp has Rf = 105 Ω & Ri =103
Ω. The correct statements is :
(a) The non-inverting gain & inverting gain are
nearly same.
(b) The inverting gain is very much higher than
In the circuit shown in the above figure, the non-inverting gain
value of output V0 is (c) The non-inverting gain is very much higher
(a) +6V (b) –9V than inverting gain
(c) –6V (d) +9V (d) The inverting & non-inverting gains are
ISRO Scientist Engg. 2009 unrelated
Ans. (b) : According to circuit diagram ISRO Scientist Engg.-2012
Q op-amp as an adder Ans. (a) : Given, Rf = 105Ω, Ri = 103Ω
R R R  Q for inverting terminal
V0 = − IR f = −  f × V1 + f × V2 + f × V3  −R f −105
 R1 R2 R3  ∴ V0 = = = −100 …………….(i)
Q Given value, Ri 103
V1 = 1, V2 = 2, V3 = 3
R 1 = 40kΩ, R 2 = 80kΩ, R 3 = 120kΩ
R f = 120kΩ
120 120 120 
V0 = −  ×1 + ×2+ ×3
 40 80 120 
V0 = –[3+3+3]
V0 = −9V
27. What is the output signal level of following
circuit? And non inverting terminal,
 R  105
V0 = 1 + f  = 1 + 3
 Ri  10
= 1 + 100 = 101 …………………………..(ii)
So, from equation (i) and (ii), magnitude are nearly
same.
29. Determine output voltage 'V0' for below circuit
where Vin=Sin(100πt)
(a) ∼5 Vrms (b) ∼1 Vrms

(c) ∼4 Vrms (d) ∼0.1 Vrms
Ans. (b) : Given,
Source frequency (fs) = 200kHz...(i)
Feedback capacitor Cf = 1µF=10–6 farad,
Feedback resistance Rf = 40kΩ = 40 ×103Ω (a) 2 sin (100πt) (b) sin (100 πt)
Time constant τ = RC (c) sin (200πt) (d) 0.5 sin (100πt)
= 10–6×40×103 ISRO Scientist Engg.-2018

Ans.(a) Ans. (c) : Q Maximum rate of change in output with
respect to time,
dV0
Slew rate = = 5V / µs
dt max
Q Given output = 1V peak = Vp
So, Slew rate = ( Vp ) × 2πf m =

dV0
dt
5 × 10 +6 = 1 × 2 × 3.14 × f m
Q op-amp output voltage
−1 5 × 106
RC ∫
V0A = Vi dt fm = = 0.79617 ×106
6.28
−1 f m = 796.18kHz
sin (100πt )
100 × 10−12 ∫
=
32. For the circuit given below, the voltage V0
1  −1 
=− −12 
× cos (100π ) t  across the op-amp output is :
100 × 10 100π 
1
V0A = cos (100π ) t
100 × 10−12 × 100π
d
V0 = − RC ( V0A )
dt
d 1 
= −200 × 10−12  −12
cos (100π ) t 
dt 100 × 10 × 100π 
(a) –9Vi (b) –3Vi
−200 × 10−12
=  − sin (100π ) t.100π  (c) –11Vi (d) 9Vi
100 × 10−12 × 100π  ISRO Scientist Engg.-2013
= −2  − sin (100π ) t  Ans. (c) :
V0 = 2sin (100π ) t
30. The circuit is with an ideal operational
amplifier with ±10 V supply. The output
voltage is:
Q ( − ve ) negative feedback, VA = 0
(a) –200 mV (b) –400 mV So, nodal analysis at point A,
(c) –600 mV (d) –300 mV VA − Vi VA − VB
+ =0
ISRO Scientist Engg. -2015 10 50
Ans. (b) : Given, Ideal op-amp, AOL= ∞, Vid = 0 , V = −5V …………………………..(i)
B i
V− = V+ virtual ground And nodal analysis at point B,
Applying KCL at inverting terminal of op-amp, VB − V0 VB VB − VA
+ + =0
20 − 0 40 − 0 0 − Vo 10 10 50
+ =
1 2 10 5 ( VB − V0 ) + 5VB + VB − VA = 0
−Vo
20 + 20 = 11VB = 5V0
10
Vo = –400 mV 5
VB = V0 …………………..(ii)
31. Output of an Op-amp is 1V peak, and slew rate 11
is 5V/µs. The maximum frequency of input From equation (i) and (ii)
sinusoidal signal that can be reproduced is : 5
(a) 398 Hz (b) 796 Hz V0 = −5Vi
11
(c) 796 kHz (d) 398 kHz
V0 = −11Vi
33. Given the output for the following non- (a) 2 VS (b) –2VS
inverting summing amplifier, the relation (c) 3VS (d) –3VS
between Rf and R in the circuit is : Nagaland PSC CTSE (Degree)-2016, Paper-II
Ans. (c) :
By virtual concept:- V+ = V−
(a) Rf = R (b) Rf = 4R
(c) Rf = 2R (d) Rf = R/2 Apply KCL at virtual node:-
ISRO Scientist Engg.-2013 VS VS − V0
+ =0
Ans. (a) : R 2R
2VS + VS – V0 = 0
3Vs − V0 = 0
V0 = 3Vs
35. The value of C required for sinusoidal
oscillation of frequency = 2 kHz in the given
circuit is
Q Nodal analysis at node A,

VA − V1 VA − V2 VA − V3 VA − V4
+ + + =0
R R R R
V1 + V2 + V3 + V4 4VA
=
R R (a) 1/(2π) µF (b) 1/ (4π) µF
And nodal analysis at node B, (c) 1/π µF (d) None of these
VR ISRO Scientist Engg. -2020
VB = 0
R + Rf Ans. (d) :
Q Ideal op-amp
VA = VB Virtual ground
V1 + V2 + V3 + V4 4V0
So, =
R R + Rf
 V1 + V2 + V3 + V4 
Q Given V0 = 
 2 
2V0 4V0 Given, Rf = 1.9 kΩ, Ri = 1 kΩ
= Condition – Wein bridge circuit must be equal to or
R R + Rf
greater than 3, for sinusoidal oscillation.
1 2 Av ≥ 3
=
R R + Rf
V0 R 1.9
R + R f = 2R ∴ = 1+ f = 1+ (non-inverting terminal)
Vin Ri 1
Rf = R
Vout
34. In the ideal Op-amp circuit shown, V0 is = 2.9
Vin
Therefore, voltage gain less than 3. So, it does not
satisfy the above condition
36. In order to ensure that the output voltage of an
op-amp is zero, when both its inputs are
grounded
(a) Internal negative feedback is used In negative half cycle Z1 will be open and Z2 will be
(b) An external offset balancing circuit is used at short.
the input terminals Therefore, the output of the circuit is same as input and
(c) The currents incident at the output node are inverted.
carefully designed 38. Assume that Vi = 2V; R3 = 10Ω; β of Q1 = 50;
(d) The totem-pole output transistors are VCC = 15V. Find Iout
designed to have exactly equal cut in voltages
Ans. (b) : Given,
Q Output voltage of an op-amp V0 = 0
And both inputs are grounded,
(a) 3.92 mA (b) 4mA

(c) 6.84 mA (d) 2.8 mA
In case of when op-amp both inputs voltage, V1 and Ans. (a) : Given,
V2 equal then the voltage V0 = 0. VCC = 15 V
An external offset balancing circuit is used at the Vi = 2V
input terminals. R3 = 10Ω
37. What is the output waveform V0 for a β = 50
sinusoidal input of peak-peak amplitude of 4V.
Assume that Z1 and Z2 are two identical Zener
diodes of 4.7V, and R1=10 kΩ and R2= 20kΩ c
(a) Same as input

(b) Sinusoidal waveform with 5.4V peak
(c) Sinusoidal waveform clamped to +/-4.7V
(d) Sinusoidal waveform clamped to +/-5.4V Vi
IE =
ISRO Scientist Engg.-2010 R3
Ans. (a) : 2
IE = = 0.2A
10
I E = I B (1 + β)
0.2
IB =
51
I B = 3.921mA (Q I B = Iout )
39. In an inverting OP-AMP, the input bias
current is -1µA, and the input and the feedback
resistances are both 1 MΩ. What will be the
Given, output voltage for an input voltage of 2.5V?
V0 for a sinusoidal input of peak –peak amplitude = 4V (a) –2.5 V (b) –3.0V
R1 = 10kΩ (c) –3.5V (d) 4.0V
R2 = 20 kΩ ISRO Scientist Engg.-2010
And Z1 and Z2 are two identical zener diode voltage Ans. (c) : Given, Vi = 2.5V
= 4.7V
−R f
In positive half cycle one zener diode Z1 will be forward V0 = Vin + Ib R f
bias that is short and Z2 will be open and, Ri

−1 ×106 42.
If d.c. supply of 10V is fed to a differentiating
V0 = × 2.5 + (−1× 10−6 × 106 × 1) circuit, then output will be______
106 (a) 20V (b) 10V
V0 = −2.5 − 1 (c) 0V (d) None of the above
V0 = −3.5V Nagaland PSC (CTSE) Diploma-2017, Paper II
40. What would be the output of the following Ans. (c) :
circuit, if a positive going unipolar pulse with
an amplitude greater than Vref, is applied at the
input?
dVi
V0 ( t ) = −RC
(a) Vo will go high momentarily and return to dt
low if d.c. supply of 10V.
(b) Vo will go low momentarily and return to d
Then V0 (t) = − RC (10 )
high dt
(c) Vo will go high and remain high = 0V
(d) Vo will not change its previous state 43. What is PSRR value of an ideal op-amp?
ISRO Scientist Engg.-2010 (a) Zero (b) Unity
Ans. (c) : (c) Infinite (d) Unpredictable
Ans. (a) : If the supply of an op-amp changes, its output
should not, but it typically does. If supply voltage
change X volt and output change Y volt then
X
PSRR =
Y
The dimensionless ratio is generally called the power
When Vin is applied at positive terminal diode will be supply rejection ratio (PSRR). An ideal value of PSRR
forward bias and Vin > Vref (D1 as a shorted) in op-amp is zero.
Then, Vo will go high and remain high. 44. In differential-mode,………….
(a) Opposite polarity signals are applied to the
41. If the input to a differentiating circuit is a saw-
inputs
tooth wave, then output will be______
(b) The gain is one
(a) Square (b) Triangular
(c) The outputs are of different amplitudes
(c) Sine (d) Rectangular
(d) Only one supply voltage is used
Ans. (d) : Ans. (a) : In differential mode opposite polarity signals
are applied to the inputs.
45. The output of a particular Op-amp increases 8
V in 12 µs. The slew rate is……….
(a) 90 V/µs (b) 0.67 V/µs
(c) 1.5 V/µs (d) None of these
Ans. (b) : Given,
dV ( t ) V = 8volt, t = 12µsec
V0 ( t ) = −RC  dV 
dt Slew Rate =  
The output of the circuit depends on the differentiation  dt  m
of the input voltage. 8 2
If we give a sawtooth wave as input (Vi) to this circuit it SR = = V / µs
12 3
will give a rectangular wave as output after
differentiating the input. SR = 0.67 V / µs

46. The input impedance of a differential amplifier Ans. (d) : The output of an ideal differential amplifier,
equals re' times……… when same input signals are applied at input will be
zero, because difference of input will zero.
(a) β (b) RE
(c) RC (d) 2β 51. What is the feedback factor of the circuit
Ans. (d) : Differential input resistance is define as the
equivalent resistance that would to measured at either
terminal with the other terminal grounded.
Ri = 2β
47. A common-mode signal is applied to………
(a) the non inverting input
(b) the inverting input
(c) both inputs 9 9
(a) (b)
(d) top of the tail resistor 100 10
Nagaland PSC (CTSE) Diploma-2017, Paper II 1 1
(c) (d)
Mizoram PSC AE/SDO-2012, Paper-I 9 100
Ans. (c) : As the common mode is known when both TNPSC AE - 2018
signals are same and it is applied to both input 1
terminals. If the transistor are perfectly matched the Ans. (d) : Feedback factor β =
output will be zero otherwise there exists some output R1 + R 2
voltage. In an ideal op-amp the voltage gain for the R 1 & R 2 = Feedback resistor.
common mode signal is zero. 1
β=
48. The common-mode voltage gain is…….. 10 + 90
(a) smaller than differential voltage gain
1
(b) equal to differential voltage gain β=
(c) greater than differential voltage gain 100
(d) none of the above 52. The low frequency gain of LPF shown is
Ans. (a) : We know that-
DifferentialGain
CMRR =
Common modeGain
CMRR > 1
Ad
>1 (a) 10 dB (b) 20 dB
Ac
(c) 30 dB (d) 40 dB
Ad > A c TNPSC AE - 2018
49. The input stage of an Op-amp is usually a…….. Ans. (d) : At low frequency f = 0 and Xc = ∞
(a) differential amplifier V
Gain = o = 100
(b) class B push-pull amplifier Vi
(c) CE amplifier
(d) swamped amplifier V
For Low frequency ⇒ Gain = 20log o = 20log100
Nagaland PSC (CTSE) Diploma-2017, Paper II Vi
Ans. (a) : The op-amp has two input terminals. The = 20 × 2
input voltage given to both the input terminals. The
Gain = 40 dB
differences of the input voltage will be amplified.
Therefore the input stage of an op-amp is usually a 53. The circuit shown in figure is a
differential amplifier.
50. The output of an ideal differential amplifier,
when same input signals are applied at the
inputs is
(a) Dependent on its CMRR
(b) Dependent on its voltage gain (a) Low-pass filter (b) High-pass filter
(c) Determined by its symmetry (c) Band-pass filter (d) Band-reject filter
(d) Zero RPSC ACF & FRO-23.02.2021
TNPSC AE - 2018 ISRO Scientist Engg.-2008
Ans. (a) : The circuit shown in figure is a second order Ans. (c) :
low pass filter.
• At low frequencies (s → 0) capacitor act as open
circuit.
1 1
Q XC = =
jωC sC
1
XC =
sC When Vs is -1 volt then diode will be off
XC = ∞
Apply KCL at node A,
• At high frequencies capacitor act as short circuit
VS − 0 0 − V01
1 =
Q XC = 1 1
jωC
−1 = −V01
1
XC = =0
∞×C V01 = 1 V
The circuit represent → Low pass filter. When VS = + 1 volt then diode will on
54. The OP-AMP integrator circuit contains
(a) Resistor in the feedback path
(b) Capacitor in the feedback path
(c) Inductor in the feedback path
(d) Short circuit in the feedback path
Ans. (b) : The OP-AMP integrator circuit contains Apply KCL at node A,
capacitor in the feedback path.
1 − 0 0 − V02
= ⇒ V02 = −0.5V
1 0.5
V01 + V02 = 1 − 0.5 = 0.5V
57. In the circuit shown below the op-amp is ideal.
Ideal integrator act as a low pass filter. The voltage gain V0/Vi is
55. Which converters uses integrating Op-amp
(a) Dual slope A/D converter
(b) Parallel A/D converter
(c) Single slope A/D converter
(d) None of these
(a) –2 (b) 2
Ans. (a) : A dual slope A/D converter produce an
equivalent digital output for a corresponding analog (c) –1 (d) 1
input. It uses a integrator clock generator, control logic UPPCL AE- 31.12.2018
and a counter. Ans. (a) : From Virtual ground concept – at terminal of
56. In the circuit shown below assume that diodes op-amp voltage will be zero.
and op-amp are ideal. Suppose that V01 is the
output voltage when input voltage is Vs = –1.0
V and V02 is the output voltage when input
voltage is Vs = +1.0 V, then the value of V01 +
V02 is
Apply virtual ground equation

Vi − 0 0 − Vo
=
1 2
Vo
= −2
Vi
(a) 2.0 V (b) –0.5 V 58. Assume that op-amp in the circuit shown below
(c) 0.5 V (d) 0.0 V is ideal. Value of the transfer function
UPPCL AE- 31.12.2018 V2(s)/V1(s) evaluated at s = j is
On putting s = j
( )
2V1 ( s ) = V2 ( s )  2 −1 + 2 2 j + 2 − 2 2j − 2 
 
= V2 ( s )  −2 + 4 2 j + 4 − 2 2 j − 2 
2V1 ( s ) = V2 ( s )  −4 + 4 + 2 2 j
2V1 ( s ) = 2 2 jV2 ( s )
(a) −1 (b) − j V2 ( s ) 1 j −j
= × =
2 2 V1 ( s ) 2j j 2
(c) j (d) 1
2 2 V2 ( s )
= − j/ 2
UPPCL AE- 31.12.2018 V1 ( s )
Ans. (b) : Draw circuit in s-domain– 59. The input impedance and voltage gain of the
given circuit in figure below is-
KCL apply at node (3), (a) 2 kΩ, 2 (b) 2 kΩ, 1

V1 ( s ) − V3 V3 − V2 ( s ) V3 − V2 ( s ) (c) 1/2kΩ, 2 (d) 1kΩ, 1
= + UPPCL AE-16.11.2013
1/ 2 1/ C1s 1/ 2
Ans. (d) :
2 ( V1 ( s ) ) − 2V3 = C1sV3 − C1sV2 ( s ) + 2V3 − 2V2 ( s )
–––––(1)
KCL apply at node (2),
V3 − V2 ( s ) V2 ( s )
=
1/ 2 1/ C 2s
2V3 − 2V2 ( s ) = C 2sV2 ( s )
2V3 = 2V2 ( s ) + C 2sV2 ( s )
In ideal open Av = ∞ ,
sV2 ( s ) + 2V2 ( s )
V3 = ( C2 = 1F ) V+ = V– (virtual ground condition)
2 Apply virtual concept at inverting terminal
From eq. (1) Vin − 0 0 − Vout
=
2V1 ( s ) = 2V3 + C1sV3 − C1sV2 ( s ) + 2V3 − 2V2 ( s ) 1 1
2V1 ( s ) = V3  2 + 2 + C1s  − C1sV2 − 2V2 ( s ) Vout
Vin = −Vout ⇒ = −1
On putting the value of V3 and C1 = 2F Vin
sV2 ( s ) + 2V2 ( s ) and input resistance Ri = 1kΩ
2V1 ( s ) =
2
(2 2 + 2s ) 60. Find output voltage Vo in the circuit below:
−2sV2 ( s ) − 2V2 ( s )
 s + 2  
2V1 ( s ) = V2 ( s ) 
 2 
(
 2 2 + 2s − 2s − 2 )

( )( )
 s + 2 2 2 + s − 2 2s − 2 
= V2 ( s )  
 2  (a) –1.1 V (b) +1.1 V
  (c) 1.0 V (d) 10 V
 (2
)
2V1 ( s ) = V2 ( s )  2 s + 2 2s + 2 − 2 2s − 2 

IES-2007
Ans. (b) : (a) 0V (b) ∞
(c) 400V (d) ± 400V
TNPSC AE-2008
Ans. (a) : Input offset voltage is the difference in input
voltage that exist between input terminal of an op-amp
without any external input & force the output voltage to
zero.
65. An OP-AMP has a common made gain of 0.01
Applying voltage division rule at point A: and a differential made gain of 105. The value
 100  of the CMRR will be
V1 = 1 mV × 1 +  =11mV (a) 105 (b) 107
 10  –3
(c) 10 (d) 103
Applying voltage division rule at point B:
 470  MPPSC Forest Service Exam.-2014
V2 = 11 mV ×  −  = −110 mV
 47  Ans. (b) : Given, Ad = 105 , Ac = 0.01
Applying voltage division rule at point C: A
 22  CMRR = d
V0 = −110mV  −  = +1.1V
Ac
 2.2 
105
61. The voltage that is to be applied between the CMRR =
two input terminals for making zero output 0.01
voltage is CMRR = 107
(a) Output offset voltage (b) Threshold voltage 66. An inverting amplifier is made using ideal OP-
(c) Input offset voltage (d) None of the above AMP. Why are the two input terminals of the
TNPSC AE-2014 OP-AMP at the same potential?
Ans. (c) : Input offset voltage is the voltage which must (a) CMRR is infinity
be applied between input terminals to make amplifier (b) The input impedance is infinity
output voltage (V0 = 0). (c) The open loop gain of the OP-AMP is infinity
62. An operation amplifier having a slew rate of (d) Both (CMRR is infinity) and (The input
62.8 v/µsec, is connected in a voltage follower impedance is infinity)
configuration. If the maximum amplitude of Mizoram PSC Jr. Grade-2018, Paper-II
the input sinusoid is 10 V, then the maximum MPPSC Forest Service Exam.-2014
frequency at which the output is undistorted.
(a) 1 MHz (b) 6.28 MHz Ans. (d) : For ideal operational amplifier– R in = ∞
(c) 10 MHz (d) 62.8 MHz and CMRR= ∞ Hence virtual ground concept is
TNPSC AE-2013 applicable which states that same voltage at both
Ans. (a) :Given value, Slew rate = 62.8 V/µsec , terminal of amplifier.
Vm = 10V 67. The slew rate of an operational amplifier is 0.8
∂V0 volts per micro second. What will be the
Slew rate = = 2πfmVm maximum amplitude of undistracted output
∂Vt
sine wave that the OP-AMP can produce at 40
62.8 × 106 = 6.28 × 10 × fm kHz?
f m = 1MHz (a) 3.18 volts (b) 4 volts
63. Op-Amp circuit consists of first two stages, (c) 20 volts (d) 2.54 volts
which are MPPSC Forest Service Exam.-2014
(a) Cascade differential amplifier Ans. (a) : Given value,
(b) Buffer amplifier S.R. = 0.8 V/µ sec f = 40 kHz
(c) Driver S.R. = 2π × f × Vm
(d) Emitter follower
0.8
TNPSC AE-2013 Vm =
Ans. (a) : The Op-Amp circuit consists of two stages 2π × 40kHz ×10−6
which are cascaded differential amplifier. The first stage Vm = 3.18 V
providing high gain and the second stage providing 68. In a log amplifier the input is 'a'. The output
additional voltage gain and large output signal swing. will be proportional to
64. A 741 OP-AMP has an open loop gain 200,000. (a) log a (b) 2.3 log a
The output offset voltage is 2 mV. If the input (c) log 20 a (d) None of these
terminals are shorted, the output voltage is MPPSC Forest Service Exam.-2014

Ans. (a) : The logarithm amplifier gives an output Ans. (a) : For Integrated circuit →
voltage which is proportional to the log of applied input −1
voltage,
Vout = log (Vin)
V0 =
RC ∫Vi dt
Vin = a
Vout = log a
69. An inverting operational amplifier has
Rf = 2MΩ and R1 = 2kΩ. Its scale factor is
(symbols/notations carry their usual meaning) If the capacitor in an RC integrator shorts, the output is
(a) 1000 (b) 100 at ground.
(c) -100 (d) -1000 75. The frequency compensation is used in op-amp
RPSC LECTURER-10.01.2016 to increase its
Ans. (d) : Given , Rf = 2MΩ, R1 = 2kΩ (a) Input impedance (b) Output impedance
V0 −2 × 106 (c) Gain (d) Bandwidth
= = −1000 Nagaland PSC CTSE (Diploma)-2018, Paper-I
Vi 2 × 103
GATE-1994
–ve sign indicates polarity of output signal is reversed Ans. (c) : The frequency compensation is used in op-
to that of input signal. amp to increase its gain.
70. Logarithmic amplifiers are used in 76. An op-amp is used as a zero-crossing detector.
(a) Adders (b) Dividers If the maximum output voltage is ± 15 Volt p-p
(c) Multipliers (d) All of the above and the slew rate is 10 V/µsec, then the
Nagaland PSC CTSE (Degree)-2016, Paper-II maximum frequency will be
Ans. (d) : Logarithmic amplifiers are used in adders, (a) 106 Hz (b) 10.6 Hz
multipliers, subtractions. (c) 106 kHz (d) 10.6 kHz
71. The number of operational amplifiers required Nagaland PSC CTSE (Diploma)-2018, Paper-I
to design an electronic PID controller is : Ans. (c) : Given, V0 = 15V,
(a) 1 (b) 2
S.R = 10 V/µsec.
(c) 3 (d) 4
dV0
Nagaland PSC CTSE (Degree)-2016, Paper-II slew rate = = 2πVf V/µsec
dt
Ans. (a) : The no. of op-amp in a PID controller = 1
dV
72. How many stages are involved in bipolar op- = 10V / µ sec
amp? dt
(a) 2 (b) 3 2π f V0 = 10V/µsec
(c) 4 (d) 6 10 × 106
f=
Nagaland PSC CTSE (Diploma)-2017, Paper-I 2π ×15
Ans. (b) : The bipolar op-amp consists of three stages- f = 106 kHz
Input differential amplifier 77. A differentiator circuit is also a
Gain stage (a) High pass circuit (b) Low pass circuit
Output stage (c) Band pass circuit (d) Band reject circuit
73. In op-amps, which type of noise occurs due to Nagaland PSC CTSE (Diploma)-2018, Paper-I
discrete flow of current in the device? Ans. (a) : In electronics, a differentiator is a circuit that
(a) Shot noise (b) Burst noise is designed such that the output of the circuit is
(c) Thermal noise (d) Flicker noise approximately directly proportional to the rate of
Nagaland PSC CTSE (Diploma)-2017, Paper-I change of the input. The differentiator circuit is a high
Ans. (a) : In op-amp, shot noise occurs due to discrete pass filter.
flow of current in the device. 78. An op-amp having a slew-rate specification of 1
74. If the capacitor in an RC integrator shorts, the V/µs has been connected in the voltage follower
output configuration. The input is a unit step of
(a) is at ground voltage applied at instant t = 0. What is the
(b) would measure the same as the input output magnitude at t = 500 ns?
(c) would measure zero volts (a) 1 V (b) 0 V
(d) none of the above (c) 0.5 V (d) 2.5 V
Nagaland PSC CTSE (Diploma)-2018, Paper-I Mizoram PSC Jr. Grade -2018, Paper-II
Ans. (c) : Given, Slew rate = 1V/µsec, t= 500ns Ans. (c) : Given data -
 dV  Bandwidth = 1 MHz
S.R. =  o  Closed loop gain ACL = 200 V/mV
 dt  max
BW
1×106 =
dVo ∵ fC =
500 × 10−9 A CL
( Vo )m = 1× 500 × 10−3 ∴ Put the value, the cut off frequency
( Vo )m = 0.5Volt 1×106
fC =
200 × 103
79. In an op-amp, when the input signal drives the
= 5 Hz
output at a rate of voltage change greater than
the slew rate, then the resulting signal 84. If the bias current in the IC-741 op-amp is IQ =
(a) is enhanced 19 µA and the internal frequency compensation
(b) is clipped capacitor C1 = 30pF, the slew rate of the op-
(c) is unaffected amp will be nearly
(d) remains the same, but with 900 phase (a) 1.58 V/µs (b) 1.26 V/µs
difference (c) 0.93 V/µs (d) 0.63 V/µs
Mizoram PSC IOLM-2010, Paper-I IES-2020
Ans. (a) : In an op-amp, when the input signal drives Ans. (d) :
the output at the rate of voltage change greater than dV I
slew rate, the resulting output signal will increase it Slew rate S = 0 = 2πf m Vm =
width. Hence signal is enhanced. dt C
I
80. In ideal op-amp the current through the virtual S=
ground is C
(a) 1 A (b) 10 A ∵ Given value -
(c) Zero (d) infinity IC - 741 op-amp is IQ = 19µA
RPCS Lect.-2011 Internal frequency compensation capacitor C1 = 30 pF
Ans. (c) : In op-amps the term virtual ground means 19 ×10−6
that the voltage at that particular node is almost equal to ∴ S=
ground voltage zero. 30 ×10−12
It is not physically connected to ground. So, in ideal op- = 0.633 × 106 V / s
amp the current through the virtual ground is zero. = 0.63 V/µs
81. An operational amplifier is a 85. In a differential amplifier, there are two sets of
(a) high gain CE amplifier input signals. In first set, V1 = +50 µV and V2 =
(b) cascaded CE amplifier –50µV. and in second set V1 = 1050 µV and V2
(c) high gain direct coupled amplifier = 950 µV. If the common mode rejection ratio
(d) high gain CB amplifier is 100, the percentage difference in the output
RPSC Vice Principal ITI-2016 voltage for the two sets of input signals will be
Ans. (c) : An operation amplifier op-amp is a high gain (a) 10% (b) 15%
direct coupled amplifier with high input resistance and (c) 20% (d) 25%
zero output resistance. IES-2020
82. Gain of an Op-Amp inverting amplifier with an Ans. (a) : Differential amplifier - A differential
input of 0.25 V and output of 17.5 V is amplifier is a type of electronic amplifier the difference
(a) 4.375 (b) 17.75 between two input voltage but suppresses any voltage
(c) 17.25 (d) 70 common to the two input.
Ans. (d) :
V
Gain of an operational amplifier is given by out
Vin
17.5
A0 = = 70
0.25
83. If an op-amp having specified signal bandwidth
(BW) of 1 MHz and closed loop gain ACL = 200 Vout = A V ( V1 − V2 )
V/mV, the cut-off frequency Fc will be where AV = op-amp gain.
(a) 25 Hz (b) 15 Hz
A
(c) 5 Hz (d) 1 Hz ∵ Common-mode rejection ratio (CMRR) = d
IES-2020 Ac

 1 V  Ans. (b) : The switch will be open-
∴ Vo = A d Vid 1 + . c
 CMRR Vid 
Given data -
V1 = +50 µV, V2 = –50 µV
CMRR = 100
Vid = V1 − V2 = 50 − ( −50 ) = 100 µV
1
Vcm = ( V1 + V2 )
2 Apply point A nodal analysis
1 Vi − 0 0 − V0
= 50 + ( −50 )  = 0V =
2 R 2R
 1 0  Vi −V0
∴ V01 = A d ×100 1 + .  =
 100 100  R 2R
V01 = 100 A d µV ................. (i) V0
= −2
And second saturation of input - Vi
V1 = 1050 µV and V2 = 950 µV ∵ Given in this question
Vid = V1 − V2 = 1050 − 950 = 100µV V0
= x = −2 ............. (i)
Vi
1
Vcm = (1050 + 950 ) = 1000 µV Now, switch will be closed then,
2
Vi − 0 0 − V0
 1 1000  =
V02 = A d × 100 1 + × R R
 100 100 
Vi −V0
V02 = 110 A d µV .................... (ii) =
R R
From equation (i) and (2) V0
Percentage difference in the output voltage = −1 ......................(ii)
Vi
V02 − V01 ∴ from equation (i) and (ii),
%V0d = × 100
V01 V0 x
=
110A d − 100A d Vi 2
= ×100
100A d 87. An op-amp is used in a notch filter. The notch
10 frequency is 2 kHz, lower cut-off frequency is
= ×100 = 10% 1.8 kHz and upper cut-off frequency is 2.2 kHz.
100 Then Q of the notch filter.
86. The magnitude of the gain V0/Vi in the (a) 3.5 (b) 4.0
inverting op-amp circuit shown in the figure is (c) 4.5 (d) 5.0
x with switch S open. When switch S is closed, IES-2018
the magnitude of the gain will be Ans. (d) : The bandwidth is defined as the difference in
the upper and lower cut-off frequency.
BW = f upper − f lower
ω0 L X L f
Q= = = r
R R BW
Given value -
fupper = 2.2 kHz, notch frequency = 2 kHz = fr
fLower = 1.8 kHz
x ∴ B.W. = 2.2 – 1.8 = 0.4 kHz
(a) x (b)
2 Then,
2 f 2 kHz
(c) 2x (d) Q= r =
x BW 0.4 kHz
IES-2018 Q = 5

88. In op-amp based inverting amplifier with a Apply KCL at inverting terminal,
gain of 100 and feedback resistance of 47kΩ, V1 − 0 0 − V2
=
the op-amp input offset voltage is 6 mV and 1 15
input bias current is 500 nA. the output offset −V2
voltage due to an input offset voltage and an V1 =
15
input bias current, are
− V2 = 15V1
(a) 300 mV and 23.5 mV
(b) 606 mV and 47.0 mV V2 = −15V1
(c) 300 mV and 47.0 mV Apply KCL at y
(d) 606 mV and 23.5 mV 0 − V2 V2 V2 − V0
IES-2018 = +
15 1 15
Ans. (d) : Output offset voltage (V0)offset due to input −V = 16V − V
2 2 0
offset
−17V2 = −V0
 R 
( V0 )offset = 1 + f  Vio −17 × 15V1 = V0
 Ri 
V
∵ Given value - Gain = 100 Ib = 500 nA −255 = 0
V1
Vio = 6 mV,
Feedback resistance = 47 kΩ V0
= −255
Input bias current = 500 nA V1
Then, 90. If an input impedance of op-amp is finite, then
( V0 )offset = (1 + 100 ) × 6 mV which one of the following statements related to
virtual ground is correct?
= 101 × 6 (a) Virtual ground condition may exist.
= 606 mV (b) Virtual ground condition cannot exit
(V0)offset due to input bias current (c) In case of op-amp, virtual ground condition
( V0 )offset = R f I b always exists.
= 47 kΩ × 500 nA (d) Cannot make a valid declaration
IES-2017
= 23.5 mV
Ans. (b) :
89. What is the gain of the amplifier circuit as
In ideal case,
shown in the figure?
Ri = ∞
AV = ∞
V0 = AvVd
V0 = A v ( V1 − V2 ) V1 = Non- inverting voltage
V0
(a) 255 (b) 31 V1 − V2 = V2 = Inverting voltage
(c) –31 (d) –255 Av
IES-2018 ∵ In ideal case Av = ∞
Ans. (d) : V
V1 − V2 = 0
∞
V1 − V2 = 0
V1 = V2 Virtual ground condition.
∴ Virtual short circuit is valid.
Such that, from the equivalent circuit of op-amp, there
is a drop in Ri and
V1 ≠ V2
So, virtual short circuit not valid.

91. Hysteresis is desirable in a Schmitt-trigger 93. The transient response rise time (unity gain) of
because an op-amp is 0.05µs. The small signal
(a) Energy is to be stored/discharged in parasitic bandwidth is
capacitances (a) 7 kHz (b) 20 kHz
(b) Effect of temperature variations would be (c) 7 MHz (d) 20 MHz
compensated IES-2016
(c) Devices in the circuit should be allowed time Ans. (c) : ∵ Given value,
for saturating and de-saturating transient rise time (tr) = 0.05 µsec.
(d) It would prevent noise from causing false Relation between rise time (tr) and bandwidth
trigging 0.35
IES-2017 B.W. = ......(i)
tr
Ans. (d) : Schmitt trigger - A Schmitt trigger is a
comparator circuit with hysteresis implemented by 0.35
B.W. =
applying positive feedback to the non-inverting input of 0.05 µ sec
a comparator or differential amplifier. 0.35
=
0.05 × 10−6
B.W. = 7 MHz
94. What is the maximum frequency for a sine
wave output voltage of 10 V peak with an op-
amp whose slew rate is 1V/µs.
(a) 15.92 kHz (b) 19.73 kHz
(c) 23.54 kHz (d) 27.36 kHz
IES-2016
Ans. (a) : Given that -
Slew rate = 1V µs
Upper threshold is given -
 dV 
Slew rate =  0  = 2πf max V0 max
 dt  max
Slew rate ×106
f max =
2πVm
1×106
f max = = 15.92 kHz
2π × 10
Vupper =
Vsat R 1 f max = 15.92 kHz
R1 + R 2 95. An FET-input IC operational amplifier has an
Lower threshold open loop differential gain of 1,00,000 and a
−Vsat R1 common mode gain of 25. Then the common
VL = mode rejection ratio is
R1 + R 2 (a) 46 dB (b) 72 dB
VH = VU − VL (c) 106 dB (d) 144 dB
IES-2015
So, as long as, noise amplitude is in between VLower and Ans. (b) : Given value -
Vupper, the triggering of the circuit does not takes place Ad = 100000
and this prevents noise. Ac = 25
92. In an op-amp, if the feedback voltage is ∴ Common mode rejection ratio
reduced by connecting a voltage divider at the
A 100000
output, which of the following will happen? CMRR = d =
1. Input impedance increases Ac 25
2. Output impedance reduces = 4000
3. Overall gain increases |CMRR|dB = 20 log 4000
(a) 1 only (b) 2 only = 20× 3.60
(c) 3 only (d) 1, 2 and 3 = 72 dB
IES-2019 96. If the inverting input terminal of an
operational amplifier is grounded and a
Ans. (c) : If feedback voltage are reduced by connecting sinusoidal voltage waveform is applied at the
the voltage divider at the output then overall voltage non-inverting input terminal, the output will
gain has increased. be:
(a) Square wave 98. The differential gain of op-amp is 4000 and
(b) Triangular wave value of CMRR is 150. Its output voltage, when
(c) Half-wave rectified sine wave the two input voltages are 200 µ V and 160 µV
(d) full-wave rectified sine wave respectively, will be
IES-2017, 2015 (a) 16 V (b) 164.8 mV
(c) 64 mV (d) 76 mV
Ans. (a) : In an op-amp-
IES-2014
Open loop gain A = ∞ (Ideal case)
Inverting terminal voltage = 0V (according to the given Ans. (b) :
op-amp) Given value –
So, If Vin > 0V that is output saturate (+Vsat). A d = 4000 V1 = 200µV
If Vin < 0V, then output is saturated (–Vsat). CMRR = 150 V2 = 160µV
Note - In open loop it acts as a comparator. Q CMRR for differential Amplifier –
Ad
CMRR =
Ac
4000
150 =
Ac
A c = 4000 /150
= 26.66
Q Differential voltage Vd = V1 − V2
Vd = 200 − 160 = 40µV
So, the output will be square wave for the given Q common-mode input of the op-Amp
sinusoidal input. V + V2
97. An op-amp has the following open loop Vc = 1
2
parameters Zin = 300 kΩ, Zout = 100 Ω, A =
200 + 160 360
50,000. The low frequency system input and Vc = =
output impedance, when closed loop gain is set 2 2
to 100, are = 180 µV
(a) 0.6 Ω and 50 k Ω ∴ Output voltage V0 = A d Vd + A c Vc
(b) 150 M Ω and 0.2 Ω
(c) Same as in open loop V0 = 4000 × 40µV + 26.66 × 180µV
−6
(d) None of the above = (160000 + 4798.8 ) ×10
IES-2014 = 164798.8 × 10−6
Ans. (b) : = 164.798mV
Q Given value. 99. An amplifier using op-amp with a slew rate SR
Zin = 300k Ω , = 1 V/µsec has a gain of 40 dB. If this amplifier
Zout = 100 Ω , has to faithfully amplify sinusoidal signals from
A = 50000 10 to 20 kHz, without introducing any slew-rate
AcL = 100 induced distortion, then the input signal level
A must not exceed.
Q A CL = (a) 795 mV (b) 395 mV
1 + Aβ
(c) 79.5 mV (d) 39.5 mV
50000
1 + Aβ = = 500 GATE-2002
100 Nagaland PSC CTSE (Degree)-2017, Paper-II
Q The input for an op-Amp increase with feedback IES-2014
Zif = Zi (1 + Aβ ) Ans. (c) : Given that,
Zif = 300kΩ × 500 Slew rate = 1V / µ sec
f m = 20kHz
Zif = 150MΩ
Q after feedback output impedance 20 log10 A v = 40dB
Z0 100 A v = 100
Zof = =
1 + Aβ 500  dV 
Q slew rate =  0  = A v Vm 2πf m V/µsec
Zof = 0.2Ω  dt  max

Q Slew rate = A v Vm 2πf m Vo(s) 1
=
1V / µ sec = 100 × Vm × 2 × 3.14 × 20 ×10
3
Vi(s) sR i C
10 6 f=0 (at low freqeuncy)
Vm = V0 ( s )
314 × 20 × 2 ×10 3
=∞
= 79.61775 × 10 −3 Vi ( s )
Vm = 79.5mV At low frequency, gain = ∞ and the op-amp saturates.
Thus, Rf is used to prevent saturation.
100. A 5 mV, 1 kHz sinusoidal signal is applied to
the input of an op-amp integrator for which R 102. What is the output voltage for the below
= 100 kΩ and C = 1µF. the output voltage is: circuit?
1
(a) cos(2000πt − 1) (b) cos(2000πt − 1)
40π
−1
(c) cos(2000πt − 1) (d) − cos(2000πt − 1)
40π
IES-2013
f = 1kHz, R = 100kΩ,C = 1µF (a) –4.8V (b) +1.2V
(c) –2.4V (d) +2.4V
Let, Vi = 5mV sin ( ωt − 1) (Q ω = 2πf )
IES-2011
Vi = 5 × 10−3 sin ( 2π× 103 t − 1) Ans. (c) :
In the integrator circuit –

−1 t
V0 ( t ) = v i ( t ) dt
RC ∫0
−1 Q given value –
5 × 10−3 sin ( 2π×103 t − 1) dt
t
V0 ( t ) = −6 ∫0 V1 = 40mV V2 = 20mV
100 × 10 × 10
3
1 Apply KCL at node A

V0 ( t ) = cos ( 2000πt − 1) mV
40π VA − V0 VA − V1 VA − V2
+ + =0
101. In the circuit shown, the need of the resistor RF 470 47 4.7
is Q VA = 0 (Virtual ground).
0 − V0 0 − 40 0 − 20
+ + =0
470 47 4.7
V 20 40 200 40
− 0 = + = +
470 4.7 47 47 47
V0 240mV
− =
(a) To increase the overall gain 470kΩ 47kΩ
(b) To stabilize the circuit V0 = −2.4 volt
(c) To increase input impedance 103. The output of the below op-amp circuit is
(d) To prevent saturation
IES-2012
Ans. (d) : When resistance (Rf) is not present
Ri
(a) –0.75 volts (b) –cosωt volts

(c) –4 cosωt volts (d) 16 volts
IES-2010
Ans. (c) : Ans. (b) : Two type applications of op-amp linear and
non-linear.
1. Linear application of op-amp-
Addition
Substration
I to I or V to V converter
I to V converter
Instrumentation amplifier.
Q According to circuit diagram –
2. Non-linear application of op-amp-
By virtual ground,
Clipper Clamper Limiter circuit
V1 = V2
Comparator Peak detector Log amplifier
Then, Rectifier
R
V2 = ( 4 − 2cos ωt ) + R ( −4 ) 106. Consider the following statements :
2R 2R Dominant-pole frequency compensation in an
1 1
= ( 4 − 2 cos ωt ) + × −4 op-amp :
2 2 1. Increases the slew-rate of the op-amp
= 2 − cos ωt − 2 2. Increase the stability of the op-amp
V2 = − cos ωt 3. Reduce the bandwidth of the op-amp
Therefore, output voltage, 4. Reduces the CMRR of the op-amp
 3R  ( Which of the statements given above are
∴ Vout = 1 +  − cos ωt ) correct?
 R 
Vout = −4cos ωt (a) 1 and 3 only (b) 1, 2 and 4
104. Consider the following statements regarding an IES-2008
op-amp :
Ans. (c) : Dominant pole compensation is an external
1. All types of negative feedback reduce
compensation technique used in amplifiers and
nonlinear distortion.
especially in amplifiers employing negative feedback. It
2. All types of negative feedback reduce the usually has two primary goals. To avoid the
output offset voltage. unintentional creation of positive feedback, which will
3. Non-inverting (current and voltage) feedback cause the amplifier to oscillate and to control overshoot.
increases the input impedance. It is also used extensively to improve the bandwidth of
4. Inverting (current and voltage) feedback system. Increases the slew rate, improve the CMRR and
decreases input impedance. overall improve the stability.
Which of the above statements is/are correct? 107. Which one of the following causes phase shift
(a) 1 only (b) 2 and 3 only through an op-amp?
(c) 2 and 4 only (d) 1, 2, 3 and 4 (a) Internal RC circuits
IES-2009 (b) External RC circuits
Ans. (d) : Op-amp characteristics- All types of (c) Gain roll off the internal transistor
negative feedback reduces in non linear distortion and (d) Negative feedback
reduce output offset voltage. Non-inverting (like current IES-2007
and voltage) feedback increases the input impedance Ans. (c) : Phase shift occurs in op-amp due to gain roll
and decreased inverting input impendence. off of the internal transistor.
105. Which of the following are the non-linear 108.
applications of op-amp?
1. Current-to-voltage converter
2. Comparator
3. Peak detector
4. Limiter
Select the correct answer from the codes
given below :
(a) 1, 2 and 3 (b) 2, 3 and 4 What is the output voltage V0 of the above
(c) 1, 3 and 4 (d) 1, 2 and 4 circuit?
Nagaland PSC CTSE (Diploma)-2017, Paper-II (a) –11 V (b) 6 V
RPSC Lect.-2011 (c) 11 V (d) –6 V
IES-2009 IES-2007
Ans. (a) : From the circuit-
Vy = Vx − i x Z2
= 0 − I1Z2 ...........(i)
Again,
Vy = 0 + I0 Z1 ...........(ii)
From equation (i) and (ii),
− I1Z2 = I0 Z1
According to circuit diagram,
Point A to B current (I), I0 Z 
∴ = − 2 
2 −1 I1  Z1 
I= = 0.5mA.
2kΩ 110. Consider the following statements :
Q Point C, apply KCL at node C, 1. Stray capacitance at the input terminal of an
V1 = 2 + 10I = 7V. op-amp effectively introduces an additional
Apply KCL at node D, phase lag network in feedback loop.
V2 = 1 − 10I = −4V 2. Stray capacitance depends upon the value of
∴ At the point E, resistor used in feedback.
4.7 3. Low value of resistance has higher effects on
V3 = × V2 stray capacitance.
4.7 + 4.7
4.7 1 4. High value of resistances has higher effects
= × V2 = × −4 on stray capacitance.
9.4 2
= −2 Volt.
correct?
Therefore, output voltage in circuit,
(a) 1, 2 and 3 (b) 2,3 and 4
V1 − V3 V3 − V0
= (c) 1, 3 and 4 (d) 1,2 and 4
4.7 4.7 IES-2006
V0 = 2V3 − V1
Ans. (a) :
= 2 × ( −2 ) − 7
V0 = −11 Volt
109. In the circuit shown below, what is the value of
transfer function I0/I1?
Stray capacitance effects (Cs) at the input terminal of an

operational amplifier effectively introduces an
additional phase-lag network in the feedback loop. Thus
Z2 Z1 making the Op-amp circuit unstable.
(a) − (b) −
Z1 Z2 With low resistances, small stray capacitances normally
have little effect on the circuit stability.
Z   Z1 
(c) 1 +  2  (d) 1 +   111. An I.C. operational amplifier has a typical
 Z1   Z2  open loop gain of 1200 and the common mode
IES-2006 rejection of 55 dB. What is the common mode
Ans. (a) : rejection ratio (CMRR)?
(a) 550 (b) 560
(c) 570 (d) 580
IES-2006
Ans. (b) :
Given data–
Open loop gain ( A OL ) = 1200
CMRR = 55 dB

20log10 ( CMRR ) = 55 From virtual ground concept-
55 V + = V − = V1
log10 ( CMRR ) =
20 Apply KCL at inverting terminal–
CMRR = 10 55 20 I1 = I 2 + I3
CMRR = 562.34 Q I3 = 0A
CMRR ≈ 560 I1 = I2
112. Pulses of definite width can be obtained from Vs − V1 V1 − V0
irregular shaped pulses : = ⇒ Vs − V1 = V1 − V0
(a) When it is given as input to a monostable R1 R1
multivibrator Apply KCL at Non-inverting terminal voltage.
(b) When it is given as triggering signal to a I 4 = I5 + I 6 + I L
bistable multivibrator
(c) When it is used as input to a Schmitt-trigger Q I6 = 0A
(d) When it is used as input to a pulse V0 − V1 V1
transformer = + IL
R2 R2
IES-2005
Ans. (c) : Schmitt trigger works on the principle of V0 − V1 V1 + R 2 ⋅ I L
=
positive feedback. Here are two special case where R2 R2
output is triggered two level– From eqn (i)
(i) UTP (upper threshold point) V1 − Vs = V1 + R ⋅ I L
(ii) LTP (lower threshold point)
Above both level Schmitt trigger switches to saturation −Vs
IL =
level. R2
thus, Schmitt trigger can be used to generate pulses of 114. For a given op-amp, CMRR = 105 and
definite width. differential gain = 105. What is the common
113. For the circuit given below, what is IL equal mode gain of the op-amp?
(a) 1010 (b) 2 × 105
5
(c) 10 (d) 1
IES-2005
Ans. (d) : We know –
A
CMRR = dm
A cm
Where:-
A dm = Differential mode gain (105)
A cm = Common mode gain
−Vs V
(a) (b) s CMRR = (Common mode rejection ratio) (105)
R2 R2
105
−Vs Vs 105 =
(c) (d) A cm
RL R1
ISRO Scientist Engg.-2008 A cm = 1
IES-2005 115. Consider the following op-amp circuit :
GATE-2004
Ans. (a) :
What is the output voltage V0 in the above

op-amp circuit ?
(a) +10 V (b) –10 V
(c) +11 V (d) –11 V
IES-2004
Ans. (b) :
(a) –5 mA (b) –10 mA

Using super position theorem – (c) +25 mA (d) +50 mA
Case- I IES-2004
Ans. (b) :
When 1 volt active and 2 volt will be ground.
( V0 ) ' = 1 +
RF  Apply KCL at inverting terminal –
 ⋅ Vx
 R  I1 = I 2 + I3
 100  1× 100  Q ( I 2 = 0A )
= 1 +  
 10  110  10 − V1 V1 − V0
=
110 100 1 1
= × −2V1 = −V0 − 10
10 110
( V0 ) ' = 10V V0 + 10
V1 = ...........(i)
2
Case-II
Apply KCL at Non-inverting terminal –
When 2 volt active and 1 volt will be ground. I 4 = I L + I5 + I 6
Q ( I6 = oA )
V0 − V1 V
= IL + 1
1 1
I L = V0 − 2V1
 V + 10 
= V0 − 2  0 
 2 
I L = −10 mA
( V0 ) " =  − F  ⋅ Vin
R
117. Consider the following circuit :
 R 
( V0 ) " =  −
100 
× 2
 10 
( V0 ) " = −20 Volt.
O/P voltage (when both active)
V0 = ( V0 ) '+ ( V0 ) " = 10 − 20 = −10V
What is the value of R4 in the above circuit, if
116. What is the load current IL in the circuit
the voltage V– and V+ are to be amplified by the
below? same amplification factor?
(a) 7 kΩ (b) 22 kΩ Ans. (c) :
(c) 33 kΩ (d) 35 kΩ Case-I
IES-2004 When V = + Ve
0
Ans. (c) :
Then diode will be in Reverse bias.
V0 = 0V
When V– active and V+ ground.
Case-II
−R 2
( V0 ) ' = ( V– ) When V0 = − Ve
R1
Then diode will be in forward bias.
When V+ active and V− ground.
 R2   R 4 × V+ 
( V0 ) " = 1 +  
 R1  R3 + R4 
V0 = ( V0 ) '+ ( V0 ) "
 R   R  R4 
V0 =  − 2  ( V− ) + 1 + 2    V+ V0 = Vi
 R 1   R1   R 3 + R 4 
there are V− and V+ has to be amplified by same
amplification factor.
V− = V+ = V0
given – R 1 = 10kΩ R 2 = 22kΩ
R 3 = 15kΩ R4 = ?
Hence the circuit works as a positive clipper.
22kΩ  22kΩ   R4 
= 1 +   119. The stage marked X in the shown below
10kΩ  10kΩ   15kΩ + R 4 
architecture of a two-stage op-amp is
22  22   R4 
= 1 +   
10  10   R 4 + 15kΩ 
2.2 R4 (a) Direct coupled amplifier
= ⇒ 2.2R 4 + 33 = 3.2R 4 (b) Buffer amplifier
3.2 R 4 + 15kΩ
(c) Level shifter
⇒ R 4 = 33kΩ (d) Blocking oscillator
118. Consider the following circuit : IES-2003
Ans. (c) :
How does the above circuit work

(a) As a logarithmic amplifier
(b) As a negative clipper
(c) As a positive clipper
(d) As half-wave rectifier
IES-2004 Internal architecture of op-amp.

120. The current through the resistor R in the below 122. An op-amp circuit is shown in the figure given
below. Different inputs and output are given
under List-I and List-II. Match List-I (Input)
with List-II (Outputs) and select the correct
answer using the codes given below the list :
List-I List-II
(a) 1 mA (b) 4 mA
(c) 8 mA (d) 10 mA
IES-2003
Ans. (d) :
(a) 1.
(b) 2.
(c) 3.
(d) 4.
Vx = 2V (due to virtual short concept) Codes :
 12 − 2  A B C D
I= 
 1kΩ  (a) 2 4 1 3
I = 10mA (b) 1 3 2 4
Here Q β = ∞ ∴ I B = 0A (c) 2 3 1 4
So IC = I E = I R L (d) 1 4 2 3
I R L = 10mA IES-2002
Ans. (a) :
121. In a circuit, if the open loop gain is 106 and
output voltage is 10 volt, the differential voltage
should be
(a) 10 µV (b) 0.1 µV
(c) 100 µV (d) 1 µV
IES-2002
Ans. (a) : We know–
In op-amp
VO = A OL × Vid
This circuit is differentiator circuit.
Where –
A OL → Open loop gain dVin
O/P will be V0 = −RC
Vid → Input differential voltage. dt
VO 10 As we know–
Vid = = 6 = 10µV
A OL 10 Ramp signal  
d dt
→ step signal  
d dt
→ Impulse signal

123. A non-inverting op-amp is shown below Ans. (a) :
(assume ideal op-amp)
 1 
The output voltage VO for an input Vx =   sin t
Vi = [2+ sin(100t)]V  1 + RCs 
(a) 3/2 sin (100t) (b) 3 sin (100t)  1 
= −6  sin t
 1 + 10 × 10 ⋅ s 
6
(c) 2 sin (100t) (d) 3 sin (100t) + 1/2
Nagaland PSC CTSE (Degree)-2017, Paper-II  1 
=  sin t
IES-2002 1+ s 
Ans. (a) :  1  1
=  sin t ⇒  − tan −1 (1 1)  sin t
 1 + jω  2
sin t
Vx = ∠ − 45º
2
 4.14 
V0 = 1 +  ⋅ Vx
 10 
 14.14  sin t
At Non inverting terminal- V0 =   ∠ − 45º
 10  2
 2R 
V0 = 1 +  ⋅ Vx 2
 R  V0 = sin t ∠ − 45º
2
V0 = 3Vx .......... (i)
V0 = sin ( t − 45º )
Apply KCL at Node Vx
V0 = sin ( t − π 4 )
I1 + I2 + I3 = 0
125. In a 741 op-amp, there is 20 dB/decade fall-off
Q I1 = 0A starting at a relatively low frequency. This is
Vx + 2 Vx − ( 2 + sin100t ) due to the
+ =0 (a) Applied load
R R
(b) Internal compensation
2Vx − sin100t = 0
(c) Impedance of the source
sin (100t ) (d) Power dissipation in the chip
Vx =
2 APGENCO AE-23.04.2017
n
Put the value of Vx in eq (i) IES-2001
Ans. (b) : In op-amp, there is 20dB/decade fall-off
3
V0 = sin (100t ) starting at a relatively low frequency this is due to
2 internal compensation.
124. In the circuit shown in the given figure, V0 is 126. The input differential stage of op-amp 741 is
given by biased at about 10µA current. Such a low
current of the input stage gives
1. High CMRR
2. High differential gain
3. Low differential gain
4. High input impedance
Which of these are correct :
(a) sin (t–π/4) (b) sin (t+π/4) (a) 1 and 2 (b) 1, 2 and 4
(c) sin t (d) cos t (c) 3 and 4 (d) 1, 2, 3 and 4
IES-2001 IES-2001
Ans. (b) : 2−0
IC = = IE = 5mA
• An ideal op-amp have high CMRR. RL
A ↑ 2
↑ CMRR = dm RL =
A cm ↓ 5 × 10−3
• Differential mode gain is high. R L = 0.4kΩ
• Common mode gain is low.
R L = 400Ω
• Input resistance is high.
127. The main drawback in the performance of 129. In the circuit shown in the given figure, the
shunt peaked wide band amplifier is current through the resistance R is
(a) To low gain at low frequency
(b) Reduced gain at middle frequency
(c) Poor phase response
(d) That the maximum gain of the stage is small
IES-2001
Ans. (c) : The main drawback in the performance of
shunt peaked wide band amplifier is poor phase
response.
128. A circuit is shown in the given figure. The
largest value of RL that can be used is
(a) 100 µA (b) –100 µA
(c) 1 mA (d) –2 mA
IES-2001
Ans. (d) :
(a) 100 Ω (b) 400 Ω

(c) 2 kΩ (d) 20 kΩ
IES-2001
Ans. (b) : Here Vx1 = Vx 2 (due to virtual short concept)
Apply KCL at inverting terminal –
I1 = I2
2 − Vx 2 Vx 2 − V0
=
10 10
2Vx 2 = V0 + 2
V + 2
Vx 2 =  O  .............(i)
Vx = 2V (due to virtual short concept)  2 
12 − Vx 12 − 2 Apply KCL at Non-inverting terminal –
IE = =
2kΩ 2kΩ I 3 = I 4 + I5
I E = 5mA V0 − Vx1 Vx1 Vx1
= +
→ When β (current gain) of transistor i.e. not given we 1 1 10
assumed β = ∞ Vx1
V0 − 2Vx1 =
I 10
β= C 10V0 − 20Vx1 = Vx1
IB
IB = 0 10V0 = 21Vx1
I E = IC 10V0 = 21Vx 2 (Q Vx1 = Vx 2 )

21  V0 + 2  I B = 0mA
V0 =  ( from eq (i) )
n

10  2  IC = I E
21 21
V0 = V0 + I E = 8mA
20 10
V0 = − 42V 132. The V0 of the op-amp circuit shown in the
given figure is
Put the value of V0 in eqn (i)
2Vx 2 = − 42 + 2
Vx 2 = −20V = Vx1
Vx 2 −20
I= = = −2mA
10KΩ 10
I = −2mA
(a) 11 Vi (b) 10 Vi
130. The effect of a finite gain of an operational (c) Vi (d) zero
amplifier used in an integrator is that
IES-1999
(a) It would not integrate
Ans. (d) :
(b) The slope of the output will very with time
(c) The final value of the output voltage will
reduce
(d) There will be instability in the circuit.
APGENCO AE-23.04.2017
IES-2001
Ans. (d) : The effect of a finite gain of an op-amp used
in an integrator is that there will be instability in the
circuit. Output voltage in op-amp.
−10  1 + 10   10 
131. In the circuit shown in the given figure, the V0 = × Vi +  ×  × Vi
current flowing through resistance of 100Ω 1  1   1 + 10 
would be −10 11 10
= × Vi + × × Vi
1 1 11
= –10Vi +10Vi
V0 = 0V
133. The output voltage Vo of the given circuit
(a) 8 mA (b) 10 mA
(c) 20 mA (d) 100 mA
IES-2000
Ans. (a) :
(a) –100 V (b) –100 mV
(c) 10 V (d) –10 mV
IES-1999
Ans. (d) :
Vx = 2V (due to virtual short concept)

10 − 2
IE = = 8mA
1kΩ
Here β is not given so we assume ( β = ∞ )
IC 1st output op-amp
β=
IB Vo1 = −1µA × 1k

= −1mV then red LED will be glow
Second stage of op-amp. For op-amp 2-
Output voltage at non inverting op-amp. V+ < V− then
 R  V0 = −Vsat
Vo = 1 + f  Vin
 R in  then green LED will not be glow
So, clearly only red LED will be glow.
Vin = V01
R F = 90 136. In the circuit shown, it is required that V0 = Vi
the values of l , m, n are respectively.
R in = 10kΩ
(x represents don't care condition)
Put the value
 90 
Vo = 1 +  × −1× 10−3
 10 
= −10 × 10 −3 V
Vo = −10mV
134. In a single-stage differential amplifier, the (a) 0, 1, 1 (b) ∞, x, x
output offset voltage is basically dependent on (c) x, ∞, x (d) 0, x, ∞
the mismatch of IES-1998
(a) VBE, IB and β (b) VBE and IB Ans. (b) :
(c) IB and β (d) VBEand β
LMRC AM (S&T)-13.05.2018
IES-1999
Ans. (c) : Output offset voltage -
Voffset = Input offset voltage × gain +(feedback
resistance) × IB
= Vin (offset) × A v + R f I B Voltage at non-inverting terminal (at node 2)
Here, Av depend upon β and I B lR
Vm = × Vi
So output offset voltage depend upon β and I B (n + l ) R
135. In the circuit shown in the figure, l
Vm = × V …(i)
(n + l) i
KCL apply at node (1)
V0 − Vm Vm − Vi
=
mR R
m ( Vm − Vi ) = V0 − Vm
mVm − mVi = V0 − Vm
(a) Only red will glow V0 = Vm (1 + m ) − mVi …(ii)

(b) Only green will glow From equation (i) and (ii)
(c) Both red and green will glow  l 
Vo = ( m + 1)   ⋅ Vi − mVi
(d) Neither red nor green will glow  n +l 
IES-1998  
Ans. (a) :  1 
Vo = ( m + 1) ⋅ − m  Vi ........ (iii)
  n 
 1 +  
 l
From equation no. (iii). if l → ∞ then
 ( m + 1) 
Vo =  − m  Vi
 (1 + 0 ) 
For op-amp 1- Vo = Vi
V+ > V− then If l → ∞ then it does not matter what is m and n
V0 = + Vsat Hence, m = x, n = x

137. In the case of the circuit shown in the figure, 138. For a sinusoidal input, the circuit shown in the
Vio = 10 mV dc maximum, the maximum figure will act as a
possible output offset voltage V∞ caused by the
input offset voltage Vio with respect to ground
is :
(a) Pulse generator (b) Full-wave rectifier

(c) Ramp generator (d) Voltage doubler
IES-1997
Ans. (b) :
(a) 60 mV dc (b) 110 mV dc
(c) 130 mV dc (d) 150 mV dc
IES-1997
Ans. (b) :
This circuit can be rearranged.
Apply the KCL at node VA

0 − VA VA − Vo
= –––––––––(i)
R1 R2
Diode D1 and diode D 2 will produce negative and
VA = Vio positive signal at output ( Vo ) . So, given circuit act as a
Put the value of equation (i) full wave rectifier.
−Vio Vio − Vo 139. An instrument needs an amplifier to amplify
= pulses of one microsecond duration. This
R1 R2
amplifier must have a bandwidth of at least.
−10mV 10mV − Vo (a) 10 kHz (b) 10 MHz
=
1kΩ 10kΩ (c) 1 kHz (d) 1 MHz
IES-1997
−10 × 10−3 10 × 10−3 − Vo
= Ans. (d) : Amplifier pulse duration ( T ) = 1 × 10 −6
1 10
second
−100 × 10 −3 = 10 × 10 −3 − Vo 1
Frequency =
Vo = 100 × 10−3 + 10 × 10 −3 Time duration
1
Vo = 110 × 10−3 =
1×10−6
= 1MHz
Vo = 110mV
Hence bandwidth = 1MHz

140. The op-amp circuit shown in the given figure 142. Op-amp circuit shown in the given figure is
be used for
(a) Addition (a) A sample and hold circuit

(b) Subtraction (b) An integrator
(c) Both addition and subtraction (c) A zero crossing detector
(d) Logarithmic (d) A half-wave precision rectifier
IES-1995
IES-1996
Ans. (a) : Given circuit represents a sample and hold
Ans. (d) : circuit.
143. The op-amp of the circuit shown in the figure
has a unity gain frequency of 1MHz. The cut
off frequency of the feedback amplifier is
Given circuit is a logarithmic amplifier.

141. When z >> z' the op-amp circuit shown in the
given figure behaves as a/an
(a) 100 kHz
(b) 1 MHz
(c) 10 MHz
(d) 90 MHz
IES-1995
Ans. (a) :
(a) Inverting amplifier

(b) Schmitt trigger
(c) Non-inverting amplifier
(d) Voltage follower
IES-1995
Ans. (d) :
Given, R f = 90kΩ, R in = 10kΩ and unity gain

frequency f T = 1MHz
R 
Av = 1+  f 
A voltage follower (also known as a buffer amplifier.)  R in 
Unity-gain amplifier. 90
= 1+ = 10
Whose output is voltage is equal to the input voltage. 10
Unity frequency gain
 z' 
V0 = Vs  1 +  f T = gain × f 3dB
 z
fT 1000000
= Vs 1 + 0 )
( (Q z >> z ') So, f 3dB =
gain
=
10
V0 = Vs f 3dB = 100kHz

144. The circuit given in the figure is a 146. Under what condition will the instrumentation
amplifier circuit given in the figure possess
highest CMRR?
( R S1 and R S2 source resistances)
(a) Low-pass filter (b) High-pass filter

(c) Band-pass filter (d) Notch filter
IES-1997, 1994
Ans. (c) :
R1 R 3
(a) =
R2 R4
R S1 + R1 R S2 + R 3
(b) =
R2 R4
R S1 + R 2 R S2 + R 4
This circuit is a band pass filter. (c) =
R1 R3
At low frequency, X c → ∞ then open circuit
R S1 R S2
High frequency, X c → 0 then short circuit. So in both (d) =
R2 R4
case we get small signal in output.
IES-1994
145. Considering the following statements regarding
the state variable section given in the figure A
Ans. (b) : CMRR = d
Ac
For high value of CMRR
Ac should be very low.
Ac ≈ 0
For this condition
R s1 + R1 R s2 + R 3
=
R2 R4
1. V1 is the notch filtered output of Vi 147. The output offset voltage is zero for circuit
2. V3 is the low pass filtered output of Vi given in the figure, when
3. V2 is the band pass filtered output of Vi
Of these statements :
(a) 1, 2 and 3 correct (b) 1 and 2 are correct
(c) 2 and 3 are correct (d) 1 and 3 correct
IES-1994
Ans. (a) :
(a) V1 = 0, I −B = I +B and V1 = V2
(b) V1 = 0 and I−B = I+B
(c) I −B = I +B and V1 = V2
V1 is notch filter output of Vi and V2 is the band pass (d) V1 = 0 and V1 = V2
filter due to capacitor, V3 is low pass filter output of Vi IES-1994

Ans. (a) : 149. The approximate input impedance of the op-
amp circuit shown in given figure is
Given offset voltage = 0

V1 = V2 = 0 and I −B = I +B (a) Infinity (b) 120 kΩ
V
+
From above circuit, I = 2
B [Q V2 = 0] (c) 110 kΩ (d) 10 kΩ
R4 IES-1993
+
I =0
B
Ans. (d) :
148. Which one of the following conditions would
give Vo = 0 in the circuit shown in the figure?
Due to the presence of virtual ground at input, the

resistances in the series path of input of inverting
(a) R = R1 + R2 (b) R = R2/R1 amplifier is input impedance,
(c) R = R2 – R1 (d) R = R1 || R2 V+ = V− = 0
IES-1993 Apply KVL at input loop-
Ans. (d) :
− Vin + 10K ( I ) + 0 = 0
Vin
= 10K = R in
I
the circuit shown in the given figure :
Q Given conditions V0 = 0
AV = ∞
Vid = V1 − V2 = 0
∴ Both input virtual ground.
Apply KCL at inverting terminal,
0 − V1 V − Vo
=I+ 1
R1 R2
–V1 V −0
Q = I+ 1
R1 R2
1. The circuit represents an active low pass
–V1 V
= I+ 1 filter.
R1 R2 2. The circuit represents a second order
and V1 = V2 = −IR active filter.
IR
= I+
( −IR ) 3. The circuit has a roll-off rate of 40 dB/
decade.
R1 R2
(a) 1, 2 and 3 are correct
R
= 1+
( −R ) , 1 = 1 + 1 (b) 1 and 2 are correct
R1 R2 R R1 R 2 (c) 1 and 3 correct
(d) 2 and 3 are correct
∴ R= R1 || R 2 IES-1993
Ans. (a) : ∴ Vm = peak value of output signal
Given value –
Slew rate = 100 V µ sec = 100 ×106 V second .
given, f m = 10MHz
100 ×10 = 2 × π × 10 × 106 × Vm
6
10 5
Vm = =
The given circuit represents a second order active low 2× π π
pass filter and roll-off rate = 40 dB/decade. 153. In the Op-Amp circuit shown in, the output
151. The hysteresis phenomenon in Schmitt trigger would be
has which of the following features :
1. It is due to negative feedback
2. In the inverted mode, circuit triggers at a
higher voltage for increasing signals than
for decreasing signals
3. Noise signal voltages greater than VH are
cut-off, where VH is the hysteresis voltage
4. Slowly varying signals are converted to
output waveform with abrupt changes at
two specified levels of input signals. (a) 400 mV (b) 300 mV
Of these four statements, the true statements (c) 200 mV (d) 100 mV
are : TANGEDCO-2015
IES-1991
(c) 2, 3 and 4 only (d) 3 and 4 only
IES-1992 Ans. (c) :
Ans. (b) : Hysteresis phenomenon in Schmitt trigger –
• In inverted mode, circuit triggers at a higher voltage
for increasing signal than for decreasing signal.
• Slowly varying signals are converted to output
waveform with abrupt changes at two specified
levels of input signals.
• Schmitt triggers a comparator circuit with hysteresis
implemented by applying positive feedback to the
monitoring input of a comparator or differential Ideal open amplifier,
amplifier. A V = ∞, R i = ∞
Vo = A V Vid
Vid = V+ − V– = 0
Output voltage in op-amp,
10  10  10
V0 = −10 × +  1 +  × × 30
152. An operational amplifier has a slew rate of 1  1  10 + 1
100V/microsecond. For a frequency of 10 MHz, = − 100mV + 300mV
the maximum (peak) value of the sine wave
output voltage will be = 200mV
50 154. In an operational amplifier circuit, the
(a) 100 V (b) V
π maximum frequency for the undistorted output
5 is 100 kHz for 10 Volts P - P output because of
(c) 10 V (d) V the finite slew rate of the op-amp. The
π
maximum frequency for undistorted output of
TANGEDCO-2015
5 volts P - P.
IES-1991
(a) Will be approximately 100 kHz
Ans. (d) : Given , slew rate = 100V/µsec, f = 10MHz
(b) Will be less than 100 kHz
Q Slew rate (Maximum case)
(c) Will be more than 100 kHz
 dVo  (d) Cannot be determined from the given data.
SR =   = 2πf.Vm
 dt  max IES-1991

Ans. (c) :
∴ Slew rate in op-amp
 dV 
SR =  o  = 2πf m Vm
 dt  max
(d)
Vm = 10V, f max = 100kHz
SR = 10 × 100 × 103 × 2π
SR = 2π × 106 ………….. (1) ISRO Scientist Engg. -2020
When, Vm = 5V, then, Ans. (a) :
SR = 2π × f m × 5
2π × 106 = 2π × f m × 5
f m = 200kHz
Hence, Q f m > 100kHz
155. In the circuit shown, diodes are ideal. Which is
the correct representation of transfer
characteristics of the circuit?
Q In op-amp output voltage can be either +10V to –

5V.
Ideal op-amp-Av = ∞ ,
R i = ∞ , ( Vsat ) = ∞ [ +10V to − 5V ]
V+ = V− = 0 virtual ground
Q Upper threshold voltage , If D2 = on, D1 = off
V .R
VUTP = sat 3
R3 + R2
10 × 4 40
= = = 6.67V
4+2 6
And lower threshold voltage, If D2 = off, D1 = on,
− Vsat .R 3 −5 × 4 −20
(a) VLTP = = = = −3.33V
R 3 + R1 4+2 6
(b)
156. Most of the linear ICs are bases on two

transistor differential amplifiers because of
(a) Input voltage-dependent linear transfer
characteristic
(b) High voltage gain
(c) (c) High input resistance
(d) High CMRR
IES-2013
Ans. (d) : Differential Amplifier :- The Given circuit is a Schmitt trigger with positive
• High CMRR can be achieved by employing two- feedback. OP-amp circuit as comparator.
transistor differential amplifiers in most of the linear Vo = +Vcc = +10V, if V+ > V–
ICs. Vi = –Vcc = –10 V, if V– > V+
A Case-I
• CMRR = d
Ac Vi is increase from –∞ to +∞
• Differential Amplifier can reduce external interface. initially V+ dominates Vi = –∞
• Differential amplifier has property of noise Vo = +10 Volt, D2 is forward biased
cancellation. and D1 is reverse biased
157. Given the ideal operational amplifier circuit 2
shown in the figure indicate the correct V+ = 10 × = 8 Volt
transfer characteristic assuming ideal diodes 2 + 0.5
with zero cut-in voltage. then, Vo = +10 Volt, V– < + 8V
if Vi ≥ +8V, then V– dominate.
Vo = –10 Volt.
(a)
Case-II
Vi decreasing from +∞ to –∞
V– dominates initially, Vo = –10 V
D1 is FB and D2 is RB
(b) 2
V+ = –10 × = –5 V
2+2
Hence, V0 = –10 V, Until Vi < – 5 V
V0 = +10 V, When Vi ≤ + 8 V
158. Consider the Schmitt trigger circuit shown
(c) below:
(d)
GATE-2005
Ans. (b) :
A triangular wave which goes from –12V to

12V is applied to the inverting input of the OP-
Amp. Assume that the output of the OP-Amp
swings from +15 V to –15V. The voltage at the
non-inverting input switches between
(a) –12 V and +12V
(b) –7.5 and +7.5 V
(c) –5 V and +5V
(d) 0V and 5V
GATE-2008

Ans. (c) : = 1× 10−3 × −103
= −1V
It can be either positive or negative that is ±1V, voltage
follower.
So, output voltage Vo = ±1V
160. The circuit of figure uses an ideal Op-Amp for
small positive values of Vin, the circuit works as
Condition 1 – If Vi = –12 V and V0 = +15 V

Vr – ( +15 ) Vr – ( –15 ) Vr – V0
KCL at Vr, + + =0 (a) A half wave rectifier
10 × 103 10 × 103 10 × 103
Vr – 15 + Vr + 15 + Vr – (–15) = 0 (b) A differentiator
3Vr = –15 (c) A logarithmic amplifier
Vr = +5V (d) An exponential amplifier
Condition 2 – If Vi = +12 V and V0 = –15 V UKPSC Assistant Radio Officer Screening Exam-2011
IES-1994
Vr – 15 Vr – ( –15 ) Vr – V0
KCL at Vr, + + = 0 GATE-1992
10 × 103 10 × 103 10 × 103 Ans. (c) :
Vr –15 + Vr + 15 + Vr – (–15) = 0
3Vr = –15
Vr = –5 V
Hence, the voltage at the non-inverting input (Vr)
switches between –5V and +5V
159. An Op-Amp has an offset voltage of 1mV and
is ideal in all other respects. If this Op-Amp is Q In Ideal op-amp, R = ∞
i
used in the circuit shown in fig. The output
voltage will be (Select the nearest value). So, I + = I − = 0
and gain A OL = ∞
So, Vo = A OL × Vid
Vo V
Vid = = o =0
A OL ∞
 Where V+ = non inverting 
 
Vid = V+ − V− = 0  terminal 
(a) 1 mV (b) 1 V  V = Inverting terminal 
(c) ± 1 V (d) 0 V  – 
RPSC VP/Suptd. ITI 05.11.2019 V+ = V− (Virtual ground)
ISRO Scientist Engg.-2008 V − 0 Vin
GATE-1992 Q I= in = ......(1)
R R
Ans. (c) :
( )
I = Io e V VT − 1 Io ⋅ e V VT
(diode current in forward bias)
I   I  V
= eV VT ⇒  V = VT ln    (where, I = i )
Io   Io   R
 I 
− Vout = VT ln  
 Io 
–R f −106 V 
Q gain= = = −103 = −VT ln  in 
Ri 103  Io R 
Since Vin = Voffset = 1mV
V 
Q Output voltage in op-amp, Vout ∝ −VT ln  in 
Vo = Vin Gain  Io R 

161. The circuit shown in the figure is that of Ans. (d) :
(a) A non-inverting amplifiers

(b) An inverting amplifier Q In op-amp open loop gain A oL = ∞, R i = ∞
(c) An oscillator Q V0 = A oL ⋅ Vid
(d) A Schmitt trigger V0 = 0 = V+ − V−
GATE-1996
V+ = V− Virtual ground.
Ans. (d) : Represented circuit diagram → Schmitt
trigger. KCL apply at inverting terminal.
V− − 2 V− − V0
+ =0
5 10
V +4
V− = 0 ............ (1)
3
Again KCL apply at non inverting terminal,
V+ V+ − V0
+ =0
10 100
11V+ − V0 = 0
V0
V+ = ............(2)
11
(Concept of hysteresis in Schmitt trigger circuit) Q V+ = V− ( Virtual ground )
→ Schmitt trigger is form of comparator circuit that has
V0 V0 + 4
hysteresis switching levels to change input to output = from equation (1) and (2)
11 3
between the two states.
3V0 = 11V0 + 44
R2
Vin = ⋅ Vout V0 = −5.5 Volt
R1 + R 2
163. One input terminal of high gain comparator
162. The output voltage V0 of the circuit shown in circuit is connected to ground and a sinusoidal
the figure is voltage is applied to the other input. The
output of comparator will be
(a) A sinusoid
(b) A full rectified sinusoid
(c) A half rectified sinusoid
(d) A square wave
GATE-1998
Ans. (d) :
V+= non inverting terminal voltage
V– = inverting terminal voltage
(a) –4 V
Then, V+ > V−
(b) 6V
V0 = + VCC
(c) 5V
(d) –5.5 V Then, V− > V+
GATE-1997 V0 = −VCC

166. If the op-amp in the figure, is ideal, then V0 is
(a) Zero (b) (V1 – V2) sin ωt

(c) –(V1 + V2) sin ωt (d) (V1 + V2) sin ωt
GATE-2000
Ans. (c) :
If Let, R F = R1 = R 2
V0 = − ( V1 sinωt+V2 sin ωt )
V0 = − ( V1 + V2 ) sin ωt.
164. The first dominant pole encountered in the 167. Assume that the op-amp of the figure is ideal. If
frequency response of a compensated op-amp is Vi is a triangular wave, then V0 will be
approximately at
(a) 5 Hz (b) 10 kHz
(c) 1 MHz (d) 100 MHz
GATE-1999
Ans. (a) : First dominant pole encountered in the
frequency response of a compensated op-amp is
approximate = 5Hz.
(a) Square wave (b) Triangular wave
165. In the circuit of the figure, V0 is
(c) Parabolic wave (d) Sine wave
GATE-2000
Ans. (a) :
(a) –1V (b) 2V

(c) +1V (d) + 15V
GATE-2000
Ans. (d) : Op-amp in balance condition,
iC = i R
CdVi 0 − V0
=
dt R
CdVi V0
=
dt R
dVi
In the given circuit, positive feedback is used and in V0 = −RC ⋅
positive feedback op-amp act in its saturation region dt
± Vsat . −dVi
Q V0 ∝ for differentiator op-amp.
Due to positive feedback V0 = + Vsat = +15V dt

t
(a) 10 cos (100 t) ∫
(b) 10 cos(100t)dt
0
t
d
∫
(c) 10−4 cos(100t)dt
0
(d) 10−4
dt
cos(100t)
GATE-2001
Ans. (a) : Apply nodal analysis at node 1,
0 − Vs 0 − V0 '
+ =0
10 XL
−Vs V0 '
=
10 XL
168. If the op-amp in the figure has an input offset −10cos (100t ) V0 '
voltage of 5 mV and an open-loop voltage gain =
10 XL
of 10,000, then V0 will be
V0 ' = −ωL cos (100t )
V0 ' = −100 × 10 × 10−3 cos (100t )
V0 ' = − cos (100t )
Apply nodal Analysis at node 3,
0 + cos (100t ) 0 − V0
+ =0
100 1 ωc
(a) 0 V (b) 5 mV cos (100t )
= V0 ×100 × 10 × 10−6
(c) + 15 V or –15 V (d) +50 V or –50 V 100
GATE-2000 V0 = 10cos (100t )
Ans. (c) : Q Given value 170. If the input to the ideal comparator shown in
Vio = 5mV the figure is a sinusoidal signal of 8 V (peak to
peak) without any DC component, then the
A oL = 10000 output of the comparator has a duty cycle of
V0 = A oL ⋅ Vid
(a) 1/2 (b) 1/3

(c) 1/6 (d) 1/12
GATE-2003
V0 = 5 ×10000 × 10 −3 Ans. (b) : Q Vin = 4sin ωt
V0 = ± 50 Volt. (But wrong)
Q Op-amp saturation case–
If, V+ > V− then V0 = + VCC
ToN
If, V− > V+ then V0 = −VCC Q Duty cycle = = 360º
T
Therefore, V0 = ±15V ( TON = 180 − 2ωt )
169. In the figure assume the op-amps to be ideal. Let, ωt = x, Vin = 2 volt
The output V0 of the circuit is: Vin = 4sin ωt
2 = 4sin x
1
sin x = ⇒ x = 30º
2
TON T
Duty cycle = = ON
TON +TOFF T
180º −60º 120º 1
= = =
360º 360º 3
171. If the op-amp in the figure is ideal, the output 1
voltage Vout will be equal to Vo1 = 50Vin ×
1.25
(a) 1 V (b) 6 V
(c) 14 V (d) 17 V V0 V0 Vo 2 V01
GATE-2003 = ⋅ ⋅
Vin V02 V01 Vin
Ans. (b) :
50V02 V02 V01
= ⋅ ⋅
V02 V01 Vin
1 1
= 50 × 50 × × 50 ×
1.25 1.25
= 50 × 40 × 40
Q Inverting op-amp– = 80000
−R F ( A V )dB = 20log ( A V ) = 20log (80000 )
V0− = ⋅ Vin
R1
( A V )dB = 98.061 dB.
−5K
= ⋅ 2V 173. The circuit in the figure is
1K
V0− = −10 volt.
and Non-inverting terminal voltage in op-amp.
 R 
V0+ = 1 + f  ⋅ V+
 R2 
(a) Low-pass filter (b) High-pass filter
 5  8  (c) Band-pass filter (d) Band-reject filter
= 1 +    × 3V
 1   8+1  GATE-2004
8 Ans. (a) :
= 6× ×3
9
V0+ = 16 Volt.
Therefore, total output op-amp voltage.
V0 = −10 + 16 = 6 Volt.
172. Three identical amplifiers with each one having 1
a voltage gain of 50, input resistance of 1 kΩ If f = 0, X C = = ∞, then signal will be pass.
and output resistance of 250Ω, are cascaded. 2πfC
The open circuit voltage gain of the combined 1
and f = ∞, X C = = 0, then signal will not be pass.
amplifier is 2πfC
(a) 49 dB (b) 51 dB Therefore, represented diagram is low pass filter.
(c) 98 dB (d) 102 dB
174. The input resistance Ri of the amplifier shown
GATE-2003
in the figure is
Ans. (c) :
Given value–
Zout = 250Ω
Zin = 1kΩ
30
(a) kΩ (b) 10 kΩ
4
1 (c) 40 kΩ (d) Infinite
Vo2 = 50Vo1 ×
1.25 GATE-2005

Ans. (b) : 176. The op-amp circuit shown in the figure is a
filter. The type of filter and its cut-off
frequency are respectively
According virtual short method.

VA = 0V
VS − VA VS − 0 V
= = S =I
10kΩ 10kΩ 10kΩ (a) High pass, 1000 rad/sec.
VS (b) Low pass, 1000 rad/sec
So, R i = = 10kΩ
I (c) High pass, 10000 rad/sec
175. The voltage e0 indicated in the figure has been (d) Low pass, 10000 rad/sec
measured by an ideal voltmeter. Which of the GATE-2005
following can be calculated? Ans. (a) : The op-amp circuit shown in the figure is
high pass filter.
1
ωc =
RC
1
=
1× 103 × 1× 10−6
ωc = 1000 rad / sec
(a) Bias current of the inverting input only 177. For the circuit shown in the following figure,
(b) Bias current of the inverting and non- the capacitor C is initially uncharged. At t = 0,
inverting inputs only the switch S is closed. The voltage VC across the
(c) Input offset current only capacitor at t = 1 millisecond is
(d) Both the bias currents and the input offset
current
OPSC Poly. Lect.(Instrumentation)-2018, Paper-I
GATE-2005
Ans. (c) : The algebraic difference between the currents
into the inverting and non-inverting terminals is referred
to as input offset current Iio i.e., In the figure shown above, the Op-amp is
Iio = I B1 − I B2 supplied with ± 15V.
(a) 0 Volt (b) 6.3 Volts
(c) 9.45 Volts (d) 10 Volts
GATE-2006
Ans. (d) :
Due to virtual ground method – V2 = V1

V2 = −I B 2 × 1MΩ, V1 = I B1 ⋅1MΩ
Drop in feedback resistance = I B2 × 1MΩ 10 − 0
I= = 10mA = constant current.
e0 = V2 + IB2 ⋅1MΩ 1K
= −IB2 ⋅1MΩ + I B1 ⋅1MΩ V
Q Ideal op-amp, A V = ∞ = 0
Vid
( )
= I B1 − I B2 ⋅1MΩ
V0 V0
Vid = =
e0 = Ii0 ⋅1MΩ , Where I B1 − I B2 = Iio AV ∞

Vid = 0 = V+ − V− − virtual ground. Total output voltage in op-amp circuit,
V0 = V01 + V02
At t = 0, switch is closed.
= −2 + 1.5
R i = ∞ → so, no internal current, I + = I − = 0 = −0.5 Volt
A current of 10mA is flowing through capacitor. 179. In the op-amp circuit shown, assume that the
∴ Current flowing through capacitor is constant diode current follows the equation I = Is exp
1 1 t (V/VT). For Vi = 2V, V0 = V01, and for Vi = 4 V,
VC = ∫ idt = ∫ Idt
C C 0 V0 = V02. The relationship between V01 and V02
1 t I is
VC ( t ) = ∫ Idt = × t
C 0 C
∴ Given t = 1ms
1× 10−3 × 10 ×10−3
VC(1ms ) =
1×10−6
= 10 Volt
178. For the op-amp circuit shown in the figure, V0 (a) V02 = 2 V01 (b) V02 = e2 V01
is (c) V02 = V01 ln 2 (d) V01 – V02 = VTln 2
BSNL (JTO)-2009
GATE-2007
Ans. (d) :
(a) –2 V (b) –1 V
(c) –0.5 V (d) 0.5 V
BSNL (JTO)-2009 V0 = −V
GATE-2007 or
Ans. (c) : V = −V0
I = ISe( V VT )
I
= e V VT
IS
V
= ln ( I IS )
VT
KCL at node x, V = VT ln ( I IS )
R2 V0 = − V = −VT ln ( I IS )
V01 = −
× Vin
R1 V0 = −VT ln ( I IS )
−2
= × 1 = −2 Volt  1mA 
1 V01 = −VT ln   .........(1)
Apply KCL at node y,  IS 
 R   2mA 
V02 = 1 + 2  × Vy ……………(i) V02 = −VT ln   ..........(2)
 R1   IS 
 R3  1 2
Where Vy =  × Vin  V01 − V02 = − VT ln   + VT ln  
 R3 + R 4  I
 S  IS 
 R  R3   2  1  m
V02 = 1 + 2    × Vin From equation (i) = VT  ln   − ln    log m − log n ⇒ log
 R1  R 3 + R 4    IS   IS   n
 2  1    2 I 
= 1 +   ×1 ⇒ VT  ln  × S  
 1  1 + 1   
  IS 1  
1
= 3 × = 1.5 Volt V01 − V02 = VT ln2
2

180. Consider the following circuit using an ideal Ans. (d) : Suppose the transistor is off:-
op-amp. The I-V characteristics of the diode is Which means the op-amp will act as comparator
 V  Vt = 10V, V– = 5 Volt
described by the relation I = I0  e VT − 1  where
  V = + Vsat ⇒ transistor will be on.
 
VT = 25 mV, I0 = 1 µA and V is the voltage ⇒ The op-amp will operate in the linear region.
across the diode (taken as positive for forward Ideal op-amp.
bias). V V
i.e A = = =∞
Vid V+ − V−
⇒ V+ − V− = 0 (virtual ground condition)
⇒ V+ = V− = 5V
For an input voltage Vi = –1V, the output

voltage V0 is
(a) 0 V (b) 0.1 V
(c) 0.7 V (d) 1.1 V
GATE-2008
Ans. (b) : Output voltage,
V0 = V4K + V = I ( 4K ) + V …………..(i)
Where, 10 − 5
I= = 1mA , I E = 1mA
V4K → Voltage across 4kΩ 5
V → Voltage across diode. VE = IERE =1mA×1.4kΩ
VE = 1.4V
0 − ( −1)
I= = 10µA VBE = V − VE
100kΩ
From the given equation diode current, V = VBE + VE
 V  V = 0.6 + 1.4 = 2V
I D = I = 10µA = I0  e VT − 1
 
  Negative feedback, V = 2V
10µA = 1µA ( e V 0.25 − 1) 182. Assuming the op-amp to be ideal, the voltage
V = 0.06V gain of the amplifier shown below is
V0 = I ( 4K ) + V (equation- i)
V0 = 10µA × 4kΩ + 0.06
V0 = 0.04 + 0.06
V0 = 0.1 Volt
181. In the circuit shown below, the op-amp is ideal,
the transistor has VBE = 0.6 V and β = 150. R2 R3
Decide whether the feedback in the circuit is (a) − (b) −
R1 R1
positive or negative and determine the voltage
V at the output of the op-amp.  R || R 3   R + R3 
(c) −  2  (d) −  2 
 R1   R1 
GATE-2010
Ans. (a) : Redraw the circuit-
(a) Positive feedback V = 10 V

(b) Positive feedback, V = 0 V
(c) Negative feedback, V = 5 V
(d) Negative feedback, V = 2V
GATE-2009
I1 = I2 20 Vi V0
+ + =i
Vi − 0 0 − V0 4R R R
= If V0 is positive not conduct i = 0
R1 R2
Then,
−R 2 Vi 20 Vi V0
V0 = + + =0
R1 4R R R
V0 R 5+Vi+V0 = 0
=− 2 At Vi = –10V
Vi R1 V0 = –5+10 = 5V
183. The transfer characteristic for the precision At Vi = –5V
rectifier circuit shown below is (assume ideal V0 = –5+5 = 0V
op-amp and practical diodes) 184. In an op-amp, non-inverting terminal is
grounded, input is connected to inverting
terminal and there is no feedback resistance.
The output is
(a) A Vin (b) –A Vin
(c) A/Vin (d) –A/Vin
SAIL- 2014
Ans. (b) :
When input is connected to inverting terminal and there

is no feedback resistance then-
(a) V0 = –A Vin
185. A differential amplifier has a differential mode
gain of 100 and a common mode rejection ratio
of 1000. If the two applied input voltages are v1
and v2, then the output voltage will be :
(b) (v + v 2 )
(a) 100(v1 − v 2 ) + 0.1 1
2
(v1 + v 2 )
(b) 100 + 0.1(v1 − v 2 )
2
(v + v 2 )
(c) 100(v1 − v 2 ) + 105 1
(c) 2
(v1 + v 2 )
(d) 100 + 100(v1 − v 2 )
2
BSNL(JTO)-2002, 2001
Common mode rejection ratio (CMRR) = 1000
(d) Differential mode gain (Ad) = 100
A
Q CMRR = d (Where Ac is common mode gain)
Ac
GATE-2010
100
Ans. (b) : 1000 =
Ac
1
Ac =
10
For two input voltage v1 & v2
Output voltage = Ad vd + Ac vc
1  v 1 + v2 
Output voltage = 100 (v1 – v2) +  
10  2 
(v + v 2 )
Output voltage = 100 (v1 – v2) + 0.1 1
i1 + i2 + i3 = i 2

186. Schmitt trigger can be used as 188. In the circuit shown below what is the output
(a) Comparator (b) Square-wave generator voltage (Vout) if a silicon transistor Q and an
(c) Flip-flop (d) All of these ideal op-amp are used?
TSGENCO AE-2015
Ans. (d) : Schmitt-trigger can be used as square wave
generator.
• Schmitt trigger work as a principle of positive
feedback configuration
• Schmitt trigger also used to remove noise from an (a) –15V (b) –0.7 V
analog signal while converting it to a digital signal. (c) +0.7 V (d) +15 V
• A Schmitt trigger is basically an inverting comparator GATE-2013
circuit with positive feedback. Ans. (b) : Input to the op-amp is given to inverting
• It converts any wave into a square wave. terminal the output will be negative value.
• It can be used as a flip-flop. Transistor is biases → positive voltage (Collector) and
187. The circuit below implement a filter between negative voltage (Emitter) and base → ground.
the input current ii and output voltage V0. Therefore, base to collector junction → reverse and
Assume that the op-amp is ideal. The filter base to emitter junction → forward bias.
implemented is a Then, transistor (Si) cut- in voltage = 0.7 volts.
So, base to emitter voltage drop = 0.7 volts
VB − VE = 0.7
Q BJT VB = 0, IC = 5mA
∴ 0 − VE = 0.7
VE = −0.7 (Q Base is ground)
VB = 0V
∴ given circuit Vout = VE
(a) Low pass filter (b) Band pass filter
V0 = −0.7
(c) Band stop filter (d) High pass filter
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I 189. In the circuit shown, the op-amp has finite
GATE-2011 input impedance, infinite voltage gain and zero
Ans. (d) : input offset voltage. The output voltage Vout is
Effective impedance in feedback path
Z P = X L1 || R 1
Vout = i i ( Z P )
(
Vout = ii X L1 || R1 )
X L1 = 2 πfL1 (a) –I2 (R1 + R2) (b) I2 R2
(c) I1 R2 (d) –I1 (R1 + R2)
For low frequency - as f 0 = 0, X L = 0 UPPSC ITI Principal/Asstt. Director-09.01.2022
Vout = ii1 ( 0 || R1 ) GATE-2014
Ans. (c) :
Vout = 0 (that is DC component is not passed)
So that output is going to be block in the DC
component.
For large frequency of
f ↑ X L ↑ ( L arg e )
( )
V0 = ii X L1 || R 1 ≅ ii ( R1 )
Because X L1 is large as compared to R1 so parallel KCL at node A
V2 = (R1|| R2)I1….(i)
combination always gives the smaller than the smallest Apply KCL at node A
one V0 ≅ i1 ( R 1 ) = output occurs for large value of
I1' + I1" = 0
frequency.
→ This filter is rejecting the low frequency and it is 0 − V2 V0 − V2
+ =0
passing the High frequency. R1 R2

V0 − V2 V2  β + 1  Vref  β  Vref
= (a) I0 =   (b) I0 =  
R2 R1  β  R  β +1 R
V0 V2 V2
− =  β + 1  Vref  β  Vref
(c) I0 =   (d) I0 =  
R 2 R 2 R1  β  2R  β + 1  2R
V0  1 1  GATE-2016
= V2  + 
R2  R1 R 2  Ans. (b) :
from equation i & ii, V+ = Vcc − Vref = V−
V0 = I1R 2 Vcc − V− Vref
IE = =
190. Assuming that the op-amp in the circuit shown R R
is ideal, V0 is given by V+ = non inverting voltage
V– = inverting voltage
5 5
(a) V1 − 3V2 (b) 2 V1 − V2
2 2
3 7 11
(c) − V1 + V2 (d) −3V1 + V2
2 2 2
GATE-2014
Ans. (d) :
IE = I
β β V
I0 = Ic = α I E = IE = × ref
1+ β 1+ β R
Apply KCL at node A, we get
V2 − V1 V2 V2 − V0  β  Vref
+ + =0 I0 =  
R 2R 3R  1+ β  R
6V2 − 6V1 + 3V2 + 2V2 − 2Vo
=0 192. For the operational amplifier circuit shown, the
6R
output saturation voltages are ± 15 V. The
11V2 − 6V1 = 2V0
upper and lower threshold voltages for the
11 circuit are, respectively,
V0 = −3V1 + V2
2
191. Consider the constant current source shown in
the figure below. Let β represent the current
gain of the transistor.
(a) +5 V and –5 V
(b) +7 V and –3 V
(c) +3 V and –7 V
(d) +3 V and –3 V
The load current I0 through RL is GATE-2017

Ans. (b) : 1
= × 10−3 t1
10−6
= 1000t1 …(i)
Q Capacitor C 2 across voltage Vc2
1 t
{Q C 2 = 1µF}
C2 ∫0
= Ic dt
1 t
Ic dt = 1000 ( t 2 )
10−6 ∫0
…(ii)
KCL at node A
Q t = 0 switch closed then zener diode will be open.
VA − Vo VA − 3 Vc = Vc = 2.5 volt (zener diode turn on).
+ =0
10kΩ 5kΩ
1 2
Put value equation (1),

VA − Vo + 2VA − 6 = 0
2.5 = 1000t1
6 + Vo
VA = t1 = 2.5ms (zener turn on)
3
For UTP, Vo= +15V ∴ C1 continue to charge = 7.5 volt
Then, Q Vc2 = 5 volt
6 + 15 ∴ 5 = 1000 × t 2 (from equation …ii)
VUTP = = 7V
3
t 2 = 5msec
For LTP, Vo = –15V
6 − 15 ∴ Total time T = t1 + t 2
Then, VLTP = = −3V = 2.5 + 5
3
193. In the circuit shown below, the op-amp is ideal = 7.5m sec
and Zener voltage of the diode is 2.5 volts. At 194. The components in the circuit shown below are
the input, unit step voltage is applied i.e. VIN(t) ideal. If the op-amp is in positive feedback and
= u(t) volts. Also at t = 0, the voltage across the input voltage Vi is a sine wave of amplitude
each of the capacitors is zero 1 V, the output voltage V0 is
(a) A square wave of 5V amplitude

The time t, in milliseconds, at which the output (b) An inverted sine wave of 1V amplitude
voltage VOUT crosses –10 V is (c) A non-inverted sine wave of 2V amplitude
(a) 2.5 (b) 5 (d) A constant of either +5 or –5V
(c) 7.5 (d) 10 GATE-2020
GATE-2018 Ans. (d) :
Ans. (c) :
Given value = Zener diode voltage V2 = 2.5 volt Apply KCL -

Vout = −10Volt V+ − Vi V+ − V0
+ =0
Q Capacitor does not change sudden voltage. 1k 1k
1− 0 Vo = −5V
Ic = = 1mA
1k −5 + Vi
Then, V+ =
1 t 1 2
Q Vc1 = ∫ Ic dt = −6 × Ic t1
C1 0 10 Vo change from –5V to +5V, if V+ > 0

−5 + Vi 198. The output voltage of circuit shown below is
> 0, Vi > 5V
2
In the same way Vo change from +5V to –5V, if Vi<–
5V, but Vi has maximum value of 1V, so output cannot
change from +5V to –5V or –5V to +5V. Hence output
remain constant at +5V or –5V.
195. The components in the circuit given below are
ideal. If R = 2 kΩ and C = 1 µF, the –3 dB cut-
off frequency of the circuit in Hz is
(a) –10V (b) 5 V
(c) –5V (d) 0.5V
TSGENCO AE-2015
Ans. (c) : Apply KCL at node 2,
0 − 500 0 − Vout
+ =0
R1 R2
(a) 34.46 (b) 79.58 −500 −Vout
+ =0
(c) 59.68 (d) 14.92 1kΩ 10kΩ
GATE-2020 −500mv V
= out
Ans. (b) : Given value, 1kΩ 10kΩ
R = 2kΩ, C = 1µF Vout = −5V
Q cut off frequency of the circuit. 199. The differential gain of op-amp is 4000 and
1 value of CMRR is 150. Its output voltage, when
ω0 =
RC the two input voltages are 200 µV and 160 µV
1 respectively, will be
2πf 0 = (a) 16 V (b) 76 mV
RC (c) 64 mV (d) 164.8 mV
1 TSGENCO AE-2015
3.14 × 2 × f 0 =
2 × 103 × 10−6 Ans. (d) : Given, V1 = 200 µV, V2 = 160 µV, Ad =
103 4000, CMRR = 150
f0 = V0 = AdVd + AcVc Vd = V1–V2
2 × 3.14 × 2
= 79.6Hz V + V2
Vc = 1
196. The rise time of low pass RC Circuit is given by 2
(a) 2.2 RC (b) 30.2 RC A
CMMR = d
(c) 10 RC (d) 20.2 RC Ac
TSGENCO AE-2015 4000
150 = ⇒ A c = 26.67
Ans. (a) : The rise time of Low pass RC circuit is given Ac
by
Vd = V1 − V2
τ = 2.2 RC
Vd = 200 – 160 ⇒ Vd = 40 µV
197. In RC integrator circuit the output is taken
200 + 160
across Vc = = 180µV
(a) resistor 2
V0 = 4000 × 40 ×10–6+ 26.67 × 180×10–6
(b) transistor
(c) diode V0 = 164.8mV
(d) capacitor 200. In an RC differentiator, the condition for
TSGENCO AE-2015 differentiation is
Ans. (d) : (a) RC >> 0.16T (b) RC << 0.16T
(c) RC >> T/0.16 (d) RC << T/0.16
Ans. (b) : In an RC differentiator, the condition for
differentiation is τ << 0.16T. A RC differentiator is a
series connected RC network that produce an output
In RC integrator circuit, the output is taken across the signal which corresponds to the mathematical process
capacitor. of differentiator.

201. An op-amp is having an open loop gain of V
'10^(5)' and open loop upper cutoff frequency In dB, 20log 0 = 20 dB
of 10 Hz. If this op-amp is connected as an Vi
amplifier with a closed loop gain at 100, then V
the new upper cutoff frequency will be or, 0 = 10 = voltage gain
Vi
(a) 10 Hz (b) 100 Hz
As gain bandwidth product remains constant, hence,
(c) 10 kHz (d) 100 kHz
1 × 106 = 10 × Bnew
MPPSC Forest Exm.2014 Bnew = 105 = 100 kHz
Mizoram PSC AE/SDO-2012, Paper-I 204. An OPAMP-based comparator drives an LED,
Ans. (c) : Given, AOL = 105 fH = 10 Hz with VF = 1.6V, the current through which is
ACL = 100 regulated by a 1kΩ resistor and a silicon diode
5 in series. Assume a ±10V DC voltage is applied
A OL 10
ACL = ⇒1 + A OL .β = as ±VCC respectively to the op-amp. Then find
1 + A OL β 100 out the current through the LED when the
1 + AOL β = 103 comparator output is + 10V.
fCH = fH(1 + AOLβ) = 10×103 (a) 5.4mA (b) 8.5mA
fCH = 10 kHz (c) 7.7 mA (d) 6.7mA
202. Most of the linear ICs are based on the two APPSC POLY. LECT. 14.03.2020
transistor differential amplifier because of its
Ans. (c) :
(a) High CMRR
(b) High voltage gain
(c) High input resistance
(d) Input voltage dependent linear transfer
characteristics
IES-2013
Ans. (a) : Most of the linear ICs are based on the two
transistor differential amplifier because it has high
CMRR. VD = 1.6 + 0.7
CMRR- It is defined as the ratio of differential voltage = 2.3
gain to common mode voltage gain 10 − 2.3
ID =
CMRR = d
A 1 kΩ
Ac
I D = 7.7 mA
- It indicates the ability of an op-amp to reject common-
mode noise signals and to amplify desired differential 205. When an OP-AMP is used as an inverting
mode signal. amplifier with Rf = 100 kΩ and R1 = 10 kΩ, the
- The ideal op-amp will have the infinite CMRR and closed-loop gain is :
with finite differential gain and zero common mode (a) 10.00 (b) – 10.00
gain. (c) – 11.00 (d) 11.00
-High CMRR can be achieved by employing two-
transistor differential amplifiers in ICs.
203. A 741-type op-amp has a gain-bandwidth Ans. (b) : Given, Rf = 100kΩ , R1 = 10kΩ
product of 1 MHz. A non-inverting amplifier R
using this op-amp and having a voltage gain of Close loop gain inverting amplifier = – f
Ri
20 dB will exhibit a 3 dB bandwidth of:
(a) 100 kHz (b) 50 kHz Vo −100
= = −10
1000 1000 Vin 10
(c) kHz (d) kHz
17 7.07 206. The transfer function T(s) of a single OPAMP
Punjab PSC Poly. Lect. 20.08.2017 inverting mode filter that has a capacitance C
GPSC Asstt. Prof. 11.04.2017 and resistance R in the feedback path and an
GATE-2002 input resistance R is :
Ans. (a) : Given, (a) –1/{1 + sRC} (b) 1 + sRC
V (c) – sRC/{1 + sRC} (d) sRc/{1 + sRC}
Non inverting amplifier voltage gain = 0
Vi APPSC POLY. LECT. 14.03.2020

Ans. (a) : Ans. (c) : The output voltage is the sum of input voltage
with different weighting factor this circuit is called as
inverting summing amplifier.
210. For a non inverting op-amp when Ri = ∞, in an
open circuit, the closed-loop gain becomes
V
A v = 0 = 1 , then output voltage follows the
Vi
Vi × 1/ Cs input; this op-amp circuit is called:
V0 = − (a) Basic amplifier
1
R+ (b) Voltage follower
Cs
(c) Summing amplifier
V0 1 (d) Non inverting amplifier
=−
Vi 1 + RCs UPSC Poly.Lect.10.03. 2019
Ans. (b) : For a non-inverting op-amp if the closed loop
V0 1 gain become 1. Then output voltage follow the input
T(F) = =− voltage. This circuit is called voltage follower.
Vi 1 + RCs
211. What is the output voltage of an op-amp for
207. In a regulated power supply, a pass transistor input voltages of Vi1 = 150 µV, Vi2 = 140 µV
is used at the output of OPAMP to :
with amplifier differential gain of Ad = 4000
(a) provide a higher gain in the feedback loop.
and the value of CMRR = 100?
(b) provide a high input impedance to the
(a) 72.2 mV (b) 63.4 mV
OPAMP.
(c) 54.6 mV (d) 45.8 mV
(c) provide a larger current drive to the load.
(d) allow input voltage to pass efficiently to the UPSC Poly.Lect.10.03. 2019
output. Ans. (d) : Output voltage V0 = Ad Vd + Ac Vc _____(i)
APPSC POLY. LECT. 14.03.2020 Ad = 4000, Ac = 4000/100 = 40
Vd = 10 µV, Vc = 145 µV
Ans. (c) : In a regulated power supply, a pass transistor
V0 = 4000 × 10µV + 40 × 145 µV
is used at the output of OPAMP to provide a larger
current drive to the load. = 45.8 mV.
208. Consider an inverting amplifier with a 212. The responsivity of the PIN photodiode shown
is 0.9 A/W. To obtain Vout of – 1 V for an
feedback resistor R2 = 10 kΩ and an op-amp incident optical power of 1 mW, the value of R
with parameters; AoL = 105 and Ri = 10 kΩ. to be used is
Assuming the output resistance R0 of the op-
amp is negligible, the closed-loop input
resistance at the inverting terminal of an
inverting amplifier will be nearly:
(a) 0.4 Ω (b) 0.2 Ω
(c) 0.1 Ω (d) 0.05 Ω
(a) 0.9 Ω (b) 1.1 Ω
UPSC Poly.Lect.10.03.2019 (c) 0.9 kΩ (d) 1.1 kΩ
Ans. (c) : The open loop gain of inverting amplifier AoL APGENCO AE- 23.04.2017
= 105. Input resistance Ri = 10 kΩ, So closed loop input
I
resistance will be reduce by the factor {1 + (AoL. β)}. Ans. (d) : Responsivity = 0
Pi
R ( Open Loop )
R 1 ( Closed Loop ) = 1 I0 = Resposivity × Pi
(1 + A oL .β )
= 0.9A / W × 1mW
R1 ( Open Loop ) 104
= 5 = 0.1Ω = 0.9mA
A oL 10 So,
209. The output voltage is the sum of the input V0 = I0 × R
voltage, with different weighting factors. This − 1V = 0.9mA × R
circuit is called: R = 1.1kΩ
(a) Non inverting summing amplifier
213. A typical 8 pin op-amp has pin number 6 as
(b) Ideal op - amp
the:
(c) Inverting summing amplifier (a) inverting input (b) noninverting input
(d) Non inverting amplifier (c) output (d) positive power supply
UPSC Poly.Lect.10.03.2019 APPSC Poly. Lect. 15.03.2020
Ans. (c) : For 8-pin op-amp, 6th pin is output Ans. (a) :
0 − 2 0 − 1 0 − V0
By KCL at node-A = + + =0
5k 2.5k 10k
214.
2 1 V
− − = 0
5 2.5 10
V0 = −8V
217. The output offset voltage of the circuit given
here is______(given VIo = 1.2 mV)
For the given circuit, if Vi = 0.5V, the value of

Vo will be :
(a) – 2.5V (b) – 1.25 V
(c) 2.5V (d) 1.25V
Ans. (b) : Given Rf = 25kΩ, Ri =10 kΩ, Vi =0.5 V
(a) 76 mV (b) 15.7 mV
R (c) 91.2 mV (d) 101.5 mV
V0 = − f × Vi
Ri RPSC ACF & FRO 23.02.2021
−25kΩ APPSC Poly. Lect. 15.03.2020
= × 0.5 1
10kΩ Ans. (c) Vof = VI0
Vo = −1.25V β
R in
215. where β =
R f + R in
given,
Input offset voltage (VIo) =1.2 mV
Input resistance (Rin) = 2kΩ
The given circuit represents a/an : feedback resistance(Rf) =150 kΩ
(a) inverting amplifier 2kΩ
(b) non inverting amplifier β=
150kΩ + 2kΩ
(c) voltage follower
β = 0.01316
(d) difference amplifier
APPSC Poly. Lect. 15.03.2020 1
= 76
 R  β
Ans. (b) : Since Vo = Vi 1 + 2  → ( + ve) Vof = 1.2 × 76mV
 R1 
A non inverting amplifier is an operational amplifier Vof = 91.2mV
circuit with an output voltage that is in phase with the 218.
input Voltage. Inverting op-amp which produces an
output signal that is 180º out of phase.
216.
Vo for the above op-amp circuit is :

(a) – 8V (b) – 4V
(c) 8V (d) 4V
For the differential amplifier circuit shown (c) Square output when the input is trapezoidal
here Vc1 and Vc2 are respectively. (d) Rectangular output regardless of the input
(a) 12V and 2.7V (b) 12V and 9.7V waveform
(c) – 12V and 2.7V (d) – 12V and 9.7V APPSC Poly. Lect. 15.03.2020
APPSC Poly. Lect. 15.03.2020 Ans. (d) : A Schmitt trigger is a digital circuit that
Ans. (b) : From circuit Vc1 = 12V produces rectangular output regardless of the input
waveform as it saturates at a positive high for some time
12 − 0.7 12 − 0.7 and negative high for the other time. So only produces a
IE = = = 0.452mA
RE 25k square wave.
I 221. A difference mode gain of an amplifier is 2000,
Ic2 = E = 0.226mA CMRR = 100, difference mode input = 0.1 mV,
2
common mode input is 0.95 mV. The output is
∴ Vc2 = Vcc − Ic2 .R c2
(a) 438 mV (b) 219 mV
= 12 − (0.226 × 10−3 × 10 × 103 ) = 9.74V (c) 657 mV (d) 200 mV
219. Nagaland PSC (Degree) 2018, Paper-II
Ad
Ans. (b) : ∴ CMRR =
A cm
2000
∴ Acm = = 20
100
Vout = AdVd + AcmVcm
= (2000 × 0.1 + 20 × 0.95) mV
= 219 mV
222. A differential amplifier has inputs V1 = 1050
µV, the inverting terminal V2 = 950µV and
CMRR = 1000. The error in the differential
The instrument amplifier shown here is an output is
amplifier of low level signals used in process (a) 10% (b) 1%
control and commercially available in single-
package units. Vo for the instrument amplifier (c) 0.1% (d) 0.01%
is : Nagaland PSC (Degree) 2018, Paper-II
R2  R3 
(a) v o = 1 +  (v 2 − v1 ) IES-2006
R 1  2R 4  Ad
Ans. (b) :CMRR = .........(I)
R  2R 3  A cm
(b) v o = 2  1 +  (v 2 − v1 )
R1  R4  Vo = AdVd + AcmVc
 A V 
R  R  Vo = A d Vd  1 + cm c 
(c) v o = 2  1 + 3  (v 2 − v1 )  A d Vd 
R1  R 4 
 A cm Vc 
Vo = A d Vd 1 + 
R  2R 4   CMRR A V
cm d 
(d) v o = 2  1 +  (v 2 − v1 )
R1  R3   1 V 
Vo = A d Vd  1 + × c
APPSC Poly. Lect. 15.03.2020  CMRR Vd 
Ans. (b) : It is a output of differential amplifier
V 1
 2R 3 
R2 Error in differential output = c × ×100%
Vo = 1 +  [ V2 − V1 ] Vd CMRR
R1
 R4 
V1 + V2 1050 + 950
220. A Schmitt trigger is a digital circuit that Vc = = = 1000µV
2 2
produce
Vd = V1 – V2 = (1050 – 950) = 100µV
(a) Rectangular output when the input is
1000
sinusoidal so error in differential output = × 100
(b) Sinusoidal output when the input is 1000 × 100
rectangular = 1%

223. The output voltage for the open loop 225. The circuit shown below is a
differential amplifier of given figure is (Assume
Vin1= 5µV DC, Vin2 = -7µV DC, A = 200,000)
(a) Half-wave rectifier (b) Average detector

(c) Peak detector (d) Clamping circuit
TNPSC AE-2019
IES-1997
(a) 10V (b) 2.4V Ans. (c) : Peak detector is a circuit which is used to
(c) -20V (d) -1.4V detect the peak of the applied input signal. It basically
TNPSC AE- 2019 follows the input voltage and store the peak voltage.
Ans. (b) : Open loop differential amplifier
The given circuit is known as Peak detector.

226. In the circuit shown below, find Io
Vd = Vin1 –Vin2
hence, Vd = ( 5+7) µV
Vd = 12µV
Vout = AVd
Vout = 200000 × 12×10-6 Vs R L Vs
= 2. 4 V (a) (b)
Rs (RL + Rs ) Rs
224. The transfer function of a second order low
pass filter shown in Figure is Vs  1 1 
(c) (d) Vs  + 
RL R
 s R L 

Ans. (b) :
1
(a)
R C s + 3RCs + 1
2 2 2
RCs
(b)
R 2 C 2s 2 + 3RCs + 1
Vo − Vs
R 2 C 2s 2 + 1 Io =
(c) RL
R 2 C 2s 2 + 3RCs + 1
 R   R + RL 
R 2 C 2s 2 And Vo = 1 + L  Vs =  s  Vs
(d)  R s   Rs 
R 2 C 2s 2 + 3RCs + 1
TNPSC AE- 2019  Rs + RL 
  Vs − Vs
Ans. (a) : Transfer function of second order low pass  Rs   R + RL − Rs 
Then, I o = = Vs  s 
filter RL  R sR L 
Vo ( s ) 1 V
H(s) = = Io = s
Vi ( s ) s 2 R 2 C 2 + 3sRC + 1 R s

227. Frequency at which the gain of op-amp is zero
decibel is called
(a) α cut off frequency
(b) α cut off frequency (a)
(c) gain crossover frequency
(d) unity gain cross over frequency
TNPSC AE-2013
Ans. (d) : The frequency at which the magnitude is
equal to one is called unity gain frequency.
In dB, 20 log10 (1) = 0 dB (b)
If G ( jω) H ( jω) = 1 (Q log10 1 = 0 )
228. OPAMP circuit given below is a __________
(c)
(a) Differentiating Amplifier

(b) Integrating Amplifier
(c) Differential Amplifier
(d) Summing Amplifier (d)
(e) Inverting Amplifier
CGPSC SO 14.02.2016
DRDO-2008
Ans. (b) : An integrator is an Op-Amp circuit whose
output is proportional to the integral of input signal. An
integrator is basically an inverting amplifier where we
replace feedback resistor with a capacitor of suitable
value (e)
CGPSC SO 14.02.2016
Ans. (a) : (1) Vin < 3 : Vout = Vin
(2) Vin > 3 ; Vout = 3V
−1
t
RC ∫0
Vout = Vin (t)dt
229. Which of the five waveforms of Vout predicts 230. Out of following circuit is _______
the correct output of circuit for Vin as shown
below:
(a) 3 V (b) 6 V
(c) 9 V (d) 12 V
(e) 24 V
CGPSC SO 14.02.2016
Ans. (d) : 232. In the given block diagram, which is the
sampling element?
Apply KCL at node x

3− x 3− x
+ =0 (a)Voltage divider using R1 and R2
10 10 (b)Transistor Q2
3− x +3− x = 0 (c)Op-amp
x=3 (d)R3 and Zener diode
Virtual ground concept UPRVUNL AE -19.07.2021, Shift-II
y = 3V Ans. (a) : In given circuit voltage divides using R1 and
Apply KCL at node y- R2 are act as sampling element.
233. Consider the following :
0 − 3 3 − Vout
= 1. Oscillator
10 30 2. Emitter follower
−9 = 3 − Vout 3. Cascaded amplifier
−12 = − Vout 4. Power amplifier
Which of these use feedback amplifiers ?
Vout = 12V (a) 1 and 2 (b) 1 and 3
231. The circuit shown in the fig. below is a (c) 2 and 4 (d) 3 and 4
IES - 2009
Ans. (a) : Oscillator and emitter follower circuit are
used as a feedback amplifier. Most oscillators use
positive feedback.
Common-collector is also known as emitter follower.
234. In the given circuit, assume the op-amp is ideal
and the transistor has a β of 20. The current Io
(in µA) flowing through the load ZL is:
(A1 & A2 are ideal op-amps)

(a)Logarithmic Multiplier
(b)Logarithmic Amplifier
(c)Antilog Amplifier
Ans.(c): For antilogarithmic amplifier,
 1  R1 
V0 = RI f anti log  − Vs .  
 ηVT  R 1 + R 2   (a) 100 (b) 200
(c) 300 (d) 400
V0 = k1anti log ( k 2 Vs ) OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
kT Ans. (c) : By using virtual ground concept,
Where, VT =
q V – = V+ = 2V
η = Ge (1) and Si ( 2 ) 5–2 1
IC = = mA
10.5 × 103 3.5
If = forward current
I 1
V0 ∝ Anti log Vs IB = c = mA
β 3.5 × 20
1 237. The amplifier has a gain of –10 and input
IB = mA resistance of 10 kΩ. The value of Ri and Rf are
70
respectively:
 1 1 
I E = I0 = IC + I B =  +  mA
 3.5 70 
I E = 300µA
235. An Instrumentation amplifier generally uses
the following number of op-amp:
(a) 1 (b) 2
(c) 3 (d) 4
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I (a) 10 kΩ and100 kΩ (b) 1 kΩ and10 kΩ
Ans. (c) : Instrumentation amplifier
(c) 5 kΩ and100 kΩ (d) 10 kΩ and 200 kΩ
Ans. (a) :
–R f
An instrumentation amplifier is usually employed to A v = , R i = 10 kΩ , Av = –10
amplify low-level signals, rejecting noise and Ri
interference signals. R f = –A v R i
Hence the instrumentation amplifier contains 3 op-
amps. Rf = +10 × 10 kΩ
236. For the op-amp shown in the figure, the bias Rf = 100 kΩ
currents are lb1 =450 nA and lb2=350 nA. The 238. In the circuit shown below the op-amps are
values of the input bias current (lB) and the ideal. The Vout in volts is:
input offset current (lf) respectively are:
(a) 400nA and 50 nA (b) 400 nA and 100nA (a) 10 (b) 8

(c) 800 nA and 50 nA (d) 800 nA and 100 nA (c) 6 (d) 4
Ans. (b) : Bias current and voltage- GATE-2013
Ans. (b) :
Input bias current (IB)

I +I
I B = B1 B2
2
450 + 350
= = 400nA
2
Input offset current
I io = ( I B1 – I B 2 )
Vout = [1 × 2 + 2 ] × 2 = 8V
= ( 450 – 350 ) nA = 100nA

239. Assume that the op-amp of the figure is ideal. if Ans. (a) :
Vi is a triangular wave, then V0 will be:
By apply nodal analysis at inverting node,

Va Va − V1
(a) Square wave (b) Sine wave + =0
R R
(c) Triangular wave (d) Parabolic wave
V1 = 2Va ……… (i)
Apply nodal analysis at non-inverting node,
Ans. (a) : Differentiator-
Va Va − Vs
dv + =0
Vo = –RC 2R 2R
dt
Vs = 2Va ………. (ii)
From equation (i) and (ii),
Vs = V1 = 2Va
Apply nodal analysis at V1 ,
V1 − Vo V1 − Va V1
+ + =0
R R R
If Vi is a triangular wave, then V0 will be square wave. 3V1 − Va = V0
240. The following configuration is an example of V 5V
positive feedback system: V0 = 3Vs − s = s = 2.5Vs
2 2
(a) Inverting amplifier
242. The output voltage for the given circuit is
(b) Non-inverting amplifier V0 = –5V1 + 3V2. Then the value of R1 and R2 is
(c) Schmitt trigger
(d) None of these
Ans. (c) : The Schmitt trigger or bistable multivibrator
uses positive feedback with a loop-gain greater than
unity to produce a bistable characteristic.
(a) R1 = 25 kΩ and R2 = 25 kΩ
(b) R1 = 25 kΩ and R2 = 50 kΩ
(c) R1 = 50 kΩ and R2 = 25 kΩ
(d) R1 = 50 kΩ and R2 = 50 kΩ
Ans. (d) :
Positive feedback occurs because the feedback resistor
is connected between the output and non-inverting input
terminals.
241. For the circuit shown below, assume that the
OPAMP is ideal. Which one of the following is
TRUE?
Given, V0 = −5V1 + 3V2

Apply KCL,
VA − V1 VA − V0
+ ...( i )
R1 Rf
(a) V0=2.5Vs (b) Vo = Vs
VB − V2 VB  1 1  V2
(c) V0=1.5Vs (d) Vo=5Vs + = VB  + =
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I R1 R2 R
 1 R 2  R1

 1 1  V1 V0 Apply KCL,
VA  + − = V01 − 0 V01 − V0
 R 1 R f  R1 R f + =0 ...( ii )
1k 2k
V2
VB = ...( ii ) −1 −1 − V0
+ =0
 R1 
1 +  1k 2k
 R2  −1 − V0 = 2
R  V V0 = −3
V0 = VA  f + 1 − 1 ( R f )
 1  R1
R 244. An op - amp having input voltage Vi1 = 150µV
VA = VB virtual ground and Vi 2 = 140 µV, differential gain Ad = 4000
 Rf  and CMRR = 105, The output voltage of op -
 + 1 amp will be
R
V0 =  1  V −  R f  V …………(iii)
2   1 (a) 45.8 mV (b) 45.102 mV
 R1   R1  (c) 40.006 mV (d) 42.6 mV
1 + 
 R2  UPPSC ITI Principal/Asstt. Director-09.01.2022
Given output voltage with eqn. (iii) Ans. (c) : A d = 4000, CMRR = 105
Rf Vi1 = 150µV, Vi2 = 140µV
=5
R1
Op-amp output voltage,
250kΩ
R1 = = 50kΩ  1 V 
5 Vo = A d Vid 1 + × c
By calculating R 2 = 50kΩ  CMRR Vd 
Q Vd = 150 − 140 = 10µV,
243. Assuming ideal op-amps in the circuit shown
below, the output voltage v0 will be 150 + 140
VC = = 145µV
2
 1 145 
Vo = 4000 ×10 1 + 5 . = 4 ×104 [1.000145]
 10 10 
Vo = 40005.8 µV
Vo 40mV
245. The circuit shown below employs +ve feedback
(a) 21 V (b) -21V and is intended to generated sinusoidal
oscillations.
(c) 2V (d) -3V
Ans. (d) :
If at a frequency f0, feedback factor β(f) =

In Ist op-amp, Vs(f)/V0(f) = 1/6, then to sustain oscillation at this
Apply KCL at node VA, frequency is
VA − 2 VA − V0l (a) R2 = 6R1 (b) R2 = 5R1
+ =0 ...( i ) (c) R2 = R1/6 (d) R2 = R1/5
1 2k
VB − 1
=0 Ans. (b) :
1
VB = 1 ( VA = VB ) virtual ground
put value equation….(i)
1– V01 = 2
V01 = –1
In 2nd op-amp,

∆Vf ( t ) 1
249. For the circuit with an ideal OPAMP shown in
β(f) = = <0 the figure, VREF is fixed.
v0 ( f ) 6
Loop gain = 1
A ⋅β = 1
OP.amp is non investing mode.
R
Gain of op.amp = 1 + 2
R1
R2
6=1+
R1
R2 = 5R1 If VOUT= 1 volt for VIN=0.1 volt and VOUT=6
246. A buffer is a device that has volt for VIN=1 volt, where VOUT is measured
(a) a high input impedance and a low output across RL connected at the output of this
impedance OPAMP, the value of RF/RIN is
(b) a high input as well as output impedance (a) 5.555 (b) 2.860
(c) a low input impedance and a high output (c) 3.825 (d) 3.285
impedance GATE-2021
(d) a low input impedance as well as output Ans. (a) : Case-1
impedance When Vin = active , VREF = 0
RPCS Lect.-2011
Ans. (a) : Unity gain buffers have a high input
impedance and low output impedance. The voltage
follower is used as a buffer amplifier, isolation
amplifier, unity gain amplifier (output follows the
input).
247. Gain of 1st amplifier is 50; 2nd amplifier is 10,
then both in cascaded manner overall gain
is_______.
−R F
(a) 500 (b) 60 Then V01 = × VIN –––––(i)
(c) 40 (d) 30 R IN
AAI-2015 Case-2
Ans. (a) : Given, when VIN = 0 , VREF = active
First-stage gain ( A1 ) = 50  V × R2  RF 
Then , V02 =  REF  1 +  ––––––(ii)
and 2 amplifier gain ( A 2 ) = 10
nd
 R1 + R 2  R IN 
∴ Total gain of a two stage cascaded amplifier,
A T = A1 × A 2
= 50 × 10
= 500
248. For an OPAMP, unity gain frequency is 106 if
gain is 20, What is the Bandwidth of the op-
amp _____.
(a) 60kHz (b) 50kHz
(c) 40kHz (d) 100kHz Q From equation (i) and (ii)
NPCIL-2015 So, Total output voltage,
Ans. (b) : Given value, VOUT = V01+ V02
Unity gain frequency = 10 6
 V × R2  RF  RF
VOUT =  REF  1 + − × VIN
and gain = 20  1R + R 2  R IN  R IN
Q Gain × Bandwidth = 106 Given VREF is fixed then non inverting terminal voltage
20 × Bandwidth = 10 6 V+ is fixed.
1000000 VREF × R 2
Bandwidth = V+ =
20 R1 + R 2
Bandwidth = 50kHz For VIN = 0.1 volt, VOUT = 1V

 R  V × R 2  R F Then V0 = 0
1 = 1 + F  REF − × 0.1 ∴ Putting value equation (i),
 R IN   R1 + R 2  R IN
VIN − 0 VREF
RF  R  V  − =0
1+ × 0.1 = 1 + F   REF × R 2  ––(iii) R R
R IN  R IN   R1 + R 2  VIN = VREF
For VIN = 1V, VOUT= 6V
R R 251. Using a µA 741 OPAMP, a first order low pass
6 = 1 + F × 0.1 − F ×1 filter is designed to have a cutoff frequency of
R IN R IN
1kHz. If the value of the capacitance used is
RF
6 = 1+ ( 0.1 − 1) 1nF, find the value of R.
R IN (a) 159.15 kΩ (b) 160.87 kΩ
5 =
RF
× ( −0.9 ) (c) 172.42 kΩ (d) 127.78 kΩ
R IN UPPCL AE-05.11.2019
RF −5 Ans. (a) : Cutoff frequency of filter is given by
So, = = −5.55
R IN 0.9 1
fc =
RF 2π ⋅ R 2 C
or = 5.55
R IN 1
R2 =
250. Consider the circuit with an ideal OPAMP 2πf c ⋅ C
shown in the figure.
1
R2 =
2π × 10 × 1× 10−9
3
1000 500
R2 = kΩ = kΩ
2π π
R 2 = 159.15kΩ
252. The reason for using a precision OPAMP based
rectifier diode for detecting weak AM signals is
that.
(a) the demodulation is easy
(b) the signal is amplified and power is less.
(c) the noise is less and easy to filter
Assuming VIN << VCC and VREF << VCC , the (d) the cut-in voltage of the diode is reduced.
condition at which VOUT equals to zero is UPPCL AE-05.11.2019
(a) VIN=0.5 VREF (b) VIN=2+VREF
Ans. (d) : The major limitation of conventional
(c) VIN=2VREF (d) VIN=VREF
rectifier is that it cannot rectify AC voltage below a
GATE-2021
forward voltage drop of diode. So the precision rectifier
Ans. (d) : makes it possible to rectify the input voltage of a very
small magnitude, even less than the forward voltage
drop of the diode.
253. An OPAMP RC phase shift oscillator has three
pairs of R and C ( R = 22kΩ,C = 10pF ) . Find
the frequency of oscillation.
(a) 356.12 kHz (b) 312.98 kHz
In Ideal case , AV = ∞ (c) 512.62 kHz (d) 295.34 kHz
V+ = V– (Virtual ground)
So, using virtual condition, UPPCL AE-05.11.2019
Vx =VY = 0 1
Ans. (d) : f =
Apply KVL at node X, 2πRC 6
VIN − 0 −VREF − 0 0 − V0 1
+ = ––––––(i) ⇒f =
R R RF 2π × 22 × 10 × 10 × 10 −12 6
3
Q Given = 0.0029548946×108
VIN << Vcc and VREF << Vcc f = 295.3 KHz

254. A simple single OPAMP inverting amplifier Ans. (a) :
has R F = 220kΩ and R1 = 10k. If two such
stages are cascaded, find the mid frequency
gain of the cascade.
(a) 53.70 dB
(b) -53.70 dB
(c) -26.85 dB
(d) 26.85 dB
UPPCL AE-05.11.2019
R f −220
Ans. (a) : A V1 = = ⇒ A V = −22
R1 10
When two amplifier are cascaded, their gain will be
multiplied
Two input balance difference amplifier
A V = A V1 ⋅ A V2 = −22 × −22 Difference Amplifier:-A differential amplifier is one
A V = 484 whose output is the difference between its two input
signals
In dB = 20 log10 484 = 20 × 2 ⋅ 684 Vo ∝ Vin1 − Vin 2
= 53.70dB Vo = A d ( Vin1 − Vin 2 )
255. A second order RC low pass filter is using 257. In order for an output to swing above and
OPAMP and two pairs of R and C. If the cutoff below a zero reference, the op-amp circuit
frequency is 2.2kHz, and the value of requires−
capacitance is 22 nF, find the value of R. (a) A negative and positive supply
(b) A wide bandwidth
(a) 4.7 k Ω
(c) Zero offset
(b) 3.3 k Ω (d) A resistive feedback network
(c) 2.2 k Ω RRB JE-01.09.2019, 3:00 PM – 5:00 PM
(d) 1.0 k Ω Ans. (a) : To get zero voltage at the output terminal for
this a small amount of DC voltage has to be used at the
UPPCL AE-05.11.2019
input which can be positive or negative. This method is
Ans. (b) : For second order RC low pass filter- called off-set null method.
1 258. In a OPAMP differential mode gain is 20,000
f= CMRR is 40dB common mode gain is
2π R 1 ⋅ R 2 C1C 2
(a) 200 (b) 0
C1 = C 2 = C & R 1 = R 2 = R (c) 300 (d) 400
1 BEL-2015
f= Ans. (a) : Given that
2πRC
A d = 20000
1
R= CMRR = 40dB
2πfC
A
R=
1 CMRR = 20log d
2π × 2.2 × 103 × 22 × 10−9 Ac
20000
R = 3.3kΩ 40 = 20log
Ac
256. A circuit whose output is proportional to the 20000
difference between the input signals is A c = 100
considered to be which type of amplifier?
A c = 200
(a) Differential
(b) Common-mode 259. OP-AMP used as a tuned amplifier, the tuned
circuit connected across
(c) Operational (a) input (b) output
(d) Darlington (c) series impedance (d) feedback impedance
RRB JE-01.09.2019, 3:00 PM – 5:00 PM BEL-2015

Ans. (d) : Op-amp used as a tuned amplifier, the tuned 263. Find V0
circuit connected across feedback impedance (Zf).
Tuned amplifier are commonly used to separate a
desired frequency from a composite waveform.
260. In an Op-Amp Ad = 80dB, CMRR = 40dB, Ac
in dB
(a) 40 (b) –40 (a) –100V (b) 111V
(c) 20 (d) 60 (c) 100V (d) –89V
SAIL- 2014 SAIL- 2014
Ans. (d) :
Ans. (a) : Given value
Ad = 80dB, CMRR = 400dB
Q CMRR(dB) = Ad(dB)–AC(dB)
AC (dB) =80 – 40
AC(dB) = 40 dB
NOTE:- → CMRR =
Ad In Ideal op-amp, AV = ∞
AC V+ = V– (virtual ground)
So, VA =VB = 1V
A
→ CMRR (dB) = 20log10 d Apply Nodal analysis point A,
AC 10 − VA VA − V0
=
261. Imax= 32pA, C= 6 µF, SR in µV/Sec? 1kΩ 10kΩ
(a) 5.33 (b) 5.33×10 3
10 − 1 1 − V
= 0
(c) 1.9×103 (d) 1.9×109 1 10
SAIL- 2014 90 = 1–V0
V0 = –89V
Ans. (a) : Given that, I max = 32pA 264. If the OP-AMP shown in the figure below is
C = 6µF ideal, then the output voltage Vout will be equal
to
dV
I max = C
dt
I max dV
=
C dt
dV 32 × 10−12
= = 5.33 ×10−6
dt 6 × 10−6
dV
S.R. = = 5.33 µV sec (a) 17V (b) 1V
dt (c) 6V (d) 14V
262. Find gain of a non-inverting Amplifier, BPSC Polytechnic Lecturer-2014
Ans. (c) :
if Vi = 1 V, RF = 10kΩ, Ri = 1kΩ.
3
(a) 10 (b) 10
(c) 11 (d) ∞
SAIL- 2014
Ans. (c) : For non-inverting amplifier.
Vo  R 
= 1 + f  Q Output voltage in op-amp
Vi  R in 
 5  1+ 5  8×3
Given that, R i = 1kΩ R F = 10kΩ Vi = 1V V0 = −2 ×   +  ×
 1   1  1+ 8
Vo  10 
Av = = 1 +  8
Vi  1  V0 = − 2 × 5 + 6 ×
3
A v = 11 V0 = –10+16
V0 = 6V

265. The zero level detector is one application of a Given circuit configuration – Inverting because input is
(a) Comparator connected to the inverting terminal.
(b) Summing amplifier Gain in op-amp at inverting terminal,
(c) Integrator V R
(d) Differentiator AV = 0 = − 2
Vs R1
269. Slew rate of the op amp (S) is ______(f is
Ans. (a) : The zero level detector circuit is an important operating frequency and Vm is the output
application of the op-amp comparator circuit. voltage amplitude):
266. A low-pass filter circuit is basically (a) 2πfVm (b) 2πf/Vm
(a) differentiating circuit with low time constant (c) 2m/2πf (d) (1/2πfVm)
(b) differentiating circuit with larger time UPMRC AM – 2020
constant GPSC Asstt. Prof. -11.04.2017
(c) an integrating circuit with low time constant UPPCL AE-16.11.2013
(d) an integrating circuit with larger time Ans. (a) : Slew rate – The maximum rate of change of
constant.
the output voltage ( V0 ) of the op-amp for each unit
Ans. (d) : The filter circuit which allows only low pass time.
frequency components and blocks all other higher  dV 
frequency component is called a low pass filter. A low- SR =  0  = 2πfVm V / µ sec
pass filter circuit is basically an integrating circuit with  dt max
larger time constant. 270. A non-inverting amplifier (in closed loop)
267. A differential amplifier is invariably used in incorporates an op-amp having a gain of 1000.
the input stage of all OP-AMPs. This is done If the nominal gain is 5 then the gain error of
basically to provide OP-AMPs with a very the circuit will be:
high. (a) 5000% (b) 5%
(a) CMRR (b) bandwidth (c) 50% (d) 0.5%
(c) slew rate (d) open-loop gain. UPMRC AM - 2020
TRB Poly. Lect. -2012 Ans. (d) : Given,
Mizoram PSC IOLM-2010, Paper-II Nominal gain, A V = 5
IES-2001 and gain A = 1000
Ans. (a) : A differential amplifier is invariably used in Q Loop gain = A ⋅β
the input stage of all OP-AMPs. This is done basically
to provide OP-AMPs with a very high CMRR. 1 1
Where β = =
268. AV 5
1
∴ Loop gain = × 1000 = 200
5
Therefore, percentage error,
1
%E = ×100
(1 + loop gain )
1
= × 100
(1 + 200 )
The configuration and the gain of the above = 0.49%
circuit is _____ and _____.
%E ≅ 0.5%
R R
(a) inverting, − 2 (b) inverting, 1 + 2 271.
R1 R1
 R  R2
(c) non −  1 + 2  (d) non inverting,
 R1  R1
UPMRC AM - 2020
Ans. (a) :
The Op-amp circuit configuration is:
(a) unity gain buffer
(b) a square root amplifier
(c) a precision rectifier
(d) a logarithmic amplifier
UPMRC AM - 2020
Ans. (c) : Analysis the circuit diagram, Ans. (b) :
Case-I– Diode work as forward biased (Diode on)
when Vin > 0 then,
Vo = V+ = V– = Vin
It is so because the forward biased diode provide the
closed loop feedback path.
Case-II– Diode is reverse biased then Op-amp work as
Apply KCL at inverting node amplifier,
a open loop (Diode off).
0 − Vin 0 − Vo
+ =0
R in 1 Cs
0 − Vin
= CsVo
R in
Vo(s) −1
=
Vin(s ) sR in C
274. A sinusoidal input which can be reproduced in

Since, the circuit is a precision half wave rectifier. an op-amp without any distortion having slew
rate of 10π V.(µs)–1 and 5 V peak output
272. Input resistance of inverting amplifier as
amplitude, has the maximum frequency of
shown in figure with ideal op-amp is :
(a) 1 kHz (b) 1 MHz
(c) 31.42 kHz (d) 31.42 MHz
Ans. (b) : Given,
Slew rate = 10π V µ sec
Vm = 5V
(a) ∞ (b) zero  dV 
(c) 1 kΩ (d) 10 kΩ Q Slew rate =  o  = 2πfVm
 dt max
10π
Ans. (c) : = 2π × f × 5
V −0 10−6
Ii = i f = 106 = 1MHz
1kΩ
Vi 275. Which of the following is NOT true for Schmitt
= 1kΩ Trigger ?
Ii
(a) Schmitt trigger can be used as sine-to-square
R in = 1kΩ wave converter
273. What is the transfer function of the following (b) Schmitt trigger uses op-amp in open loop
circuit? mode
(c) Hysteresis exists in Schmitt trigger
(d) All of these
Ans. (b) : A Schmitt trigger is a comparator circuit
with hysteresis implemented by applying positive
feedback to the non-inverting input of a comparator or
Vout ( s ) −1 Vout ( s ) −1 differential amplifier and Schmitt trigger uses
(a) = (b) =
Vin ( s ) R in C Vin ( s ) sR in C operational amplifier in closed loop with a positive
V (s) V (s ) feedback.
−s 1
(c) out = (d) out = 276. For the following circuit, determine the output
Vin ( s ) R in C Vin ( s ) sR in C
voltage V0 in terms of input voltages V1 and V2,
NLC GET -24.11.2020 assuming A1 and A2 are ideal op-amps.
Virtual ground concept-
RB
V1 = V2 = × V0 …………………(i)
RA + RB
V1
Iin = , V1 = Iin × R s
Rs
from equation (i) put the value of V1
RB V
Iin = × 0
(a) 11V2 − V1 (b) V2 − 11V1 R A + R B Rs
(c) 11( V2 − V1 ) (d) None of these  R 
V0 = Iin R s 1 + A 
ISRO Scientist December, 2017  RB 
Ans. (c) : Output voltage at inverting node-
278. The voltage gain versus frequency curve of an
 R  op-amp is shown in the figure. The gain
Vo = 1 + f  Vi
 R1  bandwidth product of op-amp is
In first op-amp,
 1 11
V01 = 1 +  V1 = V1 ……… (i)
 10  10
In second op-amp,
 −10   10 + 1 
V02 =   V01 +   V2 ……(ii)
 1   1  (a) 200 Hz (b) 200 MHz
From equation (i) and (ii) (c) 200 kHz (d) 2 MHz
−10 11  10 + 1  LMRC AM (S&T)-13.05.2018
Vo = × V1 +   V2 IES-1999
1 10  1 
= −11V1 + 11V2 Ans. (c) : Given value,
= 11( V2 − V1 ) Gain = 80dB = 104
Bandwidth = 20Hz
277. In the following circuit, find the output voltage
V 0: ∴ Gain bandwidth product = 20 ×104
= 200kHz
279. In the op-amp circuit shown below (assuming
ideal op-amp)
(a) ( R A R B ) × Iin × R s
(b) Iin × R s × (1 + R A / R B )
(c) ( R B / R A ) × Iin × R s
(d) Iin × R s × (1 + R B / R A )
ISRO Scientist December, 2017 (a) Vo = –5V (b) Vo = 0 V
Ans. (b) : (c) Vo = +5V (d) Vo = –2V
LMRC AM (S&T)-13.05.2018
IES-2003
Ans. (b) : Ideal op-amp, A V = ∞, V+ = V– virtual
ground.
At node 2-
RB
V2 = × V0
RA + RB

output voltage in op-amp , Ans. (c) : Given
 22   22   22 
V0 = −0.5 ×   + 1 + ×  × 0.5
 2.2   2.2   2.2 + 22 
11× 11
V0 = −5 + = −5 + 5
24.2
V0 = 0V
280. For a voltage follower circuit using an op-amp, Q Diode connected in op-amp feedback reverse bias so,
which of the following is true ? Output voltage in op-amp Vo = 0
(a) both input and output impedance are very
because diode not conduct or behave as a open circuit.
large
(b) input impedance is very large and the output 283. The voltage at the output of the circuit shown
impedance is very small below will be
(c) input impedance is very small and the output
impedance is very large
(d) both input and output impedance are very
small
(a) zero (b) +VCC
RPSC Lect.2011
BSNL(JTO)-2002, 2001
(c) triangular wave(d) square wave
BSNL(JTO)-2002, 2001
Ans. (b) : Voltage follower circuit characteristics–
Input Impedance = High Ans. (a) : Output voltage in given operational
Output Impedance = Low amplifier Vo = 0V
Current gain = High 284. The input Vi to the circuit shown in figure
Power gain = High below is a square wave of amplitude ± 1 V and
=
Voltage gain Unity frequency 100 Hz.
Voltage follower used in buffer amplifier, isolation
amplifier, unity gain amplifier.
281. An op-amp based inverting amplifier has a
gain of -10 and a bandwidth of 100 kHz. If the
gain of the amplifier is reduced to unity, its
bandwidth will changes to
(a) 10 kHz (b) 100 kHz
(c) 1 MHz (d) 10 MHz Assuming ideal components, the peak-to-peak
BSNL (JTO)-2001 amplitude of the output V0 is :
Ans. (c) : Gain × Bandwidth = Constant (a) 2 V (b) 5 V
Then, (Gain)1× (Bandwidth)1= (Gain)2×(Bandwidth)2 (c) 10 V (d) 12 V
DRDO-2009
10 × 100 × 103
(Bandwidth)2 = = 106 = 1MHz Ans. (c) :
1
282. When the diode is ideal in the circuit shown
below, the output voltage will be close to
the peak-to-peak amplitude of output voltage.

V 1
(a) 0.7 volts (b) +5 V V0 = =
fRC 100 × 1000 × 10−6
(c) 0 volts (d) -VCC
V0 = 10Volt
BSNL (JTO)-2001
285. An inverting amplifier is designed for a gain of Ans. (d) : The gain at the centre frequency for the band
40 dB using an op-amp having open loop gain pass filter,
of 250000 and unity-gain frequency of 750 1
KHz. The bandwidth of the designed amplifier f =−
R1 C2
is : +
R 2 C1
(a) 2.5 kHz (b) 7.5 kHz
(c) 750 kHz (d) 250 kHz 288. For the Schmitt trigger circuit shown in figure,
DRDO-2009 assuming diodes and op-amp are ideal, the
Ans. (b) : Given value, value of lower and upper threshold points of
20 log10 A V = 40dB voltage transfer characteristics, respectively,
are
log10 A V = 2
A V = 100 Q Gain × BW = 750 ×103
750 × 103
B.W =
100
= 7.5kHz
286. Assuming ideal op-amps and that the op-amp
U2 is not saturated, the output voltage
waveform in the circuit shown in figure below
is a :
(a) –8 V, +5 V (b) –5 V, +5 V
(c) –5 V, +8 V (d) –8 V, +8 V
BSNL(JTO)-2009
(a) pulse (b) sine wave Ans. (c) : Given,
(c) triangular wave (d) square wave
DRDO-2009
Ans. (c) : Given circuit, in first op-amp, sine wave
converted into square wave. In second op-amp, square
wave converted into triangular wave because second
op-amp is integrator circuit or feedback op-amp across
capacitor.
287. The gain at the centre-frequency for the band
pass filter shown in figure shown in figure
below is :
(1) When Vo = Vsat = +10V
D1 = OFF and D 2 = ON
2
then VUTH = ×10 = 8V
2 + 0.5
(2) When Vo = Vsat = −10V
D1 = ON and D 2 = OFF
R 1C1 R 2 C2 2
(a) − (b) − VLTH = × ( −10 ) = −5V
R 2 C2 R 2 C2 2+2
R C  1 289. The circuit shown in figure oscillates at an
(c) −  1 + 2  (d) −
 R 2 C1  R1 C 2 angular frequency of ω at a particular R. The
+
R 2 C1 values of ω (in rad/sec) and R (in kΩ),
DRDO-2009 respectively, are

291. For the given figure, the output voltage is
Rf  R + Rf 
(a) V0 = − V2 +  V1 
R R
 1 + R 2 
R  R + R f  R + R f 
(b) V0 = − V2 +   V1 
Rf  R f  R 1 + R 2 
Rf  R + R f   R1 + R 2 
(a) 105 and 20 (b) 2 × 105 and 20 (c) V0 = − V2 +   V1 
R  R  R + Rf 
(c) 2 × 105 and 10 (d) 105 and 10
BSNL(JTO)-2009 Rf  R + Rf  R2 
(d) V0 = − V2 +   V1 
Ans. (a) : Given, R  R  1
R + R 2 
L = 10mH, C = 0.01µF
ESE-2021
1
Angular Frequency ω = Ans.(d) :
LC
1
ω=
10 ×10 × 0.01× 10−6
−3
ω = 105
1 5
And =
1 + R 5 + 100
100 Q Output voltage at inverting node,
R= = 20KΩ
5 −R f
V01 = × V2
290. What is the maximum closed-loop voltage gain R
that can be used when the input signal varies and output voltage at non inverting node,
by 0.2 V in 10 µs with slew rate of op-amp
 R + R f   R 2 V1 
SR = 2 V µs? V02 =  ⋅ 
 R  R1 + R 2 
(a) 40 (b) 50
(c) 80 (d) 100 So, output voltage,
ESE-2021 −R f  R + R f   R 2 V1 
Ans.(d) : Given value, V0 = V01 + V02 = V2 +   
R  R   R1 + R 2 
Vm = 0.2
292. Inside a 741 op-amp the last functional block is
t = 10µs
a
SR = 2V µs (a) differential amplifier
 dV  (b) level shifter
Q Slew rate =  0 
 dt  max (c) class-A power amplifier
dV0 (d) class-AB power amplifier
SR = = 2V µS DRDO-2008
dt
Q Input signal varies by 0.2 V in 10µS Ans. (d) : Inside a 741 op-amp the last function block is
complementary symmetry push-push amplifier or Class
d V0 dt
So, voltage gain A V = AB power amplifier.
dVi dt
293. Assume the op-amps in figure to be ideal. If the
2 input signal vi is a sinusoid of 2 V peak-to-peak
AV =
0.02 and with zero DC component, the output signal
A V = 100 v0 is a

V+ = 5.001 Volt
V– = 4.999 Volt
∴ Output voltage of the op-amp.
 1 V 
V0 = A d ( V+ − V− ) 1 + ⋅ C
 CMRR Vd 
Vd = 5.001 − 4.999 = 0.002V
(a) sine wave (b) square wave V+ + V− 5.001 + 4.999
(c) pulse train (d) triangular wave VC = =
2 2
DRDO-2008 VC = 5
Ans. (d) : Given,
 1 5 
Vi = 2V peak to peak voltage Vo = 2000 × ( 5.001 + 4.999 ) 1 + ×
 1000 0.002 
 5
Vo = 2000 × 0.002 1 + 
 2
Vo = 4 [1 + 2.5] = 4 × 3.5 = 14V
295. For the circuit in figure, if the value of the
capacitor C is doubled, the duty-cycle of the
Case-I- First op-amp. It converts the sinusoidal signal output waveform v0
into a two level fixed square wave.
When V– = Vi > V+
then Vi = +12 Volt
And when, V– < V+ then Vi = −12 Volt.
Case-II- Second op-amp. It is an integrator non-linear
op-amp circuit. So, it converts square wave into a
triangular wave.
−1
RC ∫
V0 = Vid dt
(a) increases by a factor of 2

(b) increases by a factor of 1.44
(c) remains constant
(d) decreases by a factor of 1.44
DRDO-2008
RA + RB
Ans. (c) : Duty cycle = ×100
R A + 2R B
Therefore, Independent of capacitor value.
296. Assume the op-amp in the circuit of figure to
be ideal. The value of the output voltage v0 is
294. An op-amp is ideal except for finite-gain and

CMRR. Given, the open loop differential gain
Ad = 2000, CMRR = 1000, the input to the non
inverting terminal is 5.001 V and the input to
the inverting terminal is 4.999 V, the output
voltage of the op-amp is
(a) 14V (b) 24V
(c) –6 V (d) –8 V
DRDO-2008
Ans. (a) : Given value, (a) 3.2 vi (b) 4 vi
A d = 2000 (c) 9 vi (d) 10 vi
CMRR = 1000 DRDO-2008

Ans. (b) :
(a) 15 V (b) 27 V
(c) 13 V (d) 14 V
GATE-2022
Ans. (c) : Given circuit,
2 2
Va = × Vi = Vi
2+3 5
Then
2  9 2
V0 = Vi 1 +  = Vi ×10
5  1 5
V0 = 4Vi Case-I- V0 = +15V and
297. An ideal OPAMP circuit with a sinusoidal D1 = ON and D 2 = OFF
input is shown in the figure. The 3 dB
That capacitor charge,
frequency is the frequency at which the
magnitude of the voltage gain decreases by 3 VC = 15 × R = 5V
dB from the maximum value. Which of the
max
R + 2R
options is/are correct ? Case-II- If V0 = −12V
D1 = OFF and D 2 = ON
That, capacitor discharges
−12 × 2R
VCmin =
2R + R
VCmin = −8V
(a) The circuit is a low pass filter. So, capacitor voltage,
(b) The circuit is a high pass filter. VC = VCmax − VCmin
(c) The 3dB frequency is 1000 rad/s.
1000 VC = 5 − ( −8 )
(d) The 3 dB frequency is rad/s.
3 VC = 13V
GATE-2022, 2012 299. A circuit with an ideal OPAMP is shown. The
Ans. (b,c) : Bode plot for the magnitude (in dB) of the gain
transfer function
( A V ( jω ) = Vout ( jω ) /Vin ( jω ) ) of the circuit is
also provided (here, ω is the angular frequency
in rad/s). The values of R and C are ______.
Q Given circuit is a high pass filter.

1 1
Q ωC = = = 1000rad / sec.
R1C1 103 ×10−6 (a) R = 3 kΩ, C = 1 µF
298. For the following circuit with an ideal OPAMP, (b) R = 1 kΩ, C = 3 µF
the difference between the maximum and the (c) R = 4 kΩ, C = 1 µF
minimum values of the capacitor voltage (Vc) is (d) R = 3 kΩ, C = 2 µF
_______. GATE-2022
Ans. (a) : Given, Ans. (d) : At low frequency
1
ω → 0, X C =
ωC
X C = ∞ ( open circuit )
Maximum gain = 12dB

20 × log A max = 12
20log10 A m = 12
Am = 4
R2
Where A m = 1 +
R1
Apply KCL at virtual node:-
R
∴ 1+ 2 = 4 ⇒ R 2 = 3R1 0 − Vi 0 − V0
R1 +0+ =0
1kΩ 100 kΩ
R 2 = R = 3 ×1
V0 −Vi
R = 3kΩ =
100 K 1K
Q log10 ωc = 3
V0 = −100Vi
ωc = 103
ωc = 1000 rad sec. V0
= −100
Vi
1
Q ωc = V0
R 3C AV = = 100
Vi
1 1
C= = AV in dB = 20 log10 AV
R 3 ωc 1000 × 1000
= 20 log10100
C = 1µF
= 40 dB
300. The main advantage in using three op-amp
instrumentation amplifier over a single stage 302. A low pass filter as shown in following figure is
op-amp differential amplifier lies in built using an operational amplifier having
(a) Higher value of CMRR unity gain bandwidth of 1 MHz. What is the
(b) Lower noise figure bandwidth of this circuit?
(c) Elimination of the need for accurate matching
of resistor
(d) Simplicity of gain adjustment
Ans. (c) : The main advantage in using three op-amp
instrumentation amplifier over a single stage op-amp
differential amplifier is for elimination of the need for
accurate matching of resistor. There is no need for (a) 1 kHz (b) 10 kHz
accurate matching of resistor. (c) 100 kHz (d) 500 kHz
301. The very low frequency gain of the low pass ISRO Scientist Engg.-2013
filter shown in the given figure is
Ans. (c) : As per question diagram, circuit given is the
integrator or low pass filter.
Bandwidth is given by
1
BW =
2πRC
As given R = 10 kΩ & C = 160 PF
∴
1
(a) 10 dB (b) 20 dB BW = = 99, 472 100,000Hz
2π ×10 ×10 ×160 × 10−12
3
(c) 30 dB (d) 40 dB
= 100kHz
303. The probability that an electron in a metal 0 − V 0 − VC
occupies the fermi level at any temperature, at
in
+ =0
R R
any temperature.(>0K)
VC = − Vin
(a) 0 (b) 1
(c) 0.5 (d) 1.0 Again apply nodal analysis at node B,
Nagaland PSC CTSE (Degree) -2015, Paper I VB − VC + VB − Vin + VB − V0 = 0
Ans. (c) : For the fermileval equation we know R1 R2 R3
1 0 − VC 0 − Vin 0 − V0
f (E) = ( E − Ef ) KT = + + =0
1+ e R1 R2 R3
So, the probability that an electron occupy the fermi Put value,
1
level at any temperature will be = = 0.5 − ( − Vin ) − Vin − V0
1+1 + + =0
R1 R2 R3
304. For which of the following conditions, the
circuit shown below will function as precision V0 R 3 .Vin ( R 2 − R 1 )
=
full wave rectifier? R3 R 1R 2
R 3.Vin ( R 2 − R 1 )
V0 = if ( R 3 = R 2 )
R 1.R 2
R 2 .Vin ( R 2 − R 1 )
V0 =
R 1R 2
V
(a) R1 = R2 = R (b) R1 = R3 = R V0 = in ( R 2 − R1 )
(c) R2 = 2R1 (d) R1 = R2 = R3 R1
ISRO Scientist Engg.-2013 Q full wave- Vin for –ve half cycle,
Ans. (c) : V
V0 = in ( R 2 − R1 ) = Vin if ( V0 = Vin )
R1
R 2 − R1
=1
R1
R 2 − R1 = R1
R2 = 2R1
Condition – 305. The circuit shown represents
Positive half cycle,
D1 = open circuit D2 = short circuit
VA = VB= 0 (Virtual ground )
Apply nodal analysis at node B-
VB − Vin VB − VA VB − V0
+ + =0
R2 R + R1 R3
0 − Vin 0 − 0 0 − V0 (a) A bandpass filter
= + + =0 (b) A voltage controlled oscillator
R2 R + R1 R3
(c) An amplitude modulator
−R 3
V0 = ( Vin ) (d) A monostable multivibrator
R2 GATE-2014
If R 3 = R 2 Ans. (d) : This circuit represent mono stable
V0 = − Vin (+ve half cycle) multivibrater.
Vi can be used as a trigger input to change the output
Negative half cycle,
state. Charging of C1 capacitor will see that the circuit
D1 = Short circuit D2 = open circuit
output comes back to the original state.
VA = VB = 0 ( Virtual ground ) Application of mono stable Multivibrater
Q Apply nodal analysis at node A, (i) Pulse Generation
VA − Vin VA − VC (ii) Delay circuit
+ =0
R R (iii) gating circuit

Ans. (c)
(ix) Multivibrators, Voltage
Regulators & power supply
1. What are the approximate values of t1, t2,
frequency and duty cycle of a 555 timer used as
an astable multivibrator respectively?
(Take C = 680 pF)
Frequency of IC 555 as astable

1.44
f=
( R1 + 2R 2 ) C
R1 = 1K Ω
R 2 = 1K Ω
C = 1µF
(a) 4.76 µsec, 6.997 µsec, 85kHz and 59.5% 1.44
f=
(b) 6.84 nsec, 9.997 nsec, 68 kHz and 59.5% (1 + 2 ) ×103 ×1×10−6
(c) 4.76 µsec, 6.997 µsec, 68 kHz and 68% = 480 Hz
(d) 6.84 µsec, 9.997 nsec, 85kHz and 68% 3. Using a 10 nF of capacitor, find the value of
ESE-2022 Resistor that yields an output pulse of 100 µs in
Ans. (a) : From question figure we can calculate the 555 time based monostable multvibrator.
t1 = TC = charging time = 0.693 (RA+RB)C (a) 5.6 kΩ (b) 2.8 kΩ
(c) 9.8 kΩ (d) 9.1 kΩ
= 0.693 ( 4.7 kΩ + 10kΩ ) × 680 ×10−12
= 0.693 (14.7kΩ ) × 680 ×10−12 Ans. (d) : Monostable Multi vibrator -
= 0.693 × 14.7 × 680 × 10 −9
= 6.927µ sec 6.997 µ sec
and t 2 = Td = discharging time = 0.693 R B C
= 0.693 × 10kΩ × 680 × 10 −12
= 0.693 × 10 × 680 × 10−9
= 4.705µ sec 4.76 µ sec
Now frequency of oscillation-
1 1
f= = = 85.96kHz T = RC ln (3) = 1.1 RC
t1 + t 2 6.927 + 4.705
The within of the output pulse is a function of only the
85kHz external time constant RC.
And duty cycle 100 µs = 1.1 × R × 10 × 10-9
Tc t 100 ×10−6
%D = = 1 R=
Tc + Td t1 + t 2
1.1×10 × 10−9
6.927 = 9.1 kΩ
= × 100
6.927 + 4.705 4. Calculate the frequency of following circuit
= 0.5955 × 100 = 59.5%
2. If R1=1 kΩ , R2=1 kΩ , C = 1µF, then the
output frequency of IC 555 as astable
multivibrator is:
(a) 4.8 kHz (b) 48 kHz
(c) 480 Hz (d) 48 Hz
(a) f = 1270 Hz (b) f =1905 Hz Where n = Number of bits
(c) f = 635 Hz (d) f = 325 Hz
Ans. (c) : T = 0.693 (RA+2RB)C
T = 0.693 ( 7.5 × 103 + 2 × 7.5 × 103 ) 0.1× 10 −6
= 1.559×10-3sec
l 103
f= = 7.
Consider the following statements :
T 1.559
In order to generate square wave from a
= 641.43 Hz sinusoidal input signal one can use
635Hz 1. Schmitt trigger circuit
5. For given Schmitt trigger, find the upper 2. Clippers and amplifiers.
threshold voltage. Lower threshold voltage 3. Monostable multivibrators
(Assume : the maximum output voltage swing Which of the above statements is/are correct?
is ± 14 V) (a) 1 alone (b) 1 and 2
Vut : upper threshold voltage (c) 2 and 3 (d) 1, 2 and 3
Vlt : lower threshold voltage Nagaland PSC-2018 Diploma, Paper-II
TRB Poly. Lect-2012, IES-2009, 2002, 2001
Ans. (a) :
(a) Vut = 2.33 V Vlt = -2.33 V

(b) Vut = 84 V Vlt =-84 V
(c) Vut = 1.4 µV Vlt = -1.4µV
(d) Vut = 7.31 V Vlt = -7.31 V
• Schmitt trigger is a comparator circuit with positive
RPSC ACF & FRO 23.02.2021 feedback. It works as an astable multivibrator. It
Ans. (a) : generates square wave form a sinusoidal wave form.
 R1   R1  • Clippers is a circuit that only clips the waveform.
Vut =   VH , Vlt =   VL But it cannot generate square wave from a
 R1 + R 2   R1 + R 2  sinusoidal wave.
 10   10  • Monostable multivibrator generates only square
Vut =   ×14, Vlt =   × ( −14) pulse from a sinusoidal wave form. It is also known
 10 + 50   10 + 50 
as pulse generator or pulse stretcher circuit.
= 2.33 V = – 2.33 V
8. An astable multivibrator has_______
6. For an N bit F-V converter, to ensure less than (a) One stable state (b) Two stable states
1/2 LSB output ripple, the time constant T of (c) No stable state (d) None of the above
simple RC low pass filter must be at least Nagaland PSC (CTSE) Diploma-2017, Paper II
(where T0 is the output period of the n bit Nagaland PSC CTSE (Degree)-2016, Paper II
converter). TNPSC AE- 2013
(a) T = 0.69 (n+1) T0 (b) T = (n +1) T0 Ans. (c)
(c) T = 0.69 nT0 (d) T = nT0
UPMRC AM - 2020
Ans. (a) : Frequency to voltage convertor-
(1) Counter can be used to generate a frequency. The
digital pulse can be averaged using low pass filter to get
voltage.
(2) To ensure less than 1/2 LSB output ripple, the time Astable multivibrators are free-running oscillators that
constant (RC) must be long enough or the output to oscillates between two states continuously producing
two square wave output waveforms. These both states
settle i.e
are not stable as it changes from one state to the other
T ≥ 0.69 ( n + 1) To all the time.

9. In a series regulated power supply circuit the Ans. (c) : Current following through a capacitor in an
voltage gain AV of the "pass", transistor AC circuit is displacement current because of change in
satisfies the condition electric field between plates with time.
(a) Av → ∞ (b) 1 << Av << ∞ Q Maxwell equation
(c) Av ≈ 1 (d) Av << 1 ∇ × H = jc + jD
GATE-1998
Where jC = conduction current density
Ans. (c) : VZ = VBE +V0
VBE = VZ –V0 jD = displacement current density
Since VZ is constant. jC = σE, and
∂D
jD =
∂t
∂V
Then IC = C. in capacitor.
dt
12. The approximate O/P Frequency of 555
V0 ↑→ VBE ↓→ IL ↓ I L R Z ↓→ V0 ↓ Oscillator for R A = R B = 2.2 kΩ and C=2000
and V0 ↓→ VBE ↑→ IL ↑→ I L R Z ↑→ V0 ↑ pF-
(a) 110 kHz (b) 109.3 kHz
So, V0 will be regulated
(c) 120.5 kHz (d) 108.9 kHz
for Q , Load in connected at VZ is connected at base.
V0 ≈ VZ Ans.(b)
So,
Emitter follower base. It is a common collector.
Voltage gain A V ≈ 1
So, In a series regulated power supply circuit, the
voltage AV, In a series regulated power supply circuit,
the voltage gain Av of the 'Pass' transistor satisfies the
condition.
10. In a feedback series regulator circuit, the
output voltage is regulated by controlling the
(a) Magnitude of the I/P voltage IC 555 timer acts as oscillator in astable mode,
(b) Gain of the feedback transistor Given,
(c) Voltage drop across the series pass transistor RA=RB=2.2kΩ
(d) Reference voltage Let RA = R1
ISRO Scientist Engg.-2012 RB =R2
IES-1999 C = 2000pF
Ans. (d) : Feedback series regulator- 1 2
Q During charging of capacitor from VCC to VCC ,
3 3
Then n output is high and times duration is
Thigh = 0.69 ( R 1 + R 2 ) C
And during discharging of capacitor from
2 1
VCC to VCC , the output is low and time duration is,
3 3
TLow = 0.69R 2 C
Maintains the DC output voltage of a power supply Time period (T) = TH+TL
constant respect in AC supply and variations in T = 0.69(R 1 + 2R 2 )C
load current. So, frequency of oscillator
Output does not change due to change in the load 1 1
(f) = =
voltage. (or Reference voltage) T 0.69 ( R A + 2R B ) C
11. The current flowing through a capacitor in an
AC circuit is : 100
f=
(a) Non-existent 69 × ( 2.2 + 2 × 2.2 ) ×103 × 2000 × 10 −12
(b) Conduction current
108
(c) Displacement current = Hz
(d) None of the above 13.2 × 69
ISRO Scientist Engg.-2013 = 109.79 109.8kHz

13. The approximate frequency of oscillation of the 16. A Schmitt trigger circuit achieves hysteresis by
circuit shown below is utilizing
(a) The magnetic properties of transformer core
(b) Avalanche multiplication in a Zener diode
(c) The Barkhausen principle
(d) Regenerative positive feedback
Ans. (d) :
(a) 8.3 kHz (b) 16.6 kHz

(c) 7.2 kHz (d) 3.6 kHz
Vout = V+ if Vin < VL
Ans. (c) : The given circuit is an astable multi-vibrator.
V– if Vin > VH
So the frequency.
Schmitt trigger is a Comparator Circuit with hysteresis
1
f= implemented by applying positive feedback to the non
1.38RC inverting input of a Comparator amplifier.
Given, R = 10kΩ, C =0.01pF It achieves hysteresis by utilizing Regenerative
1 positive feedback.
f=
1.38 × 10 ×103 × 0.01× 10−6 17. An astable multivibrator is also called
f = 7.246 kHz (a) Free running multivibrator
(b) Edge triggered multivibrator
14. A bistable multivibrator has………… (c) Emitter coupled multivibrator
(a) Two stable states (b) One stable state (d) Collector coupled multivibrator
(c) No stable state (d) None of the above Mizoram PSC IOLM -2018, Paper II
Nagaland PSC (CTSE) Diploma-2017, Paper II Ans. (a) : In electronic circuit, astable multivibrators
Nagaland PSC (CTSE) Diploma-2018, Paper I are also known as free running multivibrators as they do
Ans. (a) : not require any additional input.
18. In which circuit duty cycle of any pulse wave is
50%
(a) Astable Multivibrator
(b) Mono-stable Multivibrator
(c) Bistable Multivibrator
(d) Schmitt trigger
UPPCL AE-16.11.2013
A type of multivibrator whose output consists of 2
Ans. (a) : Astable multivibrators generally have an even
stable states is known as Bistable multivibrator. The
50% duty cycle, that is the 60% of the cycle time the
circuit switches from one stable state to the other when
output is high and remaining 50% of the cycle time of
an appropriate trigger pulse is applied.
output is off. In other words, the duty cycle of an
15. ……………multivibrator is a square wave astable timing pulse is 1 : 1.
oscillator
19. The duration of the ON time of any pulse of
(a) Monostable (b) Astable
mono-stable multivibrator depends on
(c) Bistable (d) None of the above
(a) External R connected to the circuit only
Nagaland PSC (CTSE) Diploma-2017, Paper II (b) R and C both
Ans. (b) : An astable multivibrator is a square wave (c) External C connected to the circuit only
oscillator because it produces a continuous square wave (d) External R but not external C
from its output which can be used to flash lights or UPPCL AE-16.11.2013
produce a sound in a loudspeaker. It is a free running Ans. (b) : In monostable multivibrator, there is only one
and frequency of square wave generator independent of stable state. The duration of the output pulse is
output voltage. determined by the RC network connected externally to
the 555 timer. The stable state output is approximately 23. The output frequency of an astable
zero at logic low level. multivibrator using NE555 timer is given by,
1.44 1
(a) (b)
(R a + 2R b )C (R a + 2R b )C
1 1.44
(c) (d)
1.44(R a + 2R b )C (R a + R b )C
TNPSC AE-2013
Ans. (a) : The frequency of oscillation being the
reciprocal of over all time period.
T = 0.693 (Ra+2Rb) C sec.
1.44
F= Hz
20. A bleeder resistor is used in a D.C power (R a + 2R b )C
supply because it 24. What will be the period and frequency of
(a) Keeps the supply OFF oscillation for an astable multivibrator, given
(b) Keeps the supply ON the following specifications?
(c) Improves filtering action R1 = 1kΩ R2 = 5.6 kΩ C1 = 0.01 µF C2 = 0.03 µF
(d) Improves voltage regulation (a) 12.5 ms, 80 Hz (b) 1.25 µs, 800 kHz
KVS TGT (WE)- 2016 (c) 1.25 ms, 800 Hz (d) 0.125 ms, 8 kHz
Ans. (d) : Bleeder resistor is used in a DC power supply 1
because- Ans. (d) : f =
0.69(R 1C1 + R 2 C 2 )
• It improves voltage regulation of the supply.
• It provides safety to the technician handling the 1
f=
equipment. 0.693 (1 × 103 × 0.01× 10−6 + 5.6 × 103 × 0.03 × 10−6 )
• By maintaining a minimum current through the
1000
choke, it improves its filtering action. f= = 8196 Hz
0.69(.01 + 5.6 × 0.03)
f 8kHz
1 1
and, T = = × 10−3
F 8
= T = 0.125ms
25. Important applications of Schmitt trigger
circuit are as below :
21. A monostable multivibrator has R = 10 kΩ and (a) As an amplitude comparator
C = 1pF? What is the width of the pulse? (b) As a squaring circuit
(a) 6.3 ps (b) 6.3 ns (c) As a Flip Flop circuit
(c) 6.3 µs (d) 6.3 ms (d) All the above
Ans. (b) : Phase width of the pulse of monostable Ans. (d) : A Schmitt trigger circuit produce square
multivibrator, wave for sine wave input and it also used as an
T = 0.69 RC amplitude comparator and flip-flop also.
= 0.69 × 10 × 103 × 1 × 10–12 = 6.9 ns 26. What is the maximum load current that one
≅ 6.3 ns can draw from a 15 volt 3-pin regulator of the
22. Which of the following is also called as Eccles type 781.15?
Jordan Circuit? (a) 1 A (b) 0.5 A
(a) Astable Multivibrator (c) 100 mA (d) 3 A
(b) Monostable Multivibrator TNPSC AE-2013
(c) Bistable Multivibrator Ans. (c) : For 3 pin regulator the maximum current that
(d) Schmitt Trigger can flow through it is 80 mA to 100 mA - for 15 V
TNPSC AE-2014 rating.
Ans. (c) : Bistable Multivibrator– 27. What is a Schmitt trigger?
It has two absolutely stable states. It can stay in one of (a) A trigger circuit
its two states indefinitely changing to the other state (b) A comparator with Hysteresis
only when it receives as trigger pulse from outside. (c) A comparator without Hysteresis
Bistable multivibrator is also called as Eccles Jordan (d) Amplifier
circuit. RPSC LECTURER-10.01.2016
Ans. (b) : A Schmitt trigger is a comparator circuit with Ans. (c) : Frequency of oscillation
hysteresis implemented by applying positive feedback 1
to the non-inverting input of a comparator or differential f=
amplifiers. T
1.44
f=
( A + 2R B ) C
R
1.44
=
(10 + 2 × 10 ) × 0.1× 103 × 10−6
1.44
It is an active circuit which converts an analog input =
30 × 0.1× 10−3
signal to a digital output signal.
f = 480Hz
28. In a digital frequency meter, the Schmitt
trigger is used for f 476 Hz
(a) Converting sinusoidal waveforms into t
rectangular pulses. Duty cycle D = c × 100
T
(b) Scaling of the sinusoidal waveforms 0.693(R A + R B )C
(c) Providing time base = × 100
(d) Triggering a start pulse 0.693(R A + 2R B )C
=
( R A + R B ) × 100
Ans. (a) ( R + 2R ) A B
20
= × 100
30
D = 66.66%
30. The basic important blocks of IC 555 timer
(a) Voltage source (b) Flip-flop
(c) Resistors (d) Switch
RPCS Lect.-2011
Ans. (b) : The important blocks of IC 555 timer has two
comparators, which are basically 2 operational
• A digital frequency meter is an electronic instrument amplifiers an R-S flip flop, two transistors and a
that can measure even the smaller value of frequency resistive network.
up to 3 decimals of a sinusoidal wave and displays it 31. A d.c. voltage supply provides 60 V when the
on the counter display. output is unloaded. When connected to a load,
• The main purpose of the Schmitt trigger is to convert the output drops to 56 V. the value of the
the sinusoidal wave signal into a square wave or voltage regulation is
rectangular pulse train.
(a) 3.7% (b) 5.7%
• Digital frequency meter has High sensitivity and
good frequency response. (c) 7.1% (d) 9.1%
• It does not measure the exact value. IES-2019
29. In astable multivibrator as shown in figure, if Ans. (c) : Given, No Load Voltage, VNL = 60 V
RA = RB = 10 kΩ and C = 0.1 µF, then duty Full Load Voltage, VFL = 56 V
cycle and frequency of oscillation is (select V – VFL
nearest values) : Voltage Regulation = NL × 100%
VFL
60 – 56
= ×100%
56
4
= × 100%
56
= 7.14%
32. For 555 astable multivibrator, if C = 0.01 µF,
RA=10kΩ, RB = 50kΩ, the frequency and the
(a) (50% and 300 Hz) respectively duty cycle will be nearly.
(b) (66.66% and 350 Hz) respectively (a) 1.6 kHz and 54.5% (b) 1.3 kHz and 54.5%
(c) (66.66% and 476 Hz) respectively (c) 1.6 kHz and 46.5% (d) 1.3 kHz and 46.5%
(d) (40% and 200 Hz) respectively IES-2019
MPSC HOD Govt. Poly. -2013 TNTRB AE– 2017

Ans. (b) : Given, RA = 10 kΩ, RB = 50 kΩ, C = 0.01 µF Ans. (b) : Voltage Regulator :-
• Voltage Regulator has a Zener Diode connected in
parallel with filter output.
• The Zener Diode is biased with reverse connection
for voltage regulation.
• Voltage Regulator is a circuit that creates and
maintains a fixed output voltage.
35. A 1 µs pulse can be converted into a 1 ms pulse
by using
(a) A monostable multivibrator
(b) An astable multivibrator
(c) A bistable multivibrator
(d) A J-K flip-flop
APGENCO AE-23.04.2017
IES-2014, 2007, 2000,1999, 1995
Frequency of A stable multivibrator Ans. (a) : Monostable multivibrator-
1.44 • It has only one stable state.
f= • It is also known as single shot or one shot
( R A + 2R B ) C multivibrator.
1.44 • It is used as delay and timing circuits.
=
(10 + 2 × 50 ) ×103 × 0.01×10 –6 • It converts 1 µs pulse into a 1 ms pulse so it is called
f = 1.3 kHz a pulse stretcher circuit.
Duty cycle of A stable multivibrator • It is also used for temporary memories.
RA + RB 36. A monostable multivibrator is frequently used :
D= × 100% (a) In memory and timing circuit
R A + 2R B
(b) For regeneration of distorted waves
10 + 50 (c) In counting circuits
= ×100%
10 + 2 × 50 (d)For producing triangular waves
60 KVS TGT (WE)- 2016, IES-2013
= × 100% Ans. (b) : Used of monostable multivibrator :-
110
D = 54.54%. • Monostable multivibrator is used in analog systems
to control an output signal frequency.
linear power supply : • It can consider as triggered pulse generators.
1. It requires low frequency transformer. • It used for the generation of clock pulse and the
regeneration of distorted waves.
2. It requires high frequency transformer.
• It is called a pulse stretcher circuit because it
3. The transistor works in active region.
increases the width of a pulse.
Which of the above statements is/are
correct? 37. The frequency of oscillation of astable
multivibrator with component values R1 = 2kΩ,
(a) 1 only (b) 2 and 3 only
R2 = 20kΩ, C1 = 0.01 µF and C2 = 0.05 µF is:
(c) 1 and 3 only (d) 3 only (a) 1428.5 Hz (b) 142.85 Hz
IES-2016 (c) 14.285 Hz (d) 1.4285 Hz
Ans. (c) : Features of Linear Power Supply :- IES-2013
• Required a step-down low-frequency transformer and Ans. (a) : Given, R1 = 2 kΩ, C1 = 0.01 µF, C2 = 0.05 µF
high the input voltage and frequency both. Frequency of oscillation of a stable multivibrator
• Required the voltage across the load does not vary. 1
• Transistor should operate in the active region so that f=
0.69 ( R 1C1 + R 2 C 2 )
the desired amplification is achieved.
34. In a voltage regulator, zener diode is 1
=
1. Connected in series with filter output (
0.69 2 × 10 × 0.01 × 10 + 20 × 103 × 0.05 ×10 –6
3 –6
)
2. Forward biased 1
=
3. Connected in parallel with filter output
4. Reverse biased
(
0.69 20 × 10 –6 + 1000 × 10 –6 )
Which of the above are correct? 106
=
(a) 1 and 2 (b) 3 and 4 703.8
(c) 1 and 4 (d) 2 and 3 f = 1420.85 Hz
IES-2015 f 1428.5Hz

38. In order to obtain repetitive pulses of unequal Ans. (b) : The circuit shown above is a mono-stable
mark space one can use : multivibrator.
1. A voltage comparator fed with a triangular • IC 555 mono-stable multivibrator works as a
wave signal and DC-voltage. frequency divider circuit.
2. An astable Multivibrator • Monostable multivibrator used in pulse width
3. A mono-astable Multivibrator fed with square modulation.
wave input. • It acts as a Linear Ramp Generator.
Which of these statements are correct? • It can be used to drive a relay.
(a) 1 and 3 only (b) 1 and 2 only 41. Consider the following statements about a good
(c) 2 and 3 only (d) 1, 2 and 3 power supply :
IES-2011 1. The a.c. ripple should be high.
Ans. (d) : To obtain repetitive pulses of unequal mark 2. SV' (Voltage stability factor) should be low.
space, we can use – 3. ST' (Temperature stability factor) should be
• An astable multivibrator without any trigger input. low
• A monostable multivibrator fed with a square wave Which of the above statements are correct?
input. It can produce one stable output by triggered (a) 1, 2 and 3 (b) 2 only
input. (c) 3 only (d) 2 and 3 only
• Voltage comparator having triangular wave signal IES-2009
and DC voltage. Ans. (d) : Specifications of a good power supply-
39. Consider the following statements : • In a good power supply AC ripple should be low.
1. A Schmitt trigger circuit can be emitter • Voltage stability factor (SV) and Temperature
coupled bistable circuit. stability factor (ST) both should be low in a good
2. Schmitt trigger circuit exhibits hysteresis power supply.
phenomenon. • The power supply must always be voltage regulated
3. The output of Schmitt trigger will be and be able to hold a fixed voltage output over a
triangular if the input is square wave. range of loads.
Which of these statements are correct? 42. Which one of the following is a regulated power
(a) 1, 2 and 3 (b) 1 and 2 only supply?
(c) 2 and 3 only (d) 1 and 3 only (a) IC 555 (b) IC 844
IES-2011 (c) IC 3080 (d) IC 723
IES-2009
Ans. (b) : Schmitt Trigger :-
Ans. (d) :
• Schmitt trigger is a comparator circuit with
hysteresis implemented by positive feedback which
gives a Bi-stable output.
• Schmitt trigger shows different characteristics for
increasing and decreasing value of the input. This
property is known as the hysteresis phenomenon.
• The output of Schmitt trigger will be a square wave
for any input.
• From the emitter-coupled Bi-stable circuit. We can
get the property of a Schmitt trigger circuit.
40. The circuit shown above is :
IC 723 :-
• IC 723 voltage regulator is used for series voltage
regulator applications.
• It can be used as both positive and negative voltage
regulator.
• IC 723 can also be used as a temperature controller,
current regulator or shunt regulator.
• It is available in both Dual – In – Line and metal
cane packages.
43. Narrow pulses with adjustable mark to space
(a) Bi-stable multi-vibrator ratio can be obtained from square wave input
(b) Mono-stable multi-vibrator signal by using which of the following?
(c) Free running multi-vibrator 1. Schmitt trigger.
(d) Ramp generator 2. Monostable multivibrator
IES-2010 3. Clippers
Select the correct answer using the code Ans. (d) : Series Transistor Feedback Voltage
given below : Regulator :-
(a) only 1 (b) only 2 • It is also called the series pass regulator and used in
(c) 1 and 2 (d) 2 and 3 linear regulated power supply.
IES-2006 • In this type of Regulator, the regulation factor can be
Ans. (b) : Monostable multivibrator is a circuit used as improved by increasing the low of the shunt transistor
pulse Generator. It is able to changes pulse width of and by increasing the resistance between the collector
signals. of the shunt transistor and the collector of the series
So, Narrow pulses with adjustable mark to space ratio transistor.
can be obtained from square wave input signal by using
monostable multivibrator.
44. Match List-I (Application of the circuit) with
List-II (Circuit Name) and select the correct
answer using the code given below the lists :
List-I List-II
A. Divider 1. Astable
multivibrator
B. Clips input voltage at 2. Schmitt trigger
two predetermined
Levels
C. Square wave generator 3. Bistable • Transistor, In transistor series voltage regulator
multivibrator behaves like a variable resistor.
D. Narrow current 4. Blocking • The output resistance can be reduced by using a
pulse generator oscillator Darlington pair in place of the series transistor.
A B C D • Output resistance cannot be reduced by reducing the
(a) 4 2 1 3 hfe of the shunt transistor.
(b) 3 2 1 4 46. Consider the following circuit :
(c) 4 1 2 3
(d) 3 1 2 4
IES-2009, 2004
Ans. (d) : Astable multivibrator :- It is an electronic
circuit that has not stable states. It clips input voltage of
two predetermined levels.
Schmitt Trigger :- It is regenerative comparator that Which one of the following expressions for V0 is
employs positive feedback and converts sinusoidal input correct?
into a square wave output.  R1 + R 2 
Bistable multivibrator :- It is also known as Flip-Flop (a) V0 = Vz  
multivibrator. It is widely used in latches and counters.  R + R1 + R 2 
It is also used in frequency divider circuits and in (b) V0 = AVz
storage devices.
 R 
Blocking Oscillator :- It is a waveform generator that (c) V0 = AVz  1 + 1 
is used to produce narrow current pulses or trigger  R2 
pulses. It blocks the feedback, after a cycle, for certain
predetermined time while it having the feedback from  R1 + R 2 
(d) V0 = AVz  
the output signal.  R + R1 + R 2 
45. Which one of the following statements is not IES-2003
correct in respect of a series transistor Ans. (c) :
feedback voltage regulator?
(a) The regulation factor can be improved by
increasing the hfe of the shunt transistor
(b) The regulation factor can be improved by
increasing the resistance between the
collector of the shunt transistor and the
collector of the series transistor. Apply voltage divider rule,
(c) Output resistance can be reduced by using a
Darlington pair in place of the series  R2 
AVz = V0  
transistor.  R1 + R 2 
(d) Output resistance can be reduced by reducing
 R 
the hfe of the shunt transistor. V0 = AVz  1 + 1 
IES-2004  R 2 

47. Match List-I (Circuit Name) with List-II Ans. (c) T = RC ln(3)
(Characteristics) and select the correct answer T = 1.1 RC
using the code given below the lists :
List-I List-II
A. Schmitt trigger 1. It need a pulse
transformer
B. Monostable 2. It is used to
Multivibrator generate gating
pulse whose
width can be
controlled
C. Astable 3. It is a bistable
multivibrator circuit 50. Which one of the following sets of circuits can
D. Blocking oscillator 4. It has no stable be obtained by using a 555 timer ?
state (a) Pulse modulator and amplitude demodulator
Codes : (b) Pulse modulator and astable multivibrator
A B C D (c) Amplitude demodulator and AC to DC
(a) 3 2 4 1 converter
(b) 2 3 1 4 (d) AC to DC converter and astable multivibrator
(c) 3 2 1 4
IES-2000
(d) 2 3 4 1
Ans. (b) : Pulse Width Modulator (PWM) using 555
IES-2003
Timer :-
Ans. (a) :
• Schmitt Trigger behaves as a Bi-stable circuit.
• Monostable multivibrator is a pulse generator circuit.
• A stable multivibrator has no stable states. It has two
quasi-stable states.
• A blocking oscillator is a wave-form generator that is
used to produce narrow pulses. It needs a pulse
transformer.
48. The function of the diode D in the timer circuit
shown below is to
Astable multivibrator using 555 Timer :-
(a) Increase the charging time of C.

(b) Decrease the charging time of C.
(c) Increase the discharging time of C.
(d) Decrease the discharging time of C.
IES-2003
Ans. (d) : In the above given timer circuit, Diode ‘D’ is
connected in forward bias. The capacitor ‘C’ will
charge through the resistance (RA+RB). Due to forward
biasing of Diode ‘D’, the capacitor will discharge by
diode ‘D’ instead of resistance RB and discharging time Hence, pulse modulator and Astable multivibrator
of capacitor ‘C’ will decrease. circuit can be obtained by using a 555 timer.
49. What is the time period of a monostable 555 51. For the high-pass circuit to act as a
multivibrator? differentiator, the time constant must be
(a) T = 3RC (b) T = RC (a) Small
(c) T = 1.1RC (d) T = 0.33RC (b) Very small in comparison to the time period
RRB JE- 31.08.2019, 10 AM-12 PM of the input signal

(c) Very high in comparison to the time period of Ans. (c) : Use of commutating capacitors in a bi-
the input signal (that is low pass circuit) stable multivibrator –
(d) Moderate value
TNPSC AE-2013
IES-1999
Ans. (b) : High-Pass Filter Circuit as Differentiator–
The output of a HPF circuit at low frequency will be

zero but at high frequency the value of output will be
infinite. This property is same as a differentiator circuit.
(τ = RC)
When the time constant of the HPF is smaller than the
Bi-stable multivibrator has two stable states. It is known
time period of the input signal then the circuit acts as a
as flip-flop. R1 and R2 are feedback resistors and are
differentiator. RC << T connected in parallel with C1 and C2 respectively.
A differentiator circuit produces a constant output Capacitor C1 and C2 are commutating capacitors. These
voltage when the input applied tends to change steadily. are also known as speed-up commutating capacitors.
52. A second-order band-pass active filter can be They reduce the transition time (time taken for the
obtained by cascading a low-pass second-order transfer).
section having cut-off frequency fOH with a Hence, commutating capacitors (C1 & C2) are used in a
high-pass second-order section having cut-off Bi-stable multivibrator to increase the speed of
frequency fOL, provided response.
(a) fOH > fOL (b) fOH < fOL 54. Higher order active filters are use for variable
(a) Bandwidth
(c) fOH = fOL (d) f OH ≤ 1 f OL (b) Gain in the pass-band
2
IES-1999 (c) Impedance
(d) Roll-off rate
Ans. (a) : Band-Pass Active Filter – A second order
band-pass active filter allows frequencies within a IES-1998
specific frequency range and attenuates the other Ans. (d) : Higher Order Active Filters : Higher order
frequencies. active filters can be obtain by cascading a proper
Low –pass filter isolates the frequencies higher than the number of first and second order filters. Higher order
cut-off frequency but High-pass filter isolates the active filters are used for variable Roll-Off rate.
frequencies lower than the cut-off frequency. The rate at which gain changes is called roll-off rate. It
By cascading a High pass second-order filter and Low- is expressed in dB/octave or dB/decade.
Pass second-order filter, we can make a second order 55. Consider the following statements :
band-pass active filter. The 555 timer can be employed in
The condition for getting a Band-Pass the cut-off 1. A monostable multivibrator
frequency (fOH) of low-pass second-order filter must be 2. A bistable multivibrator
greater than the cut-off frequency (fOL) of High-pass 3. An astable multivibrator
second-order filter. Of these statements
fOH > fOL (a) 1 and 2 are correct
53. In a bistable multivibrator, commutating (b) 1 and 3 are correct
capacitors are used to (c) 2 and 3 are correct
(a) Increase the base storage charge (d) 1, 2 and 3 are correct
(b) Provide a.c. coupling IES-1996
(c) Increase the speed of response Ans. (d) : The 555 timer can be employed An astable
(d) Alter the frequency of the output multivibrator monostable multivibrator and bi-stable
IES-1998 multivibrator –

Astable multivibrator – • Monolithic regulator allows to create a stabilized
power supply.
• 78XX series of monolithic linear regulators (for
positive voltage) and 79XX (for negative voltage).
• It is used to introduce flexibility in setting output
voltage level.
• To maintain a constant output voltage. It can adjust
the device resistance.
In a series transistor regulator, the regulation
factor and output resistance can be improved
by
1. Increasing hfe of the series transistor
2. Increasing hfe of the shunt transistor
Monostable multivibrator :- 3. Increasing the external resistance R connected
between the collector and base of the series
transistor.
Of these statements
(a) 1 and 2 are correct
(b) 2 and 3 are correct
(d) 1, 2 and 3 are correct
IES-1996
Ans. (a) : Series transistor regulator :-
Bi-Stable Multivibrator :-
• In this regulator transistor acts as control element

and it is connected in series with the load (RL).
Therefore it is called series voltage regulator.
• The regulation factor and output resistance can be
improved by increasing hfe of the series transistor
and hfe of the shunt transistor respectively.
Limitation :-
• Output voltage can not maintain absolutely because
VBE and VZ decrease with increase room
temperature.
• Output voltage cannot be changed as there is no
provisional it in the circuit.
Monolithic regulators can be used to • It can not provide good regulation at high current.
1. Realize a constant voltage regulator • It has poor ripple factor with respect to input
2. Realize a constant current regulator. variation.
3. Introduce flexibility in setting output voltage 58. The given figure shows the application of 555
level. timer circuit as an astable multivibrator. The
charging and discharging, time constants are
Of these statements
respectively
(b) 1 and 3 are correct
(d) 1, 2 and 3 are correct
IES-1996
Ans. (b) : Monolithic Regulator :-
• Monolithic Regulator is also known as integrated
Regulator. It is a linear voltage regulator.

(a) R1 C and R2 C
(b) R1 C and (R1 + R2) C
(c) (R1 + R2) C and R1 C
(d) R2 C and R1 C
IES-1995
Ans. (c) : Of these statements :
(a) 1, 2 and 3 are correct (b) 1 and 2 are correct
IES-1994
Ans. (b) : The given circuit is a High-Pass filter.
Time constant of High-Pass RC filter τ = RC
• When the time constant of a high-pass RC circuit is
very small as compare to the time period, the circuit
will act as a differential circuit. RC << T
At this condition the output V0 will consist of a positive
and negative spike.
From the given 555 time circuit diagram. The
Resistance (R1+R2) will charge the capacitor (C). The • When the time constant is very large as compare to
capacitor (C) will discharge through resistance R1. So, the time period, the impedance (XC) of the circuit
will be very small. RC >> T
the charging time of the capacitor (C)
At this condition the output V0 will equal to the input Vi
Tc = ( R 1 + R 2 ) C , (V0 = Vi).
and the discharging time, 61. Match List-I with List-II and select the correct
Td = R 1C answer using the code given below the lists :
List-I List-II
59. The circuit shown in the given figure is : (Type of filter) (Property
associated with
it)
A. Low pass filter 1. Tuned circuit
B. High pass filter 2. Compensated
attenuator
C. Band pass filter 3. Differentiator
D. RLC – Circuit 4. Ringing
(a) Pulse amplifier A B C D
(b) Monostable multivibrator (a) 3 2 4 1
(c) Astable multivibrator (b) 2 3 1 4
(d) Bistable multivibrator (c) 2 3 4 1
(d) 2 1 3 4
IES-1995
IES-1994
Ans. (b) : The circuit shown in the given figure is a
monostable multivibrator. Ans. (b) : Low-Pass Filter :- It passes signals with a
frequency lower than a selected cut-off frequency and
Monostable multivibrator has one stable state and one
attenuates signals with frequencies higher than the cut-
quasi stable state. When we applied an external trigger
off frequency.
pulse to the circuit, the multivibrator will jump to quasi
High-Pass Filter :- It acts as a differentiator circuit
stable from stable state. After the few time period it will when time constant is very small as compare to the time
automatically set back to the stable without any external period.
trigger. It is mainly used as timer. RC << T
60. For the circuit given in the figure, consider the Band Pass Filter :- It acts like a tuned circuit that
following statements : passes all frequencies between lower and Higher
frequency Range. It passes all frequencies above its cut-
1. The output VO will consist of a positive and off frequencies.
a negative spike if RC << T. RLC Circuit:- A Circuit with a value of resistor that
2. The output VO will be similar to Vi if RC >> causes it to be just on the edge triggering is called
T critically damped.
3. The output will have a higher rise time if RC Under damped-ringing happens
is made progressively smaller than T. Over damped-ringing is suppressed

62. Which of the following pairs is/are correctly Ans. (c) : Astable multivibrators are self triggered.
matched?
Waveform
1. Triangular wave
2. Impulse wave
3. Saw-tooth wave
Circuitry and input signal
1. Integrating circuit and square wave
2. Differentiating circuit and Step signal
3. Differentiating circuit and triangular wave
Select the correct answer using the codes
given below :
(a) 2 and 3 (b) 1 and 2 Advantage of Astable Multivibrator:-
(c) 1 alone (d) 1 and 3 • They are very simple in design
IES-1993 • They are very reliable.
Ans. (b) : • They are very easy to construct with a very nominal
cost
• They do not need any external triggering or input
clock pulse.
• They can run continuously for a very large amount of
time without any problem.
65. Consider the following two statements:
Statement 1: Astable multivibrator can be used
for generating square wave.
Statement 2: Bistable multivibrator can be used
for storing binary information.
63. An astable multivibrator can be used as
(a) Only statement 1 is correct
(a) Squaring circuit
(b) Only statement 2 is correct
(b) Comparator
(c) Both the statements 1 and 2 are correct
(c) Frequency to voltage converter (d) Both the statements 1 and 2 are incorrect
(d) Voltage to frequency converter GPSC Asstt. Prof. 11.04.2017
Nagaland PSC CTSE (Diploma) 2018, Paper-I GATE-2001
Nagaland PSC CTSE (Degree) 2018, Paper-II
Ans. (c) : Astable multivibrator :- It has two unstable
Nagaland PSC CTSE (Degree) 2017, Paper-II states.
Ans. (d) : Voltage to frequency converter:- • It can be used for generating square wave.
• Astable multivibrator are used in the application • It is also called a free running multivibrator.
like pulse position modulation, frequency Bistable Multivibrator:-
modulation.
• It can be switched over from one stable state to the
• Astable multivibrator circuit mainly used as a other by the external trigger pulse.
continuous wave generation circuit. • It is also known as latches and Flip-Flops for use in
• It is used in voltage to frequency converter circuits. sequential type circuits.
• Astable multivibrator circuit can generate also • It can be used for storing binary information.
square wave for this reason, they are used in digital 66. An ideal sawtooth voltage waveform of
transmission, receiver, television broadcast etc. frequency 500Hz and amplitude 3V is
64. Which one of the following multivibrators does generated by charging a capacitor of 2 µF in
not required input clock pulse or trigger? every cycle. The charging requires
(a) Monostable (a) Constant voltage source of 3V for 1 ms
(b) Bistable (b) Constant voltage source of 3V for 2 ms
(c) Astable (c) Constant current source of 3 mA for 1 ms
(d) Schmitt trigger circuit (d) Constant current source of 3 mA for 2 ms
Nagaland PSC (Degree) 2018, Paper-II GATE-2003
1 1 1
Ans. (d) : Given, f = 500 Hz, T = = 2 ms V C, VCC = × 9 = 3V
f 3 3
2 2
VCC = × 9 = 6 V
3 3
VC = 3 V to 6 V
68. In the following astable multivibrator circuit,
which properties of V0 (t) depend on R2?
1 t
C ∫0
Vc(t) = i C .dt
I
Vc(t) = × t = slope × f
C
Vc(t) = 3V at t = 2 ms
−3
I 2 ×10
2 ×10 –6 ∫0
3= 1dt
(a) Only the frequency
I ( 2 ×10−3 − 0 ) = 6 × 10−6 (b) Only the amplitude
I = 3 mA (c) Both the amplitude and the frequency
(d) Neither the amplitude nor the frequency
t = 2 ms
GATE-2009
67. An astable multi-vibrator circuit using IC 555
Ans. (a) :
timer is shown below. Assume that the circuit is
oscillating steadily.
The voltage VC across the capacitor varies

between
(a) 3 V to 5 V (b) 3 V to 6 V If V+ > V– then, V0 = + Vsat
(c) 3.6 V to 6 V (d) 3.6 V to 5 V V+ > V– then, V0 = + Vsat
GATE-2008 Hence, amplitude of astable multivibrator does’nt
depend on R2.
Ans. (b) : Given VCC = 9V For charging and discharging of capacitor ‘C’ time
period.
T = (R1 + R2)C
TON = TOFF = 0.69 (R1 + R2)C
So, T = TON + TOFF = 1.38 (R1 + R2)C
1 1
frequency f = =
T 1.38 ( R1 + R 2 ) C
Hence, In astable multivibrator circuit, only the
frequency depends on R2.
69. If a pulse train with a frequency of 10 kHz is
applied to the trigger input of a bistable
In given astable multivibrator circuit, the capacitor
multivibrator, the frequency of the output
1 2 pulse train would be
voltage VC, varies between VCC and VCC
3 3 (a) 5 kHz (b) 20 kHz
Given that the VCC = 9 Volt (c) 10 kHz (d) None of these
Hence the variation Range of capacitor voltage. Kerala PSC Lecturer (NCA) 04.07.2017

Ans. (a) : For Bi-stable multivibrator– 20 − 5 15
F R L(min) = =
Fout = in 15 15
2 RL(min) = 1kΩ.
10 kHz 74. Which component's size is affected by the
Fout =
2 frequency of operation of a switched mode
Fout = 5 kHz power supply?
70. Asymmetrical astable multivibrator has R = (a) Transformer
100Ω and C = 0.1 mF. The periodic time T is (b) Transistor and Transformer
equal to (c) Transformer and Capacitor
(a) 138 mS (b) 69 mS (d) Capacitor
(c) 6.9 mS (d) 13.8 mS
Kerala PSC Lecturer (NCA) 04.07.2017 Nagaland PSC- 2018, Diploma Paper-II
Ans. (d) : For astable multivibrator– Ans. (c) : A switch mode power supply (SMPS) is a
Time period T = 1.38 RC modern power supply converter that works on switching
T = 1.38 × 100 × 0.1 mF technique. In SMPS regulation a large component such
T = 138 × 0.1 msec as transformer, capacitor and inductor are affected by
T = 13.8 ms the frequency of operation.
71. In transistor series voltage regulator the 75. DC output drops from 50 V with no load to 48
transistor behaves like a variable V with full load. Load regulation is
(a) resistor (b) capacitor (a) 2% (b) 4%
(c) inductor (d) resistor and capacitor (c) 1% (d) 8%
Ans. (a) : Transistor series voltage regulator has a
transistor in series to the zener regulator and both in Ans. (b) : VNL = 50 V VFL = 48 V
parallel to load. The transistor works as a variable VNL − VFL
resistor regulating its collector emitter voltage in order %VR = ×100
VNL
to maintain the output voltage constant.
72. In a typical 555 astable multivibrator circuit, if 50 − 48
= ×100
RA = RB = 2.2kΩ and C = 0.1µF then the free- 50
running frequency is : %VR = 4%
(a) 3.123 kHz (b) 2.186 kHz
(c) 4.128 kHz (d) 6.226 kHz 76. By the use of which of the following the PPM
APPSC POLY. LECT. 14.03.2020 can be converted to PWM?
Ans. (b) : RA = RB = 2.2 kΩ (a) Astable multivibrator
C = 0.1 µF (b) Integrator
(c) Monostable multivibrator
1
f= (d) Bistable multivibrator
0.693 ( R A + 2R B ) × C
1
f= Ans. (d) : With the help of bistable multivibrator pulse
0.693 ( 2.2 × 10 + 2 × 2.2 × 103 ) × 0.1× 10−6
3
position modulation can be converted into pulse width
modulation.
1000
f= 77. In a free running multivibrator, each stage is
0.693 × 0.66
cut off for 1µs. What is the oscillation
f = 2.186 kHz frequency
73. A zener regulator has an input voltage from 20 (a) 10 MHz (b) 5 MHz
V to 30 V. The load current varies from 10 mA (c) 1 MHz (d) 0.5 MHz
to 15 mA. If the Zener voltage is 5 V, the value Nagaland PSC (Degree) 2018, Paper-II
of series resistor will be Nagaland PSC CTSE- 2015, Paper-II
(a) 1 kΩ (b) 1.5 kΩ Ans. (c) : In electronic circuits, astable multivibrators
(c) 1.66 kΩ (d) 2.5 kΩ are also known as free–running multivibrator as they
Mizoram PSC IOLM -2018, Paper I do not require any additional inputs or external
Ans. (a) : Given , V = 20 volt, Vz = 5 V , assistances to oscillation.
IL(max) = 15 mA 1 1
f= = = 1× 106 Hz
VL V − Vz T 1× µs
I L(max) = =
R L(min) R L(min) = 1 MHz

78. (c) A bistable multivibrator
(d) An oscillator
Ans. (c) :
The figure given above shows the circuit of

which one of the following?
(a) Bi-stable multi-vibrator
(b) Schmitt trigger
(c) Mono-stable multi-vibrator
(d) Astable multi-vibrator
IES - 2008
Ans. (c) :
• Any AC input signal is converted into square wave
so the Schmitt trigger is also called as square wave
converter.
• It is also called amplitude comparator
• A comparator circuit with positive feedback is called
Schmitt trigger circuit. It exhibit Hysteresis
The given above circuit, phenomenon.
This is the monostable multi-vibrator monostable -a • It is a basically used Bistable multivibrator
one-shot as once externally triggered it returns back to 82. Pick the odd one out (One of the following type
it's first stable state. numbers is a negative output regulator)
Application of monostable multivibrator (a) LM 7912 (b) LM 7812
The monostable multivibrator is used as delay and
timing circuit. It is also used for temporary memories. It (c) LM 317 (d) LM 7805
is often used to trigger another pulse generator. It is Nagaland PSC CTSE (Diploma)-2018, Paper-I
used for regenerating old and workout pulses. KVS TGT (WE)- 2014
79. What is another name for one-shot Ans. (c) : LM 7912, 7805, 7812, 7905 are voltage
multivibrator? regulator ICs while LM 317 is a positive linear voltage
(a) Monostable regulator and LM 7912 is a negative output regulator.
(b) Astable 83. Pick the odd one out (one of the following is an
(c) Bistable adjustable output regulator)
(d) None of the above options (a) LM 337 (b) LM 7815
NIELIT Scientists- 2017 (c) LM 7918 (d) MC 7812C
Ans. (a) : Mono stable mltivibrator – Nagaland PSC CTSE (Diploma)-2018, Paper-I
• It is also called a single-shot or single swing or a one- Ans. (d) : LM 337, LM 7815 and LM 7918 are
shot multvibrator.
regulator while LM 7812C is a datasheet.
• Other names are; delay multivibrator and univibrator.
• It has one absolutely stable (stand-by) state and one 84. Which of the following circuits converts any
quasi-stable state. arbitrary waveform into square waveform?
80. The output time period of a transistorized (a) Hartley oscillator
monostable multivibrator using base resistance (b) Schmitt trigger
Rb and coupling capacitor Cb for the output (c) Differentiator
transistor is given by (d) RC phase shift oscillator
(a) Rb Cb (b) 0.69 Rb Cb RPSC LECTURER-10.01.2016
(c) 2 Rb Cb (d) 1.38 Rb Cb Ans. (b) :
TSGENCO AE - 2015
Ans. (b) : The width of monostable multivibrator output
pulse depends upon the RC time constant.
Hence it depends on the values of Rb Cb. The duration
of pulse is given by
T = 0.693 R b C b
81. Schmitt trigger is basically
(a) An astable multivibrator
(b) A mono stable multivibrator
Ans. (d) : Basically there are two types of voltage
regulators.
(i) Linear voltage regulator
(ii) Non linear or switching voltage regulator
• There are three types of switching voltage regulator
(i) Step up
(ii) Step-down
(iii) Inverter voltage regulator.
• There are two types of linear voltage regulator.
Schmitt trigger- A Schmitt trigger is a comparator (i) Series
circuit with hysteresis implemented by applying (ii) Shunt (Adjustable voltage regulator)
positive feedback to the non-inverting input of a
comparator or differential amplifier. It is an active 89. How can a monostable multivibrator be
circuit which converts any arbitrary waveform into modified into a ramp generator?
square waveform. (a) Connect a constant current source to trigger
output
85. When a sinusoidal voltage wave drives a
Schmitt Trigger, the output is a : (b) Replace resistor by constant current source
(a) Triangular wave (b) Rectified sine wave (c) Replace capacitor by constant current source
(c) Rectangular wave (d) Trapezoidal wave (d) Connect a constant current source to trigger
input
RRB JE-01.09.2019, 3:00 PM – 5:00 PM
RPSC Lect.- 2011
Ans. (b) : When we replace the resistor of the
Ans. (c) : When a sinusoidal voltage wave drives a monostable multivibrator circuit by a constant current
Schmitt trigger, the output is a rectangular wave. source, then the capacitor is charged linearly and
Schmitt trigger is also known as regenerative generates a ramp signal.
comparator, used to convert waveform of any shape to
rectangular/square wave.
86. The output impedance of a voltage regulator is
(a) Very small
(b) Very large
(c) Equal to the load voltage divided by the load I
TNPSC AE-2013
Ans. (a) : Output impedance is what is seen when
looking into power supply circuitry from output end.
The power supply output impedance depends on
weather. It is used as a voltage source. Hence output 90. Consider the following circuit :
impedance very small.
87. Bistable multivibrator can be induced to make
an abrupt transition from one state to the other
on application of
(a) an internal excitation
(b) an external excitation
(c) no excitation
TNPSC AE-2013
Ans. (b) : A Bistable multivibrator has two stable states What is the type of circuit given above?
and maintain a given output state indefinitely unless an (a) Monostable multivibrator
external trigger is applied forcing it to change state.
(b) Ramp generator
Bistable multivibrator can be switched over from one
stable state to other by the application of an external (c) VCO
trigger pulse, it requires two external trigger pulses (d) Bistable multivibrator
before it returns back to its original state. IES-2004
88. Which is not considered as a linear voltage Ans. (c) : Voltage-Controlled Oscillator (VCO) – It is
regulator? also known as voltage to frequency converter because
(a) Adjustable voltage regulator the output frequency changed by changing the input
(b) Series voltage regulator voltage VCO can be used for frequency and phase
(c) Shunt voltage regulator modulation.
(d) Switching regulator • It is used in function generators, phase-locked loops
RRB JE-01.09.2019, 3:00 PM – 5:00 PM and synthesizers.

03.
Electronics Measurements
and Instrumentation
5. The expected value of voltage across a resistor
(i) Error Analysis, Units and is 80V. however, the measurement gives a value
Dimensions of 79V. Then % error and relative accuracy
are-
1. A thermometer is calibrated 1500C to 2000C. (a) 1.25%, 0.9875 (b) 12.5 %, 0.09875
The accuracy is specified within ±0.25% . What (c) 0.125 %, 0.009875 (d) 1.025 %, 0.0009875
is the maximum static error?- UPPSC Poly. Tech. Lect.-22.03.2022, Paper-I
(a) ±0.1250 C (b) ± 0.2160C Y − Xn
(c) ± 0.3150C (d) ± 0.2500C Ans. (a) : % Error = n × 100
UPPSC Poly. Tech. Lect.-22.03.2022, Paper-I Yn
Ans. (a) : Span = Max. temperature – Min. temperature 80 − 79
= × 100
= 200-150 = 500C 80
The accuracy is ± 0.25% of instrument span = 1.25%
±0.25
Maximum static error = × 50 = ±0.125 C
0
Y − Xn 80 − 79
100 Relative accuracy (A) = 1 − n = 1−
Hence, the static error is ± 0.125 C.
0 Yn 80
2. Precision is defined as = 1 − 0.0125 = 0.9875
(a) Repeatability (b) Reliability 6. A 0-200 V voltmeter has guaranteed accuracy
(c) Uncertainty (d) Accuracy of 1 percent of full-scale reading. The voltage
UPPSC Poly. Tech. Lect.-22.03.2022, Paper-I measured by this instrument is 150 V. The
TNPSC AE-2014 percentage limiting
Ans. (a) : Precision–It is a measure of the (a) 25.00% (b) 12.50 %
reproducibility of the measurement. It is a measure of (c) 2.66% (d) 1.33%
degree of agreement within a group of measurements. ESE-2022
Precision is not the guarantee of accuracy.
Ans. (d) : Given, full scale reading = 200V
3. Which of the following is dynamic Guaranteed accuracy = 1% of full scale reading
characteristics of the measurement system?
(a) Accuracy (b) Resolution 1
= × 200 = 2V
(c) Speed of response (d) Sensitivity 100
UPPSC Poly. Tech. Lect.-22.03.2022, Paper-I Measured voltage = 150V
Ans. (c) : Dynamic Characteristics : Set of criteria 2
defined for the instruments which are rapidly changing % limiting error = 150 × 100
with time is called dynamic characteristics. The various % limiting error = 1.33%
dynamic characteristics are -
a. Speed of response 7. A voltage has a true value of 1.55 V. An analog
b. Measuring lag indicating instrument with a scale range of 0-
c. Fidelity 2.5 V shows a voltage of 1.48 V. What is the
d. Dynamic error relative error?
(a) –2.67% (b) –1.60%
4. The scale of a galvanometer is placed at a
distance of 0.4 m from the mirror. A deflection (c) –4.52% (d) –2.80%
of 44 mm is observed. What is the angle ESE-2022
through which coil has tuned? Ans. (c) : % relative error
(a) 22 × 10–3 rad (b) 33 ×10–3 rad Measured voltage − True voltage
(c) 44 ×10–3 rad (d) 55×10–3 rad = × 100
True voltage
UPPSC Poly. Tech. Lect.-22.03.2022, Paper-I
Given, measured voltage = 1.48V
Ans. (d) : Given, r = 0.4 m, d = 44 mm
True voltage = 1.55V
Deflection ( d ) = 2rθf
1.48 − 1.55
Then, = × 100 = −0.04516 × 100
d 44 ×10−3 1.55
θf = = –3
= 55×10 rad
2r 2 × 0.4 % relative error –4.52%
Electronics Measurements and Instrumentation 503 YCT

8. The measurement precision of an instrument 10.03 + 10.10 + 10.11 + 10.08
defines the smallest change in measured Ans. (a) : Iavg=
quantity that can be observed, which is called 4
= 10.08A
(a) accuracy of the instrument
Emax = Imax – Iavg = 10.11 – 10.08 = 0.03A
(b) precision of the instrument
(c) resolution of the instrument Emin = Iavg – Imin = 10.08 – 10.03 = 0.05A
(d) Significant figure of the instrument 0.03 + 0.05
Eavg = ±
ESE-2022 2
Ans. (c) : If the input is slowly increased from some Eavg = ± 0.04 A
arbitrary value, it will be found that the output does not 12. If the same measurement process is used
change at all until a certain increment is exceeded, this among different instruments and operators,
increment is known as resolution. In other words, it is over a longer time period, then the variations
the smallest change in a measured variable in which an arising out of it are called.
instrument will respond. (a) Measurement of length
9. Which one of the following statement is correct (b) Sensitivity
regarding standards of measurements? (c) Reproductability
(a) The primary standards are as accurate as the (d) Repeatability
international standards. DMRC AM S&T-2020
(b) The secondary standards are preserved at the Ans. (c) : If the same measurement process is used
‘International Bureau of Weights and among different instruments and operators, over a
Measures’ and not available to the ordinary
longer time period, then the variations arising out of it
users.
are called reproductability.
(c) The secondary standards are the absolute
Reproductability- It is define as the measure of
standards and not as accurate as the
repeatability of reading an instrument over a period of
international standards.
time.
(d) Working standards are used by manufacturers
Repeatability- The repetition of reading of an
for comparing and standardizing their
products. instrument taken over a period of time.
ESE-2022 Sensitivity-
small change in output 1
Ans. (a) : A standard is a physical representation of a sensitivity = =
unit of measurement. They are used for the small change in input Deflection factor
measurements of other physical quantities by 1 Ω
comparison methods. The primary standards are the Sensitivity = =
absolute standards which can be used as ultimate I FSD Volt
reference standards. Primary standards have the highest 13. Accuracy is the state of being ‘______’,
possible accuracy and stability. International standards whereas precision is ‘the state of being ‘_____’.
are defined on the basis of international agreement and (a) Correct, correct (b) Exact, correct
represent the units of measurements which are closed to (c) Exact, exact (d) Correct, exact
the possible accuracy attainable with present day DMRC AM S&T-2020
technology and scientific method. Hence, the primary
Ans. (d) : Accuracy is the state of being correct
standards are as accurate as the international standards.
whereas precision in ‘the state of being exact’.
10. A 0-25 A ammeter has a guaranteed accuracy Accuracy- The closeness of a measured value to a
of 1% of full scale reading. The current standard or known value.
measured by this instrument is 10A. The
limiting error in % is, Precision- The closeness of the measurements to each
other.
(a) 25.0 % (b) 2.0 %
(c) 2.5 % (d) 1.0 % 14. Which measurement errors also include wrong
RPSC ACF & FRO 23.02.2021 readings due to parallax errors?
RRB JE-31.08.2019, 10 AM – 12 PM (a) Observational errors
(b) Environmental errors
25 × 1 (c) Random errors
Ans. (c) : Error = = 0.25
100 (d) Instrumental errors
0.25 DMRC AM S&T-2020
% error for 10A = × 100 = 2.5%
10 Ans. (a) : Observational errors also include wrong
11. A set of independent current measurements readings due to parallax errors.
was recorded as 10.03, 10.10, 10.11 and 10.08 15. Which errors arise due to the hysteresis of the
A. Calculate the range error. equipment or due to friction
(a) ± 0.04 A (b) ± 0.028 A (a) Observational errors (b) Random error
(c) ± 0.065 A (d) ± 0.033 A (c) Environmental error (d) Instrumental errors
RPSC ACF & FRO 23.02.2021 DMRC AM S&T-2020
Ans. (d) : Instrumental errors arise due to the hysteresis Ans. (c) : S.I. the international system of units are
of the equipment or due to friction. divided into three classes.
Classification of error- (1) Base units
(2) Derived units
(3) Supplementary units
• Supplementary units
Plane angle - Radian
Solid angle - Steradian
16. The _____ denotes the smallest change in the 20. A 0-300 V Voltmeter has an error of ± 2% of
measured variable to which the instrument full deflection. What would be the range of
responds. readings if true voltage is 30 V ?
(a) sensitivity (b) measurement of length (a) 20 V to 40 V (b) 29 V to 30.6 V
(c) repeatability (d) reproductability (c) 24 V to 36 V (d) 28 V to 32 V
DMRC AM S&T-2020 MPPSC Forest Service Exam.-2014
Ans. (a) : The sensitivity denotes the smallest change in Ans. (c) : Range of voltmeter = (0-300)V
the measured variable to which the instrument responds. So, full scale reading = 300V
17. The difference between the indicated value and Full scale error = ±2%
true value of a quantity is known as
Hence, error in voltmeter at full scale
(a) Relative error (b) Absolute error
2
(c) Gross error (d) Dynamic error = 300 × = ±6V
Nagaland PSC CTSE (Degree) -2016, Paper I 100
Nagaland PSC CTSE (Degree) -2015, Paper I i.e. 6V will be the guaranteed accuracy error of
Mizoram PSC AE/SDO 2012 Paper I instrument.
TNPSC AE -2014 Therefore, the range of voltage for 30V
IES -1999 = 30 ± 6
Ans. (b) : Absolute error (δA) = Am–At 30 − 6 = 24
Where Am = measured value 30 + 6 = 36
At = true value. = 24 V to 36V
Relative static error is defined as the ratio of absolute
static error to the true value of the quantity under 21. Number of significant figure in 0.130450 is
measurement. (a) 7 (b) 5
δA (c) 8 (d) 6
εr = Nagaland PSC CTSE (Diploma)-2018, Paper-I
At
Ans. (d) : Significant figure-
18. The percentage limiting error, in the case of an (1) Non-zero digits are always significant.
instrument reading of 8.3 V with a 0 to 150
voltmeter having a guaranteed accuracy of 1% (2) Any zeros between two significant digits are
full-scale reading is significant.
(a) 1.810% (b) 0.181% (3) A final zero or trailing zeros that are also to the right
(c) 18.10% (d) 0.0018% of a decimal point in a number of significant. According
RPCS Lect. 2011, IES-2013, 1993 to these rules the given number 0.130450 has 6
significant figure like (1,3,0,4,5,0).
Ans. (c) : GAE = 1% of full scale reading.
(Full scale reading) VFSD = 150V 22. Subtracting 437±4 from 462±4 would yield a
Measured voltage Vm = 8.3 V. result with percentage error of
V (a) ±4% (b) ±16%
% Limiting Error = % GAE × FSD (c) ±8% (d) ±32%
Vm
150
= 1% × Nagaland PSC CTSE (Diploma)-2016, Paper-I
8.3
Ans. (d) : a = 437 ± 4
= 18.10%
b = 462 ± 4
19. Steradian is a ∆a + ∆b
(a) Base unit % error = × 100
(b) Derived unit a−b
(c) Supplementary unit ± (∆a + ∆b) = ± 8
(d) Unit of measuring susceptance b – a = 462 – 437 = 25
Nagaland PSC CTSE (Degree) -2016, Paper I % error = ± 8 × 100 = ± 32%
Nagaland PSC CTSE (Degree) -2015, Paper I 25
23. The maximum percentage error in the sum of Ans. (b) : Measured value (Am) = 100 µF
two voltage measurements when V1 = 100 V ± True value (At) = 110 µF
1% and V2 = 80 V ± 5% is
A − At
(a) 180 V ± 6.0% (b) 180 V ± 4.0% % Relative error = m × 100
(c) 180 V ± 2.8% (d) 180 V ± 3.6% At
RPSC VP/Suptd. ITI 05.11.2019 100 − 110
= ×100
TSGENCO AE-2015 110
Ans. (c) : V = V1+ V2 = 100+80=180 −10
% εr = ×100 = −9.09%
∆V1 ∆V 110
= 1% , 2 = 5% 26. Consider the circuit as shown below, Z1 is an
V1 V2
unknown impedance and measured as Z1 =
 V ∆V V ∆V  (Z2Z3)/Z4. The uncertainties in the value of Z2,
% error = ±  1 . 1 + 2 . 2  Z3 and Z4 are ±1%,±1% and ±3% respectively.
 V V1 V V2 
100 80 
= ± × 1% + × 5% 
180 180 
 500 
= ± %  = ± 2.8%
 180 
answer:
List – I List - II
P. Precision i. The smallest change in The overall uncertainty in the measured value
the input quantity of Z1 is
which can be detected (a) 11% (b) ±4%
with its certainty.
(c) ±5% (d) 5%
Q. Accuracy ii. Closeness of the
IES-2003
reading with its true
value. Z Z 
Ans. (c) : Z1 =  2 3 
R. Resolution iii. Measurement of the  Z4 
reproducibility of the
measurement. δZ1  δZ δZ δZ 
hence % = ± 2 + 3 + 4 %
S. Static iv. Ratio of infinitesimal Z1  Z2 Z3 Z4 
Sensitivity change sensitivity in = ± [1 + 1 + 3]% = ± 5%
output to infinitesimal 27. A wattmeter has a range of 1000 W with an
change in input. error of ±1% of full scale deflection, If the true
P Q R S power passed through it is 100W, the relative
(a) ii iii i iv error would be
(b) iii ii iv i (a) ±10% (b) ±5%
(c) iii ii i iv (c) ±1% (d) ±0.5%
(d) ii iii iv i Mizoram PSC AE/SDO 2012-Paper-I
IES-2003 Ans. (a) :
Ans. (c) : (i) Precision - Measurements of the PFS = 1000 W measured value = 100W
reproducibility of the measurement. % error = 1% error = 10 W
(ii) Accuracy - Closeness of reading with the value. 1
error = 1000× = 10W
(iii) Resolution - the smallest change that can be 100
detected with certainty. Measured power = 100±10
(iv) Static sensitivity - Ratio of infinitesimal change
10
sensitivity in o/p to infinitesimal change in input. % relative error = × 100 = 10%
100
25. The measured value of a capacitor is 100µF.
28. In an experiment the power factor was
The true value of the capacitor is 110µF. The determined by measuring power, voltage and
percentage relative error is current. The relative errors in their
(a) 9.99% (b) 9.09% measurement are, respectively, ± 0.5%; ± 1%
(c) 10.0% (d) 4.76% and ±1%. The relative limiting of error in the
IES-2003 power factor would be
(a) ± 0.5% (b) ± 1.5% (c) uncertainty of the value of gravitational
(c) ± 2.0% (d) ± 2.5% constant
UPSC JWM-2016 (d) all of these
Ans. (d) : Power = ±0.5% TNPSC AE-2008
Voltage = ±1% Ans. (d) : The accuracy of the dead weight tester is
affected due to the friction between the piston and
Current = ±1% cylinder, and due to the uncertainty of gravitation
Power ( P ) constant (g).
Power factor =
Voltage ( V ) × Current ( I ) 33. A d-Arsonval movement is rated at 50
microamperes. Its sensitivity is
δPF  δP δV δI 
% = + + % (a) 20000 Ω/V (b) 200000 Ω/V
PF  P V I  (c) 200 Ω/V (d) 2000 Ω/V
= [(±0.5) + (±1) + (±1)]% MPPSC Forest Service Exam.-2014
= ±2.5% Ans. (a) : d-Arsonval current = 50 µAmp
29. Random errors are otherwise known as 1 1
(a) residual errors (b) gross errors Sensitivity = =
I FSD 50 × 10−6
(c) threshold errors (d) instrumental errors
TNPSC AE-2008 = 1000000 = 20000Ω / V
Ans. (a) : Random error caused by uncontrollable error 50
which can not be eliminated. Hence it treated as residual L
error. 34. The term has the dimension of
C
30. A d.c. circuit can be represented by a voltage (a) Time (b) Capacitance
source of 10V in series with an output
(c) Inductance (d) Resistance
resistance of 1 kΩ. An ammeter of 50 Ω
resistance is connected to the source terminals
for measurement of current. The accuracy of Ans. (d) :
measurement is nearly L
(a) –4.8 percent (b) + 4.8 percent The term has the dimension of resistance.
C
(c) 99 percent (d) 95.2 percent
TNPSC AE-2008 35. Current passing through a resistor of 100+
0.2Ω is 2.00 +0.01 A. Computed value of power
Ans. (b) : When ammeter is not connected will be
V 10 (a) 400 + 0.21W (b) 400+ 0.002W
I1 = = = 10 mA
R 1 × 103 (c) 400+5.2W (d) 400+4.8W
When ammeter is connected- Nagaland PSC CTSE (Degree) -2015, Paper I
I2 =
V
=
10
= 9.523mA Ans. (a) : R = 100 ± 0.2 Ω
R + R m 1050 I = 2.00 ± 0.01
I2 = 9.523 × 10–3 = 9.523 mA Power consumed, P = I2 R = 22 × 100 = 400 Watts
I −I 10 − 9.523 Limiting error, εp = ± (2εI +εR)
Accuracy = 1 2 ×100 = ×100 = 4.8% = ± (2 × 0.01 + 0.2)
I1 10
= ± 0.22
31. Changes in atmospheric temperature, humidity P = (400 ± 0.22) watt
etc. cause
36. The major difference between a current probe
(a) systematic errors and voltage probe is that the current probe
(b) instrumental errors (a) Has a lower input impedance
(c) cumulative errors (b) Can measure a.c. signals only
(d) environmental errors (c) Provides a method of coupling
TNPSC AE-2008 (d) All the above
Ans. (d) : Changes in atmospheric temperature, Nagaland PSC CTSE (Degree) -2015, Paper I
humidity etc caused by environmental error. An Ans. (a) : A test probe is a physical device used to
environment error is an error in calculation that are connect electronic test equipment to a device under test.
being a part of observations due to environment. The major difference between a current probe and
32. The accuracy of the dead weight testers is voltage is that the current probe has a lower input
affected by impedance.
(a) friction force between the piston and the 37. A platinum thermometer has a resistance of
cylinder 100Ω at 25ºC. The resistance at 65ºC for its
(b) uncertainty of the value of the effective area resistance temperature co-efficient of
of the piston 0.00392/ºC will be nearly
(a) 107.3Ω (b) 115.7Ω 43. While measuring resistance by the voltmeter-
(c) 123.3Ω (d) 131.7Ω ammeter method, the maximum possible
IES-2020 percentage errors in the voltmeter and
ammeter are ± 1.4% and + 1.1% respectively.
Ans. (b) : Given that, Then the maximum possible percentage error
R25 = 100Ω in the value of resistance will be:
t1 = 25°C (a) ± 2.5% (b) ± 3%
α1 = 0.00392/°C (c) ± 0.3% (d) ± 1.5%
R65°C = ? APPSC Poly. Lect. 15.03.2020
t2 = 65°C Ans. (a) : Resistance = voltmeter/current maximum
R2 = R1 [1+α1 (t2–t1)] possible error is given by adding the errors in case of
R65°C = 100 [1+0.00392(65–25)] product or quotient of two numbers.
Voltmeter reading V
= 100 [1+0.1568] Measured resistance R m = =
= 100×1.1568 Ammeter reading I
= 115.68 δR m  δV δI 
Error in resistance = + %
38. The static error band of an instrument implies Rm  V I 
the
= ± (1.4 + 1.1) % = ±2.5%
(a) Accuracy of the instrument
(b) Irreparability of the instrument 44. The resistance of a circuit is measured from the
(c) Error caused when the pen is stopped at some current flowing through and power fed to that
deflection circuit. The uncertainty in current and power
are ±1% and ±2% respectively. The
(d) Error introduced in low varying inputs
uncertainty in the measurement of resistance is
Nagaland PSC CTSE (Degree)-2017, Paper-I (a) ± 2% (b) ± 3%
Ans. (c) : Error caused when the pen is stopped at some (c) ± 4% (d) ± 5%
deflection. APPSC Poly. Lect. 15.03.2020
39. Which of the following is not a static Ans. (c) : Now power = I2R
characteristic? Power
(a) drift (b) dead zone R=
I2
(c) sensitivity (d) fidelity P=I R2
TSGENCO AE-2015 P
R= 2
Ans. (d) : Fidelity is not a static characteristic. Fidelity I
is defined as the degree to which a measurement system δR δP δI
is capable of faithfully reproducing the change in input = +2
without any dynamic error. R P I
= ± (2% + 2×1)% = ± 4%
40. Parameter defined as the nearness of the
45. Which one of the following is composed of two
indicated value to the true value of the quantity
being measured is characteristics: conformity and the number of
significant figures to which a measurement
(a) accuracy (b) resolution
may be made?
(c) reproducibility (d) static error (a) Sensitivity (b) Resolution
TSGENCO AE-2015 (c) Accuracy (d) Precision
Ans. (a) : Accuracy for any measuring instrument IES-2020
indicate the closeness of measured value to true value.Ans. (d) : Precision of a measuring instrument is related
If both are equal then instrument is more accurate. to reproducibility and repeatability. It is the number of
41. _______ is defined as the difference between significant figures to which a measurement may be made.
the largest and smallest reading of instrument.46. A thermometer reads 95.45ºC and the static
(a) span (b) range correction given in the correction curve is –
(c) dead space (d) resolution 0.08ºC. The true value of temperature will be
TSGENCO AE-2015 (a) 95.37ºC (b) 95.45ºC
(c) 95.65ºC (d) 95.73ºC
Ans. (a) : Span is defined as the difference between the IES-2020
largest and smallest value of any measurement Ans. (a) : Given that,
instrument. Measured value Am = 95.450C
42. The wide band noise in an electronic Static correction = –0.080C
measurement system is sometimes called: True value (At) = ?
(a) Johonson noise (b) Conducted noise δc = A t − A m
(c) White noise (d) Radiated noise
A t = δc + A m
Ans. (c) : The wide band noise in an electronic A t = −0.08 C + 95.45 C
0 0
0
measurement is called white noise. At = 95.37 C
47. In a parallel circuit having two branches, the Ans. (c) : Given, True value (At) = 1.5 V,
current in one branch is I1 = 100 ± 2A and in Measured value (Am) = 1.46 V
the other is I2 = 200 ± 5A. Considering errors in ∵ Absolute Error (δA) = Am – At
both I1 and I2 as limiting errors, the total = 1.46 – 1.5
(a) 300 ± 5A (b) 300 ± 6A δA = –0.04
(c) 300 ± 7A (d) 300 ± 8A δA −0.04
IES-2019 Relative error ( %ε r ) = = ×100
At 1.5
Ans. (c) : I = I1+I2= 100+200= 300
4
limiting error of total current =−
δI = ± ( δI1 + δI2 ) 1.5
40
= ± (2 + 5) = ± 7 = − = –2.66%
15
Total current = I1+I2 ± error = 300 ± 7 %ε r = –2.66%
48. A resistance is determined by voltmeter- 50. A liquid flows through a pipe of 100 mm
ammeter method. The voltmeter reads 100V diameter at a velocity of 1 m/s. If the diameter
with a probable error of ± 12V and the is guaranteed within ± 1% and the velocity is
ammeter reads 10A with a probable error of ± known to be within ± 3% of measured value,
2A. The probable error in the computed value the limiting error for the rate of flow is
of the resistance will be nearly (a) ± 1% (b) ± 2%
(a) 0.6 Ω (b) 1.3 Ω (c) ± 3% (d) ± 5%
(c) 2.3 Ω (d) 3.6 Ω IES-2017
IES-2019 Ans. (d) : We know that,
R=
V Volume A × L
Ans. (c) : We know that Rate of flow = = = A × Velocity
I Time T
Q = A ×V
rv = ±12 and rI = ± 2 πd 2
Q= ×V
Probable error in resistance due to voltage 4
δR   δd  δV 
 = ± [ 2 ×1 + 3]
rRV = × rV % limiting error = ±  2   +
δV   d  V
δV 1 = ± 5%
rRV = × rV = × rV
δV × I I 51. Precision is composed of two characteristics, one
12 is the number of significant figures to which a
rRV = ± = ±1.2Ω measurement may be made, the other is :
10
(a) Conformity (b) Meter error
Probable error in resistance due to current
(c) Inertia effects (d) Noise
δR
rRI = × rI IES-2016
δI Ans. (a) : Precision is composed of two characteristics
δV one is the number of significant figures to which a
= × rI measurement may be made and the other is conformity.
δI × I
Instrument with more significant figure has more
V 100
= 2 × rI = 2 × ( ± 2 ) precision.
I 10 52. The resolution of an indicating instrument can
= rRI = ± 2Ω be defined as:
Now probable error in total resistance 1. Variation in the meter reading for the
same applied input
= ( rRV ) + (rRI ) 2
2
2. Detectable change in the deflection due to

= (1.2)2 + (2) 2 smallest change in the applied input
3. Detectable change in the output due to
=2.33Ω drifting of pointer.
49. A voltage has a true value of 1.5 V. An analog (a) 1 only (b) 2 only
indicating instrument with a scale range of 0 – (c) 3 only (d) 1 and 3
2.5 V shows a voltage of 1.46 V. The relative
error is : IES-2016
(a) –4.0% (b) 26.6% Ans. (b) : Resolution of an indicating instrument can be
(c) –2.66% (d) –0.04% defined as smallest or detectable change in the
KVS TGT (WE)- 2017 deflection due to smallest change in the applied input.

53. Dynamic characteristics of instruments leading 57. A 1 kΩ resistor with an accuracy of ± 10%
to variations during measurement are: carries a current of 10 mA. The current was
1. Speed of response measured by an analog ammeter on a 25 mA
2. Fidelity range with an accuracy of ± 2%. The accuracy
3. Dynamic error in calculating the power dissipated in the
Which of the above are correct? resistor would be
(a) 1 and 2 only (b) 1 and 3 only (a) ± 4% (b) ± 12%
(c) 2 and 3 only (d) 1, 2 and 3 (c) ± 15% (d) ± 20%
IES-2016 IES-2015
Ans. (d) : The performance characteristics of an Ans. (d) : Error at 25mA = 2%
instrument are mainly divided into two categories - δR
1. Dynamic characteristics = 10%
R
2. Static characteristics
25
1. Dynamic Characteristics : Set of criteria defined for so error at 10mA = × 2 = 5%
the instruments which are rapidly changing with time is 10
2
called dynamic characteristics. The various dynamic P=I R
characteristics are - δI δR
now error or accuracy of power (P) = 2 × +
a. Speed of response I R
b. Measuring lag = 2×5+10 = 20%
c. Fidelity 58. Consider the following statements regarding
d. Dynamic error error occurring in current transformer :
54. The reliability of an instrument refers to: 1. It is due to the magnetic leakage in
(a) Degree to which repeatability continues to secondary winding.
remain within specified limits 2. It is due to power consumption in the
(b) The extent to which the characteristics remain metering circuit
linear 3. It is due to the exciting mmf required by
(c) Accuracy of the instrument the primary winding to produce flux
(d) Sensitivity of the instrument 4. It is due to the non-linear relation between
IES-2016 flux density in the core and magnetizing
Ans. (a) : Reliability of an instrument refers degree to force
which repeatability continues to remain within specified Which of the above statements are correct?
limit is concerned with consistency and replicability or (a) 1, 2, 3 and 4 (b) 1, 2 and 4 only
with repeatability over specified (c) 2, 3 and 4 only (d) 1, 2 and 3 only
IES-2015
55. Error caused by the act of measurement on the
physical system being tested is Ans. (a) : Causes of error in current transformer–
(a) Hysteresis error (b) Random error • The magnetic leakage in the secondary winding
(c) Systematic error (d) Loading error • It is due to power consumption in the metering circuit.
IES-2015 • It is due to the exciting MMF required by the primary
Ans. (d) : Error caused by the act of measurement on winding to produce flux.
the physical system being tested is loading error. • The flux density in the core is not a linear function of
Loading Error– It is the most common type of error magnetising force [i.e. core becomes saturated].
which is cause by the instrument in measurement work. 59. The current in a circuit is measured as 235µA
56. Four independent observations recorded and the accuracy of measurement is ± 0.5%.
voltage measurement of 110.02 V, 110.11 V, This current passes through a resistor 35 kΩ ±
110.08 V and 110.03 V. The average range of 0.2%. The voltage is estimated to be 8.23V. The
error will be error in the estimation would be
(a) 110.06 V (b) 0.05V (a) ± 0.06V (b) ± 0.04V
(c) ± 0.045V (d) ± 0.9V (c) ± 0.016V (d) ± 0.1V
IES-2015 IES-2014
Ans. (c) : Measured voltages are, V1 = 110.02V , V2 = Ans. (a) : Given,
110.11V, V3 = 110.08V , V4 = 110.03V. δV  δI δR 
= ± + = ±[0.5 + 0.2] = ± 0.7%
 V − Vmin 
The average range of error = ±  max V I R 

 2  δV
= ±0.007
 110.11 − 110.02  V
= ± 
 2  So δV = 0.007 × V
0.09 δV = 0.007 × 8.23
=± = ± 0.045V δV = ± 0.0576V 0.06V
2

60. The expected value of the voltage across a 64. A resistance is measured by a voltmeter-
resistor is 80V. However, the voltmeter reads ammeter method using DC excitation and a
79V. The absolute error in the measurement is voltmeter of very high resistance connected
(a) 0.875 V (b) 0.125 V directly across the unknown resistance. If the
(c) 1.00 V (d) 1.125 V voltmeter and ammeter are subject to
IES-2014 maximum error of ±2.4% and ±1.0%
respectively, then the magnitude of maximum
Ans. (c) : VT = 80V, Vm = 79V error in the value of resistance obtained from
absolute error (δA) = Vm – VT = 79 – 80 the measurement is nearly
= – 1 Volt(Voltage can't be negative) (a) 1.4% (b) 1.7%
61. A current of 2 ± 0.5% a passes through a (c) 2.4% (d) 3.4%
resistor of 100 ± 0.2%Ω. The limiting error in IES-2012
the computation of power will be δV
(a) 0.7% (b) 0.9% Ans. (d) : = ± 2.4%
V
(c) 1.2% (d) 1.5% δI
IES-2014 = ± 1.0%
I
Ans. (c) : I = 2 ± 0.5% A V
R = 100 ± 0.2% Ω V = IR, R =
I
P = I 2R
δR  δV δI 
δP  δI δR  Error in resistance, = ± + 
= ± 2 + R  V I 
P  I R 
= ± (2.4 + 1.0)
= ± [ 2 × 0.5 + 0.2] =1.2% δR
= ± 3.4%
62. A voltmeter reads 40 V on its 100 V range and R
an ammeter reads 75 mA on its 150 mA range 65. Two milli ammeters with full scale currents of
in a circuit. Both the instruments are 1 mA and 10 mA are connected in parallel and
guaranteed ±2% accuracy on FSD. The they read 0.5 mA and 2.5 mA respectively.
limiting error in the measured power is Their internal resistance are in the ratio of
(a) 4 % (b) 5 % (a) 1 : 10 (b) 10 : 1
(c) 9 % (d) 12 % (c) 1 : 5 (d) 5 : 1
IES-2014 IES-2010
Ans. (b) :
%GAE × Fullscale
Ans. (c) : Voltmeter L.E. = V 1
Measured Value Q I = , I ∝ , I 1 = 1, I 2 = 10
R R
2 ×100
% L.E of voltmeter = = 5% I1 R 2
40 So =
I2 R1
%GAE × Fullscale
% L.E. of ammeter = 1 R2
Measured value =
10 R1
2 × 150 × 10−3 R2 1
= = 4% =
75 × 10−3 R 1 10
Limiting error of power = 5% + 4% = 9% R1: R2 = 10:1
63. A voltmeter, having a guaranteed accuracy of 66. The accuracy of 0-10 mA meter is ±2%. What
1%, reads 9V on a 0V to 150 V range full-scale is its accuracy while taking a reading of 5 mA?
reading. The percentage limiting error is (a) ±0.5% (b) ±1%
(a) 0.167% (b) 0.67% (c) ±2% (d) ±4%
(c) 16.7% (d) 0.0167% IES-2008
IES-2014
Ans. (d) : GAE = 2% IFSD = 10 mA
Ans. (c) : Given, % GAE = 1 Im = 5 mA
Measured value = 9V GAE × IFSD
Full scale reading = 150V % L.E. =
Im
%GAE × Fullscale value
% L.E. = 2% × 10
measured value =
5
1× 150 50 L.E. = 4%
= ⇒ = 16.667% 16.7%
9 3 So, the accuracy while taking a reading of 5 mA is 4%.
67. Match List-I (Term) with List-II (Statement) C2 = 120 ± 1.5 µF
and select the correct answer using the code Resultant capacitance in parallel
given below the lists: Ceq = C1 + C2
List-I List-II Limiting error of resultant capacitance-
A. Relative 1. The ability of the device to δ Ceq = ± (δ C1 + δ C2)
error give identical output when = ± (2.4 + 1.5)
repeat measurement are δ Ceq = ± 3.9 µF
made with the same input 69. The expression for mean torque T of an electro
signal. dynamic wattmeter can be expressed as
B. Precision 2. The ratio of difference T∝MaVbZc, where M is mutual inductance
between measured value
between fixed and moving coils, V is applied
and the true value to the
true value of the measurand voltage and Z is impedance of coil. What are
C. Calibration 3. The smallest increment in the values of the constants a, b and c?
measurand that can be (a) a = 1, b = 2 and c = –2
detected with certainty by (b) a = 1, b = 1 and c = –1
the instrument (c) a = 1, b = –2 and c = 2
D. Resolution 4. The process of making (d) a = 2, b = 2 and c = –1
adjustments on the scale so IES-2008
that the instrument reading
conform to an accepted Ans. (a) : Torque in electrodynamometer wattmeter
standard I2 dM 1 V 2 dM
Codes: Td = =
K dθ K Z2 dθ
A B C D
(a) 2 3 4 1 V 2 dM
(b) 4 1 2 3 Td ∝ ……….....(i)
Z 2 dθ
(c) 4 3 2 1
So, T ∝ Ma Vb Zc ......(ii)
(d) 2 1 4 3
IES-2008 From equation (i) the value of a, b and c will be-
Ans. (d) : Relative Error:- It is the ratio of absolute a = 1 , b = 2 , and c = –2
error to the true value of the measured value. 70. A 0-250V voltmeter has guaranteed accuracy of
δA 1% full-scale reading (deflection). The voltage
εr = measured by this instrument is 100V. The
AT
limiting error is given by
Absolute error (δA) = Measured value – True value (a) 1.25% (b) 25%
AT = True value (c) 0.25% (d) 2.5%
Precision- It is the measure of the reproducibility of the IES-2008
measurement. Or the ability of the device to give
identical output when repeat measurements are made be Ans. (d) : Given,
same input signal. Full scale voltage (VFSD) = 250V
Calibration- The process of making adjustments on the GAE = 1%
scale so that the instrument reading conform to an Measured value (Vm) = 100V
accepted standard.
V 250
Resolution- The smallest change in input which can be % L.E. = % GAE × FSD = 1 ×
detectable by an instrument is called resolution. Vm 100
68. Two capacitance, C1 = 150 ± 2.4µF and % L.E. = 2.5%
C2 = 120 ± 1.5 µF are connected in parallel. 71. Which one of the following is the most stable
What is the limiting error of the resultant
frequency primary atomic standard for
capacitance C?
frequency?
(a) 0.9µF (b) 1.95µF
(a) Cesium beam standard
(c) 3.9µF (d) 4.8µF
(b) Hydrogen maser standard
IES-2008
(c) Rubidium vapor standard
Ans. (c) : Given,
(d) Quartz crystal standard
IES-2005
Ans. (a) : The most stable frequency in the world are
cesium beam standard, including cesium fountain and
C1 = 150 ± 2.4 µF hydrogen masers.
72. A voltmeter has a range of 0–20 V and 74. 0-150 voltmeter has an accuracy of 1% of full
manufacturer rates its accuracy as ±1% fsd. scale reading. The voltage measured by the
Match List-I (Voltage Values) with List-II instrument is 75V. The limiting error is
(Error as Percentage of True Value) and select (a) 1% (b) 2%
the correct answer using the codes given below (c) 2.5% (d) 3%
the lists: IES-2019, 2001
List-I List-II Ans. (b) : VFSD = 150V, %GAE = 1%
A. 2V 1. 4% Vm = 75V
B. 5V 2. 10% V 1% × 150
C. 10V 3. 2% % L.E. = % GAE × FSD =
Vm 75
D. 20V 4. 1%
L.E. = 2%
Codes:
A B C D 75. Which one of the following is the best definition
of accuracy?
(a) 3 1 2 4
(a) It is the measure of consistency or
(b) 2 1 3 4
reproducibility of measurements.
(c) 2 4 3 1
(b) It is the ratio of change in output signal to the
(d) 3 4 2 1 change in input signal
IES-2004 (c) It is the smallest change in measurable input
Ans. (b) : Guaranteed accuracy = ± 1% (d) It is the closeness with which an instrument
Full scale range of voltmeter VFSD = 20V approaches the true value of the quantity
V being measured.
%L.E. = %GAE × FSD IES-2001
Vm
Ans. (d) : Accuracy is the closeness with which an
When, Vm = 2V instrument approaches the true value of the quantity
20 being measured. Precision is defined as the measure of
% L.E. = 1× = 10%
2 consistency or reproducibility of measurement.
When, Vm = 5V 76. The dimension of flux density is
20 (a) MT–1Q–1 (b) MT–2Q–2
% L.E. = 1 × = 4% (c) MT Q 1 1
(d) MT–1Q–2
5
When, Vm = 10V IES-2000, 1998
20 Ans. (a) : Dimension of flux density
% L.E. = 1 × = 2% φ = ML2T–2A–1
10
When, Vm = 20V φ ML2T −2 A −1
B= =
20 A [L2 ]
% L.E. = 1 × = 1%
20 B = ML0T–2A–1 Q Q = [AT]
73. The resistivity of the wire material can be B = [MT–1Q–1]
expressed in terms of LMTI system of 77. An ammeter of range 0-25 A has a guaranteed
dimensional parameter as accuracy of 1% of full-scale reading. The
(a) ML2T2I–2 (b) ML2T3I–2 current measured by the ammeter is 5A. The
3 –3 –2
(c) ML T I (d) ML3T2I–2 limiting error in the reading is
IES-2001 (a) 2% (b) 2.5%
R.A (c) 4% (d) 5%
Ans. (c) : Resistivity of material ρ =
l IES-2018, 2000
Unit of resistivity = Ω-m Ans. (d) : Full scale range IFSD = 25A
V W %GAE = 1%
R= = Measured value, Im = 5A
I q.I
%GAE × I FSD 1 × 25
q=It % L.E. = =
Im 5
W
R= 2 L.E. = 5%
I t
78. "The current internationally recognized unit of
WA  ML2 T −2   L2  time and frequency is based on the cesium
ρ= =
I2 tl I 2 TL clock, which gives an accuracy better than 1µs
Resistivity = Ω-m = [ML3T–3I–2] per day." This statement is related to

(a) Working standards RT = R1 + R2 ⇒ 36 + 75 = 111 Ω
(b) International standards δRT = ±[δR1 + δR2] Ω
(c) Primary standards δRT = ± [1.8 + 3.75] Ω
(d) Secondary standards
δRT = 5.55 Ω
IES-2000
RT = 111 ± 5.55 Ω
Ans. (c) : The current internationally recognized unit of
time and frequency is based on the cesium clock, which 82. In terms of LMTQ system of dimensional
gives an accuracy better than 1 µs per day. This parameters, the dimension of 'permittivity' can
statement is related to the primary standard. be expressed as
• Primary standards are used in calibration of working (a) L–3M–1T2Q2 (b) L–1M–1T2Q2
2 –1 –1
standards. (c) L MT Q (d) L–2M–1T2Q2
79. A 300V full-scale deflection voltmeter has an IES-1997
accuracy of ±2%, when it reads 222V. The Ans. (a) : From Coulomb's law-
actual voltage 1 qq
(a) lies between 217.56V and 226.44V F= × 12 2
4πε0 r
(b) lies between 217.4V and 226.6V
(c) lies between 216V and 228V 1 qq
(d) is exactly 222V ε0 = × 12 2
4π F r
IES-1999
Q1Q2
Ans. (c) : 2% of 300V = 6 ε0 ∝ F = ma, {a = [LT–2]}
Actual voltage = 222 ± 2% × 300 F × r2
300 F = [MLT–2]
= 222 ± 2 × [Q 2 ]
100 ε0 =
= 222 ± 6 [MLT −2 ][L2 ]
So the actual voltage will lie between 216 V and 228V Dimension of permittivity- ε0 = [M–1L–3T2Q2]
80. The error in measurement of a DC voltmeter 83. With reference to 'random errors' in
with input signal: 1.5 V, voltage range: 2 V, measurement, the standard deviation σ can be
accuracy: ± (25 ppm of reading + 5 ppm of expressed, in terms of deviation of any
range) is individual observation from the mean of the
(a) ± 50 µV (b) ± 30 µV group 'dm' and the number of observations in
(c) ± 47.5 µV (d) ± 10 µV the group 'n' as
∑ dm ∑ d 2m
Ans. (c) : given Reading = 1.5, Range = 2 (a) σ = (b) σ =
n n
According to question,
Error = ± [25 ppm of Reading + 5 ppm of Range] ∑ d 2m ∑ d 2m
(c) σ = (d) σ = 0.6745
 25 × 1.5 5 × 2   37.5 10  n −1 n −1
=± + 6 = ± 6 + 6 
 10 6
10   10 10  IES-1997
= ± 47.5 µV Ans. (b) : Standard deviation or the root mean square
deviation is an important term in the analysis of random
81. Two resistors R1 = 36 ohms and R2 = 75 ohms, errors.
each having tolerance of ±5% are connected in
series. The value of the resultant resistance will ∑ d 2m
be. Sample standard deviation =
n −1
(a) 111 ± 0 ohm (b) 111 ± 2.778 ohm
(c) 111 ± 5.55 ohm (d) 111 ± 7.23 ohm ∑ d 2m
Population standard deviation =
IES-1998 n
Ans. (c) : R1 = 36 ± 5% , R2 = 75 ± 5% 84. Two resistance R1 and R2 are connected as
shown in the given figure. If R1 = 528 ± 5Ω and
R2 = 325 ± 3Ω, then the total resistance RT will
If resistors are connected in series– be
RT = R1 + R2
δR1 5 × 36
= 5% , δR1 = ± = ±1.8Ω
R1 100
δR 2 5 × 75
= 5% , δR 2 = ± = ±3.75Ω (a) 583 ± 2Ω (b) 853± 5Ω
R2 100
(c) 853 ± 3Ω (d) 853 ± 8Ω
R1 = 36 ± 1.8 Ω , R2 = 75 ± 3.75 Ω IES-1996
Ans. (d) : R1 = 528 ± 5Ω 87. Joule/Coulomb is the unit of
R2 = 325 ± 3Ω (a) Electric field potential (b) Potential
(c) Charge (d) None of the above
IES-1992
Ans. (b) : Joule per coulomb is the unit of potential.
Electric potential is defined as the amount of work done in
RT = R1 + R2 moving a unit positive charge from infinite to that point.
RT = 528 + 325 = 853Ω. W joule
δRT = ± [δR1 + δR2] V= =
q coulomb
δR1 = ± 5Ω , δR2 = ± 3Ω.
δRT = ± 8Ω
RT = 853 ± 8Ω List-I List-II
85. The current flowing through the resistor R is as (a) Resistance 1. M–1L–2T2I2
indicated in the given figure. The computed (b) Inductance 2. ML2T–3I–2
value of power is (c) Capacitance 3. M–1L–2T4I2
(d) Reluctance 4. ML2T–2I–2
Codes:
A B C D
(a) 1 2 3 4
(b) 4 2 3 1
(a) 400 ± 0.42W (b) 400 ± 4.60W (c) 2 1 3 4
(c) 400 ± 8.8W (d) 400 ± 1065W (d) 2 4 3 1
RPCS Lect. 2011 IES-1992
IES-1994 Ans. (d) : Dimension of resistance-
Ans. (c) : P = I2R , P = 4 × 100 = 400W V W
R= & V=
I Q
[ML2T −2 ]
V= = [ML2T −3I −1 ] W = [ML2T–2]
[IT]
Q = [IT]
δP  δI δR  V
% = 2× + % R = = [ML2T −3I −2 ]
P  I R  I
R = [ML2 T–3 I–2]
δP  0.02 0.2 
= 2× + % Dimension of Inductance-
P  2 100  Nφ φ
δP L= ,= L ∝
% = [ 2 × 0.01 + 0.002] % I I
P φ = [ML2 I–1 T–2]
δP
% = ± [ 0.02 + 0.002] % [ML2 I −1T −2 ]
P L=
[I]
δP 2 –2 –2
% = ±[0.022]% L = [ML I T ]
P Dimension of capacitance-
δP = 400 × 0.022 q  W
δP = ± 8.8W C=  V =  , q = [IT]
V  q 
P = 400 ± 8.8W.
2
86. The most serious source of error in ac bridge q
C= [W = F.d = ma.d]
measurement is W
(a) eddy currents (b) leakage currents a = [LT–2]
(c) residual imperfectness (d) stray fields [I 2T 2 ]
IES-1994 C = W = [M L2 T–2]
[ML2T −2 ]
Ans. (d) : The most serious source of error in AC C = [M–1 L–2 T4 I2]
bridge measurement is stray fields. Factors causing
Dimension of reluctance-
errors in AC bridge circuit-
MMF NI
(1) Stray conductance effect due to imperfect insulation Reluctance(S) = =
(2) Mutual conductance effects, due to magnetic Flux φ
coupling between various components of the bridge. Reluctance (S) = [M–1 L–2 T2 I2]

89. Which of the following does not have the same Ans. (c) :
units as the others? The symbols have their 1 1
usual meanings. c= =
L ε 0µ 0 4π× 10 × 8.854 × 10−12
−7
(a) (b) RC
R c = 3 × 108 m / s
1 c = Speed of light in m/sec
(c) LC (d) now dimension = LT–1
LC
IES-1992 So option C is correct.
Ans. (d) : Time constant of an inductive circuit 92. Consider the following statements regarding
L precision in measurements of quantity:
τ = sec. 1. Precision is the measure of the spread of
R the incident errors.
Time constant of an capacitive circuit
2. Precision is independent of the realizable
τ = RC sec. correctness of the measurement.
At resonance the angular frequency- 3. Precision is usually described in terms of
1 number of digits used in the measurement
f= Hz. by a digital instrument.
2 π LC
1
ω= Hz (a) 1, 2 and 3 (b) 1 and 2 only
LC (c) 1 and 3 only (d) 2 and 3 only
1 IES-2017
= τ = 2π LC sec.
f Ans. (a) : Precision is a measure of the reproducibility
Where 2π → constant of the measurement.
1 • It is the measure of the speed of the incident errors.
= τ = LC sec.
f • It is independent of realizable correctness of the
1 measurement.
So, the unit of is not the same as other. • It is described in terms of number of digits used in the
LC
measurement by a digital instrument.
90. The force between two charged particle is given
1
1 Q1Q 2 93. A 3 digit DMM has an accuracy specification
by, F = , where the symbols have 2
4πε 0 r 2
of ± 1 % of full scale (accuracy class 1). A
their usual meanings. The dimensions of ∈0 in reading of 100.0 mA is obtained on its 200 mA
free space in SI system are: full scale range. The worst case error in the
(a) M–1L–3T3A4 (b) M–1L–3T4A2 reading in milli ampere is
–3 4 3
(c) ML T A (d) M–1L–3T2 (a) ± 8 (b) ± 4
IES-1992 (c) ± 6 (d) ± 2
1 Q1Q2 APGENCO AE- 23.04.2017
Ans. (b) : F =
4πε0 r 2 Ans. (d) : Full scale range of 3½ digit = 200 mA.
1 QlQ2 1
ε0 = ± 1% of full scale = 200 × = ±2mA.
4π F r 2 100
So, error is ±2 mA
Dimension of ε0
Q1Q 2 Coulomb 2 94.
The voltage of a circuit is measured by a
ε0 ∝ voltmeter having an input impedance
F × r 2 Newton × m 2 comparable with the output impedance of the
Q2 circuit thereby causing error in voltage
ε0 = 2
Q = [A T] measurement. This error may be called
F×r
F = [MLT ]–2 (a) gross error
(b) random error
[(A T)2 ]
ε0 = (c) error caused by misuse of instrument
[MLT −2 ] × [L2 ] (d) error caused by loading effect
ε0 = [M–1 L–3 T4 A2] TNPSC AE-2008
91. The quantity 1/ ∈0 µ 0 is SI units has the Ans. (d) : The voltage of a circuit is measured by a
4 voltmeter having high input impedance comparable
(a) value 330 m/s (b) value 1.73 × 10
(c) dimension LT–1 (d) none of the above with output impedance of the circuit thereby causing
IES-1992 error in voltmeter, this error is called loading effect.
95. Consider the ammeter-voltmeter method of 98. An instrument to be used for measurement and
determining the value of the resistance R using control should preferably have
the circuit shown in the figure. The maximum (a) Dead zone and dead time
possible errors of the voltmeter and ammeter (b) Linear output and fast response
are known to be 1% and 2% of their readings, (c) Non-linear output
respectively. Neglecting the effects of meter (d) A highly damped response
resistances, the maximum possible percentage Nagaland PSC CTSE (Degree)-2018, Paper-I
error in the value of R determined from the Nagaland PSC CTSE (Degree)-2015, Paper-I
measurements, is: Ans. (b) : An instrument to be used for measurement
and control should preferably have linear output and
fast response.
99. The repeat accuracy of an instrument can be
judge from its
(a) Static error
(b) Linearity error
(a) 4 (b) 3 (c) Dynamic error
(d) Standard deviation of error
(c) 2 (d) 1
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I Nagaland PSC CTSE (Degree)-2015, Paper-I
Ans. (b) :Voltmeter error % V= 1% Ans. (d) : The repeat accuracy of an instrument can be
Ammeter error (%I) = 2% judge from its deviation of error. A standard deviation
V of an infinite number of data is defined as the square
R= root of the sum of the individual deviations squared,
I
Error in resistance reading =(%V)+(%I) divided by the number of readings.
= 1+2=3%
( S.D.) = σ = 1
d 2 + d 22 + ........d 2n
=
∑ d2
96. A wattmeter has a range of 1000 W with an n n
error of 1% of full scale deflection. If the true 100. If A = 629 ± 8 and B = 131 ± 3, A – B with
power to be measured using this wattmeter is range of doubt is
100 W, then the relative error would be:- (a) 498 ± 8 (b) 498 ± 4
(a) ± 1% (b) ± 5% (c) 498 ± 11 (d) 498 ± 13
(c) ± 10% (d) ± 20% RRB SSE-03.09.2015, Shift-III
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I Ans. (c) : Given, A = 629 ± 8, B = 131 ±3
Ans. (c) : A − B = 629 − 131 = 498
Error at desired value Total measurement error = ( ±8 ± 3) = ± 11
Full scale value × Error at full scale
= ( A − B ) = 498 ± 11
Desired Value
101. Errors which may be variable both in
1000 ×1%
= magnitude and nature (positive or negative) are
100 classified as _____ error.
= 10% (a) Hysteresis (b) Random
97. What temperature are Fahrenheit and Celsius (c) Interaction (d) Systematic
equal? RRB SSE 21.12.2014, (Red)
(a) – 40º (b) 574.59 Ans. (b) : Errors which may be variable both in
(c) 40 (d) –574.59 magnitude and nature (positive or negative) are
TNTRB -2017 classified as Random error.
Ans. (a) : We know that, 102. Linear meter with a 1% of full scale accuracy
should have _______ on the 1 V range.
0
C−0 0
F − 32 (a) 200 divisions (b) 100 divisions
=
100 180 (c) 500 divisions (d) 50 divisions
5 0
F − 160 RRB JE-01.09.2019, 3:00 PM – 5:00 PM
0
C= Ans. (b) : The linear meter should have 100 divisions
9
over the 1 volts range with 1% of full scale accuracy.
Given , 0
C= F=x
0
1
9x = 5x − 160 1% ×1Volt =
100
4x = −160 Accuracy is that property of the measuring instrument
x = –40 which shows the closeness between the measured value
Hence, 0 C = 0 F = −400 of a quantity and the value of the quantity.

103. To distinguish between signals having very 0.5
close values, we need an instrument with Ans. (b) : Estimated error = ± ×100
40
(a) high accuracy (b) high resolution
50
(c) high sensitivity (d) high linearity ∈= ±
BSNL (JTO)-2006 40
Ans. (b) : To distinguish between signals having very ∈= ±1.25%
close values, we need an instrument with high 109. The voltage across an impedance is measured
resolution. by a voltmeter having input impedance
104. A voltmeter must have very high internal comparable with the impedance causing an
resistance so that error in the reading. What is the error called?
(a) Accuracy is high (a) Random error (b) Gross error
(b) Resolution is high (c) Systematic error (d) Loading effect error
IES-2005
(c) Draws small amount of current
Ans. (d) : The voltage across an impedance is measured
(d) Creates high loading effect of the circuit by a voltmeter having input impedance comparable with
RRB SSE 02.09.2015, Shift-I the impedance causing an error in the reading. This error is
Ans. (c) : A voltmeter must have very high internal called as loading effect error. To reduce loading effect, a
resistance so that draws small amount of current. voltmeter with higher value of sensitivity is preferred.
105. What is the unit of measure for electrical 1 R + Rm
pressure or electromotive force? Sensitivity of voltmeter SV = = s
I FSD V
(a) amps (b) ohms
(c) volts (d) watts IFSD → Full scale Deflection Current.
Ans. (c) : Volts is the unit of measure for electrical
(ii) Basic Instruments
pressure or electromotive force. 1. Analog type wattmeter can be fabricated by
Quantity Unit using
Current Amperes (a) PMMC type moving system
Resistance Ohms (b) Attraction type moving system
Voltage/emf Volt (c) Repulsion type moving system
Power Watt (d) Dynamometer type moving system
106. The use of ________ instruments is merely UPPSC ITI Principal/Asstt. Director-09.01.2022
confined laboratories as standardizing Ans. (d) : Analog type wattmeter can be fabricated by
instruments. using dynamometer type moving system.
(a) Absolute (b) Indicating 2. Horizontally mounted moving iron instruments
(c) Recording (d) Integrating employ
RRB SSE 02.09.2015, Shift-III (a) Eddy current damping
Ans. (a) : The use of absolute instruments is merely (b) Air friction damping
confined laboratories as standardizing instrument. (c) Fluid friction damping
Absolute instruments-In these type of instruments, the (d) Electromagnetic damping
quantity being measured can only be measured by UPPSC Poly. Tech. Lect.-22.03.2022, Paper-I
observing the output indicated by the instrument. IES-2002
Ex-Ammeter, voltmeter, pressure gauge etc. Ans. (b) : Air friction damping is used for horizontally
107. Which of the following errors is repetitive in mounted moving iron instruments. Depending upon the
nature? pointer movement, the air pressure in air chamber
changes which reduces the damping produced by the
(a) Random error
pointer.
(b) Environmental error
Air friction damping is preferred where low value of
(c) Error due to observation magnetic field is used. For example- moving iron and
(d) Systematic error electrodynamometer type instruments-
OPSC Poly. Lect. (Instrumentation)-2018, Paper-II
Ans. (d) : Systematic errors are regularly repetitive in
nature. Systemic errors are not determined by chance
but are introduced by inaccuracy inherent to the system.
108. The radius of a sphere is given as 40 ± 0.5 mm.
The estimated error is :
(a) ± 3.75% (b) ± 1.25%
(c) ± 12. 5% (d) ± 12%
3. A 1-mA meter movement with an internal I = current = 10 mA
resistance of 100Ω is to be converted into a 0- K = spring constant = 0.016 N-m/rad
100 mA ammeter. The value of shunt resistance θ= deflection angle = 1000
will be Now putting values
(a) 2.41Ω (b) 2.01Ω π
N × 0.0046 × 10 × 10−3 × 65 × 25 × 10−6 = 0.016 × 100
(c) 1.41Ω (d) 1.01Ω 180
UPPSC Poly. Tech. Lect-22.03.2022, Paper-I N = 37399.27 374582
IES-2020, 2011 7. A moving coil instrument gives a full-scale
Ans. (d) : Rm (Meter resistance) = 100Ω. deflection of 5mA when the potential difference
−3 across its terminal is 50mV. Calculate the series
I 100 × 10 resistance for a full-scale reading 550 mV.
m= = = 100
Im 1 × 10−3 (a) 1Ω (b) 10Ω
R 100 (c) 1000Ω (d) 100Ω
Rsh = m = = 1.01Ω LMRC AM- 16.07.2021
m − 1 100 − 1
4. Calculate the sensitivity of a 200 µA meter Ans. (d) : We know that, R se = R m ( m − 1)
movement which is to be used as a DC V 50mV
voltmeter? Given R m = m = = 10
Im 5mA
(a) 5Ω/V (b) 200 µA/V
V 550mV
(c) 5 kΩ/V (d) 200mA/V m= = = 11
UPPSC Poly. Tech. Lect-22.03.2022, Paper-I V m 50mV
1 So, R se = 10 (11 − 1) = 100
Ans. (c) : S =
I FSD Hence, R se = 100Ω
1 8. A moving coil instrument gives a full-scale
=
200 × 10−6 deflection of 10mA when the potential
= 5kΩ / V difference across its terminal is 100 mV.
5. A 500 mA voltmeter is specified to be accurate Calculate the shunt resistance for a full-scale
with ±2%. Then, what is the limiting error deflection corresponding to 110 mA.
when instrument is used to measure 300 mA? (a) 1Ω (b) 0.1Ω
(a) 0.333% (b) 3.033% (c) 0.01Ω (d) 10Ω
(c) 3.0033% (d) 3.33% LMRC AM-, 16.07.2021
UPPSC Poly. Tech. Lect-22.03.2022, Paper-I Ans. (a) : R = R m
Ans. (d) : accuracy = ±2%

sh
( m − 1)
2 100mV
Magnitude of limiting error = 500mA× =10 mA Rm = = 10
100 10mA
Therefore, the limiting error at 300mA 110mA
m= = 11
10 mA 10mA
= × 100%
300 mA 10
So, R sh = =1
= 3.33% (11 − 1)
6. The coil of a recording ammeter is 65 mm long Hence, R sh = 1Ω
and 25 mm wide. The rated current of the coil 9. The bolometer is a,
is 10 mA. The flux density in the air gap is
2 (a) humidity-sensitive element
0.0046 Wb/m . The damping constant is 0.008
–1 (b) capacitive clement
N-m/rad-s . The moment of inertia is 0.008 kg-
(c) temperature-sensitive resistive element
m2. The spring constant is 0.016 N-m/rad. The
(d) Sound-sensitive resistive element
Coulomb friction is 0.2 ×10–6 N-m. The number
of turns on the coil to produce a deflection of
100º at rated current is approximately Ans. (c) : A bolometer is a temperature-sensitive
(a) 374582 (b) 471548 resistive element. A bolometer is a device for measuring
(c) 581548 (d) 675284 the power of incident electromagnetic radiation via the
heating of material with temperature dependent
ESE-2022
electrical resistance.
Ans. (a) : We know that at the balance condition Td = 10. Identify the 'CORRECT' statements,
Tc I. Loading effect is primarily caused by
NBIA = kθ instruments having low sensitivity.
Where N = number of turns = ? II. Relative error is the difference between
B = flux density (Wb/m2) = 0.004 (Wb/m2) the measured value and the true value.

III. Resolution is small increment is 14. Which one is not the error in moving iron
measurand that can be detected with instrument with a.c. and d.c.
certainty by the instrument. (a) Hysteresis error
IV. Moving-coil permanent magnet (b) Stray magnetic field
instruments can be used for the (c) Temperature error
measurements of AC and DC. (d) Eddy current error
(a) I and IV (b) II and IV Nagaland PSC CTSE (Diploma)-2018, Paper-I
(c) I and III (d) II and III Nagaland PSC CTSE (Degree)-2015, Paper-I
RPSC ACF & FRO 23.02.2021 Nagaland PSC CTSE (Degree)-2016, Paper-I
Ans. (c) : Sensitivity is depend upon loading effect. Ans. (d) : The eddy current error does not result in
Relative error-The relative error is defined as the ratio moving iron instrument with both dc and ac. Only
of the absolute error of the measurement to the actual hysteresis type error is serious type error in MI
measurement. instrument.
Measured Value − Real Value 15. The meter suitable for only DC measurement
Relative error =
Real Value (a) Moving iron type
Resolution- Resolution is the number of significant (b) Permanent magnet type
digits (decimal places) to which a value is being reliably (c) Electrodynamics type
measured. (d) Hot wire type
Moving coil permanent magnet instrument can be used RRB SSE 01.09.2015, Shift-III
for only measurement of d.c. RRB SSE 01.09.2015, Shift-II
11. Which of the following methods are not used to AAI-2015
produce damping torque? Ans. (b) : Permanent magnet moving coil (PMMC) is
(a) Eddy current (b) Air friction only used for dc measurements.
(c) Controlling (d) Fluid friction Material used for magnet in PMMC is AlNiCo
DMRC AM S&T-2020 (Al+Ni+CO) .
Ans. (c) : Controlling methods are not used to produce Operating field of PMMC instrument varies from 0.1
damping torque. Wb/m2 to 1Wb/m2.
In measurement three type of damping is used- Power consumption of PMMC instrument is very
Air friction damping low.
Fluid friction damping The accuracy of PMMC instrument is higher due to
Eddy current damping high torque to weight ratio of the instrument.
12. If an ammeter is used as a voltmeter, in all PMMC instrument scale is linear.
probability it will : θ∝I
(a) Indicate much higher reading
(b) give extremely low reading 16. In the case of PMMC rectifier type instruments
(c) indicate no reading at all the deflecting torque is proportional to
(d) burn out (a) Average value of alternating current
APPSC Poly. Lect. 15.03.2020 (b) R.M.S. of a.c.
(c) Peak value
Ans. (d) : If an ammeter which has minimum resistance
while using in series of circuit is used as voltmeter it (d) Instantaneous value
will burn out due to heating effect. Nagaland PSC CTSE (Degree)- 2018, Paper-I
13. Frequency compensation in a moving iron
instrument is achieved by connecting a Nagaland PSC CTSE (Degree)- 2015, Paper-I
(a) High resistance in series with the coil Ans. (a) : PMMC instruments measure average values.
(b) Low resistance in series with the coil In PMMC rectifier type instrument, the deflecting
(c) A capacitor in series with the fixed coil torque is proportional to the average value of ac current.
(d) A capacitor across the fixed coil 17. Murray, Verley and Fisher loop tests are used for
Nagaland PSC CTSE (Degree) -2016, Paper I (a) Short ckt. Fault in cables
Nagaland PSC CTSE (Degree) -2015, Paper I (b) Open ckt. Fault in cable
ISRO Scientist Engg. 2009 (c) Short ckt. And ground Fault in cables
Ans. (d) : (d) Open ckt. And ground Fault in cables
Ans. (c) : Location of fault in cable
(1) Murray loop test, (2) Verley loop test
(3) Fisher loop test
These tests use the principle of wheatstone bridge for
locating the fault.
Frequency compensation in a moving iron instrument is These tests can be employed to locate the earth fault or
achieved by connecting a capacitor across the fixed coil. short circuit fault in underground cables.
18. The effect of stray magnetic fields on the Ans. (b) : In electrostatic voltmeters the operating
actuating torque of a portable instrument is current is small. Hence this meter is suitable for high
maximum when the operating field of the voltage measurement.
instrument and the stray fields are It has very high accuracy.
(a) perpendicular (b) parallel
(c) Inclined at 60º (d) Inclined at 30º 23. If the secondary burden of a current
Nagaland PSC CTSE (Degree)-2017, Paper-I transformer is 15VA and the secondary current
is 5A, then the impedance of the connected load
will be
Ans. (b) : Stray magnetic field error will be more when (a) 0.6 ohms (b) 5 ohms
the magnitude of the external magnetic field is parallel
with the main field. (c) 6 ohms (d) 10 ohms
For minimized this error shielding the instrument IES-1994
with the help of a steel case. Ans. (a) : IS = 5A , secondary burden of current = 15
PMMC instrument have a strong magnetic field and VA
MI instrument have a weak magnetic field. 15
So, MI instrument have more stray magnetic field error VS = = 3V
5
as compared to PMMC instrument.
V = IZ
19. An AC current of 5 A and DC current of 5A
V 3
flow simultaneously through a circuit. Which Z= =
of the following statements is true? I 5
(a) An AC ammeter will read less than 10 A but Z = 0.6Ω
more than 5A 24. If the secondary winding of a current
(b) An AC ammeter will read only 5A transformer opened while the primary winding
(c) A DC ammeter will read 10A is carrying current, then
(d) A DC ammeter will read zero (a) the transformer will burn immediately
GPSC Asstt. Prof. 11.04.2017 (b) there will be weak flux density in the core
IES-1991 (c) there will be very high induced voltage in the
2 secondary winding
 5 
( 5)
2
Ans. (a) : rms value of current = +  (d) there will be a high current in the secondary
 2 TNPSC AE -2008
= 37.5 = 6.12 A IES-1999, 1994
So that, An AC current of 5A and DC current of 5A Ans. (c) : If the secondary winding of a current
flows simultaneously through a circuit. transformer opened while the primary winding is
An AC ammeter will reads less than 10A but more than carrying current, then there will be very high induced
5A. voltage in the secondary winding. Secondary side of
20. Torque/weight ratio of an instrument indicates current transformer is always kept short circuited in
(a) selectivity (b) accuracy order to avoid core saturation and high voltage
(c) sensitivity (d) fidelity induction. So that current transformer can be used to
Nagaland PSC CTSE (Degree)-2017, Paper-I measure high value of current.
Mizoram PSC AE/SDO 2012-Paper-I 25. While transporting a sensitive galvanometer
Ans. (c) : Torque/weight ratio of an instrument decides (a) the terminals are kept shorted
the sensitivity of an indicating instrument it should be (b) critical damping resistance is connected
high. across the terminals
21. Which meter has the highest accuracy? (c) the terminals are kept open circuited.
(a) PMMC (d) it does not matter as to what is connected
(b) Moving iron across the terminals.
(c) Bridge meter IES-1994
(d) Electrodynamometer Ans. (b) : A galvanometer is an electromechanical
KVS TGT (WE)- 2018 device used to detect the electric current in a circuit.
Ans. (a) : PMMC has highest accuracy. PMMC During transportation, if any emf induced due to a stray
instrument which used the permanent magnet for magnetic field or any other changes, then there must be
creating stationary magnetic field. damping resistance across the galvanometer terminal to
22. An electrostatic Voltmeter is suitable for protect the galvanometer.
measuring 26. Which one of the following force is not needed
(a) low voltage at high frequency for the satisfactory operation of any indicating
(b) high voltage (or measuring) instrument?
(c) low voltage at low frequency (a) Controlling force (b) Damping force
(d) all ac and dc voltages (c) Deflecting force (d) Gravitational force
Mizoram PSC AE/SDO 2012-Paper-I KVS TGT (WE)- 2017
Ans. (d) : For satisfactory working of indicating 30. The primary current in a current transformer
instrument following force or torque required is dedicated by
(1) Deflecting force (a) The second burden
(2) Controlling force (b) The core of transformer
(3) Damping force (c) The load current
Not required Gravitational force. (d) None of the above
27. 3 Voltmeter are connected in series having GPSC Asstt. Prof. 11.04.2017
specification V1 = 100V, 5mA, V2 = 100V, Ans. (c) : A current transformer is a device used to
250Ω/V and V3 = 10mA, 15000Ω across a 120V produce an alternating current and its secondary. The
supply, then reading of each voltmeter is primary current in a current transformer is dedicated by
(a) 40, 50, 30 (b) 20, 40, 50 the load current.
(c) 40, 40, 40 (d) 50, 30, 40 31. A moving coil galvanometer is converted into a
BARC Scientific Officer-2016 DC ammeter by connecting
Ans. (a) : (a) A low resistance across the meter
(b) A high resistance in series with the meter
(c) a pure inductance across the meter
(d) A capacitor in series with the meter
Ans. (a) : A moving coil galvanometer is converted into
100 a DC ammeter by connecting a low resistance across the
R1 = = 20 × 103 = 20,000Ω = 20kΩ
5 ×10−3 meter.
R 2 = 250 × 100 = 25000Ω = 25kΩ , R 3 = 15000 = 15KΩ 32. Resistance of an accurate ammeter is
(a) high (b) low
 120 
I =  (c) very low (d) very high
 R1 + R 2 + R 3  Mizoram PSC AE/SDO 2012-Paper-I
 120  Ans. (c) : For accurate measurement, an ammeter must
I =  = 2mA have very small resistance and very large current
 20kΩ + 25kΩ + 15kΩ  capacity. For an ideal ammeter, the resistance should be
 V1 = 2mA × 20kΩ = 40V  zero.
 V = 2mA × 25kΩ = 50V  33. The first order instrument is characterized by
 2  (a) time constant only
 V3 = 2mA × 15kΩ = 30  (b) static sensitivity and time constant
28. A moving coil iron ammeter may be (c) static sensitivity and damping co-efficient
compensated for frequency errors by (d) static sensitivity and natural frequency of
(a) Series inductance (b) Shunt resistance oscillations
(c) Series resistor (d) Shunt capacitor Mizoram PSC AE/SDO 2012-Paper-I
ISRO Scientist Engg. 2009 Ans. (b) : The first order instrument is characterized by
static sensitivity and time constant, The first order
Ans. (d) : The frequency error introduced by the
instrument experiences a time delay between its output
inductance of the instrument coil can be compensated
and time varying input.
by shunting of R by a capacitor as shown in figure.
34. Which one of the following decides the time of
response of an indicating instrument?
(a) deflecting system
(b) controlling system
(c) damping system
(d) pivot and jewel system
29. The rms value of complex waveforms are Ans. (c) : Damping system is responsible for time
measured using response of an indicating instrument. The deflecting
(a) Transistor Voltmeter torque is used for deflection. the controlling torque acts
(b) Differential voltmeter opposite to the deflecting torque.
(c) High bandwidth Voltmeter 35. In a flux meter, the controlling torque is
(d) Voltmeter containing heat sensing element (a) produced by weight attached to the moving
such as thermocouples coil
ISRO Scientist Engg.-2008 (b) produced by spring
Ans. (d) : The rms value of complex waveforms are (c) provided by cross coil mechanism
measured using voltmeter containing heat sensing (d) not provided by all
elements such as thermocouples. Mizoram PSC AE/SDO 2012-Paper-I
Ans. (d) : In a flux meter, the controlling torque is not Ans. (b) : Resistance of meter-
provided at all. The flux meter is the advance form of Rm = Vm × Sdc
ballistic galvanometer. Changing flux value is directly Rm = 200 ×1×103
proportional to the change in the deflection R m = 200kΩ
G
φ =  θ 41. Generation of an emf due to motion of a coil in
N a magnetic field
φ∝θ (a) Thermocouple
So, its scale is uniform. (b) Piezo electric transducer
36. The household analog energy meter is (c) Photo voltaic cell
(a) indicating instrument (d) Moving coil generator
(b) recording instrument TNPSC AE-2014
(c) integrating instrument Ans. (d) : Moving coil generator–If a coil of wire is
(d) none of these placed in a magnetic field and rotated, an alternating
Mizoram PSC AE/SDO 2012-Paper-I (sinusoidal) current is induced. As it rotates, sometimes it is
Ans. (c) : The energy meter are classified as integrating cutting through lots of flux, and so lots of current is induced.
type energy meter because the reading is not directly 42. A thermometer at a room temperature of 28ºC
measure. is suddenly immersed in a steaming water bath.
37. A moving iron instrument gives correct reading Calculate the time constant of the
when used at thermometer, if it takes 30 sec to show a
(a) low frequencies reading of 96.4ºC
(b) high frequencies (a) τ = 10 sec (b) τ = 15 sec
(c) only one frequency (c) τ = 5 sec (d) τ = 20 sec
(d) any frequencies up to certain value TNPSC AE-2014
Mizoram PSC AE/SDO 2012-Paper-I Ans. (a) : Given
T = 96.4ºC, T1= 28ºC, T2 = 100ºC, t = 30 sec.
Ans. (c) : Moving iron instrument gives a correct
−t
reading when used at only one frequency because the T = (T2 – T1) (1 − e τ ) + T1
change in frequency may cause an error due to change T − T1 −t
of reactance of moving coil. = (1 − e τ )
T2 − T1
38. The current in a circuit is measured using a
150:1 CT. If the ohm-meter reads 0.6A, the 96.4 − 28 = 1 − e −30 τ
circuit current is 100 − 28
(a) 250 A (b) 90 A 68.4 −30
= 1− e τ
(c) 156 A (d) 144 A 72
Mizoram PSC AE/SDO 2012-Paper-I −30
0.95 = 1 − e τ
Ans. (b) : Ip : Is = 150:1 Im = 0.6 −30
e τ = 0.05
I
IC = p × I m Taking log to both side
Is −30
loge 0.05 =
IC = 150×0.6 τ
IC = 90A 30
2.995 =
39. Which of these has a magnetic brake? τ
30
(a) thermo couple ammeter τ= = 10 sec
(b) energy meter 2.995
(c) dynamometer ammeter 43. Consider the following statements. A moving
(d) frequency meter iron instrument :
Mizoram PSC AE/SDO 2012-Paper-I (1) is an unpolarized meter
(2) has a permanent magnet
Ans. (b) : Energy meter has a rotating disc.
(3) has two iron vanes
So there are some magnetic breaks present in energy (4) has a fixed coil
meter.
Of these statements,
40. A 0-200V voltmeter has a sensitivity of 1kΩ/V. (a) 1, 2 and 4 are correct
The resistance of the voltmeter is (b) 1, 2 and 3 are correct
(a) 100kΩ (b) 200kΩ (c) 2, 3 and 4 are correct
(c) 1kΩ (d) 50kΩ (d) 1, 3 and 4 are correct
Mizoram PSC AE/SDO 2012-Paper-I TNPSC AE-2013
Ans. (d) : A moving iron instrument is an unpolarized (c) determination of flux density, magnetizing
meter and has two iron vanes. An MI instrument has a force and B-H curve and hysteresis loop of
fixed coil. A moving iron instrument is used to measure the specimen
ac as well as dc. (d) finding out iron losses in the specimen
TNPSC AE-2008
44. The input quantity to most of instrumentation
systems is generally Ans. (c) : The ballistic method is based on the
measurement using a ballistic galvanometer which
(a) Electrical (b) Mechanical measures the quantity of electricity induced in a
(c) Non-electrical (d) Thermal measuring coil. Hence by use of this method, we can
TNPSC AE-2013 measure flux density, magnetising force B-H curve and
Ans. (c) : The input quantity to most of instrumentation hysteresis loop of the specimen.
system is generally non electrically. The measuring 48. In the multimeter circuit shown in the figure
device is being used to keep track of some quantity. for AC voltage measurement, the function
45. The scale used for moving coil meter is diode D1 is to
(a) non-linear (b) linear
(c) square scale (d) log scale
TNPSC AE-2013
Ans. (b) : In moving coil instrument
Deflecting torque ( Td ) = BINA
Where, (a) provide half-wave rectification
B- Flux density (b) make the rectifier D2 perform full-wave
I- Current rectification
N- Number of turn (c) by pass reverse leakage current of D2 in the
A- Area of coil negative cycle of the input
Controlling torque ( Tc ) = Kθ (d) short-circuit over range voltages
TNPSC AE-2008
Tc ∝ θ Ans. (c) : If D1 were not there in the negative half cycle
So, the scale of moving coil instrument is linear. of the applied voltage, there would be some small
reverse current through D2. It if by pass reverse leakage
In MI instrument, current of D2 in the negative half cycle of the input.
Tc ∝ sin θ 49. The unit of static sensitivity is
Thus, scale of MI instrument is non-linear. (a) millimetre per microampere
(b) millimetre per milliampere
46. The ratio of transformation in the case of
(c) micrometre per microampere
potential transformers
(d) micrometre per milliampere
(a) increases with increase in power factor of
TNPSC AE-2008
secondary burden
(b) remains constant irrespective of the power % change in output
Ans. (a) : Static sensitivity=
factor of secondary burden % change in input
(c) decreases with increase in power factor of The static sensitivity is also expressed as the ratio of the
secondary burden magnitude of the response.
(d) none of these The sensitivity of an instrument should be high and
TNPSC AE-2008 therefore the instrument should not have a range greatly
exceeded the value of measured quantity. So as it’s
I1 units is shown as mm/ micro-ampere.
Ans. (c) : Transformation ratio = for CT
I2 50. In permanent magnet moving coil instruments,
V2 damping torque is provided by
Transformation ratio = for PT (a) air friction (b) eddy currents
V1 (c) fluid friction (d) magnets
the burden across the secondary of an instrument KVS TGT (WE)- 2014
transformer is specified as V2/I2. the ratio of Ans. (b) : In permanent magnet moving coil instruments,
transformation in case of PT decrease with increase in damping torque is provided by eddy currents.
power factor of secondary burden. 51. The dead zone in a certain pyrometer is
47. Ballistic test is used in magnetic measurements 0.125% of span. The calibration is 400ºC to
for 1000ºC. What temperature change might occur
(a) determination of B-H curve of the specimen before it is deflected?
only (a) 0.075ºC (b) 0.75ºC
(b) determination of hysteresis loop of the (c) 7.5ºC (d) 1.5ºC
specimen only TNPSC AE-2008
Ans. (b) : Span = 1000 – 400 = 600ºC 56. The largest change of input quantity for which
0.125 there is no output of the instrument is called as
Dead zone = × 600 = 0.75ºC (a) Dead time of that instrument
100
52. A toothed type tachogenerator has 60 teeth. A (b) Live zone of that instrument
magnetic pick-up is used in conjunction with it. (c) Dead zone of that instrument
If the speed of the shaft to which the toothed (d) Discrimination of that instrument
wheel is connected is 25 rps, the number of RPSC LECTURE-10.01.2016
pulses generated per second in the magnetic Ans. (c) : It is the largest change of input quantity for
pick-up is which there is no output of the instrument is called dead
(a) 3000 (b) 1500 zone of that instrument.
(c) 1800 (d) 1200
57. Torque at a ferrodynamic instruments is given
TNPSC AE-2008 by the relation
f (a) T=I1I2 cosφ (b) T=φ1φ2 cosφ
Ans. (b) : N =
H.S dc dL
f = N × (H.S) (c) T= K (d) T= K
dθ dθ
f = 25 × 60
f = 1500
Ans. (a) : The ferrodynamic type instruments are same
53. Which of the following instruments indicate the as the electrodynamics type instruments. The main
instantaneous value of the electrical quantity difference is that the ferrodynamic type instruments
being measured at the time at which it is being
consists a magnetic circuit of soft magnetic steel.
measure?
(a) Absolute instruments If Ic is r.m.s. current flowing through current coil
(b) Indicating instruments and IP is the rms current flowing through potential coil
(c) Recording instruments then torque developed is T = K Ic Ip Cosθ
(d) Integrating instruments 58. The most common method used for damping in
RRB SSE 02.09.2015, Shift-III measuring instruments is
Ans. (b) : Indicating instruments indicate the (a) Air friction damping
instantaneous value of the electrical quantity being (b) Eddy current damping
measured at the time at which it is being measure. (c) Electromagnetic braking
54. A 1mA ammeter has a resistance of 100Ω. It is (d) Fluid friction damping
to be converted to a 1A ammeter. The required Nagaland PSC CTSE (Degree) -2015, Paper I
shunt resistance will be Ans. (b) : Eddy current damping- This method if
(a) 100 Ω (b) 0.001 Ω damping is based on the principle that when a
(c) 100000 Ω (d) 0.1001 Ω conducting, non-magnetic material is moved in a
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I magnetic fields an e.m.f. is induced in it which causes
MPPSC Forest Service Exam.-2014 currents called the eddy currents. Due to these eddy
IES-1996 currents, a force exists between them and the field.
Ans. (d) : Given, Im = 1 mA, Rm = 100Ω, 59. An ohmmeter is connected across in inductor
I = 1A, Rsh = ? and the pointer indicates zero ohms. The
inductor is
Rm 100
R sh = = (a) Good (b) Open
(m − 1)  1 
 −3 − 1  (c) Short (d) None of these
 10  Nagaland PSC CTSE (Diploma)-2017, Paper-I
100 100
Rsh = = = 0.1001Ω Ans. (c) : An ohm meter is on electrical instrument that
(1000 − 1) 999 measures electrical resistance. Mega ohm meter (also a
55. Which instrument has the highest frequency trademarked device Megger) measure large values of
range with accuracy within reasonable limits? resistance. The unit of measurement for resistance is the
(a) Electrodynamometer (b) Thermocouple ohm (Ω).
(c) Moving iron (d) Rectifier type An ohmmeter is connected across an inductor and the
MPPSC Forest Service Exam.-2014 pointer indicates zero ohms. The inductor is short.
Ans. (b) : The thermocouple working principle is based 60. Resolution of an instrument is
on the seebeck effect. It is an electrical device (a) The minimum quantity it can measure
consisting of two dissimilar electrical conduction (b) The maximum quantity it can measure
forming an electrical junction. (c) The maximum nonlinearity
It has high frequency range which accuracy with in (d) Ability to distinguish polarity
reasonable limit. Nagaland PSC CTSE (Degree)-2017, Paper-I
Ans. (a) : The minimum quantity it can measure. (c) Has low (torque/weight of the moving parts)
Resolution is a ability of measuring instrument which ratio
indicate the small changes in the characteristic of the (d) Can be used on both ac and dc
measurement result. Nagaland PSC CTSE (Degree)-2017, Paper-I
61. Thermal zero-shift in an instrument refers to Ans. (b) : PMMC Advantages–
(a) Maximum variation in pen zero due to 1. Consume less power
temperature variation 2. Highest accuracy
(b) Inaccuracy in measurement due to 3. High torque to weight ratio
temperature variation 67. Rectifier moving coil instruments respond to
(c) Shift in zero adjustment due to expansion of (a) Peak value, irrespective of the nature of the
springs due to temperature variation waveform
(d) None of the above (b) Average value for all waveform
Nagaland PSC CTSE (Degree)-2017, Paper-I (c) rms value for all waveforms
Ans. (a) : Maximum variation in pen zero due to (d) rms vale, for symmetrical square waveform
temperature variation. Nagaland PSC CTSE (Degree)-2017, Paper-I
62. Sensitivity inaccuracy of a recording Ans. (b) : Rectifier moving coil instruments respond to
instrument means the average value for all waveforms but the calibration is in
(a) Degree to which the instrument is not rms value for sinusoidal waveforms.
sensitive enough to repeat the readings 68. If the resistance of an ammeter is too high, it
(b) Maximum error in sensitivity displayed by a will cause the current in the circuit to
pen (a) Increase (b) Decrease
(c) Smallest signal required to give detectable (c) Stop (d) Fluctuate
error Nagaland PSC CTSE (Diploma)-2018, Paper-I
(d) Amount of input needed to give unit pen Ans. (b) : If the resistance of the ammeter would be
deflection high the total resistance would be high this would be
Nagaland PSC CTSE (Degree)-2017, Paper-I decrease the amount of current flowing through the
circuit. Hence, in order to avoid the change of current
Ans. (a) : Sensitivity inaccuracy of a recording flowing in a circuit the resistance of an ammeter should
instrument means the degree to which the instrument is be as small as zero.
not sensitive enough to repeat the readings. 69. Damping of the ballistic galvanometer is kept
63. For a sensitive galvanometer, the type of very small
support used is (a) To make the system oscillating
(a) Suspension (b) Taut suspension (b) In order to get first deflection small
(c) Uni pivot suspension (d) None of these (c) Make the system critically damped
Nagaland PSC CTSE (Degree)-2017, Paper-I (d) In order to get first deflection large
Ans. (a) : For a sensitive galvanometer, the type of Nagaland PSC CTSE (Diploma)-2018, Paper-I
support used is suspension. Ans. (d) : Damping of the ballistic galvanometer is kept
64. A moving coil galvanometer is made into dc very small in order to get first deflection large. A
ammeter by connecting galvanometer is designed to deflect its indicating needle
(a) A low resistance across meter in a way that is proportional to total charge passage
through its moving coil.
(b) A high resistance in series with the meter
(c) A pure inductance across the meter 70. A popular method of increasing the range of an
ac instrument is use of
(d) A capacitor in series with the meter
(a) shunt
(b) multiplier
Ans. (a) : A moving coil galvanometer is made into dc (c) ac potentiometer
ammeter by connecting a low resistance across meter. (d) instrument transformer
65. Hysteresis error, in moving iron instruments RPSC Vice Principal ITI-2016
may be reduced by using Ans. (d) : Instrument are available in low ranges and in
(a) Mumetal or Permalloy (b) Stainless steel order to measure large value instrument needs to be
(c) Silver coating (d) High speed steel calibrated. So in order to increase range of an ac
Nagaland PSC CTSE (Degree)-2017, Paper-I instrument, instrument transformer is used.
Ans. (a) : Hysteresis error, in moving iron instruments 71. The basic principle of a D' Arsonval
may be reduced by using mumetal or permalloy. instrument is the same as the principle of a
66. An advantage of a PMMC instrument is that it (a) Moving iron instrument
is (b) PMMC instruments
(a) Free from friction error (c) Induction instruments
(b) Has high (torque/weight of the moving parts) (d) Moving coil instrument
ratio Nagaland PSC CTSE (Degree)- 2016, Paper-I

Ans. (b) : The rotation of the spindle is proportional to 78. A moving-coil meter has a resistance of 3Ω and
the electric current passed through the coil. gives full-scale deflection with 30 mA. What
Hence it is same as PMMC. external resistance should be added in series so
72. The prescribed permissible noise level, Leq for that it can measure voltages up to 300 V?
commercial area at night time is (a) 10 Ω (b) 9997 Ω
(a) 45 dBA (b) 65 dBA (c) 0.19 Ω (d) 0.01 Ω
(c) 50 dBA (d) 55 dBA IES-2014
RRB SSE 02.09.2015, Shift-I Ans. (b) : Given,
Ans. (d) : The prescribed permissible noise level, Leq Rm = 3 Ω, Im = 30 mA
for commercial area at night time is 55 dBA. Vm = Im Rm = 3 × 30 × 10–3 = 90 × 10–3
73. Electrostatic instrument uses the principle of Rse = Rm(m–1)
the variation of  300 
(a) Capacitance with the current = 3 – 1
 90 × 10 –3

(b) Inductance with the voltage
(c) Inductance with the current  900 × 1000 
=  – 3
(d) Capacitance with the voltage  90 
Nagaland PSC CTSE (Degree)- 2016, Paper-I Rse = 9997 Ω
Ans. (d) : Electrostatic instrument uses the principle of 79. A milliammeter can be used as
the variation of capacitance with voltage. In electro- (a) Voltmeter and ammeter
static instrument output occurs across the capacitors. (b) Wattmeter
74. Which of the following is not used for DC (c) Ohmmeter
measurements. (d) Frequency meter
(a) Moving iron voltmeter Nagaland PSC CTSE (Degree)- 2016, Paper-I
(b) Vibration galvanometer
Ans. (a) : A milliammeter can be used as voltmeter and
(c) Arsonval galvanometer
ammeter. A milliammeter is used to measure current
(d) Elastic galvanometer and voltage in mA and mV.
80. Which of the following methods are used for
Ans. (b) : The vibrational galvanometer is used to producing damping torque in analog
detecting alternating current in the frequency of natural instruments?
resonance. Hence vibrational galvanometer can not used 1. Air friction damping
to measure the DC.
2. Fluid friction damping
75. T=Ki is the torque equation of a 3. Eddy current damping
(a) PMMC instrument 4. Electromagnetic damping
(b) Rectifier instrument (a) 1, 2 and 3 only (b) 1, 2 and 4 only
(c) Moving iron instrument (c) 1, 3 and 4 only (d) 1, 2, 3 and 4
(d) D' Arsonval instrument IES-2020
Ans. (d) : Before coming to rest, pointer always
Ans. (d) : T = Ki T∝i oscillates due to inertia, about the equilibrium position.
this equation is used in D' Arsonval instruments. So to bring the pointer to rest within short time damping
system is required. The following methods are used to
76. Which of the following can not be measured on
a ballistic galvanometer? produce torque-
(a) Capacitance (b) Charge (1) Air friction damping
(c) Current (d) Inductance (2) Fluid friction damping
Nagaland PSC CTSE (Degree)- 2016, Paper-I (3) Eddy current damping.
(4) Electromagnetic damping (for galvanometer).
Ans. (a) : The ballistic galvanometer is an instrument
which is used to measure or indicate current in a closed 81. The inductance of a 25 A electro dynamic
circuit. The galvanometer also known as PMMC ammeter changes uniformly at the rate of
instrument works on the principle of permanent magnet 0.0035µH/degree. The spring constant is 10–6
moving coil. Nm/degree. The angle of deflection at full scale
77. Reproducibility measurement of an instrument will be
gives an indication of (a) 135º (b) 125º
(a) Resolution (b) Precision (c) 115º (d) 105º
IES-2019
(c) Reliability (d) Accuracy –6
Nagaland PSC CTSE (Degree)- 2016, Paper-I Ans. (b) : K = 10 N-m/degree.
I = 25 A
Ans. (c) : Reproducibility or reliability is the degree of
stability of a data when the measurement is repeated dM
= 0.0035 µH / degree
under similar condition. dθ

Kθ = I2
dM I 100 × 10−3
m= = = 100
dθ Im 1 × 10−3
I 2 dM 25 × 25 200 200
θ= × , θ= −6
× 0.0035 × 10 −6 Rsh = =
K dθ 10 100 − 1 99
180 Rsh = 2.02Ω
θ = 2.18 rad = 2.18× 1250
π 85. A voltmeter having a sensitivity of 1000Ω/V
82. A null type of instrument as compared to a reads 100V on its 150V scale when connected
deflection type of instrument across at resistor of unidentified specifications
in series with a milliammeter. When the
(a) has a higher accuracy (b) is less sensitive
milliammeter reads 5 mA, the error due to the
(c) is more rugged (d) is faster in response loading effect of the voltmeter will be nearly
IES-2019 (a) 13% (b) 18%
Ans. (a) : The accuracy of Null type instruments are (c) 23% (d) 33%
higher than that of deflection type instruments. IES-2017
Null type instruments are highly sensitive as compared Ans. (a) : Sensitivity of voltmeter (s) = 1000 Ω/V.
with deflection type instruments. VFSD = 150V.
• Deflection type of instruments are more suited for Voltmeter resistance = s ×VFSD = 1000×150 = 150 kΩ.
measurements under dynamic conditions than null type 100
of instruments whose intrinsic response is slower. Voltmeter current (Iv) = = 0.67mA
83. An electric kettle contains 1.5 kg of water at 150 × 103
15ºC. It takes 15 minutes to raise the Im = I – Iv = 5–0.67 = 4.33 mA.
temperature of water to 95ºC. If the heat loss Resistance due to loading effect
due to radiations and heating the kettle is 15 100
= = 23.09 kΩ.
kcalories and the supply voltage is 100 V, the 4.33 × 10−3
current taken will be 100
(a) 8.0A (b) 7.1A Meter resistance Rm = = 20 kΩ
(c) 6.3A (d) 5.4A 5 × 10−3
Error due to loading effect
IES-2019
20 − 23.09
Ans. (c) : Total energy produced (Q) = (Energy = × 100 = −13.4%
consumed) +[Heat loss due to radiation] 23.09
Energy consumed (H) = mS ∆t 86. A PMMC instrument if connected directly to
m = 1.5 × 103 gm, Heat loss = 15 kcal = 15×103 cal. measure alternating current, it indicates
(a) the actual value of the subject AC quantity
S=1
(b) zero reading
∆t = (95 °C – 15 °C) = 80 °C
Q = [1.5×103×1×80 + 15×103] cal. (c) 1/ 2 of the scale value where the pointer
rests
Q = [120×103 + 15×103] Cal.
Q = 135 kcal = 135×103×4.2 joule (d) 3 / 2 of the scale value where the pointer
Q = 567×103 joule rests.
IES-2017
Q = V.I.t
Ans. (b) : A PMMC instrument if connected directly to
Q 567 × 103 measure AC, It indicates zero reading. As permanent
I= = Amp.
V.t 100 × 15 × 60 magnet moving coil instrument measures the DC only.
I = 6.3 Amp. It gives only average value of the quantity being
measured.
84. A 0 – 1 mA FSD ammeter is to be used to
measure 0 – 100 mA full-scale deflection using 87. Consider the following statements in
a shunt. If the internal resistance of the meter connection with deflection type and null-type
instruments:
is 200Ω, what is the required shunt resistance?
1. Null-type instruments are more accurate
(a) 4.04Ω (b) 3.03Ω than the deflection type ones.
(c) 2.02Ω (d) 1.01Ω 2. Null-type of instrument can be highly
IES-2018 sensitive compared to a deflection type
Ans. (c) : Given that, instrument.
Im = 1 mA 3. Under dynamic conditions, null-type
I = 100 mA find Rsh = ? instruments are less preferred to deflection
type instruments.
Rm = 200Ω
4. Response is faster in null-type instruments
R as compared to deflection type
Rsh = m
m −1 instruments.
Which of the above statements are correct? Ans. (a) : Given, Vm = 150V, R = 15Ω
(a) 1, 2 and 3 (b) 1, 2 and 4 Hot wire instrument measures RMS value-
(c) 1, 2 and 4 (d) 2, 3 and 4 V 150
IES-2017 Im = m , Im = = 10 Amp.
R 15
Ans. (a) : In compare to deflection type instrument, a I 10
null type instrument attempts to maintain the deflection For PMMC Iavg = m = = 3.18 A
at zero by suitable application of an effect opposing that π π
I
generated by the measured quantity. For hot wire I rms = m
• Null type instruments are more accurate than 2
deflection type instrument. 10
I rms = =5A
• Null type instruments can be highly sensitive as 2
compared with deflection type instrument. 91. The scale of an electrodynamometer usually
• Deflection type of instruments are more suitable for reads the:
measurements under dynamic conditions than null (a) Average value of the ac
type of instruments. (b) Mean value of the ac
88. A megger is an instrument used for measuring: (c) Effective value of the ac
(a) Very high voltages (d) Squared value of the ac
(b) Very low voltages IES-2016
(c) Very high resistances Ans. (c) : Electrodynamometer type instruments are
capable of service as transfer instruments. A transfer
(d) Very low resistances instrument is one that may be calibrated with a DC
IES-2016 source and then used without modification to measure
Ans. (c) : Megger is also called as a mega ohmmeter AC. The scale of an electrodynamometer usually reads
and is a device used for the testing of insulation the effective or RMS value.
resistance of a cable. Megger works on the principle of 92. Which one of the following thermocouple pair
electromagnetic attraction. When a current carrying coil has maximum sensitivity around 2730K?
is placed under the influence of a magnetic field it (a) Nichrome-constantan
experiences a force. This force produces a torque that is (b) Copper-Nickel
used to deflect the pointer of the device which gives (c) Platinum-constantan
some reading. (d) Nickel-contantan
89. the expected voltage across a resistor is 100 V. IES-2015
However, the voltmeter reads a value of 97 V. Ans. (a) : Nichrome constantan sensitivity = 60µV / 0 K
The relative error is:
(a) 0.97 (b) 0.03 Copper nickel sensitivity = 31µV / 0 K
(c) 0.07 (d) 3.00 Platinum constantan sensitivity = +35 µV / 0 K
IES-2016 Nickel constantan sensitivity = 10µV / 0 K
Ans. (b) : Relative error ( εr ) So, nichrome constantan has highest sensitivity.
absoluteerror Vm − VT 93. In eddy current damping system, the disc
= = employed should be of
True value VT (a) Conducting and magnetic material
VT = True value of voltage (b) Conducting but non-magnetic material
Vm = Measure value (c) Magnetic but non-conducting material
Given, (d) Non-conducting and non-magnetic material
VT = 100V. IES-2015
Vm = 97V Ans. (b) : In eddy current damping system, the disc
97 − 100 −3 employed should be of conducting but non-magnetic
εr = = = −0.03 material. It is the most effective way of providing
100 100 damping. It is based on the Faraday's law and Lenz's
90. A sinusoidal voltage of amplitude 150 V has law. When a conductor or disc moves in the magnetic
been applied to a circuit having a rectifying field, it cuts the flux and emf induces in it. And the
device and prevents flow of current in one direction of this emf is so as to oppose the cause
direction and offers a resistance of 15Ω for the producing it.
flow of current in the other direction. If hot 94. True RMS voltmeter is ideal for the
wire type and PMMC type instruments are measurement of RMS value, because it employs
connected in this circuit to measure the electric (a) Feedback
current, their readings would respectively be: (b) High gain amplifier
(a) 3.18 A and 5 A (b) 7.07 A and 3.18 A (c) Two thermocouples
(c) 3.18 A and 5 mA (d) 5 A and 3.18 mA (d) Two heaters, heated by ac and dc
IES-2016 IES-2015
Ans. (c) : True RMS reading voltmeter gives a meter 98. Which one of the following materials has
indication by sensing the heating power of waveform temperature coefficient of resistance very close
which is proportional to the square of the RMS value of to zero?
voltage. The thermocouple is used to measure the (a) Manganin (b) Nichrome
heating power of the input waveform of which heater is (c) Carbon (d) Aluminium
supplied by the amplified version of the input IES-2015
waveform. One more thermocouple, called the Ans. (a) : The alloy of constantan and manganin has a
balancing thermocouple is used in the same thermal temperature coefficient of resistance of nearly zero.
environment in order to overcome the difficulty arising Manganin alloy contains copper, Nickel and manganese
out of the non linear behaviour of the thermocouple. in the fraction of 84% Cu, 4% Ni and 12% Mn. It's
temperature coefficient is about 1×10–5/°C.
99. A moving-coil instrument has a resistance of
10Ω and gives a full-scale deflection when
carrying a current of 50mA. What external
resistance should be connected so that the
instrument can be used to measure current up
True RMS Voltmeter to 50 A?
95. The principle of working of a D' Arsonval (a) 20Ω in parallel (b) 100Ω in series
Galvanometer is based upon (c) 0.010Ω in parallel (d) 18.7Ω in series
(a) Heating effect of current IES-2014
(b) Induction effect of current
Ans. (c) : Given-
(c) Magnetic effect of current
Rm = 10Ω.
(d) Electrostatic effect of current
Im = 50 mA
IES-2015
I = 50 A
Ans. (c) : When a current carrying coil is suspended in
I 50
a uniform magnetic field it experiences torque. m= = = 1000
I m 50 × 10−3
96. The different torques acting on the coil of a
moving coil instrument are R 10 10
Rsh = m = =
(a) Deflecting torque and control torque m − 1 1000 − 1 999
(b) Deflecting torque and damping torque Rsh = 0.010Ω
(c) Control torque and damping torque So, the resistance of 0.010Ω value should to connected in
(d) Deflecting torque, control torque and parallel with the meter to measure the current upto 50 Amp.
damping torque 100. The full-scale deflecting torque of a 20 A
IES-2015 moving-iron ammeter is 6 × 10–5 N-m. What is
Ans. (d) : Torques which are acting on the coil of a moving the rate of change of self-inductance with
coil or indicating type instruments are given below– respect to the deflection of the pointer of the
(a) Deflecting Torque–Torque needed to move the pointer ammeter at full scale?
over a calibrated scale is known as deflecting torque. (a) 0.5µH/rad (b) 0.2µH/rad
(b) Controlling Torque– It is used to control the (c) 1.3µH/rad (d) 0.3µH/rad
pointer to a definite value which is proportional to the IES-2014
quantity being measured. Ans. (d) : Given, I = 20A
(c) Damping Torque– is used for deflection, the Deflecting torque Td = 6×10–5 N-m
controlling torque acts opposite to the deflecting torque. dL
So before coming to rest pointer will oscillate due to =?
inertia. So to bring at rest within short time by reducing dθ
oscillations, we use damping torque. 1 dL
Deflecting torque Td = I 2
97. If an ammeter is to be used in place of a 2 dθ
voltmeter, we must connect with the ammeter a 1 2 dL
6×10 = × (20) ×
–5
(a) High resistance in parallel 2 dθ
(b) High resistance in series dL 12 × 10 −5
(c) Low resistance in parallel =
dθ 400
(d) Low resistance in series
dL
IES-2015 = 3 × 10−7 H / rad
dθ
Ans. (b) : If an ammeter is to be used in place of a
dL
voltmeter we must connect a high resistance is = 0.3 µH / rad
connected in series, with the ammeter. dθ

101. An ideal voltage source and an ideal voltmeter 104. To increase the range of a voltmeter
have internal impedances respectively (a) a low resistance in series is connected with
(a) zero, zero (b) zero, infinite the voltmeter
(c) infinite, zero (d) infinite, infinite (b) a low resistance in parallel is connected with
the voltmeter
IES-2014
(c) a high resistance in series is connected with
Ans. (b) : A voltage source is connected as series with the voltmeter
any network circuit. So to bear full load current, it's (d) a high resistance in parallel is connected with
resistance should be minimum, Ideally it should be zero. the voltmeter
A voltmeter is connected in parallel with the measuring IES-2012
circuit, so minimum current should flow with the meter
RRB SSE 21.12.2014 (Yellow)
that's why the voltmeter's resistance should be as high
as possible. Ideally it should be infinite. Ans. (c) : To increase the range of voltmeter a high
resistance is connected in series with the voltmeter.
102. Two 100 V F.S.D.PMMC type dc voltmeter That high resistance is called as multiplier.
having figure of merit of 10KΩ/V and 20 KΩ/V Multiplying factor for multiplier–
are connected in series. The series combination
V R
can be used to measure a maximum dc voltage m= = 1 + se
of Vm Rm
(a) 200 V (b) 175 V R se = (m − 1) × R m
(c) 150 V (d) 125 V
IES-2013 Rse → Multiplier resistance
Ans. (c) : For 100V, maximum resistance for first Rm → Internal resistance of meter.
voltmeter.
Given, Sensitivity = 10 kΩ/V.
R m 1 = Sensitivity × voltage
= 10×103×100 = 1×106Ω.
1 1
IFSD = = = 0.1mA 105. The following type of instrument can be used
Sensitivity 10 × 103 for measuring AC voltage of the highest
For the second voltmeter– frequency with reasonable accuracy.
Given:- Sensitivity = 20 kΩ/V. (a) Electrodynamometer
Maximum resistance R m 2 = 20×103×100 = 2×106Ω. (b) Moving-iron
(c) Thermal-thermoelectric
1 1 (d) Rectifier
IFSD = = = 0.05mA
Sensitivity 20 × 103 IES-2012
when connected in series, only 0.05 mA can flow Ans. (c) : For measuring the AC voltage of the highest
through without damaging the meters. frequency with reasonable accuracy thermal-thermo
Req = R m 1 + R m 2 electric instruments are used. The thermoelectric type
instruments or thermocouple type of instruments can be
= 1×106 + 2×106 used for measurement of both AC and DC applications.
= 3×106 = 3000×103Ω The most attractive feature of thermocouple instruments
Vmax = IR = 0.05×10–3×3000×103 is that they can be used for measurement of current and
voltages at very high frequency.
= 0.05×3000 = 150V.
106. A d' Arsonval meter 100Ω DC coil and 0-1 mA
103. The true rms responding voltmeter senses sensitivity gives full-scale reading of 10 A on
(a) the rms value divided by the average value of using an external resistance of
voltage (a) 100Ω (b) 10Ω
(b) the square of the rms value of voltage (c) 0.01Ω (d) 0.001Ω
(c) the actual rms value of voltage IES-2012
(d) the rms value divided by the peak value of
Ans. (c) : Given, Meter resistance Rm = 100Ω
voltage
Im = 1 × 10–3 A
IES-2013
IFSD = 10 A,
Ans. (b) : True rms reading voltmeter gives a meter
I
indication by sensing the heating power of waveform m = FSD
which is proportional to the square of the rms value of Im
the voltage. A thermocouple is used to measure the 10
heating power of the input waveform. The heating m= −3
= 104
power in a thermocouple is given by– 1 × 10
R
P = E 2rms / R heat Shunt resistance, Rsh = m
m −1

100 • Electromagnetic damping is used in the
= Galvanometer.
10000 − 1
• Eddy current damping method is used in PMMC
100 type of instruments.
=
9999 Damping in measuring instrument is used to damp out
Rsh = 0.01001Ω oscillations at final steady state position.
107. Moving-coil permanent magnet instruments 110. Which one of the following meters has
can be used for the measurement of maximum loading effect on the circuit under
(a) AC and DC measurement?
(b) AC only (a) 1000Ω/volt (b) 100Ω/volt
(c) DC only (c) 1M Ω/volt (d) 10 MΩ/volt
(d) half-wave rectified DC IES-2011
IES-2012, 1996 Ans. (b) : To reduce loading effect, a voltmeter with
Ans. (c) : Permanent magnet moving coil instruments higher value of sensitivity is preferred. So,
can be used for the measurement of DC only. The 1
torque reverses if the current reverses. If the instrument Loading effect ∝
is connected to AC, the pointer cannot follow the rapid Sensitivity
reversals and the deflection corresponding to mean So for lower value of sensitivity, loading effect will be
torque, which is zero. Hence these instruments cannot maximum. From given options 100Ω/volt have
be used for AC. maximum value of loading effect.
108. Consider the following statements are 111. A voltmeter with an internal resistance of 200
regarding the controlling torque: kΩ when connected across an unknown
1. It is not present in power factor meter resistance reads 250 V. The milliammeter
2. It opposes the deflecting torque internal resistance ≈ 0 connected in series with
3. It is provided by air friction or by fluid the above combination reads 10 mA. The actual
friction value of the unknown resistance is
Which of these statements are correct? (a) 25 kΩ (b) 200 kΩ
(a) 1, 2 and 3 (b) 1 and 3 only (c) 28.57 kΩ (d) 20 kΩ
(c) 2 and 3 only (d) 1 and 2 only IES-2011
IES-2011 Ans. (c) : Internal resistance of voltmeter–
Ans. (d) : Controlling torque is opposite to deflecting Rm = 200 kΩ
torque when, deflecting torque equals to controlling Unknown resistance R = ?
torque, pointer comes to final steady state position at Req. = Rm || R
equilibrium- 200 × 103 × R
TC = TD =
200 × 103 + R
• Control torque is provided by– V 250
Req. = = = 25 × 103 Ω
(i) Spring control I 10 × 10−3
(ii) Gravity control
200 × 103 R
109. Match List-I with List-II and select the correct 25×103 =
answer using the code given below the lists: 200 × 103 + R
3
List-I List-II 200×10 + R = 8R
A. Moving iron and hot 1. Air friction 7R = 200×103
wire type 200 × 103
B. Galvanometer 2. Electromagnetic R= Ω
7
C. PMMC type 3. Fluid friction
R = 28.57kΩ
D. Electrostatic type 4. Eddy current
Codes: 112. What is the voltage across the load resistance
A B C D RL in the above circuit? The value of each
(a) 1 4 2 3 resistor connected in the circuit is 10Ω.
(b) 3 4 2 1
(c) 1 2 4 3
(d) 3 1 2 4
IES-2011
Ans. (c) : • Damping method used in moving Iron and
hot wire instrument is air friction damping.
• Fluid friction damping is used in only Electrostatic
type instruments.
(a) 3.33 V (b) 33.33 V (a) 2 A (b) 3.46 A
(c) 333.33 V (d) 0 V (c) 4 A (d) 2.83 A
IES-2010 IES-2007
Ans. (b) : Ans. (b) : R = 20Ω , I = 2 + 4 sin314t
Hot wire instrument measures the RMS value of
current-
2 2
I  I 
I rms =  m  +  m  + .....
 2  2
2
R1 = R2 = RL = 10Ω  4 
I rms = 2 2 +  
as R2 & RL are in parallel-  2
10 × 10 100
Req. = = = 5Ω 16
10 + 10 20 I rms = 4 +
From voltage division rule- 2
V × R eq 100 × 5 100 I rms = 4 + 8
V2 = = = = 33.33V
R1 + R eq 15 3 I rms = 12
Voltage across load resistance RL will be same as Irms = 3.46 A
voltage across R2 VL = 33.33V 116. Which one of the following measuring devices
113. Which of the following meters cannot measure has minimum loading effect on the quantity
a.c. quantities? under measurement?
(a) Thermocouple (a) PMMC (b) CRO
(b) Hot wire (c) Hot wire (d) Electrodynamometer
(c) P.M.M.C. IES-2007
(d) Electrodynamometer Ans. (b) : Because CRO has high input impedance
IES-2009 approx 1MΩ. For ideal = ∞ . So, CRO has minimum
Ans. (c) : PMMC instrument cannot measure AC loading effect.
quantity. It measures only DC or average value. The 117. A meter having sensitivity of 2kΩ/V is used for
working principle of these instruments is the same as the measurement of voltage across a circuit
that of the D'Arsonval type of galvanometers. Spring is having an output resistance of 1kΩ and an
used for controlling torque. For AC quantity PMMC open circuit voltage of 8V. What is the reading
instrument shows zero deflection. of the meter at its 10 V scale?
114. What precaution (s) is/are required for (a) 5.72 V (b) 6.51 V
absolute measurement of current by Rayleigh (c) 7.62 V (d) 7.91 V
current balance? IES-2006
1. Precision balance of special form must be Ans. (c) : Output resistance = 1 kΩ, open circuit voltage
used for the accuracy of measurement Vo = 8V
2. The flexible leads, used for taking current Sensitivity = 2 kΩ/V , Full scale division FSD = 10 V
into the moving coil, must not exert RV = Sensitivity × FSD
appreciable torque upon the moving
RV = 2×103×10 = 20 kΩ
system.
Now by voltage division Rule–
below: 8 × 20 k
Vm = = 7.62 V.
(a) 1 only (b) 2 only (20 + 1)k
(c) Both 1 and 2 (d) Neither 1 nor 2 Vm = 7.62 Volts.
IES-2008 118. Which of the following meters does not exhibit
Ans. (c) : Precaution required for the measurement of square law response?
current by Rayleigh current balance are following- (a) Moving coil (b) Moving iron
• Precision balance of special form must be used for (c) Electrodynamometer (d) Hot wire instrument
the accuracy of measurement. IES-2006
• The flexible leads used for taking current into the Ans. (a) : Permanent magnet moving coil does not
moving coil, must not exert appreciable torque upon exhibit square law response. It has linear scale. As
the moving system. deflecting torque–
115. The current flowing in a 20Ω resistor is given TD = NBAI
by i = 2 + 4 sin 314t. This current is measured
by a hot wire ammeter. What is the measured N → Number of turns ; A → Area
value? B → Flux density, I → Current to be measured.
Td = G I Torque/weight ratio high
full scale deflection range
Hot wire instruments, moving iron and dead end should be minimum
electrodynamometer type instrument follow the square
response. As deflecting torque for moving iron type 122. A resistance thermometer has a temperature
instrument is– coefficient of resistance 10–3 per degree and its
resistance at 0ºC is 1.0Ω. At what temperature
1 I 2dL is its resistance 1.1Ω?
Td =
2 dθ (a) 10ºC (b) 100ºC
Deflecting torque for hot wire instruments– (c) 120ºC (d) –10ºC
The expansion is proportional to the heating effect of IES-2003
the current and hence to the square of the RMS value of Ans. (b) : α = 10 / °C.
–3
the current. Therefore, the meter may be calibrated to Ro = 1.0Ω. , Rt = 1.1Ω.
read the rms value of the current.
Rt = Ro (1 + α ∆t)
119. The current passing through a 10Ω resistance 1.1 = 1 {1 + 10–3 (t-0)}
is given by i = 3 + 4 2 sin 314t. This current is 1.1 = 1 + 10–3 t
measured by a PMMC meter. What is the 1.1 − 1
measured value? t=
(a) 3 A (b) 4 A 10−3
(c) 5 A (d) 4 2A 0.1
t = −3 = 100°C
IES-2005 10
Ans. (a) : PMMC measures the average value of 123.
quantity being measured.
As given–
i = 3 + 4 2 sin 314t
Iavg = 3 Amp
120. Which one of the following statements is not
correct in connection with electrodynamic
instruments?
(a) As the coils are air-cored, these instruments
are free from hysteresis and eddy current An iron cored choke of large inductance is
losses. connected to a d.c. supply as shown in the
(b) These instruments have a high torque/weight above circuit. A capacitor C is also connected
ratio and hence have a high sensitivity. across the switch. The role of C is to:
(c) These instruments can be used on both a.c. (a) Improve the power factor of the circuit
and d.c. and are very useful where accurate (b) Minimize the current drawn from supply
r.m.s. values of voltage irrespective of (c) Prevent has arcing across switching under
waveforms, are required switching conditions
(d) These are more expensive than either PMMC (d) Increase the magnetic flux in the core
or moving-iron type instruments. IES-2003
IES-2004 Ans. (c) : When an iron cored choke of large inductance
Ans. (b) : Electrodynamometer type instruments are is connected to d.c. supply, A capacitor C is also
most accurate type of instrument but the sensitivity is connected across the switch. A capacitor is connected
low in comparison with the DC instruments (PMMC). across the switch to prevent arching.
The magnetic field produced by air cored coil is
essentially small. Therefore the deflecting torque is low. 124. Consider the following statements regarding a
On the other hand an increase the number of turns of the moving coil instrument.
moving coil will gives in rise to increase the weight of 1. The sensitivity of a moving coil voltmeter is
moving part resulting a low torque to weight ratio. specified in terms of ohms per volt.
121. To increase the sensitivity of a deflecting type 2. A higher range moving coil voltmeter has
instrument higher sensitivity.
(a) Torque/weight ratio should be high 3. A higher current moving coil instrument
(b) Torque/weight ratio should be low has higher sensitivity.
(c) It should be lightly damped 4. Higher sensitivity meters give more
(d) Control torque must be reduced reliable results.
RRB SSE 02.09.2015, Shift-I Which of these statements are correct?
(a) 1, 2 and 3 (b) 1, 3 and 4
Ans. (a) : To increase the sensitivity of a deflecting
type instrument to torque/weight ratio should be high. (c) 1, 2 and 4 (d) 2, 3 and 4
The method to increase the sensitivity of deflecting type RPSC Vice Principal ITI-2016
instrument- IES-2002
Ans. (c) : Sensitivity is the ratio of the magnitude of
output signal to the magnitude of input signal applied to Moving Iron → Square law type scale as θ∝ I2
the instrument. Electrostatic type → Mainly used for high voltage
Output measurement θ∝ V 2
Sensitivity =
Input 127. Radiation pyrometers are used for the
It is the smallest value of input that the instrument can measurement of temperature in the range of
sense. (a) – 200º to 500ºC (b) 0ºC to 1200ºC
(c) 500ºC to 1200ºC (d) 1200ºC to 2500ºC
1 Rs + R m
(Sensitivity) S = = Ω/V IES-2000
I FSD V Ans. (d) : Measurement of temperature in various
Sensitivity of a moving coil voltmeter is specified in ranges can be done by the following transducers-
terms of ohms per volt. Resistance thermometer → upto 600 °C
A higher range moving coil voltmeter has higher Thermocouple → upto 1400 °C
sensitivity. Higher sensitive meter gives more reliable Thermistors → –100 °C to 300 °C
result. Pyrometer → 1200 °C to 2500 °C
125. In an electro dynamometer, a moving coil has Bimetallic strip → Room temperature (27 °C)
an area A, turn N and carries a current I Radiation pyrometers are used for the measurement of
producing a magnetic flux B. The torque on the temperature in the range of 1200 °C to 2500 °C.
moving coil is proportional to
(a) I (b) I2 128. Match List-I with List-II and select the correct
2 answer using the codes given below the lists:
(c) B.I (d) A.N.B.I2
List-I List-II
IES-2002 A. Former 1. Produces deflecting torque
Ans. (b) : Torque equation in electrodynamometer type B. Coil 2. Provides base for the coil
instrument– C. Core 3. Makes the magnetic field radial
Td = i1 i2 dM D. Spring 4. Provides controlling torque
dθ Codes:
For DC i1 = i2 = I A B C D
(a) 1 2 3 4
I 2dM
then, Td = (b) 1 2 4 3
dθ (c) 2 1 3 4
(d) 2 1 4 3
or Td α I 2
IES-1999
An electrodynamometer type voltmeter and ammeter Ans. (c) : In indicating instruments-
measures rms value of the voltage and current • Metal former is used for damping and also provides
respectively due to square law relationship, of the base for the coil.
deflection. Electrodynamometer type instruments works • Coil is a part of moving system which produces
on the principle of mutual inductance. deflecting torque.
126. Match List-I (Instrument) with List-II • Core makes the magnetic field radial.
(Property/use) and select the correct answer • Spring provides controlling torque.
129. The equivalent circuit of a resistor is shown in
List-I List-II the given figure. The resistor will be non
A. PMMC 1. Square law type scale inductive if
B. Moving iron 2. Very good high
frequency response
C. Thermocouple 3. Linear scalar over the
entire range
D. Electrostatic 4. Voltmeter type
Codes:
A B C D
(a) 4 1 2 3 (a) R = L/C (b) R = L / C
(b) 3 2 1 4 (c) L = CR (d) C = LR2
(c) 4 2 1 3 IES-1999
(d) 3 1 2 4 Ans. (b) : Equivalent circuit of resistor-
IES-2000
Ans. (d) : PMMC → Linear scale over the entire range
as θ∝ I
Thermocouple → Very good high frequency response.
1 1 Rs + R m
Admittance Y = + j ωC Sensitivity (S)= = Ω/V
R + jω L I FSD V
R − j ωL As given I = 5 mA
Y= 2 + jωC FSD
R + (ωL)2 1 1
So, Sensitivity S = =
R jωL I FSD 5 × 10−3
Y= 2 + jωC − 2
R + (ωL)2 R + (ωL)2 1000
S= = 200Ω / V
For resistor to be non inductive imaginary part should 5
be equal to zero. {Y(jω)} = 0 133. In the circuit shown in the figure, if the
ωL 2 2 L voltmeter and the ammeter are interchanged, it
ωC − 2 2
= 0, R + (ωL) = likely to result in damage to
R + (ωL) C
For resistor to be very high.
R >>>> ωL
ωL is negligible
L
R2 =
C (a) Both the instruments
L (b) The ammeter
⇒R= (c) The voltmeter
C
(d) Neither of these instruments
130. Loading effect is primarily caused by
IES-2012, 1997
instruments having:
(a) high resistance (b) high sensitivity Ans. (b) : Ammeter have very low value of internal
(c) low sensitivity (d) high range resistance, so if position of both meters are interchanged
Nagaland PSC CTSE (Degree)-2017, Paper-I and now ammeter is connected in parallel, so then
maximum current flows through the meter, so ammeter
IES-1999 will get damaged.
Ans. (c) : Loading effect is primarily caused by 134. A moving iron instrument has a resistance of
instruments having low sensitive. Sensitivity of a 10 ohms and takes 40 mA to produce full scale
voltmeter is defined as- deflection. The shunt resistance required to
1 convert this instrument for use as an ammeter
Sv = Ω/V of range 0 to 2A is:
I FSD
(a) 0.1021Ω (b) 0.2041Ω
• A sensitive instrument have a high value of (c) 0.2561Ω (d) 0.4210Ω
resistance. If a low sensitive voltmeter is used to IES-1997
measure the voltage across the low resistance, some
of the current will pass through the meter and hence, Ans. (b) : As given that,
the meter reading will be a wrong or with error. Rm = 10Ω
131. DC voltage of the order of a few mV can be Im = 40 mA = 40×10–3 A
measured using a/an I = 2A
(a) moving coil voltmeter I 2 2000
m= = =
(b) null-balancing potentiometer I m 40 × 10−3 40
(c) moving iron voltmeter m = 50
(d) electrostatic voltmeter Rm 10
IES-1998 Rsh = =
m − 1 50 − 1
Ans. (b) : DC voltage of the order of a few millivolt can 10
be measured by using null balancing potentiometer. Rsh =
Potentiometer is a instrument design to measure an 49
unknown voltage by comparing it with a known voltage Required shunt resistance to extend the range of
or standard voltage. It is also used for comparing the ammeter Rsh = 0.2041Ω
emf of two cells. 135. A special voltmeter can be devised which can
132. The sensitivity of a voltmeter using 0 to 5 mA measure the amplitude of a signal at two points
in a circuit and simultaneously measure the
meter movement is phase difference between the voltage
(a) 50 ohm/volt (b) 100 ohm/volt waveforms at these two points. Such a meter
(c) 200 ohm/volt (d) 500 ohm/volt would be a
IES-1998 (a) phase meter (b) wave form meter
Ans. (c) : Sensitivity of a voltmeter is defined as the (c) vector voltmeter (d) digital voltmeter
smallest value of input that the instrument can sense. IES-1997
Ans. (c) : The special voltmeter can be devised which 138. Match List-I with List-II and select the correct
can measure the amplitude of a signal at two points in a answer using the codes given below the lists:
circuit and simultaneously measures the phase List I List-II
difference between the voltage waveforms at these two (Type of instrument) (Item it measure)
points. Such a meter would be vector voltmeter. A. Hot wire 1 Only voltage
Vector voltmeter- instrument
It is a two- channel high frequency sampling voltmeter B. PMMC 2. Phase
which measures phase as well as the voltage of input instrument
signals of the same frequency. C. Electrostatic 3. True rms value
136. The coil of a moving coil ammeter of 100 turns instrument
is 40 mm long and 30 mm wide. The control D. Lock-in 4 dc value
torque is 240 × 10–6 Nm on full scale. If the amplifier
magnetic flux density in the air gap is 1 wb/m2, Codes:
what will be the range of the ammeter? A B C D
(a) 1 mA (b) 2 mA (a) 3 2 1 4
(c) 3 mA (d) 4 mA (b) 1 4 2 3
IES-1996 (c) 3 4 1 2
Ans. (b) : As given that - (d) 2 3 4 1
N = 100 Turns IES-1995
Tc = 240×10–6 Newton-meter Ans. (c) : (a) PMMC Instrument - It measures only
Area A = l×b = 40×10–3×30×10–3 m2 DC value or average value of supply.
= 12×10–4 m2 (b) Hot wire instrument - Hot wire instrument
measures the true RMS value.
Flux density B = 1 Wb/m2
(c) Electrostatic Instrument- Electrostatic instruments
In moving coil instrument- are used for the measurement of voltage only. Generally
deflecting torque Td = BINA it is used for measurement of high voltage.
at steady state Td = Tc (d) Lock-in amplifier-
It is a type of amplifier that can extract a signal with a
So, Tc = BINA known carrier waveform, from an extremely noisy
T environment. Basically it performs a multiplication of
I= c its input with a reference signal.
BNA
139. Which one of the following instruments is used
240 × 10−6 almost exclusively to measure radio frequency
=
1 × 100 × 12 × 10−4 currents?
IFSD = 2 mA (a) Moving-coil meter
137. It is desired to convert a 0 – 1000 µA meter (b) Rectifier-type moving coil meter
moment, with as internal resistance of 100 (c) Iron-vane meter
ohms, a 0-100 mA meter. The required value of (d) thermocouple meter
shunt resistance is about. IES-1995
(a) 1 ohm (b) 10 ohms Ans. (d) : Thermocouple instrument is used almost
(c) 99 ohms (d) 100 ohm exclusively to measure radio frequency currents.
IES-1995 Thermocouple instruments are RF (Radio frequency)
type indicating instruments. It can be used for the
Ans. (a) : As given that- measurement of AC signals upto 50 MHz frequency. It
Im = 1000 µA = 1 mA = 1×10–3 A can be used for both the AC and DC measurement. In
I = 100 mA = 100×10–3 A this instrument current produces the heat in the heater
Rm = 100Ω element and the thermocouple induces emf in the output
terminals. The emf is proportional to the temperature
I 100 × 10−3
m= = = 100 and rms value of the current.
Im 1 × 10−3 140. Consider the following statements regarding
required value of shunt resistance to extend the range of the use of electrodynamometer type indicating
ammeter - instruments:
R It is used for measuring
Rsh = m 1. direct current
m −1
100 100 2. alternating current
Rsh = = 3. direct voltage
100 − 1 99 4. alternating voltage
Rsh = 1.01 Ω Of these statements
V 500 × 10−3
(b) 3 and 4 are correct Im = = = 5 × 10−4 Amp.
(c) 1 and 3 are correct Rm 1000
(d) 1,2,3 and 4 are correct Im = 0.5mA
IES-1994 V= Im Rm = Ish Rsh
Ans. (d) : Electrodynamometer type instrument can I R
Ish = m m
measure both AC and DC value of voltage or current. R sh
These instruments have same accuracy for both dc and
5 ×10−4 ×1000
ac. Electrodynamometer type instruments has highest Ish =
accuracy in prescribed limit of frequency range. These 0.02
instruments are transfer type of instrument. 0.5
⇒
141. In the circuit of an electrostatic wattmeter 0.02
given below, the instantaneous torque is 50
proportional to ⇒ = 25 Amp.
2
Ish = 25 Amp
i2R i2R 143. A dc supply of 35V is connected across 600Ω

(a) ei + (b) ei −
2 2 resistance in series with an unknown
(c) ei + i R
2 2
(d) ei – i R resistance. The voltmeter having a resistance
of 1.2 kΩ is connected as 600Ω resistance
IES-1993
which reads 5V. Then the unknown resistance
Ans. (a) : e = instantaneous value of voltage across the should be
load (a) 50 kΩ (b) 1.7 kΩ
i = instantaneous value of load current (c) 7.2 kΩ (d) 2.4 kΩ
V, V1 and V2 = instantaneous values of potential of IES-1992
needle and two pair of quadrants respectively.
Ans. (d) :
Instantaneous torque ( Ti ) ∝ ( V − V1 ) − ( V − V2 )
2 2
e = V − V2 = voltage across load

V − V1 = ( V − V2 ) + ( V2 − V1 ) = e + iR
Now, Ti ∝ ( e + iR ) − e 2 = e 2 + 2eiR + i 2 R 2 − e 2
2
600 and 1.2 kΩ are in parallel

Ti ∝ 2eiR + i 2 R 2
600 × 1200
 i2R  So, Req = = 400Ω
Ti ∝ 2R  ei + 600 + 1200

 2  5
Now, i= A
 i2R  400
So, Ti ∝  ei +  Q 5V drop across 600Ω so drop across R =Vs–5 = 35–5
 2 
= 30V
142. A moving coil ammeter has a fixed shunt of
5
0.02 ohm resistance. If the coil resistance of the i= A will also flows through the unknown
meter is 1000 ohms, a potential difference of 400
500 mV is required across it for full scale resistance
deflection. Under this condition, the current in [Q both are in series ]
the shunt would be V 30
So, R = = × 400 = 2400 = 2.4kΩ
(a) 2.5 A (b) 25 A i 5
(c) 0.25 A (d) 0.025 A 144. Which meter has the highest accuracy in
IES-1993 prescribed limit of frequency range?
Ans. (b) : Given- (a) PMMC (b) moving iron
Rsh = 0.02Ω (c) electrodynamometer (d) rectifier
Rm = 1000Ω TSGENCO AE-2015
Ans. (d) : Rectifier type meter has the highest accuracy 148. A moving iron instrument operates on :
in prescribed limit of frequency range. (a) DC only (b) AC only
Rectifier type instrument- (c) both DC and AC (d) complex wave AC only
• Used for both AC & DC supply APPSC Poly. Lect. 15.03.2020
• Has linear scale Ans. (c) : A moving iron instrument operates on both
for DC and AC type instruments.
• It made with the help of PMMC instrument Moving iron type instrument-
• Its frequency range lies 20 Hz to 20 kHz For damping air friction damping is used.
145. When the pointer of an indicating instrument spring control is used for controlling purpose.
comes to rest in the final deflected position 149. With regard to the moving coil PMMC
(a) only controlling torque act instruments, which of the following is an
(b) only deflecting torque act incorrect statement?
(c) both controlling and deflecting torque act (a) It has low power consumption
(d) only damping torque act (b) It has no hysteresis loss
TSGENCO AE-2015 (c) It has high torque-to-weight ratio
(d) It has low sensitivity
Ans. (c) : When controlling torque is equal to the
deflecting torque, then the pointer of an indicating
instrument comes to the rest in final deflection position. Ans. (d) : PMMC is High Sensitivity Instrument.
i.e. Td = Tc 150. For a dynamometer-type instrument, the
incorrect statement from the following is :
146. Identify the instrument that does not exist (a) It is free of hysteresis error
(a) Dynamo-meter type ammeter (b) It is free of eddy current error
(b) Dynamo-meter type wattmeter (c) It has high torque-to-weight ratio
(c) Moving-iron voltmeter (d) It has low sensitivity
(d) Moving-iron wattmeter APPSC Poly. Lect. 15.03.2020
APGENCO AE- 23.04.2017 Ans. (c) : Electro Dynamo meter Instrument has low
Ans. (d) : The moving iron instruments are most Torque to weight ratio. So that, sensitivity is low.
common and can be constructed to measure current and 151. A moving-coil ammeter, is wounded with 40
voltage but cannot be used as wattmeter. For wattmeter turns and gives full-scale deflection with 5A.
the most suitable instrument is electrodynamometer. How many turns would be required on the
147. A periodic voltage waveform observed on an same bobbin to given full scale deflection with
20A?
oscilloscope across a load is shown in figure. A
(a) 2.5 (b) 10
Permanent Magnet Moving coil (PMMC)
(c) 40 (d) 160
meter connected across the same load reads
Ans. (b) : Td = nBIA
1
Td = constant → I ∝
n
I 2 n1 I 5
= ⇒ n 2 = 1 × n1 = × 40 = 10
I1 n 2 I2 20
(a) 4 V (b) 5 V
(c) 8 V (d) 10 V n 2 = 10
APGENCO AE- 23.04.2017 152. Which of the below is NOT used in a photo-
Ans. (a) : PMMC instrument reads average (dc) value conductive cell?
1 T (a) Selenium (b) Quartz
Vavg = ∫ V ( t ) dt (c) Silicon (d) Cadmium sulphide
T 0
1 20
= −3 ∫0
V ( t ) dt Ans. (b) : Photoconductive cell is a two terminal
20 ×10 semiconductor device whose terminal resistance will
1 10 very linear with the intensity of the incident light so
=  ∫ tdt + ∫ ( −5) dt + ∫ 5dt 
12 20
20  0 10 12  quartz is not used in photoconductive cell.

153. A DC voltmeter of 50V range uses a 200 µA
1   t2  
10
   − 5 [ t ]10 + 5 [ t ]12  meter movement with an internal resistance of

12 20
=
20   2  0  100Ω.The value of the multiplier resistance is :
 
(a) 224.9 kΩ (b) 249.9 kΩ
1 80
= 50 − 5 ( 2 ) + 5 ( 8 )  = = 4V (c) 200.9 kΩ (d) 159.9Ω
20  20 APPSC Poly. Lect. 15.03.2020
Ans. (b) : Vm = I m R m = 200 × 10−6 × 100 = 0.02V Ans. (c) : Electronic voltmeters requires an external
power source for its operation.
V = 50V
Electronic voltmeter-
V 50
m= = = 2500
Vm 0.02
Multiplier Resistance = R se = R m (m − 1)
R se = 100(2500 − 1)
In electronic voltmeter, the pointer is deflected by
R se = 249.9 kΩ taking the supply from the auxiliary amplifier circuit.
The output voltages of the amplifier circuit similar to
154. A voltmeter having a sensitivity of 1000 kΩ/V the voltage of the test circuit. The extra power not
reads 100V on its 150V scale when connected in passing through the deflector because of the meter gives
a circuit. The resistance of voltmeter is : the accurate reading.
(a) 100 kΩ (b) 150 kΩ The electronic voltmeter gives accurate reading because
(c) 50 kΩ (d) 250 kΩ of high input resistance.
APPSC Poly. Lect. 15.03.2020 158. The D' Arsonval meter movement can be
converted into an audio frequency ac ammeter
1 by adding to it a
Ans. (b) : Sv =
If (a) Thermocouple (b) Rectifier
Rs (c) Chopper (d) Transducer
Sv = Ω/V Where Sv is selectivity IES-1997
V
Ans. (b) : By connecting a rectifier to a D’ Arsonval
Rs = VSv = 150 × 1000 = 150 kΩ
meter movement, an alternating current measuring
155. For the voltmeter, if meter movement is from device is created. When AC is converted to pulsating
0-12 mA, then what will be its sensitivity? dc, the D’ Arsonval movement will react to the average
(a) 12 KΩ/V (b) 8.333 KΩ/V value of the pulsating dc.
(c) 83.33 Ω/V (d) 83.33 KΩ/V 159. Which of the following meters are not used on
UPRVUNL AE -19.07.2021, Shift-II D.C. circuit Mercury motor meters
(a) Commutator motor meters
1 Ω
Ans. (c) : Sensitivity = = (b) Mercury motor meters
I FSD V (c) Induction meters
1 1000 (d) Integrating and recording meters
= −3
=
12 × 10 12 RRB SSE 03.09.2015, Shift-I
= 83.33 Ω / V Ans. (c) : Induction meters are not used on dc circuit
mercury motor meters.
156. An instrument always extracts some energy
from the measured medium. Thus the 160. Swamping resistor is connected with PMMC
meter in order to:
measured quantity is always disturbed by the
(a) Obtain large deflecting torque
act of measurement, which makes a perfect
(b) Reduce the size of the meter
measurement theoretically impossible and it is
(c) Minimize the effect of stray magnetic fields
due to:
(d) Minimize the effect of temperature variation
(a) Skin-effect (b) Inductive effect
(c) Loading effect (d) Lorenz effect Nagaland PSC CTSE (Degree)- 2016, Paper-I
IES-2016 Ans. (d) :
Ans. (c) : Loading Effect:-
• The loading effect is a power supply specification
(also known as load regulation) that describes how well
the power supply can maintain its steady-state output
setting when the load changes.
• All practical sources have finite internal resistance.
157. Which of the following meters requires an
external power source for its operation?
(a) P.M.M.C meter The PMMC basic movement is not inherently
insensitive to temperature, but it may be temperature-
(b) Hot wire ammeter compensated by the swamping resistance. The
(c) Electronic voltmeter swamping resistors is made of managin (having)
(d) Electrodynamometer temperature coefficient of practically zero) and
IES-2009 combined with copper in the ratio of 20:1 to 30:1
161. The power indicated by the dynamometer type 166. In measuring volts and amperes, the
wattmeter is: connections should be made with:
(a) Average power (b) rms power (a) the voltmeter in series and ammeter in
(c) Peak power (d) Instaneous power parallel
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I (b) the voltmeter in parallel and ammeter in
Ans. (a) : The power indicated by the dynamometer series
type wattmeter is Average power. (c) both voltmeter and ammeter in series
The scale of the dynamometer type wattmeter is (d) both voltmeter and ammeter in parallel
uniform (because defecting torque is proportional to RRB SSE 03.09.2015, Shift-I
true power in both the case, i.e. D.C and A.C and the Ans. (b) : In measuring volts and amperes the
instrument is spring controlled. connection should be made with the voltmeter in
162. A current i = 10 (1+sint) amperes is passed parallel and ammeter in series.
through an ideal moving iron type ammeter. Its
reading will be
(a) zero (b) 10 A
(c) √150A (d) √2 A
Ans. (c) : Moving iron instrument will measure rms
value i(t) = 10 + 10sin t
Ammeter- Ammeter, instrument for measuring either
102 direct or alternating current in amperes. An ammeter
[i(t)]rms = 10 +
2
usually has low resistance so that it does not cause a
2
significant voltage drop in the circuit being measured.
= 150 A Voltmeter-Voltmeter, instrument for measuring either
163. For a given frequency the deflecting torque of an direct or alternating voltage. Voltmeter should have
induction ammeter is directly proportional to high resistance.
(a) current2 (b) current3 167. The pointer of an indicating instrument should
(c) current (d) current be
Punjab PSC Poly. Lect. 20.08.2017 (a) very light (b) very weighty
Mizoram PSC AE/SDO 2012-Paper-I (c) light (d) weighty
Ans. (a) : The torque depends on two factors. The first RRB SSE 03.09.2015, Shift-I
one is the strength of the fields and second one is the Ans. (a) : The pointer of an indicating instrument
value of the eddy current on the disc. should be very light.
The pointer is very light then the torque/weight ratio is
Therefore, Td ∝ ωI 2m high so that sensitivity is high.
164. The most common method used for damping in 168. In a portable instrument, the controlling
measuring instruments is torque is provided by
(a) Air friction damping (a) Spring (b) Gravity
(b) Eddy current damping (c) eddy currents (d) damping friction
(c) Electromagnetic braking RRB SSE 03.09.2015, Shift-I
(d) Fluid friction damping Ans. (a) : In a portable instruments, the controlling
Nagaland PSC CTSE (Degree)-2018, Paper-I torque is provided by spring.
Ans. (a) : The most common method used for damping The spring is made of phosphor bronze.
in measuring instrument is Air friction damping. 169. The multiplier and the meter coil in a voltmeter
Types of damping- are in
Air friction damping (a) Series (b) Parallel
Eddy current damping
(c) series-parallel (d) bi-junction mode
Fluid friction damping
165. For measuring DC value of current which
meter is preferable _____. Ans. (a) : The multiplier and the meter coil in a
voltmeter are in series.
(a) PMMC (b) MI
(c) Dynamometer (d) EMMC Multiplier resistance should be high from meter
AAI-2015 resistance.
Ans. (a) : For measuring dc value of current permanent Multiplier resistance is used to range extension in
magnetic moving coil (PMMC) meter is preferable. voltmeter.
PMMC → only DC measure Multiplier resistance is made up of manganin and
constantan.
MI→ Both DC and AC
(EMMC)dynamometer→ Both DC and AC R se = R m ( m − 1)

170. Heating effect of current is used in TD = TC (In balance condition)
(a) ammeters ∂M
(b) voltmeters kθ = I1I 2
∂θ
(c) both ammeters and voltmeters 1 ∂m
(d) wattmeters θ = I1I 2
k ∂θ
173. Which of the following is NOT used for
Ans. (c) : Heating effect of current is used in ammeters
measurement of temperature?
and voltmeters.
(a) Thermocouples (b) Thermistors
The heating effect produced by the flow of current these
instruments are classified as- (c) Pyrometers (d) All are used
Hotwire instruments- RRB SSE 21.12.2014, (Green)
The hot wire instruments is calibrated in term of Ans. (d) : Measurement of temperature-
rms value of the current. Thermocouple - upto 14000C
Hot wire instrument is made of platinum-Iridium Thermistors - –1000C to 3000C
wire. Pyrometers - 12000C to 35000C
Thermocouple instruments- 174. In order to increase the range of a voltmeter
Thermocouple instrument works on seebeck effect. (a) a low resistance is connected in parallel
∑ = a∆T + b∆T 2 (b) a low resistance is connected in series
(c) a high resistance is connected in parallel
(d) a high resistance is connected in series
Ans. (d) : In order to increase the range of a voltmeter
a high resistance connected in series.
171. A PMMC meter has an internal resistance 200 The extension of the range of voltmeter multiplier is
Ω and the current required for its full scale use, multiplier is made up manganin and constantan.
deflection is 50 µA. The meter is capable of R m = R v ( m − 1)
measuring on its own a maximum voltage of :
(a) 5 µV (b) 10 µV 175. The internal resistance of the milliammeter
(c) 5 mV (d) 10 mV must be very low for
KVS TGT (WE)- 2017 (a) high accuracy
Ans. (d) : Given, For PMMC meter has internal (b) high sensitivity
resistance (rm) = 200Ω, Im = 50µA (c) minimum effect on the current in the circuit
∵ Vm = Imrm = 200 × 50 × 10 –6 (d) maximum voltage drop across the meter
= 10000 × 10 = 10 × 10
–6 –3 RRB SSE 21.12.2014, (Yellow)
Vm= 10 mV Ans. (c) : The internal resistance of the milliammeter
must be very low for minimum effect on the current in
172. Which of these instruments has highest power
the circuit.
consumption?
(a) Dynamometer (b) Electrostatic An instrument for measuring small electric current
calibrated in milliamperes.
(c) Moving coil (d) Hot wire
RRB SSE-03.09.2015, Shift-III 176. In order to have fast, steady and accurate
responses, the meters should have
Ans. (d) : Hot wire has highest power consumption (a) Critical damping
because this instruments is based on heating effect of
current. When AC or DC is passed through the wire (b) Under damping
than it gets heated up to heating effect of current. (c) a very high damping coefficient
In dynamometer type instruments- (d) No damping
Fixed coil- The flux is produced by fixed coil this coil RRB SSE 21.12.2014, (Yellow)
is divided into two section to give a more uniform field Ans. (a) : In order to have fast, steady and accurate
near the center and to allow passes of the instrument responses, the meters should have critical damping.
spendal.
Moving coil- The moving coil is wound either as a self
stranded or on a non metallic former.
Damping- Air friction damping.
Control- Spring control basically used in
electrodynamometer type instruments.
∂m
I D = I1I 2
∂θ
Tc = kθ

177. In case of overdamping, the instrument will (a) X is more sensitive
become (b) Y is more sensitive
(a) Oscillating (b) dead (c) Both are equally sensitive
(c) fast and sensitive (d) slow and lethargic (d) It is not possible to determine the relation
RRB SSE 21.12.2014, (Yellow) between the sensitivity of the meters from the
Ans. (d) : In case of overdamping, the instrument will given data
become slow and lethargic. RRB SSE 03.09.2015 Shift-II
Damping- The damping torque should be of such a IES-1992
magnitude that the pointer quickly comes to its final Ans. (a) : Given that,
steady position, without overshooting. Meter X full scale deflection = IFSD1 = 40 mA
Meter Y full scale deflection = ISFD2 = 50 mA
We know that,
1
sensitivity =
I FSD
Since meter X full scale deflection is low therefore X is
more sensitive..
182. The extension range of ammeter and voltmeter
can be made respectively by
178. Which one of the following materials used in (a) Using multiplier and shunt
fabrication of swapping resistance of PMMC (b) Using shunt and multiplier
instruments (c) Using series capacitor and series inductor
(a) Copper (b) Aluminium (d) Reducing the spring tension of deflecting system
(c) Manganin (d) Tungsten RRB SSE 01.09.2015, Shift-II
RRB SSE 01.09.2015 Shit-I Ans. (b) : The extension range of ammeter and voltmeter
Ans. (c) : Manganin materials used in fabrication of can be made respectively by using shunt and multiplier.
swapping resistance of PMMC instruments.
R
In manganin materials the temperature coefficient is Extension range of ammeter R sh = m
0.0006. m −1
Resistance of manganin material should not vary
with respect to time.
To reduce temperature effect, a swamping resistance
is connected in series to a galvanometer. Extension range of voltmeter R se = R m ( m − 1)
179. Shunt is connected in parallel to ammeter to− V → New value
(a) Increase the sensitivity m=
(b) Increase the resistance Vm → Old value
(c) Measure heavy current 183. The most efficient from of damping employed
(d) Decrease the sensitivity in electrical instruments is
RRB JE-01.09.2019, 3:00 PM – 5:00 PM (a) Air friction (b) fluid friction
Ans. (c) : To measure heavy current, the shunt is (c) Eddy currents (d) None of these
connected in parallel with the ammeter, high current RRB SSE 01.09.2015, Shift-III
due to low resistance path passes through the shunt, Ans. (c) : Eddy current damping is the most efficient
some amount of current passes through the ammeter. form of damping.
180. Use of high permeability core in moving iron Eddy current damping is use for PMMC and
instrument helps in induction type instrument.
(a) reducing size of meter Air friction damping is used for moving iron and
(b) increasing sensitivity electro dynamometer type instruments.
(c) reducing temperature error Fluid friction damping is use for electro static
(d) reducing losses voltmeter type instrument.
RRB SSE 03.09.2015 Shift-II 184. Moving iron instruments can be used for
(a) Direct current and voltages
Ans. (b) : The core of moving iron instruments is made
up of perm-alloy to increase sensitivity. (b) Alternating current and voltages
Perm alloy = 80% (Nickel) +20% (iron) (c) Radio frequency current
Temperature errors are caused due to self heating of coil (d) Both a and b
and series resistance. RRB SSE 01.09.2015, Shift-III
181. Two meters X and Y require 40 mA and 50 mA Ans. (d) : Moving iron instrument measure both ac
for full scale deflection. Which of the following and dc quantities.
is correct? In case of ac it measure rms value.

Moving iron instrument scale is non linear or (c) Make the moving system fast
cramped. (d) Reduce the angle of deflection of the pointer
Controlling torque is provided by spring and air on the graduated scale
friction damping is used. RRB SSE 02.09.2015, Shift-I
Moving iron instrument operating field is low as Ans. (a) : Damping of deflecting type instruments is
compare to PMMC instrument.
done to reduce the oscillation of the pointer in the final
Moving iron instrument torque to weight ratio is low.
deflected position.
185. PMMC ammeter have uniform scale because In a measuring instrument, the damping torque is
(a) of eddy current damping necessary to bring the moving system to rest to indicate.
(b) they are spring controlled Steady state reflection in a reasonable short time.
(c) their deflecting torque varies directly as
current 189. Which one of the following decides the time of
(d) Both spring controlled and having deflecting response of an indicating instrument
torque varies directly as current. (a) Deflecting system
RRB SSE 01.09.2015, Shift-III (b) Controlling system
Ans. (d) : PMMC ammeter have uniform scale because (c) Damping system
both spring controlled and having deflecting torque (d) Pivot and jewel bearing
varies directly as current. RRB SSE 02.09.2015, Shift-II
Td = NBIA Ans. (c) : Damping system is the responsible for the
Td ∝ I Td → Deflecting torque time response of an indicating instrument.
Tc ∝ θ Tc→ Controlling torque Air friction damping→ moving iron and
electrodynamometer type instruments.
186. The damping force acts on the moving system Fluid friction damping → Electrostatic type
of an indicating instrument only when it is instrument
(a) Moving
Eddy current damping →PMMC and induction type
(b) Stationary
instruments.
(c) Near its full deflection
(d) Just starting to move 190. The following is not essential for the working of
RRB SSE 02.09.2015, Shift-I an indicating instrument
(a) Deflecting torque (b) Braking torque
Ans. (a) : The damping force acts on the moving
system of an indicating instrument only when it is (c) Dampling torque (d) Controlling torque
moving. RRB SSE 02.09.2015, Shift-II
The damping torque in indicating can be provided by- Ans. (b) : Essential for the working of indicating
Air friction damping is use for low magnetic field. instrument are-
Ex.- Moving iron and electrodynamometer type Deflecting torque
instruments. Controlling torque
Fluid friction damping is preferred where medium Dampling torque
value of magnetic field is used. Braking torque is not essential for the working of an
Ex.- Electrostatic instrument indicating instruments.
Eddy current damping is preferred where high/strong 191. Clamp on ammeter is used for
magnetic field is used.
(a) Low ac current (b) High ac current
Ex.- PMMC and induction type instrument
(c) Low dc current (d) High dc current
187. The hot wire ammeter:
(a) Is used only for dc circuits
(b) High precision instrument Ans. (b) : The working principle of clamp meter is the
(c) Used only for ac circuit magnetic induction principle.
(d) Reads equally well on dc and ac circuit A clamp meter is one kind test equipment and it is also
RRB SSE 02.09.2015, Shift-I known as Tong tester. This equipment is very simple to
use. The main function of this device is to measure a
Ans. (d) : Hot wires ammeters uses the heating effect of live conductor in the circuit without damage of power
current so it is all the same for both ac and dc as heat
loss. By using this equipment one can measure the high
generated is square function of current.
current without turning off the circuit while testing.
Hot wire instrument is made up of platinum-Iridium
wire. 192. Volt box basically used for
188. Damping of deflecting type instruments is done (a) Measuring voltage
to (b) Extending range of voltmeter
(a) Reduce the oscillation of the pointer in the (c) Extending voltage range of the potentiometer
final deflected position (d) Measuring power
(b) Make the moving system slow RRB SSE 02.09.2015, Shift-II
Ans. (c) : Volt box basically used for extending the (c) FET-input multimeter and an analog
voltage range of potentiometer. This volt ratio box electronic ammeter
measures the high voltage. It consists of the simple (d) FET-input multimeter and an analog
resistance potential divider which has many lapping on electronic voltmeter
the input side. ESE-2021
193. Resistances can be measured with the help of
Ans.(a) : Vacuum-tube voltmeter (VTVM) and a FET-
(a) Wattmeters
input multimeter have large scales for easy reading.
(b) Voltmeters
(c) Ammeters 198. Current was measured during a test as of 30.4
(d) ohmmeters and resistance bridges A, flowing in a resistor of 0.105 Ω. It was
RRB SSE 02.09.2015, Shift-III discovered later that the ammeter reading was
Ans. (d) : Resistances can be measured with the help of low by 1.2 percent and the marked resistance
ohmmeters and resistance bridges. was high by 0.3 percent. What is the true
power as a percentage of the power that was
194. Which of the following essential features is
possessed by an indicating instrument? originally calculated?
(a) Deflecting device (a) 118.4% (b) 109.7%
(b) Controlling device (c) 102.1% (d) 104.8%
(c) Damping device ESE-2021
(d) Deflecting, Controlling & Damping device Ans.(c) : Given
RRB SSE 02.09.2015, Shift-III I1 = 30.4 A
Ans. (d) : Essential features is an indicating instrument R = 0.105
deflecting, controlling and damping. These are essential 1.2
features in an indicating instrument. It = 30.4 + 30.4× = 30.7648 A
100
195. A voltmeter having symmetrical square wave 0.3
shape is applied to an average reading voltmeter Rt = 0.105 – 0.105× = 0.104685
with scale calibrated in terms of RMS value of a 100
sinusoidal wave has an error of: Pm = I2m R = (30.4)2×(0.105) = 97.036 W
(a) -3.9% (b) 3.9% Pt = I2t Rt = (30.7648)2 × (0.1046) = 99.08 W
(c) -11% (d) 11% P 99.08
Hence, t × 100 = ×100 = 102.1%
OPSC Poly. Lect. (Instrumentation)-2018, Paper-II Pm 97.03
Ans. (d) : When it is calibrated with sinusoidal wave
has an error of : 199. An analog voltmeter has a sensitivity of 10
than = Vo(rms) = 1.11 Vdc KΩ/volt. The galvanometer used in
constructing the instrument will produce a full
V ( rms ) − Vdc
% error = 0 × 100 scale deflection when the current passed
Vdc through it is
1.11Vdc − Vdc (a) 10 mA (b) 20 mA
% error = × 100 (c) 50 mA (d) 100 µA
Vdc
BSNL (JTO)-2006
% error = 11%
1
196. Which one of the following is essentially a Ans. (d) : Current = = 100µA
permanent magnet moving coil instrument 10 × 103
designed to be sensitive to extremely low 200. Match List-I (Instruments) with List-II
current levels? (Measurement in which the instrument is used)
(a) Multimeter and select the correct answer using the codes
(b) Galvanometer given below the lists:
(c) Electrodynamic Wattmeter List-I List- II
(d) Electrodynamic Voltmeter A. Lock-in 1. Patient monitoring
ESE-2021 amplifier
Ans.(b) : Galvanometer is essentially a permanent B. Sampling 2. Overcoming ground
magnet moving coil instrument designed to be sensitive oscilloscope loop problem
to extremely low current levels.
C. Isolation 3. Phase difference
197. Which of the following instruments have large amplifier between two signals
scales for easy reading?
(a) Vacuum-tube voltmeter (VTVM) and a FET- D. Strip-chart 4. Signal recovery form
input multimeter recorder noise
(b) Vacuum-tube voltmeter (VTVM) and an 5. Observing very high
analog electronic ammeter frequency signals

Codes:- 203. In the circuit shown in figure, the voltage
A B C D across 25 kΩ resistor is be measured by using a
(a) 1 3 5 4 voltmeter of sensitivity of 1 kΩ/V. The
(b) 2 1 3 4 magnitude of percentage error in the
(c) 4 5 2 1 measurement is
(d) 3 4 1 2
BSNL (JTO)-2006
Ans. (c) :
Lock-in amplifier Signal recovery form noise
Sampling Observing very high
oscilloscope frequency signals
(a) 10 (b) 20
Isolation amplifier Overcoming ground loop
(c) 30 (d) 40
problem
BSNL(JTO)-2009
Strip-chart recorder Patient monitoring
Ans. (d) : Resistance of voltmeter
201. A 0.1 A ammeter having a resistance of 10 Ω is Rv = Sv×V = 1×103×25 = 25kΩ
to be converted to a 1 A ammeter by using
shunt resistance. Which one of the following is
the most appropriate shunt resistance ?
(a) 0.1 Ω (b) 1.0 Ω
(c) 1.1 Ω (d) 1.2 Ω
BSNL(JTO)-2009
1 12.5
Ans. (c) : M = = 10 Vm = × 75 = 15V
0.1 62.5
R se 10 15 − 25
Rsh = = = 1.1 %error = × 100 = 40%
M − 1 10 − 1 25
202. The voltmeter in the circuit shown in the figure
is ideal. The transformer has two identical 204. In an analog PMMC 0-10 A ammeter is
windings with perfect coupling. The reading on provided with no controlling mechanisation
the voltmeter will be and the moving parts are free to rotate. What
will be the readings of the instrument if 1A
(d.c.) is passed through the moving coil?
(The torque produced is sufficient to overcome
the frictional losses)
(a) 1A
(b) 10A
(c) The pointer will continuously rotate
(d) The pointer will remain stationary
TNPSC AE-2008
Ans. (c) : In an analog PMMC, when there is no
(a) 440 V (b) 220 V
controlling mechanisation and moving parts are free to
(c) 110 V (d) zero rotate, then if we provide some current then the pointer
ISRO Scientist- May, 2017 will rotate continuously.
Ans. (d) : 205. In the circuit shown in the figure, if the
voltmeter and the ammeter are interchanged, it
likely to result in damage to
(a) both the instruments

Voltmeter reading is zero volt (b) the ammeter
Ideal voltmeter current through voltmeter = 0 (c) the voltmeter
Since the dot is on same side so stone polarity of the (d) neither of these instruments
primary and secondary voltage will be same. IES-1997
Ans. (b) : • The ammeter will get damage. 4. In a Q meter, an inductor turns to 2 MHz with
• If ammeter is connected in parallel. So it has very 450 pF and to 4 MHz with 90 pF. The value of
low resistance, current is follow only low resistive self-distributed capacitance is :
path so they act like short circuit, so chances of (a) 20 pF (b) 30 pF
ammeter get damaged. (c) 40 pF (d) 50 pF
• Now if voltmeter is connected in series then due to APPSC Poly. Lect. 15.03.2020
high resistance no current will flow through circuit Ans. (b) : f1 = 2 MHz, f2 = 4MHz
so no voltage drop occurs. Voltage in same line is C1 = 450 pF, C2 = 90 pF
zero, its indicate zero. Cd = ?
C − n 2C2
(iii) Potentiometers and Q-meters Cd = 1 2
n −1
1. The principle of operation of Q-meter is based n = 2 = 4MHz = 2
f
on f1 2MHz
(a) Self inductance (b) Mutual inductance
450 × 10−12 − ( 2 ) × 90 ×10−12
2
(c) Series resonance (d) Parallel resonance Cd =
( 2) −1
2
UPPSC Poly. Tech. Lect.-22.03.2022, Paper-I
Nagaland PSC CTSE (Degree)- 2018, Paper-I ( 450 − 360 ) × 10−12 = 90 = 30 pF
Nagaland PSC CTSE (Degree)- 2016, Paper-I Cd =
3 3
BSNL (JTO)-2009
5. The number of turns of wire needed to provide
Ans. (c) : The Q meter working Principle is based on
a potentiometer with a resolution of 0.05% is:
series resonance, the voltage drop across the coil or
(a) 200 (b) 2000
capacitor is Q times the applied voltage (where Q is the
ratio of reactance to resistance XL/R) if a fixed voltage (c) 500 (d) 5000
is applied to the circuit a voltmeter across the capacitor APPSC POLY. LECT. 14.03.2020
can be calibrated to read. UPMRC-AM-2020
X X E 100
Q= L = C = C Ans. (b) : %R =
R R E no.of turn ( N )
2. In a Q meter, distributed capacitance of coil is 100
measured by changing the capacitance of the 0.05 =
N
tuning capacitor. The values of tuning
capacitor are C1 and C2 for resonant frequency N = 2000
f1 and 2f1 respectively. The value of distributed 6. The Q factor of an inductor would be higher it
capacitance is : is made of
(a) (C1 - C2)/2 (b) (C1 - 2C2)/3 (a) thinner wire (b) longer wire
(c) (C1 - 4C2)/3 (d) (C1 - 3C2)/2 (c) shorter wire (d) thicker wire
RPSC ACF & FRO 23.02.2021 Mizoram PSC AE/SDO 2012-Paper-I
IES-1998
1 1
Ans. (c) : f1 = , f2 = X L ωL
2π L ( C1 + Cd ) 2π L ( C 2 + Cd ) Ans. (d) : Q factor of an inductor = =
R R
f1 C 2 + Cd 1
= Q f 2 = 2f1 So Q ∝
f2 C1 + Cd R
l X
 f1 
2
C 2 + Cd C 2 − 4Cd and R↓ = ρ , Q ↑= L
Cd = A↑ R↓
  =
 2f1  C1 + Cd 3 1
Therefore Q ∝ A ∝
3. The function of the Q-meter is to measure : R
(a) capacitance So, that the Q-factor of an inductor would be higher if it
(b) inductance is made of Thicker wire.
(c) quality factor of capacitor and inductor 7. A dc potentiometer is designed to measure up
(d) quality factor and form factor of capacitor and to about 2V with a slide wire of 800mm. A
inductor standard cell of emf 1.18V obtains balance at
APPSC Poly. Lect. 15.03.2020 600mm. A test cell is seen to obtain balance at
Ans. (c) : A Q-meter is a piece of equipment used in the 680mm. The emf of the test cell is
testing of radio frequency circuits. It has been largely (a) 1.00V (b) 1.34V
replaced in professional laboratories. It is used to (c) 1.5V (d) 1.7V
measure quality factor of capacitor and inductor. Mizoram PSC AE/SDO 2012-Paper-I
Ans. (b) : For potentiometer E is directly proportional 12. The Q-factor measures
to the length of wire. (a) Frequency selectivity
E1 L1 R1 (b) Energy dissipation
= = (L1 = 600mm and L2 = 680 mm) (c) Energy stored in the cavity
E 2 L2 R 2
(d) All of these
1.18 600 Nagaland PSC CTSE (Degree)-2016, Paper-II
=
E2 680 Ans. (d) : Q-factor or quality factor is used for
frequency selectivity. Q factor is the ratio of energy
E 2 = 1.34V dissipated to the energy stored in cavity or any coil.
8. The value of Q in terms of conductance G and 13. In a flux meter, the controlling torque is
susceptance B of the circuit is define as: (a) Produced by weight attached to the moving
coil
G B (b) Produced by spring
(a) (b)
B G (c) Not provide at all
G G (d) Provided by crossed–coil mechanism
(c) (d) Nagaland PSC CTSE (Degree)-2017, Paper-I
B B
Ans. (c) : In a flux meter, the controlling torque is not
UPSC JWM-2016 provided.
Ans. (b) : For a parallel resonance circuit is generally 14. The study of energy distribution across the
defined as the ratio of circulating branch currents to the frequency spectrum of a given electrical signal
supply current. is done by a
B (a) Distortion meter (b) Wave analyzer
Quality factor = 2πfCR = . (c) Spectrum analyzer (d) Q-meter
G
9. A potentiometer is basically a
Ans. (c) : The study of energy distribution across the
(a) deflectional type instrument
frequency spectrum of a given electrical signal is done
(b) null type instrument by a Spectrum analyzer.
(c) deflectional as well as null type instrument 15. Q factor is measured using
(d) a digital instrument (a) Reflect meter method
TNPSC AE-2008 (b) Transmission line method
Ans. (b) : A potentiometer is an instrument designed to (c) Power ratio method
measure an unknown voltage by comparing it with a (d) Current ratio method
known voltage. It is a null type instrument. It can Mizoram PSC Jr. Grade -2018, Paper-III
measure- Ans. (b) : There are three method Transmission
Voltage Current Resistance method, Impedance method and transient method for
10. In a Q-meter, the value of shunt resistance measuring Q of a cavity resonator. The easiest and most
connected across the oscillator is typically of followed method is transmission method.
the order of 16. Volt Ratio box (VR box) is used in conjuction
(a) Ω (b) mΩ with
(a) Voltmeters (b) Ammeters
(c) µΩ (d) kΩ
(c) Potentiometers (d) Wheatstone bridge
TNPSC AE-2008 Nagaland PSC CTSE (Degree)- 2016, Paper-I
Ans. (b) : The small resistor is used in Q-meter, the Ans. (c) : Volt ratio box is basically a device used for
order of the resistor is mΩ. Approx 0.02Ω extending the voltage range of potentiometer. The volt
11. A 100 Ω resistive potentiometer is used with an box measure the high voltage.
input supply voltage of 10V. If the thermal 17. A capacitance of 250 pF produces resonance
resistance 30ºC/W and the ambient with a coil at a frequency of (2/π) × 106 Hz,
temperature is 40ºC, the temperature of the while at the second harmonic of this frequency,
POT is resonance is produced by a capacitance of 50
(a) 60ºC (b) 80ºC pF the coil will be nearly
(c) 70ºC (d) 100ºC (a) 16.7 pF (b) 20.5 pF
TNPSC AE-2008 (c) 24.3 pF (d) 28.1 pF
IES-2019
V 2 100
Ans. (c) : P = = = 1W Ans. (a) : Given, C1 = 250pF, C2 = 50 pF
R 100 At the resonance condition-
temperature of POT = tA + tR/P 1
= 40 + 30/1 fr =
= 70ºC 2π L ( C1 + Cd )

Second harmonic frequency = 2fr 2. If the inductance to be measured is less
1 than 0.1 mH, the error due to presence of
2f r = residual inductance cannot be neglected.
2π L ( C 2 + Cd ) 3. The presence of distributed capacitance in
2 1 a coil modifies the effective Q of the coil.
= = Which of the above statements are correct?
2π L ( C1 + Cd ) 2π L ( C 2 + C d )
(a) 1, 2 and 3 (b) 1 and 2 only
4 1 (c) 2 and 3 only (d) 1 and 3 only
= =
L ( C1 + Cd ) L ( C2 + Cd ) IES-2009
C1 + Cd 1
4= Ans. (c) : We know- Qactual =
C 2 + Cd ωCR
Effect of residual or insertion resistance = 0.1R
4C2 + 4Cd = C1 + Cd
Then,
3Cd = C1 − 4C2 1 1
Qmeasured = =
C1 − 4C2  250 − ( 4 × 50 )  −12 ωC(R + 0.1R) ωCR(1 + 0.1)
Cd = =  ×10
3  3  1 1
Qmeasured = ×
( 250 − 200 ) ×10 −12 1.1 ωCR
= Hence, 1 Statement wrong.
3
The residual inductance of the instrument affects the
= 16.66 × 10 −12 = 16.67 pF measurement of only small inductors.
18. The null balance potentiometric measurement Option (c) is true because
of voltage technique is not capable of QTrue  C 
We know = 1+ d 
Q measured 
measuring
C
(a) DC voltage
(b) AC voltage 21. A coil is tuned to resonance at 500 kHz with a
(c) voltage with higher accuracy and sensitivity resonating capacitor of 36 pF. At 250 kHz, the
as compared to deflection-type instrument resonance is obtained with resonating
(d) dynamic and transient voltage changes capacitor of 160 pF. What is the self-
IES-2012 capacitance of the coil?
Ans. (d) : Potentiometer measures the unknown voltage (a) 2.66 pF (b) 5.33 pF
using null or balance conditions, hence no power is (c) 8 pF (d) 10.66 pF
required for the measurement, it can be used to measure IES-2008
both DC and AC voltages. Ans. (b) : Given that– f1 = 250 kHz, C1 = 160 pF
It is not capable of measuring dynamic and transient f2 = 500 kHz , C2 = 36 pF
voltage changes. Self capacitance of a coil-
19. A Q-meter is supplied with an oscillator having 2
a 500 mV output voltage. While testing an C = C1 − n C 2
S
unknown inductor, the voltage across the n2 −1
variable capacitor of the Q-meter, measured by If f = nf
2 1
a digital voltmeter, is obtained as 10V. The Q-
f 500
factor of the inductor is n= = 2
=2
(a) 5 (b) 10 f1 250
(c) 20 (d) 0.05
160 − (2) 2 × 36 160 − 4 × 36
IES-2012 So that, CS = =
(2)2 − 1 3
VC Voltage across capacitor
Ans. (c) : Q factor = = 16
V Supply Voltage CS = = 5.33pF
3
10 10 × 103
= = 22. How can be resolution of a wire-wound
500 × 10−3 500 potentiometer be improved?
Q-factor = 20 (a) By increasing the applied voltage
20. Consider the following statements regarding (b) By decreasing the applied voltage
sources of error in a Q-meter: (c) By reducing the diameter of the resistance
1. If a coil with resistance R is connected in wire
direct measurement mode and if the
residual resistance of Q-meter is 0.1R, then (d) By increasing the diameter of the resistance
the measured Q of the coil would be 1.1 wire
times the actual Q. IES-2005
Ans. (c) : Percent resolution (%R) of the potentiometer 26. In the given circuit, C0 is the distributed
is given as- capacitance of the coil and C is the tuning
100 capacitor. If C = C1 for the fundamental
%R = frequency and C = C2 for the second harmonic,
Number of turns then the value of C0 can be expressed a
a
The resolution of a wire-wound potentiometer is ×
improves by decreasing of the diameter of the resistance
wire. L
23. An inductor tunes at 200 kHz with 624 pF C0
capacitor and at 600 kHz with 60.4 pF C (Tuning
capacitor. The self capacitance of the inductor R capacitor)
would be-
(a) 8.05 pF (b) 10.05 pF ×
b
(c) 16.10 pF (d) 20.10 pF C1 − 2C2 C1 − 4C2
IES-2000 (a) C0 = (b) C0 =
3 3
Ans. (b) : Given, f1 = 200 kHz, C1 = 624 pF
C1 − C2
f2 = 600 kHz, C2 = 60.4 pF (c) C0 = (d) C0 = C1 − 2C2
2 3
C1 − n C2 f 600
CS = 2
n= 2 = =3 IES-1998
n −1 f 1 200 Ans. (b) : For fundamental frequency the capacitor
624 − 9 × 60.4 value is C1 then resonant frequency-
=
9 −1 1
f1 =
624 − 543.6 2π L(C1 + C0 )
= = 10.05pF
8 for second harmonics and capacitor C2
24. Measurement of an unknown voltage with a dc 1
potentiometer loses its advantage of open- ⇒ f2 = 2 f1, 2 f1 =
circuit measurement when 2π L(C 2 + C0 )
(a) the primary circuit battery is changed 1 2
(b) standardization has to be done again to
= =
2π L(C 2 + C0 ) 2π L(C1 + C0 )
compensate for drifts
(c) voltage is larger than the range of the 1 4
=
potentiometer L ( C2 + C0 ) L ( C1 + C0 )
(d) range reduction by a factor of 10 is employed
C1 + C0 = 4C2 + 4C0
IES-1999
Ans. (c) : Measurement of an unknown voltage with a C1 − 4C 2 = 3C 0
dc potentiometer loses its advantage of open-circuit C1 − 4C2
measurement when voltage is larger than the range of C0 =
the potentiometer. 3
27. Potentiometer method of dc voltage
25. A coil is tuned to response at 1 MHz with a
resonating capacitance of 72 pF. At 500 kHz, measurement is, in principle, more accurate
the resonance is obtained with a resonating than direct measurement of a voltage using
capacitance value of 360 pF. The self- voltmeter because.
capacitance of the coil is (a) it loads the circuit to the maximum extent.
(a) 12 pF (b) 24 pF (b) it loads the circuit moderately
(c) 36 pF (d) 72 pF (c) it does not load the circuit at all
IES-1999 (d) it uses zero centre galvanometer instead of a
Ans. (b) : Given, f1 = 1 MHz, C1 = 72 pF voltmeter
f2 = 500 kHz, C2 = 360 pF IES-1995
f 500kHz 1 Ans. (c) : A potentiometer is a null type instrument
n= 2 = = = 0.5 which is used to measure an unknown voltage by
f1 1000 kHz 2
comparing it with a known voltage source.
n 2 = 0.25 The leading of the unknown voltage is measured
C1 − n 2C 2 whenever the galvanometer current is equal to zero or
Cs = null hence it is called "Null detector".
n2 −1
72 − 0.25 × 360 28. The arrangement shown in the given figure
Cs = × 10−12 represents an RC potentiometer for measuring
0.25 − 1
ac voltage. What should be the value of C so
−18
Cs = = 24 pF that V0/Vin is independent of the frequency of
−0.75 the input signal?
(a) 150 (b) 100
(c) 50 (d) 200
APGENCO AE- 23.04.2017
Ans. (b) : Battery reading measured while using
potentiometer is 1.08 volts-
(a) 10µF (b) 11µF

(c) 0.10µF (d) 0.09µF
IES-1993
Ans. (a) : Voltage across 1 kΩ resistance–
By voltage divider rule-
1
Vo = Vin Vm = 0.99V
1 + 10
Vo 1 V = 1.08 − 0.99
= .....(i) V = 0.09 volts
Vin 11
Now voltage divider across C we get Vm 0.99
∴ Im = = = 9 ×10−4 Amps
1 R v 1100
Vo = Vin
C +1 V 0.09
∴ Ri = = = 100Ω
Vo 1 I m 9 ×10−4
=
Vin C + 1 31. Potentiometer can be classified as:
Q from equation (i)  (a) Deflection type instrument
1 1  Vo  (b) Null type instrument
⇒ = 1
11 C + 1  V = 11  (c) Both deflection as well as null type
 in  instrument
C = 10 µF (d) None of the above
29. With the signal generator frequency of a Q OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
meter set to 1.25 MHz, the Q of a coil is TNPSC AE-2008
measured as 98 when Capacitance C = 147 pF. Ans. (b) :A potentiometer is an instrument used for
Then the coil inductance and resistance would measuring and comparing the e.m.f. of different cells
be and for calibrating and standardizing voltmeters,
(a) 112 nH, 12 Ω (b) 982 nH, 10 Ω ammeters. etc.
(c) 110 µH, 8.8 Ω (d) 320 µH, 6.2 Ω potentiometer makes use of a balance or null condition,
TSGENCO AE-2015 no current flows and hence no power is consumed in the
circuit containing the unknown e.m.f. when the
Ans. (c) : f = 1.25 × 106 Hz, Q = 98 C = 147 pF
instrument is balanced.
1 1
Q= ⇒ 98 = 32. Which one of the following multi range
ωCR P 2π× 1.25 × 10 × 147 × 10−12 × R
6
voltmeters has high and constant input
1000000 impedance
R= (a) PMMC voltmeter
98 × 2π× 1.25 ×147
(b) Electronic voltmeter
R = 8.8Ω (c) Moving iron voltmeter
2πfL (d) Dynamometer type voltmeter
Q=
R Nagaland PSC CTSE (Degree)-2018, Paper-I
2πfL = Q × R Ans. (b) : Electronic voltmeter has high input impedance
98 × 8.8 = 2π × 1.25 × 106 L because of when it detects the signals of very weak
L = 110µH strength. Hence gives the accurate reading the high
impedance means the circuit opposes the input supply.
30. When the voltage across a battery is measured 33. Q factor of Quartz ______.
using a D.C. potentiometer, the reading shows (a) 20000 (b) 10000
1.08 V. But when the same voltage is measured (c) 30000 (d) 50000
using a Permanent Magnet Moving Coil
AAI-2015
(PMMC) voltmeter, the voltmeter reading
shows 0.99 V. If the resistance of the voltmeter Ans. (a) : Q factor of Quartz is 20000
is 1100Ω, the internal resistance of the battery, Q = 16 million f where f is the resonance frequency in
in Ω, is megahertz.

34. The resolution of potentiometer must be: Ans. (b) : De Sauty’s bridge is the simplest ac bridge
(a) Infinite (b) Very high circuit used for the measurement of unknown
(c) Zero (d) Medium capacitance. This bridge is used to compare the two
TNTRB -2017 value of capacitor as long as dielectric losses are
Ans. (a) : The resolution of potentiometer is the negligible.
smallest possible change in resistance ratio. The infinite 3. In a DC Wheatstone bridge, the current
resolution of potentiometer brings it the best advantage. through the galvanometer at balance condition
35. The sensitivity of a potentiometer can be is :
increased by (a) 1.08A (b) 0.0A
(a) Increasing the length of wire (c) 1.414A (d) 1.732A
(b) Decreasing the length of wire APPSC Poly. Lect. 15.03.2020
(c) Increasing the current in the wire Ans. (b) :
(d) Decreasing the current in the wire
KVS TGT (WE)- 2014
Ans. (a) : The sensitivity of a potentiometer can be
increased by increasing the length of wire.
 1 
potential gradient ∝  
 sensitivity  In a balanced Wheatstone bridge
 potentialdifference  R1 R 3
=
potential gradient ( K ) =  
 length of wire  R2 R4
This means that no current should pass through
(iv) Bridge Measurements galvanometer at the balance condition.
4. The dielectric loss of capacitance can be
1. A Kelvin double bridge is best suited for the measured by
measurement of (a) Hay bridge (b) Schering bridge
(a) inductance (b) capacitance (c) Maxwell bridge (d) Anderson bridge
(c) low resistance (d) high resistance OPSC Poly.Lect. (Instrumentation)-2018 Paper-I
UPPSC Poly. Tech. Lect.-22.03.2022, Paper-I Nagaland PSC CTSE (Diploma)-2018 Paper-I
APPSC Poly. Lect. 15.03.2020 GPSC Asstt. Prof. 11.04.2017
GPSC Asstt. Prof. 11.04.2017 Nagaland PSC CTSE (Degree) -2015, Paper I
Mizoram PSC AE/SDO 2012-Paper-I IES-1992, 1991
IES-2006 Ans. (b) : Schering bridge is the AC bridge used for the
Ans. (c) : A Kelvin bridge or Kelvin double bridge is measurement of unknown capacitance, dielectric loss,
a modified version of the Wheatstone bridge. A loss angle, dissipation factor and power factor.
Kelvin double bridge is best suited for the
measurement of low resistance.
Measurement of resistance
Low Medium High resistance
resistance resistance (1Ω < (R >100kΩ)
(R < 1Ω) R < 100kΩ)
Ammeter- Voltmeter - Megger
voltmeter ammeter method
method 5. Inductance of a coil having Q value in the
Kelvin double Wheatstone Direct range of (1 < Q < 10), can be measured by
bridge bridge deflection using
method (a) Hay's bridge
Potentiometer • Ohm-meter Loss of charge (b) De Sauty's bridge
• Carey foster method (c) Maxwell's bridge
bridge (d) Carry Foster's bridge
2. Which of the following bridges is NOT used for RPSC VP/SUPTD. ITI-05.11.2019
measurement of inductance? OPSC Poly. Lect. (Instrumentation)-2018 Paper-I
(a) Owen’s bridge (b) De Sauty’s bridge IES-2016
(c) Anderson’s bridge (d) Hay’s bridge Ans. (c) : Maxwell's inductance capacitance bridge
LMRC AM- 16.07.2021 used only for measure medium Q coils (1 < Q < 10).
Ans. (d) : Wheatstone bridge used for the measurement
of medium resistance.
Raleigh's method used for the absolute measurement of
• It measures an unknown inductance in terms of current.
known capacitance. Lorentz method used for the absolute measurement of
L1 = R2 R3 C4 resistance.
• Maxwell's inductance bridge measures inductance by 9. The most common method for measurement of
comparison with a variable standard. low resistance is :
R (a) Wheatstone bridge
Self inductance- L1 = 3 L 2 (b) Potentiometer method
R4 (c) Voltmeter-ammeter method
6. Hay's bridge is suitable for measuring (d) Kelvin's double bridge
inductance of which one of the following OPSC Poly. Lect. (instrumentation)-2018 Paper-I
inductors? Nagaland PSC CTSE (Degree)- 2016, Paper-I
(a) Having Q value less than 10 Ans. (d) : With the help of Kelvin's double bridge
(b) Having Q value greater than 10 method, we can measure the resistance at very low
(c) Of any value of Q value. It is most common type method to measure the
(d) Having phase angle of reactance very large low value resistance.
TSGENCO AE-2015
Mizoram PSC AE/SDO-2012 Paper-I 10. Wagner's earth a.c. bridge circuit is used to
IES-2007 eliminate the effect of
(a) stray electrostatic fields
Ans. (b) : • Hay's bridge is suitable for measuring self
(b) stray electromagnetic fields
inductance of high Q value (Q > 10).
(c) inter-component capacitances
ωL1 1 (d) parasitic capacitance to earth
• Q= =
R1 ω R 4 C 4 Nagaland PSC CTSE (degree)-2018, Paper-I
• It is the slowest bridge. UPSC JWM-2016
TNPSC AE-2013
IES-2003, 2000, 1998
Ans. (d) : Wagner's earth AC bridge circuit is used to
eliminate the effect of all the earth capacitances from
the bridge network and inner arm capacitance.
The stray element causes the error in measurement.
11. The sensitivity of a Wheatstone bridge depends
upon
7. The equations under balance condition for a (a) galvanometer current sensitivity
bridge are R1 = R2R3/R4 and L1 = R2R3C4 (b) galvanometer resistance
where R1 and L1 are unknown quantities. (c) bridge supply voltage
Which one of the following sets of parameter (d) all of the above
should be chosen as variables in order to Mizoram PSC AE/SDO 2012-Paper-I
achieve converging balance?
(a) R2 and R3 (b) R2 and C4 Ans. (d) : The sensitivity of Wheatstone bridge depends
(c) R4 and C4 (d) R3 and C4 on
RPSC Vice Principal ITI-2016 (i) Galvanometer current sensitivity
IES-2000 (ii) Galvanometer resistance
Ans. (c) : Given that, (iii) bridge supply voltage
R R 12. The resistance of a shunt for a precision grade
R1 = 2 3 ammeter can be best measured by
R4 (a) Wheatstone bridge (b) Schering bridge
L1 = R2 R3 C4 (c) Maxwell bridge (d) Kelvin double bridge
In the above equation R2 R3 is common in both equation Mizoram PSC AE/SDO 2012-Paper-I
and R1 and L1 are unknown quantity. So that R4 and C4
parameter should be chosen as variable in order to Ans. (d) : The Kelvin double bridge also known as
achieve converging balance. 'Thompson bridge' used for measuring the unknown
resistance having a value less than 1Ω by using Kelvin's
8. Which method can be used for absolute
double bridge the resistance of a shunt for a precision
measurement of resistance?
grade ammeter can also be measured.
(a) Ohm's Law method
(b) Wheatstone bridge method 13. Which bridge can be used to measure
(c) Raleigh method frequency?
(d) Lorentz method (a) Maxwell (b) Kelvin
Nagaland PSC CTSE (Degree)-2016 Paper-I (c) Schering (d) Wien
Mizoram PSC AE/SDO 2012-Paper-I Mizoram PSC AE/SDO 2012-Paper-I
Ans. (d) : Wien's bridge is used for the measurement of I 45 × 10−3
frequency which range lies between 100 Hz to 100 C= =
2 2Vrms 2 × 50 2 × 1.414 × 100 × 103 × 100
KHz. Wien's bridge also employed in harmonic
distortion analyzer, where it is used as notch filter. 45 × 10−3
= = 15.9 ×10–10 F
14 . In a Wheatstone bridge a change of 6Ω in the 2.828 × 107
unknown arm of the bridge produces a change Note:- PMMC instrument reads only average value.
in deflection produces a change in deflection of 17. Which of the following instruments can be used
3 mm of the galvanometer. The sensitivity of for measurement of very high value resistances
the instrument is such as insulation resistance in industries?
(a) 2% (b) 2 Ω/mm (a) Wheatstone bridge
(c) 0.5 mm/Ω (d) 5% (b) Megger
MPPSC Forest Service Exam.-2014 (c) Ohm-meter
Ans. (c) : Change arm resistance in wheatstone bridge (d) Resistive potentiometer
=5Ω RPSC LECTURE-10.01.2016
Deflection in galvanometer = 3 mm RRB SSE-03.09.2015,Shift-III
Mizoram PSC AE/SDO-2012 Paper-I
3
Sensitivity = = 0.5 mm/Ω Ans. (b) : Megger instruments can be used for
6
measurement of very high value resistances such as
S = 0.5 mm/Ω insulation resistance in industries. Megger is also called
15. The advantage of Hay's bridge over Maxwell's as moving coil type instrument here controlling is done
inductance-capacitance bridge is by coil and air friction damping is used.
(a) It can be used for measurement of inductance 18. Carey Foster bridge measures :
of high Q-coils (a) Very low resistances
(b) It can be used for measurement of inductance (b) Very high resistances
of low Q-coils (c) The difference between two nearly equal
(c) Its equation for balance do not contain any resistances
frequency term (d) The difference between two nearly equal
(d) None of these voltages
MPPSC Forest Service Exam.-2014 Nagaland PSC CTSE (Degree)- 2016, Paper-I
Ans. (a) : The advantage of Hay's bridge over Ans. (c) : The Carey foster bridge is a bridge circuit
Maxwell's inductance - capacitance bridge is that it can used to measure medium resistance or to measure small
be use for measurement of inductance of high Q-coils. difference between two large resistance.
16. A 100 kV, 50 Hz supply is fed to a bridge Carey Foster's bridge is a modified form of the 'meter
rectifier ammeter through a capacitor. The bridge' and works on the principle of Wheatstone
PMMC ammeter of the rectifier reads 45 mA. bridge.
The value of capacitor will be 19. Which of the following methods are used for
(a) 17.66 × 10–9 F (b) 15.9 × 10–10 F measurement of low resistance?
(c) 15.9 × 10 F–12
(d) 17.66 × 10–12 F 1. Ammeter voltmeter method
MPPSC Forest Service Exam.-2014 2. Kelvin's double bridge method
3. Maxwell's bridge method
Ans. (b) : Vrms = 100 kV
4. Potentiometer method
f = 50 Hz
(a) 1, 2 and 3 only (b) 1, 2 and 4 only
I = 45 mA
(c) 1, 3 and 4 only (d) 2, 3 and 4 only
C=?
IES-2020
Output of bridge wave rectifier output-
Ans. (b) :
2V 1
Vo = m Xc = (a) Ammeter-Voltmeter method- measured resistance,
π ωc V
V Rm = the voltage across the resistor is measured by a
Vo = I.Xc Vrms = m I
2 voltmeter an current flowing through resistor is being
2Vm I measured by an ammeter.
= Vm = 2 Vrms (b) Kelvin double bridge method- It is accurate
π ωc
method to measure the low value of resistance because
2 2Vrms I in this method the contact lead resistance of wire is
= eliminated.
π 2πfC
• It is a modification of the wheat stone bridge.
(c) Potentiometer method- It is a comparison method
and have high accuracy. This method uses a volt-ratio
box to measures the unknown resistance.
20. What are the advantages of resistance
potentiometer?
1. They are inexpensive.
2. They are useful for measurement of large
amplitudes of displacement. RS PQ
Ro = + [Taking ∆R << R]
3. Their electrical efficiency is very high and R +S P+Q
they provide sufficient output to permit Q P = Q = R = S = 1 kΩ
control operations without further ∴ Ro = R = 1 kΩ
amplification. Output voltage of bridge due to unbalance condition-
(a) 1 and 2 only (b) 1 and 3 only ∆R ∆R
(c) 2 and 3 only (d) 1, 2 and 3 Vo = V = 20 × = 5 × 10−3 ∆R
4R 4 × 1000
IES-2020
V
Ans. (d) : Resistance Potentiometer- Q Galvanometer current Ig = o
R
It is a null type instrument used to measure the
unknown resistance and it is based on comparison 5 × 10−3 ∆R
0.1×10–9 =
method. 1000
E1 l1 R1 100 ×10−9 = 5 × 10−3 ∆R
= = 100
E2 l 2 R 2 ∆R = µΩ = 20 µΩ
5
Advantage-
22. A Wheatstone bridge requires a change of 7Ω
• They are inexpensive.
in the unknown resistance arm of the bridge to
• They are simple and easy to operate. produce a change in deflection of 3 mm of the
• Its power consumption is less. galvanometer. The sensitivity and the
• They are very useful to measure the displacement of deflection factor will be nearly
large amplitude (a) 0.23 mm/Ω and 2.3Ω/mm
• Their electrical efficiency is very high and it does not (b) 0.43 mm/Ω and 2.3Ω//mm
require further amplification. (c) 0.23 mm/Ω and 1.3Ω/mm
• Potentiometer works on zero deflection method so, (d) 0.43 mm/Ω and 1.3Ω/mm
possibility of error is very small. IES-2019
21. The galvanometer used in a Wheatstone bridge Ans. (b) : Sensitivity of Wheatstone bridge-
as a detector can detect a current as low as 0.1 change in deflection in galvanometer
=
nA and its resistance is negligible compared to change in resistance in arm
internal resistance of the bridge. Each arm of
3
the bridge has a resistance of 1 kΩ. The input = mm / Ω ⇒ 0.43mm / Ω
voltage applied to the bridge is 20V. The 7
smallest change in the resistance that can be 1 1
Q Deflection factor = = = 2.3 Ω/mm
detected is sensitivity 0.43
(a) 10µΩ (b) 20µΩ 23. The Wheatstone bridge consists of a power
(c) 30µΩ (d) 40µΩ source, 3 known resistors, a resistor whose
IES-2019 value is to be measured and a null detector.
Which of the following is not a source of errors
Ans. (b) : in a Wheatstone bridge?
(a) Limiting errors of the known resistors
(b) Poor sensitivity of the null detector
(c) Fluctuations in the power supply voltage
(d) Thermal e.m.f.s in the bridge circuit.
IES-2018
Ans. (c) : A Wheatstone bridge circuit has two input
The smallest change in the resistance = ∆R
terminals and two output terminals. Consisting of four
Thevenin equivalent circuit between a and b keeping
resistors configured arrangement like a diamond in the
galvanometer circuit open circuit.
balanced condition.
Thevenin equivalent resistance of bridge
R1 R 2 Ans. (d) : Wheatstone bridge used for the measure
= medium resistance. At balance condition the diagonal
R4 R3
resistance multiplication are equal.
PS = RQ
The value of resistance does not depends on the supply
voltage in Wheatstone bridge so, the value of resistance
is 10.0 kΩ
Sources of error in Wheatstone bridge are-

• Error in the values of the known resistance
• Insufficient null detector sensitivity, which may lead
to error in detecting the balance point
• Thermoelectric emf in the bridge and the
galvanometer circuit 27. The Wheatstone bridge method of measuring
• The error committed by the operator in detecting the resistance is ideally suited for the measurement
exact balance of resistance values in the range of
24. Maxwell's bridge measures an unknown
(a) 0.001 to 1Ω (b) 0.1 to 100Ω
inductance in terms of:
(a) Known inductance (b) Known capacitance (c) 100Ω to 10 kΩ (d) 100 kΩ to 10 MΩ
(c) Known resistance (d) Q of the coil IES-2009
IES-2016 Ans. (c) : Wheatstone bridge method of measuring
Ans. (b) : Maxwell's inductance capacitance bridge is resistance is suitable for the measurement of medium
used only medium Q coils (1 < Q < 10).
resistance (1Ω < R < 105 Ω).
This bridge uses for variable capacitance.
L1 = R2 R3 C4 • It is not suitable for the measurement of low
25. The values of capacitance and inductance used resistance as lead resistance effect is not eliminated.
in the series LCR circuit are 160 pF and 160 28. Which of the following bridges is also used in
µH with the inherent tolerance ±10% in each. an oscillator?
Then, the resonance frequency of the circuit is
in the range of: (a) Maxwell (b) Schering
(a) 0.8 MHz to 1.2 MHz (c) Hay (d) Wien
(b) 0.9 MHz to 1.0 MHz IES-2009
(c) 0.8 MHz to 1.0 MHz
Ans. (d) : • Wien's bridge is also used in an oscillator.
(d) 0.9 MHz to 1.2 MHz
IES-2016 • Wien's bridge is suitable for the measurement of
Ans. (b) : Given C = 160pF, L = 160µH frequency but not suitable for the measurement of those
Resonance frequency- signals which having harmonics because bridge balance
1 is difficult.
f=
2π LC • Wien's bridge also used in distortion analyzer.
1 • Measurement of frequency from (100 Hz to 100 kHz)
So that f = = 0.994MHz
2π 160 × 10 × 160 × 10−12
−6
Now by taking tolerance = ± 10 %

10
For f max = 0.994 + 0.994 × = 1.09 MHz
100
10
f max = 0.994 − 0.994 × = 0.9 MHz
100
26. The value of a resistance as measured by a
Wheatstone bridge is 10.0kΩ using a voltage
source of 10.0 V. The same resistance is
measured by the same bridge using 15.0 V.
The value of resistance is 29. The figure shows 'Owen bridge' arranged to
(a) 15.0 kΩ (b) 15.5 kΩ measure incremental inductance of the
(c) 16.6 kΩ (d) 10.0 kΩ unknown inductance Lx, Rx. At balance, what
IES-2010 are the values of Lx and Rx ?
(b) Wien bridge is used for the measurement of
frequency and unknown value of capacitance also
can be calculated.
(c) Kelvin's Double bridge is use to measure very low
resistance because it eliminate lead/contact
resistance.
(d) Schering bridge is used for the measurement of
capacitance and it is also useful for the
measurement of relative permittivity, dissipation
RaRc R C factor and power factor.
(a) L x = ,Rx = a b
Cb Cc 31. The bridged-T network circuit shown below
(b) Lx = RaRcCb, Rx = RxCbCc can be used for determination of inductance
and Q of R.F. coils. Lx and Rx are unknown
R R R C
(c) L x = a c , R x = a c parameter of the coil. Using equations for
Cb Cb balance, what are the values of Lx and Rx?
R aCb
(d) L x = R a R cC b , R x =
Cc
IES-2007, 2003
Ans. (d) : Impedance of Owen bridge–
1
Z1 =
jωCb
1
Z2 = R c +
jωCc
Z3 = Ra 2 1
Z4 = Rx + jωLx (a) L x = ,Rx =
ω2 C R(ωC) 2
at balance condition
Z1 Z4 = Z2 Z3 1 1
(b) L x = 2 , R x =
ωC R(ωC) 2
 1   1 
⇒   ( R x + jωL x ) =  R c +  Ra 1 1
 jω C b   jω Cc  (c) L x = 2 , R x = 2
ωC ω CR
⇒ Rx Cc + jωLx Cc = jωCc Rc Ra Cb + Ra Cb
2 2
Having comparison of real and imaginary terms- (d) L x = 2 , R x =
ωC R ( ωC )
2
Cb
R x = Ra and L x = R a R cC b IES-2006
Cc
Ans. (a) :
30. Match List-I (Bridge) with List-II (Quantity)
and select the correct answer using the code
given below the lists:
List-I List-II
A. Wheatstone bridge 1. Capacitance
B. Wien bridge 2. Very low
resistance
C. Kelvin double bridge 3. Resistance
D. Schering bridge 4. Frequency
Codes:
A B C D In balance condition galvanometer measure the zero
(a) 3 4 2 1 current-
(b) 2 1 3 4 At node V1
(c) 3 1 2 4 Vin − V1 V1 V
(d) 2 4 3 1 = + 1 ( where s = jω)
1/ sC R 1/ sC
IES-2007 Vin 1 1 1 
Ans. (a) : = V1  + + 
1/ sC  R 1/ sC 1/ sC 
(a) Wheatstone bridge is used for the measurement of
medium resistance and it is used in industry due to V1 = sCVin × R = sRCVin
high accuracy. 1 + 2sRC 1 + 2sRC

Q Balanced condition
ICD = 0 and VCD = 0
Vin 0 − V1
=
R x + sL x 1/ sC
ω2 RC 2
1
=
R x + jωL x 1 + 2 jωRC
(Q s 2
= −ω2 and s = jω)
1 + 2 jωRC = ω2 RC 2 R x + jω3 RC 2 L x
Comparison of real and imaginary terms-
1 1 (a) C = L4/R2R3, R1 = R2R3/R4
Rx = 2 2 = − (b) C = L4/R3R4, R1 = R4/R2R3
ω RC R ( ωC )
2
(c) C = L4R2/R3, R1 = R3/R2R4

And 2ωRC = ω2 RC 2 L x (d) C = L4R3/R2,R1 = R3/R2R4
2 IES-2003
Lx = Ans. (a) : In Maxwell bridge at balanced condition-
ω2 C
32. Consider the following statements: Z1Z4 = Z2 Z3
The major problem in most of the a.c. bridges
is control of electric fields in order to minimize R1
the capacitance effects between bridge jωC R1
Z1 = =
components and from them to ground. The
R1 +
1 R 1 jω C +1
effects due to this electric field can be jωC
minimized by
Z2 = R2, Z3 = R3, Z4 = jωL4 + R4
1. separating various components of the
bridge as widely as practicable  jωL 4 + R 4 
2. controlling capacitance so as to enclose
R1   = R 2R 3
 jωCR1 + 1 
bridge components in conducting shields,
connected to place the capacitance where it R1 jωL4 + R1 R4 = R2R3R1 jωC + R2R3
does not harm Having comparison of real and imaginary terms-
3. using wagner earthing device R R
R1 R4 = R2 R3 , R1 = 2 3
4. using high grade insulation and mounting R4
the apparatus on insulating stands R1L4 = R2R3R1 C
correct? L4
C=
(a) 1, 2 and 3 (b) 2 and 3 R 2R 3
(c) 1 and 3 (d) 1, 2 and 4 34. In the bridge circuit shown below, at balance
IES-2004 condition, the value of Cs = 0.5µF and Rs =
Ans. (c) : The major problems in the ac bridges are to 1000Ω.
control the electric field in order to minimize the
capacitance effects between bridge components and
form them to ground.
The effects due to this electric field can be minimize by
using-
(1) Wagner's Earthing device -
• The Wagner earthing device is used for removing
the earth capacitance from the bridges.
The value of inductance Lx and resistance Rx
• At high frequency, stray capacitance is induced are
between the bridge elements ground and between
the arms of the bridge. (a) Lx = 0.5 Rx = 1000Ω
• This stray element causes the error in the (b) Lx = 0.25, Rx = 2000Ω
measurement (c) Lx = 0.5, Rx = 3000Ω
• The Wagner earth device provides high accuracy to (d) Lx = 0.25, Rx = 500Ω
the bridge. IES-2003
(3) separating various components of the bridge as Ans. (a) : The given bridge is Maxwell's inductance
widely as possible.
capacitance bridge.
33. In Maxwell bridge as shown above, the value of Given data-
C and its shunting resistance R1 are unknown.
The bridge balance relations are Z1/Z3 = Z2/Z4. R 2 = 1000Ω, R s = 1000Ω
The values of C1 and R1 are R 3 = 1000Ω,Cs = 0.5µF

Rx and Lx = unknown quantity (vii) Unchanged if the source and the detector are
interchanged
R 2R 3 (viii) Changed if the impedance of one set of adjacent
As we know R x = and L x = R 2 R sCs
Rs arms are interchanged.
1000 × 1000 37. The reading of high impedance voltmeter V in
Rx = = 1000Ω the bridge circuit shown in the given figure is
1000
Lx = 1000×1000×0.5×10–6
L x = 0.5 H
35. Match List-I (Measuring bridge) with List-II
(Application) and select the correct answer
(a) zero (b) 3.33 V
List-I List-II
(c) 4.20 V (d) 6.66 V
A. Kelvin Double Bridge 1. Capacitance
IES-2001
B. Wien Bridge 2. Self inductance
C. Schering Bridge 3. Frequency Ans. (b) :
D. Maxwell's Bridge 4. Low resistance
Codes:
A B C D
(a) 4 2 1 3
(b) 1 3 4 2 having apply voltage division rule at point Vx -
(c) 4 3 1 2
20 20
(d) 1 2 4 3 Vx = 10 × = 10 ×
IES-2002 20 + 10 30
Vx = 6.66
Ans. (c) : • Kelvin's double bridge is used to measure Similarly–
very low resistance because it eliminate lead/contact
resistance. 10
Vy = 10× = 3.33
• Wein bridge is used for the measurement of frequency 30
and it can also measures capacitance. Vxy = Vx – Vy = 6.66 – 3.33
• Schering bridge is used for the measurement of Vxy = 3.33
capacitance. It also measures relative permittivity, 38. Consider the following statements regarding
dissipation factor and power factor. the advantage of Anderson bridge
• Maxwell's bridge is used for the measurement of self 1. It is the modification of the Maxwell's
inductance and can it also measures medium Q-coil. inductance-capacitance bridge
36. Consider the following statements in 2. For measuring the low Q of coils, it is
connection with the null or balance condition in superior to the Maxwell's bridge
a bridge circuit? 3. It is simple compared to Maxwell's bridge
1. It is always independent of the magnitude 4. It can be used to determine mutual
of the source voltage or its impedance. inductance also.
2. It is independent of the sensitivity of the While of these statements are correct?
detector or its impedance. (a) 1, 2 and 3 (b) 1, 2 and 4
3. It is unchanged if the impedance of one set (c) 2 and 4 (d) 1, 3 and 4
of adjacent arms are interchanged IES-2001
4. It is unchanged if the source and the Ans. (b) : Advantage of Anderson's bridge–
detector are interchanged. (i) It is the modification of Maxwell's inductance
Which of these statements are correct? capacitance bridge.
(a) 1, 2 and 3 (b) 1, 2 and 4 (ii) In this method, the self inductance is measured in
(c) 2, 3 and 4 (d) 1, 2, 3 and 4 terms of standard capacitor.
RPSC Vice Principal ITI-2016 (iii) A fixed capacitor can be used instead a variable
IES-2002 capacitor.
Ans. (b) : At balanced condition, a bridge circuit are - (iv) It can measure the self inductance of very low Q
(i) Z2Z3 = Z4Z1 coils (Q < 1)
(ii) Independent to the magnitude of source voltage. (v) This bridge is more complex comparision to
(iii) Independent of impedance. Maxwell's bridge.
(iv) ∠θ2 + ∠θ3 = ∠θ4 + ∠θ1 39. Match List-I (Bridges) with List-II (Quantities)
(v) Independent of the sensitivity of the detector. and select the correct answer using the codes
(vi) The reading to detector is zero. given below the lists:
List-I List-II (R4–ω2C3R1C1R3R4) – jω(C1R3R2 – R4 R3C3 – R1 R4C1)
A. Maxwell's bridge 1. Frequency =0
B. Wein bridge 2. Inductance with By comparing imaginary and real part –
value of Q < 10
R4 – ω2R1C3C1R3R4 = 0, C1R3R2 = R1R4C1 + R4R3C3
C. Hay's bridge 3. Capacitance
1
D. Schering bridge 4. Inductance with ω2 =
value of Q > 10. R 1C1R 3C3
Codes: if R1 = R3 = R and C1 = C3 = C
A B C D then CRR2 = RCR4 + R4RC
(a) 2 1 4 3 CRR2 = RC(2R4)
(b) 4 3 2 1
R2
(c) 4 1 2 3 =2
(d) 2 3 4 1 R4
IES-2001 41. At the balance condition of the a.c. bridge
Ans. (a) : Maxwell's bridge – Inductance with value of shown in the figure below, the value of Z4
Q < 10 would be
Wien bridge – Frequency
Hay's bridge – Inductance with value of Q > 10
Schering bridge – capacitance
40. The Wein bridge circuit shown in the figure
below can be used as a frequency measuring
device, provided
(a) 120∠70ºΩ (b) 187.5∠–10ºΩ

(c) 187.5∠–70ºΩ (d) 333.3∠–70ºΩ
IES-2000
Ans. (c) : Given that -
Z1 = 200∠30°Ω
Z2 = 250∠–40°Ω
(a) R2/R4 = 2 (b) R4/R2 = 2 Z3 = 150∠0°Ω
(c) R2/R4 = 4 (d) R2/R4 = 3 Z4 = ?
IES-2000 At balance condition -
Ans. (a) : Z1Z4 = Z2Z3
1 Z Z 250∠ − 40°× 150∠0°
Z1 = R1 + Z4 = 2 3 =
jωC1 Z1 200∠30°
Z2 = R2 Z4 = 187.5∠ − 70°Ω
1
Z3 = R3 || 42. Wien bridge is usually used for measuring
jωC3
Z4 = R4 (a) resistance (b) capacitance
at balance condition– (c) frequency (d) current
Z1 Z4 = Z2 Z3 Mizoram PSC AE/SDO 2012-Paper-I
 1  Ans. (c) : Wien's bridge is used for the precision
 1   R 3 × jωC  measurement of capacitance in term of resistance and
 R4 = R2 
3 
⇒  R1 + frequency. It also used to measure audio frequency.
 jω C1  1 
 R 3 + jωC  43. Match List-I (Bridges) with List-II
 3  (Parameters) and select the correct answer
jωR1R 4 C1 + R 4 R 3R 2 using the codes given below the lists:
=
jωC1 jωR 3C3 + 1 List-I List-II
(jωR1R4C1 + R4) (jωR3C3 + 1) = jωC1R3R2 A. Anderson bridge 1. Low Resistance
(j2ω2R1C1R3C3R4+ jωR4 R3C3 + jωR1 R4C1 + R4) B. Kelvin Bridge 2. Medium
= jωC1R3R2 Resistance
(–ω2R1C1R3C3R4 + R4) = jωC1R3R2 – jωR4 R3C3 – jωR1 C. Schering Bridge 3. Inductance
R4 C1 D. Wheatstone Bridge 4. Capacitance

Codes: or Q-factor = ωRC
A B C D
(a) 4 2 3 1
(b) 3 2 4 1
(c) 3 1 4 2
(d) 4 1 3 2
IES-1999
Ans. (c) :
(A) Anderson bridge – Measures inductance
(B) Kelvin bridge – Low resistance
(C) Schering bridge – Capacitance
(D) Wheatstone bridge – Medium resistance
46. The ac bridge shown in the figure is balanced if
44. In the balance bridge shown in the figure, 'X' Z1 = 100∠30º, Z2 = 150∠0º, Z3 = 250∠ – 40º
should be and Z4 is equal to
(a) a self-inductance having resistance (a) 375∠70º (b) 375∠ – 70º

(b) a capacitance (c) 150∠0º (d) 150∠20º
(c) a non-inductive resistance IES-1999
(d) an inductance and a capacitance in parallel Ans. (b) : Given that,
IES-1999 Z1 = 100∠30°
Ans. (a) : Given- Z2 = 150 ∠0°
Z1 = X Z3 = 250 ∠ –40°
Z2 = R2 + jωL2 Z4 = ?
Z3 = R3 At balance condition -
Z4 = R4 Z1Z4 = Z2Z3
At balance condition - Z2 Z3 150∠0o × 250∠ − 40o
Z1 Z4 = Z2 Z3 Z4 = =
X. R4 = (R2 + jωL2). R3
Z1 100∠30o
R R R Z4 = 375 ∠ –70°
X = 2 3 + jω L 2 3 47. Consider the following operations in respect of
R4 R4
a Wheatstone bridge:
So, that X should be a self inductance (L) having
resistance (R) in series. (Key 'Kb' is used for the supply battery and
Key 'Kg' is used for the galvanometer)
X = R + jωL
1. Open Kb 2. Close Kg
45. While using Maxwell bridge, the Q factor of a
coil is obtained as 3. Close Kb 4. Open Kg
1 (a) 1, 2, 3, 4 (b) 3, 1, 2, 4
(a) (b) ωCR (c) 4, 3, 2, 1 (d) 3, 2, 4, 1
ωCR
IES-1999
R
(c) ωC/R (d) Ans. (d) :
ωC
IES-1999
Ans. (b) : According to Maxwell bridge -
R R
R1 = 2 3 and L1 = R2R3C4
R4
Where R1 and L1 unknown quantity
Quality factor for Maxwell bridge -
ωL1 ωR 2R 3C4 ωR 2R 3C4R 4
Q= = = = ωR 4 C 4
R1 R 2 R 3 / R 4 R 2R 3

The battery key 'kb' should be closed first followed by 1
closing of galvanometer key (kg) after short interval. Rb ×
1 jωCb Rb
If the galvanometer key pressed first then due to self Z1 = Rb || = =
jωCb R + 1 1 + jωR bCb
induction, a current will be induced which is likely to b
damage the galvanometer. jωCb
48. Given, Za = 100∠50º, Zb = 300∠90º, Zc = Z2 = Rc
200∠0º the value of Zd for the bridge shown in Z3 = Ra
the figure to be balanced is Z4 = Rd + jωLd
at balance condition –
Z1 Z4 = Z2 Z3
Rb
(R d + jωLd ) = R a R c
1 + jωR b C b
RbRd + jωRbLd = Ra Rc + jωRaRbRcCb
having comparison of real and imaginary terms –
Rb Rd = Ra Rc and Rb Ld = Ra Rb Rc Cb
R R
(a) 600∠ – 40º (b) 600∠140º R d = a c and Ld = Ra Rc Cb
Rb
(c) 600∠ – 140º (d) 600∠40º
IES-1998 Q Qd = ωLd = ωR a R cC b
Ans. (d) : As Given that, Rd RaRc / Rb
Za = 100∠50° Q d = ωR b C b
Zb = 300∠90° 50.
Which one of the following detectors is
Zc = 200∠0° generally used in ac bridges for audio
Zd = ? frequency range?
At balance condition- (a) AC voltmeter
ZaZd = ZbZc (b) CRO
Z Z 300∠90°× 200∠0° (c) Headphones
Zd = b c =
Za 100∠50° (d) Vibrations galvanometer
Zd = 600∠40° IES-1997
49. For the ac bridge circuit shown in the figure at Ans. (c) : Headphone detectors is generally used in ac
balance, the value of Rd, Ld and Qd will be bridge for audio frequency range.
respectively. 51. To measure low resistances, four terminals
approach is preferred because it
(a) eliminates the effect of thermoelectric emf
(b) minizes the effects of parasitic capacitances
(c) reduces the effects of parasitic inductances
(d) eliminates the effects of lead and contact
resistances.
IES-1996
Ra R R Ans. (d) :
(a) R b ; a c ; ωC b R b
Rc Cb
Rb R R
(b) R c ; a c ; ωC b R b
Ra Cb
Rb
(c) R c ;R a R c Cb ; ωC b R c
Ra
To measure low resistance, four terminals approach is
Ra
(d) R c ;R a R c C b ; ωC b R b preferred because it eliminates the effects of lead and
Rb contact resistance.
IES-1998 52. Kelvin double bridge is chosen to measure low
Ans. (d) : The given bridge is Maxwell inductance resistance because
capacitance bridge. (a) it has a high sensitivity
Rd and Ld → unknown quantity (b) thermoelectric emfs can be taken

(c) resistance variation due to temperature can be 54. De-Sauty bridge is more widely used because of
accounted for (a) Simplicity
(d) resistance variation due to contacts of leads (b) perfect balance for imperfect capacitors
can be eliminated (c) perfect balance for air capacitors
IES-1996 (d) maximum sensitivity
Ans. (d) : • Kelvin double bridge is chosen to measures IES-1994
the low resistance because it eliminate resistance Ans. (a) : • De-sauty bridge is more widely used
variation due to contacts of lead. because of simplicity.
• Kelvin's double bridge method is a modification of the • This bridge is suitable for perfect capacitor value
Wheatstone bridge method. measurement only (No-dielectric loss)
53. In the ac bridge shown in the given figure, the 55. The three impedances of an ac bridge shown in
value of Rx and Cx at balance will be given figure are:
Z1 = 200Ω∠60º
Z2 = 400Ω∠–90º , Z3 = 300Ω∠0º
The value of Z4 for the bridge to be balanced is
(a) 150Ω∠30º (b) 400Ω∠90º
(c) 300Ω∠90º (d) 600Ω∠–150º
IES-1994
Ans. (d) : As given that–
Cb R Z1 = 200Ω∠60°
(a) R x = R c ,C x = b C a Z2 = 400Ω∠–90°, Z3 = 300Ω∠0°
Ca Rc Z4 = ?
Ca R
(b) R xx = R c ,C x = c C a
Cb Rb
Ca R
(c) R x = R c ,C x = b C a
Cb Rc
Cb R
(d) R x = R c ,C x = c C a
Ca Rb
IES-2016, 2007, 1996
Ans. (a) : Given that, At balance condition-
Z1Z4 = Z2Z3
1
Rb × Z Z
1 jωC b R b / jωC b Z4 = 2 3
z1 = R b || = = Z1
jωC b R + 1 ( jωR b C b + 1) / jωC b
400∠ − 90°× 300∠0°
jωC b
b
=
Rb 200∠60°
z1 = Z4 = 600Ω∠–150°
1 + jωR b C b
56. Consider the circuit shown in the given figure
z 2 = Rc for the measurement of resistance X using
1 Voltmeter-Ammeter method.
z3 =
jωCa Ammeter resistance, Ra = 0.1Ω
1 1 + jωR x C x Voltmeter resistance, Rv = 5000Ω
z4 = R x + = If X1 and X2 are the measured values of X
jωC x jωC x switch positions 1 and 2 respectively, then the
At balance condition, arithmetic means of X1 and X2 will be
z1z 4 = z 2 z 3
Rb 1 + jωR x C x 1
× = Rc ×
1 + jωR b C b jωC x jωC a
R b Ca (1 + jωR x C x ) = R c C x (1 + jωR b C b )
R bC a + jωR x C x R b Ca = R c C x + jωR b C b R c C x
Having comparison of real and imaginary terms-
R b Ca = R c C x and R x C x R b Ca = R b C b R c C x
(a) 9.98Ω (b) 10.000Ω
Rb C
Cx = .Ca and R x = b R c (c) 10.04Ω (d) 10.10Ω
Rc Ca IES-1993
Ans. (c) : As given that, Ra = 0.1Ω, Rv = 5000 Ω 58. Weins bridge is used for measurement of
1st case – when switch at position- 1 frequency in the applied voltage waveform is
(a) sinusoidal (b) square
(c) rectangular (d) triangular
IES-1991
Ans. (a) : Weins bridge is used for measurement of
frequency in the applied voltage waveform is sinusoidal.
Any other periodic signal has many harmonics.
V1 59. The bridge most suited for measurement of a
X1 = = Ra + X
I1 four-terminal resistance in the range of 0.001Ω
= 0.1 + 10 = 10.1Ω to 0.1Ω
2nd case- when switch at position-2 (a) Wien's bridge (b) Kelvin double bridge
(c) Maxwell's bridge (d) Schering Bridge
Ans. (b) : Low resistance standard are four terminal
type. With four terminal resistor the errors on account
of contact (Lead) resistance are avoided. Kelvin double
bridge is suitable for the measurement of low value of
resistance upto micro ohm (µΩ).
V2 60. The bridge best suited for measurement of
X2 = = R v || X
I2 mutual inductance is:
= 5000 ||10 (a) De Sauty bridge
(b) Wien bridge
5000 × 10
= = 9.98Ω (c) Heaviside Campbell bridge
5010 (d) Schering bridge
X + X 2 9.98 + 10.1 20.08 OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
∴ 1 = = = 10.04Ω
2 2 2 APGENCO AE-23.04.2017
57. In the Wheatstone bridge shown in the given Ans. (c) : Heaviside Campbell bridge- This bridge is
figure, if the resistance in each arm is increased used to measure self-inductance in terms of a mutual
by 0.05% then the value of Vout will be inductance.
(a) 50 mV (b) 5 mV
(c) 0.1 V (d) zero
IES-1993
Ans. (d) :
R1 R4 = R 2 R3 61. The following bridge can be used for
5kΩ×16 kΩ = 8kΩ×10kΩ measurement of frequency:
80kΩ = 80kΩ (a) Maxwell bridge (b) Wien bridge
(c) Hay bridge (d) De Sauty bridge
Therefore bridge is at balanced condition so, Vout = 0
when the resistance in each arms is increased by 0.05%
Mizoram PSC AE/SDO-2012, Paper I
then -
Ans. (b) : Wien Bridge- The wien bridge is primary
R1 R4 = R 2 R3 known as a frequency determining bridge. It can also be
2.5Ω×8Ω = 4Ω×5Ω used for the measurement of an unknown capacitor with
20Ω = 20Ω great accuracy.
So that bridge is balanced. The bridge employed for measuring frequency in the
Vout = 0 audio range ( 20Hz − 20kHz ) .

62. The bridge circuit shown in the figure below is (a) cannot be balanced
used for the measurement of an unknown (b) can be balanced but the frequency of
element Zx. The bridge circuit is best suited excitation must be known
when Zx is a: (c) can be balanced for only one frequency
(d) can be balanced at any frequency
BSNL(JTO)-2009
Ans. (b) : At balance condition
Z1Z3 = Z2Z4
1
R1×R2 = jωL×
jωC
(a) Low resistance (b) High resistance
(c) Low Q inductor (d) Lossy capacitor L
R1×R2 =
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I C
Ans. (c) : Maxwell Bridge- So it can be balanced at any frequency.
65. Which of the following is used to measure the
leakage resistance of a capacitor?
(a) Megger
(b) Schering bridge
(c) Potentiometer
(d) Loss of charge method
R R Nagaland PSC CTSE (Degree)-2018, Paper-I
Rx = 2 3 Ans. (b) : Schering bridge is used to measure the
R1
leakage resistance of a capacitor.
C x = C1R 2 R 3 Schering bridge also measure dissipation factor,
Maxwell bridge is limited to the measurement of low Q capacitance, relative permittivity and power factor.
values (1–10). Megger- Megger is an easily portable hand driven
generator megger is used for the measurement of
63. Wheatstone bridge is used to measure insulation resistance of cables, bushing insulation.
(a) low values of current and high values of current
(b) high values of current (v) Power and Energy Measurements
(c) low value of voltages
1. If power is measured using two-wattmeter
(d) resistance values method with unity power factor, then :
RRB SSE 21.12.2014, (Yellow) (a) one of the wattmeters will read zero
MPPSC Forest Service Exam-2014 (b) both the wattmeters will have the same
Ans. (d) : Wheatstone bridge is used to measure of reading
unknown resistance value. We use this method for medium (c) the reading of one wattmeter will be two
range resistors (1Ω to 100KΩ ) . For balance condition- times the other
(d) one of the wattmeters will read negative
Ans. (b) : W1 = W2
Then,
 W − W1 
tan φ = 3  2 
R1 R 4  W1 + W2 
=
R2 R3  W − W1 
= 3 1 
R 1R 3 = R 2 R 4  W1 + W1 
tan φ = 00
64. The bridge circuit shown in figure
φ = 00
So, cos φ = cos 00 = 1
2. The phenomenon of creeping occurs in
(a) Ammeter (b) Voltmeter
(c) Wattmeter (d) Energy meter
IES-2005, 1995
Ans. (d) : Creep error is associated with energy meter. Ans. (c) : Induction effect is used to measuring power
In energy meter, if the friction is over compensated or i.e. For measurement of power in A.C. circuit, the meter
there is excessive voltage across the potential coil there used is based on electro-magnetic induction. We can
is a tendency for the disc to run even when there is no use these instrument as an wattmeter voltmeter,
current through the current coil is called creeping for ammeter and an energy meter.
preventing creeping two diametrically opposite hole are 6. If an induction type energy meter runs fast, it
drilled in the opposite side of the disc. can be slowed down by
Energy meter - (a) lag adjustment
• It is an integrating type instrument. (b) light load adjustment
• Its principle is similar to transformer. (c) by adjusting the position of braking magnet
• It is known as watt-hour meter and used to measure and making it come closer to the centre of the
energy in kWh disc
φ ⋅N
2 (d) by adjusting the position of braking magnet
Tb ∝ ×R and making it move away from the centre of
Re the disc.
Where, TNPSC AE-2008
N → speed in rpm Ans. (d) : If the energy meter run fast, it can be slowed
φ → Flux down by adjusting the position of braking magnet and
Tb → Braking torque making it move away from the disc and to increase the
R → radius of disc speed adjust the position of breaking magnet and
making it close to the disc.
Re → resistance in path of current (i.e. disc)
1
3. The energy meter installed near the main N∝
switch in a residence and other locations is d
(a) Indicating or deflecting type instrument where,
(b) Integrating type instrument d → distance of braking magnet.
(c) Recording type instrument 7. Which type of wattmeter cannot be used for
(d) Absolute instrument D.C.?
RRB SSE 01.09.2019, Shift-II (a) Electrostatic type (b) Dynamometer type
RRB SSE 02.09.2015, Shift-II (c) Induction type (d) None of these
Ans. (b) : Energy meter is integrating type instrument. TNPSC AE-2008
It is a device that measures the amount of electrical Ans. (c) : Induction phenomenon is not occurred in
energy consumption. DC. So, induction type wattmeter cannot be used for
4. The moving coil in a dynamometer wattmeter DC.
is connected 8. Three phase four wire energy meter is used to
(a) In series with the fixed coil measure:
(b) Across the supply (a) Single phase energy
(c) In series with the load (b) Two phase energy
(d) Across the load (c) Three phase balanced energy
GPSC Asstt. Prof. 11.04.2017 (d) Three phase unbalanced energy
Ans. (b) : Nagaland PSC CTSE (Diploma)-2018, Paper-I
Ans. (d) : Three phase four wire energy meter is used to
measure three phase unbalanced energy.
The two wattmeter method used for the measurement of
power in 3-phase, 3-wire load circuits and three-
wattmeter method used for the measurement of power
in 3-phase, 4-wire load circuit.
9. The simplest and most common method of
reducing any effect of inductive coupling
A dynamometer type wattmeter is basically a moving between measurement and power circuits is
coil instrument. The moving coil in a dynamometer achieved by using
wattmeter is connected across the supply is called a (a) a screen around the entire measurement
voltage coil or pressure coil. circuit
(b) twisted pairs of cable
5. Which one of the following effect is used in
(c) capacitor(s) to be connected at the power
measuring power? circuit
(a) seebeck (b) Ferranti (d) capacitor(s) to be connected at the
(c) induction (d) hall measurement circuit
Mizoram PSC AE/SDO 2012-Paper-I IES-2017
Ans. (b) : Inductive coupling is used to transfer the
energy from one circuit to another by virtue of the
mutual inductance between the circuits.
To minimize the effect of inductive coupling, use the
twisted pair cable that will reduces the area (A) and
decreases the induced voltage effect in the function of B
field.
(ii) Pload = 20×30 = 600W
dφ
E∝ φ = BA V 2 (30)2
dt Ppc = =
d R pc 100
E ∝ ( BA )
dt 30 × 30
= =9
100
Pmeasured = 600+9
= 609
609 − 600 9
Error = × 100 = × 100 = 1.5%
600 600
11. For controlling the vibration of the disc of an
AC energy meter, damping torque is produced
by
The twisted pair consider as a pair of wires. The wire (a) eddy current (b) chemical effect
are wound in a spiral in order to, reduce the noise and (c) electrostatic effect (d) magnetic effect
maintain the electrical properties throughout its length. IES-2012, 2004
10. The resistance of two coils of a watt-meter are Ans. (a) : Damping torque is produced by eddy current
0.0Ω and 100Ω respectively and both are non- for controlling the vibration of the disc of an AC energy
inductive. The current through a resistance meter.
load is 20 A and the voltage across it is 30 V. In Tb . ∝ Nφ2m d
one of the two ways of connecting the voltage Tb → braking torque
coil, the error in the reading would be The braking toque of induction type single phase
(a) 0.1% too high (b) 0.2% too high energy meter proportional to flux square.
(c) 1.5% too high (d) zero 12. What is the major cause of creeping in an
energy-meter?
IES-2013
(a) Over compensation for friction
Ans. (d) : Case-I When pressure coil is connected to (b) Mechanical vibrations
source side- (c) Excessive voltage across the potential coil
(d) Stray magnetic fields
IES-2009
Ans. (a) : The major cause of creeping in an energy
meter is over compensation for friction. Creeping in
energy meter is the phenomenon by which the disc of
energy meter rotates even in absence of any load current
in the current coil (CC) and only pressure coil (PC) is
energized. The necessary condition for creeping is that
PLoad = 20 × 30 = 600W
PC must be energized.
Pcc = Ic2 rcc 13. A compensated wattmeter has its reading
= (20)2 × 0 corrected for error due to which one of the
following parameters?
=0W (a) Frequency
Pmeasured = 600 + 0 = 600W, (b) Friction
Measured value − True value (c) Power consumed in current coil
% Error = ×100
True value (d) Power consumed in pressure coil
IES-2006
600 − 600
% Error = × 100 = 0% Ans. (d) : A compensated wattmeter has its reading
600 corrected for error due to power consumed in potential
Case-II When pressure coil is connected to load side- coil.

To compensate for the power loss in the pressure coil 15.
compensating coil with an equal number of turn of the
current coil is connected in series opposition to the
potential coil or pressure coil.
14. Consider the following statements in respect of Consider the following data for the circuit
two types of a dynamometer wattmeter shown above:
connections are shown below the figure (a) and Ammeter : Resistance 0.2Ω; Reading 5.0A
figure (b). Voltmeter: Resistance 2kΩ ; Reading 200V
Wattmeter : Current coil resistance 0.2Ω
Pressure coil resistance 2KΩ
Load : Power factor = 1
The reading of the Wattmeter is :
(a) 980 W (b) 1000 W
(c) 1005 W (d) 1010 W
IES-2003
Ans. (d) : Resistance of ammeter = 0.2Ω
Resistance of current coil = 0.2Ω
V = 200 V
Effective resistance = (0.2 + 0.2) Ω

= 0.4 Ω
Net voltage (V) = (0.4 × Ia) + 200
1. Figure (a) is used when applied voltage is = 0.4 × 5 + 200
high and load current flowing is low.
= 202 V
2. Figure (b) is used when applied voltage is Reading of wattmeter, W = VI cosφ
low and load current flowing is high.
= 202×5×1
3. If the order of connections in Statements 1 = 1010 W
and 2 are in opposite order, gross error
16. If a dynamometer type wattmeter is connected
will be increased.
in an ac circuit the power indicated by the
4. If the order of connections in Statements 1 wattmeter will be
and 2 are in opposite order, gross error (a) volt-ampere product
will be reduced. (b) average power
Which of the statements given above are (c) peak power
correct? (d) either 90 degrees or 270 degrees
(a) Only 1 and 2 (b) Only 1 and 2 IES-1998, 1997
(c) 1, 2 and 3 (d) 1, 2 and 4 Ans. (b) : If a dynamometer type wattmeter is
IES-2006
connected in an A.C. circuit the power indicated by the
Ans. (c) : When pressure coil is connected in source wattmeter will be average power.
side the it is used for small current and high power We know that- Td ∝ VIcos φ
factor load. Where, Td → Deflection Torque
When pressure coil is connected in load side then it And P = VI cos φ
is used for large current and low power factor load.
So, Td ∝ Average power
If the order of connection is reversed then there will
be more power consumption, this increases gross It has a uniform scale. It can be used both on AC and
error. DC on circuits.
17. Which of the following methods can be used for  2W1 − W1  W1
measuring power without using wattmeter. = 3  = 3×
1. One voltmeter, one ammeter  W1 + 2W1  3W1
2. Two voltmeters, two ammeters 1
tan φ =
3. Three voltmeters 3
4. Three ammeters φ = 30 0

(c) 1 and 3 only (d) 4 only So, cos φ = cos300 = 0.866
IES-1992 20. A 300 V, 5A, 0.2 pf low power factor wattmeter
Ans. (a) : P = VI cosφ is used to measure the power consumed by a
Where, φ = angle between voltage and current load. The wattmeter scale has 150 divisions and
the pointer is on the 100th division. The power
cos φ = load power factor consumed by the load (in watts) is:
Power is the multiplication of voltage and current. So (a) 100 (b) 200
for the measurement of power without wattmeter can be (c) 400 (d) 500
done by using a ammeter and a voltmeter. OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
18. Which of the following statements is true about Ans. (b) :Voltage (V)=300 V
two wattmeter method for power measurement Current (I)=5A
in three phase current? Power factor (cos φ) = 0.2
(a) Power can be measured using two wattmeter full scale reading of wattmeter.
method only for star connected three phase P= VI cosφ
circuits. =300 ×5×0.2=300W
(b) When two meters show identical readings, the Wattmeter scale has 150 divisions.
power factor is 0.5. 300
(c) When power factor is unity, one of the Each division constitutes, 150 = 2W / div of reading
wattmeter reads zero. while measuring the power consumed by a load, pointer
(d) When the readings of the two wattmeters are is on the 100th division.
equal but of opposite sign, the power factor is 100 division constitute 100×2=200 W of power.
zero. 21. Creeping error in energy meter is due to _____
IES-1992 voltage
Ans. (d) : According option d (a) linearly increasing (b) constant
W1 = − W2 (c) least (d) Excessive
Then, AAI-2015
Ans. (d) : Creeping error in energy meter is due to
 W − W2  excessive voltage at no load. Due to this error energy
tan φ = 3  1 
W
 1 + W 2 
meter disk creeps slowly. Slowly to avoid this error we
do two holes on the disc of energy meter at 1800
 W – ( –W1 )   W1 + W1  diagonally.
= 3 1  = 3 
 W 1 – W 1   0  22. The power factor meter has
tan φ = ∞ (a) one current and one pressure circuit
(b) one current circuit and two pressure circuits
φ = 900 (c) two current circuits and two pressure circuits
So, cos φ = cos90° = 0 (d) two current circuits and one pressure circuits
19. The power of a three phase, three wire
balanced system was measured by two Ans. (b) : The power factor meter has one current and
Wattmeter method. The reading of one two pressure coil. It is used to measure the power factor of
Wattmeter was found to be doubled that of the circuit. The shunt coil is connected across the circuit.
other. What is the power factor of the system? 23. The following could be the one of the errors in
(a) 0.5 (b) 0.866 an energy meter
(c) 0.25 (d) 1 (a) Clamping (b) Clipping
(c) Creeping (d) Clogging
Ans. (b) : According to the question -
Ans. (c) : Due to excessive voltage at no load creeping
W2 = 2W1 errors occurs in an energy meter. In this error disc of
 W − W1  energy meter creeps, slowly-slowly. To avoid this error
Then tan φ = 3  2  we do two holes on the disc of energy meter at 1800 or
W
 1 + W 2  diagonally.

24. Wattmeter is of Ans. (b) : given 600 rev/Kwh
(a) PMMC type (b) Dynamometer type 600
(c) Moving iron type (d) Hot wire type = rev / min
RRB SSE 01.09.2015, Shift-II 1000 × 60
Ans. (b) : Wattmeters is a dynamo meter type 600
So reading of wattmeter = × 600
instruments. It is used to measure electric power in 1000 × 60
electric circuit. There are 2 type of wattmeter. = 6 RPM
(i) Dynamo meter type wattmeter.
29. Consider two metallic wires W1 and W2. They
(ii) Induction type wattmeter
are made up of same material and each has
It has one pressure coil and one current coil. It is used t
circular cross-section. The diameter of W2 is
measure active power.
twice that of W1 and the length of W2 is four
25. For the measurement of electrical energy, we times that of W1. Which one of the following
may use a
statement is TRUE ?
(a) Wattmeter
(a) Resistance of W1 is half that of W2
(b) KWh meter
(b) Resistance of W1 is equal to that of W2
(c) Multimeter
(d) Voltmeter, ammeter and PF meter (c) Resistance of W1 is twice that of W2
RRB SSE 01.09.2015, Shift-III (d) Resistance of W1 is eight times that of W2
Ans. (b) : For the measurement of electrical energy, we BSNL(JTO)-2009
use kWh meter. It has two current coils and one l
pressure coil. A permanent magnet is used for breaking Ans. (b) : R = ρ
A
torque. It’s pressure coil is highly inductive.
d2 = 2d1, l2 = 4l1
 N No. of revolution 
 K = E =
l
kWh  R1 = ρ 1 2
πd1
[ K = Energy meter constant ] 4 × l1
l2
26. Induction type single phase energy meters R2 = ρ = ρ×
π × ( 2d1 )
2
πd 2 2
measure electric energy in
(a) kW (b) Wh l1
= ρ = R1
(c) kWh (d) VAR d12
RRB SSE 02.09.2015, Shift-III Hence, R2 = R1
Ans. (c) : Induction type single of energy inters
30. Most common form of A.C. meters met with in
measure electric energy in kWh. Energy meter has two
every day domestic and industrial installation
current coil and one coil is pressure coil. The pressure
are
coil of energy meter is highly inductive. Breaking
(a) mercury motor meters
torque is provided by permanent magnet. Due to
excessive voltage at no load creeping error is present. (b) commutator motor meters
(c) induction type single phase energy meters
27. A wattmeter will read zero under the following
(d) either mercury motor meters or commutator
condition
motor meters
(a) The voltage and current are exactly in phase
(b) The voltage and current have the same time
periods but the voltage is sinusoidal whereas Ans. (c) : Induction type single of energy meters most
the current is a square wave common form of a.c. meters. It is used in domestic and
(c) the voltage frequency is twice the current industrial ac circuit for measuring the power.
frequency 31. Which one of the following has a magnetic
(d) The current is dc and the voltage is sinusoidal brake?
BSNL (JTO)-2001 (a) Thermocouple ammeter
Ans. (d) : A wattmeter will read zero under the current (b) Energy meter
is dc and the voltage is sinusoidal. (c) Frequency meter
(d) Thermocouple voltmeter
28. On an induction type energy meter, is written
"600 rev/kWh". If it is to be used an KVS TGT (WE)- 2014
approximate wattmeter which is read off in Ans. (b) : A ‘brake magnet’ produces a controlling
rpm, a 600 watt load would read as torque on the disc which has no pointer as an energy
(a) 10 rpm (b) 6 rpm meter is an integrating. Instrument and the disc has to
(c) 1 rpm (d) 36 rpm rotates continuously so long the meter remains
BSNL (JTO)-2001 connected in the circuit.

1
(vi) Electronic Voltmeters and 5. A DVM has a 4
2
digit display. The 1 volt
Digital Voltmeters range can read upto
(a) 9999 (b) 9.99
1. A digital voltmeter uses an A/D converter which
needs a start pulse, uses an analog comparator (c) 1.9999 (d) 0.19999
and has a relatively fixed conversion time Nagaland PSC CTSE (Diploma)-2018, Paper-I
independent of the applied voltage. Nagaland PSC CTSE (Degree)-2016, Paper-I
The A/D converters is IES-2011
(a) Successive approximation converter TNPSC AE-2008
(b) Digital Ramp converter 1
(c) Digital slope converter Ans. (c) : 4 Digit display have five digits with 1 half
2
(d) All of these
digit (0 or 1) and 4 full digits the range of display from
0 to 19999.
Ans. (a) : A digital voltage uses an A/D converter
which needs a start pulse uses an analog comparator and
has a relatively fixed conversion time independent of
applied voltage. The A/D converter is successive The 1volt range can read up to 1.9999.
approximation converter.
6. The common mode error voltage in a DVM
2. In Electronics Voltmeter (EVM), Buffer amplifier is can be eliminated by using at its input
used to? (a) a differential amplifier
(a) Increase the current amplification.
(b) a wide band amplifier
(b) Decrease the current amplification.
(c) a tuned amplifier
(c) Decrease the Loading Capacity.
(d) Increase the Loading Capacity. (d) a low-pass filter
APPSC Poly. Lect. 15.03.2020 RPSC Vice Principal ITI-2016
Ans. (d) : Electronic voltmeter which use the amplifier IES-2002
for increase the loading capacity. It is used for Ans. (a) : In a DVM, common mode error can be
measuring the voltages of both the A.C. & D.C. devices. eliminated through a differential amplifier. It is a device
The electronics voltmeter gives the accurate reading that is used to amplify the difference in voltage of the
because of high input resistance. two input signal.
The working of electronic voltmeter is free from CMRR (Common Mode Rejection Ratio) of differential
frequency range because of the transistor. amplifier is very high.
3. A DVM measures : A
(a) Peak value (b) R.M.S. value CMRR = d
(c) Peak-to-peak value (d) Average value Ac
Nagaland PSC CTSE (Degree)-2018, Paper-I Where, Ad - Differential voltage gain
Nagaland PSC CTSE (Degree)-2017, Paper-I Ac - Common mode gain
TNPSC AE-2008 7. Modern electronic multimeter measure
resistance by
Ans. (d) : Digital voltmeter (DVM) is an electronic
testing equipment that is used for measuring the (a) using bridge circuit
electrical potential difference between two conductors (b) using an electronic bridge compensation for
in a circuit. nulling
A DVM measures average value. (c) applying a constant voltage and measuring
A DVM is also known as integrating type voltmeter. the current through the unknown resistor
4. A digital voltmeter has a read-out range from 0 (d) Forcing a constant current and measuring the
to 9999. When full-scale reading is 9.999 V, the voltage across the unknown resistor
resolution of the full scale reading is KVS TGT (WE)- 2014
(a) 0.001 (b) 1000 Ans. (d) : For measurement of resistance by modern
(c) 3 digit (d) 1 mV electronic multimeter is done by forcing a constant
Nagaland PSC CTSE (Degree)-2017, Paper-I current and measuring the voltage across the unknown
Mizoram PSC AE/SDO 2012-Paper-I resistor.
RPSC Lect. 2011 8. The reed frequency meter is essentially a :
Ans. (d) : • FSR = 9.999 (a) Recording measuring system
• It is a 4 digit voltmeter, r = 4 (b) Deflection measuring system
• Range of voltmeter = 10V (c) Vibrational measuring system
1 (d) Oscillator measuring system
• Resolution = × 10 = 1mV
104 Nagaland PSC CTSE (Degree)- 2016, Paper-I
Ans. (c) : The reed frequency meter is essentially a Ans. (d) : A VTVM is more reliable than multimeter
vibrational measuring system with the help of system for measuring voltage across a low impedance because
vibrations, we can measure the frequency. its sensitivity is very high. It offers high impedance and
The reed frequency meter has vibrating reeds and each it does not alter the voltage measurement.
vibrating reed has a specific value. These reeds vibrates 14. A vector impedance meter measures
when this frequency meter is connected to supply for (a) The magnitude of the impedance
the measurement of frequency. (b) The power dissipation in the impedance
9. Which of the given frequency meters is suitable (c) The phase angle of the impedance
to measure radio frequency. (d) Both the magnitude and the phase angle of
(a) Weston frequency meter the impedance
(b) Electrical resonance frequency meter IES-2018
(c) Heterodyne frequency meter Ans. (d) : A vector impedance meter can measure both
(d) Either (b) or (c) the magnitude and phase angle of the impedance.
Nagaland PSC CTSE (Degree)- 2016, Paper-I Impedance, which is having both magnitude and phase,
Ans. (c) : Heterodyne frequency meter used to measure is truly an opponent to the flow of current in A.C.
radio frequency while reed vibrator frequency meter circuits with the presence of an applied voltage.
used for the measurement of low frequency. Electrical In vector impedance meter, the coverage of instrument
resonance frequency meter is used only for power can be obtained with sweep frequency plot of
frequency. impedance and phase angle versus frequency.
10. Which of the following equipment can check 15. A vector voltmeter can be used to measure
the condition of a transistor? 1. Complex insertion loss
(a) Current tracer (b) Ohmmeter 2. Two-port network parameters
(c) Digital display meter (d) All of these 3. Amplifier gain and phase shift
Mizoram PSC IOLM -2018, Paper I 4. Harmonic distortion
Ans. (d) : Current tracer, digital display meter and Which of the above are correct?
ohmmeter equipments to check the condition of a (a) 1, 2 and 4 (b) 1, 2 and 3
transistor. (c) 1, 3 and 4 (d) 2, 3 and 4
11. An electronic voltmeter with a broad IES-2018, 2017
bandwidth has Ans. (b) : A vector voltmeter measures the amplitude of
(a) low noise level and high sensitivity signal at two points and at the same time measure their
(b) high noise level and high sensitivity phase difference. It is used to measure the following
(c) high noise level and low sensitivity quantities:
(d) low noise level and low sensitivity (1) Amplifier gain and phase shift
TNPSC AE-2008 (2) Complex insertion loss
(3) Two-port network parameter
Ans. (c) : The noise is a function of bandwidth, the
lesser the bandwidth, less is the pickup of noise. The (4) Radio frequency distortion
voltmeter with broad bandwidth is sensitive to pick up (5) Amplitude modulation index.
more noise and has less sensitivity. (6) Filter transfer function.
12. VTVM can be used to measure (7) ‘s’ parameter of transistor
(a) DC voltage 16. Consider the following statements:
(b) AC voltage of high frequency Sphere gap method of voltage measurement is
(c) DC voltage and ac voltage up to the order of used
5MHz frequency 1. for measuring r.m.s. value of a high voltage
(d) AC voltage of low frequency 2. for measuring peak value of a high voltage
Nagaland PSC CTSE (Degree)-2017, Paper-I 3. as the standard for calibration purposes
Ans. (a) : Vacuum tube voltmeter (VTVM) used to Which of the above statements are correct?
measure the DC voltage. A VTVM can never measures (a) 1 and 2 only (b) 2 and 3 only
current directly because of its high resistance. (c) 1 and 3 only (d) 1, 2 and 3
Note: A VTVM are used for the measurement of the dc IES-2017
and ac voltages. Ans. (b) : Sphere gap voltmeter is used for measure
13. A VTVM is more reliable as compared to voltage.
multimeter for measuring voltage across low • Sphere gap can be used to measure the peak value of
impedence because high voltage if gap distance is known.
(a) Its sensitivity is very high It is also used for the standard calibration purpose.
(b) It offers high input impedance Sphere gap measurement can be arranged in two ways-
(c) It does not alter the measured voltage 1. Vertically with lower sphere grounded.
(d) All of these 2. Horizontally with both sphere connected to the
Nagaland PSC CTSE (Degree)- 2016, Paper-I source voltage or one sphere grounded.
17. AC voltmeters are diodes with: (100110)2 = (?)10
(a) High forward current and low reverse current = 1×25+0×24+0×23+1×22+1×21
ratings +0×20
(b) Low forward current and low reverse current = 32+4+2
ratings = (38)10
(c) Low forward current and high reverse current Now the output voltage is
ratings
Vo = 0.317 × 38
(d) High forward current and high reverse current
= 12.046
ratings
Vo 12.06
IES-2016
Ans. (a) : A.C. voltmeters are diodes with high forward 20. Consider the following types of digital
current and low reverse current rating. voltmeters:
Rectifying Element:- 1. Ramp type
2. Dual slope integrating type
• The rectifying element offers zero resistance when it
is in forward bias and infinite resistance when it is in 3. Integrating type using voltage to frequency
reverse biased. Therefore, diodes have a high forward conversion
current and low reverse current rating. 4. Successive approximation type
Germanium (Ge) and Silicon diode are used for making 5. Servo balanced potentiometer type
rectifying elements. Which of these require a fixed reference
voltage at the comparator stage?
1
18. A 3 digit voltmeter has an accuracy (a) 1 and 2 only (b) 2, 4 and 5 only
2 (c) 2 and 3 only (d) 1, 4 and 5 only
specification of ±0.5% for reading ± one digit. IES-2015
What is the possible error in volts when the
instrument displays 2.00 V on the 10V scale? Ans. (c) : Dual slope DVM- Block diagram of dual
slope DVM-
(a) 0.03 V (b) 0.02 V
(c) 0.01 V (d) 0.005 V
IES-2017, 2016
Ans. (b) : Given that,
Voltmeter reading = 2
Full scale reading = 10V
No. of full digit = 3
1
Revolution of N-digit DVM= N × range of voltage
10
1
Resolution = 3 × 10 = 0.01V
10
For accurate voltage measurement, ramp type DVM
The voltage corresponding to one digit = 0.01V
require precise ramp voltage and precise time
Error in voltmeter = ± 0.5% of displaying 2.0V periods both of which can be difficult to maintain.
reading ± 1 digit The dual slope DVM virtually eliminates those
= 0.005×2 + 0.01 requirement by using a special type of ramp
= 0.02V generator or integrator.
19. A 6-bit ADC has a maximum precision supply 21. A ±1 count error occurs in digital frequency
voltage of 20V. What are the voltage changes meter due to :
for each LSB present and voltage to be
presented by (100110), respectively? (a) Trigger level uncertainty
(a) 0.317 V and 12.06 V (b) Spurious interference
(b) 3.17 V and 12.06 V (c) Clock uncertainty
(c) 0.317 V and 1.206 V (d) Gate time uncertainty
(d) 3.17 V and 1.206 V IES-2015
IES-2016 Ans. (d) : Digital frequency is a instrument that display
Ans. (a) : Given that, the frequency of a periodic electrical signal to an
Supply voltage is 20V and 6 bit ADC output voltage accuracy of three decimal places. When a counter
when only LSB is present in resolution itself. makes a measurement, a ±1 count uncertainty can exist
in the least significant digit. This uncertainty can occur
20 because of the non-coherence between the internal
Vo = 6
2 −1 clock frequency and the gate time uncertainty.
20 The range of modern digital frequency meter is between
Vo = = 0.317
63 the 104 to 109 Hz.

1 Ans. (b) : Full scale voltage = 5V
22. A 4 digit voltmeter is used for measurements.
2 Accuracy = step size = 10 mV
It would display the voltage value 0.3861 on a full scale voltage
Step size =
10 V range as 2N − 1
N
(a) 0.3861 (b) 0.386 2 –1 = 5000/10 = 500
(c) 0.38 (d) 0.38610 2N = 501
IES-2013 N=9
1 26. The figure shows the circuit of a rectifier type
Ans. (b) : For 4 digital voltmeter, n = 4
2 voltmeter. The diode D2
1
Resolution = N × range of voltage
10
1 1
R= n = 4
10 10
Resolution on 10V range is
1
= 4 ×10 1. Does not allow any current to flow through the
10
meter during negative half cycle.
= 0.001V (means only 3 digit can displayed) 2. Does not allow reverse leakage current to flow
Hence, 0.3861 will be displayed as 0.386 on 10V range. through the meter during negative half cycle.
23. A-10 bit A/D converter is used to digitize an 3. Short circuits the meter during negative half
analog signal in the 0-5 V range. The maximum cycle.
peak to peak ripple voltage that can be allowed Which of these statements are correct?
in the dc supply voltage is nearly: (a) 1 and 2 only (b) 2 and 3 only
(a) 100 mV (b) 50 mV (c) 1 and 3 only (d) 1, 2 and 3 only
(c) 25 mV (d) 5 mV IES-2011
IES-2013, 2011 Ans. (c) :
No. of bit (n) = 10
Peak to peak voltage (Vpp) = 5V
Vpp
Peak to peak ripple voltage (Vpp)r = n
2 −1 When the A.C. input is applied, for the positive half
5 5 5 cycle, the diode D1 conduct and this causes the meter
= 10 = = = 4.88 mV deflection, which is proportional to the average value of
2 − 1 1024 − 1 1023 that half cycle. So during (+ve) half cycle D1 is ON and
5mV D2 is OFF, while (–ve) half cycle D2 is ON and D1 is
24. In a digital frequency meter, the Schmitt OFF. Hence when D2 is ON, it shorts the meter and
does not allow any current to flow through it.
trigger is used for
(a) converting sinusoidal waveforms into 27. A dual slope Analog to Digital converter
rectangular pulses 1. Responds very fast
(b) scaling of sinusoidal waveforms 2. Has better accuracy
(c) providing time base 3. Requires an accurate and stable dc source
(d) triggering a start pulse 4. Requires a buffer at the input side.
IES-2012, 2004 (a) 1 is not correct (b) 2 and 3 are correct
(c) 3 and 4 are correct (d) 1,2,3 and 4 are correct
Ans. (a) : In a digital frequency meter, the Schmitt
trigger is used for converting sinusoidal waveforms into IES-2011
rectangle pulses. Ans. (b) : A dual slope analog to digital converter has
A Schmitt trigger can be used as a comparator when it many advantage.
has no hysteresis to create clean digital pulses. • It is the most accurate ADC compare to all other.
25. The value of n for the n-bit A/D converter • Noise present on the input voltage is reduced by
required to convert an analog input in the averaging.
range of 0 to 5 volts to an accuracy of 10 mV is: • Component value variations will have no effect on
(a) 8 (b) 9 accuracy.
(c) 7 (d) 6 • High resolution can be achieved by using an
IES-2012 accurate count.

28. Which of the following devices is used at the Ans. (c) : Lux meters are used for the measurement of
first stage of an electronic voltmeter? illumination.
(a) BJT (b) SCR A lux is equal to the total intensity of light falls on the
(c) MOSFET (d) UJT surface of square meter area that is one foot away from
IES-2009 the point of source of light.
Ans. (c) : MOSFET is used at the first stage of an 33. Which one of the following is not true of digital
electronic voltmeter which provides high input instruments?
impedance to reduce loading effect. Typically of the (a) Loading of the circuit under measurement is
less
order of 1014 Ω .
(b) Accuracy is better
29. What is an advantage of an electronic (c) Free from observational errors
voltmeter over a non electronic voltmeter? (d) Can present the reading in overall context of
(a) Low power consumption range
(b) Low input impedance IES-2007
(c) The ability to measure wide ranges of Ans. (d) : Digital instrument cannot present the reading
voltages and resistance. in overall context of range.
(d) Large portability Advantage of digital instrument-
IES-2009 Highly accurate measurement
Ans. (a) : The main advantage of electronic voltmeter Energy consumption is very less
over non-electronic meter is that it draws a very small Numeric data representation format gives better
fraction of power from the circuit on which the readability
measurement is made. In other words, it offers very Better resolution
high input impedance due to this way they have high 34. What is a reading of 0.5245 on 1 V range in
sensitivity and low power consumption. They also have four and a half digit voltmeter displayed as?
wide range of frequency response. (a) 0.5245 (b) 00.524
30. An average response rectifier type electronic (c) 000.52 (d) 0000.5
voltmeter has a d.c. voltage of 10 V applied to IES-2006
it. What is the meter reading? 1
(a) 7.1 V (b) 10 V Ans. (a) : 4 Digit display have five digit with 1 half
2
(c) 11.1 V (d) 22.2 V digit (0 or 1) and 4 full digits.
IES-2009 The range of display will be from 0 to 19999.
Ans. (c) : Rectifier type instrument is calibrated to read
rms value for the sinusoidal waveform, it will be display
1.11 times of D.C. value
VDC = 10V
Then the meter reading VDisplay
VDisplay = 1.11 × VDC 1 1
Resolution = N
= 4 = 0.0001
= 10×1.11 10 10
= 11.1 V So resolution on 1V range = 1×0.0001 = 0.0001
31. In a digital voltmeter the oscillator frequency is So, for 1V range any reading displays to 4th decimal
400 kHz and the ramp voltage falls from 8 V to place.
0 V in 20 ms. What is the number of pulse So, 0.5245 displayed 0.5245 on 1V range.
counted by the counter? 35. In a digital voltmeter, input signal is integrated
(a) 800 (b) 2000 for a duration of 50 clock cycles. To eliminate
(c) 4000 (d) 8000 the effect of 100 Hz noise present in the signal,
IES-2009 what is the maximum clock frequency?
(a) 5 kHz (b) 50 kHz
Ans. (d) : f = 400 kHz
(c) 100 kHz (d) 250 kHz
N = Tw × f
IES-2004
The pulse width (Tw) of the ramp voltage
Ans. (a) : From the question, as given that-
given, TW = 20 ms
Number of clock cycle (T1) is 50 clock cycles and
N = 20 × 10−3 × 400 × 103 = 8000 fs= 100Hz
32. Illumination is measured using which one of 1
the following? So, T1 = nTs Ts =
fs
(a) Milli voltmeter (b) Stroboscope
1
(c) Luxmeter (d) pH meter 50 clock = n ×
IES-2008 f s

1
50 × Tclock = n ×
100
1 1
50 × = n×
f clock 100
100 × 50
f clock =
n
For maximum clock frequency, n = 1
100 × 50
fclock = = 5000 = 5kHz
1
correct?
(a) The power requirements of digital
instruments are considerably lower than that
of analog instruments.
(b) In analog instruments, the resolution limit is
one part is several hundreds, whereas digital (a) 1 V (b) 150 V
instruments can be made with a resolution of (c) 120 V (d) 147 V
one part in several thousands IES-2002
(c) Digital instruments are extremely portable Ans. (c) : When switch at position- B
and usually do not require an outside source
of supply for measurements
(d) Digital instruments indicate the readings
directly in decimal numbers and therefore
errors due to parallax and approximation, etc.
are eliminated
IES-2004
Ans. (c) : The digital instrument have following
important features-
The input impedance of digital instrument is very
high because of it can draws very less power.
The digital instrument is free from the parallax
error.
The digital instrument is less portable and it
requires a outside source for its operation.
So, option (c) is incorrect.
37. For the measurement of the voltage of the
order of mV, the voltmeter used is
(a) Rectifier-amplifier type VTVM 2 2
(b) Amplifier-rectifier type VTVM V1 = 12 × = 12 ×
6+2+2 10
(c) Diode peak reading voltmeter = 2.4V
(d) Slide wire VTVM When switch at position- D
IES-2003
Ans. (b) : Amplifier-rectifier type VTVM sensitivity is
limited to approximately 1 volt of full scale for the most
sensitive range. It is often desirable to measure much
smaller voltage and this can be done if the signal which
have to measured in first amplified and then rectified.
Amplifier rectifier type VTVM voltmeter is used to
measurement of voltage of the order of mV.
38. The figure shows input attenuator of a V × 0.2
multimeter. The meter reads full-scale with 12 V1 =
V at M with the range switch at position B. 2 + 7.8 + 0.2
What is the required voltage at M to obtain 2.4 = V × 0.2
full-scale deflection with the range switch 10
position at D? V = 120V
39. Consider the following statements in (a) 3, 1, 2 (b) 1, 2, 3
connection with measurement of frequency/ (c) 2, 3, 1 (d) 3, 2, 1
time interval using a digital frequency counter: IES-2001
1. Period measurements are preferred over Ans. (d) : A to D converters conversion time
frequency measurements at lower Counter type ADC → (2n – 1) Tclk
frequencies due to 'gating error' of ±1 Successive approx. time ADC → nTclk
count ambiguity.
Flash type ADC → 1 Tclk
2. The error in time-interval and period
(Flash type ADC is also known as simultaneous or
measurements due to trigger level
parallel type ADC.)
uncertainty can be reduced with large
signal amplitudes and fast rise times. Dual slop ADC → (2n+1)Tclk
3. Short-term frequency stability errors can Flash type > Counter type > Dual slope type
be minimized by taking frequency 1
42. A 3 digit voltmeter having a resolution of
measurements over long gate times. 2
4. Long-term frequency stability errors are 100 mV can be used to measure maximum
generally negligible since they tend to voltage of
average out (a) 100 V (b) 200 V
Which of these statements are correct? (c) 1000 V (d) 5000 V
(a) 1, 2 and 3 (b) 1, 3 and 4 OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
(c) 2, 3 and 4 (d) 1, 2 and 4 IES-1999
IES-2002 VFS
Ans. (a) : Resolution of DVM =
Ans. (a) : Given statement 1, 2 and 3 are correct and 10 N
statement 4 is not correct because of long term VFS = Full scale voltage
frequency stability not neglected.
N = Number of full digit
40. Match List-I (ADCs) with List-II
(Characteristics) and select the correct answer V
So, 100mV = FS3
using the codes given below the lists: 10
List-I List-II VFS = 100V
A. Parallel comparator 1. Null balancing
type 43. Which use of the following measuring
B. Successive 2. Fastest converter instruments would consume the lowest power
from the source during measurement?
approximation
(a) Permanent magnet moving coil
C. Dual-slope 3. Voltage
(b) Electronic millimeter
dependent
(c) Moving iron meter
conversion time
(d) All of the above
D. Counter-ramp 4. Integrating type
IES-1997
Codes:
Ans. (b) : The input impedance of electronic millimeter
A B C D
is very high because of it can draws very less power.
(a) 2 1 3 4
44. A diode peak reading VTVM and a
(b) 2 1 4 3
thermocouple meter are connected across the
(c) 1 2 4 3 output of an amplitude modulator circuit. In
(d) 1 2 3 4 the absence of modulation, both the meters
IES-2002 read 10 V. When a sinusoidal AM is applied,
Ans. (b) : the VTVM reads 15 V. The reading of the
Parallel comparator ADC – Fastest converter thermocouple meter in this case will, be
Successive approximation ADC – Null balancing type (a) 10 V (b) 12.5 V
Dual slope ADC – Integrating type (c) 14.1 V (d) 15 V
Counter-ramp ADC –Voltage dependent IES-1997
conversion time Ans. (a) : VTVM deflection proportional to the peak
value of applied voltage and thermocouple deflection
41. Digital measuring instruments use the proportional to rms value of applied voltage.
following three types of A to D converters:
For modulated wave
1. Dual Slope Type
E = EC (1+ma cos ωmt ) cos ωct
2. Counter Type
Thermocouple reads 10V, hence
3. Flash type
The correct sequence for these converters in Peak value = 10 2
decreasing order of their speed (fastest to When sinusoidal AM is applied the peak value is = EC
slowest) is (1+ ma)
So, 10 (1+ma) = 15 47. An average responding as voltmeter, employing
ma = 0.5 a full-wave precision rectifier has been
Now rms value of AM wave calibrated to given a reading of 1V for 1V rms
sinusoidal input. For 1V peak-to-peak square
EC m2 weave input, the meter reading will be
= 1+ c
2 2 π
(a) V (b) zero
10  (0.5) 2  4 2
=  1+  π
2  2 
 (c) V (d) π 2V
2 2
= 10.61
IES-1995
45. A digital displacement indicator based on a
Ans. (a) : As given, the scale calibrated in terms of the
linear voltage differential transformer (LVDT) rms value of a sine wave, then
transducer and A/D conversion used a LVDT
Vrms = Form factor × Vavg
with a sensitivity of 1 mV/mm. If the smallest
displacement to be measured is 0.1 mm and the For sine wave, form factor
maximum displacement of the LVDT core is 10 rms value of AC signal Vm / 2
= = = π/2 2
cm, then the digital display required for the Avg.value of AC signal 2Vm / π
instrument has to be
1
(a) 2 digit type (b) 2 digit type
2
1
(c) 3 digit type (d) 3 digit type
2
IES-1997
–4
Ans. (c) : Smallest resolution = 0.1 mm = 10 m
Maximum displacement = 10 cm = 10×10–2 m
As we know that,
Range = Count × Resolution As given, 2Vm = 1V
10×10–2 = Count × 10–4 Vm = V
1
Count = 1000 2
A 1000 count meter is 3 digit type. As we know that for square wave Vm = Vrms = Vavg
46. An average responding rectifier type electronic Then, Vrms = form factor × Vavg
ac voltmeter has its scale calibrated in terms of π 1
the rms value of a sine wave. If a square wave = ×
2 2 2
voltage of peak magnitude 100 V is measured
π
using this voltmeter, what will be the reading = V
indicated by the meter? 4 2
(a) 111 V (b) 100 V 48. A digital frequency counter can be converted to
(c) 90.09 V (d) 70.7 V a DVM by addition of a stage of suitable.
TANGENDCO-2015 (a) voltage controlled oscillator
IES-1996 (b) A/D converter to it
Ans. (a) : As given, the scale calibrated in terms of the (c) power amplifier to it
rms value of a sine wave, then (d) operational amplifier to it
IES-1995
Vrms = Form factor × Vavg
Ans. (b) : A digital frequency meter counts the number
For sine wave, form factor of pulse in a given time Tc to convert it into DVM. The
rms value of AC signal Vm / 2 test instruments which are associated with a wide range
= = = π/2 2 of ratio of frequencies and time of digital signals are
Avg.value AC signal 2Vm / π called frequency counters.
1.11 These are capable of measuring the frequency and time
So, Vrms = 1.11 × Vavg ……………..(i) of repeated digital signals accurately.
49. A voltage waveform shown in the given figure
Given Vm = 100V [for square wave] is applied to an ideal full wave rectifier
We know that for square wave = Vm = Vrms = Vavg voltmeter. The voltmeter is calibrated to read
the RMS values of sine waves. The voltmeter
Then, Vrms = 1.11×100 = 111 volts will read
Ans. (c) : Digital instruments are preferred than other
indicating instruments because digital instrument has
better resolution. Resolution is the number of parts that
the output or displayed reading from a measuring
instrument can be broken down into without any
instability in the reading.
1
Resolution = N
10
N = No. of full digits.
50 100 52. In a digital measuring device, if the input
(a) (b) V electrical signal is in the frequency range dc to
2 2
fmax Hz, then it must be sampled at a rate of
(c) 100 V (d) 111 V (a) fmax times/sec (b) fmax/2 time/sec
IES-1994 (c) every 2 fmax sec (d) 2 fmax times/sec.
Ans. (d) : As given, the scale calibrated in terms of the IES-1994
rms value of a sine wave, then
Ans. (d) : According to the Nyquist theorem, the
Vrms = Form factor × Vavg sampling rate must be at least 2fmax, or twice the highest
For sine wave, form factor analog frequency component. The sampling in an
analog to digital converter is actuated by a pulse
rms value of AC signal Vm / 2
= = = π/ 2 2 generator. The Nyquist theorem also known as the
Avg.value of AC signal 2Vm / π sampling theorem.
1.11 53. VTVM stands for
(a) Vacuum Tube Voltmeter
(b) Valve type Variable Meter
(c) Volt Temperature Virtual Meter
(d) Virtual Type Voltmeter
TSGENCO AE-2015
Ans. (a) : VTVM is stands for vacuum tube voltmeter.
The vacuum tube increase the sensitivity of voltmeter
because it can deflect the signal of very weak strength.
54. The sensitivity of a multimeter is given in
(a) Ω (b) kΩ/V
From the diagram 2Vm = 200V (c) Amperes (d) V/kΩ
Vm = 100V
Ans. (b) : The sensitivity of a multimeter is defined as
Vrms(reading) = 1.11 × Vm
1
= 1.11 × 100 Sdc =
= 111 Volt Idc
50. A peak-responding ac voltmeter employing a kΩ
half-wave precision rectifier has been Sdc =
V
calibrated to give a reading of 1V for 1V rms
sinusoidal input. For 1V dc input, the meter 55. Digital multimeter display is generally _______
reading will be digits.
(a) 0.707 V (b) 0.707 V or 0V (a) 3 1 2 (b) 2 1 3
(c) 1.414 V (d) 1.414 V or 0V (c) 1 3
2 (d) 1 3 2
IES-1994 TNPSC AE-2014
Ans. (a) : For square wave, rms Ans. (a) : 3 1 2 digit display– The number of digit
Value = average value = max value. positions in a digital meter determines the resolution.
As given that, Vm = 1V Hence, a 3-digit display on digital voltmeter for 0-1
V 1 range will indicates the values from 0-999 mV with a
So, Vrms = m = = 0.707 smallest increment of 1 mV. A fourth digit capable of
2 2 indicating 0 or 1 is placed to the left.
51. Digital instruments are preferred to other 56. A pulse waveform of 5 V peak and 25% duty
indicating instruments because of the following cycle is applied to a true rms responding
qualities: voltmeter. The reading will be:
(a) Narrow Bandwidth (b) better accuracy (a) 2.5V (b) 3.183 V
(c) better resolution (d) cost (c) 3.535 V (d) 5V
IES-1994 OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
Ans. (a) : Given, 60. To detect the small output voltage of LVDT
Peak voltage (Vs) = 5V which DVM is preferable.
Duty cycle ( α ) = 25% = 0.25 1
(a) 2 digit (b) 3 digit
2
rms load voltage = α × Vs = 0.25 × 5 = 2.5V
1
57. The sensitivity of a voltmeter using 0 to 5 mA (c) 3 digit (d) 4 digit
2
meter movement is:
BARC Scientific Officer-2016
(a) 200Ω/V (b) 1kΩ/V
Ans. (d) : The small out voltage of LVDT, DVM is
(c) 50 Ω/V (d) 100 Ω/V
preferable a 4-digit.
61. Tachymeter (or Tacheometer) is an instrument
Ans. (a) : Voltage sensitivity (Sv)
for measuring -
1 R + Rm (a) rpm
Sν = = s Ω/V
IFSD V (b) Torque
1 (c) Rotational kinetic energy
= = 200 Ω / V (d) Distances
5 ×10 –3
Note- To reduce loading effect, a voltmeter with higher
value of sensitivity is preferred. Ans. (a) : Tachymeter (or tacheometer) is an
instrument measuring the rotation speed of a shaft or
58. Which circuit fault do the meter readings in the disc in rpm it is used to measure rpm of motor or other
given figure indicate?
machines.
62. Sensitive low voltage electronic components are
protected from -
(a) Static charge (b) Induction circuit
(c) Lightening (d) All of these
Ans. (d) : Sensitive low voltage electronic components
should be protected from static charge, induction circuit
(a) The 1 k resistor is shorted. and also from lightning, so that’s why all option are
(b) The 4.7 k resistor is shorted. correct.
(c) The 2.2 k resistor is shorted. 63. Integrating principle in the digital
(d) The 3.3 k resistor is shorted. measurement is the conversion of
Nagaland PSC CTSE (Diploma)-2018, Paper-I (a) Voltage to time
Ans. (d) : (b) Voltage to frequency
(c) Voltage to current
(d) Current to voltage
Ans. (b) : Integrating principle in the digital
measurement is the conversion of voltage to frequency.
64. Digital voltmeter converts __________.
(a) Resistance to voltage
When 3.3 kΩ will short circuited, VB = 0 (b) Analog to digital signal
(c) Current to voltage
VA = VB = 0
(d) Digital to analog signal
Hence V1 ≠ 0 Vi will provide some reading. RRB JE- 31.08.2019, 10 AM-12 PM
59. An advantage which a VTVM has over a non- Ans. (b) : Digital voltmeter is generally known as
electronic voltmeter DVM. It converts analog signal to digital signal. It is
(a) Low power consumption versatile and accurate voltmeter. It is used in laboratory.
(b) Low input impedance 65. Out of an ammeter, a milli ammeter, a
(c) The ability to measure wider ranges of voltmeter and a milli voltmeter, which pair of
voltage and resistance the instruments have maximum and minimum
(d) Greater probability resistance respectively?
Nagaland PSC CTSE (Degree)-2018, Paper-I (a) Voltmeter; Milli ammeter
Ans. (a) : The main advantage of VTVM over non- (b) Voltmeter; Ammeter
electronic meter is that VTVM has high I/P impedance (c) Milli voltmeter; Ammeter
due to this reason it draws a very small fraction of (d) Milli voltmeter; Milli ammeter
power from the circuit on which measurement is made. RRB SSE 03.09.2015 Shift-II
Ans. (d) : The pair of the instrument have maximum Ans. (c) : Majority of digital voltmeter are quit with a
and minimum resistance respectively millivoltmeter and dual slope ADC because dual slop ADC can be
milli ammeter designed to be insensitive to noise the interference.
Millivoltmeter resistance > voltmeter resistance 71. Choose the correct statement
Milli ammeter resistance < ammeter resistance (a) Digital multimeters are built using current
66. Electronic voltmeter provides more accurate measuring elements, while analog
reading in high resistance circuit as compared multimeters are built using voltage
to non - electronic voltmeter because : measuring units
(a) High V/Ohm rating (b) High Ohm/V rating (b) Digital multimeters are built using voltage
(c) Low meter resistance (d) High resolution measuring units, while analog multimeters are
built using current measuring units
(c) Both digital and analog multimeters are built
Ans. (b) : Electronic voltmeter provides more accurate using voltage measuring units
reading in high resistance circuit as compared to non-
(d) Both digital and analog multimeters are built
electronic voltmeter because high ohm/V rating. using current measuring units
67. An average response rectifier type electronic BSNL (JTO)-2006
AC Voltmeter has DC voltage of 10 V applied
Ans. (b) : Digital multimeters are built using voltage
to it. The meter reading is :
measuring units, while analog multimeters are built
(a) 7.1 V (b) 10 V using current measuring units
(c) 22.2 V (d) 11.1 V
72. Which of the following devices id used at the
first stage on an electronic voltmeter?
Ans. (d) : meter reading = form factor × 10 (a) BJT (b) SCR
V0 = 11.1 Volt (c) MOSFET (d) UJT
68. In a digital voltmeter, the oscillator frequency
is 400 kHz and the ramp voltage falls from 8V Ans. (c) : MOSFET is used because of having high i/p
to 0 V in 20 msec. The number of pulses impedance.
counted by counter is :
(a) 800 (b) 2000 (vii) Cathode Ray Oscilloscope
(c) 4000 (d) 8000
OPSC Poly. Lect. (Instrumentation)-2018, Paper-II 1. Lissajous pattern can be used to determine
(a) voltage amplitude (b) amplitude distortion
Pulse width
Ans. (d) : Number of Pulse = (c) voltage gain (d) phase shift
Time Period UPPSC ITI Principal/Asstt. Director-09.01.2022
T ω = 20 ms Nagaland PSC CTSE (Degree)-2018, Paper-I
Ans. (d) : Lissajous pattern can be used to determine
20 ×10−3
N= = 8000 phase shift. A lissajous figure is displayed on the screen
1 when sinusoidal signals are applied to both horizontal
400 × 103 and vertical deflection plates of CRO. It is used to
N = 8000 measure frequency and φ difference.
2. Trigger pulses in CRO are used-
69. In a dual-slope type digital voltmeter, an
unknown signal voltage is integrated over 100 (a) to generate high voltage required for CRT
cycles of the clock. If the signal is 50 Hz, the (b) to synchronize the input with the time base
maximum clock frequency is : generator
(a) 50 Hz (b) 5 kHz (c) to synchronize the input and vertical amplifier
(c) 10 kHz (d) 50 kHz (d) to generate low voltage required for the CRT
OPSC Poly. Lect. (Instrumentation)-2018, Paper-II UPPSC Poly. Tech. Lect.-22.03.2022, Paper-I
Ans. (b) : FCLK = No. of cycle × Fsig. Ans. (b) : Trigger pulses in CRO are used to
FCLK = 100 × 50 = 5,000 synchronize the input with the time base generator.
3. A vertical amplifier of CRO is set at a
FCLK = 5kHz sensitivity of 0.5 V/cm. A sine wave voltage is
70. Majority of digital voltmeter are built with a connected to the Y-input. A straight line trace
dual - slope ADC because : of length 5.6 cm is obtained. Then rms value of
(a) Dual - slope ADC is less complex voltage is-
(a) 0.099V (b) 0.99V
(b) Dual-slope ADC is faster
(c) 9.9V (d) 0.0099V
(c) Dual -slope ADC can be designed to be
insensitive to noise and interference UPPSC Poly. Tech. Lect.-22.03.2022, Paper-I
(d) Dual-slope ADC provide BCD output Ans. (b) : Sensitivity = 0.5V / cm
OPSC Poly. Lect. (Instrumentation)-2018, Paper-II Straight line trace of length = 5.6 cm
VP − P = 0.5 × 5.6 = 2.8V 7. The input impedance of a CRO is nearly:
VP = 1.4V (a) Zero (b) 100 Ω
Vrms = 1.4×0.707 = 0.99 V (c) 1 kΩ (d) 1 MΩ
Mizoram PSC AE/SDO-2012, Paper-I
4. What is the displayed rise time (approximately) OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
when a pulse waveform with a rise time of 21 KVS TGT (WE)-2018, IES-1992
ns is applied to an oscilloscope that has an
upper cutoff frequency of50MHz? Ans. (d) :Practically input impedance of the cathode ray
oscilloscoped (CRO) has a range of megaohm
(a) 18 ns (b) 22 ns Practically input capacitance of the cathode ray
(c) 32 ns (d) 28 ns oscilloscope (CRO) has a range of pico farad (pF) Input
ESE-2022 impedance, input capacitance, gain, bandwidth
Ans. (b) : Given, product & rise time all terms are all associated with a
Rise time (tr) = 21 ns vertical amplifier of CRO
1 8. The time base signal in a CRO is
So, frequency(f) = (a) a sinusoidal signal
21× 10−9
= 47.62 MHz (b) square wave signal
(c) saw tooth signal
50 MHz (upper cut-off frequency oscilloscope)>47.62
(d) triangular wave signal
MHz
Upto nearly 21 nsec 22n sec can be displayed.
5. With testing is possible to see even UKPSC Assistant Radio Officer Screening Exam.-2011
smallest distortions clearly on CRO. Ans. (c) : CRO is a very fast X-Y plotter that shows the
(a) triangular wave (b) sine wave input signal versus another signal versus time. It
(c) square wave (d) sawtooth wavegenerate an output voltage which varies linearly with
time. The time base signal in CRO is a sawtooth signal.
Ans. (c) : Square wave testing is possible to see even
9. The trace on an Oscilloscope Continually
smallest distortions clearly on CRO. moves to the right of the screen when
6. The waveform shown in the given figure is (a) the sweep is triggered.
observed on the screen of an oscilloscope. If the (b) the sweep period is larger than the signal
vertical attenuation is set to 2.5V/div, period
determine the maximum amplitude of the (c) the sweep period is smaller than the signal
period
signal.
(d) there is no sweep.
KVS TGT (WE)-2018
BSNL (JTO)-2006
Ans. (c) : The trace on an oscilloscope continually
moves to the right of the screen the sweep period is
smaller than the signal period.
10. The lissajous pattern appearing on the screen
of a CRT, when two sinusoidal voltages of
equal frequencies, which are in phase with each
other are applied to the CRO is
(a) 3.75V (b) 5V (a) A straight line (b) a circle
(c) 7.5V (d) 10V (c) an ellipse (d) a parabola
APPSC Poly. Lect. 15.03.2020 KVS TGT (WE)-2018
Ans. (a) : Mizoram PSC AE/SDO 2012-Paper-I
Ans. (a) : Lissajous pattern with equal frequency
voltage and zero phase difference the Lissajous figure
will be straight line. If phase difference is 90º, pattern
will be circle.
11. High frequency (in the MHz range) and low
amplitude (in the mV range) signals are best
measured using
(a) VTVM with a high impedance probe
(b) CRO
(c) moving-iron instrument
(d) digital multimeter
Q 1 div = 2.5 Nagaland PSC CTSE (Degree) -2015, Paper I
∴ 1.5 div = 1.5 × 2.5 = 3.75 IES-2017
Ans. (b) : High frequency (in MHz range) and low 15. A delay line is used in high speed CRO to
amplitude (in mV range) signals are best measured introduce time delay in
using CRO. CRO is suitable for the measurement of 10 (a) vertical channel (b) horizontal channel
mV at 50 MHz. CRO is a very versatile instrument in (c) z axis of the CRT (d) all of the above
the laboratory for measurement of voltage, current, Mizoram PSC AE/SDO 2012-Paper-I
frequency and phase angle of any electrical quantity. Ans. (a) : A delay line is placed between output of
12. A pulse signal having 100 kHz frequency and vertical amplifier and y input of cathode ray tube, to
70 nsec rise time is to be measured on an delay incomming unknown signal.
oscilloscopse. The minimum required
16. The Y plates of a CRO are excited by a voltage
bandwidth of the oscilloscope is,
2sin (100t) and X plates are not connected. The
(a) 500 kHz (b) 14.3 MHz display would be
(c) 5 MHz (d) 200 kHz (a) a vertical line (b) a horizontal line
ISRO Scientist Engg.-2013 (c) a sine wave (d) a slanting line
Ans. (c) : We know that, Mizoram PSC AE/SDO 2012-Paper-I
t r × BW = 0.35 Ans. (a) : When the horizontal input is zero and hence
Given , the output will a vertical line. For zero vertical input,
t r = 70 × 10−9 sec the output will horizontal line.
0.35 17. The Lissajous pattern obtained on a CRO is
BW = used to determine
70 × 10−9 (a) amplitude of applied signal
35 × 106 (b) current in a circuit
=
7 (c) phase shift and frequency
BW = 5 MHz (d) distortion in a system
13. How could Schrodinger's equation be relevant Nagaland PSC CTSE (Degree)- 2016, Paper-I
in the practical design of a Cathode-Ray Tube? TNPSC AE-2013
(a) To optimize the colour quality Ans. (c) : The Lissajous pattern obtained on a CRO is
(b) To optimize the picture sharpness used to determine phase shift and frequency. Lissajous
(c) It is not relevant, because the CRT contains pattern also provide the amplitude information.
no crystalline lattice structure 18. The horizontal sweep speed is set so that a full
(d) Its effects are negligible, as the electron cycle takes 0.4 m/sec. The resulting display for
wavelength is very small compared to the one sweep of beam will be
spot size (a) two cycles of the input signal
ISRO Scientist Engg.-2010 (b) one cycle of the input signal
Ans. (b) : To optimize the picture sharpness. (c) half cycle of the input signal
14. Deflection sensitivity of CRO is ............. (d) one-fourth cycle of the input signal
distance between the deflecting plate and TNPSC AE-2008
screen Ans. (a) : The horizontal sweep speed is set so that a
(a) directly proportional to full cycle take 0.4 m/sec. The resulting display for one
(b) inversely proportional to sweep of beam will be two cycle of the input signal.
(c) does not depend on 19. Which of the following statements about CRO
(d) none of these is correct?
Mizoram PSC AE/SDO 2012-Paper-I (a) The lissajous pattern obtained in a CRO is
D used to measure distortion in the input signal
Ans. (a) : Deflection Sensitivity of CRO, S = (b) The colour of the spot on the screen of a CRO
Ed
is a characteristic of the electron gun in a
L ⋅ ld ⋅ E d CRT
D=
2d ⋅ Ea (c) The time base signal in a CRO is a square
ld = Length of deflecting plates (in m) waveform
(d) None of these
L = Distance between screen and the centre of the
deflecting plates (in m) TNPSC AE-2008
D = Deflection of electron beam on the screen in Y- Ans. (d) : Lissajous pattern are used for the
direction. measurement of frequency and phase difference. It is
d = distance between deflecting plates used with the help of CRO.
Ea = Voltage of Pre-accelerating anode 20. For accurate measurement of voltage the most
hence, suitable equipment
(a) Analog Voltmeter (b) Digital Voltmeter
D L × ld
S= = (m / V) (c) CRO (d) None of these
E d 2d ⋅ Ea
Ans. (c) : CRO cathode ray oscilloscope is a measuring 25. If retrace is visible on the CRT screen, the
instrument in laboratory. The graph voltage is measure trouble may be that
by using CRO. (a) There is a loss of SYNC signal
21. The bandwidth of a CRO is from 0-20 MHz. (b) Blanking control is not set properly
The fastest rise time for a sine wave which can (c) Sweep signal is too lengthy
be reproduced accurately by the instrument is (d) All of these
(a) 35 micro seconds Nagaland PSC CTSE (Degree) -2015, Paper I
(b) 0.175 micro seconds
(c) 35 nano seconds Ans. (d) : The trace in a CRO is performed by the
sweeping of electrons for a small period of time on the
(d) 17.5 nano seconds
phosphorus screen by the voltage generated due to the
signal. This voltage is known as sweep voltage.
IES - 2000
When the sweep is completed the voltage
Ans. (d) : Band width = 20 MHz returns to its original value and thus forcing the beam of
0.35 electrons to move back. This process is called retrace.
Rise time is =
B.W This blanking control is not set property, then
0.35 the retrace is visible on CRO screen.
= = 17.5 nano second
20 × 106 26. The sweep width in a CRO is controlled by
22. CRO works in (a) Horizontal gain control
(a) Frequency domain (b) Time domain (b) Vertical gain control
(c) Digital domain (d) None of these (c) Accelerating -anode potential control
MPPSC Forest Service Exam.-2014 (d) Focusing-anode potential control
Ans. (b) : CRO stands for a cathode ray oscilloscope. It Nagaland PSC CTSE (Degree) -2015, Paper I
is typically divided into four sections which are display,
Ans. (a) : The time base (sweep or ramp) generator
vertical controller horizontal controller and trigger.
produces a saw - tooth wave of the same frequency as
CRO work in time domain.
the input signal to the Y-plates. The sweep width in a
23. The input attenuator in the vertical amplifier CRO is controlled by horizontal gain control.
of a general purpose CRO is generally followed
by a FET followed by the emitter -follower on 27. Sampling oscilloscope are specially designed to
cathode follower circuit which measure
(a) Acts as an impedance transformer (a) Very low frequency
(b) Acts as an isolating element (b) Very high frequency
(c) Connects low impedance attenuator output to (c) Microwave frequency
high impedance paraphrase amplifier (d) None of these
(d) Amplifies the input signal to the required Nagaland PSC CTSE (Degree)-2017, Paper-I
value Ans. (b) : It can be used for continuous display for
Nagaland PSC CTSE (Degree) -2015, Paper I frequencies in the range of 50 - 300 MHz. The sampling
Ans. (a) : The input attenuator in the vertical amplifier oscilloscopes can be used beyond 50 MHz into the UHF
of a general purpose CRO is generally followed by a around 500 MHz and beyond up to 10 GHz.
FET followed by the emitter follower on cathode
follower circuit which acts as an impedance 28. The length of time that a beam excites a certain
transformer. area of the phosphor of the CRO screen can be
adjusted with the control marked
24. AQUADAG is a
(a) Non-conductive coating on the screen of a (a) Vertical position (b) Horizontal position
CRT to collect the high velocity electrons (c) Time/div (d) Sweep
(b) Non-conductive coating on the screen of a Nagaland PSC CTSE (Diploma)-2018, Paper-I
CRT to collect the secondary-emission Ans. (d) : Horizontal sweep selects sweep rate from
electrons calibrated steps or admit external signal to horizontal
(c) Conductive coating on the screen on a CRT to amplifier.
collect the low-velocity electrons 29. The magnitude of the beam current in a CRT
(d) None of these can be adjusted by a front panel control
Nagaland PSC CTSE (Degree) -2015, Paper I marked
Ans. (c) : AQUADAG- (a) Time/Div (b) Focus
• The bombarding electrons striking the screen, (c) Astigmatism (d) Intensity
release secondary emission electrons. Nagaland PSC CTSE (Degree)- 2016, Paper-I
• These secondary electrons are collected by an Ans. (d) : The magnitude of the beam current in a CRT
aqueous solution of graphite called Aquadag. can be adjusted by a front panel control marked
• It is the conductive coating on the screen. intensity.
30. What will be seen on the screen of a CRO,
Ll V
when a sinusoidal voltage signal is applied to D= d d
the vertical deflection plate of this CRO with 2d Va
no simultaneous signal applied to the 2 × d Va D
horizontal deflection plate? Vd =
(a) A horizontal line Ll d
(b) A vertical line 2 × 0.5 × 3 × 1000
Vd =
(c) A sinusoidal signal 1 × 30
(d) A spot at the centre of the screen Vd = 100V
IES-2018 32. For displaying high frequency signals cathode
Ans. (b) : When a sinusoidal voltage signal is applied to the ray tube should have
vertical deflection plate of this CRO with no simultaneous (a) High persistence
signal applied to the horizontal deflection plate then a (b) Focusing system
vertical line will be seen on the screen of a CRO. (c) Very high input impedance
Let x = 0 and y = Vmsin ωt (d) Provision for post deflection acceleration
Case - 1 at t = 0 IES-2015
i.e. x = 0 , y = 0 Ans. (d) : For displaying high frequency signals
Case-2 at t = T/4 cathode ray tube should have provision for post
deflection acceleration as for high frequency signal we
need that the moving electron beam should have high
energy and thus we must have post deflection
acceleration.
33. A sinusoidal waveform has peak-peak
amplitude of 6 cm viewed on a CRO screen.
The vertical sensitivity is set to 5V/cm. The
2π T π RMS value of the signal is
x = 0, y = Vm sin × = Vm sin = Vm
T 4 2 (a) 15 V (b) 12.6 V
i.e. x = 0, y = Vm (c) 21.2 V (d) 10.6 V
Case-3 at t = T/2 IES-2015
2π T Ans. (d) : Given that,
x = 0 , y = Vmsin × = Vm sin π = 0
T 2 Vertical sensitivity = 5V/cm.
i.e. x = 0, y = 0 Peak to peak amplitude = 6 cm.
Case-4 at t = T Peak to peak voltage = 5V/cm × 6 cm = 30 V.
2π V 30
x = 0, y = Vm sin × T = Vm sin 2π = 0 Vm = P − P = = 15V
T 2 2
i.e. x = 0, y = 0 V 15
RMS value (Vrms) = m = = 10.6 Volt
2 2
34. Example of an active display and a passive
display respectively are:
(a) LCD and Gas discharge plasma
(b) LED and LCD
(c) Gas discharge plasma and LED
We can observe from these four cases, that the point (d) Electrophoretic Image display and LED
moves only on vertical direction. IES-2015
31. An input voltage required to deflect a beam Ans. (b) : Electronic visual display is classified into
through 3 cm in a Cathode Ray Tube having an three types-
anode voltage of 1000 V and parallel deflecting (1) Analog or digital
plates 1 cm long and 0.5 cm apart, when screen (2) Active display
is 30 cm from the centre of the plates is
(3) Passive display
(a) 300 V (b) 200 V
Active Display- If visual information is presented by
(c) 100 V (d) 75 V
emitting light then that is called active display.
IES-2016
Example- CRT, LED's, VFD, SED etc.
Ans. (c) : D = 3cm, Va = 1000 V, ld = 1cm, Passive Display- If the visual information is presented
d = 0.5 cm, L = 30 cm by modulating lights then that is called passive display.
We know that deflection of CRO Example- LCD, digital micromirror device etc.

35. Lissajous pattern shown in double-beam (a) 1 and 2 only (b) 2 only
cathode-ray oscilloscope screen for two (c) 3 only (d) 4 only
sinusoidal voltages of equal magnitude and of Nagaland PSC CTSE (Degree)-2018, Paper-I
the same frequency but of phase shift of 30º AAI-2015, IES-2008
electrical is
Ans. (b) : Probe compensation is the process where by
(a) a circle the probe capacitance is adjusted to compensate for the
(b) a straight at 45º in the first and third quadrant effect of the internal input capacitance of the scope. The
(c) an ellipse in the first and third quadrant compensated probe of a CRO contains RC network. In
(d) an ellipse in the second and fourth quadrant. which a variable capacitors is used to tune the probes
IES-2012 cable.
Ans. (c) : Lissajous pattern shown in double beam CRO 39. Which one of the following measuring devices
screen for two sinusoidal voltages of equal magnitude has minimum loading effect on the quantity
and of the same frequency but of phase shift of 30° under measurement?
electrical will be an ellipse in the first and third (a) PMMC (b) CRO
quadrant. When φ is less than 90 (0 < φ < 90°) the (c) Hot wire (d) Electrodynamometer
Lissajous pattern is of the shape of an ellipse having a IES-2007
major axis passing through the origin from first
Ans. (b) : When an instrument of lower sensitivity is
quadrant to the third quadrant.
used with a heavier load the measurement it makes
For φ = 30° or 330° Lissajous pattern. incorrect, this effect is known as the loading effect.
CRO has minimum loading effect on the quantity under
measurement, because the input impedance of CRO is
very high. Input impedance of CRO is approx 1 MΩ.
40. A circle is found on the screen of CRO when 2
time varying signals of same frequency and
36. When a sinusoidal signal of 220 V, 50 Hz same magnitude are applied to X and Y plates
produces on CRO a vertical deflection of 2 cm of the CRO. What is the relative phase
at a particular setting of the vertical gain difference?
control, what would be the value of the voltage (a) 0º (b) 90º
to be applied to produce a deflection of 3 cm (c) 180º (d) 45º
for the same vertical gain? IES-2016, 2007,2001
(a) 330 V (b) 110 V Ans. (b) : The pattern indicated by CRO is a
(c) 220 V (d) 55 V clockwise rotating circle when phase shift of φ = 90°.
IES-2011 When two sinusoidal signals of same frequency and
Ans. (a) : Given- magnitude are applied two both pairs of deflecting
For 2 cm deflection required value of voltage = 220V plates of CRO, the lissajous pattern changes with
220 change of phase difference between signals applied to
For 1 cm deflection = = 110 the CRO.
2
Phase angle (φ) Lissajous Pattern
220
So, 3 cm deflection = ×3 0º or 360º
2
= 330 V
37. A 1000 Hz sinusoidal voltage is connected to
both X and Y inputs of a CRO. Which of the
following waveforms is seen on CRO? 0 º < φ < 90 º
(a) Sine wave (b) Circle (or)
(c) Ellipse (d) Straight line 270º < φ < 360º
IES-2011
φ = 90º or 270º
Ans. (d) : When φ = 00 or 3600, a straight line results
when two voltage are equal and a straight line formed
with an angle of 450 in 1st and 3rd quadrant.
90º < φ < 180º
38. A compensated probe of a CRO contains which
of the following? or
1. An amplifier 180º < φ < 270º
2. R-C network
3. Only resistive network φ = 180º
4. Only capacitive network
below:
41. Which of the following A/D converter is used in (c) cannot couple high frequency signals
a Digital Storage Oscilloscope (DSO)? (d) can attenuate more
(a) Ramp type IES-2006
(b) Successive approximation type Ans. (a) : Active probes are designed to provide an
(c) Dual slope type efficient method of coupling high frequency, fast rise
(d) Parallel type time signals to the CRO input. Usually active probes
IES-2007 have very high input impedance with less attenuation
Ans. (b) : Successive approximation type A/D than passive probe. Active probe used in a CRO is
converter is used in a digital storage oscilloscope. bulkier than passive ones.
Digital storage oscilloscope is an oscilloscope which 46. For measurement of modulation factor by a
stores and analysis the input signal digitally rather than CRO, a trapezoidal pattern is obtained on the
using analog technique. CRO screen, as shown in figure given above.
42. It is desired to make accurate measurement of What is the value of the modulation factor 'M'?
voltage using a CRO. Which of the following
items should be taken into consideration in this
measurement?
1. Electrostatic deflection type CRT
2. Magnetic deflection type CRT
3. Small deflection for measurement at the
centre of the screen.
4. Large deflection to cover the entire screen.
below: (A) CRO connection circuit
(a) 1 and 4 (b) 2 and 3 (B) a trapezoidal pattern on CRO screen
(c) 2 and 4 (d) 1 and 3 (a) 0 (b) 0.5
IES-2007 (c) 0.75 (d) 1
Ans. (a) : In CRO, electrostatic deflection type CRT is used IES-2005
and not magnetic deflection type. Also a large deflection has Ans. (d) : For a trapezoidal pattern, on CRO screen-
to be provided so that entire screen can be covered. A − A min
Modulation factor (M) = max
43. A certain oscilloscope with 4 cm × 4 cm screen A max + A min
has its own sweep output fed to its input. If the
X and Y sensitivities are same, what will the
oscilloscope display?
(a) Triangular wave (b) Straight line
(c) Sine wave (d) Circle According to question Amin=0
IES-2006, 2002
A −0
Ans. (b) : Sensitivities of both are same means approx Q Modulation factor (M) = max =1
same voltage are applied on both plate. So, pattern will A max + 0
be straight line. 47. Voltages Vy = 100 sin 1000t and VX = 50 sin
44. The sine wave output of a function generator is 1000t are connected to Y and X terminals of
fed to both the horizontal (X) and vertical (Y) CRO, respectively. What is the shape of the
inputs of a CRO. What will be the pattern on figure seen on the CRO?
the cathode ray screen? (a) A circle (b) A straight line
(a) circle (c) An ellipse (d) A parabola
(b) An ellipse IES-2005
(c) A straight line with 45º slope Ans. (b) : Voltage-
(d) Sinusoidal Vy = 100 sin 1000t
IES-2006 Vx = 50 sin 1000t
Ans. (c) : When two sinusoidal signals of the same If the frequency of the both signals are same and the
frequency and magnitude are applied both pairs of phase difference between both signals are zero then the
deflecting plates of CRO, then cathode ray screen will shape of the figure will be a straight line.
show and straight line with 450 slope on the screen. The as Vy > Vx the output waveform will be a straight line
Lissajous pattern changes with the change of phase with shape > 1.
difference between signals applied to the CRO. 48. Which one of the following instruments is most
45. Which one of the following is the correct suitable to study the behaviour of a damped
statement? transient around 10 kHz?
Active probe used in a CRO (a) Double beam CRO (b) Recorder
(a) is bulkier than passive ones (c) Storage Oscilloscope (d) Plotter
(b) cannot measure small signals IES-2005
Ans. (b) : Recorders are used to study the behaviour of 52. A dual-trace CRO has
a damped transient around 10 KHz. (a) one electron gun
49. The x-input and y-input to a CRO are, (b) two electron guns
5 cos ( ωt + φ) and 5sin ( ωt + φ ) respectively. (c) one electron gun and one two-pole switch
(d) two electron guns and one two-pole switch
What will be the resulting Lissajous pattern? RPCS Lect.-2011, IES-1999
(a) A straight line inclined to an angle φ
Ans. (c) : A dual trace CRO has a single electron gun
(b) An ellipse with an inclined major axis whose electron beam is splited into two by an electronic
(c) A circle switch. There is one control for focus and another for
(d) A horizontal line intensity. It has one electron gun with one two pole
IES-2004, 2003 switch.
Ans. (c) : Vx = 5 cos ( ωt + φ) = 5 sin [( ωt + φ )+90] 53. Two sinusoidal signals having the same
Vy = 5 sin ( ωt + φ) when phase difference between both amplitude and frequency are applied to the X
signals is 90° then the pattern shown on the lissajous and Y inputs of a CRO. The observed Lissajous
pattern will be a circle. figure is a straight line. The phase shift
between the two signals would be.
50. A sinusoidal signal of frequency 2 kHz is
(a) Zero
applied to the x-deflection plates and a saw-
tooth of frequency 1 kHz is applied to the y- (b) 90 degrees
deflection plates of a C.R.O. The waveform (c) Either zero or 180 degrees
display on the screen will be (d) Either 90 degrees or 270 degrees
IES-1998
Ans. (c) : Two sinusoidal signals having the same
(a) (b) amplitude and frequency are applied to the X and Y
inputs of a CRO. The observed Lissajous figure is a
straight line. The phase shift between the two signals
would be either zero or 180°.
54. The input impedance of a CRO is 1M ohm in
parallel with 10 pF. If the CRO is required to
(c) (d)
display pulse using a 10:1 attenuator, the
attenuator will have to use a
(a) 9 M ohm resistor
(b) 1.11 pF capacitor
IES-2002 (c) Parallel combination of 9 M ohm resistor and
Ans. (a) : A sinusoidal signal of frequency 2 kHz is 1.11 pF capacitor
applied to the X plate (d) Series combination of 9 M ohm resistor and
A sawtooth signal of frequency 1 kHz is applied to the 1.11 pF capacitor.
Y plate IES-1997
Sine wave complete two cycles in time period of single Ans. (c) : Given input impedance
cycle of sawtooth signal so graph a will be correct. Ri = 1 MΩ.
51. A d.c. voltage of 1 V is applied to the X-plates Input capacitance
of a CRO and an a.c. voltage 2 sin 100t is Ci = 10 pF.
applied to the Y-plates. The resulting display For a 10 : 1 attenuator–
on the CRO screen will be a Ri
(a) vertical straight line Vi = V
Ri + Rp
(b) horizontal straight line
(c) sine wave V Ri
= V.
(d) Slant line 10 Ri + R p
RPSC Vice Principal ITI - 2016 Ri + Rp = 10 Ri
IES-2000 9 Ri = Rp
Ans. (a) : R p = 9MΩ
also, Ri Ci = RpCp
1×106×10×10–12 = 9×106×Cp
Cp = 1.11 pF
On the x-plates of CRO a DC voltage of 1V is applied

and AC voltage of 2 sin 100t is applied to the y-plates.
The resulting display on the CRO screen will be a
vertical straight line.
55. A dual trace oscilloscope usually offers two Ans. (a) : In CRT aquadag carries aqueous solution of
modes, chop and alternate. graphite. Aquadag coating is used to collect the secondary
The alternate mode can be used for displaying. electron emitted when the electron strikes the screen.
(a) any two waveforms 59. A signal of 10 mV at 75 MHz is to be measured.
(b) two waveforms of relatively high frequency Which of the following instrument can be used?
(c) two waveforms of relatively low frequency (a) VTVM
(d) one low frequency and one high frequency (b) Cathode ray oscilloscope
waveform
(c) moving iron voltmeter
Nagaland PSC CTSE (Diploma) - 2017 (Paper-I)
(d) digital multimeter
IES-1996
IES-1992
Ans. (b) : In dual trace oscilloscope, a single electron
beam generates two traces, that undergoes deflection by Ans. (b) : CRO- Cathode ray oscilloscope is a device
two independent sources. In order to produce two that convert electrical signals into an active graphical
separate traces, basically, two method are used, known representation on screen. Standard screen size is 8 × 10
as alternate and chopped mode. These are also known as cm. The screen is coated with a phosphor that emitt
two operating modes of the switch. light when struck by the electron beam. CRO is measure
56. The Lissajous pattern observed on the screen to the voltage, current, frequency, phase angle.
of a CRO is a straight line inclined at an angle 60. A pulse waveform with a 3.3 kΩ source
of 45º to the x-axis. If the voltage applied to the resistance is to be displayed on an oscilloscope
x-plate is 2 sin ωt, then the voltage applied to with an input capacitance of 15 pF. The rise
the Y-plates will be time of the pulse shown on the scope is
(a) 2 sin ωt (b) 2 sin ( ωt + 45º) measured as
(c) 2 sin ( ωt – 45º) (d) 2 2 sin(ωt + 45º ) (a) 49.5 ns (b) 54.45 ns
(c) 113.85 ns (d) 109.0 ns
IES-1994
TSGENCO AE-2015
Ans. (a) : If the lissajous pattern observed on the screen
of a CRO is a straight line inclined at angle of 45° to the Ans. (a) : Rise time = RC
x-axis and applied voltage on the x-axis is 2 sin ωt, then = 3.3 × 15 × 10–9
the applied voltage to the Y-plates will be 2 sin ωt. As t r = 49.5 ns
for phase difference (φ) of 0° and 360° Lissajous pattern
on CRO will be a straight line inclined at angle of 45°. 61. Deflection sensitivity of a CRO is expressed in
terms of
57. An oscilloscope has an input impedance
(a) V/cm (b) cm/V
consisting of 1 MΩ and 20 pF in parallel. A
high impedance probe connected to the input of (c) V/cm2 (d) V.cm
this oscilloscope has a 10 MΩ series resistance. TSGENCO AE-2015
This 10 MΩ resistance. Ans. (b) : Deflection sensitivity of a CRO is expressed
(a) need not he shunted in terms of cm/V. Unit of deflection factor is v/m.
(b) should be shunted by a 2 pF capacitor 1
(c) should be shunted by a 20 pF capacitor Deflection factor =
deflection sensitivity
(d) should be shunted by a 200 pF capacitor.
IES-1994 62.
For the Gaussian response, the rise time (tr)
and bandwidth (BW) are related by
Ans. (b) : Given–
(a) tr = 0.35/BW (b) tr = 0. 5/BW
Input resistance, Ri = 1 MΩ
(c) BW = 0.35tr (d) tr = 0.35BW
Input capacitance, Ci = 20 pF
TNPSC AE- 2019
Probe resistance, Rp = 10 MΩ
Probe capacitance, Cp = ? Ans. (a) : The rise time (tr), of signal applied to CRO
and bandwidth of CRO are related as
R i Ci = R p C p tr × BW = 0.35
If this condition fails then the signal is distorted at the
R i Ci 1× 106 × 20 ×10−12
Cp = = output of CRO.
Rp 10 × 106 63. CRO can not measure
Cp = 2×10–12 = 2 pF (a) Power (b) Voltage
58. In CRT aquadag carries. (c) Frequency (d) None of these
(a) aqueous solution of graphite MPPSC Forest Service Exam.-2014
(b) sweep voltage Ans. (a) : CRO means cathode ray oscilloscope is use
(c) secondary emission electrons in laboratory to measure voltage, current, frequency and
(d) none of the above draw the graph.
IES-1992 Power can not be measure CRO,
64. A voltage signal V(t)=A+B sin ωt is fed to an Ans. (b) : When a signal is to be displayed or viewed
oscilloscope with the coupling mode set to DC, on the screen it is applied across the y-plates of a
other settings being appropriate. The displayed cathode ray tube (CRT). But to see its waveform or
wave can be expressed as: pattern, it is essential to spread it horizontally from left
(a) A+B sin ωt (b) B sin ωt to right.
(c) A (d) 0 In a single beam-single trace analog oscilloscope a
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I delay line is inserted between y-input and y-plates.
Ans. (a) : A voltage signal V(t)=A+B sin ωt is fed to an 68. Oscilloscope is basically a
oscilloscope with the coupling mode set to DC, other (a) Voltmeter (b) Ammeter
settings being appropriate. The displayed wave can be
(c) Wattmeter (d) Energy meter
expressed as A+B sin ωt.
65. Given x(t)=3sin (1000 πt) and y(t)=5cos (1000
Ans. (a) : Oscilloscope is basically a voltmeter this
πt+π/4). The x-y plot will be:
(a) Circle (b) Multi-loop closed curve instrument displays graphically electrical signals and
shows how those signals change over time. It is used to
(c) Hyperbola (d) Ellipse
measure frequency and of difference of signals.
Ans. (d) : Phase angle (φ) 69. The Miller sweep circuit normally used in CRO
is basically
(a) A voltage to current converter circuit
(b) A current to voltage converter circuit
(c) An integrator circuit
(d) A differentiator circuit
Ans. (c) : The Miller sweep circuit normally used in
CRO is basically. An integrator circuit.
70. For the given Lissajous figure Find fy, if fx is
1200Hz
x(t) =3sin(1000 πt)

y(t) = 5cos(1000πt + π / 4)
y ( t ) = 5sin (1000πt + 450 ) + 900 
(a) 1200Hz (b) 1800Hz
= 5sin 1000πt + 1350  (c) 2400Hz (d) 1600Hz
φ = 1350 BARC Scientific Officer-2016
66. An aquadag is used in a Cathode Ray Ans. (b) : Given, fy = ?, fx = 1200 Hz
Oscilloscope of collect: fy 3
(a) Primary electrons =
fx 2
(b) Secondary emission electrons
(c) Both primary and secondary emission fy 3
=
electrons 1200 2
(d) None of the above fy = 1800 Hz
71. In a CRO which of the following is/are part of
Ans. (b) : The bombarding electrons, striking the electron gun?
screen, release secondary emission electrons
(a) Cathode (b) All of the option
These secondary electrons are collected by an aqueous
solution of graphite called Aquadag which is connected (c) Grid (d) Accelerating anode
to the second anode. RRB JE-01.09.2019, 3:00 PM – 5:00 PM
67. In a single beam, single trace analog Ans. (b) : The electron gun in CRO consist of the
oscilloscope a delay line is inserted between: following parts such as heater cathode, electrons, grids
(a) X-input and X-plates and various type of anodes is required an electron gun is
(b) Y-input and Y-plates an electrical component that produces a beam of
(c) X-input and trigger circuit electron with a specified kinetic energy. It is often used
(d) Y-input and trigger circuit in computer panel in (C) second degree a television
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I receivers.
72. A double beam oscilloscope has- 77. A CRO has 50 small divisions on X axis. If
(a) Two screens frequency is measured using 10 microsecond
(b) Two electron guns per small division range; the error in
(c) One vertical amplifier measurement is upto ______ Hz.
(d) Two different phosphor coatings (a) 2 (b) 40
RRB JE- 31.08.2019, 10 AM-12 PM (c) 2000 (d) 100000
Ans. (b) : Dual beam oscilloscope is a two electron gun, UPRVUNL AE, 2016
who give used to display signals two, real time of
signals can be displayed simultaneously. Two electron Ans. (b) : Given, T = 50×10 = 500 µsec
beam obtained either by using two electron gun or by 1
And f = = 2000 Hz
using beam splitting technique are done. 50 × 10 × 10−6
73. A 53 Hz reed type frequency meter is polarized 2000
with DC. The new range of frequency meter is : Error in frequency = = 40 Hz
50
(a) 106 Hz (b) 26.5 Hz
78. The Lissajous patterns on a CRO screen is
(c) 53 Hz (d) 100 Hz
shown in the figure. The frequency ratio of the
vertical signal to the horizontal one is
Ans. (a) : When frequency meter in polarized with DC
then
Fnew = 2 × fold (a) 3 : 2 (b) 5 : 1
Fnew = 2 ×53
(c) 1 : 5 (d) 2 : 3
Fnew = 106 Hz KVS TGT (WE)- 2014
74. Normal width of QRS signal is : Ans. (b) : Given,
(a) 0.08 to 0.12 sec (b) 0.12 to 0.2 sec
(c) 0.35 to 0.43 sec (d) 0.8 to 1.2 sec
Ans. (a) : For QRS signal, the width should be less than
0.12 sec. Amplitude should be greater than 0.5 mV. fy Horizontalsignal 5
= = = 5 :1
75. Two sinusoidal signals of the same frequency fx verticalsignal 1
are displayed on a dual-trace oscilloscope. One
79. The function of input attenuators in measuring
complete cycle of each signal covers 6 cm of the
instruments like VTVM, CRO etc is to
horizontal scale and the starting point be the
horizontal scale and the starting point of the (a) decrease the input impedence.
two signals are separated by 0.5 cm. The phase (b) attenuate the frequency range.
difference between the two signals in degrees is (c) attenuate the input signal amplitude without
(a) 30 (b) 45 altering the frequency contents.
(c) 60 (d) 90 (d) attenuate the input impedence without
BSNL (JTO)-2006 altering the frequency contents.
2π KVS TGT (WE)- 2014
Ans. (a) : A phase difference = × path difference
λ Ans. (c) : Attenuators are passive device which
2π attenuates the input signal amplitude without altering
= × 0.5 = 300
6 the frequency contents.
76. In a dual trace oscilloscope, the display appears 80. Input and output from a common-base
segmented when amplifier are fed to an oscilloscope to see their
(a) low frequency signals are observed in phase relationship. The Lissajous figure is :
Alternate mode (a) an ellipse (b) an oblique ellipse
(b) low frequency signals are observed in chop (c) a circle (d) a straight line
mode
KVS TGT (WE)- 2017
(c) high frequency signals are observed in
Alternate mode Ans. (d) : Phase shift of input and output of common
(d) high frequency signals are observed in chop base amplifier is 00. Hence Lissajous pattern will be a
mode straight line.
BSNL (JTO)-2006 81. The waveform shown in the below figure is
Ans. (d) : In a dual trace oscilloscope, the display observed on the screen of an oscilloscope. If the
appears segmented high frequency signals are observed time div is set to 2.5 µs/div, determine the
in chop mode. frequency of the signal.
3. Absolute encoders are normally used for:
(a) One revolution
(b) Continuous speed in clockwise direction
(c) Continuous speed in counter clockwise
(d) Counting least significant bits.
IES-2014
Ans. (a) : Absolute encoders, gives output as a unique
words or bits for each partition.
• They also provides programming flexibility.
(a) 100 KHz (b) 125 KHz • They don't cause partition whenever power is
(c) 150 KHz (d) 200 KHz switched off.
APPSC Poly. Lect. 15.03.2020 • Absolute encoders are mainly used for the single
Ans. (a) Signal cover 1-div at = 2.5µs revolution of the shaft
For 4 div, signal period will be 2.5 × 4µs = 10µs • These are the feedback device that provides speed,
partition information by providing output as a digital
1 1 106 word.
f= = −6
= = 105 = 100 kHz
T 10 × 10 10 4. What is the dynamic range of a spectrum
analyzer with a third order interrupt point of
(viii) DF Meters and Analyzers +25 dBm, and a noise level of (–) 85 dBm.
(a) 0.73 dB (b) 7.3 dB
1. A digital timer with eight readout is stated to (c) 73 dB (d) 730 dB
have accuracy of 0.005 percent of reading,
±1 in the final digit. Readout is in s, ms and IES-2013
µs. Assuming that the instrument meets its Ans. (c) : As given that-
specifications, the maximum likely errors when I p3 = + 25 dBm
the reading is 05000000 µs is MDS = – 85 dBm
(a) ±251 µs (b) ±260 µs Dynamic range of a spectrum analyzer (in dB)
(c) ±261 µs (d) ±250 µs
ESE-2021
with a third order intercept = (
2
I P – MDS
3 3
)
Ans.(d) : reading = 5000000 µsec 2
Dynamic range =  25 – ( –85)
Error due to 0.005% of reading 3
0.005 2
= × 5000000 µ sec = [110]
100 3
= 250 µ sec 220
=
Error due to ±1 final digit 3
1 = 73.33 dB
resolution = n n = 8 ( eight read out )
10 5. For the recording of very fast random signals,
1 the most suitable instrument would be
= ±1× 8 = 10 −8 = 0.01µ sec (a) dual-trace
10
Total error = error due to 0.005% of reading+ error due (b) sampling oscilloscope
to ±1 final digit (c) real-time spectrum analyzer
= 250 µ sec+ 0.01µ sec = 250.01µ sec (d) scanning-type spectrum analyzer
250 µ sec IES-2012
2. A tachometer encoder can be used for Ans. (c) : For the recording of very fast random signals
measurement of speed: the most suitable instrument would be real time
(a) of false pulses because of electrical noise spectrum analyzer.
(b) In forward and reverse direction Real-time spectrum analyzer- It is made to have the
(c) in one direction only ability to continuously monitoring the spectrum.
(d) for single revolution in a multiple track Generally it is a non-scanning type spectrum analyzer.
IES-2016 6. Which of the following cannot provide as
Ans. (c) : A tachometer encoder can be used for much time interval accuracy as the
measurement of speed in one direction only. oscilloscope but can capture and display eight
or more signals simultaneously, something that
Tachometer encoder has a single output signal. It is
consist of pulse for each increment of displacement. If scopes cannot do?
motion is unidirectional it can easily be used to (a) Logic analyzer (b) Digital oscilloscope
measures the speed/displacement. Any reversed motion (c) Frequency analyzer (d) Wave analyzer
will produce identical pulse causing error. IES-2009
Ans. (a) : A logic analyzer is an electronic instrument List-I List-II
which captures and displays the multiple signals from a A. Digital Counter 1. Measurement of
digital system or digital circuit. harmonic
7. In a distortion factor meter, the filter at the B. Scherring bridge 2. Measurement of
front end is used to suppress frequency
(a) odd harmonics C. Meggar 3. Measurement of
loss angle in a
(b) even harmonics
dielectric
(c) fundamental component D. Spectrum Analyzer 4. Measurement of
(d) dc component insulation
IES-2008, 2000 resistance.
Ans. (c) : In a distortion factor meter, the filter at the Codes:
front end is used to suppress the fundamental A B C D
component. The filter at the front end is used to (a) 1 2 3 4
suppress fundamental component so that only the (b) 2 3 4 1
strength of harmonics can be measured. (c) 4 3 2 1
8. An inductive pick-up is used to measure speed (d) 4 1 3 2
of a shaft on which a 120 tooth-wheel is IES-1992
attached. The number of pulses produced per Ans. (b) :
second is 3000. What is the RPM of the shaft? Digital Counter - Measurement of frequency
(a) 1500 (b) 1800 Scherring bridge - Measurement of loss angle in a
(c) 3000 (d) 3600 dielectric
IES-2005 Meggar - Measurement of insulation
resistance
Ans. (a) : Spectrum Analyzer - Measurement of harmonic
No. of pulse produced per second 12. The voltage (E0) developed across a glass
R.P.M of shaft =
No. of tooth wheels electrode for pH measurement is related to the
3000 temperature (T) by the relation
= × 60 = 1500 rpm 1 1
120 (a) E 0 ∝ 2 (b) E 0 ∝
9. The most suitable primary standard for T T
frequency is: (c) E0∝T (d) E0∝T2
(a) Rubidium vapour standard APGENCO AE- 23.04.2017
(b) Quarts standard Ans. (c) : In electrochemistry, the ‘Nernst equation’ is
(c) Hydrogen maser standard an equation that is related to the reduction potential of
(d) Cesium beam standard an electrochemical reaction to the standard electrode
potential, temperature and activities of the chemical
IES-2002
species undergoing reduction and oxidation.
Ans. (d) : The most suitable primary standard for Nernst equation for pH measurement
frequency is cesium beam standard. Cesium beam
−RT C0
standard is the primary standard for frequency. Cesium E0 = ln
beam standard is the primary standard of nf Ci
time/frequency the significant of cesium beam standard E0 ∝ T
is essentially for telecommunication, navigation and for
other scientific experiments. 13. For a rotameter, which one of the following
statements is TRUE?
10. Harmonic distortion analyzer (a) The weight of the float is balanced by the
(a) Measures the amplitude of each harmonic buoyancy and the drag force acting on the
component
float
(b) Measures the rms value of fundamental
frequency component (b) The velocity of the fluid remains constant for
(c) Measures the rms value of all the harmonic all positions of the float
component except the fundamental frequency (c) The measurement of volume flow rate of gas
component is not possible
(d) Displays rms value of each harmonic (d) The volume flow rate is insensitive to
component of the screen of a CRO. changes in density of the fluid
IES-1999, 1998 APGENCO AE- 23.04.2017
Ans. (c) : Harmonic distortion can be measured Ans. (a) : Rotameters are simple industrial flow meters
accurately by using harmonic distortion analyzer. that measures the flow rate of liquid or gas in a closed
Harmonic distortion analyzer measures the rms value of tube.
all the harmonic component except the fundamental The flow rate inside the rotameter is measured by using
frequency component. a float that is lifted by the fluid flow based on the
11. Match List-I, List-II and select the correct buoyancy and velocity of the fluid opposing gravity
answer by using the codes given below the lists: pulling the float down.
14. The pressure and velocity at the throat of a 2. Which of the following is NOT active
Venturi tube, measuring the flow of a liquid, transducer?
are related to the upstream pressure and (a) Thermoelectric transducer
velocity, respectively, as follows: (b) Piezoelectric transducer
(a) Pressure is lower but velocity is higher (c) Hall-effect transducer
(b) Pressure is higher but velocity is lower (d) Electromagnetic transducer
(c) Both pressure and velocity are lower UPPSC ITI Principal/Asstt. Director-09.01.2022
(d) Pressure and velocity are identical Ans. (c) : Active transducers- Those transducers,
APGENCO AE- 23.04.2017 which uses their own developed voltage or current for
Ans. (a) : As pipe becomes narrow towards throat, a giving the output signal. Ex. Thermoelectric transducers
gradual decrease in cross-sectional area that causes piezoelectric transducer, electromagnetic transducer.
higher fluid velocity according to continuity equation. Passive transducers- Passive transducers are those
Venturi tube is a device for measuring fluid flow transducers which uses an external power supply for
consisting of a tube so constricted that the pressure converting the non-electrical quantity to an electrical
differential produced by fluid flowing through the quantity.
construction gives a measure of the rate of flow. Ex. Potentiometer, LVDT, hall effect transducer.
15. The standard for long distance analog signal So, hall effect transducer is not active transducer.
transmission in process control industry is
3. Four strain gauges are mounted on a simple
(a) 4-20 mV (b) 0-20 mA flat tensile specimen arranged for complete
(c) 4-20 mA (d) 0-5 V temperature compensation and maximum
APGENCO AE- 23.04.2017 sensitivity when connected in a four-arm
Ans. (c) : The standard for long distance analog signal bridge circuit. An 8 ×105 Ω calibration resistor
transmission in process control industry is, is shunted across one of the strain gauges. It the
Current ; (4 – 20) mA gauge resistances are each 188Ω and the gauge
Voltage ; (1 – 5)V factors are 1.22, then the effective strain is
16. The most fundamental method of frequency (a) 545 ×10–6 (b) 775 ×10–6
–6
measurement is (c) 48.1×10 (d) 32.4 ×10–6
(a) By comparison ESE-2022
(b) By using absorption wave meter Ans. (c) : As per question four train gauges resistances
(c) By using slotted line are
(d) By using transmission wave meter Let R eq = 188Ω and Rsh = 8 × 105 Ω
Figure can be drawn as-
Ans. (a) : The most fundamental method of frequency
measurement is by comparison.
17. A vibration galvanometer is tunded:
(a) By changing its damping constant
(b) By attaching weight to the vibrating coil
(c) By changing the length and tension of
vibrating coil
Ans. (c) : Vibration Galvanometers are widely used as Change in resistance when switch is open and closed-
null-point detectors in a.c. bridges.
R G R sh
A vibration galvanometer tuned ∆R = − RG
1. by changing the length of suspension R G + R sh
2. by adjusting tension in the suspension 188 × 8 × 105
= − 188
188 + 8 ×105
(ix) Transducers = −0.04417Ω
∆R / R G
1. Resistance strain gauge is NOT used to How G f = = gauge factor = 1.22 (given)
measure which one of the following? strain
(a) Pressure (b) Temperature ∆R 0.04417
Strain = = = 192 × 10−6
(c) Torque (d) Displacement R G × G f 188 × 1.22
UPPSC ITI Principal/Asstt. Director-09.01.2022 Then for quarter bridge effective strain-
Ans. (b) : An electrical strain gauge works on the basis of −6
change in resistance as a function of strain this type of = 192 × 10 = 48.1×10−6
gauge can measure pressure, Displacement torque. etc. 4
4. Piezoelectric material serves as a source of Gf = 2.2 find ∆l
(a) Microwaves (b) Ultrasonic waves ∆R = 0.013Ω
(c) Musical waves (d) Resonant waves We know that,
∆R
Ans. (b) : Piezoelectric materials are those which get
polarized when they are subjected to mechanical stress. Gauge factor = R
∆l
Piezoelectric material also get strained when subjected
to electric stress. e.g. Quartz, BaTiO3, BaTio ceramic l
5. A thermistor has a resistance temperature ∆R × l
Gf =
coefficient of -2% over a temperature range of R × ∆l
250C to 500C. If the resistance is 50 Ω at 25°C. ∆R × l
what is the resistance at 450C ? ∆l =
R × GF
(a) 70 Ω (b) 20 Ω
(c) 15 Ω (d) 30 Ω 0.013 × 0.1 13 ×10−4
RPSC ACF & FRO 23.02.2021 ∆l = = = 0.0246 × 10 −4
240 × 2.2 24 × 22
Ans. (d) : Resistance at 250C = 50Ω ∆l = 2.46 × 10 −6
−2
temperature coefficient = –2% = 8. The LVDT is used in an accelerometer to
100 measure seismic mass displacements. The
R2 = R1 [1+α1 (t2 – t1)] LVDT and signal conditioning outputs are 0.31

( 45 − 25)
2 mV/mm with a ±20mm core displacement. The
R45 = 50 1 −
 100  spring constant is 240 N/m and the core mass is
R45 = 30Ω 0.05 kg. The natural frequency and maximum
6. A quartz piezoelectric crystal having a measurable acceleration are respectively.
thickness of 1.5 mm and voltage sensitivity of (a) 69.3 rad/s and 69.3 m/s2
0.05 V-m/N is subjected to a pressure of 2 (b) 69.3 rad/s and 96 m/s2
MN/m2. The permittivity of the quartz is (c) 15.59 rad/s and 96 m/s2
40.6×10-12 F/m. The output voltage is (d) 15.59 rad/s and 31.18 m/s2
(a) 150 V (b) 155 V ESE-2021
(c) 165 V (d) 300 V
Ans.(b) : Given that,
ESE-2021
x = ± 20mm
Ans.(a) : Given that,
Voltage sensitivity (g) = 0.05V − m / N M = 0.05kg
Crystal thickness (t) = 1.5mm K = 240 N/m
t = 1.5 × 10−3 m K 240
Natural frequency ( ωn ) = =
Pressure (P) = 2 MN / m 2 M 0.05
= 2 × 106 N / m 2 ωn = 69.3 rad / sec
Output voltage (V0) = gtp
Acceleration = ω2n x
V0 = 0.05 × 1.5 ×10 −3 × 2 × 106
= ( 69.3) × 20 × 10−3
2
V0 = 150V
7. A strain gauge is bonded to a beam 0.1 m long = 96m/sec2
2
and has a cross-sectional area 4 cm . Young’s 9. Which one is not a type of Viscometer?
modulus for steel is 207 GN/m2. The strain (a) Orifice viscometer
gauge has an unstrained resistance of 240
Ω and a gauge factor of 2.2. When a load is (b) Capillary viscometer
applied, the resistance of gauge changes by (c) Redwood viscometer
0.013 Ω. The change in length of the steel beam (d) Rotameter viscometer
is APPSC Poly. Lect. 15.03.2020
(a) 1.23 × 10 −6 m (b) 2.46 × 10 −6 m Ans. (d) : Viscometer is an instrument used to measure
(c) 4.92 × 10 −6 m (d) 9.84 × 10 −6 m the viscosity and flow properties of fluids. Its principle
ESE-2021 is based on 'Poiseuille's law' viscometer generally used
in petrochemical, light industry, textiles and other
Ans.(b) : Given that, fields.
l = 0.1m , A = 4 cm2 There are three main types of viscometers are-
Y = 207 GN / m 2 1. Orifice viscometer 2. Capillary viscometer
R = 240Ω 3. Redwood viscometer.

10. Which of the following is NOT a characteristic Ans. (d) : Drift errors are caused due to deviations in
of an ideal transducer? the performance of the measuring instrument that
(a) High sensitivity (b) High dynamic range occurs after calibration. In case of pH meter zero drift
(c) Low linearity (d) Low noise can be reduced by using balanced and differential
APPSC Poly. Lect. 15.03.2020 amplifiers.
Ans. (c) : Ideal Transducer is a Linear Instrument. 16. In the ultrasonic-level gauge, the ultrasonic
OR source is placed at the :
(a) bottom of the vessel containing the liquid
Linearity is a property of mathematical relationship that
can be graphically represented as straight line. So low (b) top of the vessel containing the liquid
linearity is not a characteristics of an ideal transducer. (c) middle of the vessel containing the liquid
(d) far end from the vessel containing the liquid
11. Which device measure velocity at a point of
fluid in a stream? APPSC Poly. Lect. 15.03.2020
(a) Venturi meter (b) pH meter Ans. (a) : Ultrasonic level instruments operates on the
basic principle of sound wave to determine solid or
(c) Pitot-Static tubes (d) Viscometer
liquid level. Here in Ultrasonic-level gauge, the
APPSC Poly. Lect. 15.03.2020 ultrasonic source is placed at the bottom of the vessel
Ans. (c) : Pitot-Static tubes are the devices used for containing the liquid to measure differential level.
measuring the velocity of a fluid at a point in a fluid 17. Thermocouple does NOT work on the principle
stream. of :
12. Name the sensor used for measuring very high (a) Seebeck Effect (b) Thomson Effect
temperature to which physical contact is (c) Stroboscopic Effect (d) Peltier Effect
impractical? APPSC Poly. Lect. 15.03.2020
(a) Thermocouple (b) Thermistor Ans. (c) : Thermocouple does not works on the
(c) Pyrometer (d) RTD principle of stroboscopic effect because, stroboscopic
APPSC Poly. Lect. 15.03.2020 effect is a visual phenomenon while seebeck effect,
Ans. (c) : Pyrometer is a device used for measuring Thomson effect and Peltier effect are based on
very high temperature to which physical contact is thermoelectric phenomenon.
impractical. Note:- Specially thermocouple working is based on
13. Synthetic piezo-electric material is : seebeck effect.
(a) Quartz 18. Which of the following statements is false?
(b) Lithium sulphate (a) A transducer is an energy conversion device
(c) Sodium Potassium Tartrate (b) Strain gauge is an electrical transducer
(d) Rochelle Salt (c) A thermistor is variable resistance transducer
APPSC Poly. Lect. 15.03.2020 (d) Thermistors have negative temperature
coefficient of resistance
Ans. (b) : The piezoelectric material is mode analytic KVS TGT (WE)- 2016
specific by application of a surface cating doped with
specific reaction. Lithium sulphate is a piezoelectric Ans. (b) :
material. A transducer is an energy conversion device.
A thermistor is variable resistance transducer
14. Which of the following does NOT belong to Thermistors have negative temperature coefficient
passive transducer? of resistance.
(a) Thermistor (b) Thermocouple Strain gauge is a mechanical transducer
(c) Strain gauge (d) LVDT 19. Shaft encoder is used to measure
APPSC Poly. Lect. 15.03.2020 (a) angular position (b) linear position
Ans. (b) : Thermocouple is dissipative element. Hence (c) linear velocity (d) angular velocity
it is not passive transducer. RRB SSE 03.09.2015 Shift-II
It is active transducer, because it gives output without Mizoram PSC AE/SDO 2012-Paper-I
any external force. Ans. (d) : Shaft encoders are digital; transducer that are
OR used for measuring angular displacement and velocities.
Passive transducer is a device which converts the given Output is a pulse signal that is generated when
non-electrical energy into electrical energy by external transducer disc rotate.
force. So thermocouple is not a part of passive 20. LVDT is a
transducer. (a) Pressure transducer
15. In which of the following ways can zero drift be (b) Displacement transducer
reduced in the pH meter? (c) Velocity transducer
(a) Using filter (d) Acceleration transducer
(b) Giving zero adjustment arrangement MPPSC Forest Service Exam. 2014
(c) Keeping the input impedance high UKPSC Assistant radio Officer Screening Exam-2011
(d) Using balanced and differential amplifiers GPSC Asstt. Prof. 11.04.2017
APPSC Poly. Lect. 15.03.2020 UPRVUNL AE – 11.06.2014
Ans. (b) : LVDT is an acronym for Linear Variable 25. Which of the following meters is based on the
Differential Transformer LVDT is common type of principle of Hall Effect?
Displacement transducer for electrical signal (current or (a) Ammeter (b) Gaussmeter
voltage). (c) Voltmeter (d) All of the above
21. Which one of the following transducer is made ISRO Scientist Engg.-2014
of semiconductor ? Ans. (b) : Gauss meter works on the principle of hall
(a) Thermometer (b) Microphone effect. Voltmeter works on the principle of electrostatic
(c) Thermocouple (d) Thermistor principle.
KVS TGT (WE)- 2017 26. Measurement of Hall coefficient enables the
determination of :
RPCS Lect.-2011
(a) Temperature coefficient and thermal
Ans. (d) : Thermistor are semiconductor sensor which conductivity
are made from the sintered compound of metallic oxide (b) Mobility and concentration of charge carriers
of Cu, Mn, Ni & Co form beads, rings and disc. (c) Fermi level and forbidden energy gap
22. It is required to measure temperature in the (d) None of the above
range of 1300º-1520ºC. The most suitable ISRO Scientist Engg.-2012
thermo couple is Ans. (b) : Measurement of Hall coefficient enables the
(a) chromel-constantan (b) iron-constantan determination of mobility and concentration of charge
(c) chromel-alumel (d) platinum-rhodium carriers.
OPSC Poly. Lect.(Instrumentation)-2018, Paper- II Application of Hall effect-
Mizoram PSC AE/SDO 2012-Paper-I Hall effect is very useful phenomenon and help to
IES-2006, 1998 determine the type of semiconductor.
Ans. (d) : Type B (Platinum-Rhodium) suited for high By knowing the direction of the Hall voltage one on
temperature measurements up to 1820 º C. determine that the given sample is whether n-type
semiconductor or p-type semiconductor.
Type Thermocouple Temperature range
types 27. Which of the following materials is used in the
construction of thermistors?
E Chromel –270 to 1000 ºC (a) Pure metal
Constantan (b) Pure semiconductor
J Iron-constantan –210 to 1200 ºC (c) Pure insulator
K Chromel-Alumel –250 to 1250 ºC (d) Sintered mixture of metal oxides
B Platinum - rhodium 250 to 1820 ºC RPSC LECTURER-10.01.2016
23. LVDT : Ans. (d) : Thermistors are typically built by using
(a) Converts linear motion into electrical signal sintered mixture of metal oxides. NTC thermistors are
manufactured from oxides of the iron group of metals.
(b) Translates electrical signal into linear motion
Ex. chromium (CrO, Cr2O3), manganese (MnO) etc.
(c) Helps measuring temperature
(d) Can be used to sense angular displacement 28. Which of the following transducers can be used
for non-contact temperature measurement?
Nagaland PSC CTSE (Degree)-2017, Paper-I (a) Resistance temperature detector
Nagaland PSC CTSE (Degree) -2015, Paper I (b) Thermistor
Ans. (a) : Linear variable differential transformer (c) Sensistor
(LVDT) LVDT is the most widely used inductive (d) Pyrometer
transducer for converting the linear motion into RPSC LECTURER-10.01.2016
proportional output electrical voltage. Ans. (d) : A pyrometer known as 'radiation
24. Which of the following principle is used in thermometers' can be used for non-contact temperature
displacement transducers measurement. Pyrometers act as photo detector because
(a) Capacitive, inductive and differential of the property of absorbing energy and measuring of
electromagnetic wave intensity at any wavelength.
(b) lonization, oscillation and photoelectric
29. The temperature coefficient of resistance for a
(c) Piezoelectric, potentometric and velocity thermistor is
(d) All of the above (a) low and negative (b) low and positive
Nagaland PSC CTSE (Degree) -2015, Paper I (c) high and negative (d) high and positive
Nagaland PSC CTSE (Degree) -2016, Paper I ISRO Scientist Engg.-2016
Ans. (a) : Some of the transducers can convert the input Ans.(c) : Temperature coefficient of resistance for a
displacement into a corresponding output electrical thermistor is high and negative.
voltage and hence, can be used for the measurement of A thermistor is a type of resistor whose resistance is
displacement. strongly dependent on temperature more than standard
resistor.
(1) Potentiometer Thermistor are widely used as inrush current limiters
(2) Linear variable differential transformer (LVDT) temperature sensors (negative temperature coefficient or
(3) Hall transducer NTC type).
30. Under identical values of cold and hot junction Ans. (a) : An orifice meter is a piece of equipment used
temperatures, which thermocouple gives the to measure the flow rate of a gas or a fluid.
highest output?
(a) iron constantan (b) nickel iron
(c) chromal constantan (d) platinum rhodium
Ans. (c) : Under identical value of cold and hot junction
temperature, chromal constantan thermocouple gives
the highest output.
Because of its have highest sensitivity which range lies
between (40 - 80) µV/ºC The minimum cross sectional area of the jet is known
31. A transducer must have as the vena-contracta. It is the point in a fluid stream
(a) good dynamic response where the diameter of the stream is the least, and fluid
(b) good sensitivity velocity is at its maximum.
(c) good resolution 36. In electromagnetic flow meters, dc magnetic
(d) all of above field is not used because of ______.
Mizoram PSC AE/SDO 2012-Paper-I (a) Frequency
Ans. (d) : A transducer should have good resolution, (b) Electrolytic discharge
good accuracy the transducer can give good result (c) Electrolytic polarization
within its specified range so select transducer as per the (d) Current continuity
operating time. UPRVUNL AE, 2016
32. Piezo electric effect can be used to measure Ans. (c) : Electromagnetic flowmeters are based on
(a) force (b) strain Faraday’s law of electromagnetic induction. In this, the
(c) acceleration (d) all of above magnetic field is generated by a set of coils, as the
Mizoram PSC AE/SDO 2012-Paper-I conductive liquid passes through the electromagnetic
field, an electric voltage is induced in the liquid which
Ans. (d) : A piezoelectric sensor is a device that uses
is directly proportional to its velocity.
the piezoelectric effect to measure changes in pressure
acceleration, temperature strain, or force by converting E = kBVD
then to an electrical charge. Where, k= flow tube constant
33. Bellows transducers are used to measure: V= mean flow velocity
(a) Velocity (b) Humidity D= electrode spacing
(c) Pressure (d) Torque B= magnetic field strength
UPRVUNL AE, 2016 When dc supply is given to magnetic field coils the
problems such as polarization and electromechanical
Ans. (c) : The bellow are made up of an alloy with high and electrochemical effect occurs.
strength and ductility commonly brass or phosphor
bronze is used for making bellow. Bellow transducer 37. In flow transducers, ________ is not used at
are used to meaure pressure. higher frequencies whereas _____is suitable for
suspended fluids.
34. Natural quartz is used in piezoelectric pressure (a) Bellows, balloons
transducers because of its ____temperature
(b) Accelerometer, reluctance sensor
sensitivity and _____ resistivity.
(c) Orifice meter, venturi tube
(a) Low, low (b) Low, high
(d) Venturi tube, orifice meter
(c) High, Low (d) High, high
UPRVUNL AE, 2016
UPRVUNL AE- 2016
Ans. (c) : An orifice meter is a piece of equipment used
Ans. (b) : A piezoelectric transducer is one that generate a to measure the flow rate of a gas or a fluid. It mainly
voltage proportional to the strees applied to it. consist of an orifice plate, an orifice plate housing, and
Lower temperature sensitivity and higher resistivity a meter tube. It can not be used at higher frequencies.
provide an inherently long time constant which allows Venture meter is a device in which pressure energy is
static calibrations. converted into kinetic energy, and it is used for
35. In orifice meter, vena contracta is a position measuring the rate of flow of liquid through pipes. It
where ______ is maximum and _____ is can be used for measuring the flow rate of gases,
minimum. slurries, suspended solids, water and dirty liquid.
(a) Velocity, static pressure 38. Which of the following is used for measuring
(b) Velocity, dynamic pressure torque in rotating parts in machines?
(c) Static pressure, dynamic pressure (a) Accelerometer (b) Dynamometer
(d) Acceleration, inertia (c) Tachometer (d) Rotatometer
UPRVUNL AE, 2016 APPSC Poly. Lect. 15.03.2020
Ans. (b) : Dynamometers are the devices which are ∆R / R ∆R / R
used to measure torque in rotating parts of machines Gf = = = 2 ( G f = 2 for metal)
∆L / L ε
mainly torque of rotating shafts, and power required to Change in resistance (∆R)= G f × ε × R
operate the drive on a machine or motor, which can be
measured by evaluating the torque and rotational speed = 2 × 120 × 1000 × 10–6
of a motor simultaneously. = 0.24 Ω
39. Which device can be used for measuring 44. Consider the following statements related to a
torque? strain gauge:
(a) Helical spring (b) Flat spiral spring 1. It is a passive transducer
(c) Bellow (d) Diaphragm 2. It converts mechanical pressure into a change
of resistance
APPSC Poly. Lect. 15.03.2020 3. Its efficiency is described in terms of Gauge
Ans. (b) : Flat spiral spring device can be used for factor
measuring torque. Flat springs which are fixed at center  ∆R 1 
and force is applied on the peripheral end. Flat spiral 4. Its Gauge factor is equal to  × 
spring device is only applicable for the very low range  R σ
of torque measurement since high range of force may Which of the above statements are correct?
break the device. (a) 1 and 3 (b) 2 and 3
(c) 1 and 4 (d) 2 and 4
40. A resistance strain gauge has a resistance of UPSC JWM-2016
(a) 100 Ω (b) 25 Ω Ans. (c) : 1. The strain gauge is a passive transducer.
(c) 10 Ω (d) 1Ω
 ∆R 1 
Mizoram PSC AE/SDO 2012-Paper-I 2. Its gauge factor is equal to  × .
Ans. (a) : The normal value of resistance of a resistance  R σ
strain gauge is 100Ω. 45. Semiconductor strain gauges are usually made
of
41. The term 'Poisson's ratio' is connected with (a) Rochelle salt
(a) strain gauge (b) LVDT (b) Ammonium dihydrogen phosphate
(c) Bourden tube (d) thermistor (c) Quartz
Mizoram PSC AE/SDO 2012-Paper-I (d) Silicon
Ans. (a) : Poisson's ratio terms is connected with strain UPSC JWM-2016
guage. Poisson's ratio is defined as the ratio of the Ans. (d) : Semiconductor strain gauges are usually
change in per unit lateral strain to the per unit made of silicon, and its band gap energy is 1.12 eV.
longitudinal strain. 46. The output of a thermocouple is
The Poisson's ratio for all metal lies between 0 to 0.5. (a) DC current (b) AC current
(c) DC voltage (d) AC voltage
42. RTD is generally suitable for temperature of
UJVNL AE-2016
about
(a) 50ºC (b) 200ºC Ans. (c) : The output of thermocouple is in constant DC
voltage. Thermocouple output voltage is very small in
(c) 800ºC (d) 1500ºC mV unit.
47. Which one of the following is a passive
Ans. (c) : The RTD typically can be used over a transducer?
higher temperature range of -250 ºC to 800 ºC. (a) Piezoelectric (b) Thermocouple
Transducer Measurement range (in ºC) (c) Photovoltaic cell (d) LVDT
Resistance upto 800 ºC Mizoram PSC Jr. Grade-2018, Paper-I
thermometer (RTD) IES-2018
Thermocouple upto 1400 ºC
Ans. (d) : LVDT is a passive transducer.
Thermistors –100 ºC to 300 ºC
LVDT is the most widely used inductive transducer for
Pyrometer 1200 ºC to 3500 ºC converting the linear motion into proportional output
Bimetallic strip Room temperature (27 ºC) electrical voltage.
43. What is the change in resistance in a metal wire LVDT stands for linear variable differential transformer.
of resistance 120 Ω, that results from a strain of 48. The function of the dummy strain gauge, in
1000 µm/m, employing strain gauge? measurement using two strain gauge, is to
(a) 0.16 Ω (b) 0.24 Ω (a) Increase the stability of measuring system
(c) 0.33 Ω (d) 0.42 Ω (b) Nullify the errors due to temperature i.e.
thermal e.m.f
UPSC JWM-2016 (c) Measure the strain in both, x as well as y,
Ans. (b) : Given that, direction
Resistance of wire (R) = 120 Ω (d) Increase the sensitivity of measuring system
Strain(ε) = 1000 µm/m Nagaland PSC CTSE (Degree)-2018, Paper-I

Ans. (b) : Dummy strain gauge is used for nullify the 53. Which of the following is not used in making
errors due to temperature. resistance-temperature transducer ?
49. Consider a strain gauge of Rg = 350 Ω and (a) Copper (b) Platinum
gauge factor of 2.82. Calculate equivalent (c) Tungsten (d) Nickel
strain if resistance of 100 kΩ is shunted across TNPSC AE-2013
the strain gauge Ans. (c) : Tungsten is not used in making resistance
(a) 1236 × 10–6 cm/cm (b) 1236 × 10–3 cm/cm temperature transducer. Because Tungsten has a
(c) 1236 × 10–13 cm/cm (d) 1236 × 10–8 cm/cm relatively high resistivity.
TNPSC AE-2014 54. Load cells are
Ans. (a) : Given that, (a) Electrical sensors used for flow measurement
Rg = 350 Ω Rsh = 100 KΩ = 100 × 103 Ω (b) Mechanical sensors used for flow
Gf = 2.82 Strain (ε) = ? measurement
∆R / R (c) Electrical sensors used for force measurement
Gf =
ε (d) Mechanical sensors used for force
350 × 100 × 103 350 × 105 measurement
Req = = = 348.7927 Ω TNPSC AE-2013
350 + 100 × 10 3
100350
∆R = Rg – Req = 350 – 348.779 = 1.221Ω Ans. (c) : Load cells are electrical sensors used for
∆R / R 1.22 / 350 force measurement. A load cell is essentially a force
ε= = = 1236 × 10–6 cm/cm transducer or force sensor. It is used principally to
Gf 2.82 measure weight.
50. Hooke's law is written as 55. Gas flow and gas pressure can be measured by
(a) applied force per unit area. (a) Potentiometer device
(b) elongation of the stressed member per unit (b) Dielectric gauge
length.
(c) Eddy current gauge
(c) strain is equal to the ratio of stress to Young's
modulus. (d) Pirani gauge
(d) strain is equal to the ratio of Young's modulus TNPSC AE-2013
to stress. Ans. (d) : The operation of Pirani gauge depends on
TNPSC AE-2013 variation of the thermal conductivity of a gas with
Ans. (c) : Hooke's law is written as strain is equal to the pressure.
ratio of stress to Young's modulus. • It's pressure ranging from 10–1 to 10–3 mm of Hg
f s = + kx • It's ragged and usually more accurate than
thermocouple gauges:
51. The use of thermocouple meters for ac Pirani gauge is used to measure Gas flow and gas
measurement leads to a meter scale which is pressure.
(a) linear (b) square law
56. A resistance thermometer is an example of
(c) logarithmic (d) exponential
TNPSC AE-2013 (a) zero order system (b) first order system
Ans. (b) : The use of thermocouple meter for ac (c) second order system (d) none of these
measurement leads to a meter scale which is square law. TNPSC AE-2008
A thermocouple is a sensor for measuring temperature. Ans. (a) : Resistance thermometer is an example of zero
In thermocouple induced emf = a (∆θ) + b (∆θ)2 order system. In resistance thermometer resistance
where a and b → constant temperature detectors are used.
∆θ → temperature difference between junction 57. Dunmore hygrometer has
52. A wire strain gauge with a gauge factor k = 2 is (a) linear resistance/relative humidity
bonded to a steel member which is subjected to characteristics
a strain of 10–6. If original to strain resistance (b) non-linear resistance/relative humidity
of a gauge is 120 Ω, the change in gauge characteristics
resistance (c) linear inductance/relative humidity
(a) 120 µΩ (b) 240 µΩ characteristics
(c) 120 mΩ (d) 240 mΩ (d) non-linear inductance/relative humidity
TNPSC AE-2013 characteristics
∆R / R TNPSC AE-2008
Ans. (b) : k = Ans. (b) : Dunmore hygrometer has a non linear
ε
resistance and relative humidity characteristic it is a
k=2 R = 120Ω ε = 10–6
solution containing lithium chloride is applied between
∆R the wires.
= 2 × 10−6
120 58. Three types of temperature transducers are
∆R = 240 × 10−6 Ω compared as regards their sensitivity. The
∆R = 240 µΩ order in which they exhibit their sensitivities
(highest to lowest) is
(a)Thermistors, RTDs, thermocouples pressure, acceleration, temperature, strain or force by
(b)Thermocouples, RTDs, thermistors converting them to an electrical charge. Hence it is a
(c)RTDs, thermistors, thermocouples inverse transducer. piezoelectric transducer is a self
(d)RTDs, thermocouples, thermistors generating type transducer that can produce an electrical
TNPSC AE-2008 voltage or current output without utilizing any external
power source.
Ans. (a) : The order of sensitivity from high to low
Thermistors > RTDs > thermocouple 62. Piezoelectric accelerometer
Sensor type Thermocouple RTD Thermistor
(a) should not be used for high frequencies above
100 Hz
Accuracy 0.5 to 5°C 0.1 to 1°C 0.05 to 1.5°C
(Low) (High) (Moderate) (b) should be used for low frequencies
Stability Variable 0.05°C /year 0.2 °C/year (c) should use a monitoring source of low input
Temperature 200 to 1750°C –200 to –100 to impedance
Range 650°C 325°C (d) has a low natural frequency
Power Self powered Constant Constant OPSC Poly. Lect. (Instrumentation)-2018, Paper-II
required voltage or voltage or TNPSC AE-2008
current current
Susceptibility Susceptible/Col Rarely Rarely Ans. (d) : A piezoelectric accelerator is an
to electrical d junction susceptible susceptible accelerometer that employs the piezoelectric effect of
noise compensation high certain material to measure the dynamic changes in
resistance mechanical variables. So it has low natural frequencies.
only
Response time Fast Generally Fast 63. Capacitive transducers can be used for
0.10 to 10s slow 1 to 50s 0.12 to 10s measurement of liquid level. The principle of
Linearity Non-linear Fairly linear Exponential operation used in this case is
Cost Low High Low to (a) change of capacitance with change of
moderate distance between plates
Sensitivity Low Moderate High (b) change of area of plates
59. The microphones, which are widely used for (c) change of dielectric strength
sound measurement systems having a very (d) none of these
wide range of amplitudes are TNPSC AE-2008
(a) carbon microphones Ans. (c) : A capacitive transducer work on the principle
(b) piezoelectric microphones of change in the capacitances of the capacitor. The
(c) inductive microphones variation in capacitance by changes in the dielectric or
(d) capacitive microphones dielectric constant.
TNPSC AE-2008 Dielectric gauge can measure liquid level and thickness
Ans. (b) : A pressure field microphones or piezoelectric of liquid or gas.
microphones is designed to measure the sound pressure 64. A transducer has an output impedance of 1kΩ
in from of the diaphragm. It has same magnitude and and the load resistance is 1MΩ. The transducer
phase at any position in the field. behaves as
60. In wire-wound strain gauges, the change in (a) a constant current source
resistance on application of strain is mainly due (b) a constant voltage source
to (c) a constant power source
(a) Change in length of wire (d) none of these
(b) Change in diameter of wire TNPSC AE-2008
(c) Change in both length and diameter of wire Ans. (b) : If Z0 >>> ZL, All current passes through the
(d) Change in receptivity load. Hence transducer works as constant current source
TNPSC AE-2008 but Z0 <<< ZL, No current will pass through load. So it
Ans. (c) : When a conductor is stretched or compressed behaves as a voltage source.
due to the change in it's length and diameter it's Z0 = 1 kΩ ZL = 1 MΩ Z0 <<< ZL
resistance changes. The property of the conducting 65. A seismic transducer working in the
material is called piezo resistive effect. displacement mode should be designed to have
61. Piezoelectric transducers are (a) weak springs and heavy mass
(a) passive transducers (b) weak springs and light mass
(b) active transducers (c) stiff springs and heavy mass
(c) inverse transducers (d) stiff springs and light mass
(d) (b) and (c) TNPSC AE-2008
TNPSC AE-2008 Ans. (a) : When seismic transducer are used in the
Ans. (d) : A piezoelectric sensor is a device that uses displacement mode they should be designed with weak
the piezoelectric effect due to measure changes in spring and heavy mass.
66. A vibrometer is an instrument, which can be 71. The size of a venturimeter is expressed as 200 ×
used for measurement of vibrations by 100 mm2. It means that
measuring (a) the diameter of the upstream pipe is 200 mm
(a) acceleration and that of downstream pipe 100 mm
(b) displacement and velocity (b) the diameter of the pipe is 200 mm and that of
(c) displacement, velocity and acceleration throat is 100 mm
(d) none of these (c) the diameter of the pipe is 100 mm and that of
TNPSC AE-2008 throat is 200 mm
Ans. (c) : Vibrometer is an instrument which can be used (d) none of these
for measurement of vibration are displacement, velocity TNPSC AE-2008
and acceleration but measurement of acceleration is
preferred. Seismic transducer, also known as seismic Ans. (b) : The size of venturimeter is expressed as 200
accelerometer is used for measuring acceleration. × 100 mm2. It means that the diameter of pipe is 200
mm and the throat is 100 mm.
67. Extremely small motion can be measured with
(a) seismic type accelerometer 72. The desirable property of a monometric fluid is
(b) a pneumatic motion transducer (a) high viscosity
(c) piezoelectric type transducer (b) high coefficient of thermal expansion
(d) an optical interferrometric type sensor (c) low vapour pressure
TNPSC AE-2008 (d) corrosiveness and stickiness
Ans. (d) : Extremely small motion can be measured by TNPSC AE-2008
an optical interferrometric type sensor. Ans. (c) : Desirable property–
Because of their wide application, interferometers come 1. Fluid should have low vapour pressure
in a variety of shapes and sizes. They are used to 2. High density
measure everything from the smallest variations on the 3. Immiscible with work fluid
surface of a microscopic organism, to the structure of
enormous expanses of gas and dust in the distant 4. Low surface tension.
universe, and now, to detect gravitational waves. 5. Low freezing point.
68. The seismic transducers give satisfactory 6. Low viscosity.
results, both in displacement mode and 73. The discharge over a V-notch is proportional to
acceleration mode, if the damping factor is (a) H1.5 (b) H3.5
2.5
(a) 1 (b) 0 (c) H (d) H0.5
(c) nearly 0.7 (d) nearly 0.5 TNPSC AE-2008
TNPSC AE-2008 Ans. (c) : The V-notch design causes small changes in
Ans. (c) : In amplitude response for zero and infinite discharge to have a large change in depth allowing more
frequencies amplitude become zero and we do not get accurate head measurement than with a rectangular
any flat amplitude response, so damping ratio will be weir.
less than 1.
Discharge through a triangular notch is given by
69. When accelerometers operate in the 8 θ
displacement mode the ratio of forcing Q = Cd tan   . 2g × H 5 / 2
frequency to natural frequency should be 15 2
(a) below 1 (b) below 2
Q ∝ H 2.5
(c) above 2 (d) above 200
TNPSC AE-2008
Ans. (c) : In reality, accelerometer have long been used
to measure displacement when accelerometers operated
in the displacement mode the ratio of forcing frequency
to natural frequency should be above 2.
70. Hydraulic load cells are available which have a
maximum capacity of 74. Which of the following meters is used for
(a) 10 kN (b) 50 kN measuring flow of clean fluids only?
(c) 10 MN (d) 50 MN (a) Ultrasonic flowmeter
TNPSC AE-2008 (b) Hot wire anemometer
Ans. (d) : The hydraulic load cell design contains no (c) Turbine flowmeter
electrical components, this type of load cell lends itself (d) All (a), (b) and (c)
to environments where explosion safety is a concern, or TNPSC AE-2008
where an outside power source may be difficult to
provide. Hydraulic load cells can typically measure up Ans. (c) : Turbine flowmeter are used for measurement
to 50MN and have an accuracy of about 0.25 to 1.0 of natural gas and liquid flow. Turbine meters are used
percent of full scale output. for low viscosity and high flow measurement.

75. In a vortex shedding flow meter, the shedding 79. The rate of flow of fluid depends upon
N V (a) density (b) gravity force
frequency is f = st where Nst is (c) viscosity (d) all of these
D
(a) Reynolds number (b) Mach number TNPSC AE-2008
(c) Strouhal number (d) none of these Ans. (d) : The flow rate depends upon the density
TNPSC AE-2008 viscosity and gravity force.
Ans. (c) : The frequency at which vortex shedding takes we know that Reynolds number is a very important
place for an infinite cylinder– reference number in the accurate determination of flow
it is used to determine the point at which the flow goes
N V from the viscous to the turbulent stage.
f = st
D VDρ
Nst = strouhal number Rd =
µ
V = flow velocity
where
D = diameter
ρ = density of flowing fluid
76. Mercury is used in liquid filled system as it
µ = absolute viscosity.
gives
(a) wide temperature range 80. Which one of the following is not used for
(b) high sensitivity measurement of density?
(c) wide temperature range and approximately (a) Manometer
linear scale (b) Hydrometer
(d) wide temperature range and high sensitivity (c) Force balanced method
TNPSC AE-2008 (d) Both (b) and (c)
TNPSC AE-2008
Ans. (c) : Mercury is a liquid, and in this respect a
mercury-filled thermometer is similar to the liquid-filled Ans. (a) : A manometer is the simplest measuring
thermometer. These two are separated because of the instrument used for gauge pressure (low range pressure )
unique characteristics of mercury and its importance as measurement while hydrometer & force balance method
a temperature measuring medium. Mercury provides is used to measurement of density.
rapid response, accuracy and plenty of power for 81. The potential drop across pH meter is
operating control elements and also approximately RT C
linear scale. (a) ∆Vt = −2.30 log H
ξ CR
77. In using capillary tube viscometer corrections
are to be made for RT C
(b) ∆Vt = 2.30 log H
(a) change of density ξ CR
(b) change in temperature RT C
(c) change gravitational constant (c) ∆Vt = 2.30 log R
(d) losses in head ξ CH
TNPSC AE-2008 RT C
(d) ∆Vt = 1.65 log R
Ans. (d) : Capillary viscometers utilize the flow of the ξ CH
process liquid through a capillary to measure viscosity. TNPSC AE-2008
The technique of determining the viscosity of
Ans. (a) : The potential drop across pH meter
Newtonian fluids by measuring the pressure drop across
a capillary tube during isothermal laminar flow is well RT C
∆Vt = −2.30 log H
known. It is also gives kinematic viscosity in stokes ξ CR
from measurements of the pressure gradient and losses
in head. 82. In a Saybolt viscometer, the viscosity can be
measured to measuring the time to fill a flask
78. For an ideal Newtonian fluid, the relationship is
with liquid volume equal to
(a) µ = shear stress/velocity gradient
(a) 50 ml (b) 200 ml
(b) µ = velocity gradient/shear stress
(c) 60 ml (d) 10 ml
(c) µ = velocity/stress
TNPSC AE-2008
(d) µ = stress/velocity
Ans. (c) : Saybolt viscometer is the standard instrument
TNPSC AE-2008
for testing petroleum products. The viscosity
Ans. (a) : If τ is the relevant shear stress producing the determination should be conducted in a room free from
motion and γ is the velocity gradient, we have drafts and rapid changes in temperature to attain the
τ highest degree of accuracy. Accuracies within ± 0.1%
µ= of reading are possible when the standard testing
γ
procedures are follow. The Saybolt viscometer controls
where µ is sometime called the coefficient of viscosity, the heat of the fluid and the viscosity is the time is takes
but it is now more commonly referred as the viscosity. the fluid to fill a 60ml container.
83. Loudspeaker is also used in the recorder of Ans. (d) : Thermistors are temperature dependent
(a) EMG (b) ECG resistors, changing resistance with changes in
(c) EOG (d) EEG temperature.
TNPSC AE-2008 89. Strain gauge is a passive transducer and is used
Ans. (a) : The tape recorder is induced in the system to for converting mechanical displacement into a
facilitate playback and study of the EMG sound change
waveforms at a later convenient time. The waveform (a) Temperature (b) Resistance
can also be photographed from the CRT screen by using (c) Inductance (d) Capacitance
a synchronized camera. Nagaland PSC CTSE (Degree) -2015, Paper I
84. In the case of ERG, what type of electrodes are Ans. (b) : When a conductor is stretched or
used to pick-up signals? compressed, due to the change in its length and
(a) Disc electrodes diameter it is resistance changes. This property of the
(b) Retinal electrodes conducting material is called piezoresistive effect due to
(c) Vacuum type electrodes this reason strain gauges are also called piezoresistive
(d) pH electrodes transducers.
TNPSC AE-2008 90. The function of the dummy strain gauge, in
Ans. (b) : ERGs are often recorded using a thin fiber measurement using two strain gauge, is to
electrode that is placed in contact with the cornea or an (a) increase the stability of measuring system
electrode that is embedded with cornea contact lens. (b) Nullify the errors due to temperature i.e.
85. The active transducer in the measurement of thermal e.m.f
pressure is (c) Measure the straining both, x as well as y.
(a) piezoelectric transducer direction
(b) capacitive transducer (d) Increase the sensitivity of measuring system
(c) strain gauge Nagaland PSC CTSE (Degree) -2015, Paper I
(d) inductive transducer Ans. (b) : A dummy strain gauge is used in a quarter
TNPSC AE-2008 bridge strain gauge circuit to compensate for changes in
temperature and lead wire resistance.
Ans. (a) : A piezoelectric crystal there is an emf across
certain surface if the dimensions are changed due to 91. In spite of their high gauge factors
applied mechanical stress and vice-versa. i.e. effect is semiconductor strain gauges are not preferred
reversible means if there is applied voltage across in most of the applications because they
certain surfaces then there will be change in dimensions (a) Are sensitive to temperature fluctuations
i.e. stress and strain respectively. (b) Behave in nonlinear manner
86. Arrhythmia can be diagnosed by (c) Have a high cost
(a) EEG (d) (a) and (b)
(b) ECG Nagaland PSC CTSE (Degree) -2015, Paper I
(c) Vector cardiogram Ans. (d) : Disadvantage of semi-conductor strain gauge.
(d) Phono-cardiography (i) The semi-conductor strain gauges is that they are
TNPSC AE-2008 very sensitive to changes in temperature.
Ans. (b) : Arrhythmia can be diagnoses by ECG or (ii) Linearly of the semi-conductor strain - gauge is
EKG. It detect the abnormal heart rhythms. poor.
(iii) Semiconductor strain gauges are more expensive
87. In thermo-couple instruments, in which of the
and difficult to attach to the object under study.
following is an emf caused if the junction of two
wires of dissimilar metals is heated and the free 92. The poisson ratio µ for a material is defined as
or cold ends are connected to a milli-voltmeter? the
(a) Kelvin effect (b) Hot wire effect (a) Ratio of strain in the lateral direction to strain
(c) Seebeck effect (d) Faraday effect in the axial direction
Nagaland PSC CTSE (Diploma)-2018, Paper-I (b) Ratio of strain in the axial direction to strain
RPSC LECTURER-10.01.2016 in the lateral direction
(c) Ratio of change in length to change in
Ans. (c) : The seebeck effect is a phenomenon in which resistance
a temperature difference between two dissimilar
electrical conductors or semi-conductor produces a (d) Ratio of change in resistance to axial strain
voltage difference between the two substances. Nagaland PSC CTSE (Degree) -2015, Paper I
88. A resistor in which the resistance changes Lateralstrain
Ans. (a) : Poisson 's Ratio = −
exponentially with change in temperature is Longitudinalstrain
called as
(a) Potentiometer (b) Phototransistor −∆ D
= = D=γ
(c) Varactor (d) Thermistor ∆L
RPSC LECTURER-10.01.2016 L

93. Rosette gauges are used to measure the strains Ans. (a) : Piezoelectric materials are those which get
in polarized when they are subjected to mechanical stress.
(a) More than one dimension Piezoelectric material also get strained when subjected
(b) More than one plane to electrical stress.
(c) More than one direction e.g: Quartz, Rochelle salt, BaTiO3 crystal.
(d) Only in single direction 98. Hall Coefficient Rh is equals to ratio of hall
Nagaland PSC CTSE (Degree) -2015, Paper I voltage multiply by width to
Ans. (c) : Strain rosette can be defined as the (a) magnetic field and length
arrangement of strain gauges in three arbitrary (b) electric field and length
directions. These strain gauges are used to measure the (c) electric field and magnetic field
normal strain in those three directions. On the surface of (d) current density
the object can be determined. Nagaland PSC CTSE (Diploma)-2017, Paper-I
94. Generally, the resistance of thermistor Ans. (a) : Hall coefficient (Rh) is defined as the ratio
decreases between the induced electric field and to produce of
(a) Linearly with an increase in temperature applied magnetic field and current length.
(b) Linearly with the decreases in temperature BI R H
Hall voltage VH =
(c) Exponentially with an increase in temperature w
(d) Exponentially with the decrease in V w
temperature Hall coefficient RH = H
BI
99. True rms responding voltmeters use
Ans. (c) : Thermistor is widely applicable for several
(a) Thermistor (b) RTD's
compensation technique. It exhibits variations in its
resistance with respect to change in temperature. As the (c) LVDT's (d) Thermocouple
resistance of thermistor decrease with temperature Nagaland PSC CTSE (Degree)-2017, Paper-I
increase. Ans. (d) : Thermocouples used in rms measuring
95. For a particular material the Hall coefficient voltmeters. The thermocouple is an electrical device
was found to be zero. The material is consisting of two dissimilar electrical conductors
(a) insulator forming an electrical junction. A thermocouple
(b) metal produces a temperature dependent voltage as a result of
(c) intrinsic semiconductor the seebeck effect.
(d) extrinsic semiconductor 100. Hall-effect pickup is used for the measurement
Nagaland PSC CTSE (Diploma)-2017, Paper-I of
Ans. (b) : For metal the Hall coefficient is zero. (a) Electron concentration in a semiconductor
1 (b) Current through a metal
RH = (c) Magnetic flux
ne
(d) All the above
1
RH = [for metal n = ∞] Nagaland PSC CTSE (Degree)-2017, Paper-I
∞×e
Ans. (d) : Hall effect can be used to measures.
RH = 0
• Electron concentration in a semiconductor
96. S1: Transducer is device which converts
physical into electrical quantity • Current through a metal
S2: Transducer is also called as sensor. • Magnetic flux.
(a) S1 is true & S2 is false V w
RH = H
(b) S2 is true & S1 is false BI
(c) Both S1 & S2 are true 101. Platinum resistor (PTR) and a thermistor
(d) Both S1 & S2 are false (THR) are used to measure room temperature.
Nagaland PSC CTSE (Diploma)-2017, Paper-I Which of the following is true?
Ans. (a) : Transducer is not a sensor. It convert any (a) PTR offers more accuracy, THR more
physical quantity into electrical quantity. Hence resolution
transducer is just like a electrical generator. (b) PTR offers more resolution, THR more
97. What is the piezoelectric effect in a crystal? accuracy
(a) Voltage is developed due to mechanical stress (c) Both offer same accuracy, THR offers more
(b) Change in resistance due to temperature resolution
(c) Change of frequency due to temperature (d) Both offer same resolution, PTR offers more
(d) Current is developed due to force applied accuracy
Nagaland PSC CTSE (Diploma)-2017, Paper-I Mizoram PSC IOLM-2010, Paper-I

Ans. (a) : The platinum resistance thermometer is a (c) Transmission of data random
versatile instrument for temperature measurement in the (d) Transmission of data of one measurand
range from 200º to 1000ºC. It is used both for precision Mizoram PSC IOLM-2010, Paper-II
measurements of the highest accuracy and for routine Ans. (b) : time-division multiplexing is a method of
industrial work. transmitting and receiving independent signal over a
102. Tall tended T wave represents : common signal path by means of synchronized switches
(a) Hyperkalemia (b) Tachycardia at each and of transmission line.
(c) Bradycardia (d) Normal ECG 108. The most useful transducer for displacement
OPSC Poly. Lect. (Instrumentation)-2018, Paper-II sensing with excellent sensitivity, linearity and
Ans. (a) : Peaked T - wave in a patient who missed resolution is
three runs of dialysis are likely to represent (a) an incremental encoder
hyperkalemia, white tell hyperacute. (b) an absolute encoder
103. For elastic materials stress and strain are (c) a LVDT
related by (d) a strain gauge
(a) Poisson's law (b) Gauss's law RPCS Lect.-2011
(c) Hooke's law (d) Dalton's law
Ans. (c) : LVDT is an acronym for linear variable
Nagaland PSC CTSE (Diploma)-2018, Paper-I differential transformer. It is common type of
Ans. (c) : For linear elastic material, stress is linearly electromechanical transducer that can convert the
related by to strain by Hooke's law. rectilinear motion of an object to which it is coupled
104. Which of the following material is not used as a mechanically into a corresponding electrical signal.
piezoelectric transducer? 109. The gauge factor of the material of strain gauge
(a) Rochelle (b) Lithium sulphate is such that the resistance changes from 1000
(c) Barium titanate (d) Tungsten oxide ohms to 1009 ohms when subjected to a strain
Mizoram PSC Jr. Grade -2018, Paper-I of 0.0015. The Poisson's ratio for the material
IES-2008 of the gauge wire is
Ans. (d) : A piezoelectric material is one in which an (a) 1.75 (b) 2
electric potential appears across a crystal if the (c) 2.5 (d) 6
dimensions of the crystals are changed by the RPSC Vice Principal ITI-2016
application of mechanical force. Ans. (c) : ∆R = 1009–1000 = 9
e.g. Quartz crystal, BaTiO3, Lithium sulphate, Rocelle
R = 1000Ω , Strain = 0.0015Ω
salts, Dipotassium tartrate.
105. In an electromagnetic blood flow meter, the ∆R 9
induced EMF is directly proportional to : Gauge factor = R = 1000 = 6
(a) Blood flow rate Strain 0.0015
(b) Square root of blood flow rate Gauge factor = 1+2 µ
(c) Logarithm of blood flow rate 6 = 1+2 µ
(d) Cube of blood flow rate 2µ = 6–1 = 5
OPSC Poly. Lect. (Instrumentation)-2018, Paper-II µ = 2.5
Ans. (b) : Electromagnetic flow meters detects flow by 110 Which of the following instruments will be used
using Faraday's law of induction. In an electromagnetic to measure the temperature above 16000C
blood flow meter, the induced emf is directly (a) A simple thermometer
proportional to square root of blood flow rate.
(b) Electrical resistance pyrometer
106. A piezoelectric crystal has Young’s modulus of (c) Thermo-electric pyrometer
130 GPa. The uniaxial stress that must be
applied to increase the polarization from 550 to (d) None of the above
-2
555 Cm is, nearly Nagaland PSC CTSE (Degree)- 2016, Paper-I
(a) 2.798 GPa (b) 2.175 GPa Ans. (c) : Pyrometer is an instrument used to measure
(c) 1.593 GPa (d) 1.182 GPa very high temperature such as the temperature of a
Mizoram PSC IOLM-2010, Paper-I furnace. Thermo electric pyrometer is used to
temperature above 1500ºC
stress
Ans. (d) : γ = 111. Which of the following is not a disadvantage of
strain LVDT
130 × 5 (a) A LDVT is inherently low in power output
∴ stress = GPa
550 (b) Relatively large displacements are required
= 1.182 GPa for appreciable differential output
107. Time division multiplexing requires (c) They are sensitive to stray magnetic fields
(a) Constant data transmission (d) All the above
(b) Transmission of data samples Nagaland PSC CTSE (Degree)- 2016, Paper-I
Ans. (a) : Disadvantage of LVDT: Advantages of thermistor
(1) Relatively large displacements are required for • It is rugged and compact and expensive
differential output • It has good stability.
(2) LVDT sensitive to stray magnetic field. • It requires relatively simple circuitry
(3) Affected by vibrations • The response time of a thermistor can vary from a
LVDT gives high output, Hence option (a) is correct. fraction of second to minutes depending on the size
112. The sensitivity of a strain gauge is described in of the detecting mass and capacity of the thermistor.
terms of a characteristic called the gauge factor 116. The capacitive transducer works on the
'K' defined as the principle of change of capacitance which may
(a) Change in resistance per unit change in length be caused by change in
(b) Unit change in length per unit change in 1. Dielectric constant
length 2. Overlapping area of plates
(c) Unit change in length per unit change in 3. Distance between the plates
resistance (a) 1 and 2 only (b) 1 and 3 only
(d) Change in length per unit change in resistance (c) 2 and 3 only (d) 1, 2 and 3
Nagaland PSC CTSE (Degree)- 2016, Paper-I IES-2020
Ans. (a) : A fundamental parameter of the strain gauge
Ans. (d) : • Capacitive transducers are used for the
is its sensitivity to strain, expressed quantitatively as the
measurement of displacement, pressure and other
gauge factor. GF is the ratio of the frictional change in
physical quantities.
electrical resistance to the frictional change in length.
• It works on the principle of variable capacitances.
113. The relation which relates the gauge factor 'K'
to poisson ratio 'µ' is given as • The capacitance of a parallel plate is mathematically
defined as:-
(a) µ = 1 + 2K (b) µ = 1 –2K
εA
(c) K= 1–2µ (d) K=1 + 2µ C=
Nagaland PSC CTSE (Degree)- 2016, Paper-I d
Ans. (d) : The relation which relates the gauge factor From the given formula we observe that the capacitance
and poisson ratio- of the capacitive transducer can change because of the
following reason:-
K = 1 + 2µ (1) The overlapping area of plates.
114. Apart from LVDT, linear displacement can (2) Change in the distance between the plates and
also be sensed by (3) Dielectric constant
(a) RVDT 117. What are the advantages of capacitive
(b) Capacitance transducer transducers?
(c) Thermocouple 1. They are extremely sensitive
(d) Thyristor 2. They have a high input impedance and
Nagaland PSC CTSE (Degree)- 2016, Paper-I therefore the loading effects are minimum
Ans. (b) : Apart from LVDT, linear displacement can 3. They have a good frequency response
also sensed by capacitance transducer. It also used to (a) 1 and 2 only (b) 1 and 3 only
sense pressure. (c) 2 and 3 only (d) 1, 2 and 3
115. What are the salient features of thermistors? IES-2020
1. They are compact, rugged and inexpensive Ans. (d) : Advantages of capacitive transducer :-
2. They have good stability when properly aged • They are extremely sensitive.
3. The response time of thermistors can vary • They have a high input impedance.
from a fraction of a second to minutes, • Loading effects are minimum in capacitive transducers.
depending on the size of the detecting mass • They have a high resolution.
and thermal capacity of the thermistor • They can be used in the stray magnetic field.
(a) 1 and 2 only (b) 1 and 3 only • They have a good frequency response.
(c) 2 and 3 only (d) 1, 2 and 3 • They require a small power to operate.
IES-2020
118. A resistance wire strain gauge with a gauge
Ans. (d) : factor of 2 is bonded to a steel structural
• Thermistors are generally made up of member subjected to a stress of 100 MN/m2.
semiconductors materials. The modulus of elasticity of steel is 200 GN/m2.
• Thermistors have a negative temperature coefficient The change in the value of gauge resistance
of resistance i.e. the resistance decreases with an due to the applied stress will be
increase in the temperature. (a) 0.05% (b) 0.10%
• Thermistors can measure the temperature in the (c) 0.30% (d) 0.60%
range of –100°C to 300°C IES-2019
Ans. (b) : Gauge factor 121. A strain gauge with gauge factor 4 and
∆R / R resistance 250 Ω undergoes a change of 0.15Ω
Gf = during a test. The measured strain is
∆L / L (a) 150 × 10–4 (b) 15 × 10–4
∆R ∆L –4
(d) 0.15 × 10–4
= Gf . (c) 1.5 × 10
R L IES-2018
stress Ans. (c) : Given that, ∆R = 0.15, R = 250Ω
ε=
Y G.F = 4
ε = strain ∆R / R
Y = Young’s modulus of elasticity G.F =
∆L / L
∆R stress ∆L/L = ε
= G f .ε = G f .
R Y ∆R / R
ε =
100 × 106 G.F
= 2×
200 × 109 0.15 1 15 1
ε = × = ×
= 2×0.5×10–3 250 4 25000 4
∆R = 0.00015
= 0.10%
R = 1.5×10–4
119. A quartz piezoelectric crystal having a 122. Unbonded strain gauge is mainly in a
thickness of 2 mm and voltage sensitivity of (a) Pressure transducer
0.055 Vm/N is subjected to a pressure of 1.5 (b) Force transducer
MN/m2. The voltage output will be (c) Vibration transducer
(a) 165 V (b) 174 V (d) Displacement transducer
(c) 183 V (d) 192 V IES-2018
IES-2019 Ans. (b) : Unbonded strain gauge is mainly in a force
Ans. (a) : Given, transducer.
Thickness(t) = 2mm Unbonded strain gauges are the gauges that are not
Voltage sensitivity (g) = 0.055 Vm/N directly bonded on to the surface of the structure under-
study.
Pressure (P) = 1.5 MN/m2
An unbonded strain gauge is used in places where the
E0 =g.t.p gauge is to be detached and used again and again.
= 0.055 × 2 × 10–3×1.5×106
123. A displacement of ±12.5 mm results in a
= 165 V
secondary voltage of 5 V in an LVDT. If the
120. A heater element is made of nichrome wire then secondary voltage is 3.2 V, the absolute
having resistivity equal to 100 × 10–8 Ωm and value of the corresponding displacement would
diameter of 0.4 mm. The length of the wire be
required to get a resistance of 40Ω will be (a) 4 mm (b) 6 mm
nearly (c) 8 mm (d) 10 mm
(a) 9 m (b) 7 m IES-2018
(c) 5 m (d) 3 m Ans. (c) : V α d
IES-2019 A displacement of ± 12.5 mm result in a secondary
Ans. (c) : Given that, ρ = 100×10 Ωm
–8
voltage of 5V
d = 0.4mm = 0.4×10–3 m d1 = ± 12.5 mm, V1 = 5V
R = 40Ω V2 = 3.2 V
A = πr2 V
2
d2 = 2 × d1
d V1
= π 
2 =
3.2
× 12.5
l ρl 5
R=ρ = = 8 mm
A d2
π 124. A resistance strain gauge is used to measure
4 stress of steel which is stressed to 1200 kg/cm2.
4ρl If the gauge factor is 2.5 and the Young's
=
πd 2 modulus of steel is 2×106 kg/cm2 the percentage
change in resistance of the gauge is
4 ×100 ×10−8 × l
40 = (a) 0.05% (b) 0.10%
π(0.4 ×10 −3 )2 (c) 0.15% (d) 0.25%
l = 5.024 m IES-2018
stress 1200 Ans. (d) : Advantage of LVDT-
Ans. (c) : ε = = = 6 × 10−4 Linearity- The output voltage of this transducer is
Y 2 × 106
practically linear for displacements up to 5 mm (a
∆R / R
G.F. = linearity of 0.05% is available in commercial LVDTs).
ε Infinite Resolution- The change in output is stepless
∆R ∆R the effective resolution depends more on the test
= G.F. × ε ⇒ = 2.5 × 6 × 10−4
R R equipment than on the transducer.
= 15×10–4 High Output- It gives a high output, therefore there is
∆R frequently no need for intermediate amplification
× 100 = 0.15% device.
R
High Sensitivity- The transducer possess a sensitivity
125. A capacitance transducer uses two quartz as high as 40 V/mm
diaphragms of area 750 mm2 separated by a
distance 3.5 mm. The capacitance is 370 pF. 128. Strain gauges are constructed with Germanium
When a pressure of 900 kN/m2 is applied, the chips because Germanium
deflection is 0.6 mm. The capacitance at this (a) has a strong Hall Effect
pressure would be: (b) is crystalline in nature
(a) 619 pF (b) 447 pF (c) can be doped
(c) 325 pF (d) 275 pF (d) has piezoelectric property
IES-2017 IES-2016
εA Ans. (c) : Semiconductor is strain gauge are used where
Ans. (b) : C =
d a very high gauge factor and a small envelope are
CαA required the resistance of semiconductors changes with
1 change in applied strain. Unlike in the case of metallic
Cα gauges where the change in resistance is mainly due to
distance change in dimension when strained the semiconductor
C1 d 2 strain gauge depend for there action upon piezoresistive
=
C2 d1 effect of property because can be doped.
A = 750 mm2 129. Which of the following transducers measures
= 7.5×10–4 m the pressure by producing emf as a function of
d = 3.5 mm its deformation?
C = 370 pF (a) Photoelectric transducer
P = 900 kN/m2 (b) Capacitive transducer
Deflection (D) = 0.6 mm (c) Inductive transducer
Distance between plates d2 = d1 – D = 3.5 – 0.6 (d) Piezoelectric transducer
= 2.9 mm IES-2016
d Ans. (d) : Piezoelectric transducer measures the pressure
C2 = C1. 1 by producing emf as a function of its deformation.
d2
Piezoelectric Transducer:- It is a device that uses the
3.5 × 10−3 piezoelectric effect to measure changes in acceleration,
= 370×10–12 × = 446.6×10–12
2.9 × 10−3 pressure, strain, temperature or force by converting this
C2 447 pF energy into an electric charge. A transducer can be
anything that converts one form of energy to another.
126. For which one of the following measurements a
130. A rotameter works on the principle of variable:
thermistor can be used?
(a) Velocity (b) Humidity (a) Pressure (b) Length
(c) Displacement (d) Percent of CO2 in air (c) Area (d) Resistance
IES-2016 IES-2016
Ans. (d) : Thermistor and RTDs are devices used to Ans. (c) : A rotameter works on the principle of
measured temperature in modern heating, ventilating, variable area. Rotameter is a constant pressure drop
air conditioning system. variable area flowmeter. It measures the flow rate of
Thermistor can used to measure the flow of air. liquid or gas. As area changes, there will be a change in
the volumetric flow rate. No electricity is required.
127. The advantages of an LVDT is/are
1. Linearity
2. Infinite resolution
3. Low Hysteresis
Which of the above advantages is/are correct?
(a) 1 only (b) 2 only
(c) 3 only (d) 1, 2 and 3
IES-2016
131. The instrument servomechanism is actually an 134. Which of the following flow meters is capable of
instrument system made of components, which giving the rate of flow as well as the total flow?
are: (a) Nutating disc flow meter
(a) Exclusively passive transducers (b) Electromagnetic flow meter
(b) Exclusively active transducers (c) Orifice meter
(c) Combination of passive transducers and (d) Lobed impeller flow meter
active transducers IES-2015
(d) Exclusively primary sensing elements Ans. (d) : Lobed impeller flow meter:- It is used to
IES-2016 measure both rate of flow as well as the total flow.
Ans. (c) : The instrument servomechanism is actually • This meter uses two lobed impellers, which are
an instrument system made of components, which are geared and mashed to rotate at opposite directions
passive transducers and active transducers. within the enclosure.
Active transducers are those which do not require any • It is one of the positive displacement meter types. Other
power source for their operation. They produce an meter types include Nutating disk, oscillating piston,
electrical signal proportional to the input. rotating vane, oval gear, reciprocating piston etc.
Passive transducers require external power and their • Positive displacement flow meter directly measures
output is a measure of some variation such as resistance, volume of the fluid or gas passing through the
inductance, capacitance etc. meter.
132. Which one of the following transducers 135. A resistance strain gauge is cemented to a steel
requires power supply for its operation? member, which is subjected to a strain of
(a) Thermocouple (b) Photovoltaic cell 2 × 10–6. If the original resistance is 100Ω and
(c) Piezoelectriccrystal (d) Thermistor change in resistance is 600µΩ, the gauge factor
KVS TGT (WE)- 2018 will be
Ans. (d) : Thermistor of the following tranducers (a) 3 (b) 0.33
requires power supply for its operation. (c) 300 (d) 0.03
Thermistor can be used to produce an analogue output IES-2015
voltage with variation in ambient temperature as its Ans. (a) : Given that,
resistance depends on temperature.
 ∆L  −6
133. A resistance strain gauge with a gauge factor of Strain   = 2 × 10
3 is fixed to a steel member subjected to a stress  L 
of 100 N/mm2. The Young's modulus of steel is R = 100Ω
2 × 105 N/mm2. ∆R = 600µΩ
The percentage change in resistance is ∆R
(a) 0.1% (b) 0.15%
(c) 1.0% (d) 1.5% G.F. = R
∆L
IES-2015 L
600 ×10−6
G.F. = 3, stress = 100 N/mm2
Young's modulus of steel (Y) = 2×105 N/mm2 = 100
2 × 10−6
∆R
R 600 × 10−6
G.F. = =
∆L 100 × 2 × 10−6
L G.F. = 3
∆L 136. In viscosity meters, the quantity measured is
= strain( ε) (a) Buoyant force (b) Frictional force
L
Stress (c) Coriolis force (d) Centrifugal force
ε= IES-2015
Y
100 Ans. (b) : • Viscosity meters, the quantity measured is
ε= = 5 × 10−4 frictional force. Viscosity meters, the quantity Viscosity
2 × 105 meters are used to measure the internal friction of a
Percentage change in resistance moving fluid.
 ∆R  • The viscosity meter or rheometer measures the
%  = G.F. × strain × 100 resistance of flow liquid.
 R 
• Viscosity is the measure of a liquid substance's
∆R
% = 3 × 5 × 10–4 × 100 resistance to the motion under an applied force, and
R the SI unit of viscosity is N-S/m2 or Pascal-second or
= 0.15% kg/ms.
137. Measurement of pressure can be done by using • It has a very high sensitivity. So, it has a high-
wire, foil or semiconductor type Strain Gauges. frequency response i.e. the parameters change very
The disadvantage of the semiconductor type of rapidly.
Strain Gauge compared to the other two is in • The steady-state response of the piezoelectric
terms of transducer to a constant displacement (static
(a) Gauge factor conditions) is zero.
(b) Hysteresis characteristics Hence, it cannot be used for the measurement of static
(c) Temperature sensitivity displacement and only used for dynamic displacement.
(d) Frequency response • It has the output voltage of the order of 1 mV to 30
IES-2015 mV per unit of acceleration.
Ans. (c) : Types of strain gauges 139. An inductive pick-up used to measure the
speed of a shaft has 120-tooth wheel. If the
number of pulses produced in a second is 3000,
the r.p.m. of the shaft is
(a) 1200 (b) 1500
(c) 1800 (d) 3600
IES-2014
f 3000
Ans. (b) : Speed = = = 25rps
n 120
∴In rpm = 25 × 60
Semiconductor or Piezo-resistive gauge = 1500 rpm.
• These gauges are produced in wafers from silicon or Inductive type pick-up tachometers:-
germanium crystals. • The unit consists of a small permanent magnet with
• In these crystals, the exact amount of special a coil around it.
impurities such as Boron have been added to impart • This magnetic pick-up is placed near a metallic
certain desirable characteristics. toothed rotor whose speed is to be measured.
• These are of two types : Negative or N-type whose
• As the shaft rotates, the teeth pass in front of the
resistance decreases in response to tensile strain.
pick-up and produce a change in the reluctance of
Positive or P-type whose resistance increases in
the magnetic circuit.
response to tensile strain.
• The field expands or collapses and a voltage is
Disadvantages:
induced in the coil.
• Temperature-sensitive:- Reacts to a small change in
• The frequency of the pulses depends upon the
temperature.
number of teeth on the wheel and its speed of
• Poor linearity
rotation.
• For the perfect measurement of strain the strain
• Since the number of teeth is known, the speed of
gauges must be independent of the ambient
temperature. So, the semiconductor strain gauge is rotation can be determined by measuring the pulse
disadvantageous here. frequency
138. Consider the following statements: 140. A piezoelectric crystal having a thickness of 2
Piezoelectric transducer has mm and a voltage sensitivity of 0.02 V-m/N is
1. a very good HF response subjected to a pressure of 20 × 103 Pa. What is
2. typical output voltage of the order of 1 mV to the output voltage?
30 mV per unit of acceleration (a) 0.775 V (b) 0.80 V
3. no requirement of external power and is self- (c) 0.002 × 10–6 V (d) 0.2 × 10–6 V
generating IES-2014
4. no response for static conditions Ans. (b) : The voltage induced is given by :
Which of the above statements are correct? E = gt p where,
(a) 1, 2 and 3 only (b) 1, 2 and 4 only g = voltage sensitivity in (V-m/N)
(c) 3 and 4 only (d) 1, 2, 3 and 4 only t = Thickness (m)
IES-2014 P = Pressure (N/m2 or Pa)
Ans. (d) : Piezoelectric transducer:- Voltage sensitivity = 0.02 V-m/N
• It (also known as piezoelectric sensor) is a device Thickness = 2 mm = 2×10–3 m
that uses the piezoelectric effect to measure changes
Pressure = 20×103 Pa
in acceleration, pressure, strain, temperature or force
by converting this energy into an electrical charge. E = g.t.P.
• It has no requirement of external power and is self = 0.02×0.002×20×1000
generating. = 0.80 Volts
141. A resistance strain gauge with gauge factor of 3 • Thermocouple consist of two wire legs made from
is cemented to a steel member subjected to a different metals.
strain of 2 × 10–6. If the original resistance is • The wire's lags are welded together at one end
100Ω, what is the change in resistance? creating a junction. This junction is where the
(a) 600µΩ (b) 600mΩ temperature is measured.
(c) 300µΩ (d) 200µΩ • When the junction experiences a change in
IES-2014 temperature a voltage is created.
Ans. (a) : Strain gauge transducers are the types of
transducers based on the principle that if a conductor is
stretched or compressed, its resistance value will change
accordingly due to the change in its dimensions.
Gauge factor is calculated as:-
144. The output voltage of a linear variable
∆R / R differential transformer is 1.5V at maximum
G.F. = ......(i)
∆L / L displacement. At a load of 0.5 MΩ, the
∆L deviation from linearity is maximum and it is
= ε = strain ±0.003 V from a straight line through origin.
L
Given that, R = 100Ω What is the linearity at the given load?
Strain = 2×10–6 (a) ±1.5 % (b) ±0.2%
G.F. = 3 (c) ±2.2% (d) ±15%
using equation (i) IES-2014
∆R /100 Ans. (b) : The percentage linearity (%L) is defined as the
3= ratio of maximum deviation to the full-scale value, i.e.
2 × 10−6 maximum deviation
∆R %L = × 100
⇒ 6×10–6 = Fullscale value
100
⇒ 6×10–6 × 100 = ∆R maximum deviation = ± 0.003V
output for maximum/full scale deviation = 1.5V
∴ ∆R = 600µΩ ±0.003
%L = × 100 = ± 0.2%
142. The dynamic characteristics of capacitive 1.5
transducers are similar to those of 145. In a piezoelectric crystal oscillator, if x
(a) low-pass filter (b) high-pass filter represent the mass of the crystal, then the
(c) notch filter (d) band-stop filter oscillation or tuning frequency is linearly
IES-2014, 1997 proportional to
Ans. (b) : The capacitive transducer uses the electrical (a) the mass of the crystal
quantity of capacitance for converting the mechanical (b) the square root of the mass of the crystal
movement into an electrical signal. The input quantity (c) the square of the mass of the crystal
causes the change of the capacitance which is directly (d) the inverse of the square root of the mass of
measured by the capacitive transducer. the crystal
Capacitive transducers are not used under static IES-2013
conditions. Capacitive transducers have high input
Ans. (d) : In a piezoelectric crystal oscillator, if x
impedance and less loading effect. Capacitive
transducers have the same frequency response as high- represents the mass of the crystal, then the oscillation or
tuning frequency is linearity proportional to the inverse
pass filters.
of the square root of the mass of the crystal.
143. Cold junction in a thermocouple is Oscillation Frequency:-
(a) the reference junction maintained at a known The frequency of oscillations in the case of series
constant temperature 1
(b) the junction maintained at a very low resonance is ωs =
temperature Ls C s
(c) the junction at which the temperature is Because the electrical and mechanical models are
sensed assumed equivalent, the natural frequency of the
(d) None of the above mechanical system must equal. The natural frequency of
IES-2014 the electrical system.
Ans. (a) : Thermocouple:- k
ωs =
• A thermocouple is a sensor used to measure x
temperature K is the spring modulus and x is the mass of the crystal.
• The thermocouple working principle is based on the
seebeck effect. This effect states that when a closed 146. Which one of the following quantities can be
circuit is formed by joining two dissimilar metals at measured with the help of the piezoelectric crystal?
two junctions, and junctions are maintained at (a) Acceleration (b) Flow
different temperatures then an electromotive force (c) Temperature (d) Velocity
(emf) is induced in this closed circuit. IES-2013
Ans. (a) : A piezoelectric transducer is used for Which of the above statements are correct?
measuring non-electrical quantities such as acceleration, (a) 1 and 2 only (b) 1 and 3 only
vibration, pressure and the intensity of sound. (c) 2 and 3 only (d) 1, 2 and 3
Piezoelectric accelerometer is a sensor that is used to IES-2013
measure acceleration by using the piezoelectric crystal. Ans. (d) : The strain gauge should have high gauge
Piezoelectric accelerometer generates a voltage based factor, low resistance temperature coefficient & high
on acceleration applied. It consists of piezoelectric resistance.
crystal which is supported by mass-spring dampers.
A strain gauge is a device that is used to measure strain
147. A reflectometer consists of on an object.
(a) two directional couplers Strain gauge is primary used to measure force or strain.
(b) one directional coupler and an isolator
151. A resistance strain gauge with gauge factor of 3
(c) one directional coupler and a circular
is subjected to a stress of 3000 kg/cm2 when
(d) two directional couplers and a circulator fastened to a steel rod. The modulus of
IES-2013 elasticity of steel is 2.1 × 106 kg/cm2. The
Ans. (a) : A reflectometer consists of two directional- percentage change in resistance of the strain
couplers. gauge element is
Directional couplers can be realized in micro strip, strip (a) 0.1428% (b) 24.84%
line, coax and waveguide. They are used for sampling a (c) 0.4284% (d) 4.3%
signal, sometimes both the incident and reflected waves IES-2013
(This application is called a reflectometer, which is an
important part of a network analyzer). Directional Ans. (c) : Gauge factor = 3
couplers generally use the distributed properties of Stress = 3000 kg/cm2
microwave circuits. Modulus = 2.1×106 kg/cm2
148. In a semiconductor strain gauge, the change in stress
Modulus of elasticity of steel =
resistance on application of strain is mainly due strain
to change in 3000
(a) length of the wire Strain =
(b) diameter of the wire 2.1 × 106
(c) resistivity of the material of the wire ∆L 1
Strain = =
(d) both the length and diameter of the wire L 700
OPSC Poly. Lect. (Instrumentation)-2018, Paper-II ∆R  ∆L  1
IES-2013 = G  × 100 = 3 × × 100 = 0.428%
R  L  700
Ans. (c) : In a semiconductor strain gauge the change in
resistance on application of strain is mainly due to 152. The wire in a metallic strain gauge is 0.1 m
change in resistivity of the material of the wire. long and has an initial resistance of 120 ohm.
On application of an external force, the wire
∆R / R length increases by 0.1 mm and the resistance
According to Gauge factor (G.f) =
∆L / L increases by 0.21 ohm. The gauge factor of the
149. In an LVDT, the two secondary windings are strain gauge will be
connected in differential mode to obtain (a) 3.00 (b) 2.00
(a) higher output voltage (c) 1.75 (d) 2.85
(b) a reduction in output impedance IES-2013
(c) an increase in input impedance ∆R / R
(d) the null for particular position of core Ans. (c) : Gauge factor =
∆L / L
IES-2013
0.21/120
Ans. (d) : In an LVDT, the two secondary windings are =
connected in differential mode to obtain the null for 0.1/100
particular position of core. 0.21 × 100 21
= =
The linear variable differential transformer is a type of 120 × 0.1 12
electrical transformer used for measuring linear 7
displacement. = = 1.75
It is a common type of electromechanical transducer 4
that can convert the rectilinear motion of an object to 153. An LVDT has the following specifications:
which it is coupled mechanically into a corresponding Input = 6.3 V,
electrical signal. Output = 5.2 V,
150. The strain gauge should have range ± 1.25 cm.
1. High gauge factor Then the output voltages produced due to core
2. Low resistance temperature coefficient movement from +1.1cm to –0.4 cm will be
3. High resistance respectively.
(a) +4.576 V and –1.664 V one of the metals. If the connecting material is different
(b) +2.288 V and –0.832 V than that of material of which thermocouple is made
(c) +4.0 V and –1.0 V then in presence of DC-voltage there will be again an
(d) + 2.0 V and –1.0 V induced emf.
IES-2013 157. The following transducer(s) may employ strain
gauge as a secondary transducer
Output 5.2
Ans. (a) : Sensitivity = = V / cm (a) Load cell only
Range 1.25 (b) Load cell and torque meter only
= 4.16 V/cm (c) Load cell, torque meter and accelerometer
For 1.1 cm, V1 = 4.16×1.1 = 4.576 V only
For – 0.4 cm V2 = 4.16× (–0.4) = –1.664 V (d) Load cell, torque meter, accelerometer and
154. A temperature sensitive transducer is subjected flow meter
to a sudden temperature change. It takes 10 sec IES-2012
for the transducer to reach steady-state. The Ans. (c) : Load cell, torque meter and accelerometer
time taken by the transducer to read half of the transducer is secondary transducer. Flow meter strain
temperature difference will be nearly gauge is not a secondary transducer
(a) 1.38 sec (b) 5.00 sec Load Cell- A strain gauge elastic member combination
(c) 8.62 sec (d) 10 sec arrangement used for measurement of load or weight is
IES-2013 called load cell.
Ans. (a) : Transducer reach at steady state at 10 sec i.e. Torque meter- A torque sensor, torque transducer or
5τ = 10 sec torque meter is a device for measuring and recording
the torque meter is a device for measuring and
τ = 2 sec recording the torque on a rotating system.
θ = θ0 (1–e–t/τ) Accelerometer- These transducer generates an
θ electrical signal output as results of mechanical
θ= 0
2 acceleration input to the unit.
1 158. One of the following can act as an inverse
= 1 − e− t / τ transducer
2
τ = 1.38 sec (a) Electrical resistance potentiometer
(b) LVDT
155. A 1 m length wire has a resistance of 150Ω.
(c) Piezoelectric crystal
When it is subjected to strain, its length
becomes 1.01m. The measurement is conducted (d) Capacitive transducer
by a strain gauge whose gauge factor is 2. The IES-2015, 2012
change in resistance of the wire is Ans. (c) : A piezoelectric crystal acts as an inverse
(a) 0.5Ω (b) 1.0Ω transducer because when a voltage is applied across its
(c) 2.0Ω (d) 3.0Ω surfaces, it changes its dimensions causing a mechanical
IES-2013 displacement.
The inverse transducer is defined as a device that
∆R / R converts an electrical quantity into a non-electrical
Ans. (d) : Gauge factor =
∆L / L quantity. A piezoelectric crystal acts as an inverse
∆R = Gauge factor × ∆L/L × R transducer.
0.01 159. A Hall effect transducer is generally used for
= 2× × 150 = 300×0.01 the measurement of
1
∆R = 3 Ω (a) Power (b) current
156. While measuring the voltage developed by a (c) displacement (d) voltage
thermocouple, it is found that there is always IES-2012
an offset voltage. This is due to Ans. (b) : A Hall effect transducer is generally used for
(a) a voltage across a thermocouple even at very the measurement of current.
low temperature The principle of Hall effect transducer is that if the
(b) some photoelectric voltage across the junction current carrying strip of the conductor is placed in a
due to ambient light transverse magnetic field, then the emf develops on the
(c) a barrier potential across the junction edge of the conductor.
(d) an additional thermocouple is formed due to 160. A digital linear displacement transducer
the connecting wires and one of the metals normally uses
IES-2013 (a) straight binary code
Ans. (d) : While measuring the voltage or any quantity (b) binary coded decimal
developed by a thermocouple, it is found that there is (c) Gray code
always an offset voltage. This is due to an additional (d) Hexadecimal code
thermocouple is formed due to the connecting wires and IES-2012, 1997
Ans. (c) : A digital linear displacement transducer LVDT (Linear variable differential transformer):-
normally uses Gray code. A digital linear displacement LVDT is used to calculate displacement and work on
transducer converts the displacement under the transformer principle. The working principle of the
measurement into digital data. A binary code is a major linear variable differential transformer or LVDT
disadvantage because of the fact that even with a small working theory is mutual induction.
displacement, several bits many change at once. Hence Piezoelectric Transducer- It is an electrical transducer
a code is usually chosen in which no more than one bit that can convert any form of physical quantity into an
changes at a time for instance, a gray code. electrical signal, which can be used for measurement.
161. The following transducer is used for accurate It is used to measure acceleration
and precise measurement of temperature Hall effect- Hall effect is a very useful phenomenon
(a) Thermistor and help to-
(b) Thermocouple (Alumel/Chromel) • Determine the type of semiconductor
(c) Semiconductor temperature sensor chip • Calculate the carrier concentration
(d) Platinum resistance thermometer • Determine the mobility
IES-2012 • Measure magnetic flux density
Ans. (c) : Semiconductor temperature sensor chip 164. A second order pressure transducer has a
transducer is used for accurate and precise measurement natural frequency of 30 rad/sec, static
of temperature. sensitivity K = 1.0µV/Pa. When a step pressure
Semiconductor temperature sensors which measures input of 8 × 104 M/m2 is applied, damped
variations in the forward voltage of a diode to determine frequency of 29.85 rad/sec is observed. The
temperature. To achieve reasonable accuracy, these are damping ratio of the transducer is
calibrated at a single temperature point, typically 25°C. (a) Zero (b) 0.707
162. Two strain gauges are used to measure strain (c) 1.0 (d) 0.1
in a cantilever, one gauge is mounted on the top IES-2011
of the cantilever and the other is placed at the Ans. (d) : Given,
bottom. The two strain gauges form two arms Natural frequency ( ωn) = 30 rad/sec
of wheatstone's bridge. This bridge damped frequency ( ωd) = 29.85 rad/sec
configuration is called. damping ratio ξ = ?
(a) a quarter bridge (b) a half bridge
(c) a full bridge (d) a null bridge We know that, ωd = ωn 1 − ξ 2 ⇒ 29.85 = 30 1 − ξ2
IES-2012 29.85
⇒ = 1 − ξ2
Ans. (b) : The two strain gauges form two arms of 30
wheat stone's bridge called half bridge. ⇒ 0.995 = 1 − ξ 2
Half bridge have two active strain-gauge
elements one is mounted in the direction of bending Now squaring on both sides
strain on one side of the strain top, the other is mounted (0.995)2 = 1 – ξ2
in the direction of bending strain on the opposite side 0.990025 = 1 – ξ2
(bottom) 0.009975 = ξ2
163. Match List-I with List-II and select the correct ξ = 0.009975 = 0.0998
answer using the code given below the lists: 0.1
List-I List-II 165. Optical pyrometer is generally used to
A. Hot wire 1. Gas flow measure:
B. LVDT 2. Displacement (a) Low pressure (b) Low temperature
C. Piezoelectric 3. Current (c) High temperature (d) High pressure
D. Hall effect 4. Acceleration IES-2011
Codes: Ans. (c) : Optical pyrometer is generally used to
A B C D measure high temperature.
(a) 1 2 3 4
Optical pyrometer-The optical pyrometer is used for
(b) 4 2 3 1
measuring the temperature of the furnaces, molten
(c) 1 2 4 3
(d) 4 3 2 1 metals and other overheated material or liquids it is not
possible to measures temperature of the highly heated
IES-2011
body with the help of the contact type instrument.
Ans. (c)
A. Hot wire - Gas flow 166. A single strain gauge of resistance 120 Ω is
B. LVDT - Displacement mounted along the axial direction of an axially
C. Piezoelectric - Acceleration loaded specimen of steel (E = 200 GPa). The
D. Hall effect - Current percentage change in length of the rod due to
Hot wire - It is a type of passive transducer based on loading is 3% and the corresponding change in
resistive variation type- resistivity of strain gauge material is 0.3%. for
A hot wire probe is used in gas flow, while a hot-film is a Poisson's ratio of 0.3, the value of the gauge
for liquid flow factor is
(a) 1.3 (b) 1.5 Ans. (d) : Thermistor is a passive type transducer
(c) 1.7 (d) 2.0 thermistor need an external source for there operation.
IES-2010 Thermistors comes from the term thermally sensitive
∆R / R resistors. It is a very accurate, cost-effective sensor and
Ans. (c) : G.F. = for measuring temperature.
∆L / L Thermistors are in two types –
∆L 1. Negative temperature coefficients (NTC thermistors)
Strain (ε) = = change in length unstrained length
L 2. Positive temperature coefficients (PTC thermistors)
Gauge factor is in term of poisson's ratio (γ) :- In negative temperature coefficients (NTC) thermistors,
∂ρ / ρ its resistance decreases, temperature increase.
G.F. = 1 + 2γ + In positive temperature coefficients (PTC) thermistors
∂L / L
its resistance increases their temperature also increases.
∂ρ change in resistivity Only negative temperature coefficients thermistors used
Q =
ρ Unstrained resistivity in temperature measurement.
∆L 3 169. Consider the following statements regarding
Given γ = 0.3 , = = 0.03 Thermistor
L 100
∂ρ 0.3 1. It has a high sensitivity.
= = 0.003 2. It has a linear relationship with temperature.
ρ 100 3. It is a resistive device.
0.003 4. It can be used as a time-delay device.
G.F. = 1 + 2×0.3 +
0.03 Which of the above statements are correct?
= 1 + 0.6 + 0.1 (a) 1, 2, 3 and 4 (b) 2, 3 and 4 only
G.F.= 1.7 (c) 1, 3 and 4 only (d) 1, 2 and 3 only
167. Match List-I (Transducer) with List-II (Types IES-2010
of transducer) and select the correct answer Ans. (c) : Resistance vary according to temperature as
using the code given below the lists: per following equation–
List-I List-II 1
A. LVDT 1. Resistive = A + Bln (R) + C(ln(R))3
T
B. Strain Gauge 2. Inductive
Where A, B and C are steinhart - Hart coefficient.
C. Dielectric Gauge 3. Capacitive
D. Thermocouple 4. Self generating
Codes:
A B C D
(a) 2 3 1 4
(b) 4 3 1 2
(c) 2 1 3 4 Thermistor follows non linear relationship with
(d) 4 1 3 2 temperature.
IES-2010 170. Which of the following transducers requires a
Ans. (c) : LVDT:- The linear variable differential high input impedance preamplifier for proper
transformer is a type of electrical transformer is used for measurements?
measuring linear displacement. (a) Thermocouple (b) Piezoelectric
LVDT work under the principle of mutual induction. (c) Thermistor (d) L.V.D.T.
Strain gauge:- A strain gauge is a sensor whose IES-2010
resistance varies with applied force. Ans. (b) : Piezoelectric transducers requires a high
Dielectric Gauge:- The change in capacitance due to a input impedance preamplifier for proper measurements.
change in the dielectric is known by its corresponding When a varying potential applied to the proper axis of a
liquid level or thickness. crystal, there is a change in dimension of the crystal
Thermocouple:- Thermocouple doesn't need any which is known as 'Piezoelectric effect'. The elements
external source for its operation so it is an active or self which exhibit piezoelectric qualities are called as
generating type transducer. "Electro-resistive elements".
Piezoelectric transducer are mainly used for
168. The incorrect statement is: measurement of displacement. They can be used for
(a) Thermistor has a high sensitivity measurement of force, pressure or acceleration.
(b) Thermocouple does not require an external 171. Which of the following transducers is most
electric source for its operation suitable for monitoring continuous variations
(c) Platinum has a linear R-T relationship in very fine thickness of a material?
(d) Thermistor does not require an external (a) Diaphragm (b) Capacitor
electrical source for its operation (c) L.V.D.T. (d) Piezoelectric crystal
IES-2010 IES-2010
Ans. (b) : Capacitor is most suitable for monitoring Voltage
continuous variations in very fine thickness of a Electric field intensity =
distance
material. 150V
Capacitance of a capacitor = = 1500 V / mm
0.1mm
1
C ∝ 175. In an LVDT, there are two secondary coils
d
which are connected for a signal output. Which
So, as d changes will change considerably.
one of the following is correct?
The capacitive transducer uses the electrical quantity of (a) The coils are in series and in phase
capacitance for converting the mechanical into an opposition.
electrical signal. The input quantities causes the change (b) The coils are in parallel and in phase
of the capacitance which is directly measured by the opposition
capacitive transducer. The capacitors measure both the
(c) The coils are in series and in the same phase
static and dynamic changes. condition
172. Consider the following statements about (d) The coils are in parallel and in the same phase
ultrasonic condition.
1. The measurement is insensitive to IES-2008
viscosity, pressure and temperature Ans. (a) : In LVDT, there are two coils connected in
variations. series and in phase opposition so as to obtain the null
2. It has bidirectional measuring capability for a particular position of the core.
and can be used for any pipe size. Two secondary coils are wound symmetrically on each
3. It has good accuracy, fast response and side of the primary coil and the two secondary windings
wide frequency range. are typically connected in series opposing (Differential).
Which of the above statements is/are correct? 176. A resistance strain gauge of gauge factor 2 is
(a) 1 only (b) 1 and 2 only used as a transducer element. Neglecting
(c) 1, 2 and 3 (d) 3 and 1 only piezoresistive effects, what is the value of
IES-2010 Poisson's ratio?
Ans. (c) : Ultrasonic flowmeters have relative higher (a) 0.5 (b) 1
cost. Ultrasonic flow meter operates on pipe diameters (c) 1.6 (d) 2
ranging from 0.5 inch to 200 inch. IES-2008
Ultrasonic, vibrations of frequencies greater than the Ans. (a) : G = Gauge factor
upper limit of the audible range of humans that is γ = Poisson's ratio
greater than about 20 kilohertz.
G=1+2γ
173. A transducer that converts measured into the Given that, G = 2
form of pulse is known as
(a) active transducer (b) analog transducer 2 = 1 + 2γ
1
(c) digital transducer (d) pulse transducer γ = = 0.5
KVS TGT (WE)- 2018 2
Ans. (d) : A transducer that converts measured into the 177. Which one of the following transducers cannot
form of pulse in known as pulse transducer. Pulse measure flow in non conducting medium?
transducer use Piezo-electric element to convert force (a) Orifice meter
applied to the active surface of the transducer into an (b) Electromagnetic flow meter
electrical analog signal. (c) Turbine meter
174. A capacitive transducer is made of two (d) Rotameter
concentric cylindrical electrodes. The outer IES-2008
diameter of the inner cylindrical electrode is Ans. (b) : Electromagnetic flow meter transducers
4mm and dielectric medium is air. The inner cannot be used in non-conducting medium. Orifice
diameter of the outer electrode is 4.1 mm. meter measures volumetric flow rate. Rotameter is
When 150 V is applied across the electrodes, constant pressure drop type variable area flowmeter.
what is the electric field intensity? Electromagnetic flow meter do not put any obstruction
(a) 1500 V/mm (b) 3000 V/mm in the flow of fluid through them. These are used for
(c) 4500 V/mm (d) 6000 V/mm measurement of slurries and electrically conducting
fluid.
IES-2008
178. An ac LVDT is given 6.3 V input and produces
Ans. (a) : Given,
5.2 V for range of +0.5 inch. When the core is –
Inner diameter of outer cylinder = 4.1 mm 0.25 inch from the centre, what is the output
outer diameter of inner cylinder = 4 mm produced?
Therefore length of the airgap can be calculated as the (a) –2.0 V (b) + 2.0
difference of two cylinder diameters (c) –2.6 V (d) +2.6 V
d = 4.1 mm – 4mm = 0.1 mm IES-2008
Ans. (c) : Given that, Ans. (c) : Optical pyrometer is used to measure the
–0.25 inch when the core is moved from the centre. temperature of molten metal's, overheated material,
−0.25 boiler furnaces the working principle of this optical
= × 5.2V pyrometer is to match the object brightness of the
0.5 filament with in the device.
= –0.5 × 5.2 V
= –2.6 V The optical pyrometer is has high accuracy.
179. A strain gauge with a nominal resistance of 183. Which one of the following transducers is the
120Ω and gauge factor of 2 undergoes a strain most suitable for the measurement of linear
of 10–5. What is the change in resistance in displacement?
response to the strain (a) Strain gauge (b) LVDT
(a) 240Ω (b) 24Ω (c) Piezoelectric crystal (d) Microphone
(c) 2.4 × 10–3Ω (d) 2.4 × 10–2Ω IES-2006
IES-2008 Ans. (b) : LVDT transducers is the most suitable for the
Ans. (c) : Gauge Factor = 2 measurement of linear displacement.
Nominal resistance = 120Ω The linear variable differential transformer is a type of
∆R / R electrical transformer used for measuring linear
G.F. = displacement. A counter port to this device that is used
∆L / L for measuring rotary displacement is called a rotary
∆R / R
G.F. = , ( ∆L / L = ε ) variable differential transformer.
ε 184. The working principle of a Pirani gauge
∆R /120 pressure transducer is based on which one of
2=
10−5 the following?
∆R = 2×120×10–5 (a) Humidity of the medium
∆R = 2.4×10–3 Ω (b) Thermal conductivity of the medium
(c) Combustibility of the medium
180. Which one of the following is correct? The
generated emf of tachogenerator is (d) Electrical resistivity of the medium
(a) directly proportional to angular speed OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
IES-2006
(b) inversely proportional to angular speed
(c) Proportional to square root of angular speed Ans. (b) : The working principle of a pirani gauge
(d) proportional to square of angular speed pressure transducer is based on thermal conductivity of
IES-2008 medium. It is based on the heat transfer between a
heated sensing element (wire, plate or chip) and its
Ans. (a) : The tachogenerator is a direct type velocity
surrounding gas molecules.
transducer. It is essentially the opposite of an electric
motor since its input is a rotating shaft and its output is The pirani gauge measures the vaccum pressure
a voltage V0 proportional to the input angular dependent thermal conductivity from the heated wire to
velocity ωs . the surrounding gas.
185. Which of the following are used in making
V0 = k t .ωs resistance temperature detectors?
181. Which one of the following statements for a (a) Nickel (b) Tungsten
potentiometric transducer is correct? (c) Copperü (d) All these
(a) It is a zero order displacement transducer KVS TGT (WE)- 2016
(b) It is first order displacement transducer Ans. (d) : The making of resistance temperature
(c) It is a zero order temperature transducer detector is a used for measuring temperature. It has
(d) It is a second order displacement transducer. great stability accuracy and repeatability. The resistance
IES-2008 tends to be almost linear with temperature. The
Ans. (a) : Potentiometric transducer is a zero order resistance material used are Platinum, Copper, Nickel,
displacement transducer. Tungsten etc.
x ∝ e0 186. Which one of the following is the best method
x = k e0 of measurement of temperature of hot bodies
dx radiating energy in visible spectrum?
= k (differentiating both sides)
de0 (a) Thermocouple (b) Thermopile
So, it is a zero order displacement transducer. (c) Optical pyrometer (d) Bolometer
182. Which one of the following is used to measure OPSC Poly. Lect. (Instrumentation)-2018, Paper-II
temperature inside a boiler furnace? IES-2006
(a) Resistance thermometer Ans. (c) : Optical pyrometer is the best method of
(b) Bimetallic thermocouple measurement of temperature of hot bodies radiating
(c) Optical pyrometer energy in visible spectrum. Optical pyrometer is a
(d) Thermistor temperature measuring device that is used to measure
IES-2008 the temperature of molten metal's.
Advantages of optical pyrometer – Thermistors are widely used in inrush current limiters,
(i) The temperature is measure without contacting the temperature sensors (Negative temperature coefficients
heated body. Because of this property, the or NTC type), self regulating heating element (positive
pyrometer is used for a number of applications. temperature coefficient or PTC type). A operational
(ii) The optical pyrometer has high accuracy. temperature range of a thermistor is dependent on the
Disadvantages of optical pyrometer – probe type and is typically in between –100ºC and
(i) The accuracy of the pyrometer depends on the 300ºC.
adjustment of the filament current. 189. A piezoelectric transducers is a voltage source
(ii) The pyrometer is not used for measuring the of 10V with an internal impedance of 10 MΩ. It
temperature of clean gases. is connected to a digital oscilloscope with an
187. Match List-I (Type of Hygrometer) with List-II input impedance of 10MΩ directly. What is the
(Related process/Material) and select the voltage measured by the oscilloscope?
correct answer using the code given below the (a) 20 V (b) 10 V
lists: (c) 5 V (d) 2.5 V
List-I List-II IES-2005
A. Resistive hygrometer 1. Quartz crystal Ans. (c) : Apply voltage divider rule
B. Capacitive hygrometer 2. Lithium chloride
crystal
C. Microwave 3. Change in
refractometer dielectric
constant
D. Crystal hygrometer 4. Change in
frequency of 10 × 10
oscillator Vout =
10 + 10
Codes:
100
A B C D =
(a) 2 3 4 1 20
(b) 4 1 2 3 = 5V
(c) 2 1 4 3 190. Match List-I (Transducer) with List-II
(d) 4 3 2 1 (Measured Quantity) and select the correct
IES-2006 answer using the codes given below the lists:
Ans. (a) : Hygrometer is used for measurement of List-I List-II
humidity or amount of water vapour in the air. A. Hall Effect pick-up 1. Pressure
(a) Resistive hygrometer – Lithium chloride crystal B. Piezoelectric pick-up 2. Velocity of a fluid
(b) Capacitive – Change in dielectric C. Hot-wire anemometer 3. Flow rate
hygrometer constant D. Rotameter 4. Current
(c) Microwave – Change in frequency of Codes:
refractometer oscillator A B C D
(d) Crystal hygrometer – Quartz crystal (a) 4 3 2 1
Resistive hygrometer – In resistive hygrometers, the (b) 2 1 4 3
change in electrical resistance of a material due to (c) 4 1 2 3
humidity is measured. (d) 2 3 4 1
Capacitive hygrometer – The capacitive hygrometer IES-2005
gives the very accurate result. It is made by placing the Ans. (c) :
hygroscopic material between the metal electrodes. The
(a) Hall effect pick-up – Current
hygroscopic material can quickly absorb the water.
(b) Piezoelectric pick-up – Pressure
Microwave refractometer – The use of microwave
refractometer in humidity measurement. (c) Hot-wire anemometer – Velocity of a fluid
Crystal hygrometer – In crystal hygrometer the (d) Rotameter – Flow rate
hygroscopic crystal and the crystal having the coating of Hall Effect- Mainly lorentz force is responsible for the
hygroscopic material is used. hall effect when we place a current carrying conductor
inside a magnetic field, the conductor experiences a
188. Which one of the following transducers mechanical force to a direction depending upon the
requires power supply for its operation? direction of the magnetic field and the direction of
(a) Thermocouple (b) Photovoltaic cell current in the conductor.
(c) Piezoelectric crystal (d) Thermistor Piezoelectric pick-up- A piezoelectric transducer (also
IES-2005 known as a piezoelectric sensor) is a device that uses
Ans. (d) : Thermistor transducer requires power supply the piezoelectric effect to measure in acceleration,
for its operation the working principle of a thermistor is pressure, strain, temperature or force by converting this
that its resistance is dependent on its temperature. energy into an electrical charge.

Hot-wire anemometer- The hot-wire anemometer is a Ans. (d) : Temperature of thermistor increases which
device used for measuring the velocity and direction of cause reduction, in resistance of thermistor due to its
the fluid. negative temperature coefficient with decrease in
Rotameter- A Rotameter is a device that measures the resistance
volumetric flow rate of fluid in a closed tube.
correct?
(a) A piezoelectric pressure transducer can be
used for measuring both static and dynamic
pressures
(b) A resistance strain gauge type pressure
transducer cannot be used for dynamic 193. Which one of the following in simple elemental
pressure measurement. forms is not a pressure sensor?
(c) Vacuum levels lower than 1 micron can be (a) Cantilever beam
measured with an ionization gauge (b) Bourdon tube
(d) Accuracy of a manometer is affected by the (c) Diaphragm
shape or size of the tubes. (d) Bellows
IES-2005 IES-2005
Ans. (c) : The McLeod gauge or an ionization gauge Ans. (a) : Cantilever beam is not a pressure sensor.
can measure vacuums as high as 10–6 torr (0.1 mPa), Beam are not always supported at both ends. A
which is the lowest direct measurement of pressure that cantilever is a beam that is supported to fixed at only
is possible with current technology. one end.
192. Which one of the following correctly depicts A cantilever beam is a rigid structural element that is
the V-I characteristics of a typical bead supported at one end and free at the other as shown in
thermistor? figure.
(a)
194. Which one of the following is the principle

disadvantage of a piezoelectric transducer?
(b) (a) It can measure force only
(b) It cannot measure static conditions
(c) It is too small to handle
(d) It produces only d.c. voltage
IES-2004
Ans. (b) : The piezoelectric transducer is used for
dynamic measurement only, not suitable for static
(c) condition piezoelectric transducer has high-temperature
sensitivity.
Piezoelectric transducer are a type of electroacoustic
transducer that converts the electrical charges produced
by some forms of solid material into energy. The word
'piezoelectric' means electricity caused by pressure.
correct?
(d)
(a) the operation of LVDT can be adversely
affected by stray magnetic a.c. fields or by the
presence of larger masses of metal nearby
(b) Fitting a magnetic shield with a longitudinal
slot along it, over the transducer can largely
IES-2005 be beneficial
(c) Relatively small displacements are required LVDT is very sensitive and linear over a wide range of
for appreciable differential output motion.
(d) LVDT gives a high output and many times,
there is no need for amplification. It possesses
a high sensitivity, which is typically of about
40 V/mm.
IES-2004
Ans. (c)
All the statements are correct.

197. Which one of the following defines piezo-
resistive effect?
(a) Production of voltage in a crystal subjected to
mechanical strain
(b) Changes in the value of resistivity of a
conductor which is strained
(c) Creation of strain in a crystal when electricity
is passes through the crystal
(d) Increase in the frictional resistance of a
LVDT is transformer consisting of one primary winding sliding contact under the influence of
and two secondary winding S1 and S2 mounted on a magnetic field.
cylindrical former. IES-2004
Secondary windings are connected in series phase Ans. (b) : Piezo resistive effect- Piezo Resistive effect
opposition. is a change in the electrical resistivity of semiconductor
• The operation of LVDT can be adversely affected or metal when mechanical strain is applied.
by stray magnetic field In contrast to piezoelectric effect, the piezoelectric
• To reduce the effect of stray magnetic field; magnetic effect causes a changes in electrical resistance not in a
shielding with a longitudinal slots are used. electric potential.
• LVDT gives a high output and many times and there
is no need of amplification. 198. Consider the following statements:
• It possess a high sensitivity typically 40 V/mm. 1. A variable capacitance type transducer,
So, options a, b and d are correct. gives an output proportional to
But c is not correct Because, not small displacement are acceleration.
required for appreciable differential output. 2. LVDT is a self-governing type of
196. Consider the following statements relating to transducer
an LVDT type of transducer: 3. Eddy current type of transducer gives an
1. A soft iron core provides the magnetic output proportional to velocity
coupling between a primary coil and two 4. A piezoelectric transducer cannot be used
secondary coils, connected in series to measure static variables
opposition Which of these statements is/are correct?
2. The output is proportional to the (a) 1 and 2 (b) 1, 2 and 3
displacement of the iron core (c) 2 and 4 (d) 4 only
3. The device is very sensitive and linear over
IES-2003
a wide range of motion
4. This is a variable inductance transducer Ans. (d) : Piezoelectric transducer cannot be used to
Which of the statements given above are measures static variables.
correct? Piezoelectric transducer is used for measuring non-
(a) 1, 2 and 3 (b) 3 and 4 electrical quantities such as vibration, acceleration,
(c) 1 and 2 (d) 1, 2, 3 and 4 pressure and the intensity of sound.
IES-2004 • A variable capacitive type transducer, gives an
Ans. (d) : LVDT type of transducer - LVDT output proportional changes in capacitances.
transducer is a variable inductance transducer having In variable capacitance transducers, the distance
primary winding and soft iron core with two secondary between the two plates is variables.
winding connected in phase opposition. • It is used to measure physical quantities such as
A soft iron core provides the magnetic coupling displacement, pressure etc.
between a primary coil and two secondary coils. The • LVDT is a passive transducer gives output
output is proportional to the displacement of the iron proportional to displacement of soft iron core
core. between primary and secondary windings.

199. A hot-wire anemometer is device used to Ans. (d) :
measure LIST I LIST II
(a) Gas velocities (b) Pressure in gases
Venturi tube Flow
(c) Liquid discharge (d) Temperature
Optical tachometer Velocity
IES-2003, 2001
Linear variable
Ans. (a) : A hot wire anemometer is device used to
measure gas velocities. differential transformer Displacement
A hot-wire anemometer is a thermal transducer Pirani gauge Pressure
which has been widely used to measure instantaneous 203. Rochelle salt is a crystalline material used in
flow of velocity. producing
The use of hot-wire anemometer permits (a) velocity transducer
instantaneous flow velocity to be calculated from (b) photoelectric transducer
electric voltage measurements.
(c) piezoelectric transducer
200. Very small displacements are effectively
(d) differential transformer transducer
measured using
(a) LVDT (b) Strain gauge RPSC Vice Principal ITI-2016
(c) Thermistor (d) Tachogenerator IES-2002
IES-2003 Ans. (c) : Rochelle salt is a crystalline material used in
Ans. (a) : LVDT (Linear variable differential piezoelectric transducer.
transformer)- Piezoelectric transducer is used for measuring non-
LVDT is an electromechanical transducer that can electrical quantities such as vibration, acceleration,
turn rectilinear motion into a corresponding electric pressure and the intensity of sound.
signal. 204. The gauge factor of the material of strain gauge
Very small displacement can be measured is such that the resistance changes from 1000
accurately up to a few millions of a centimeter. ohms to 1009 ohms when subjected to a strain
The LVDT alters a linear dislocation from a of 0.0015. The Poisson's ratio for the material
mechanical position into a relative electrical signal
of the gauge wire is
including phase and amplitude of the information of
direction and distance. (a) 1.75 (b) 2
201. A temperature between 200ºC and 1000ºC may (c) 2.5 (d) 6
be measured conveniently by: IES-2002
(a) Thermistor Ans. (c) :
(b) Resistance thermometer ∆R / R
(c) Optical pyrometer Gauge factor =
∆L / L
(d) Copper-constantan thermocouple
∆L
IES-2003 Given that, strain = = 0.0015
L
Ans. (b) : Temperature ranges of different measuring
instruments R = 1000Ω , ∆R = 9Ω
Thermistor –55°C to 150°C 9
Resistance Thermometer –250°C to 1000°C 1000 9
Gauge factor = = =6
Optical pyrometer –700°C to 4000°C 0.0015 1.5
Copper constantan thermocouple –200°C to 350°C Gauge factor = 1 + 2 (poisson's ratio)
202. Match List-I (Transducers) with List-II 6 = 1 + 2 (µ)
(Measured Quantities) and select the correct Poisson ratio = 2.5
List-I List-II 205. Consider the following statements associated
A. Venturi tube 1. Displacement with electrical/electronic transducers:
B. Optical tachometer 2. Pressure 1. Mass-inertia effects are minimized
C. Linear variable 2. These transducers consume very little
differential transformer 3. Flow power.
D. Pirani gauge 4. Velocity 3. The response time is large
Codes: 4. Transmission and processing the signal for
A B C D the purpose of measurement are easier
(a) 1 4 3 2 Select the correct answer using the codes given
(b) 3 2 1 4 below:
(c) 1 2 3 4 (a) 1, 2 and 3 (b) 2, 3 and 4
(d) 3 4 1 2 (c) 1, 3 and 4 (d) 1, 2 and 4
IES-2002 IES-2001
Ans. (d) : Electrical/Electronics transducers are having Ans. (b) : Gauge factor of strain gauge is defined as the
following properties:- ratio of per unit change in resistance to the per unit
(1) Mass-Inertia effects are minimized. change in length of the element.
(2) These transducers consume very little power. ∆R / R
Gauge factor =
(3) The response time is small. ∆L / L
Transmission and processing the signal for the Gauge factor in a strain gauge must be high.
purpose of measurement are easier. 209. A variable reluctance type tachometer has 60
206. Consider the following statements: rotor teeth, the records 3600 counts/minutes.
A transducer converts The device speed is
1. mechanical energy into electrical energy (a) 60 r.p.s. (b) 1800 r.p.s.
2. mechanical displacement into electrical (c) 3600 r.p.s. (d) 7200 r.p.s.
signal IES-2001
3. one form of energy into another form of Ans. (c) : Given that,
energy Rotor teeth = 60
4. electrical energy into mechanical form. 3600counts 3600 counts
=
Which of these statement is/are correct? minutes 60 second
(a) 1 and 4 (b) 1 and 2 60counts
(c) 3 alone (d) 1 alone =
second
IES-2001 counts
Ans. (c) : A transducer converts one form of energy Device speed = 60 × 60(Rotor teeth)
second
into other form of energy. = 3600 rotations per second.
Usually a transducer converts a signal in one 210. Consider the following devices:
form of energy into a signal in another. 1. Anemometer
The process of converting one form of energy 2. Stroboscope
to another is known as transducer. 3. Accelerometer
207. Match List-I (Transducers) with List-II The correct sequence of these devices to
(Measured Qualities) and select the correct measure the rotational speed, vibration and
answer using the codes given below the lists: airflow, respectively is,
List-I List-II (a) 2, 3 and 1 (b) 2, 1 and 3
A. Capacitive transducers 1. Pressure (c) 1, 3 and 2 (d) 3, 2 and 1
B. Thermocouple 2. Torque IES-2001
C. Load cell 3. Displacement Ans. (a) Anemometer Airflow
D. Diaphragm 4. Temperature Stroboscope Rotational speed
Codes: Accelerometer Vibration
A B C D 211. The piezoelectric crystal voltage sensitivity is
(a) 2 4 3 1 defined as:
(b) 3 1 2 4 (a) voltage developed per unit stress
(c) 2 1 3 4 (b) field developed per unit stress
(d) 3 4 2 1 (c) voltage developed per unit force
(d) field developed per unit force
IES-2001
RPSC Lect. 2011, IES-2001
Ans. (d) :
Ans. (b) : The piezoelectric crystal voltage sensitivity is
Capacitive Transducers Displacement defined as field developed per unit stress. The voltage
Thermocouple Temperature sensitivity of the crystals is expressed by the ratio of the
Load cell Torque electric field intensity and pressure when the
Diaphragm Pressure mechanical deformation occurs in the crystals, it
208. Gauge factor of strain gauge is defined as the generates charges and this charge develops the voltage
ratio of a per unit change in the across the electrodes. The piezoelectric crystal is
direction sensitive.
(a) conductivity to the per unit change in applied
force acting on the element
(b) resistance to the per unit change in the length
of the element
(c) stress to the per unit change in strain of the
element
(d) current to the per unit change in the length of
the element
KVS TGT (WE)-2014
IES-2001
212. A semiconductor based temperature 216. A Hall effect transducer can be used to
transducer has temperature coefficient of – measure
2500µV/ºC. The transducer indeed is a (a) displacement, temperature and magnetic flux
(a) thermistor (b) displacement, position and velocity
(b) forward-biased pn junction diode (c) position, magnetic flux and pressure
(c) reverse-biased pn junction diode (d) displacement, position and magnetic flux
(d) FET IES-1999
IES-2000 Ans. (d) : Hall effect transducers can be used to
measure linear and angular displacement, position and
Ans. (b) : Forward biased p-n junction diode has
magnetic field etc.
temperature coefficient - 2500 µV/°C.
213. Pirani gauge is used for the measurement of
pressure in the range of
(a) 10–8 mm to 10–5 mm of Hg
(b) 10–3 mm to 10–1 mm of Hg
(c) 10 mm to 103 mm of Hg
(d) 105 mm to 108 mm of Hg
IES-2000
Ans. (b) : Pirani gauge:- The pirani gauge is a device
used to measure pressure, especially in vacuum systems
it was invented in the year 1906 by Marcello stefno
pirani, a German physicist it is based on a hot metal
wire that is suspended in a tube and exposed to gas
pressure media these hot metal wires are made of thin − IB IB  −1 
VH = = RH ,  RH = 
platinum wire it works by measuring the change in ned d  ne 
thermal conductivity and uses this measurement to n - Carrier density
obtain the pressure of system. Pirani gauge is used for t - Thickness
measurement of pressure in the range of 10–3 mm to 10– RH - Hall coefficient
1
mm Hg. VH - Hall voltage
214. The most light sensitive transducer for I - Current
conversion of light into electrical power is the B - Magnetic field
(a) photodiode 217. Load cell employ:
(b) solar cell (a) piezoelectric crystal (b) capacitor
(c) photoconductive cell (c) mutual inductance (d) strain gauges
IES-1999
(d) photovoltaic cell
RPSC Vice Principal ITI-2016 Ans. (d) : Load cells is a transducer that generates an
electric signal based on force to be measured. Load cells
IES-2000 use strain gauges to alter electric signal output based on
Ans. (a) : The most light sensitive transducer for force to be measured. Piezoelectric material is used in
conversion of light into electric power is the photo piezoelectric load cells but not piezoelectric crystals
diode cell. since they can't withstand high force.
The photodiode has very important advantages over the 218. An LVDT is used to measure displacement.
photo-conductive cell. These advantages are its The output of the LVDT is connected to a
response time is much faster so that it may be used in voltmeter of range 0 to 5 through an amplifier
applications in which light fluctuations occur at high having a gain of 250. For a displacement of 0.5
frequencies. mm, the output of the LVDT is 2 mV. The
The photo-conductive cell is useful only at very low sensitivity of the instrument would be:
frequencies. (a) 0.1 V/mm (b) 0.5 V/mm
215. The device possessing the highest (c) 1 V/mm (d) 5 V/mm
photosensitivity is a IES-1998
(a) photoconductive cell Ans. (c) : The output of LVDT = 2 mV
(b) photovoltaic cell Gain = 250
(c) photodiode Reading of voltmeter = Gain × output
= 2×250×10–3 = 0.5 V
(d) photo-transistor
Displacement = 0.5 mm
IES-1999
voltmeter reading 0.5V
Ans. (a) : The device possessing the highest Sensitivity = = = 1 V/mm
photosensitivity is a photoconductive cell. displacement 0.5mm

219. Strain sensing transducers are made of various 222. A resistance wire strain gauge with a gauge
materials in various sizes and shape. The factor of 2 is bonded a steel structural member
sensitivity of strain gauge is expressed in terms subjected to a tensile stress of 100 Mega
of gauge factor. For a certain application, a Newtons/meter2. The modulus of elasticity of
gauge factor of 100 is desired. The proper steel is 200 Giga Newton's per square meter.
strain gauge to be used in the case would be The percentage change in gauge resistance due
(a) Constantan strain gauge to the applied stress is
(b) Nichrome-V strain gauge (a) 0.1 (b) 0.2
(c) Semiconductor strain gauge (c) 0.4 (d) 0.5
(d) Platinum-tungsten alloy strain gauge UPSC Poly.Lect.10.03. 2019
IES-1998 IES-1998
Ans. (c) : For a semiconductor, Gauge factor is very Ans. (a) : Given that,
high (more then 100) for high sensitivity, higher value G.F. = 2 , stress = 100 MN/m2 Y = 200 GN/m2
of gauge factor is preferred. The resistance of the ∆R / R
G.F. =
semiconductor changes in applied strain unlike in the ε
case of metallic gauge where the change in resistance.
Stress 100 ×106 N / m 2
220. Bridge circuits using resistance temperature Q ε= =
Young's modulous 200 ×109 N / m 2
detectors (RTD's) in temperature
measurements usually employ the "three lead ε = 5 × 10 −4
system" so as to obtain ∆R
(a) higher sensitivity = G.F. × ε = 2 × 5 × 10 −4 = 10 −3
R
(b) better impedance matching ∆R
(c) compensation for signal wire resistance to the % = 0.1%
detector R
(d) reduction in power consumption 223. A variable reluctance type tachometer has 180
teeth on rotor. The speed of the shaft on which
IES-1998
it is mounted is 1200 rpm. The frequency of the
Ans. (c) : When temperature changes, the resistance of output pulses is
a conductor changes. RTD is used to measure (a) 1800 per second (b) 3600 per second
temperature using a resistance thermometer. (c) 4800 per second (d) 5600 per second
RTD is popularly known as resistance temperature IES-1998
detector.
Ans. (b) : No. of teeth = 180, Speed = 1200 r.p.m.
221. Which one of following additional devices is So, frequency of the output pulse will be
required in order to measure pressure using
LVDT? 180 × 1200
=
(a) strain gauge (b) Pilot tube minutes
(c) Bourdon tube (d) Rotameter 180 × 1200
=
IES-1998 60
Ans. (c) : Bourdon tube is used to measure pressure. A = 3600 / sec
Bourdon tube converts pressure into displacement then 224. In a piezoelectric crystal, application of
this displacement is converted into emf. mechanical stress would produces
The bourdon tube act as primary transducer and LVDT (a) plastic deformation of the crystal
which follows the output of bourdon tube act as a (b) magnetic dipoles in the crystal
secondary transducer. The bourdon tube senses the (c) electrical polarization in the crystal
pressure and converts it into a displacement. This setup (d) shift in the Fermi level
is used for measurement of pressure which is converted IES-1998
into electrical signal by LVDT. Ans. (c) : When piezoelectric material is placed under
mechanical stress, a shifting of the positive and negative
charge centers in the material takes places, which then
results in an external electrical field.
225. The most useful transducer for displacement
sensing with excellent sensitivity, linearity and
resolution is
(a) an incremental encoder
(b) an absolute encoder
(c) a LVDT
(d) a strain gauge
IES-1997
Ans. (c) : The most useful transducer for displacement
sensing with excellent sensitivity, linearity and
resolution is LVDT.
LVDT is the most widely used transducer for
converting the linear motion into proportional output (a) interferometer
electrical voltage. LVDT has several user as explained (b) absorption spectrometer
below-
(c) Refractometer
(1) LVDT is used as a secondary transducer for
(d) photometer
measurement of pressure with below or bourdon
tube acting as a primary transducer. IES-1996
(2) It is used for measurement of all displacements Ans. (b) :
ranging from fraction of mm to a few cm.
226. A variable reluctance type tachometer has 150
teeth on the rotor. The counter records 13500
pulses per second. The rotational speed is
(a) 4800 rpm (b) 5400 rpm The given block diagram represents the basic
(c) 6000 rpm (d) 7200 rpm arrangement of an absorption spectrometer.
IES-1997 Absorption spectrometer gives the measurement of
absorbed energy by the atom or molecule after which it
Ans. (b) : Given that, excite and gives the absorbed energy in the form of
Rotor teeth = 150 absorption spectrum.
Recorded speed = 13500 pulses per sec.
230. A wire strain gauge element subjected to a
No.of pulses / sec strain has a gauge factor of 2, a resistance of
Rotational speed = rps
No.of teeth or rotor 125 ohms and is of 1 m length. For a change in
length of the wire by 0.005 m, the change in the
13500
= resistance will be
150 (a) 0.25 ohm (b) 0.5 ohm
= 90 rps (c) 1.25 ohm (d) 2.5 ohm
Rotational speed in rpm = 90×60 rpm IES-1996
= 5400 rpm Ans. (c) : Given that,
227. For measuring temperature below 20 K with G.F. = 2
high accuracy, the most useful instrument is R = 125
(a) an optical pyrometer l=1m
(b) a thermistor-based thermometer ∆l = 0.005 m
(c) GaAs pn-junction diode thermometer
∆R = ?
(d) platinum resistance thermometer
∆R / R
IES-1997 Gauge factor =
Ans. (c) : For measuring temperature below with high ∆l / l
accuracy, the most useful instrument is GaAs junction ∆l
∆R = Gauge factor × R×
diode thermometer. l
228. If low pressure of the order of 10–6 mm of Hg is 0.005
= 2×125×
to be measured, the instrument of choice would 1
be = 250×0.005 = 1.25 ohm.
(a) compound pressure gauge 231. Which one of the following is not a transducer
(b) thermocouple vacuum gauge in the true sense?
(c) Pirani gauge (a) Thermocouple (b) Piezoelectric pickup
(d) ionization type vacuum gauge (c) Photovoltaic cell (d) LCD
IES-1997 IES-1996
Ans. (d) : If low pressure of the order of 10–6 mm of Hg Ans. (d) : From given options only LCD is not a
is to be measured, the instrument of choice would be transducer in the true sense LCDs are used in a wide
ionization type vacuum gauge. Low pressure of the range of applications including LCD televisions,
order of less than 1 kg/cm2 can be measured by the computer monitors, instrument panels, aircraft cockpit
different transducer listed below- display etc.
(i) Pirani gauge (ii) Thermocouple gauge (iii) Ionization Thermocouple, piezoelectric pickup and photovoltaic
cell all are the example of active transducer.
vacuum gauge (iv) McLeod gauge (v) Thermistor
Active transducer are those transducers, which uses
gauge (vi) Knudsen gauge (vii) Alphathron
their own developed voltage or current for giving the
229. The following figure represents the basic output signal.
arrangement of, a/an
232. Match List-I with List-II and select the correct (a) 30 m/s2 (b) 60 m/s2
answer using the codes given below the lists: (c) 90 m/s2 (d) 120 m/s2
List-I List-II IES-1996
(Name of the (Operation) Ans. (b) : F = kn
transducer) Where F = force, K = spring constant,
A. Bourdon tube 1. Fluid flow to resistance n = displacement
change F = 3×103 ×1×10–3
B. Hot wire 2. Velocity to pressure F = ma
anemometer
0.05 × a = 3×103×10–3
C. Hydrometer 3. Pressure to displacement
D. Pitot tube 4. Specific gravity to 3
a=
displacement 0.05
Codes: a = 60 m/s2
A B C D 236. A resistance strain gauge with a gauge factor of
(a) 1 3 2 4 2 is cemented to a steel member, which is
(b) 3 1 2 4 subjected to a strain of 10–6. If the original
(c) 3 1 4 2 resistance value of the gauge is 130 Ω, the
(d) 4 2 3 1 change in the resistance would be ________.
IES-1996 (a) 135 µΩ (b) 260 µΩ
Ans. (c) : Bourdon tube → used to convert pressure into (c) 120 µΩ (d) 320 µΩ
displacement. TSGENCO AE-2015
Hot wire anemometer → It converts the fluid flow to Ans. (b) : Gauge factor =2
the change in resistance. strain= 10–6 = ε R = 130Ω
Hydrometer → Used for the measurement of specific
∆R
gravity. = G f .ε
Pitot tube → It is used for measurement of velocity of R
flowing fluid. ∆R = 130 × 2 × 10–6
233. Pirani gauge is used to measure ∆R = 260 × 10–6
(a) very low pressure ∆R = 260 µΩ
(b) high pressures 237. In the measurement of pH value, 10–11 moles of
(c) pressures in region of 1 atm hydrogen ions in 1 liter of liquid equals to
(d) fluid flow (a) 11 pH (b) 8 pH
IES-1996 (c) 2 pH (d) 3 pH
Ans. (a) : The Pirani gauge is a robust thermal TSGENCO AE-2015
conductivity gauge used for the measurement of the Ans. (a) : Number of mole = 10 –11
very low pressure. Such gauges cover the pressure pH = –log10(m)
range 10–5 to 1 mbar.
pH = –log1010–11
234. In a thermocouple, two metal junctions pH = 11
between metals M1 and M2 are kept at
temperatures T1 and T2. The thermocouple emf 238. Thermocouple made of ________ conductors
is produced because has lowest temperature sensing range
(a) M1 and M2 are similar and T1 and T2 are also (a) Nickel Chromium/Constantan
similar. (b) Iron/Constantan
(b) M1 and M2 are dissimilar while T1 and T2 are (c) Copper/Constantan
also similar. (d) Nicrosil/Nisil
(c) M1 and M2 are similar while T1 and T2 are TSGENCO AE-2015
also dissimilar. Ans. (c) : Thermocouple made of copper/constantan
(d) M1 and M2 are dissimilar while T1 and T2 are conductors has lowest temperature sensing range.
also dissimilar. Because copper has highest conductivity and lowest
IES-1996 resistivity.
Ans. (d) : In a thermocouple two metal junctions 239. The drawbacks of strain gauges are
between metals M1 and M2 are kept at temperatures T1 S1 : Low fatigue life
and T2 the thermocouple emf is produced because M1 S2 : They are expensive, brittle and sensitive to
and M2 are dissimilar while T1 and T2 are also
temperature
dissimilar.
S3 : Poor sensitivity
235. An accelerometer has a seismic mass of 0.05 kg Choose the correct one:
and a spring constant of 3 × 103 N/m. The
maximum permissible displacement of the (a) S1 only (b) S1 & S2
mass is ±1 mm. The maximum measurable (c) S2 & S3 (d) S1 & S3
acceleration is RPSC VP/Suptd. ITI 05.11.2019
Ans. (c) : A strain gauge is a type of electrical sensor. 245. The torque transmitted by a cylindrical shaft is
The drawbacks of strain gauges are they are expensive, to be measured by using two strain gauges. The
brittle and sensitive to temperature, poor sensitivity. angles for mounting the strain gauges relative
240. Radiation pyrometers are used in the to the axis of the shaft for maximum sensitivity
are
temperature range of
(a) 0 – 500ºC (b) 500 – 1000ºC (a) ± 45º (b) ± 60º
(c) –250 – 500ºC (d) 1200 – 2500ºC (c) ± 90º (d) ± 180º
RPSC VP/Suptd. ITI 05.11.2019 APGENCO AE- 23.04.2017
Ans. (d) : A radiation pyrometer is a non-contact Ans. (a) : The torque transmitted by a cylindrical shaft
temperature sensor that infers the temperature of an is to be measured by using two strain gauges. For
object by detecting its thermal radiation emitted maximum sensitivity the strain gauges aligned at ± 45º
naturally temperature range of (1200 - 2500ºC). relative to axis of the shaft.
246. The most suitable pressure gauge to measure
241. The principle of operation of LVDT is based on
pressure in the range of 10–4 to 10–3 torr is
the variation of
(a) Bellows (b) Barometer
(a) Self Inductance (b) Mutual Inductance
(c) Strain gauge (d) Pirani gauge
(c) Reluctance (d) Permanence
UPPSC ITI Principal/Assitt. Director-09.01.2022
RPSC VP/Suptd. ITI 05.11.2019 Ans. (d) : Pirani Guage- The operation of a pirani
gauge depends on variation of the thermal conductivity
Ans. (b) : LVDT is an acronym for linear variable of a gas with pressure.
differential transformer. The principle of operation of
Pirani gauge is useful for pressures ranging
LVDT is based on the variation of mutual inductance. from 10–1 to 10–3 mm of Hg.
242. Which one of the following strain gauges has 247. An accelerometer has input range of 0 to 10g,
excellent Hysteresis characteristics? natural frequency 30 Hz and mass 0.001 kg.
(a) Bonded wire (b) Unbonded metal The range of the secondary displacement
(c) Bonded metal foil (d) Semi conductor transducer in mm required to cover the input
UPSC Poly.Lect.10.03. 2019 range is
Ans. (d) : Semi conductor device provide excellent (a) 0 to 2.76 (b) 0 to 9.81
hysteresis characteristics. (c) 0 to 11.20 (d) 0 to 52.10
It is less than 0.05%. APGENCO AE- 23.04.2017
243. The semiconductor strain gauges typically have Ans. (a) : Given, Acceleration = ω2 x
much higher gauge factors than those of At acceleration = 0, x = 0
metallic strain gauges, primarily due to: At acceleration = 10g
(a) higher temperature sensitivity 10g = ω2x = (2π × 30)2 x
(b) higher Poisson's ratio 10 × 9.8
(c) higher piezoresitive coefficient x= = 2.758mm
( 2π × 30 )
2
(d) higher magnetostrictive coefficient
APGENCO AE- 23.04.2017 248. The true r.m.s. voltmeter employs two
Ans. (c) : When a conductor is stretched or compressed, thermocouples in order to
due to the change in it's length and diameter it's (a) prevent drift
resistance changes. This property of the conducting (b) increase the accuracy
material is called "Piezoresistive effect". Due to this (c) increase the sensitivity
reason strain gauge are also called "Piezoresistive (d) cancel out the nonlinear effects of first
transducers," thermocouple
244. A piezo-electric type pressure sensor has a IES-2002
sensitivity of 1 mV/kPa and a bandwidth of 300 Ans. (d) : The true r.m.s. voltmeters employs two
Hz to 300 kHz. for a constant (dc) pressure of thermocouples in order to cancel out the non-linear
100 kPa, the steady state output of the sensor in effect of first thermocouple.
millivolt is The thermocouple used in the input section of
(a) 0 (b) 2 voltmeter is known as the measuring thermocouple
(c) 4 (d) 6 where as the thermocouple used in the feedback path is
APGENCO AE- 23.04.2017 called as balancing thermocouple.
Ans. (a) : Sensitivity = 1 mV/kPa 249. Hot wire anemometer is a device used to
Bandwidth = 300 Hz to 300 kHz measure the
DC pressure = 100 kPa (a) pressure in gases (b) liquid discharge
The steady state output of a Piezo-electric type sensor is (c) gas velocities (d) temperature
zero for static systems. The pressure input is dc OPSC Poly. Lect. (Instrumentation)-2018, Paper-II
pressure, the steady state output is zero. IES-2001
Ans. (c) : The hot wire anemometer is a device used for (c) Amplifies change in air volume
measuring the gas velocity and direction of the field. An (d) Does not exist
anemometer is a weather monitor instrument used to Nagaland PSC CTSE (Degree)-2016, Paper-II
measure wind speed. Ans. (b) : A Pneumatic amplifier amplifies differential
Hot wire anemometer use the principle that the impact pressure.
of wind will have a cooling effect on the wire. Hot wire A pneumatic amplifier is used to compare with a supply
anemometer determine the rate of cooling by either the air value with a supply input connected to a pneumatic
supply.
constant current or the constant temperature method.
256. A potentiometric type accelerometer can be
250. The use of thermocouple meters for ac used for measurement of vibration of
measurement leads to a meter scale which is frequencies
(a) Linear (b) Square law (a) lower than 50 Hz
(c) Logarithmic (d) Exponential (b) higher than 1 kHz
IES-1997 (c) higher than 10 kHz
Ans. (b) : Thermocouple junction i.e. e.m.f. is (d) from 100 Hz and higher
proportional to the square of current and voltage. So it is TNPSC AE-2008
square law device. Thermocouple junction works on the Ans. (a) : The seismic mass is connected between a
principle of the thermoelectric effect or seebeck effect spring and a dashpot since the natural frequency FN of
which states that the temperature difference between two the potentiometer accelerometer is generally less than
30 Hz, this type of accelerometer should be used in low
dissimilar electric conductor produces a voltage
frequency vibration measurement.
difference between them. Depending on the metal wires
used, a thermocouple is capable of measuring 257. Which of the following types of transducers can
temperature in the range of –2000C to +25000C. be used for the measurement of the angular
position of a shaft?
251. Bridgman gauges are used for measurement of 1. Circular potentiometer
(a) vacuum (b) medium pressures 2. LVDT
(c) high pressures (d) very high pressures
3. E-pickup
TNPSC AE-2008
4. Synchro pair
Ans. (c) : A Bridgman gauge is to be used to measure a (a) 1 and 2 (b) 2 and 3
pressure of 10,000 psi using a man-gain element having
(c) 1 and 4 (d) 3 and 4
a resistance of 100Ω at atmosphere pressure.
IES-2015, 1998
252. In a balanced lever gauge, the movement of the
Ans. (c) : Synchropair– It measures and compares two
lever arm is limited to
angular displacements and its output voltage is
(a) 180º (b) 90º approximately linear with the angular difference of the
(c) 10º (d) 5º axis of both the shaft.
TNPSC AE-2008 A circular potentiometer–
Ans. (a) : A lever is a simple machine made of three • It is also called rotary potentiometer.
parks two load arms and a fulcrum. In a balance lever
gauge the movement of lever arm as limit to 180º. • It is used to measure the angular position.
RVDT–
253. Elastic elements used for measurement of force
give • Rotary variable differential transformer
(a) high sensitivity and slow response • It measure angular displacement.
(b) low sensitivity and fast response LVDT–
(c) low sensitivity and slow response • Linear Variable, Differential Transformer or Linear
(d) none of these Variable Displacement Transducer.
TNPSC AE-2008 • It measure linear displacement.
Ans. (b) : Elastic elements used for measurement of 258. The function of the reference electrode in a pH
force give low sensitivity and fast response, the force is meter is to
measured is applied to the external busses of the (a) produce a constant voltage
providing ring. (b) provide temperature compensation
254. Hoop stress acts (c) provide a constant current
(a) in radial direction (d) measure average pH value
(b) in axial direction RPSC Vice Principal ITI-2016
(c) in both radial and axial directions Ans. (a) : A pH metre measures the difference in
(d) none of these electric potential between a pH electrode and a
TNPSC AE-2008 reference electrode.
Ans. (b) : Hoop stress is the stress that occurs along the 259. The aim of shielding an instrument is
pipes circumference when pressure is applied. Hoop (a) to prevent damage due to moisture
stress acts perpendicular to the axial direction. (b) to provide mechanical protection
255. A Pneumatic amplifier (c) to reduce the effect of stray magnetic field
(a) Amplifies flow (d) to increase the range of instrument
(b) Amplifies differential pressure Mizoram PSC AE/SDO-2012 Paper-III
Ans. (c) : The aim of shielding an instrument is to Ans. (a) : Piezoelectric or pick-up or transducer an emf
reduce the effect of stray magnetic field. is generated an external force is applied across certain
260. In a linear variable differential transformer crystalline materials such as quartz.
(LVDT). It is measure sound, vibration, acceleration and pressure
(a) all three windings have equal number of changes.
turns. 264. Ruby maser is preferred over ammonia maser
(b) two secondary windings have equal number because of ______.
of turns (a) More frequency stability
(c) the induced voltages in two secondaries are (b) More light intensity
unequal (c) Less effective
(d) the induced voltages in two secondaries are in (d) None
phase AAI-2015
KVS TGT (WE)- 2016 Ans. (a) : Ruby maser is preferred over ammonia maser
Ans. (c) : because of more frequency stability.
Ruby masers are the most sensitive and lowest noise
microwave amplifiers used in the field, yet they are
rugged and are not susceptible to the microscopic
failure.
Ruby masers are very low noise pre-amplifiers.
265. Which is not an active transducer
(a) Photo voltaic (b) Pirani-gauge
(c) Piezoelectric (d) Thermocouple
The linear variable differential transformer is a type of BARC Scientific Officer-2016
electrical transformer used for measuring linear BSNL(JTO)-2009
displacement. Ans. (b) : Pirani-gauge is not an active transducer. It is
LVDT induced voltage in two secondaries are unequal. a passive device. It consists of two wire filaments. One
V0 = Vs1 –Vs2 filament serves as a reference and is scaled in an
V0 = + Ve (V1 > V2){ Iron core upward move} evaluated glass, while the other filament is kept in a
V0 = –Ve (V2 > V1) {Iron core downword move} container connected to the source of pressure.
261. LDVT: 266. Which of the following required source operate
(a) Converts linear motion into electrical signal (a) Piezoelectric transducer (b) LVDT
(b) Translates electrical signal into linear motion (c) Thermo couple (d) None
(c) Helps measuring temperature BARC Scientific Officer-2016
(d) Can be used to sense angular displacement Ans. (b) : LVDT is a passive transducer device so it is
Nagaland PSC CTSE (Degree)-2018, Paper-I required any source for operating.
Ans. (a) : The linear variable-differential transformer It is works on the principle of mutual inductance and
(LVDT) is the most widely used inductive transducer to other device such as piezoelectric transducer and
translate linear motion into electrical signal. thermo couple are active transducer.
The two secondary windings are connected in series 267. A transducer resolution is 22.4m V/°C, what is
opposition in LVDT the temperature showing for voltage of 412mV
(a) 20.56°C (b) 18.39°C
262. Which is an active transducer?
(c) 27.04°C (d) 17.55°C
(a) Piezeo electric (b) Straingauge
(c) Pirani gauge (d) LVDT
AAI-2015
Resolution = 22.4 mV/0C
Ans. (a) : Piezeo electric transducer is an active Voltage = 412 mV
transducer. These devices utilize the piezoelectric
22.4 mV = 10C
characteristics of certain crystalline and ceramic
materials (such as quartz) to generate an electrical 412 mV = 412 × 1 C = 18.390C
0
signal. 22.4
Such transducer depend upon the principle that when 268. In a classical blood pressure measuring
pressure is applied on piezoelectric crystals, an instrument in which the doctor observes the
electrical charge is generated. rise and fall of mercury, the hand air pump is
263. Piezoelectric transducer measure _____ attached to a -
(a) Acceleration (b) Temperature (a) Isobar (b) Transducer
(c) Liquid level (d) Velocity (c) Manometer (d) Mercury column
AAI-2015 RRB SSE 21.12.2014, (Green)
Ans. (d) : In a classical blood pressure measuring 274. What are the advantages of using Electrical
instrument the hand air pump is attached a mercury transducers?
column mercury sphygmomanometer, manual device (a) Small and non-portable
for measuring B.P. (b) Large and non-portable
269. In C.G.S. system, the unit of strain is : (c) Large and portable
(a) cm/kg (b) m/kg (d) Reduce effects of friction
(c) no unit (d) None of these RRB JE- 31.08.2019, 10 AM-12 PM
RRB SSE 21.12.2014, (Green) Ans. (d) : A transducer is an electrical device used to
Ans. (c) : Strain is unit less quantities because of convert one form of energy into another form. The form
∆L Change in length of energy may be electrical, mechanical, thermal or
Strain σ = = optical.
L Length
Some advantage of electrical transducer-
270. In S.I system, unit of stress is : Attenuation can be done easily.
(a) kg/cm2 (b) N Mass inactivity effects can be reduced.
(c) N/m2 (d) Watt Friction effects can be reduced.
RRB SSE 21.12.2014, (Green) The O/P can be specified & recorded remotely at a
Ans. (c) : Stress has same unit like pressure distance from the sensing medium.
force N 275. Which of the following is correct?
Pressure/stress = =
area m 2 (a) Absolute pressure = gauge pressure +
271. Which of the following is piezo-electric atmospheric pressure
material? (b) Gauge pressure = absolute pressure +
(a) Quartz (b) Silica Sand atmospheric pressure
(c) Corundum (d) Polystyrene (c) Atmospheric pressure = absolute pressure +
RRB SSE 21.12.2014, (Yellow) gauge pressure
Ans. (a) : Quartz is a piezo-electric material. It is a hard (d) Absolute pressure = gauge pressure –
crystalline mineral composed of silica. atmospheric pressure
The atoms are linked in a continuous framework of RRB SSE 02.09.2015, Shift-II
SiO2. Ans. (a) : Absolute pressure= gauge pressure +
272. Pair of active transducer is atmospheric pressure
(a) Thermistors and solar cell Gauge pressure is positive for pressures above
(b) Thermocouple and thermistors atmospheric pressure
(c) Thermocouple and solar cell Gauge pressure is negative for pressure below
(d) Solar cell and LVDT atmospheric pressure.
RRB SSE 01.09.2015 Shit-I Gauge pressure is zero at atmospheric pressure.
Ans. (c) : Thermocouple and solar cell pair an example 276. In LVDT, the core is made up of :
of active transducer. An active transducer is a self- (a) Non-magnetic material
generating type transducer that can produce an electrical (b) Solid ferroelectric material
voltage or current output without utilizing any external (c) High permeability, nickel - iron hydrogen
power source. annealed material
273. ________ is used to measure pressure directly. (d) None of the above
(a) Rotameter (b) LVDT OPSC Poly. Lect. (Instrumentation)-2018, Paper-II
(c) Strain gauge (d) Bourdon tube Ans. (c) : An LVDT core is normally a cylinder made
RRB JE- 31.08.2019, 10 AM-12 PM from permeable magnetic material which provide
Ans. (d) : The Bourdon tube is the most frequency used inductive coupling between primary and secondary coil.
to measure pressure gauge because of its simplicity and Hence Nickel iron hydrogen annealed material is used.
rugged construction. 277. A single strain gauge has resistance of 120Ω
It convers ranges from 0-15 psig to 0-100,000 psig, as and it is mounted on the axial direction of
well as vacuum from 0 to 30 inches of mercury. axially loaded specimen of steel (Young's
modulus of steel is 200 GPa). The percentage
change in length of rod due to loading is 5%
and the corresponding change in resistivity of
strain gauge material is 0.1%. The Possion's
ratio is 0.3. What is the gauge factor?
(a) 1.53 (b) 1.38
(c) 1.84 (d) 1.62

Ans. (d) : We know that, Ans. (a) : E = 9 × 1010 N/m2
∂p / p 4500 4500 ×106 V − m
Gauge factor = 1+2µ + g= =
∂l / l E × 10−6 E N
µ = Poisson ration Vout = 127.3
Given poisson ratio n = 0.3 g× t×F
0.1/100 Now we know that V =
Gauge factor = 1 + 2 × 0.3 + A
5 /100
VA 127.3 × π× ( 0.01) × 9 ×10
2 10
= 1 + 0.6 + 0.02 F= =
= 1.6+0.2 gt 4500 × 106 × 4 × 0.002
G f 1.62 F = 100N
278. A microphone is an example of 283. In a rotameter, Pa is pressure above float, Pb is
(a) ultrasonic transducers pressure below float, A is the area of float, V is
(b) acoustic transducers the volume of the float, d1 is the density of float
(c) magnetic transducers material, d2 is the density of fluid and g is the
(d) inductive pressure transducers acceleration due to gravity. Which one of the
KVS TGT (WE)- 2016 following equations describes the equilibrium
of the float?
Ans. (b) : A microphone is an example of acoustic
(a) (Pb – Pa)A = Vg(d2 – d1)
transducer.
(b) (Pa – Pb)A = Vg(d2 + d1)
A microphone is a device that translates sound
vibrations in the air into electronic signals or sscribe (c) (Pa – Pb)A = Vg(d2 – d1)
them to recording medium. (d) (Pb – Pa)A = Vg(d2 + d1)
279. A pressure gauge used to measure vacuum
indicates the gauge pressure of 5 kPa. If the Ans. (a) : Difference in pressure × A =
atmospheric pressure is 100 kPa, then the Weight of float - Buoyancy forge
absolute pressure is :
(a) 105 kPa (b) 95 kPa
(c) 50 kPa (d) 20kPa
Ans. (a) :
Absolute pressure = Gauge pressure + Atmospheric
pressure
Pa = 100 + 5
Pa = 105kPa
280. Low pressure is measured using : ( Pb − Pa ) × A = Vg ( d 2 − d1 )
(a) McLeod gauge (b) Bourdon tube
(c) U - tube manometer (d) Diaphragm 284. When the reading of a pH meter changes from
OPSC Poly. Lect. (Instrumentation)-2018, Paper-II 5 to 7, the hydrogenion concentration of
Ans. (a) : A McLeod gauge is a scientific instrument solution is :
-6
used for measure very low pressure down to 10 Torr (a) Halved
(1.33 mPa). (b) Doubled
281. Measurement of viscosity involves measuring : (c) Increased 100 times
(a) Frictional force (b) Coriolis force (d) Decreased 100 times
(c) Centrifugal force (d) Buoyant force
OPSC Poly. Lect. (Instrumentation)-2018, Paper-II Ans. (d) : Increment in hydrogen concentration
∆H + = 10 ( 2 1 )
− PH − PH
Ans. (a) : Viscosity is the measure of fluid's resistance
∆H + = 10 ( )
to flow at given temperature. Hence measurement of − 7 −5
viscosity involves measuring frictional force.
1
282. The quartz crystal with Young's modulus ∆H + = 10−2 =
10 2
9×10 N/m with piezoelectric properties has a 100
diameter of 10 mm and thickness of 2 mm. Its 285. Identify the correct matches :
voltage sensitivity constant is 4500 V/µm. If the (A) Spirometer (i) Electric
voltage output is 127.3 V, then the applied load activity of
is : heart
(a) 100 N (b) 200 N (B) Sphygmo (ii) Respiratory
(c) 127.3 N (d) 6.4 N manometer volume
OPSC Poly. Lect. (Instrumentation)-2018, Paper-II measurement
(C) Plethysmograph (iii) Measuremen 1 10−3
t of change in T = = = 0.0125 × 10−3
volume of 80 × 10 3
80
body part T = 12.5 × 10 −6 sec
T = 12.5 µs
(D) Electrocardiograph (iv) Blood
pressure 288. A capacitive transducer uses two quartz
measurement diaphragms of area 550 mm2 each separated by
(a) A-i, B-iv, C-iii, D-ii a distance of 3.7 mm. A pressure of 750 kN/m2
applied to the top diaphragm produces a
(b) A-ii, B-iii, C-iv, D-i displacement of 0.7 mm. The capacity is 390 pF
(c) A-iv, B-i, C-ii, D-iii when no pressure is applied to the diaphragm.
(d) A-ii, B-iv, C-iii, D-i The value of the capacitance after the
OPSC Poly. Lect. (Instrumentation)-2018, Paper-II application of pressure of 750 kN/m2 is
Ans. (d) : (a) 400 pF (b) 451 pF
(i) Spirometer ⇒ Respiratory Volume measurement (c) 481 pF (d) 500 pF
(ii) Sphygmomanometer BSNL(JTO)-2009
⇒ Blood pressure measurement εA
Ans. (c) : C = 0
(iii) Plethysmograph d
⇒ Measurement of change in volume in body 1
parts. C∝
d
(iv) Electroeardiograph C1 d 2
⇒ Electric activity of heart. =
C2 d1
286. Identify the correct matches : Given that
(A) Mean free path (i) Optical Area of diaphragm = 550 mm2
pyrometer Distance (d1) = 3.7 mm
(B) Humidity (ii) Knudsen gauge Capacitance (C1) = 390 pF
(C) Heat transfer (iii) Sling Displacement (D) = 0.7 mm
psychrometer To find capacitance at 750 kN/m2 pressure
(D) Intensity of (iv) Hot wire Distance between plate ( d 2 ) = d1 − D
radiation anemometer = 3.7 − 0.7
(a) A-i, B-ii, C-iii, D-iv
d 2 = 3mm
(b) A-ii, B-i, C-iv, D-iii
(c) A-iii, B-iv, C-i, D-i d
c 2 = c1 × 1
(d) A-ii, B-iii, C-iv, D-i d2
OPSC Poly. Lect. (Instrumentation)-2018, Paper-II 3.7
Ans. (d) : = 390 × = 130 × 3.7
3
(i) Mean free path can be measured by Knudsen gauge. C = 481pF
2
(ii) Humidity can be measured by sling psychrometer
289. What is the frequency range of beta wave in
(iii) Heat transfer coefficient can be measured by hot human EEG?
wire anemometer. (a) 10 Hz to 30 Hz (b) 12.5 Hz to 30 Hz
(iv) Intensity of Radiations can be measured by optical (c) 4 Hz to 7 Hz (d) 15 Hz to 40 Hz
pyrometer OPSC Poly. Lect. (Instrumentation)-2018, Paper-II
287. We are given a delay line of unknown delay. If Ans. (b) :
a 100 kHz sinusoid is applied as input, the Frequency Band Frequency Brain stakes
output lags the input by 90º, if an 80 kHz Gamma (γ) 35 Hz Concentration
sinusoid is applied as input, the output is seen Beta (β) 12 - 35 Hz Anxiety
to be exactly in phase with the input. The delay Alpha (α) 8 - 12 Hz Very relexed
introduced by the line is
theta (θ) 4 - 8 Hz Deeply relexed
(a) 32.5 µs (b) 25 µs
delta (δ) 0.5 - 4 Hz Sleep
(c) 50 µs (d) 12.5 µs
290. The measurement of the speed of a rotating
BSNL (JTO)-2001 shaft by means of an electric tachometer is a :
Ans. (d) : Given that, (a) Direct Measurement
Frequency = 80 kHz = 80×103 (b) Secondary Measurement
delay line = time period = T (c) Tertiary Measurement
1 (d) All of these
T=
f RRB SSE 21.12.2014, (Red)

Ans. (c) : The measurement of the speed of a rotating (a) 5 rps (b) 50 rpm
shaft by means of an electric tachometer is another (c) 500 rpm (d) 50 rps
typical example of tertiary measurement. TNPSC AE-2008
291. A barometer measures : No.of flash minute
(a) Absolute pressure (b) Atmospheric pressure Ans. (c) : Speed of machine =
(c) Gauge pressure (d) Vacuum No.of pattern
RRB SSE 21.12.2014, (Red) 6000
N= N = 500 rpm
Ans. (b) : A barometer is a scientific instrument used to 12
measure atmospheric pressure, also called barometric 296. The pH value of a solution is defined as:
pressure. An Italian scientist named Torricelli built the (a) – log (H+ ion concentration)
first barometer in 1643. (b) log (H+ ion concentration)
292. The function of the reference electrode in a pH (c) – log–1 (OH-ion concentration)
meter is to: (d) –log (OH-ion concentration)
(a) produce a constant voltage IES-2001
(b) provide temperature compensation Ans. (a) : pH value of a solution is defined as the
(c) provide a constant current negative of logarithm (to the base 10) of the hydrogen
(d) measure average pH value ion concentrated in the solution.
1
IES-2000 pH = − log[H + ] = log
Ans. (a) : The most common method of measuring pH H+
value is by measuring a voltage. The electrode in a pH Its ranges from 0 to 14. pH values are used to compare
meter provides a voltage measurement of a solution's ion the relative strength of different acid and base solution.
concentration, a reference electrode is necessary because 297. Semiconductor thermometers have the
its potential essentially remains constant and independent disadvantage that they
of the solution and temperature relative to the solution (a) are not readily available and are expensive
being measured. The pH electrode can be use as
reference electrode's potential to determine how the (b) are fragile and have low sensitivity
solution's ion concentration compares to the reference. (c) are large in size and have a poor frequently
response
293. Liquid flow rate is measured using (d) none of these
(a) a pirani gauge (b) a pyrometer TNPSC AE-2008
(c) an orifice plate (d) a bourdon tube
APGENCO AE- 23.04.2017 Ans. (d) Advantage of semiconductor thermometer-
● They can be easily interfaced with control system,
Ans. (c) : An orifice plate or orifice plate flow meter is making different digital output configurations
a device used to measure the flow rate of fluid through a possible.
pipe. Basically it works on Bernoullis principle. ● Semiconductor devices are rugged with a good
Orifice plates are one of the most popular devices for the longevity
measurement and control of fluid flow. Orifice plates are ● They are inexpensive.
normally mounted between a set of orifice flanges and
are installed in a straight run of smooth pipe to avoid ● They are linear with accuracies of ±10 C or better
disturbance of flow patterns from fittings and values. Disadvantage of semiconductor thermometer
294. The differential pressure transmitter of a flow ● Limited range of operation
meter using a venturi tube reads 2.5 × 105 Pa ● Internal dissipation can cause upto 0.50C offset
for a flow rate of 0.5 m3/s. The approximate resulting in errors in temperature measurement.
flow rate in m3/s for a differential pressure 0.9 298. A digital displacement indicator based on a
× 105 Pa is linear voltage differential transformer (LVDT)
(a) 0.30 (b) 0.18 transducer and A/D conversion uses a LVDT
(c) 0.83 (d) 0.60 with a sensitivity of 1 m V/mm. If the smallest
APGENCO AE- 23.04.2017 displacement to be measured is 0.1 mm and the
Ans. (a) : Flow rate, m3/s, P = Pressure in pascal maximum displacement of the LVDT core is 10
cm, then the digital display required for the
Q∝ P instrument has to be
Q2 P 1
= 2 (a) 2 digit type (b) 2 digit type
Q1 P1 2
1
(c) 3 digit type (d) 3 digit type
0.9 × 105 2
Q2 = × 0.5 IES-1997
2.5 × 105
Q2 = 0.3 m3/s. Ans. (d) : For LVDT with a sensitivity of 1 mv/mm
295. A disc mounted on the shaft of a machine has with displacement of 0.1 mm.
12 pattern points. The number of flashes LVDT reading will be 1mV/mm × 0.1 mm = 0.1 mV.
projected on the disc by a stroboscope is 6000 with displacement of IOCM or 0.1 mm = 0.1 mV
in a minute. When the disc appears stationary 1
and it has single image of 12 points, the speed To display 0.1V-1kV, 3 digit type display is required.
of the machine will be 2
Ans. (a) : In binary data transmission DPSK is
(x) Data Acquisition Systems and preferred to PSK because a coherent carrier is not
required to the generated at the receiver.
Telemetry systems
4. Telephone traffic is measured
1. Consider the following statements regarding (a) In terms of grade of service
data acquisition systems: (b) In Erlangs
(a) Digital data acquisition systems are used (c) With echo cancellers
when wide frequency width is required. (d) None of these
(b) Analog data acquisition system are more Nagaland PSC CTSE (Degree)-2016, Paper-II
complex the digital systems. Ans. (b) : Telephone traffic is measured in terms of in
(c) Digital data acquisition systems are used Erlangs.
when the physical quality being monitored
has narrow bandwidth. 5. The FM telemetry as compared with AM
telemetry requires a channel that is
(a) 1 and 2 only (b) 1 and 3 only (a) equal to that of AM telemetry
(d) 1, 2 and 3 (d) 2 and 3 only (b) smaller than what is required for AM
telemetry
ESE-2022
(c) 100 times of that required for AM telemetry
Ans.(a) : Digital data acquisition systems are used
when the physical quantity being monitored has narrow (d) 10 times of that required for AM telemetry
bandwidth. Generally digital data acquisition ystem are RPSC Vice Principal ITI-2016
more complex than analog data acquisition system and Ans. (d) : The FM telemetry as compared with AM
this give a narrow range of bandwidth. telemetry requires a channel that is 10 times of that
2. Which of the following line telemetry systems required for AM telemetry.
are available? 6. Consider the following regarding essential
1. Voltage telemetry system functional operations of a digital data
2. Current telemetry systems acquisition system:
3. Positions telemetry systems 1. Handling of analog signals
4. Resistivity telemetry systems 2. Converting the data to digital form and
(a) 1, 2 and 3 only (b) 1, 2 and 4 only handling it
(c) 1, 3 and 4 only (d) 2, 3 and 4 only 3. Making the measurement
IES-2020 4. Internal programming and telemetry
Ans. (a) : The landline telementry system is classified Which of the above are valid in the stated
as: context?
• Voltage telementry system (a) 1, 2, 3 and 4 (b) 1, 3 and 4 only
• Current telementry system (c) 1, 2 and 3 only (d) 2 and 4 only
• Position telementry system IES-2017
Voltage telementry system:-
• A voltage telementry system transmit the measured Ans. (a) : Digital data acquisition system is used to
variable as a function of A.C. and D.C. voltage. process a sampling signal which is used to measure real
• It is used for adding several output voltage in series, analog signal and convert it into a digital signal for
with the condition that the measurement is linear. further processing. The function of digital data
Current telementry system:- acquisition system consists of handling analog signal,
converting the analog data to digital form and handling
• In the current telementry system the value of current data, measurement of data, internal programming,
is adjusted in a circuit to a corresponding measured
quantity and this value of current is determined by control and telementry.
an end device at remote place. 7. The bandwidth of a digitally recorded signal
Position telementry system:- primarily depends upon
• Transmitting instrument or device adjusts the (a) The physical properties of the system
relation between the signal corresponding to the components processing the signal
measurement. (b) the frequency at which the signal is sampled
• Receiving instruments convert these signal into (c) the frequency of the clock signal that is used
displacement. to encode binary values responding the signal
3. In binary data transmission DPSK is preferred (d) the frequency of the noise affecting signal
to PSK because quality
(a) a coherent carrier is not required to be IES-2013
generated at the receiver Ans. (b) : The bandwidth of a digitally recorded signal
(b) for a given energy per bit, the probability of primarily depend upon the frequency at which the signal
error is less is sampled.
(c) the 1800 phase shifts of the carrier are nf
unimportant Bandwidth of signal = s Hz
(d) more protection is provided against impulse 2
noise Where n = no. of bits
Mizoram PSC IOLM-, Paper-III Fs = sampled frequency.

8. Electrical voltage-based telemetering schemes 13. Some of the functional building blocks of a
used for short distances must necessarily have measurement system are:
(a) Low current level only Primary Sensing element (PSE)
(b) Small signal power only Variable conversion Element (VCE) or
S  Transducer
(c) High signal to noise ratio  >> 2  only Data Transmission element (DTE)
N 
(d) All of the above Variable manipulation Element (VME)
IES-2012 Data Presentation Element (DPE)
Ans. (d) : A voltage telementry system is used for short The correct sequential connection of a the
distance must necessarily have low current level small functional building blocks for an electronic
signal power and high signal to noise ratio. It transmits pressure gauge will be:
the measured variable as a function of AC or DC (a) PSE, VME, VCE, DPE, DTE
voltage. A slide wire potentiometer is connected in (b) PSE, VCE, VME, DTE, DPE
series with the battery. The signal transmitting medium (c) DTE, DPE, VCE, PSE, VME
is essentially a copper wire line.
(d) PSE, VCE, DTE, DPE, VME
9. Electrical positional system telemetering uses
for transmission of signal in IES-2002
(a) Two wires only Ans. (b) : Functional building block diagram of a
(b) Two or three wires only measurement system given below-
(c) Two or three or four wires only
(d) Two or three four or even five wires.
IES-2012
Ans. (d) : Electrical positional system telementry used
for transmission of signal in two or three or four wires PSE → Primary Sensing Elements.
or fives wire. According to the physical connection VCE → Variable Conversion Element.
between transmitter and receiver i.e. 'Channel' which VME → Variable Manipulation Element.
may consist of two, three or four wire. DTE → Data Transmission Element.
10. OTDR is the acronym for: DPE → Data Presentation Elements.
(a) Optical time domain reflectometry
(b) Optical transmission and detection ratio 14. Considering the following statements:
(c) Optical time deflection region 1. Use of digital computer along with
(d) Optimum transmission and detection ratio. transducer maked data manipulation easier.
IES-2006 2. Digital signals are not dependent on signal
Ans. (a) : An optical time-domain reflectometer amplifiers and so are easy to transmit
(OTDR) is an optoelectronic instrument used to without distortion and external noise.
characterize an optical fiber. An OTDR is the optical 3. Increased accuracy in pulse count is
equivalent of an electronic time domain reflectometer. possible.
11. Which one of the following types of landline 4. There are ergonomic advantages in
telemetry method has the advantage of presenting digital data
simplicity and is free from noise, leakage and The main advantages of digital transducers
supply voltage variations? include
(a) Current type (b) Voltage type (a) 1, 2 and 4 (b) 1, 2 and 3
(c) Position type (d) Impulse type (c) 2, 3 and 4 (d) 1, 2, 3 and 4
IES-2005 IES-1999
Ans. (c) : Position type of landline telementry method Ans. (d) : Advantages of digital transducer -
has the advantage of simplicity and is free from noise,
leakage and supply voltage variations. In position type (1) Use of digital computer along with transducer
telementry method, no moving part are used except maked data manipulation easier.
those connected to the transmitting primary element and (2) Digital signal are not depends on signal amplifier
receiver pointer. and so are easy to transmit without distortion and
12. In final stage of ecological succession dynamic external noise.
balance between species and physical (3) Increase accuracy in pulse count is possible.
environment takes place, which is called (4) There are ergonomics advantages in presenting
(a) progressive ecosystem digital data.
(b) ideal ecosystem 15. In data acquisition _______ block is used for
(c) stable ecosystem frequency measurement.
(d) climax ecosystem (a) Analog output (b) Multiplexer
RRB SSE-03.09.2015, Shift-III (c) Sample & Hold (d) Timer
Ans. (d) : In final stage of ecological succession UPRVUNL AE-2016
dynamic balance between species and physical
environment takes place, which is called climax Ans. (d) : A/D converter system, a counter/timer block
ecosystem. is used for frequency measurement.

04.
Digital Electronics
5. The 2's complement representation of (–541)10
(i) Number system decimal in hexadecimal is:
(a) DEE (b) DDD
1. BCD code of decimal number 15 is
(c) DEF (d) DE3
(a) 0000 1111 (b) 1111 UPRVUNL AE -19.07.2021, Shift-II
(c) 1000 0101 (d) 0001 0101
UPPSC ITI Principal/Asstt. Director-09.01.2022 Ans. (d) : ( 541)10 in binary ( 001000011101) 2
Ans. (d) : BCD code at decimal number is 1's complements of 001000011101 is -
1 5 1 1 0 1 1 1 1 0 0 0 1 0
00010101 + 1
BCD code are in 4 bit 1 1 0 1 1 1 1 0 0 0 1 1 2's complement
2. (454)8 is equal to (110111100011)2 = ( DE3)H
(a) (300)10 (b) (000101100)2 6. The Excess -3 code of decimal number 15 is:
(c) (A2C)16 (d) None of the above (a) 0100 1101 (b) 0100 1000
(c) 0100 1001 (d) 0010 1000
Ans. (a) : (454)8 = 4 × ( 8 ) + 5 × 81 + 4 × 80
2 UPRVUNL AE -19.07.2021, Shift-II
Ans. (b) : Excess -3 code for 15 = 0100 1000
= 256 + 40 + 4 Binary of 1 = 0001
= (300)10 0 0 0 1
3. Convert (329.54)10 to hexadecimal.
Add 3 = 0 0 1 1
(a) (149.8A3D70A)16 (b) (219.8A3D70A)16
0 1 0 0
(c) (149.8A70AD)16 (d) (219.8A70AD)16
ESE-2022 Binaryof 5 = 0 1 0 1
Ans. (a) : Add 3 = 0 0 1 1
1 0 0 0
Hence, Excess-3 code of decimal number 15 = 0100 1000.
7. Which of the following signed binary numbers
is equal to –13?
(a) 10000000 (b) 00001101
(329)10 = (149)16 (c) 10001101 (d) 10000111
Ans. (c) :
8. Let a denote number system radix. The value(s)

of radix (r) that satisfy the equation
(0.54)10 = (0.8A3D70A)16 144 = 12, is/are
So that, (a) Only 10 (b) 4
( 329.54 )10 = (149.8A3D70A )16 (c) Any value ≥ 5 (d) Only 12
4. What is (82)10 in base 5?
(a) (310)5 (b) (311)5 Ans. (c) : (144) r = 12r
(c) (312)5 (d) (313)5
(1×r 2 )+(4×r1 )+(4×r 0 ) = (1×r1 )+(2×r 0 )
UPPSC Poly. Tech. Lect.-22.03.2022, Paper -I
Ans. (c) : (82)10 = (?)5 r 2 +4r+4 = r+2
(r +2)2 = r+2
r + 2 = r +2
So any integer r satisfies this, but r must be greater than
5 as we have 5 in 144 are radix must be greater than any
(82)10 = (312)5 of the digits.
Digital Electronics 637 YCT

9. Which of the Following is/are self 14. The 2’s complement of –9 is :
complementing code ? (a) 11001 (b) 00111
(I) 8-4-2-1 code (II) Excess-3 code (c) 10111 (d) 10110
(III) Gray code (IV) 2421 code APPSC Poly. Lect. 15.03.2020
(a) Only I, II, and IV (b) Only III and IV
Ans. (c) :
(c) Only II and III (d) Only I, II and III
RPSC ACF & FRO 23.02.2021 Sign bit 2's compliment of actual binary
Ans. (a) : The 2421, 8-4-2-1 and the excess -3 code are
example of self-complementing codes. Such code have By converting –9 into binary equivalent = 1001
the property that the 9's complement of decimal number By taking 2's complement = 0111
is obtained directly by changing 1's to 0's and 0's to 1's therefore the value of 2's complement of (–9) is 10111.
in the code. 15. Which of the following is the correct answer
10. The 2's complement representation of -17 is when (11010)2 is subtracted from (11100)2 by
(a) 101110 (b) 101111 using the 1’s complement method?
(c) 111110 (d) 110001 (a) 01001 (b) 00001
UPMRC AM - 2020
Nagaland PSC CTSE (Degree)-2017, Paper-II (c) 10001 (d) 00010
IES - 2016 APPSC Poly. Lect. 15.03.2020
UJVNL AE-2016
Nagaland PSC (degree)-2008, Paper-II Ans. (d) : (11100 )2 − (11010 ) 2
Gate – 2001
Now,
Ans. (b) : Binary number of 17 = 10001
Check 2's complement range by complement formula
−2 n −1 to + 2 n −1 − 1
−25−1 to + 25−1 − 1
– 16 to + 15 (–17 does not lie in 2's range).
So increase 1 bit in MSB as '0'.
∴ 010001 [Q n = 6 in 2's range]
2's complement is –17 = 101111 16. The logic circuit given below converts a binary
11. When expressed in the binary system. 1.7510 is : code Y1Y2Y3 into
(a) 1.112 (b) 1.012
(c) 1.0012 (d) 1.1012
Ans. (a) : (1.75)10
2 1 1
0
0.75 × 2 = 1.50
0.50 × 2 = 1.00
0.00 × 2 = 0
(a) Excess -3 code (b) Gray code
(1.75 )10 = (1.11)2 (c) BCD code (d) Hamming code
12. When expressed in the octal number system, TNPSC AE-2019
110111101.112 is : ISRO Scientist Engg.- 2007, 2006
(a) (686.6)8 (b) (675.6)8 IES-1993
(c) (775.6)8 (d) (695.6)8
APPSC POLY. LECT. 14.03.2020 Ans. (b) :
Ans. (b) : (110111101.11)2 = ( X )8
(110111101.11) 2
= ( 675.6 )8
13. If (4310)x = (580)10, then the value of x is :
(a) 4 (b) 5
(c) 8 (d) 7 X1 = Y1
X 2 = Y 1⊕ Y 2
Ans. (b) : (4310) x = (580)10
X 3 = Y 1⊕ Y 2 ⊕ Y 3
4x 3 + 3x 2 + x = 580 Let Y1 = 1, Y2 = 1, Y3 = 1, then
4x 3 + 3x 2 + x − 580 = 0 X1 = 1, X2 = 0, X3 = 0
By substitution x = 5 So, the above conversion is binary to gray code.
17. The two numbers represented in signed 2's Ans. (a) : Range of n-bit 1's complement form
complement form are P = 11101101 and Q = = –(2n–1–1) to + (2n–1–1)
11100110. If Q is subtracted from P, the value for n=6, Range = –(26–1–1) to + (26–1–1)
obtained in signed 2's complement is = –31 to +31
(a) 1000001111 (b) 00000111 21. The greatest negative number which can be
(c) 11111001 (d) 111111001 stored in a computer that has 8-bit word length
ISRO Scientist Engg.-2013 and uses 2's complement arithmetic is
IES -2012 (a) –256 (b) –255
GATE-2008 (c) –128 (d) –127
Ans. (b) : P = 11101101 ISRO Scientist Engg. 2011, 2009
Q = 11100110 Nagaland PSC CTSE (Diploma)-2017, Paper- II
P − Q = P + ( −Q ) Here (–Q) means 2’s complement of IES - 1993
Q Ans. (c) : Range of 2’s complement representation of
number is – 2n–1 to + (2n–1–1)
The greatest negative number of 2’s complement is
–2n–1
As given that, n = 8 bit
= −28−1
= −27 = −128
Now
22. The number of bits in ASCII is
(a) 12 (b) 10
(c) 7 (d) 8
UPRVUNL AE-2016
Leaving the carry, Ans. (c) : ASCII code for alphabetic character requires
then P+Q = 00000111 7 bits. ASCII code stand for American standard code for
18. Decimal number represented by the binary information interchange. It is a 7-bit code the original
number 101101 is ASCII table is encoded, on 7 bits therefore it has 128
(a) (43)10 (b) (45)10 characters.
(c) (47)10 (d) (49)10 23. If (146)x + (313)x–2 = (246)8, then the value of
TNPSC AE-2008 base x is :
Mizoram PSC IOLM-, Paper-III (a) 5 (b) 6
Ans. (b) : (101101) 2 → (?)10 (c) 7 (d) 9
= 1 × 25 + 0 × 2 4 + 1× 23 + 1 × 22 + 0 × 21 + 1× 20
Ans. (c) : (146)x+(313)(x–2) = (246)8
= 32 + 0 + 8 + 4 + 0 + 1
1 × x 2 + 4 × x1 + 6 × x 0 + 3 × ( x − 2 ) + ( x − 2 ) + 3 × ( x − 2 )
2 1 0
= 45
Hence, (101101)2 = (45)10 = 2 × 82 + 4 × 81 + 6 × 80
x 2 + 4x + 6 + 3 ( x 2 + 4 − 4x ) + x − 2 + 3
19. The gray code of number 6 is
(a) 1100 (b) 1001
(c) 0101 (d) 0110 = 64 × 2 + 32 + 6
4x 2 − 8x + 21 + x − 2 = 128 + 38
4x 2 − 7x + 19 = 166
Ans. (c) :
Gray code is minimum error code 4x 2 − 7x − 147 = 0
(6)10 → (0110)2 → (0101)Gray 4x 2 − 28x + 21x − 147 = 0
( x − 7 )( 4x + 21) = 0
x=7
24. Gray code for number 7 is
(a) 1100 (b) 1001
(c) 0110 (d) 0100
20. The range of signed decimal numbers that can Ans. (d) : Binary number of (7) is 0111
be represented by 6-bit 1's complement Binary to gray conversion -
number is
(a) -31 to +31 (b) -63 to +63
(c) -64 to +63 (d) -32 to +31
GATE -2004
25. Given the decimal number -19, and eight bit 29. The decimal equivalent of the binary number
two's complement representation is given by (1011.011)2 is______
(a) 11101110 (b) 11101101 (a) (11.375)10 (b) (10.123)10
(c) 11101100 (d) None of these (c) (11.175)10 (d) (9.23)10
TSTRANSCO AE- 2018 Nagaland PSC (CTSE) Diploma-2017, Paper II
Ans. (a) : (1011.011)2 → ( ? )10
Ans. (b) : –19 = 2's complement of (+19)
= 2's complement of (010011) 1 × 23 + 0 × 2 2 + 1× 21 + 1× 20 + 0 × 2−1 + 1 × 2 −2 + 1 × 2−3
Q range of 2's complement- 1 1
8 + 2 +1+ +
−2 n −1 to 2 n −1 − 1 4 8
−25−1 to 25−1 − 1 3
11 +
–16 to 15 then –19 is not exist between –16 to 15 then 8
1 bit increase in MSB as 0 = (010011) (11.375)10
−26−1 to 26−1 − 1 30. What is the addition of the binary numbers
−25 to + 25 − 1 11011011010 and 010100101?
(a) 0111001000 (b) 1100110110
−32 to + 31
(c) 11101111111 (d) 10011010011
Now –19 exist between –32 to +31 Nagaland PSC (CTSE) Diploma-2017, Paper II
If we taken n = 6, then (–19) comes in this range
00010011, 2's complement = 11101101 Ans. (c) :
26. Which of the following binary number is equal 1 1 0 1 1 0 1 1 0 1 0
to octal number 66.3 +0 0 0 1 0 1 0 0 1 0 1
(a) 101101.100 (b) 1101111.111 1 1 1 0 1 1 1 1 1 1 1
(c) 111111.1111 (d) 110110.011
ISRO Scientist Engg.-2007 31. A three digit decimal number requires_____for
Ans. (d) : (66.3)8 = (?)2 representation in the conventional BCD
(66)8 = (110110)2 format.
( 0.3)8 = (0.011)2 (a) 3 bits
(c) 12 bits
(b) 6 bits
(d) 24 bits
(66.3)8 = (110110.011)2 Nagaland PSC (CTSE) Diploma-2017, Paper II
27. If one of the code words of a Hamming (7,4) Ans. (c) : The number of bits needed to represent a
code is 0001011, which of the following cannot given decimal number is always greater than the
be the valid code word in the same group?
number of bits required for a straight binary encoding of
(a) 0011101 (b) 0101100
(c) 0011010 (d) 1110100 the same.
ISRO Scientist Engg. -2020 Hence, a three digit decimal number requires 12 bits for
representation in BCD format.
Ans. (c) : As given that, Hamming code (7, 4) is
0001011 32. The representation of the decimal number
Note- The minimum bits change between any valid (27.625)10 in base-2 number system is
hamming codes is 3. (a) 11011.110 (b) 11101.101
Then in option (a), (b) and (d) Hamming code change 3 (c) 11011.101 (d) 10111.110
or more than three but option (c) code -0011010 is Nagaland PSC (CTSE) Diploma-2017, Paper II
change two bits only. So 0011010 can’t be a valid Ans. (c) :
Hamming code of same group.
28. Which of the following statement is wrong?
(a) (1000.64)8 = (1000000000.1101)2
(b) (512.512) = (4022.224)5
(c) (2202)6 = (426)11
(d) (0.23)4 = (0.1011)2
Ans. (c) :
(2202)6 = (426)11
LHS -
= 2 × 63 + 2 × 6 2 + 0 × 61 + 2 × 60
= 432 + 72 + 2 = (506)10 (27)10 = (11011)2 (.625)2 = (.101)
RHS - (27.625)10 = (11011.101)2
= 4 × 112 + 2 × 111 + 6 × 110 33. Octal code of decimal number 27 would be
= 484+28 = (512)10 (a) 010110 (b) 011011
Hence, LHS ≠ RHS (c) 110110 (d) 101010
= (2202)6 ≠ (426)11 UPRVUNL AE– 11.06.2014
Ans. (b) : (27)10 = (33)8 Ans. (d) : In two's complement negative number system
8 27 3 zeros padded for left shift and sign extension for right.
In shift 1's complement negative number system ones
3 padded to left shift and sign extension for right shift.
= ( 011011)2 Sign extension (abbreviated as text) is the operation in
computer arithmetic of increasing the number of bits of
Octal equivalent of (27)10 is (33)8 and binary equivalent binary number while preserving the number's sign
of (33)8 is (011011)2. (positive/negative) value. This is done by appending
34. 2's complement of binary number 0101 is digits to the most significant side of number.
(a) 1011 (b) 1111 39. Compute the hamming distance between two
(c) 1101 (d) 1110 valid code words 101101 and 001100
Nagaland PSC (CTSE) Diploma-2017, Paper II (a) 3 (b) 1
Ans. (a) : Binary Number = 0101 (c) 4 (d) 2
TNPSC AE - 2018
Ans. (d) : X1 = 101101 X2 = 001100
X1 ⊕ X2 = 100001
total no. of 1's = 2 Hence, Hamming
35. (100101)2 is equal to decimal number distance will be 2.
(a) 47 (b) 37 40. Find the faulty even parity code
(c) 21 (d) 17 (i) 100110010
Nagaland PSC (CTSE) Diploma-2017, Paper II (ii) 011101010
(iii) 10111111010001010
Ans. (b) :
(a) only (ii) (b) only (iii)
(100101)2 = 1 × 25 + 0 × 2 4 + 0 × 23 + 1 × 2 2 + 0 × 21 + 1 × 20 (c) both (ii) and (iii) (d) both (i) and (iii)
= 32 + 4 + 1 TNPSC AE - 2018
= ( 37 )10 Ans. (a) : Number of 1's in (i) is 4 i.e. even parity.
36. Octal number 12 is equal to decimal number No. of 1's in (ii) is 5 i.e. not even parity.
(a) 8 (b) 9 No. of 1's in (iii) is 10 i.e. even parity.
(c) 10 (d) 11 In the case of even parity,
If a number of 1’s is even, the parity bit value is 0
If a number of 1’s is odd, the parity bit value is 1
Ans. (c) : (12 )8 = ( ? )10 I case of odd parity,
= 1 × 81 + 2 × 80 If a number of 1’s is odd, the parity bit value is 0.
= 8+2 41. With 2's complement representation, the range
of values that can be represented on data bus of
= (10 )10
an 8-bit microprocessor is given by
37. Obtain the 16's complement of ABAB (a) –128 to 127 (b) –128 to 128
(a) 5455 (b) 5554 (c) –127 to 128 (d) –256 to 256
(c) 5557 (d) 5655 GPSC Asstt. Prof. 11.04.2017
TNPSC AE - 2018 Ans. (a) : For 2's Complement representation, the range
Ans. (a) : 15's complement of ABAB - of values that can be represented on data bus of an 8-bit
15 15 15 15 microprocessor (n = 8) is -
−2 n −1 to + 2n −1 − 1
A = 10, B = 11 − A B A B
5 4 5 4 −28 −1 to + 28−1 − 1
−128 to + 127
5 4 5 4
42. In a single error correcting hamming code the
16's complement = + 1 number of message bits in a block is 26. The
5 4 5 5 number of check bits in the block would be
(a) 3 (b) 4
38. In 2's complement negative number system (c) 5 (d) 7
_____ padded for left shift and ______ for right Mizoram PSC AE/SDO-2012 Paper-III
shift. In 1's complement negative number
Ans. (c) : Total Number of bits = 26
system ______ padded to left shift and ______
for right shift. Number of bit = 2n − ( n + 1)
(a) Zeros, sign extension, zeros, ones 26 = 2n − ( n + 1)
(b) Zeros, ones, zeros, ones
(c) Zeros, ones, ones, sign extension From given option when we puts n = 5 then we get 26
(d) Zeros, sign extension, ones, sign extension total number of bits i.e.
TNPSC AE - 2018 if n = 5 then total number of bit = 26
43. Hexadecimal number F is equal to octal (c) 101001010, 110001100, 110011111
number (d) 110001100, 101001010, 110001111
(a) 14 (b) 15 ESE-2022
(c) 16 (d) 17 Ans. (d) : Decimal to Binary
Mizoram PSC IOLM -2018, Paper II (396)10 = (?)2
Ans. (d) : Hexadecimal number F equal in decimal is
15. (15)10
8 15 7
1
(15)10 = (17)8
44. Binary number 1101 is equal to octal number
(a) 15 (b) 14
(c) 12 (d) 11
UPRVUNL AE-2016
Ans. (a) : (1101) = (?) = 001 101 (396)10 = (110001100)2
2 8
= (15)8 Decimal to gray code-
(396)10 = (110001100)2
45. The number FF in hexadecimal system has
equivalence in decimal system to
(a) 245 (b) 255
(c) 265 (d) 275
Ans. (b) : ( FF )16 = (?)10 = 15 × 161 + 15 × 160 (101001010) -gray code
= 240 + 15 49.
The four bit Gray code corresponding to the
= ( 255 )10 binary code 0011 is
(a) 1100 (b) 0001
46. An equivalent 2's compliment representation of (c) 0011 (d) 0010
the 2's compliment number 1101 is UPPCL AE- 31.12.2018
(a) 110100 (b) 001101 Ans. (d) :
(c) 110111 (d) 111101
GATE - 1998
Ans. (d) : Binary = 1 1 0 1
1's complement = 0 0 1 0 50. The decimal number 76 in hexadecimal and
BCD number system is respectively
+1 (a) C4, 0111 0110 (b) 3E, 0010 0101
2's complement = 00 0011 (c) 4C, 0010 1100 (d) 4C, 0111 0110
1's complement = 111100 UPPCL AE- 31.12.2018
+1 Ans. (d) :
2's complement = 111101 16 76 12 → C
47. Convert the following number system: 4
(743)8 = (?)10 ( 76 )
→ ( 4C )16
10
(a) 483 (b) 773 7 6
(c) 373 (d) 479 now
0111 0110
= (01110110)BCD
Ans. (a) : (76)10 → (01110110)BCD
(743)8 = (483)10 51. Binary 1 & 0 corresponding to-
7 × 82 + 4 × 81 + 3 × 80 (a) They are numbers
= 448 + 32 + 3 (b) AC positive and negative cycle
= ( 483)10 (c) They are two different DC voltages
(d) They are two different AC voltage
48. Represent the decimal number 396 in binary, UPPCL AE-16.11.2013
Gray and excess-3 codes respectively. Ans. (c) : The binary number '1' and '0' provides the
information about two different stages of DC level. It
(a) 110001100, 101011010, 110001111 provides the information about switching condition of
(b) 110001010, 101101011, 110010000 circuit.
52. The Excess-3 code for decimal number 72 is- 57. What is the binary number equivalent to
(a) 10100101 (b) 10010000 decimal number for, (151.75)10?
(c) 01110101 (d) 01001011 (a) 10000111.11 (b) 11010011.01
UPPCL AE-16.11.2013 (c) 00011100.00 (d) 10010111.11
Ans. (a) : ( 72 )10 = ( ? ) Ex −3 UPSC JWM-2016
Ans. (d) : (151.75)10
7 → 0111
Add(3) → 0011
1010
2 → 0010
Add(3) → 0011
0101
Now ( 72 )10 = (10100101)Ex −3
53. How many 1's are present in the binary
representation of (256×7) (4×16)(9×4096) + 5
(a) 8 (b) 11
(c) 9 (d) 10 (10010111.11)2 = (151.75)10
UPPCL AE-16.11.2013 58. Multiplication of two binary numbers 011 and
Ans. (a) : ( 7 × 256 )( 4 ×16 )( 9 × 4096 ) + 5 110 is
= ( 2 + 2 + 2 )( 2 )( 2 × 2 )( 2 + 2 )( 2 ) + ( 2 + 2 )
2 1 0 8 2 4 3 0 12 2 0 (a) 10010 (b) 11001
(c) 11100 (d) 01110
= ( 22 + 21 + 20 ) × ( 214 ) × ( 215 + 212 ) + ( 22 + 20 ) UJVNL AE-2016
= ( 216 + 215 + 214 ) × ( 215 + 212 ) + ( 22 + 20 ) Ans. (a) :

= 231 + 230 + 2 29 + 2 28 + 2 27 + 2 26 + 2 2 + 20
= 1 × 231 + 1× 230 + 1 × 229 + 1× 2 28 + 1 × 227 + 1 × 226
+1 × 2 2 + 1 × 2 0
Hence, no. of 1's is equal to 8.
54. The binary equivalent of decimal 107 is 59. What is the value of b in the conversion 1610 =
(a) 1001011 (b) 1101011 (100)b?
(c) 1101100 (d) 1001101 (a) 2 (b) 8
UPSC JWM-2016 (c) 6 (d) 4
Ans. (b) : 107 = (?)2 UJVNL AE-2016
Ans. (d) : (16 )10 = (100 )b
1 × 101 + 6 × 100 = 1× b 2 + 0 × b1 + 0 × b 0
10 + 6 = b2
b2 = 16
b=4
60. What device will perform the conversion of 4
bit BCD code to seven segment code required
107 = (1101011)2 to drive a LED read out
55. One hexa-decimal digit is sometimes referred (a) Decoder BCD to decimal
to as: (b) Full adder
(a) Byte (b) Nibble (c) Subtractor
(c) Group (d) Instruction (d) Demultiplexer
UPSC JWM-2016 UJVNL AE-2016
Ans. (b) : One hexa-decimal digit is sometimes Ans. (a) : A display decoder is used to convert a BCD
referred to as Nibble. or a binary code into a 7 segment code to drive a LED
56. The hexa-decimal equivalent of the octal readout. It generally has 4 input lines and 7 output lines.
number 762.013 is 61. The binary fraction 0.0111 in decimal form is
(a) 0F7.867 (b) 1F2.058 equal to
(c) 1E8.126 (d) 1B6.778 (a) 0.2065 (b) 0.4375
UPSC JWM-2016 (c) 0.8017 (d) 0.1100
Ans. (b) : ( 762.013)8 = (111 110 010 . 000 001 011)2 UJVNL AE-2016
= ( 0001 1111 0010 . 0000 0101 1000 )2 Ans. (b) : (0.0111)2
↓ ↓ ↓ ↓ ↓ ↓ = 0 × 2−1 + 1× 2− 2 + 1× 2− 3 + 1× 2− 4
=( 1 F 2 . 0 5 8 )H = 0.25 + 0.125 + 0.0625
( 762.013 )8 (
= 1F2.058 )H = ( 0.4375 )10

62. What would be the equivalent of A3C5H 67. The octal equivalent of the decimal number 214
hexadecimal number is binary form? is
(a) 1010 0011 1100 1010 (a) 325 (b) 326
(b) 1010 0011 1100 1100 (c) 316 (d) 306
(c) 1100 1011 0011 1101 TNPSC AE-2013
(d) 1010 0011 1100 0101 Ans. (b) : (214)10 = (?)8
UKPSC Assistant Radio Officer Screening Exam.-2011 8 214 6
Ans. (d) : A3C5H
8 26 2
1010
  0011
  1100
  0101
 
A 3 C 5 3
63. The binary equivalent of the decimal number (214)10 = (326)8
78 is 68. Octal equivalent of number (236)16 is:
(a) 1001110 (b) 111001 (a) 1065 (b) 1066
(c) 1000111 (d) 110011 (c) 1067 (d) 1068
KVS TGT (WE)- 2017
KVS TGT (WE)- 2018
Ans. (a) : Ans. (b) : (236) 16 = (1066) 8
(236)16 = 2 × 162 + 3 × 161 + 6 × 160
= (566)10
Now,
64. For any positive integer m and t, the block ∴ ( 566 )10 = (1066 )8
length of Bose-Chaudhuri-Hocquenghem code
is 69. Number (–13) when represented in 1's
(a) 2t + 1 (b) n – t complement from is
(c) 2m –1 (d) 2m (a) 11011001 (b) 10100111
TNPSC AE-2014 (c) 11110010 (d) 00001111
TNPSC AE-2013
Ans. (c) : Bose-Chaudhuri-Hocquenghem, BCH code is
one of the most important and powerful class of Ans. (c) :
random-error-correcting cyclic polynomial codes over a
finite field with a particular chosen generator
polynomial.
n = 2m – 1
(n – k) ≤ mt
dmin ≥ (2t + 1)
65. For the code X1 = (000, 111) how many errors (13)10 = (1101)2
can be successfully detected? 1's complement (–13)10 = (11110010)
(a) upto two (b) upto three 70. Two's complement of the binary number
(c) upto seven (d) upto four 10010100 is
TNPSC AE-2014 (a) 01101011 (b) 01101100
Ans. (a) : The Hamming distance between two words is (c) 11101100 (d) 10001011
the number of difference between corresponding bits. TNPSC AE-2013
The minimum Hamming distance is the smallest Ans. (b) :
Hamming distance between all possible pairs in a sets Binary No. = 10010100
of words. 1's complement = 01101011
d(000, 011) = 2 d(000, 101) = 2 d(000, 110) = 2
d(011, 101) = 2 d(011, 110) = 2 d(101, 110) = 2 +1
66. The best representation of negative numbers is 2 's complement 01101100
(a) sign magnitude form
(b) 1's complement form 71. The binary representation of the Hexadecimal
number 3B7F is
(c) 2's complement form
(a) 0100100111101101
(d) 9's complement form (b) 0011101101111111
TNPSC AE-2013 (c) 0010010000001010
Ans. (c) : 2's complement form is the best (d) 0110001110111100
representation of all negative number in binary form. TNPSC AE-2013
Ans. (b) 8 4 2 1
Hexadecimal Number = 3B7F
use code - 0 1 1 0 → 6
3 = 0011
B = 1011 1 0 1 1 → 11( B )
7 = 0111 77. By taking 2's complement again of the 2's
F = 1111 complement of a binary one gets
(3B7F)16 = (0011101101111111)2 (a) The 1's complement
72. 2's complement of 10010010 is (b) The 2's complement
(a) 01101110 (b) 00101110 (c) The original number
(d) The sign magnitude form of the number
(c) 01001110 (d) 01100010
TNPSC AE-2008 Ans. (c) : By taking 2's compliment again of the 2's
compliment no. we gets the original number.
Ans. (a) :
Binary No. – 10010010 78. The hexadecimal number 'A0' has the decimal
1's complement – 01101101 value
(a) 80 (b) 258
1's complement – 01101101
(c) 100 (d) 160
+1 Nagaland PSC CTSE (Degree)-2016, Paper-II
2's complement 01101110 Ans. (d) : (A0)16 = A × 161 + 0×160
73. The binary equivalent of (11.6275)10 is = 10 × 16 + 0
(a) 1011.1010 (b) 1110011 = 160 + 0
(c) 101.0011 (d) 1011.0011 (A0)16 = (160)10
MPPSC Forest Service Exam.-2014 79. The 2's complement of the number 1101101 is
Ans. (a) : (a) 0101110 (b) 0111110
(11.6275)10 = (1011.1010)2 (c) 0110010 (d) 0010011
Ans. (d) : Binary Number = 1101101
1's complement = 0010010
+ 1
74. The decimal equivalent of the hexadecimal 80. The decimal equivalent of binary 1101.11 is
number (BAD)16 is (a) 9.75 (b) 13.75
(a) 5929 (b) 2989 (c) 11.50 (d) 11.75
(c) 3411 (d) 11013 Mizoram PSC Jr. Grade-2015, Paper-III
MPPSC Forest Service Exam.-2014 Ans. (b)
1 1
Ans. (b) : (1101.11)2 = 1× 23 + 1× 22 + 0 × 21 + 1× 20 + +
(BAD)16 = 11×162 + 10 × 16 + 13 ×160 2 4
= 11 × 256 + 160 +13 = 8 + 4 + 1 + 0.50 + 0.25
= 2816 + 160 + 13 (1101.11)2 = (13.75 )10
= 2989 81. BCD code is
(BAD)16 = (2989)10 (a) error correcting code
75. What is the 2's complement of 01101? (b) error detecting code
(a) 10010 (b) 10011 (c) both (a) & (b)
(c) 1100 (d) 1001 (d) none of the above
RPSC LECTURER-10.01.2016 Mizoram PSC IOLM-2010, Paper-II
Ans. (b) : Binary number = 0 1 1 0 1 Ans. (d) : BCD code is used to represent a decimal
1's complement → 1 0 0 1 0 number to a binary number, in BCD code each number
is expressed in 4 bit and we consider the number and
+ 1 their code from 0 to 9.
2's complement → 1 0 0 1 1 82. A signed integer has been stored in a byte using
2’s complement format. We wish to store the
76. Converting (10110110)2 to base 16 will result in same integer in 16-bit word. We should copy
(a) A615 (b) B616 the original byte to the less significant byte of
(c) C616 (d) D616 the word and fill the more significant byte with
RPSC LECTURE-10.01.2016 (a) 0
Ans. (b) (b) 1
(c) Equal to the MSB of the original byte
 
1011 0110
      = ( B6 )16
(d) Complement of the MSB of the original byte
 2 Mizoram PSC IOLM-2010, Paper-II
Ans. (c) : lets consider an example Ans. (d) : Conversion of binary to gray code -
42 in bytes 00101010
42 in words 0000000000101010
– 42 in bytes 11010110
– 42 in words 1111111111010110 89. Add 8 and 9 in BCD code.
Hence c is correct – (a) 00010111 (b) 00010001
83. 100 = 10 is true in _______ base (c) 01110111 (d) 10001001
(a) Any (b) 6 IES - 2019
(c) 5 (d) 10 Ans. (a) : 8+9 = (17) 10 → 10001
Mizoram PSC IOLM-2010, Paper-II Q 17 > 9
∴ add 0110
Ans. (d) : 100 = 10
10001 + 0110 = 00010111
Is true in 10 base or in decimal values only.
90. The addition of the two number (1A8)16 +
84. In the Hamming code 1001101, error has
(67B)16 will be :
occurred at _______ position. (a) (889)16 (b) (832)16
(a) 4 (b) 5 (c) (823)16 (d) (723)16
(c) 1 (d) 7 IES - 2017
Ans. (c) : Converting 1A8 into decimal-
Ans. (d) : =1×162+10×161+8×160
= 256 + 160 + 8
= 424
Converting 67B into decimal.
6×162+7×161+11×160
P4 = 4567 = 1101 odd no. of 1's so error occurs = 1536+112 +11
P2 = 2367 = 0001 odd no. of 1's so error occurs = 1659
P1 = 1357 = 1011 odd no. of 1's error occurs. Adding both number = 1659 + 424 = 2083
P4P2P1 = 111 = 7 error (a) position no. 7
85. In the 8421 BCD code the decimal number 125
is written as
(a) 1111101 (b) 7 D
(c) 000100100101 (d) None of these
RPSC Vice Principal ITI-2016 (2083)10 = (823)16
Ans. (c) : As given number of decimal = (125)10 91. The subtraction of two hexadecimal numbers
So, in BCD 8421 form it will be 000100100101 8416 – 2A16 results in
86. Booth algorithm is associated with - (a) 2B16 (b) 3A16
(a) Binary division (c) 4B 16 (d) 5A16
(b) Binary integer multiplication IES - 2016
(c) Sorting binary integers Ans. (d) : (84)16 converting into decimal -
(d) Searching of binary data 8×161 + 4×160
IES - 2020 = 128+4
= 132
Ans. (b) : The Booth algorithm are used for the
Now (2A)16 converting into decimal-
multiplication of binary numbers. Basically, it is used
2×161 + 10×160
for the multiplication of 2 signed numbers. =32+10
87. The decimal value of the signed binary number = 42
10101010 expressed in 2's complement will be Subtracting both number -
(a) –42 (b) –86 132 – 42 = 90
(c) –116 (d) –170 16 90 10
IES - 2019
Ans. (b) : 1's complement of 10101010 = 01010101 16 5 5 ↑
2's complement of 10101010 = 01010101+1 0
= 01010110 (90)10 → (5A)16
= (86)10 92. What is the base of the number for the
The decimal value of the given signed binary number following operation to be correct ?
will be → –86
( 54 )b
88. Convert the binary number 11000110 to Gray = ( 13 )b
code. ( 4 )b
(a) 00100101 (b) 10100100 (a) 2 (b) 4
(c) 11100110 (d) 10100101 (c) 8 (d) 16
IES - 2019 IES - 2016
(54) b 97. Consider the following statements :
Ans. (c) : = (13) b (1) When two unsigned numbers are added,
(4)b an overflow is detected from the carry into
Now converting into decimal - the most significant position.
5 × b1 + 4 × b0 (2) An overflow does not occur if the two
= 1×b1+3 × b0 numbers added are both negative.
4 × b0 (3) If the carry into the sign bit position and
5b + 4 carry out of the sign bit position are not
= b+3
4 equal, an overflow condition is produced.
5b+4 = 4b+12 Which of the above statements is/are correct?
b=8 (a) 1,2 and 3 (b) 1 only
93. It is awkward to employ signed-magnitude (c) 2 only (d) 3 only
system in computer arithmetic, because IES - 2015
1. Sign and magnitude have to be handled Ans. (d) : (1) Two unsigned numbers are an overflow
separately which is detected from the carry out of the most
significant position. In the significant signed number,
2. It has two representation for '0'
the leftmost bit always represent the sign and negative
Which of the above statements is/are correct? number which is in 2's complements form.
(a) 1 only (b) 2 only (2) Overflow does not occur if the number are of
(c) Both 1 and 2 (d) Neither 1 nor 2 opposite sign
IES - 2016 (3) If carry in to sign bit and carry out of the sign bit are
Ans. (c) : It is awkward to employ signed-magnitude not equal, overflow occur else overflow does not occur.
system in computer arithmetic because - 1's complement of 11011 is 00100
• Sign and magnitude have to be handled separately - minuend → 11101
left most significant bit represents the sign (0 means subtrahend → 00100
positive and 1 means negative) and the remaining bits carry out → 1 00001 +1
represent the magnitude of given number. Add to carry of remain number in LSB 00010 .
MSB Magnitude 98. Which one of the following is the correct
answer when (11011)2 is subtracted from
• It has two representation for '0' → (+0) → 0000 (11101)2 by using the 1's complement method?
(–0) → 1000
94. The decimal equivalent of Binary 110.001 is (a) 01001 (b) 10001
(a) 6.25 (b) 6.125 (c) 00011 (d) 00010
(c) 62.5 (d) 0.612 IES - 2015
IES - 2015 Ans. (d) : (11101)2 – (11011)2
Ans. (b) : Binary → 110.001
Decimal = 1×22+1×21+ 0×20 +2–1× 0 + 2–2× 0 + 2–3 × 1
= 6 + 0.125
= 6.125
95. Given (125)R = (203)5. The value of radix R will
be 99. Convert the decimal 41.6875 into octal.
(a) 16 (b) 10 (a) 51.54 (b) 51.13
(c) 8 (d) 6 (c) 54.13 (d) 51.51
IES - 2015
IES - 2015
Ans. (a) :
Ans. (d) : (125)R = (203)5
Both side change in to decimal equivalent
1×R2+2×R1+5×R0 = 2×52+0×51+3×50
R2+2R – 48 = 0
(R + 8) (R – 6) = 0
R = –8, 6 (41.6875)10 = (51.54)8
Radix of number can't be negative so : R = 6 100. The number of one's present in the binary
96. The 9's complement of (25.639)10 is representation of
(a) 74.360 (b) 06732 15 × 256 + 5 × 16 + 3 are
(c) 6.732 (d) 7.436 (a) 8 (b) 9
IES - 2015 (c) 10 (d) 11
Ans. (a) : 9's complement of (25.639)10 IES - 2015
99.999 Ans. (a) : 15×256+5×16+3
– 25.639 This can be represent as below -
74.360 = (23+22+21+20)× 28+(22+20)×24+21+20

= 211+210+29+28+ 26+24+21+20 (even parity, so no error occurs)
Hence, P2 → (2,3,6,7)
↓ ↓ ↓ ↓
1×211+1×210+1×29+1×28+1×26+1×24+1×21+1×20 1 1 0 1
∴ Total number of 1's are 8. (odd parity, so error occurs)

101. Given (135)base x + (144)base x = (323)base x What is P4 → (4,5,6,7)
the value of base x ? ↓ ↓ ↓ ↓
1 1 0 1
(a) 5 (b) 3
(odd parity, so error occurs)
(c) 12 (d) 6
To check word -
IES - 2015, 2005
* *
Ans. (d) : Convert both side in decimal form - P4 P2 P1
11 0 → (6)10
(135)X + (144)X = (323)X
1×x2+3×x1+5×x0+1×x2+4×x1+4×x0 = 3x2+2x1+3x0 Hence, error present at 6th position bit (0 to 1)
x2 + 3x + 5 + x2 + 4x + 4 = 3x2 + 2x + 3 New code will be -
2x2+7x+9 = 3x2+2x+3
2
x – 5x – 6 = 0
x(x–6) +1 (x–6) = 0
105. The decimal equivalent of binary number
(x + 1) (x – 6) =0 x = +6, –1
10110.11 is:
Q Radix number is never negative
(a) 16.75 (b) 20.75
∴ x = 6 or base x = 6 (c) 16.50 (d) 22.75
102. The BCD code for a decimal number (874)10 is: IES - 2015
(a) (100001110100)BCD Ans. (d) : Binary number →( 10110.11)2
(b) (010001111000)BCD decimal equivalent -
(c) (100001000111)BCD 1 1
(d) (011110000100)BCD = 1×24+0×23+1×22+1×21+0×20+ + 2
IES - 2015 2 2
1 1
Ans. (a) : As given that- = 16 + 4 + 2 + +
Decimal number → (874)10 2 4
Binary coded decimal is simply a 4-bit binary code 3
= 22+ = 22.75
representation i.e. BCD code is a 4 bit weighted code - 4
8 7 4 106. When a binary adder is used as BCD adder, the
1000 0111 0100 sum is
(874)10 → (100001110100)BCD (a) Correct when it is < 9
(b) Correct when it is > 9
103. Hexadecimal conversion of decimal number
227 will be: (c) Correct when it is < 16
(a) A3 (b) E3 (d) None of these
(c) CC (d) C3 Nagaland PSC CTSE (Degree)-2016, Paper-II
UPRVUNL AE-2016 Ans. (a) : When a binary adder is used as BCD adder,
IES - 2015 the sum is correct when it is < 9.
Ans. (b) : Given decimal number = 227
Conversion of decimal to hexadecimal - 107. Binary data is being represented is size of byte
(227)10 → ()16 and in 2's complement form. The number of 0's
16 227 3 present in representation of (–127)decimal
(E3) (a) 8 (b) 7
16 14 E ↑ 16
(c) 6 (d) 5
0 IES - 2012
(227)10 → (E3)16 Ans. (c) : As given that - (–127)10
104. A seven-bit Hamming code is received as Binary number of (127)10 = (1111111)2
1111101. What is the correct code? ∴ (127)10 = (1111111)2
(a) 1101111 (b) 1011111
(c) 1111111 (d) 1111011
IES - 2015
Ans. (c) Sign bit 2's cmplement of actual binary
Sign bit 1's cmplement of actual binary

P1 → (1,3,5,7) ∴ 2's complement of (01111111)2 = (10000001)2
↓ ↓ ↓ ↓
1 1 1 1 Now number of zero in 2's complement is, 6.

108. The hexadecimal representation of (657)8 is : 111. Which one of the following is the correct
(a) 1AFH (b) D78H sequence of the numbers represented in the
(c) D71H (d) 32FH series given below ?
IES - 2010 (2)3 , (10)4 , (11)5 , (14)6 , (22)7 , .....
UJVNL AE-2016 (a) 2, 3, 4, 5, 6, ... (b) 2, 4, 6, 8, 10, ...
(c) 2, 4, 6, 10, 12, (d) 2, 4, 6, 10, 16, ...
Ans. (a) : As given that – IES - 2007
(657)8 → (?)10 Ans. (d) : Given series - (2)3, (10)4, (11)5, (14)6, (22)7......
Decimal equivalent = 6×82+5×81+7×80 All the given series change into decimal number
= 384+40+7 = 2×30, 1×41 +0×40,1×51+ 1×50, 1×61+ 4×60,2×71+ 2×70
= 431 = 2, 4, 6, 10, 16
Change in hexadecimal- 112. What is the addition of (–64)10 and (80)16?
(a) (–16)10 (b) (16)16
(c) (1100000)2 (d) (01000000)2
IES - 2007
Ans. (d) : As given that -
(–64)10 and (80)16
Decimal of (80)16 = 8 ×161 + 0 ×160 = (128)10
(657)8 = (1AF)16 or 1AFH Addition of (–64)10 and (128)10
109. Consider the following statements: = (128)10 – (64)10 = (64)10
1. Taking 2's complement is equivalent to (64)10= (01000000)2
sign change. 113. What is the Gray code word for the binary
2. In the 2's complement representation the number 101011?
most significant bit (MSB) is zero for a (a) 101011 (b) 110101
positive number. (c) 011111 (d) 111110
IES - 2006
3. In a 4 bit binary representation of a binary
Ans. (d) : As given that -
number A, A + 1's complement of A = 24.
(c) 2 and 3 only (d) 1, 2 and 3
IES - 2009 114. Which of the following subtraction operations
Ans. (a) : 2's complement of any binary number that is results in F16?
equivalent to sign change - 1. (BA)16 – (AB)16
Ex. (5)10 → (0101)2 2. (BC)16 – (CB)16
2's complement of (0101)2 → (1011)2 3. (CB)16 – (BC)16
If a number (1011) Select the correct answer using the code given
MSB = 1{so it is negative number } below:
2's complement of this negative number = (0101)2 (a) Only 1 and 2 (b) Only 1 and 3
= (5)10 (c) Only 2 and 3 (d) 1, 2 and 3
So the real number = –5 IES - 2006
Nagaland PSC (Degree) - 2018, Paper-II
So the sign is changed
In 2's complement representation the MSB is zero for Ans. (b) : (i) (BA)16 – (AB)16
(11×161 + 10 × 160) – (10 × 161 + 11×160)
+ve number
186 – 171 = 15 → (F)16
Take A = 1011 → A =0100→A+ A (ii) (BC)16 – (CB)16
= 1111 = 24–1 (11× 161 + 12 ×160) – (12×161 +11×160)
110. (24)8 is expressed in Gray code as which one of 188 – 203 = –15 ≠ 15
the following ? (iii) (CB)16–(BC)16
(a) 11000 (b) 10100 (12 × 161 + 11 × 160) – (11 × 161 + 12 × 160)
(c) 11110 (d) 11111 203 – 188 = 15 ⇒ (F)16
IES - 2008 Hence, (1) and (3) is the correct
Ans. (c) : Octal to binary - 115. If (2.3)base 4 + (1.2)base 4 = (y)base 4' what is the
( 24 )8 = ( 010100 )2 value of y ?
(a) 10.1 (b) 10.01
(c) 10.2 (d) 1.02
IES - 2005
Ans. (a) : As given that → (2.3)4 + (1.2)4= (Y)4
Change in decimal - 2 ×40+ 3 × 4–1 + 1×40 + 2 × 4–1
( 24 )8 = (11110 )gray 2.75 + 1.5 = (4.25)10
Ans. (d) : (a) (1CE)16 + (A2)16 = (270)16
(b) (1BC)16 – (DE)16 = (DE)16
(c) (2BC)16 – (1DE)16 = (DE)16
(d) (200)16 – (11D)16 = (E3)16
0.25×4 =1.0 → 1 Hence, option 'd' is correct
(4.25)10 = (10.1)4 120. A number is expressed in binary two's
116. The number of 1's in 8-bit representation of – complement as 10011. Its decimal equivalent
127 in 2's complement form is m and that in 1's value is
complement form is n. What is the value of (a) 19 (b) 13
m:n? (c) –19 (d) –13
(a) 2 : 1 (b) 1 : 2 IES - 2002
(c) 3 : 1 (d) 1 : 3 Ans. (d) : As given that - 2' s complement no = 1 0011
IES - 2005 (MSB.bit show SMR)
Ans. (a) : As given that - (–127)10 ∴ Decimal equivalent no = 2's complement of (0011)
Binary number of (127)10 = (1111111)2 = (1101)2 = (–13)10
∴ (127)10 = (1111111)2 121. Which of the following is a self-complementing
code?
(a) 8421 code (b) Excess- 3 code
(c) Pure binary code (d) Gray code
Sign bit 2's cmpliment of actual binary IES - 2002
Ans. (b) : The excess- 3 decimal code is a self-
Sign bit 1's cmpliment of actual binary complement code because the binary sum of a code it's
9's complement is equal to 3 and complement can be
∴ 2's complement of (01111111)2 = (10000001)2 generated by inverting each bit pattern.
and 1's complement of (01111111)2 = (10000000)2 122. F's complement of (2BFD)hex is
Number of 1's in 2's and 1's complement is 2,1 (a) E304 (b) D403
∴ The required ratio is m:n = 2:1 (c) D402 (d) C403
117. How many 1's are present in the binary IES - 2001
representation of (4 × 4096) + (9 × 256) + (7 × Ans. (c) : To find F's complement of any number then
16) + 5? subtracting every given number from F
(a) 8 (b) 9 So -
(c) 10 (d) 11
IES - 2004
Ans. (a) : As given that -
Decimal - (4×4096) +(9×256) + (7×16)+5
123. The number of digit 1 present in the binary
= (22×212)+[(23+20)×28]+[(22+21+20)24]+(22+20)
14 11 8 6 5 4 2 0 representation of 3×512+7×64+5×8+3 is
= 2 +2 +2 +2 +2 +2 +2 +2 (a) 8 (b) 9
14 11 8 6 5 4 2 0
= 1×2 +1×2 +1×2 +1×2 +1×2 +1×2 +1×2 +1×2
(c) 10 (d) 12
So number of 1's is 8
IES - 2001
118. In signed magnitude representation, the binary ISRO Scientist Engg. -2006
equivalent of 22.5625 is (the bit before comma Ans. (b) : As given that series - 3×512+7×64+5×8+3
represents the sign) = (21+20)× 29+(22+21+20)× 26+(22+20)× 23+(21+20)
(a) 0,10110.1011 (b) 0,10110.1001 = 210+29+28+27+26+25+23+21+20
(c) 1,10101.1001 (d) 1,10110.1001
=1×210+1×29+1×28+1×27+1×26+1×25+1×23+1×21 +1×20
IES - 2002
Ans. (b) : As given that - ∴ Total number of one is, 9.
decimal →( 22.5625) 124. The minimum decimal equivalent of the
number 11C.0 is
(a) 183 (b) 194
(c) 268 (d) 269
IES - 2000
Ans. (b) : Assume that base is x i.e. (11C.0)x
C = 12 in Hexa-decimal system,
In any number system the digits in the number must be
For positive sign, MSB is 0 therefore, (22.5625)10 → less than base.
(0,10110.1001)2 So, for minimum decimal equivalent the base here must
119. Which of the following represents 'E316'? be 13, taking base x = 13
(a) (1CE)16 + (A2)16 (b) (1BC)16 – (DE)16 Then decimal equivalent value - 132 +131 + 12 = 194
(c) (2BC)16 – (1DE)16 (d) (200)16 – (11D)16 125. Match List-I with List-II and select the correct
IES - 2002 answer using the codes given below the lists
List-I List-II m=d+1
A. 45 1. 1 0 1 1 0 1 0 0 Minimum Hamming distance for error correction
B. 90 2. 1 1 0 1 0 0 1 0 m = 2d + 1
C. 180 3. 0 1 0 1 1 0 1 0 Where, m = Minimum Hamming distance
D. 210 4. 0 0 1 0 1 1 0 1 D = no. of bit error
5. 1 0 1 0 1 0 0 0 So, number of error correctable
Codes : m −1 m 1
A B C D d= = −
(a) 3 4 5 2 2 2 2
(b) 4 3 1 2 m
(c) 4 3 5 2 So, d<
2
(d) 3 4 2 1
130. When signed number are used in binary
IES - 1998
arithmetic, then which one of the following
Ans. (b) : 45 → 00101101 notations would have unique representation for
90 → 01011010 zero?
180 → 010110100 (a) Sign–magnitude (b) 1's complement
210 → 11010010 (c) 2's complement (d) 9's complement
Hence, the option number 'b' is correct. IES - 1993
126. When two number are added in excess-3 code TNPSC AE-2019
and the sum is less than 9, then in order to get Ans. (c) : When signed number are used in binary
the correct answer it is necessary to arithmetic then 2's complement notation would have
(a) Subtract 0011 from the sum unique representation for zero.
(b) Add 0011 to the sum 131. Which of the following is error correcting
(c) Subtract 0110 from the sum code?
(d) Add 0110 to the sum (a) EBCDIC (b) GRAY
IES -2015, 1998 (c) Hamming (d) ASCII
Ans. (c) : Two binary number - APGENCO AE-23.04.2017
A = 0010 IES - 1992
B = 0011 Ans. (c) : Hamming code is useful for both detection
The equivalent excess - 3 number are added and correction of error present in the received data .
0101 + 0110 = (1011)2 = (11)10 This code uses multiple parity bits and we have to place
To get equivalent binary number 0110 must subtracted these parity bit in the position of powers of 2.
from 1011. Hence, the result is 0101.
132. A 7 bit Hamming code (Even parity checker)
127. The decimal equivalent of the hexadecimal
0001001 for a BCD digit is known to have
number (3E8)16 is
errors. The BCD encoded digit is :
(a) 1000 (b) 982
(a) 9 (b) 5
(c) 768 (d) 323
(c) 3 (d) 0
IES - 1998
IES - 1992
Ans. (a) : As given that - Hexadecimal number (3E8)16
Ans. (a) :
Decimal equivalent = 3×162 + 14 ×161+8×160
= 768 + 224 + 8
= (1000)10
128. In hexadecimal system, (77)16 – (3B)16 is equal P → (1, 3, 5, 7)
1
to ↓ ↓↓ ↓
(a) 3D16 (b) 6016 0 0 0 1
(c) 3C16 (d) 7316 (Odd no. of 1's, so error occurs)
IES - 1995 P2 → (2, 3, 6, 7)
Ans. (c) : As given that - (77)16 - (3B)16 ↓ ↓↓ ↓
0 0 0 1
(Odd no. of 1's, so error occurs)
P4 → (4, 5, 6, 7)
129. Hamming codes are used for error detection ↓ ↓↓ ↓
1 0 0 1
and correction. If the minimum Hamming (Even no. of 1's, so no error occurs)
distance is m, then the number of errors To check word -
correctable is
(a) Equal to m (b) Less than m/2 P = P4 P2* P1*
(c) Equal to 2 m (d) Greater than m 0 1 1 → (3)10
IES - 1994 Hence, error present in 3rd position corresponding to
Ans. (b) : Minimum Hamming distance for error BCD digit → 1001
detection =9

133. The 8-bit 2's complement form of the number- (c) copy the original byte to the less significant
14 is __________. byte of the word and make each bit of the
(a) 11110010 (b) 00001110 more significant byte equal to the most
(c) 10001110 (d) 01110001 significant bit of the original byte.
KVS TGT (WE)- 2016 (d) copy the original byte to the less significant
bytes well as the more significant byte of the
Ans. (a) : Given that, word.
Number = 14 GATE -1993
binary number = 00001110 Ans. (c) :
1's complement = 11110001 ∴ To extend it to 16-bit word , copy the original byte (
2’s complement = 11110001 less significant ) of word and copy the MSB of original
+1 byte in higher byte of word.
11110010 In 2's complement form , if MSB = 1→ –ve number
(14)10 = (11110010)2 = 0→ +ve number
134. Which of the following is incorrect? 138. 4-bit 2's complement representation of a
(a) 111002 – 100012 = 001012 decimal number is 1000. The number is
(b) 15E16 = 35010 (a) +8 (b) 0
(c) 8110 = 10100012 (c) -7 (d) -8
(d) 37.48 = 011 111.1002 GATE -2002
IES - 1991 Ans. (d) : As given, the binary number = 1000
Ans. (a) : To checking option - Binary has MSB is 1, so it is (–ve) number
(a) (11100)2 – (10001)2 = (01011)2 ≠ (00101)2 Now taking 2's complement = 0111+1
(b) (15E)16 = 1×162+5×161+E×160 = (350)10 = 1000 = –8
(c) (81)10= (1010001)2 = (1010001)2 139. 11001, 1001 and 111001 correspond to the 2's
(d) (37.4)8 = (011111.100)2 complement representation of which one of the
Hence, option 'a' is correct. following sets of number ?
135. Consider the bit pattern 01010001. Which of (a) 25, 9 and 57 respectively
the following has Hamming distance of exactly (b) -6, -6 and -6 respectively
2 from these patterns? (c) -7, -7 and -7 respectively
(a) 01010000 (b) 01010010 (d) -25, -9 and -57 respectively
(c) 01010011 (d) 01010110 GATE - 2004
IES - 1991 Ans. (c) : 2's complement of given binary sets –
Ans. (b) : Given bit pattern - 01010001 11001 → 00111 → 7
taking XOR given bit pattern to option No. b 1001 → 0111 → 7
01010001 ⊕ 01010010 = 00000011 111001→ 000111→ 7
Hence this contains two 1's the Hamming distance , Q Given question is 2's complement correspond to –7
d(01010001, 01010010) = 2 ∴ Hence, set is –7, –7, –7
136. 2's complement representation of a 16-bit 140. Decimal 43 in Hexadecimal and BCD number
number (one sign bit and 15 magnitude bits) if system is respectively
FFFF. Its magnitude in decimal representation (a) B2, 0100 0011 (b) 2B, 0100 0011
is (c) 2B, 0011 0100 (d) B2, 0100 0100
(a) 0 (b) 1 GATE - 2005
(c) 32,767 (d) 65,535 Ans. (b) : Given number – 43
GATE -1993
Ans. (b) : Binary equivalent of (F F F F) = ( 1111 in hexadecimal→ (43)10 → (2B)16
1111 1111 1111 )
In BCD conversation →(43)10 → (01000011)BCD

141. A new Binary Coded Pentary (BCP) number
=1 system is proposed in which every digit of a
137. A signed integer has been stored in a byte using base-5 number is represented by its
the 2's complement format. We wish to store corresponding 3-bit binary code. For example,
the same integer in a 16 bit word. We should the base-5 number 24 will be represented by its
(a) copy the original byte to the less significant BCP code 010100. In this numbering system,
byte of the word and fill the more significant the BCP code 100010011001 corresponds to the
byte with zeros. following number in base-5 system
(b) copy the original byte to the more significant (a) 423 (b) 1324
byte of the word and fill the less significant (c) 2201 (d) 4231
byte with zeros. GATE -2006
Ans. (d) : Given - BCP code 100010011001 146. What is the gray code of (10010)2
Group in binary of 3-bit (a) 10011 (b) 00100
(100) (010) (011) (001) = 4231 (c) 11111 (d) 11011
142. X = 01110 and Y = 11001 are two 5 - bit binary TSPSC Manager (Engg.) - 2015
numbers represented in two's complement Ans. (d) :
format. The sum of X and Y represented in
two's complement format using 6 bits is
(a) 100111 (b) 001000
(c) 000111 (d) 101001
GATE -2007
147. The 2's complement representation of the
Ans. (c) : X = + 14, Y = –7
decimal number −4 is
So, sum of X & Y is = + 7 (a) 1000 (b) 1100
In 2's complement notation +7 in 6 bit is = 000111. (c) 1011 (d) 1010
143. P, Q and R are the decimal integers TSPSC Manager (Engg.) - 2015
corresponding to the 4-bit binary number 1100 Ans. (b) :
considered in signed magnitude, 1's complement, Binary code for decimal number 4=0 1 0 0
and 2's complement representations, respectively. 1's complement = 1 0 1 1
The 6-bit 2's complement representation of + 1
(P + Q + R) is 2's complement = 1 1 0 0
(a) 111101 (b) 110101 148. The octal equivalent of the decimal number 375
(c) 110010 (d) 111001 is.
Gate - 2020 (a) 560 (b) 567
Ans. (b) : As given that - 4-bit binary number is 1100 (c) 565 (d) none
Now signed magnitude representation of (1100) = –4 TSPSC Manager (Engg.) - 2015
1's complement representation of (1100) = –3 Ans. (b) :
2's complement representation of (1100) = –4
∴P+Q+R = –4+(–3)+(–4)
= –11
6-bit representation of binary (–11) = 101011
2's complement of 6-bit representation = 110101
144. The octal equivalent of decimal 324.987 is
(a) 40.987 (b) 540.781 Hence, (375)10 → (567)8
(c) 215.234 (d) 504.771 149. The decimal equivalent of (1431)8 is
Kerala PSC Lecturer (NCA) 04.07.2017 (a) 793 (b) 739
Ans. (d) : (c) 379 (d) 397
Ans. (a) : (1431)8 = 1×83+4×82+3×81+1×80
= 512 + 256 + 24 + 1
= 793
150. What are the values respectively of R1 and R2
in the expression ( 235 ) R = (565)10 = ( 865 )R
1 2
(a) 8, 16 (b) 16, 8

( 324 )10 Octal
→ ( 504 )8 (.987 )10 
Octal
→ (.771)8 (c) 6, 16 (d) 12, 8
( 324.987 )10  Octal
→ ( 504.771)8
Ans. (b) :
145. The maximum positive and negative numbers (i) ( 235) R = 565 (ii) ( 865 )R = 565
which can be represented in 2's complement 1 2
form using n-bit are 2R 12 + 3R 1 + 5 = 565 8R 22 + 6R 2 + 5 = 565

( ) (
(a) + 2n −1 − 1 , − 2n −1 − 1 ) 2R 12 + 3R 1 − 560 = 0 8R 22 + 6R 2 − 560 = 0
(b) +(2 n −1
− 1) , −2 n −1 ( R1 − 16 )( 2R1 + 35 ) = 0 4R 22 + 3R 2 − 280 = 0
(c) +2n −1 , −2n −1 R1 = 16 ( R 2 − 8 )( 4R 2 + 35 ) = 0

(d) none R2 = 8
TSPSC Manager (Engg.) - 2015 151. Convert (2AC9) →( )
16 7
TN P S C A E- 2 0 1 9 (a) (10953)7 (b) (43635)7
Ans. (b) : The range of 2's complement form, (c) (22953)7 (d) (63544)7
–2n–1 to +(2n–1–1) TNPSC AE- 2019
Ans. (b) : (2AC9)16 →( )7 157. 10's complement of 635 is
(2AC9)16 = ( )10 (a) 632 (b) 365
= 2×163 + 10×162 + 12×161 + 9×160 (c) 366 (d) 653
= (10953)10 Nagaland PSC 2018, Diploma Paper-II
(10953)10 → (43635)7 Ans. (b) : As we know that -
10's complement = 9's complement + 1
635 
9's complement
→ 999 − 635
= 364
635 
10 's complement
→ 364 + 1
= 365
152. The 10's complement of 3250 is 158. The equivalent gray number of the binary
(a) 96750 (b) 6750 number 110 is
(c) 6749 (d) 96749 (a) 101 (b) 111
TNPSC AE- 2019 (c) 011 (d) 000
Ans. (b) : As we know that - Nagaland PSC 2018, Diploma Paper-II
10's complement = (9's complement + 1) Ans. (a) : Gray equivalent of binary 110 is 101.
3250 
9's complement
→ 9999 − 3250
= 6749
3250 
10's complement
→ 6749 + 1
= 6750
153. Gray code is
(a) Cyclic code (b) Reflected code
(c) Non weighted code (d) All of the above 159. Excess-3 code of binary number 0011 is
Nagaland PSC 2018, Diploma Paper-II (a) 0110 (b) 1100
Ans. (d) : Gray code is non weighted that, means it (c) 0010 (d) 1111
does not depends on positional value of digit. This Nagaland PSC 2018, Diploma Paper-II
cyclic variable code that means every transition from
one value to the next value involves only one bit Ans. (a) : Binary Code = 0011
change. Hence, it is also known as reflected code. Equivalent decimal = 3
154. In BCD to Excess-3 code conversion logic Equivalent excess - 3 = BCD + 3
implementation, number of don't care term 0011
exists are: + 0011
(a) 3 (b) 6 0110
(c) 1 (d) 0 160. If (432)5 = (x)7, then the value of x is
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I (a) 522 (b) 225
Ans. (b) : Binary coded Decimal Code (BCD) (c) 252 (d) 250
→ It is 4-bit binary code. Nagaland PSC 2018, Diploma Paper-II
In 4-bit binary formats, total number of possible Ans. (b) : Convert (432)5 to decimal
representation = 24=16 4 × 52 + 3 × 51 + 2 × 50
Valid BCD Codes =10 = (117)10
Don’t care term = 6 decimal to base - 7
155. If (0.100)2 = (x)10, then x is
(a) 0.5 (b) 0.1
(c) 0.2 (d) 0.01
Nagaland PSC 2018, Diploma Paper-II
Ans. (a) : 0.100 × 0 = 1 × 2–1 = 0.5
0 × 2–2 = 0 (117 )10 → ( 225)7
0 × 2–3 = 0
+ ( 432 )5 → (117 )10 → ( 225)7
0.5
(0.100)2 = (0.5)10 161. Octal number of given number (101.10100110)2
156. 9's complement of 234 is is
(a) 234 (b) 765 (a) (5.514)8 (b) (5.154)8
(c) 767 (d) 423 (c) (5.100)8 (d) None of these
Nagaland PSC 2018, Diploma Paper-II Nagaland PSC 2018, Diploma Paper-II
Ans. (b) : The 9's complement of decimal number can Ans. (a) : (101.101 001100 ) = ( 5.514 )
be obtained by subtracting each digit by 9. Hence 9's 2 8
complement of 234 is 101 → 5

999 101 → 5
– 234 001 → 1
765 100 → 4
162. The binary representation of hexadecimal 'C3' Ans. (a) : The 1’s complement of 11110010 is
is 00001101.
(a) 1111 (b) 110011 The 2’s complement is 00001110.
(c) 111100 (d) 11000011 (00001110)2 → ( )
Nagaland PSC (Degree) 2018, Paper-II 23+22+21 = 8+4+2 = 14
Nagaland PSC CTSE- 2015, Paper-II The 1’s complement of 11110011 is 00001100.
Ans. (d) : (C)16 = (1100)2 The 2’s complement 00001101.
(3)16 = (0011)2 (00001101)2 → ( )
Now, join these value and get binary result 23+22+20 = 8+4+1 = 13
(C3)16 = (11000011)2 And there sum is –(14+13) = –27
163. The binary representation for the decimal 167. The value of X in the expression given below is
number 1.375 is: ( 2 ) 3 + ( 3 )4 = ( X )5
(a) 1.111 (b) 1.110 (a) 5 (b) 11
(c) 1.011 (d) 1.010 (c) 18 (d) 10
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I NIELIT Scientists- 2017
Ans. (c) : (1.375 )10 
→ (1.011) 2 Ans. (d) : Convert into decimal –
( 2 × 30 ) + ( 3 × 40 ) = ( X × 50 )
10 10 10
(10 )5 = ( X )5 = X = 10
164. The base of the number system for the addition
operation 24+14=41 to be true is: 168. Compute the value of the expression given
(a) 8 (b) 7 below, where i represents the base of number
(c) 6 (d) 5 system, will be
9
Ans. (b) : Let the base is X, then
∑i=2
(10)i
( 24 )x + (14 )x = ( 41)x (a) 10 (b) 25

(c) 36 (d) 44
( 2x1 + 4x 0 ) + ( x1 + 4x 0 ) = 4x1 + x 0 NIELIT Scientists- 2017
3x1 + 8 = 4x1 + 1 9
Ans. (d) : ∑ (10 )i
x=7 i=2
x=7 = (10)2 + (10)3 + (10)4 + (10)5 + (10)6 + (10)7 + (10)8 +
(10)9 = 44
165. What value of x satisfies the equation
169. The octal equivalent of the HEX number
(121)7 = ( x )2 ? AB.CD is
(where integer numbers written as subscripts (a) 253.314 (b) 253.632
are the base of the corresponding number (c) 526.314 (d) 526.632
systems.) Nagaland PSC CTSE (Degree)-2017, Paper-II
(a) 1011 (b) 0111 Ans. (b) : ( AB.CD )16 = ( 253.632 )8
(c) 1010 (d) 1000 We know that -
UPPSC ITI Principal/Asstt. Director-09.01.2022 A = 1010
Ans. (d) : (121)7 = ( x )2 B = 1011
C = 1100
(11)7 = ( x )2 D = 1101
1× 71 + 1× 70 = ( x )
2
( AB.CD )16 = (1010 1011. 1100 1101)2
(8 )10 = x 2 
=  010101

   011.110
   011
  010
  
(1000) = x2  2 5 3 6 3 2 8
166. In two’s complement system, add the signed ( AB.CD )16 = ( 253.632 )8
numbers 11110010 and 11110011. Determine, 170. A gray code is a/an :
in decimal, the sign and value of each number (a) Binary weighted code
and their sum. (b) Arithmetic code
(a) – 14 and – 13; – 27 (c) Code which exhibits a single bit change
(b) – 13 and – 12; – 25 between two successive codes
(c) – 27 and – 13; – 40 (d) Alphanumeric code
(d) – 2 and – 3; –5 Nagaland PSC CTSE (Degree)-2017, Paper-II
NIELIT Scientists- 2017 IES - 2005
Ans. (c) : A gray code is a code which exhibits a single 174. Find excess –3 code of 790
bit change between two successive codes. A gray code (a) 011110010000 (b) 101011000011
is an encoding of numbers so that adjacent numbers (c) 110111110000 (d) 111010000000
have a single digit differing by 1. The term gray code is AAI-2015
often used to refer to a "reflected" code, or more Ans. (b) : General BCD code-
specifically still, the binary reflected gray code. 790 = 011110010000
171. If 73x (in base x number system) is equal to 54y change in excess –3 code
(in base y number system), the possible values 0 1 1 1 1 0 0 1 0 0 0 0
of x and y are
(a) 8 and 16 (b) 10 and 12 + 1 1 + 1 1 + 1 1
(c) 9 and 13 (d) 8 and 11 1 0 1 0 1 1 0 0 0 0 1 1
IES - 2011 34x
175. = 16x What is the value of base X
Ans. (d) : 73 is in base X and 54 in base y, 2x
Therefore, (a) 8 (b) 6
7(x1 ) + 3(xº ) = 5(y1 ) + 4(yº ) (c) 4 (d) 9
7x –5y = 1 AAI-2015
Some of the possible integral solutions are: 34x
(x, y) = (3, 4), (8, 11) Ans. (a) : = 16 x
(3, 4) is not possible because 73 is definitely 2x
not in base. 3x + 4
= x+6
But (8, 11) is a solution to your problem 3. 2
73 base 8 = 54 base11 3x + 4 = 2x + 12
172. Two 2's complement numbers having sign bits x=8
x and y are added and the sign bit of the result 176. (95.5)10 in Hexadecimal represented as _____.
is z. Then, the occurrence of over flow is (a) 5F.A (b) 6F.8
indicated by the Boolean function (c) 5F.8 (d) 60.4
(a) x y z (b) x y z NPCIL-2015
(c) x y z + x y z (d) xy + yz + zx Ans. (c) : Y = ( 95.5 )10
Ans. (c) : 2's complement, if no having sign bit x and y
are the same (same sign) and resultant sign changes.
Condition of overflow are.
1. Sum of two positive number given a negative number
there will be overflow. ( 95.5 )10 = ( 5F.80 )16
2. Sum of two negative number gives a positive
number. 177. (FF)16 when converted to 8421 BCD is
I condition (a) 0010 0101 0101 (b) 0000 0101 0101
A ⇒ Positive number ⇒ X = 0 (c) 1111 0101 0101 (d) 1000 0101 0101
B ⇒ Positive number ⇒ Y = 0 KVS TGT (WE)-2014
S ⇒ Negative number ⇒ Z = 1
Ans. (a) : (FF)16 = 15 ×16 + 15 ×16ο
Boolean function = XYZ
II Condition - =240+15
A ⇒ Negative number ⇒ X = 1 =255
B ⇒ Negative number ⇒ Y = 1 (255)10 = (0010 0101 0101)2
S ⇒ Positive number ⇒ Z = 0 178. Decimal equivalent of (0.11010)2
Boolean function ⇒ XYZ (a) 0.5V (b) 0.8125V
Boolean function = XYZ + XYZ (c) 0.625V (d) 0.125V
check, one of the types of error detection in Ans. (b) : ( 0.11010 )2 = (1× 2 ) + (1× 2 ) + (1× 2 )
173. _______is also called vertical redundancy −1 −2 −4
communications. 1 1 1
(a) Cyclic check (b) Longitudinal check = + +
2 4 16
(c) Parity Checking (d) Sum technique = 0.5 + 0.25 + 0.0625
= 0.8125
Ans. (c): Parity check is also called vertical
Redundancy check, by which error in communication is 179. All no. represented by 2's complement the
detected. Parity is of two type. following no which is divisible by 11111011
Even parity and odd parity if the total number of 1's in (a) 11100100 (b) 11100111
the data is even then it is called even parity and if the (c) 11010111 (d) 11011011
total number of 1's is odd then it is called odd parity. BARC Scientific Officer-2016
Ans. (b) : 11111011 = –8 + 2 + 1 185. The 9’s complement of the decimal number
= –5 4567.86 is:
(a) 111100100  2 's comp
→ 100011011 (a) 5678.23 (b) 5643.13
= –28 (c) 5643.12 (d) 5432.13
(b) 11100111  2 's comp
→ 10011001 UPPCL AE-05.11.2019
= –25 Ans (d) : 9’s complement of the decimal number
(c) 11010111  2 's comp
→ 1101001 4567.86 is-
= –41 9 9 9 9 . 9 9
(d) 11011011  2 's comp
→ 10100101
= –37 − 4 5 6 7 . 8 6
So, that option (b) is correct.
5 4 3 2 . 1 3
180. Number of bits needed to code 64 operation is
(a) 4 (b) 6 186. A binary number system with 2n bits, all of
(c) 8 (d) 10
which are 1’s has the value.
Ans. (b) : For n-bit the number of operation code is 2n. (a) 2 2n − 1 (b) 2 2n
Hence for 64 operation (c) 2 + 1
2n
(d) 2 × 2 n −1
2 n = 64 UPPCL AE-05.11.2019
∴ n=6 Ans. (a) : A binary number with n-bits has a range
181. In a binary number, the rightmost bit is called from 0 to 2n-1 in decimal equivalent only one bit ‘0’
(a) Most significant bit (b) Least significant bit contains 0 while other bits will definitely contain at
(c) Carry bit (d) Extra bit least one 1’s.
So 2 2n – 1 is correct option.
Ans. (b) : In a binary number the right most bit is called
least significant bit(LSB) and left most bit is called Where n = 2n given in question
most significant bit (MSB). 187. A(7, 4) Hamming Code contains_____ parity
182. The value of the binary 11111 is : bits.
(a) 24–1 (b) 24 (a) 4 (b) 2
5
(c) 2 (d) 25–1 (c) 3 (d) 1
RRB SSE 21.12.2014, (Red) UPPCL AE-05.11.2019
Ans. (d) :
Ans. (c) : Hamming codes are linear block codes. The
Y = (1× 24 ) + (1× 23 ) + (1× 22 ) + (1× 21 ) + (1× 20 )
family of (n k) code for ( a ≥ 3) is contained No. of
Y = 16 + 8 + 4 + 2 + 1 = 31
parity bit n-k
So, 25 − 1 = 32 − 1 = 31
183. Perform the subtraction operation of binary Q n = 7, k = 4, n − k = 3 No. of parity bit.
digits 1001-10. The result is : 188. The hamming distance between two code words
(a) 1010 (b) 101
(c) 100 (d) 111 C1 = [1011 0101] and C2 = [ 0111 1010] is:
RRB SSE 21.12.2014, (Green) (a) 4 (b) 5
Ans. (d) : Subtraction operation of binary is (c) 3 (d) 6
1 0 0 1 UPPCL AE-05.11.2019
Ans. (d) : The Hamming distance between two
− 1 0
codeword is the no. of bit position in which they differ
1 1 1 C1 = 10110101 C2 = 01111010
184. Considering 2's complement representation for the two code words differ in 6 bit position as they
negative numbers. -128 will be stored into an indicated. Hence Hamming distance will be 6.
8-bit memory space as 189. A single Decimal-to-BCD encoder
(a) 11111111 (b) 10000000 has_______outputs.
(c) 11111110 (d) 10000001 (a) 4 (b) 10
RRB SSE 01.09.2015 Shit-I (c) 8 (d) 5
Ans. (b) : 128 = 10000000 UPPCL AE-05.11.2019
1's complement = 0 1 1 1 1 1 1 1
Ans. (a) : A decimal to BCD encoder is the type of
+ 1 encoder that usually consist of ten input lines and 4
output lines. Each input line expressed each decimal
2's complement = 1 0 0 0 0 0 0 0
digit and BCD code represent in 4 bits

190. The binary form of hexadecimal number 67BE 195. The number of digit 1 present in the binary
is representation of 3 × 512 + 5 × 64 + 7 × 8 + 3 is:
(a) 110011110111110 (a) 9 (b) 16
(b) 11011110111110 (c) 8 (d) 10
(c) 11001111011111 RRB JE-01.09.2019, 3:00 PM – 5:00 PM
(d) 100111101111100 Ans. (a) : 3 × 512 + 5 × 64 + 7 × 8 + 3
DMRC AM S&T-2020 = (2 + 1) × 29 + (4 + 1) × 26 + (4 + 2 + 1) × 23 + (2 + 1)
Ans. (a) : Y = 0110011110111110
       = 210 + 29 + 28 + 26 + 25 + 24 + 23+ 21 + 20
6 7 B E Number of 1's is 9.
191. Convert the hexadecimal number C6 to binary 196. A logic circuit which is used to change a BCD
number number into an equivalent decimal number is-
(a) 11000110 (b) 11000100 (a) Decoder (b) Encoder
(c) 10010110 (d) 10100110 (c) Multiplexer (d) Code converter
RRB JE-01.09.2019, 3:00 PM – 5:00 PM RRB JE- 31.08.2019, 10 AM-12 PM
Ans. (a) : (C6)16 = (............)2 Ans. (a) : Decoder is used to convert the BCD number
A = 1010 into an equivalent decimal number
B = 1011
C = 1100
2 6 0
2 3 1
197. How many digits in binary notation are
1 required for the decimal number 17?
(6)10 = (0110)2 (a) 6 (b) 4
C6 = (11000110)2 (c) 7 (d) 5
192. Which of the following pairs of octal and RRB JE- 31.08.2019, 10 AM-12 PM
binary numbers are NOT equal? Ans. (d) :
(a) (11010)2 = (62)8
(b) (10101.11)2 = (25.6)8
(c) (111110111)2 = (767)8
(d) (110110101)2 = (665)8
RRB JE-01.09.2019, 3:00 PM – 5:00 PM
Ans. (a) :
(17)10 = (10001)2
= (32)8 5 digits are required.
193. Which of the following is NOT a binary 198. The radix/base of octal number system is-
number? (a) 4 (b) 8
(a) 1111 (b) 000 (c) 2 (d) 10
(c) 101 (d) 11E RRB JE- 31.08.2019, 10 AM-12 PM
RRB JE-01.09.2019, 3:00 PM – 5:00 PM
Ans. (b) : The base of octal number system is 8.
Ans. (d) : Binary number system contains only two bits
199. Construct (7, 4) Hamming code for a massage
i.e. '0' and '1', hence from the options (1011)2 , ( 000 ) 2 ,
1011.
(a) 0110011 (b) 1010011
(101)2 are in binary number system. (c) 0111011 (d) 1011011
194. The excess-3 code of decimal 7 is represented SAIL- 2014
by− Ans. (a) : Given massage
(a) 1001 (b) 1100 →1011
(c) 1011 (d) 1010 Now
RRB JE-01.09.2019, 3:00 PM – 5:00 PM
Ans. (d) :
by even parity
Binary (111)2 keâe excess − 3 code ∗ P1= (P1,M3,M5,M7)
P1= (P1 1 0 1)
P1 = 0
∗ P2= (P2,M3,M6,M7)
P2= (P2 1 1 1) (a) 10000001 (b) 11111111
P2 = 1 (c) 10111110 (d) 11100001
∗ P4= (P4,M5,M6,M7)
Ans. (a) : Y = –126
P4= (P4 0 1 1)
126 binary number = 1111110
P4 = 0 1's compliment - 0000001
So, (7,4) Hamming Code is Sign bit 1's compliment of original binary number
= 0110011 Y = 10000001
200. Find the equivalent binary value of (36.75)10
(a) 100100.10 (b) 010101.01
205. The MSB of a binary number has a weight of
(c) 100100.11 (d) 110011.01
512, the number consists of ______.
SAIL- 2014
(a) 4 bits (b) 10 bits
Ans. (c) : 36 = 100100
36 = (100100)2 (c) 8 bits (d) 16 bits
0.75 × 2 = 1.50 = 1 KVS TGT (WE)- 2016
0.50 × 2 = 1.00 = 1 Ans. (b) : The MSB of a binary number has a weight of
0.00 × 2 = 0 = 0 512, the number consists of 10 bits.
(36.75)10 = (100100.11)2 206. Considering 2's complement representation for
negative number,-86 will be stored into an 8-bit
memory space as
(a) 10101010 (b) 11000111
(c) 10111000 (d) 11101101
Ans. (a) : 86 = (1 0 1 0 1 1 0)2
201. Number of bits needed to code 256 operation is:
(a) 4 (b) 6
(c) 8 (d) 16
RRB SSE 03.09.2015 Shift-II
Ans. (c) : For 128 operation 7- bit needed (27 = 128)
like that (28 = 256) 207. The 2-s compliment of the binary number
202. In a binary number, the leftmost bit is called: (00111100)2 is
(a) Most significant bit (a) (11000100)2 (b) (11000011)2
(b) Least significant bit (c) (00110000)2 (d) (11110100)2
(c) Carry bit RRB SSE 01.09.2015, Shift-III
(d) Extra bit Ans. (a) : A = 0 0 1 1 1 1 0 0
RRB SSE 03.09.2015 Shift-II
1's compliment = 1 1 0 0 0 0 1 1
Ans. (a) : Most significant bit.
203. (211)×=(152)8, the base × is + 1
(a) 5 (b) 6
(c) 7 (d) 9 2's compliment = 1 1 0 0 0 1 0 0
208. Considering 1's complement representation for
Ans. (c) : ( 211) x = (152 )8 negative numbers, –85 will be stored into an 8-
2x + (1× x ) + (1× x ) = (1× 8 ) + ( 5 × 8 ) + ( 2 × 8 )
2 1 0 2 1 0 bit memory space as
(a) 10101010 (b) 10111111
2x 2 + x + 1 = 64 + 40 + 2 (c) 10100110 (d) 11101001
2x 2 + (15 − 14 ) x − 105 = 0 RRB SSE 02.09.2015, Shift-I
Ans. (a) : 85 = (1 0 1 0 1 0 1)2
2x 2 + 15x − 14x − 105 = 0
1's compliment = 0 1 0 1 0 1 0
x ( 2x + 15) − 7 ( 2x + 15 ) = 0 – 85 1's compliment = 1 0 1 0 1 0 1 0
2x + 15 = 0 x–7=0 ↓
15 Sign bit
x=− x=7
2 209. The 8's complement of the octal number
x value can't be in negative fraction so that x = 7. (4060)s is
204. Considering 1's complement representation for (a) (3718)8 (b) (3717)8
negative numbers, -126 will be stored into an (c) (4020)8 (d) (4720)8
8- bit memory space as RRB SSE 02.09.2015, Shift-I
Ans. (a) : A = (3718) x 2 − 3x − 4 = 0
7's compliment - x 2 − 4x + x − 4 = 0
7 7 7 7 x ( x − 4 ) + 1( x − 4 )
−4 0 6 0
3 7 1 7 x=4
+ 1 216. What is the decimal equivalent of the binary
8's compliment = 3 7 1 8 (1010)2?
(a) 12 (b) 8
210. Considering signed-magnitude representation
(c) 10 (d) 7
for negative numbers, –42 will be stored into an
NLC GET -24.11.2020
8-bit memory space as
(a) 10101010 (b) 10110111 Ans. (c) : Y = (1010)2
(c) 10110010 (d) 10100001 ( Y )10 = (1× 23 ) + ( 0 × 22 ) + (1× 21 ) + ( 0 × 20 )
RRB SSE 02.09.2015, Shift-IIY = 8 + 2 = 10
Ans. (a) : A = –42 Y = (10)10
217. What is the binary equivalent of decimal
number (37)10?
(a) 1000012 (b) 1001012
211. The 15's complement of the hexadecimal (c) 1011012 (d) 1010012
number (B0210)16 is NLC GET -24.11.2020
(a) (4FDEF)16 (b) (4FDF0)16
Ans. (b) : (37)10 = ?
(c) (50EF0)16 (d) (40DE0)16
Ans. (a) :
F F F F F
−B 0 2 1 0
4 F D E F
212. The maximum count for which a 6 bit binary
word can represent is
(a) 36 (b) 64
( 37 )10 = (100101)2
(c) 63 (d) 65 218. The number of different Boolean functions of 4
TRB Poly. Lect. -2012 variables is
Ans. (c) : Maximum count = 2n–1 Qn = 6 (a) 216 (b) 162
2
(c) 4 (d) 164
= 26 –1
BSNL (JTO)-2001
= 64–1= 63
Ans. (c) : For the three variable different Boolean
213. The hexadecimal representation of (657)8 is
(a) D 78 (b) 1 AF function is 23 = 8 like that
(c) D 71 (d) 32 F For 4 variable = 2 4 = 16 (or) 4 2 = 16
TRB Poly. Lect. -2012 219. The standard binary code for alpha numeric
Ans. (b) : (657)8 = (0001 1010 1111)2 character is
(1 AF)16 (a) ASCII (b) GRAY
214. The gray code of (1001)2 is: (c) BCD (d) Excess-3
(a) 1101 (b) 0110 BSNL(JTO)-2009
(c) 1100 (d) 1001 Ans. (a) : Standard alphanumeric binary code is the
UPMRC AM - 2020 ASCII (American standard code for information
Ans. (a) : interchange), which uses seven bits to code 128
characters.
220. The binary number 101 represents :
(a) – 3 in two's complement system
(b) 7 in sign magnitude system
(c) – 5 in two's complement system
215. In certain number system with base or radix x, (d) – 2 in sign magnitude system
if (123)x + (21)x = (210)x then base or radix x of BSNL(JTO)-2002
number system is : Ans. (a) :
(a) 5 (b) 4
(c) 3 (d) 2
Ans. (b) : (123)x+(21)x = (210)x
x 2 + 2x + 3 + 2x + 1 = 2x 2 + x + 0 Y=111=–3

221. A 12 bit binary number has accuracy (a) -31 to +31 (b) -15 to +15
equivalent to the decimal fraction (c) -16 to +15 (d) -32 to +31
(a) 1/1024 (b) 1/2048 RRB SSE 01.09.2015 Shit-I
(c) 1/6400 (d) 1/4096 Ans. (b) : Range of 1's complement number
Kerala PSC Lecturer (NCA) 04.07.2017 − ( 2n −1 − 1) to + ( 2n −1 − 1)
= − ( 25−1 − 1) to + ( 25−1 − 1)
Ans. (d) : For n-bit number–
1
decimal fraction = n = – 15 to + 15
2
n = 12 bit 225. What is the hexadecimal equivalent of this
binary number (1110)2?
1 1 (a) F (b) B
Hence, decimal fraction = 12 =
2 4096 (c) A (d) E
222. The 16's Complement of the hexadecimal RRB JE- 31.08.2019, 10 AM-12 PM
number (A10)16 is Ans. (d) : Binary number ⇒ (1110)2  → (?)H
(a) (5F0)16 (b) (5E0)16 1 × 23 + 1 × 22 + 1 × 21 + 0 × 2º
(c) (5EF)16 (d) (6F0)16 = (14)10
(14)10  → (?)H
Ans. (a) : Given hexadecimal number- (A10)16
Step1- A 1 0 14  → E
(14)10 = (E)H
10 1 0
226. Of the following, which is the binary equivalent
of the decimal number 368 ?
(a) 101110000 (b) 110110000
(c) 111010000 (d) 111100000
Ans. (a) :
2 368 0
2 184 0
2 92 0
2 46 0
223. Logic circuit shown in figure is :
2 23 1 ( 368)10 = (101110000 )2
2 11 1
2 5 1
2 2 0
1
227. Which of the following BCD code, is a
sequential code and therefore can be used for
arithmetic operations as well as has six invalid
states 0000, 0001, 0010, 1101, 1110 and 1111?
(a) The excess three code
(b) Error detecting code
(c) The 8421 BCD code
(a) Binary to BCD converter (d) The Gray code
(b) Gray code to Binary code converter DFCCIL Executive S&T 29.09.2021, 12:30 to 2:30PM
(c) Binary to Gray code converter Ans. (a) : An excess-3 is the sequential code of the code
(d) None of the above and can be used for arithmetic operation, the excess-3
MPSC HOD Govt. Poly. -2013 code has 0000, 0001, 0010, 1101, 1110 and 1111
Ans. (b) : The given logic diagram is gray code to invalid codes.
binary code converter. (i) Excess -3 code is self complementary code.
224. What is 1’s complement number of a signed (ii) Excess-3 code is not weighted code.
decimal number? The range of signed decimal (iii) In excess-3 code the binary number is written by
numbers that can be represented by 5- bits? adding three to each decimal digit.

Ans. (c) : X = (A + B) ( A + C)
(ii) Boolean Algebra and X = A + AC + AB + BC
Simplification of Boolean A (1 + C) + AB + BC
A + AB + BC
Functions A (1 + B) + BC
1. SOP canonical form of function F = X + A + BC
YZ will be 5. The expression X + X ⋅ Y is equal to
(a) m2 + m3 (a) 1 (b) 0
(b) ∑(1,4,5,6,7 ) (c) X + Y (d) 1+Y
(c) M0 + M3
Ans. (c) : X + XY
(d) XYZ + XYZ + XYZ + XYZ
UPPSC ITI Principal/Asstt. Director-09.01.2022 = X (1 + Y ) + XY (Q 1 + Y = 1)
Ans. (b) : F = X + YZ = X + XY + XY (Q X + X = 1)
= X + Y (X + X)
= X+Y
6. For the given Boolean function F(x,y,z)
=Σ(0,2,4,5,6) simplified output will be -
(b) ∑
(1,4,5,6,7 ) (a) F = z + xy'
(c) F = z' + x'y
(b) F = z + x'y
(d) F = z' + xy'
2. Simplify the following Boolean expression UPPSC Poly. Tech. Lect.-22.03.2022, Paper -I
using the De Morgan’s theorem:
Ans. (d) : F(x,y,z) =Σ(0,2,4,5,6)
F(A,B,C,D,E,F) = ( A + B ) CD + (E + F)
(a) ( A + B + C) ( D + E + F)
(b) AB + CD + EF
(c) ( AB + C + D) E F F = z + xy
(d) ABC + DEF 7. What is the output Y for the logic circuit shown
ESE-2022 in the figure?
(c) : F(A,B,C,D,E,F) = ( A + B) CD + (E + F)
= ( A + B ) C D. ( E + F )
= (( A + B) + C D ) .E. F
= ( A B + C + D ) E.F (a) AB + AB (b) AB + A + B
(c) AB + AB (d) A + B
( )
= A B + C + D E. F ESE-2022
3. Simplify the following Boolean function: Ans. (d) :
f(A, B, C) = ABC+ ABC+ ABC+ ABC+ ABC
(a) ABC + ABC + AB (b) ABC + AC + AB
(c) AB + BC + AC (d) ABC + AC + AB
ESE-2022
Ans. (c) : Y=P+Q …..(i)
f(A, B, C) = ABC + ABC+ ABC + ABC + ABC S = A + A = A.A = 0
= ABC + ABC + ABC + ABC
T = A.B
U = A. B
P = S.T = 1(A.B) = A.B
Q = U = A.B = A + B
f (A, B, C) = BC + AC +AB from equation (i)
4. If (A + B) (A + C) = X, then "X" will be Y = P + Q = A.B + B + A
(a) B + AC (b) C + AB
B(A + 1) + A
(c) A + BC (d) None of the above
UPPSC ITI Principal/Asstt. Director-09.01.2022 Y = A+B

8. Find the complement of the function F1 - (a) Binary code (b) Excess-3 code
F1 = x ( y z + yz ) (c) ASCII code (d) Gray code
(a) F1 = x + ( y + z )( y + z ) RPCS Lect.-2011
(b) F1 = x ( yz + yz ) RPSC Lect.-10/01/2016
Ans. (d) : Gray code belongs to a class of codes called
(c) F1 = x + ( y + z )( y + z ) minimum change code in which the only one bit code
(d) F1 = x ( yz + yz ) group changes when going from one step to the next.
This is an unweighted code which means that there are
UPPSC Poly. Tech. Lect.-22.03.2022, Paper -I no specific weights assigned to the bit.
Ans. (c) : F1 = x ( y z + yz ) 13. A 2n variable K-map has______cells.
(a) 2n (b) 22n
F1 = x(y z + yz)
(c) log22n (d) 2n
(
F1 = x + y z + yz) APPSC POLY. LECT. 14.03.2020
UPPCL AE-05.11.2019
F1 = x + ( y + z )( y + z )  Ans. (b) : The Karnaugh (K) map is a method of
simplifying Boolean algebra expressions.
9. A + AB + ABC + ABCD simplifies to : No. of Variables = 2n
(a) A (b) A + B No. of cells in K-map = 22n
(c) A + B (d) A ⋅ B
14 The minterm expansion of F = AB + BC + AC is :
KVS TGT (WE)- 2017
(a) m2 + m4 + m6 + m7 (b) m0 + m1 + m3 + m5
Ans. (a) : Y = A + AB + ABC + ABCD (c) m7 + m6 + m2 + m4 (d) m2 + m3 + m4 + m5
= A + AB + ABC (1 + D ) APPSC Poly. Lect. 15.03.2020
= A + AB + ABC IES - 2017
Ans. (a) :
= A + AB (1 + C )
= A + AB
= A (1 + B )
=A
10. The dual form of (A + B) is:
(a) A ⋅ B (b) A ⋅ B F = m2 + m4 + m6 + m7
(c) A + B (d) A + B 15. Simplification of the function f = AB + A + B
KVS TGT (WE)- 2018 is:
Ans. (b) : Boolean duals are replaced as OR with AND (a) AB (b) A+B
and AND with OR. (c) AB (d) AB
11. The simplified form of the function UPMRC AM - 2020
F ( A,B,C,D ) = ∑ m (1,5,6,7,11,12,13,15 ) is
Ans. (d) : f = AB + A + B
(a) ACD + ABC + ABC + ACD + BD = A + B + A.B
(b) ACD + ABC + ABC + ACD + BD = A + B + AB
(c) ACD + ABC + ABC + ACD = A+B
(d) ACD + ABC + ABC + ACD = AB
ESE-2021 16. Which law/theorem states the following
Ans.(c) : F ( A, B,C, D ) = ∑ m (1,5,6,7,11,12,13,15 ) statements?
A+B=B+A
A.B=B.A
(a) Distributive law
(b) Associative law
(c) Commutative law
(d) De Morgan's Theorems
NLC GET -24.11.2020
Ans. (c) : Some Boolean algebraic laws
(1) Commutative law A + B = B + A
F = ACD + ABC + ABC + ACD A.B = B.A
(2) Associative law A + (B + C) = (A + B) + C
12. Which code is used to map the digital datas in
K-map for simplification? A.(B.C) = (A.B)C

(3) Distributive law A(B + C) = AB + AC Ans. (d) : A + BC
(4) De Morgan's theorem = A.1 + BC → (using A.1 = A)
(1) A1.A 2 A 3 ......A n = A1 + A 2 + A 3 ...... + A n = A (1 + B ) + BC → (using 1 + B = 1)
= A + AB + BC
(2) A1 + A 2 + A 3 + ...... + A n = A1.A 2 .A 3 .......A n
= A (1 + C ) + AB + BC → (using 1 + C = 1)
17. Simplify the following expression.
Y = AB + A(B + C) + B(B + C) = A + AC + AB + BC
(a) Y = A + B + C (b) Y = B + AC = A.A + AC + AB + BC → (using A.A = A)
(c) Y = A + BC (d) Y = AB + C = ( A + B )( A + C )
NLC GET -24.11.2020
Ans. (b) : AB + AB + AC + B + BC 22. For the identity AB + AC + BC = AB+ AC the
= B (A + A + 1 + C) + AC dual form is
= B + AC ( )
(a) ( A + B ) A + C ( B + C ) = ( A + B ) A + C ( )
18. Simplify the following expression:
Y = ABC + ABC (b) ( A + B)( A + C )( B + C ) = ( A + B)( A + C )
(a) Y = C
(c) Y = B
(b) Y = A
(d) Y = AB
(c) ( A + B) ( A + C ) ( B + C ) = ( A + B)( A + C )
NLC GET -24.11.2020 (d) AB + AC + BC = AB + AC
Ans. (d) : ABC + ABC ISRO Scientist Engg.-2007
IES-2001, 1999
= AB(C + C) GATE-1998
= AB Ans. (a) : Given that-
19. The minimum number of NAND gates required AB + AC + BC = AB + AC
to implement A + AB + ABC is equal to Dual from is,
(a) 0
(c) 4
(b) 1
(d) 7
( )
( A + B) A + C .( B + C ) = ( A + B) A + C ( )
TNPSC AE- 2019 23. The number of switching functions of 3
Nagaland PSC - 2018, (Diploma) Paper-II variables is
GPSC Asstt. Prof. 11.04.2017 (a) 8 (b) 64
BPSC Poly. Lect. -2014 (c) 128 (d) 256
IES-2012, 2003 APGENCO AE-23.04.2017
GATE - 1995 IES - 1993
Ans. (a) : Y = A + AB + ABC Ans. (d) : Variable number (n) = 3
Y = A (1 + B + BC ) Maximum possible no. of boolean function using n
n
Y=A variables = 22
3
Hence, minimum number of NAND gate required is 0. = 22
20. The logic expression y = A + AB is equivalent = 28
to = 256
Then number of switching functions of 3 variable is
(a) y = AB (b) y = AB 256.
(c) y = A + B (d) y = A + B 24. With 4 Boolean variables, how many Boolean
Nagaland PSC (Degree) 2018, Paper-II expressions can be formed?
GPSC Asstt. Prof. 11.04.2017 (a) 16 (b) 256
TRB Poly. Lect. -2012 (c) 1024 (1K) (d) 64 K (64 × 1024)
GATE-1999 CGPSC SO - 14/02/2016
Ans. (d) : y = A + AB GATE-2003
IES – 2002, 1992
y = ( A + A ) ( A + B)
Ans. (d) : n = 4 Variable
y=A+B = 22
n
21. A + (BC) = _______. = 22

4
(a) AB + C (b) AB + AC
= 216
(c) A (d) (A + B) (A + C)
Nagaland PSC - 2018 (Diploma) Paper-II = 26 × 210
GPSC Asstt. Prof. 11.04.2017 = 26 ×1K , (Q 210 = 1K)
UKPSC Assistant Radio Officer Screening Exam.-2011 = 64 × 1K, (1K = 1024)
IES - 2008, TNPSC AE - 2008 = (64 × 1024)
GATE-1997 = 64K = 64 × 1024
25. What will be the simplified Boolean function of 28 The minimised expression for
the given equation? F (a,b,c) = Σ (0, 2, 4, 5, 6)
(a) ac'+b (b) c' + ab' (a + b ) (a + b ) + (ab + a) is :
(c) a+b+c (d) a'b+c (a) a+b (b) a
TNTRB AE– 2017 (c) b (d) ab
DFCCIL Executive S&T-17.04.2016, Shift-II UPPCL AE-30.03.2022
Ans. (b) : As given that,
F (a,b,c) = Σ (0, 2, 4, 5, 6)
By three- variable k- map,
( ) (
Ans. (b) : ( a + b ) a + b + ab + a )
= aa + ab + ab + bb + ab
= a + ab + ab + 0 + ab
= a + ab + ab + 0
(
=a+a b+b )
=a+a =a
F (a,b,c) = ab + c 29. Consider the following truth table :
F (a,b,c) = ab'+c'
26. Using the DeMorgan's theorem (x + y)' is
(a) x'.y' (b) (xy)'
(c) x + y (d) x + y'
Ans. (a) : From De Morgan's theorem -
F = xy or F=x+y
F=x+y F = x.y The corresponding Boolean function 'F' is
27. A programmable logic array (PLA) is shown in (a) A + B + C (b) A + B + C
the figure, (c) A (d) B
IES - 1995
Ans. (d) :
F= B C + B C
= B(C + C)
F= B
The Boolean function F implemented is
30. The number of product terms in the minimized
(a) PQR + PQR + PQR sum-of-product expression obtained through
(b) (P + Q + R)(P + Q + R)(P + Q + R) the following K=map is (where, "d" denotes
(c) PQR + PQR + PQR don't care states)
(d) (P + Q + R)(P + Q + R)(P + Q + R)
GATE - 2017
Ans. (c) :
(a) 2 (b) 3
(c) 4 (d) 5
GATE -2005
Ans. (a) :
F = X1 + X2 + X3 ( X1 = PQR, X 2 = PQR,X 3 = PQR )

SOP equation,
The number of product term is two, one quad and one
F = PQR + PQR + PQR pair.
31. The truth table for implementing a boolean Ans. (d) :
variable F is given by
C B A F
0 0 0 d
0 0 1 1
0 1 0 1
0 1 1 d
1 0 0 0
1 0 1 0 Boolean expression for shaded area = XY + X Y Z
1 1 0 0 34. The function shown in the figure when
simplified will yield a result with
1 1 1 1
Where d represents don't care states. The
minimized expression for F is
(a) B.C + A.C + A.B
(b) A.B + C
(c) A.B.C + A.B.C + A.B.C
(d) None of above
Ans. (b) :
(a) 2 terms (b) 4 terms
(c) 7 terms (d) 16 terms
Ans. (c) :
F = C + AB
32. Simplify the Boolean expression:
F(w, x,y, z) = ∑ (0,1, 2,4,5,6,8,9,12,13,14)
(a) w+x+y+z (b) y'+w'z'+xz'
(c) y+w'z'+xz (d) x+z'w'y+x'
ISRO Scientist Engg.-2018 Q No minterm is grouped with other minterm
Ans.(b): F(w, x, y, z) = ∑ (0,1, 2, 4,5,6,8,9,12,13,14) ∴ All '7' minterms will present in the simplified SOP
form.
35. Which of the following is the Boolean function
for Majority Voting, assuming A,B,C are
inputs and Y is output?
(a) Y = AB + AC + CB (b) Y = A + B + C
(c) Y = ABC (d) Y = AB + BC
Ans. (a) : Majority voting means that when two or more
inputs have their input as 1, then only output 1.
F = y + wz + xz
33. The Boolean expression for the shaded area in
the Venn diagram is
(a) X + Y + Z (b) XYZ + XYZ

(c) X+Y+Z (d) X YZ + XY
ISRO Scientist Engg.-2006 Y = AB + BC + AC
36. Simplify Boolean function represented in sum Ans. (b) : F (X,Y,Z) = Σm (1, 2, 5, 6, 7)
of product of min-terms, F(x, y, z) = = πM ( 0,3, 4 )
∑ (0, 2,4,5,6)
(a) z'+xy' (b) x'y'z'+xyz+xy'z'
(c) xyz+x'+y'+z' (d) xy+yz+zx
Ans.(a): F(x, y, z) = ∑ (0, 2, 4,5,6)
Product of sum-
= ( X + Y + Z ) ( X + Y + Z )( X + Y + Z )
41. The expression Y = Π M (0, 1, 3, 4) is
(a) SOP (b) POS
(c) Hybrid (d) None of the above
37. According to Boolean law : A + 1 = ? Nagaland PSC (CTSE) Diploma-2017, Paper II
(a) 1 (b) A
Ans. (b) : Y = πM(0,1,3, 4)
(c) 0 (d) A'
Nagaland PSC (CTSE) Diploma-2017, Paper II Σm ⇒ Represent sum of product (SOP)
Ans. (a) : Boolean Law - ΠΜ ⇒ Represent product of sum (POS)
A+1=1 42. A Karnaugh map with 4 variables has
(a) 2 Cells (b) 4 Cells
A+A=A
(c) 8 Cells (d) 16 Cells
A+0=A Nagaland PSC (CTSE) Diploma-2017, Paper II
A + A =1 Ans. (d) : K-map or karnaugh map with 4-variable has
A.A = 0 24 cells
38. De-Morgan's theorem states that_____ 24 = 16 Cells
(a) (AB)' = A' + B' (b) (A + B)' = A' * B 43. Which of the following is the simplified
(c) A' + B' = A'B' (d) (AB)' = A' + B Boolean algebra version of (P + Q).(P + R)?
Nagaland PSC (CTSE) Diploma-2017, Paper II (a) P + Q.R (b) P + P.(Q +R)
Ans. (a) : De-Morgan's theorem - The complement of (c) P (d) P.(1 + Q.R)
the product of all the terms is equal to the sum of the Nagaland PSC (CTSE) Diploma-2017, Paper II
complement of each terms. Ans. (a) : Y = (P + Q).(P + R)
According to De-Morgan's theorem. Y = P.P + P.R + Q.P + Q.R
(1) A.B.C........ = A + B + C + ........ Y = P+PR + QP + QR
(2) A + B + C +........ = A.B.C........ Y = P (1 + R ) + QP + QR
39. There are ________Minterms for 3 variables Y = P + QP + QR
(a, b, c). Y = P (1 + Q ) + QR
(a) 0 (b) 2
(c) 8 (d) 1 Y = P + QR
44. The minterm function f (A, B, C, D) =
Ans. (c) : Minterm is given by 2n.
Where n = number of variables ∑ (1, 3, 4, 6, 9,11,12,14) is .
3
So, 2 = 8 minterms are required. (a) independent of 2 variables
40. A function of Boolean variables X, Y and Z is (b) independent of 1 variable
expressed in terms of the min-terms as (c) dependent of all 4 variables
F(X,Y,Z) = Σ (1, 2, 5, 6, 7). Which one of the (d) independent of 3 variable
product of sums given below is equal to the UPRVUNL AE -19.07.2021, Shift-II
function F(X,Y,Z)? Ans. (a) :
( )( )(
(a) X + Y + Z X + Y + Z X + Y + Z )
(b) ( X + Y + Z ) ( X + Y + Z )( X + Y + Z )
(c) ( X + Y + Z)( X + Y + Z)( X + Y + Z)
( X + Y + Z) ( X + Y + Z)
(d) ( X + Y + Z)( X + Y + Z)( X + Y + Z)
( X + Y + Z)( X + Y + Z) Y = BD + BD
Nagaland PSC (CTSE) Diploma-2017, Paper II Independent of 2 variables (A,C)
45. In Boolean Algebra A. A is equal to Ans. (b) : F = ( A + B ) ( A + B )
(a) 1 (b) A
(c) A2 (d) 0 F = AA + AB + AB + BB
TNPSC AE - 2018 F = A + A ( B + B) + 0
Ans. (d) : F = A. A F=A+A
If A = 0, A = 1 F=A
F = A. A =0 × 1 50. The Boolean equation X = [(Α + Β)(Β + C)]Β
F=0
can be simplified to
46. Simplified function of the following Boolean
expression is xy + x'z + yz = (a) X = AB (b) X = AB
(a) x + z + y (b) x + z (c) X = AB (d) X = AB
(c) xy + x'z (d) xyz Mizoram PSC IOLM -2018, Paper II
( )
TNPSC AE - 2018 Ans. (c) : X =  A + B ( B + C )  .B
Ans. (c) : F = xy + xz + yz 
X = ( AB + AC + BC + B.B ) .B
( ) ( )
= xy z + z + xz y + y + yz x + x( )
= xyz + xyz + xyz + x yz + xyz + xyz X = ABB + ACB + BBC
= xyz + xyz + xyz + x yz X = AB + ABC
X = AB(1 + C)
= xy ( z + z ) + xz ( y + y ) X = AB
F = xy + xz 51. The Boolean function
XYZ + XYZ + XYZ + XYZ can be equivalently
47. A Prime implicant occupying _____ block of 1's represented as
in a karnaugh map would have lower cost than
a prime implicant occupying _____ block of 1's (a) ( X + Y + Z )( X + Y + Z )( X + Y + Z ) ( X + Y + Z )
because the _____ will result in fewer variables (b) ( X + Y + Z)( X + Y + Z)( X + Y + Z)( X + Y + Z)
than the ______ .
(a) smaller, larger, latter, former (c) ( X + Y + Z)( X + Y + Z)( X + Y + Z)( X + Y + Z)
(b) larger, smaller, former, latter
(c) smaller, larger, former latter
(d) ( X + Y + Z) ( X + Y + Z )
(d) larger, smaller, latter, former UPPCL AE- 31.12.2018
TNPSC AE - 2018 Ans. (c) : F = X YZ + XYZ + XY Z + XYZ
Ans. (b) : A prime implicant occupying larger block of This is the sum of product form and it will be equal to
1's in a k-map would have lower cost than a prime the product of sum.
implicant occupying smaller block of 1's because the F = ( X + Y + Z ) .( X + Y + Z ) .( X + Y + Z ) .( X + Y + Z )
former will result in fewer variable than the latter.
48. Consider the following function of four 52. m3 & m6 minterms are present in a function f
variables: of n variables. The number of Maxterms
F(A, B, C, D) = ∑ (1, 2, 6, 7, 8, 9, 10, 11, 12,13) present in the same function f are-
(a) Independent of one variable (a) 2n – 1, (b) 2n – 3,
n
(b) Independent of two variables (c) 2 – 2, (d) 23 – 2,
(c) Independent of three variables UPPCL AE-16.11.2013
(d) Dependent on all the variable Ans. (c) : No. of maxterm = 2n– No. of minterm
RPSC ACF & FRO 23.02.2021 No. of maxterm = 2n–2
Ans. (d) : 53. The simplified output of Y = AB + AC +
ABC ( AB + C ) is
(a) 0 (b) B
(c) AB (d) None of these
UPSC JWM-2016
Ans. (d) : Y = AB + AC + ABC ( AB + C )
Y = AB + AC + ABC
Y = AB + AC + ABC + CDB + CDB
So, dependent on all the variable. Y = A ( B + BC ) + AC
49. If A and B are Boolean variables, then what is = A ( B + C ) + AC
(A+B). (A + B) equals to
(a) B (b) A
= AB + AC + AC ( )
(c) A+B (d) AB Y = AB + 1
Mizoram PSC IOLM -2018, Paper II Y =1

54. The simplified Boolean function; ( A ⋅ B ⋅ C) + (
Ans. (d) : Given, expression is X Y + Z + W)
( A ⋅ B ⋅ C)
According to theorem -
A + BC = ( A + B )( A + C )
(a) A + B + C
(c) AB + A ⋅ B ⋅ C
(b) 1
(d) AB + C
So, W + X Y + Z ( )
UPSC JWM-2016 = ( X + W ) ( Y + Z + W )
( )
Ans. (b) : F = A.B.C + A.B.C 58.
Match List-I with List-II as per the codes given
below:
F = (A + B + C) + (A + B + C) List - I List - II
F = ( A + A ) + ( B + B) + ( C + C ) A. Y = AB + CD 1. Not
operation
F=1+1+1 B. Y = (A+B) (C +D) 2. Sum of
F=1 products
55. Simplify the Boolean function equation
F(w, x, y, z) = Σ(1, 3, 7, 11, 15) C. A +B = AB 3. Product of
And the don't care conditions: sums
d(w, x, y, z) = Σ(0, 2, 5) equation
(a) F = zw + zy' (b) F' = zw' + yz D. Y=A 4. Demorgan's
(c) F' = z' + wy' (d) F = z'w + zy' first theorem
UPSC JWM-2016 A B C D
Ans. (b) : F(w, x, y, z) = Σ(1, 3, 7, 11, 15) (a) 1 2 3 4
d(w, x, y, z) = Σ(0, 2, 5) (b) 4 2 3 1
(c) 2 3 4 1
(d) 3 1 2 4
TNPSC AE-2014
Ans. (c) :
Not operation - Y = A
Sum of products - Y = AB + CD
Product of sum- Y = (A + B) (C + D)
Demorgan's law- 1st = A + B + C + .... = A.B.C......
F = yz + wz 2nd- A ⋅ B ⋅ C ⋅ .... = A + B + C......
56. The minimum number of 2 input NAND gates 59. Mark the incorrect Boolean expression :
required to realize the equation (a) 1 + A = A' (b) 1 + A = 1
y = A ( B + C + D ) is, (c) A + A = 1 (d) A + AB = A
(a) 10 (b) 9 TNPSC AE-2013
(c) 8 (d) 7 Ans. (a) : From the option
UPSC JWM-2016 1+A=1
Ans. (c) : y = A ( B + C + D ) A + A =1
A + AB = A(1+B) = A
60. Reduce the Boolean equation AB + ABC +
AB + ABC
(a) A + BC (b) B
(c) B + AC (d) AC
TNPSC AE-2013
Ans. (c) : F = AB + ABC + AB + ABC
• Hence, the minimum NAND gate required is "8". F= AB + A B + ABC + A B C
57. The minimum product of sums of the Boolean F = B [A + A ] + AC [B + B ]
expression X(Y+ Z) +W is F = B + AC
(a) XY + XZ + W 61. The minimal sum of products form of
(b) (X + YZ)W f = ABCD + ABC + ABC + BCD is
(c) (X + W) (Y + Z)
(a) AC + BD (b) AC + CD
(d) (X + W)(Y + Z + W) (c) AC + BD (d) AB + CD
UJVNL AE-2016 TNPSC AE - 2008
Ans. (b) 67. By De-Morgan's Law Y = bar (A(B + CD)) is
equals to
(a) bar(A)bar(B + CD)
(b) bar(A) + bar(B + CD)
(c) A + bar (B + CD)
(d) bar(A) + (B + CD)
Hence, f = AC + CD Ans. (b) : Y = A ( B + CD )
62. A four bit BCD (DCBA) for numeral 9 can be By De-Morgan's law
decoded by the following logical operations in
the most economical manner (
Y = A + B + CD )
(a) ABD (b) ACD Y = A + B ⋅ CD
(c) ABCD (d) AD
⇒ Y = A+B C+D ( )
Ans. (c) : In BCD, it is 4-bit binary including no. (0 to 9) Y = A + BC + BD
So, for numeral 9 we can express it
The complement of ( AB + C ) D + E  F is
( 9 )10 = (1001)2 = ( ABCD ) 68.
63. The function of f = ABC + ABC + ABC + ABC (a) ( A + B ) .C + D  E + F

can be reduced to (b) ( A + B ) .C + D  + F
(a) f = A (b) f = ABC
(c) f = B (d) f = AB (c)  A + B + D  .E + F
Ans. (c) : F = ABC + ABC + ABC + ABC (d) ( A + B ) .C + D  .E + F
( ) (
= AB C + C + AB C + C ) Mizoram PSC Jr. Grade -2018, Paper-II
= AB + AB
Ans. (a) : X = (( AB + C ).D + E ).F
(
= B A+A ) ( ( AB + C ) .D + E ) .F
F=B
64. Which of the following expression is not true? (
X = ( AB + C ) D + E + F )
(a) A+ 1 = A (b) A. A = 0 X = ( AB + C ) D.E + F
(c) A + A = 1
(d) A.A = A
(
X = AB + C + D E + F )
Ans. (a) : Given condition, A + 1 = A
It is not true
(
= AB.C + D E + F )
If A = 0 then 0+1=1 ≠ A = ( A + B ) .C + D  E + F
65. The reason for using gray code in Karnaugh
69. If f(A, B, C) = Σ ( 1, 2, 3, 4, 5, 6, 7) and there
map is
are no 'don't care' entries, then f '(A, B, C) is
(a) Gray code provides cell values which differ in equal to
only one bit in adjacent cells
(b) Any other code can be used (a)  A + B + C  (b) A+ B+ C
(c) Gray code is more efficient than binary code (c) A.B.C (d) A. B. C
(d) None of these Mizoram PSC Jr. Grade -2018, Paper-II
Ans. (a) : In gray, code, if we go from one decimal Ans. (b) : f = ∑
m (1,2,3,4,5,6,7 )
number to next, only one bit of the gray code change. Gray
code provides cell values which differ in only one bit in
adjacent cells. So gray code is used in Karnaugh Map.
66. Two binary signal a, b are to be compared. The
output expression when the two signals are
equal is given by
(a) ab + ab (b) ab + a b f = A+ B+C
(c) ab (d) a b
70. An expression f = AB + A + AB can be reduced
Nagaland PSC CTSE (Degree)-2016, Paper-II to
Ans. (b) : For 2-bit comparator, the expression for (a) A (b) B
equal output E = ab + a b (c) 0 (d) 1
IES - 2020
Ans. (c) : f = AB + A + AB NOR-NOR expression ––
= AB.A.AB ( from De-Morgan theorem)

= AB.A. AB
Q A.A = 0
= AB ( A + B ) Y= (A + C) . (B + D)
& B.B = 0
= (A+C)(B+D)
= AB A +AB B
=0+0 So NOR-NOR expression is equivalent to OR-AND
F=0 expression
71. K-map is used to minimize the number of then option (b) also correct
(a) Flip-flops in digital circuits 74. The simplification in minimal sum of product
(b) Layout spaces in digital circuits for (SOP) of Y = F(A,B,C,D)
fabrication = ∑ m(0,2, 3,6,7) + ∑ d (8,10,11,15) using
(c) Functions of 3, 4, 5 or 6 variables
(d) Registers in CPU K-maps is:
IES - 2020 (a) Y = AC + BD (b) Y = AC + BD
Ans. (c) : K-map is a tool that is used to minimize the (c) Y = AC + BD (d) Y = AC + BD
output expressions of 3,4,5 or 6 variables it can provide IES - 2017
two forms of expressions i.e. SOP (sum of product) and Ans. (d) :
POS (product of sum) according to the need for the
problem.
72. Consider the following expression:
A.B.C.D + A.B.C.D + A.B.C.D
+ A.B.C.D + A.B.C.D
+ A.B.C.D.E + A.B.C.D.E
The simplification of this by using theorems of
boolean algebra will be
(a) A + B (b) A ⊕ B ∑m(0,2,3,6,7) + ∑d(8,10,11,15)
(c) (A + B)(A.B) (d) A.B Y= A C + BD
IES - 2019 75. The simplified form of the Boolean expression
Ans. (d) : ABCD + ABCD + ABCD + ABCD + ABCD AB + A(B + C) + B(B + C) is given by
+ ABCDE + ABCDE (a) AB + AC (b) B + AC
= ABCD + ABCD + ABCD + ABCD + ABCDE (c) BC + AC (d) AB + C
IES - 2016
+ ABCDE
Ans. (b) : Y = AB + A(B+C) + B(B+C)
= ABC ( D + D ) + ABC ( D + D ) + ABCDE + ABCDE = AB+AB+AC+BB+BC
= ABC + ABC + ABCDE + ABCDE =AB+AC+B+BC
= AB ( C + C ) + ABCDE + ABCDE = AB+AC+B(1+C) Q 1+C = 1
= AB+AC+B
= AB + ABCDE + ABCDE = AB+B+AC & (A+1) = 1
= AB (1 + CDE + CDE ) = B(A+1)+AC
= AB ()
1 Y= B+AC
= AB 76. Simplified form of the Boolean expression
73. A product-of-sums (POS) expression leads to Y = (A.B + C)(A + B + C) is
what kind of logic circuit? (a) AC + AC + BC + BC
(a) OR-AND circuit
(b) NOR-NOR circuit (b) (A + B + C)(A + B + C)
(c) AND-OR-INVERT circuit (c) (A + B)(A + C)
(d) NAND-NAND circuit
IES - 2018 (d) A (B + C)
Ans. (a,b) : Product of sum(POS) - it is equivalent to IES – 2016, 2015
logical OR-AND function which gives the AND Ans. (b) :
product of two or more OR sum to produce on output y = (AB + C).(A + B + C)
POS →(A + C) (B + D)
y = (AB + C).(A.B + C) (by using De Morgan's theorem)
y = AB A B + ABC + A BC + C C (by Multiplying)

y = ABC + A B C Ans. (a) : F (A,B,C,D) = ( A +BC) (B+CD)
= A B + A CD + BC.B + BC.CD
y = ABC.A.B.C (by using De Morgan's theorem)
= A B + A CD + BC + BCD
y = (A + B + C) (A + B + C)
82. The logic function ( A + B ) can be expressed in
77. Product of Maxterms representation for the
terms of minterms as:
Boolean function F = BD + AD + BD is
(a) AB + BA (b) AB + BA + AB
(a) ΠM (1,3,5,7) (b) ΠM (0,2,4,,6)
(c) ΠM (0,1,2,3) (d) ΠM (4,5,6,7) (c) AB + AB (d) AB + BA
IES - 2016 IES - 2013
Ans. (b) : Ans. (b) : (a) A B + B A ⇒ XOR gate
(b) A B + B A+ A B
= A B + B (A+ A )
= AB + B
minterm = ∑M (1,3,5,7) = ( B + B)( A + B )
Product of maxterms = 0,2,4,6
ΠM(0,2,4,6) = 1.( A + B )
78. K-map method of simplification can be applied = A+B
when the given function is in (c) =A B+AB
(a) Product of sum form = A ( B +B)
(b) Sum of product form
= A
(c) Canonical form
(d) Any form (d) = AB+ B A
IES - 2015 = A(B + B )
Ans. (d) : K-map method of simplification can be =A
applied when––––– 83. The minterms for AB + ACD are :
sum of product (SOP) form→ group of 1's (a) ABCD + ABCD + ABCD + ABCD + ABCD
product of sums (POS) form→ group of 0's (b) ABCD + ABCD + ABCD + ABCD + ABCD
canonical form (standard SOP and POS form)
(c) ABCD + ABCD + ABCD + ABCD + ABCD
79. Logic function (A + B)(A + B) can be reduced (d) ABCD + ABCD + ABCD + ABCD + ABCD
to: IES - 2013
(a) B (b) B Ans. (b) : Y = AB + ACD
(c) A (d) A
IES -2015, 2013
Ans. (a) : Y = ( A +B) (A+B)
= A A + A B + AB + B.B
= 0 + A B + AB + B
= B ( A +A) + B Q A +A = 1
=B+B Y = AB C D +AB C D+ABCD+ABC D +A B CD
=B 84. A 3-variable truth table has a high output for
80. Logic function ABD + ABD can be reduced to: the inputs: 010, 011 and 110. The Boolean
(a) AB (b) AB expression for sum of product (SOP) can be
(c) BD (d) AD written as:
IES - 2013 (a) AB + BC (b) AB + BC
Ans. (b) : Y= AB D+A BD (c) AB + BC (d) AB + BC
IES - 2013
Ans. (a) :
ABC
Y=AB 0 000
81. The logic function f(A,B,C,D) 1 0 01
= (A + BC)(B + CD) can be expressed to: 2 010 ABC
3 01 1 ABC
(a) AB + BC + ACD + BCD
4 1 00
(b) AB + AB + ACD + BCD
5 101
(c) AB + AB + ACD + BCD 6 1 10 ABC
(d) AB + AB + ACD + BCD 7 1 11
IES - 2013
sum of product (SOP) = A B C + A BC+AB C 88. The logic function f = X.Y + X.Y is the same
= A B( C +C)+AB C as:
(a) f = (X + Y)(X + Y)
= A B+AB C
(b) f = (X + Y)(X + Y)
= B( A +A C )
(c) f = (X.Y)(X.Y) (d) None of the above
= B{( A +A)( A + C )}
IES - 2012
= B{1( A + C )}
Ans. (b) : f = X.Y + XY
SOP = A B + B C
= X.Y . X.Y
85. The Boolean equation X = {(A + B)(B + C)}B
f = ( X +Y) (X + Y )
can be simplified to f = X X+ X Y +X Y+Y Y
(a) X = AB (b) X = AB f = X Y +X Y Q XX = 0
(c) X = AB (d) X = AB
f = X Y + XY &Y. Y = 0
IES - 2012
Ans. (c) : X = { (A+ B )(B+C)}B ( )( )
f = XY . XY
X= { AB + AC + B B + B C}B f = (X + Y). (X + Y)
X= ( AB + AC + B C) B {Q B B = 0}
f = (X+Y) (X + Y)
X= AB.B + ABC + B B C
X= AB + ABC f = (X+Y) (X+Y)
X= AB(1+C) f = (X+Y) (X+Y)
X= AB
89. If the Boolean expression PQ + QR + PR is
86. The correct expression is
minimized, the expression becomes
(a) AB + AB = AB(A + B)
(a) PQ + QR (b) PQ + PR
(b) AB + AB = AB(A + B) (c) QR + PR (d) PQ + QR + PR
(c) AB + AB = AB(A + B) IES - 2011
(d) AB + AB = AB(A + B) Ans. (b) : Y = P Q + QR + PR
Y (PQR) = ∑ (2, 3, 5, 7)
IES - 2012
Ans. (a) : A B+A B = AB (A+B)
RHS
AB (A+B) where-
Y= P Q + PR
( A + B ) (A+B) = A B+A B (LHS) A.A = 0
90. Boolean expression
the option (a) is correct B.B = 0
A + B + C + A + B + C + A + B + C + ABC
87. Simplified form of the logic expression reduces to
(A + B + C)(A + B + C)(A + B + C) is (a) A (b) B
(c) C (d) A + B + C
(a) AB + C (b) A + BC
IES - 2010
(c) A (d) AB + C
Ans. (b) : Y = A+B+C + A + B + C + A + B + C +ABC
IES - 2012
Y = A.B.C + A.B.C + A.B.C + ABC
Ans. (b) : (A+ B +C) (A+ B + C ) (A + B + C)
Y = B C ( A +A) + BC(A + A ) Q A +A= 1
Y= (A+ B +C) (A.A+AB+AC+A B + B .B+ B C
Y = B C + BC
+A C +B C +C C )
Y = B (C+ C ) (C+ C =1)
Y = ( A + B + C ) ( A + AB + AC + AB + BC + AC + BC ) Y=B
{ }
Y = ( A + B + C ) A (1 + B + C + B + C ) + BC + BC
91. The standard SOP expression for Boolean
expression AB + AC + BC is
Y= (A+ B +C) (A+ B C +B C ) (a) ABC + ABC + ABC + ABC
= (A+A B C+AB C +A B + B C+ 0 + AC+ B C + 0) (b) ABC + ABC + ABC
(c) ABC + ABC + ABC
= A(1+ B C+B C + B + C) + B C + B C
(d) ABC + ABC + ABC
= A + BC + BC = A +BC IES - 2010
Ans. (a) : Y= A B +AC+BC Ans. (d) : The ultimate purpose of minimizing logic
expressions to implement the function of the logic
expression with least hardware and also to reduce the
expression for making it feasible for hardware
implementation.
95. The Boolean functions can be expressed in
Y = A BC+ABC+A B C +A B C canonical SOP (sum of products) and POS
92. The complement of the expression (Product of sums) form. For the function,
Y = ABC + ABC + ABC + ABC is Y = A + BC , which are such two forms
(a) (A + B)(A + C) (b) (A + B)(A + C) (a) Y = ∑ (1, 2,6, 7) and Y = Π (0, 2, 4)
(c) (A + B)(A + C) (d) (A + B)(A + C) (b) Y = ∑ (1, 4,5, 6,7) and Y = Π (0, 2,3)
TNPSC AE-2019 (c) Y = ∑ (1, 2,5, 6,7) and Y = Π (0, 2,3)
IES - 2010
(d) Y = ∑ (1, 2, 4,5,6,7) and Y = Π (0, 2,3)
Ans. (d) : Y = ABC+AB C + A B C+ A BC
IES-2016, 2015, 2008
Y = AB(C+ C )+ A C( B +B) Q( B +B=1)
Ans. (b) : Y = A+ B C
Y = AB + A C ( C +C =1)
to complement
Y = A.B + A.C
Y = (A + B)(A + C)
93. Which of the following Boolean algebra rules is SOP (sum of product) =∑(1,4,5,6,7)
correct ? POS (product of sum) = Π (0,2,3)
(a) A.A = 1 (b) A + AB = A + B Q SOP is minterm and POS is maxterm
(c) A + AB = A + B (d) A(A + B) = B 96. Which one of the following statements is not
IES - 2009 correct ?
Ans. (c) : (a) A. A = 0 (a) X + XY = X
A. A ≠ 1 (b) X(X + Y) = XY
(b) A + AB = A + B (c) XY + XY = X
LHS –– (d) ZX + ZXY = ZX + ZY
A + AB IES - 2008
A(1+B)
A≠A+B Ans. (a) : X+ X Y = X
(C) A + A B = A + B X+ X Y = (X+ X )(X+Y)
LHS –– = (X+Y) ≠ X
A+ A B = (A+ A )(A+B) (b) X( X +Y) = XY
= 1(A+B) LHS –
= A+B = RHS X( X +Y) = X X +XY = XY
(d) A(A+B) = B
LHS –– (c) XY+X Y =X
A(A+B) = A.A+AB LHS–
= A+AB = XY+X Y
= A(1+B) = X(Y+ Y ) = X
=A≠B Then XY+X Y = X
94. What are the ultimate purposes of minimizing
logic expressions ? (d) ZX+Z XY = ZX+ZY
1. To get a small size expression. LHS–
2. To reduce the number of variables in the = ZX+Z X Y = Z(X+ X Y)
given expression. = Z{(X+ X )(X +Y)} = ZX+ZY
3. To implement the function of the logic
expression with least hardware. 97. Two 2's complement numbers having sign bits
4. To reduce the expression for making it 'x' and 'y' are added and the sign bit of the
feasible for hardware implementation. result is 'z' which boolean function indicates
Select the correct answer from the codes given the occurrence of the overflow ?
below: (a) x y z (b) x y z
(a) 1 only (b) 2 and 3 (c) x yz + xyz (d) xy + yz + zx
(c) 3 only (d) 3 and 4 IES – 2008
IES - 2009 GATE-1998
Ans. (c) : Let A and B are two number and S = sum 3. (a ⊕ b) c
A = x.........b1b0 4. abc + a bc + abc
B = y.........c1c0 Codes:
–––––––––––––––––––– A B C D
S = z .........s1s0 (a) 3 2 1 4
Condition of overflow are – (b) 2 3 1 4
(a) Sum of two +ve number results in a –ve number.
(c) 3 2 4 1
A → +ve number, if x = 0, B is +ve number, if y = 0
(d) 2 3 4 1
A + B ⇒ z = 1 then overflow occurs
IES - 2007
so, Boolean function ⇒ x y z
Ans. (b) : (a) ab + bc +ca +abc
(b) Sum of two –ve number results in a +ve number.
A → –ve number, if x = 1, B is –ve number, if y = 1
A + B ⇒ z = 0 then overflow occurs.
so, Boolean function ⇒ xyz
hence, combining these above two conditions F= ab + bc + ca + abc
inverse function of A
x yz + x yz
98. When the Boolean function
F(x1 , x 2 , x 3 ) = ∑ (0,1, 2,3) + ∑ φ(4,5,6,7) is
minimized, what does one get ? F =a b+b c+c a
(a) 1 (b) 0 (b)
(c) x1 (d) x3
IES - 2007
Ans. (a) : F(x1 , x 2 , x 3 ) = ∑ ( 0,1, 2,3) + ∑ φ(4,5,6,7)
F= ab+ a b + c
inverse function of B
where × = don't care

From K-map we get F( x1,x2,x3) = 1
99. By inspecting the Karnaugh map plot of the F = abc + abc
switching function F(x1x2x3) = ∑ (1, 3, 6, 7) one F = (ab + ab)c
can say that the redundant prime implicant is = (a⊕b)c
(a) x1x 3 (b) x2x3 (c)
(c) x1x2 (d) x3
IES - 2007
Ans. (b) : F( x1x2x3) = ∑(1,3,6,7)
F = a+bc
inverse function of C
From K-map the common pair is redundant prime F = a b+ac

impliment =x2x3
100. Match List-I (Boolean logic function) with List- = a(b + c)
II (Inverse of function) and select the correct (d)
answer using the code given below the lists:
List-I
A. ab + bc + ca + abc
B. ab + a b F = ( a + b + c )(a+ b + c )( a + b +c){ for max term}
C. a + bc inverse function of D –
D. (a + b + c)(a + b + c)(a + b + c)
List-II
1. a (b + c)
2. a b + b c + c a F = abc+ a bc+a b c

101. Consider the following statements : Ans. (a) : For f =1
1. Minimization using Karnaugh map may
not provide unique solution
2. Redundant grouping in Karnaugh map
may result in non-minimized solution.
3. Don't care states if used in Karnaugh map
for minimization, the minimal solution is f = A BC+AB C
not obtained. f = A BC+AB C
correct ? f = B( A C+A C )
(a) 1, 2 and 3 (b) 2 and 3 only f = B(A+C)( A + C )
(c) 1 and 3 only (d) 1 and 2 only 105. What is the minimized logic expression
IES - 2007 corresponding to the given Karnaugh Map ?
Ans. (d) : With reference to K-map
(i) minimization using karnaugh map may not provide
unique solution .
(ii) Redundant grouping in karnaugh map may result in
non minimized solution
102. What does the Boolean expression
AD + ABCD + ACD + AB + ACD + AB, on (a) xz
minimization result into ? (b) wxy + wyz + wyz + wxy
(a) A + D (b) AD + A
(c) wxy + wyz + wyz + wxy
(c) AD (d) A + D
IES - 2006 (d) xz + wyz + wxy + wxy + wyz
IES - 2005
Ans. (d) : f = AD + ABCD + ACD + A B
Ans. (b) :
+ ACD+ A B
f = ABCD + ACD + AD + ACD+ A B+ A B
f = ACD(1 + B) + AD( 1+C)+ A (B+ B )
f = ACD+ AD+ A
f = AD(C+1)+ A
f = AD+ A d
f = ( A +A)( A +D) F = wxy + wyz + wyz + wxy
f = 1.( A +D)
106. The Boolean function (x + y)(x + z)(y + z) is
f = A +D
equal to which one of the following
103. If A and B are Boolean variables, then what is expressions?
(A + B). (A + B) equal to ? (a) (x + y)(y + x) (b) (x + z)(y + z)
(a) B (b) A (c) (x + y)(x + z) (d) (x + y)(x + z)
(c) A + B (d) AB
IES - 2006 IES - 2005
Ans. (c) : F = (x+y) ( x +z)(y+z)
Ans. (b) : F= (A+B)(A+ B ) F = (x+y) ( x y + x z + yz + zz )
F = AA+A B +BA+B B Where- F = (x+y) ( x y + x z + yz + z)
F = A+A( B +B)+0 B.B = 0 F = x. x y + x x z + xyz + xz + y x y + y x z + yyz + yz
F =0 + 0 + xyz + xz + y x + x yz + yz
F = A(1+ B +B) (1+ B +B=1) F = xyz + yz + xz + x y(1+z)
F = A×1 F = yz (x+1) + xz + x y + x x
F=A F = yz + xy + xz + x.x
104. What is the Boolean expression for the truth
table shown below ? F = y(z + x) + x (z + x) (Q xx = 0 )
A 0 0 0 0 1 1 1 1 F = (x+y) (z+ x )
B 0 0 1 1 0 0 1 1 107. AB + AC = (A + C)(A + B) Which one of the
C 0 1 0 1 0 1 0 1 following is the dual form of the Boolean
identity given above ?
f 0 0 0 1 0 0 1 0
(a) AB + AC = AC + AB
(a) B(A + C)(A + C) (b) B(A + C)(A + C) (b) (A + B)(A + C) = (A + C) + (A + B)
(c) B(A + C)(A + C) (d) B(A + C)(A + C) (c) (A + B)(A + C) = AC + AB
IES - 2006 (d) AB + AC = AB + AC + BC
CGPSC SO – 14.02.2016 IES - 2005
Ans. (c) : Dual expression is equivalent to write a Then 1 .0 = 0
negative basic of the given boolean relation. The (d) A⊕B = 1
procedure is -
when the both input is different then output will be 1
(i) change each OR sign by an AND sign and vice-
versa i.e. A ≠ B
(ii) complement any '0' or 1 opening in expression then A⊕B = 1
AB + A C = (A + C)( A + B) List-I List-II
(A + B)( A + C) = (A.C) + A B (A) A⊕B = 0 (2) A = B
108. A, B and C are three Boolean variables. Which (B) A + B = 0 (3) A = 1 or B = 1
one of the following Boolean expressions cannot (C) A .B = 0 (4) A = 1 or B = 0
be minimized any further? (D) A⊕B = 1 (1) A ≠ B
(a) Z = A.B.C + A.B.C + A.B.C + A.B.C
110. The Boolean expression (A + B)(A + C)(B + C)
(b) Z = A.B.C + A.B.C + A.B.C + A.B.C
simplifies to
(c) Z = A.B.C + A.B.C + A.B.C. + A.B.C
(a) (A + B)C (b) (A + B)C
(d) Z = A.B.C + A.B.C + A.B.C + A.B.C
IES - 2004 (c) (A + B)C (d) (A + B)C
Ans. (c) : (a) Z = A B C +AB C +ABC+ A BC IES - 2003
Z = B C(A + A) + AB(C + C) Ans. (c) : F = ( A +B) (A+ C )( B + C )
Z = B C + AB F = ( A +B) (A B +A C + B C + C )
(b) Z = A. B C+AB C +ABC+ A BC F = A A. B + A A C + A B C + A C + AB B + BA C
+B B C + B C
Z = AC(B+ B ) + AB C + A B C
F = 0+ 0+ A B C + A C + 0+ AB C +B C
Z = AC + AB C + A B C
F = A B C + A C + AB C +B C
Z = AC+ C (AB + A B )
F = A C ( B + 1) + BC ( A + 1)
Z = AC+ C (A☼B)
(c) Z= A. B C + A B C+ ABC + A B C F = A C+ BC
this Boolean expressions can not minimized. F = ( A +B) C
(d) A B C + A B C + ABC + ABC 111. The minimized expression for the given K map
(x: don't care) is
B C ( A + A ) + C ( AB + AB )
BC + C ( A  B )
List-I List-II
A. A ⊕ B = 0 1. A ≠ B
B. A + B = 0 2. A = B
C. A.B = 0 3. A = 1 or B = 1 (a) A + BC (b) B + AC
D. A ⊕ B = 1 4. A = 1 or B = 0 (c) C + AB (d) ABC
Codes: IES - 2002
A B C D Ans. (a) :
(a) 3 2 1 4
(b) 2 3 4 1
(c) 3 2 4 1
(d) 2 3 1 4
IES - 2004
Ans. (b) : List - I
(a) A⊕B = 0
A⊕B is a XOR gate
when both input is same then output will be zero if A Y = A +BC
=B then A⊕A = 0 112. Consider the Boolean expression X = ABCD +
(b) A + B = 0 ABCD + ABCD + ACBD The simplified form
when A=B=1 then ––––– of X is
A + B =1 +1 =1 = 0 (a) C + D (b) BC
(c) A .B = 0 (c) CD (d) B+C
when A = 1 or B = 0 IES - 2002

Ans. (c) : X = ABCD+A B CD + A BCD + A C B D Ans. (a) : A+( A.B )
X = ACD(B+ B ) + A CD (B+ B ) A +AB
X = ACD + A CD Q B+ B =1 (A+ A )(A+B)
X = CD (A+ A ) A+ A =1 1× (A+B)
X =CD (A+B)
113. For the Karnaugh map shown in the given if we look at the whole area of both the sum of all
figure, the minimum Boolean function is scratch areas
117. How many minterms (excluding redundant

(a) x'y' + z' + yz (b) xz' + z + zy' terms) does the minimal switching function
(c) xy + z + y'z (d) x'z + z' + yz f(v, w, x, y, z) = x + yz originally have?
IES - 2001
(a) 16 (b) 20
Ans. (d) :
(c) 24 (d) 32
IES - 1998
Ans. (b) : f(v,w,x,y,z) = x+ y z
= (x+ y z)(v+ v )
F = yz + z + x z = (x+ y z)v+( x+ y z ) v
114. Which one of the following is equivalent to the
Boolean expression Y = AB + BC + CA?
(a) AB + BC + CA
( )(
(b) A + B B + C A + C )( )
(c) ( A + B)( B + C )( C + A )
minterm = 10 + 10 = 20
(d) ( A + B) ( B + C ) ( C + A ) 118. While obtaining minimal sum of products
IES - 2001 expression,
Ans. (c) : Y = A B + B C + C A (a) All don't cares are ignored
= A + B+ B+C+C+ A (b) All don't cares are treated as logic ones
{from demorgan theorem} (c) All don't cares are treated as logic zeros
(d) Only such don't cares as logic ones
= (A + B).(B + C).(C + A) minimization are treated as logic ones
115. Karnaugh map is used to IES - 1998
(a) minimize the number of flip-flops in a digital Ans. (d) : While obtaining minimal sum of products
circuit expression only such don't cares as logic ones
(b) minimize the number of gates only in a digital minimization are treated as logic ones
circuit
(c) minimize the number of gates and fan in of a 119. The complement of the Boolean expression
digital circuit AB × (BC + AC) is
(d) design gates (a) (A + B) + (B + C)(A + C)
IES - 2000
Ans. (b) : Karnaugh map is used to minimize the (b) (A ⋅ B) + (BC + AC)
number of gates in a digital expressions and is referred (c) (A + B) ⋅ (B + C)(A + C)
to as the graphical technique of simplifying Boolean
expression. (d) (A + B) ⋅ (B + C)(A + C)
116. The Venn diagram representing the Boolean IES - 1998
(
expression A + A × B is ) Ans. (a) : F = AB×( B C +AC)
to complement
F = AB × (BC + AC)
F = AB + (BC + AC)
F = (A + B) + (BC)AC
F = ( A + B ) + ( B + C )( A + C )
IES - 1998
120. Consider the Karnaugh map given below : The Ans. (b) :
function represented by this map can be
simplified to the minimal form as
Y= AB C + AC B + BC A
123. The minimized expression for the given k –
map is (X: don't
A
care)
(a) x1 x 2 x 4 + x 2 x 4 + x 1 x 3 B
CD
00 01 11 10
(b) x1 x 2 x 4 + x 2 x 4 + x1 x 2 x 3 x 4 00 1 1
(c) x 2 x 4 + x 2 x 4 + x1 x 3 01 1 X
11 1 1 X X
(d) x1 x 2 x 4 + x1 x 2 x 3 x 4 + x1 x 2
10 1 X X
IES - 1997
Ans. (c) : (a) CB + BD + CD (b) AB + C B + B C
(c) CB + AC + BC (d) CB + BD + C B
IES - 1996
Ans. (d) :
f = x 2 x 4 +x2x4+x1 x 3
121. Which one of the following is the dual form of
the Boolean Identity? Y = C B+BD+C B
A B + A C = (A + C)(A + B)? 124. The simplified Boolean expression from the
Karnaugh map given in the figure is
(a) AB + A C = AC + AB
(b) (A + B) + (A + C) = (A + C) (A + B)
(c) (A + B)(A + C) = AC + AB
(d) AB + AC = AB + A C + BC
IES - 1996
Ans. (c) : A B+ A C = (A+C).( A +B) (a) A C + A D + ABC
Dual form ––
(b) A B + A D + ABC
(A + B).(A + C) = (A.C) + A.B
Duality principle :- (c) A C + ACD + ABC + BCD
(I) every OR operator change in to AND operator and (d) AB+ CD + AD
every AND operator change into OR operator. IES - 1995
(II) every 1's change in to 0's and every 0's change into
Ans. (a) :
1's
122. The Boolean expression for the shaded area in
the given Venn diagram is
Y = A C + A D + A BC
(a) AB +BC +CA 125. What is dual of A + [B + (AC)] + D
(b) ABC + A BC + A BC (a) A + [B (A + C)] + D
(c) ABC + A BC (b) A [B + AC] D
(c) A + [B (A + C)] D
(d) A BC + A BC (d) A [B (A + C)] D
IES - 1996 IES - 1992
Ans. (d) : F = A + [B + (AC)] + D 129. What is Boolean expression for getting network
From dual theorem –– that will have output 0 only, when X = 1, Y = 1,
F = A.[B.(A+C)].D Z = 1; X = 0, Y = 0, Z = 0; X = 1, Y = 0, Z = 0?
every OR operation change into AND operation and (a) XYZ + XYZ + XYZ
every AND operation change into OR operation. (b) (XYZ)(X + Y + Z)(X + Y + Z)
126. The product-of-sum expression for given truth (c) (X + Y + Z)(X + Y + Z)(X + Y + Z)
table is :
X Y Z (d) XYZ + XYZ + XYZ
0 0 1 IES - 1992
0 1 0 Ans. (c) :
1 0 1
1 1 0
(a) (X + Y) (X + Y) (b) (X + Y) (X + Y)
(c) (X + Y) (X + Y) (d) None of the above
IES - 1992
Ans. (b) :
X Y Z (output)
0 0 1
0 1 0
1 0 1
1 1 0
P = ( X+Y+Z) ( X +Y+Z)( X + Y + Z )
product of sum (z) = (X + Y)(X + Y)
130. The term AB + AC + BC reduces to
127. The expression for shaded area shown below is: (a) AB + CA (b) AC + BC
(c) AC + BC (d) AB + BC
IES - 1991
Ans. (c) : AB + AC + B C
(a) A B + B C (b) A BC + AB C
(c) A BC + AB C (d) None of the above.
IES - 1992 then Y = B C +AC
Ans. (c) : 131. If x, y and z are Boolean variables, then the
expression
x(x + xy) z (x + y + z) is equal to
(a) x + xy (b) x + y + z
(c) xyz (d) xz
IES - 1991
Ans. (d) :x (x + xy) z (x + y + z)
= x.x ( 1+y) z(x + y + z) = xz (x + y + z)
• For shaded area I→ A =1, B=1, C = 0 = xz + xyz + xz
• Shaded area II → A = 0, B = 1, C = 1 = xz+xyz
then total shaded area = AB C + A BC = xz(1 + y)
= xz
128. What is dual of X + XY = X + Y .
132. The number of Boolean functions that can be
(a) X + Y = XY (b) X + XY = XY generated by n variables is equal to :
(c) X(X + Y) = XY (d) X(X + Y) = X + Y (a) 22
n −1
(b) 22
n
IES - 1992 (c) 2n −1 (d) 2n

Ans. (c) : X + X Y = X+Y Punjab PSC Poly.Lect. 20.08.2017
dual theorem ⇒ All OR operation change into AND Ans. (b) : The number of Boolean function that can be
n
operation and every AND operation change into OR generated by n variables is equal to 22 .
operation
133. The K-map for a Boolean function is shown in
X+ X Y = X + Y figure. The number of essential prime
X.( X +Y) = XY implicants for this function is
(iii) Y = RS + P R + P Q + P Q
( )(
Y = RS + P R. P Q )( P Q)
Y = RS + (P + R) (P + Q) (P + Q)
(a) 4 (b) 5 Y = RS + (P + R) (P + Q) (P + Q)
(c) 6 (d) 8
GATE-1998 Y = RS + (P P + P R + P Q + R Q) (P + Q)
Ans. (a) : Essential prime implicants = 4 Y = RS+ ( PP + PPR + PPQ + PRQ + PQ
+ P R Q + P Q Q + R Q Q)
Y = RS + P Q R + P Q + P RQ + P Q + RQ
Y = RS + QR ( P + P + 1) + PQ
Y = RS+QR +PQ ......(iii)
(iv) Z = R + S + PQ + P QR + P Q S
Essential Prim implicants (EPI) ⇒ These are those
groups which cover atleast one minterm that can not be = R + S + P(Q + QS) + P Q R
covered by any other prime implicants = R + S + P(Q + S) + P Q R Q (A + A B = A + B)
134. The minimized form of the logical expression
(ABC + ABC + ABC + ABC) is = R + S + P(Q + S).P Q R
(a) AC + BC + AB (b) AC + BC + AB = R + S + (P + QS) (P + Q + R)
(c) AC + BC + AB (d) AC + BC + AB = R + S + P Q + P R + P QS + QS R
GATE-1992 = R + PR + PQ + S + P QS + QS R
Ans. (a) : A B C + A B C + A B C + A B C = R(1 + P) + P Q + S(1 + P Q + QR)
Z = R + PQ+S .....(iv)
Z = R + PQ +S
F = A C + A B + BC
(
= P +S PQ)( )
135. If the functions W, X, Y and Z are as follows = R S (P + Q)
W = R + PQ + RS Z = P RS + Q RS
X = PQRS + PQRS + PQRS from equation (i) & (iv) W = Z and from equation
Y = RS + PR + PQ + PQ (ii) & (iv) X = Z
Z = R + S + PQ + PQR + PQS Z = R +S+PQ ....(iv)
Then In the above solution we see that
W=Z
(a) W = Z, X = Z (b) W = Z, X = Y
X=Z
(c) W = Z, X = Y (d) W = Y = Z
GATE-2003 136. The Boolean expression for the truth table
Ans. (a) : shown is
(i) W = R + P Q+ RS
( )
W = R + R ( R + S) + P Q
W = R +S+PQ ...(i)
(ii) X = PQR S+P Q R S+ PQ R S
X = PQR S+ Q R S P + P ( )
X = PQR S+ Q R S
(
X = RS PQ +Q )
(a) B(A + C)(A + C) (b) B(A + C)(A + C)
X = R S ( P + Q )( Q + Q )
(c) B(A + C)(A + C) (d) B(A + C)(A + C)
X = R S P + R SQ ......(ii) GATE-2005

Ans. (a) : (a) XY, XY
(b) XY,XYZ, XYZ
(c) XYZ, XYZ, XY
(d) XYZ, XYZ, XYZ, XYZ
GATE-2012
Ans. (a) : f(X,Y,Z) = ∑(2,3,4,5)
Y = ( X Y+X Y )
So, prime implicants are XY and XY
F = A BC+AB C 140. The Boolean expression
F = B( A C+A C ) (X + Y)(X + Y) + (XY) + X simplifies to

(a) X (b) Y
F = B(A+C) ( A + C ) (c) XY (d) X + Y
137. The Boolean expression GATE-2014
Y = ABCD + ABCD + ABCD + ABCD Ans. (a) : Y = (X+Y)(X+ Y )+ (X Y) + X
can be minimized to
(a) Y = ABCD + ABC + ACD Y = (X+Y)(X+ Y )+ X.Y.X
(b) Y = ABCD + BCD + ABCD Y= (X+Y) (X+ Y )+ (X + Y) .X
(c) Y = ABCD + BCD + ABCD Y= X.X+X Y +XY+Y Y +(X+Y).X
(d) Y = ABCD + BCD + ABCD Y= X+ X Y +XY+X+XY
GATE - 2007 Y= X+XY+X Y
Ans. (d) : A BC D + ABCD + ABCD + ABC D Y= X(1+Y+ Y )
Y= X
141. Consider the Boolean function,
F(w, x, y, z) = wy + xy + wxyz + wxy + xz + x y z .
Which one of the following is the complete set
of essential prime implicants ?
(a) w, y, xz, x z (b) w, y, xz
(c) y, x y z (d) y, xz, x z
Y= AB C D + BCD + ABCD Nagaland PSC CTSE (Degree)-2017, Paper-II
138. If X = 1 in the logic equation GATE-2014
 { }
 X + Z Y + ( Z + XY )  {X + Z ( X + Y )} = 1 ,

Ans. (d) :
F(w,x,y,z)=wy+xy+ w xyz+ w x y+xz+ x.y.z
then
(a) Y = Z (b) Y = Z
(c) Z = 1 (d) Z = 0
GATE-2009
Ans. (d) : [ X+Z{ Y +( Z +X Y )}] { X + Z (X+Y)} = 1
if X= 1
[ 1+Z{ Y +( Z +X Y )}] { 1 + Z (1+Y)} = 1
[ 1+Z{ Y + Z +X Y }] {0+ Z } = 1 F= y+xz+ x z
[ 1+Z Y +Z Z +ZX Y ] { Z } = 1 The set of essential prime implicants is y, xz, x z
[ 1+ Y Z+ZX Y ] { Z } = 1
142. For an n-variable Boolean function, the
Z =1 because { 1+ Y Z+ZX Y = 1} maximum number of prime implicants is
Z=0 (a) 2(n - 1) (b) n/2
139. In the sum of products function f (X, Y, Z) = Σ (c) 2n (d) 2(n - 1)
(2, 3, 4, 5), the prime implicansts are GATE-2014
Ans. (d) : In a n variable Boolean function, the
maximum number of prime implicant is given by
2n
= 2( )
n −1
Pmax =
2
143. The Boolean expression
F(X, Y, Z) = XYZ + XYZ + XYZ + XYZ
converted into canonical product of sum (POS)
(a) PQSX + PQSX + QRSX + QRSX
form is
(a) (X + Y + Z) (X + Y + Z) (X + Y + Z) (b) QSX + QSX
(X + Y + Z) (c) QSX + QSX
QS + QS
(b) ( X + Y + Z) ( X + Y + Z) ( X + Y + Z) (d)
GATE-2016
( X + Y + Z) KVS TGT (WE)- 2014
(c) ( X + Y + Z) ( X + Y + Z) ( X + Y + Z) Ans. (b) : Here 5 Variables are present - (P,Q,R,S,X)
( X + Y + Z)
(d) ( X + Y + Z) ( X + Y + Z) ( X + Y + Z)
( X + Y + Z)
GATE-2015
Ans. (a) : F ( X,Y, Z ) = XYZ + XYZ + XYZ + XYZ Q S. X Q. SX
Y = Q S X + Q. SX
146. Which one of the following gives the simplified
sum of products expression for the Boolean
function F = m 0 + m 2 + m 3 + m 5 where m0, m2,
F ( X,Y, Z ) = ( X + Y + Z )( X + Y + Z )( X + Y + Z ) m3 and m5 are minterms corresponding to the
( X + Y + Z) inputs A, B and C with A as the MSB and C as
the LSB ?
= (X + Y + Z) ( X + Y + Z )( X + Y + Z )( X + Y + Z )
(a) AB + ABC + ABC (b) AC + AB + ABC
In SOP – In POS – (c) AC + AB + ABC (d) ABC + AC + ABC
1 → High 1 → Low
GATE-2017
0 → Low 0 → High
Ans. (b) :
144. A Function of Boolean variables, X, Y and Z is
expressed in terms of the min-terms as
F (X, Y, Z) = Σ (1, 2, 5, 6, 7)
Which one of the product of sums given below
is equal to the function F (X, Y, Z) ?
(a) (X + Y + Z) . (X + Y + Z) . (X + Y + Z) Given F= m0+m2+m3+m5 Y = A C + AB + ABC
(b) (X + Y + Z) . (X + Y + Z) . (X + Y + Z) 147. A function F(A, B, C) defined by three Boolean
(c) (X + Y + Z) . (X + Y + Z) . (X + Y + Z) variables A, B and C when expressed as sum of
(X + Y + Z) . (X + Y + Z) products is given by
F = A.B.C. + A.B.C + A.B.C.
(d) (X + Y + Z) . (X + Y + Z) . (X + Y + Z)
where, A , B , and C are the complements of
(X + Y + Z) . (X + Y + Z)
the respective variables. The product of sums
GATE-2015 (POS) form of the function F is
Ans. (b) : Given min term expression
(a) F = (A + B + C).(A + B + C).(A + B + C)
F(X,Y,Z) = ∑m(1,2,5,6,7)
Then the max term expression is - (b) F = (A + B + C).(A + B + C).(A + B + C)
F ( X,Y, Z ) = ∑ m (1,2,5,6,7 ) = ΠM ( 0,3, 4 ) (c) F = (A + B + C).(A + B + C).(A + B + C)
F = ( X + Y + Z ) ( X + Y + Z )( X + Y + Z ) .(A + B + C).(A + B + C)
145. Following is the K-map of a Boolean function (d) F = (A + B + C).(A + B + C).(A + B + C)
of five variables P, Q, R, S and X. The
minimum sum-of-product (SOP) expression for .(A + B + C).(A + B + C)
the function is GATE-2018
Ans. (C) : F= A BC + ABC + ABC 152. In a logic equation
It can be represented in min term as: ( ) (
A A + BC + C + B C + A + BC )
F = ∑ m ( 0,2,4 ) +(A + BC + AC) = 1, if C = A then
and max term as :
(a) A + B =1 (b) A + B = 1
F = ∏ M (1,3,5,6,7 )
(c) A + B = 1 (d) A = 1
F = ( A + B + C )( A + B + C )( A + B + C )( A + B + C )( A + B + C ) TSPSC Manager (Engg.) - 2015
148. The Boolean expression x'y + xy' + xy is Ans. (c) :
equivalent to
(a) (x+y)' (b) x'y ( ) (
A A + BC + C + B C + A + BC + (A + BC + AC) = 1 )
(c) x+y (d) xy
TSGENCO AE-2015
Put the value of C = A ( )
Ans. (c) : f = xy + xy + xy ( ) (
A A + BA + A + B A + A + AB + A + A B + AA = 1 ) ( )
f = (x + x)y + xy
f = y + xy
(
A 1 + AB + B 1 + AB + A + A B + A = 1 ) ( )
f = (y + y)(y + x) A + B+ AB =1
f = 1(y + x) A + B (1 + A ) = 1
f = (x+y) A + B =1
149. A lamp is controlled from two positions A and 153. n-bit variables have 2n possible combinations
B (Ex. staircase circuit). The boolean and each of these possible combinations is
expression for the above circuit is called
(a) AB + AB (b) AB + AB (a) Maxterm (b) Minterm
(c) AB + AB (d) AB + AB (c) Product of sum (d) Sum of product
Kerala PSC Lecturer (NCA) 04.07.2017 TSPSC Manager (Engg.) - 2015
Ans. (b) : Each individual term in SOP form which
Ans. (b) : In case of staircase, when both switch are
different position, then bulb will ON. And it is thecontains every variable either in true of complemented
example of EX-OR Gate, Y = A ⊕ B form is called as minterm.
Y = AB + AB 154. The simplified expression of:
150. For the Boolean expression ABC + ABC + ABC, XYZ + XY Z + YZ + XZ will be:
how many 1's are in the output column of the (a) Z (b) Y
truth table (c) X (d) XY
(a) 2 (b) 3 UPSC Poly.Lect.10.03. 2019
(c) 4 (d) 5
Punjab PSC Poly. Lect. 20.08.2017 Ans. (a) : F = XYZ + XY Z + YZ + XZ
Ans. (b) : F = ABC + ABC + ABC F = Y Z ( X + 1) + XZ + XY.Z
F = YZ + XZ + XY.Z
F = YZ + XZ + ( X + Y ) Z
F = YZ + XZ + XZ + YZ
The number of one’s in truth table is, 3.
F = YZ + Z
151. Minimum number of gates required to
implement the Boolean expression XY + X(X + F = Z (1 + Y )
Z) + Y(X + Z) after simplification is F= Z
(a) 1 (b) 3
(c) 2 (d) 4 155. The complement of the Boolean expression
Punjab PSC Poly. Lect. 20.08.2017 AB BC + AC ( )
Ans. (c) : O/p = XY + X (X + Z) + Y(X + Z)
= XY + X + XZ + XY + YZ (a) A + B + B + C A + C ( ) ( )( )
( ) ( )
= X ( 1 + Y + Z + Y) + YZ
= X + YZ (b) A.B + BC + AC
(c) ( A + B ) .( B + C )( A + C )
(d) ( A + B ) .( B + C ) ( A + C )
Minimum two gate required APGENCO AE- 23.04.2017

Ans. (a) : F = A + AB + ABC
Ans. (a) : AB. ( BC + AC ) = AB + ( BC + AC )
F = A ( B + B' )( C + C' ) + AB ( C + C') + ABC
( ) ( )
= ( A + B ) + BC.AC = ( A + B ) + B + C .( A + C ) F = ( AB + AB' )( C + C') + ABC + ABC'+ ABC
= ( A + B ) + ( B + C ) .( A + C ) F = ABC + ABC' + AB'C + AB'C' + ABC + ABC'
+ ABC
156. The simplification of AC + ABC is : F = ABC + ABC' + AB'C + AB'C'
F = ∑ m ( 4, 5,6, 7 )
(a) A + BC (b) AC - AB
(c) BC (d) (A + B)C 161. The sum of product form of the given
APPSC Poly. Lect. 15.03.2020 expression f = (x + z) (x'+y) (y+z) is
(a) xy + yz (b) xy + x'z
Ans. (d) : AC + ABC (c) xyz + xz' (d) xy + y'z
= (A + AB)C Q A + AB = ( A + B ) ( A + A ) = A + B Nagaland PSC 2018, Diploma Paper-II
Ans. (b) : F = (x + z)(x' + y)(y + z)
= (A + B)C F = (x + z)(x'y + x'z + y + yz)
F = xx'y + xx'z + xy + xyz + zx'y + x'z + zy + yz
157. The complement of (A + B)(A + B) is : F = xy + xyz + zx'y + x'z + yz + yz Q x.x = 0
(a) B (b) A F = xy(1 + z) + x'zy + x'z + yz
(c) 1 (d) A F = xy + x'z(y + 1) + yz
APPSC Poly. Lect. 15.03.2020 F = xy + x'z + yz
Ans. (b) : = (A + B)(A + B) = AA + AB + BA + BB
= A + AB + BA
= A + A ( B + B) = A + A = A
158. The simplified Boolean equation for the F = xy + x 'z
following logic function is : 162. The simplified form of the given expression f =
f (A, B, C, D) = ∑m (7, 9,10,11,12,13,14,15) Σm(0, 1, 2, 4, 6) is
(a) f (A, B, C, D) = ABC + AD + BCD (a) A'B' + C' (b) AB + C'
(b) f (A, B, C, D) = AB + AD + BCD (c) ABC + B'C (d) None of these
(c) f (A, B, C, D) = AB + AC + AD+BCD Nagaland PSC 2018, Diploma Paper-II
(d) f (A, B, C, D) = AC + AD + BCD
TNPSC AE- 2019
Ans. (a) : f = ∑
m ( 0,1, 2, 4,6 )
From k-map.
Ans. (c) :
F = C+A B
163. In Karnaugh map following code is used for
fixing the value of a minterm
(a) Excess-3 code (b) 2421 code
(c) Gray code (d) 6423 code
F = AB + AD + AC + BCD
159. Name the table in which every row has only Ans. (c) : In Karnaugh map Gray code is used for fixing
one stable state the value of a minterm. In Gray code only one variable
(a) state table (b) flow table changes between each pair of adjacent cells.
(c) primitive flow table (d) Excitation table 164. The dual of the function f = xy + yz is
TNPSC AE- 2019 (a) (xy).(y + z) (b) (x + y) (yz)
Ans. (c) : A primitive flow table is a flow table which (c) (x + y).(y + z) (d) (xz). (y+z)
has only one stable state in each row. The total state Nagaland PSC 2018, Diploma Paper-II
consists of the internal state combined with the input. Ans. (c) : F = xy + yz
160. The canonical SOP form of given expression f = Dual of any function occurs when AND gate converted
A + AB + ABC is to OR gate and OR gate converted AND gate , 0
(a) Σm (4, 5, 6, 7) (b) Σm (1, 2, 3, 4) converted to 1 and 1 converted to 0.
(c) Σm (1, 3, 6, 7) (d) Σm (1, 7, 4) F = (x + y) ⋅ ( y + z)
165. In the expression A(A + B) by writing the first X [P, Q, R, S] = ∑ (1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 13, 14,
term A as (A + 0), the expression is best 15)
simplified as
(a) A + AB (b) AB
(c) A (d) A + B
Ans. (c) : A (A+B)
First term A as (A+0)
= (A+0) (A+B) = A.A + A.B + 0.A + 0.B.
= A + AB
=A
166. Boolean expression AC + CB is equivalent to : Y= PQRS +PQRS +PQRS
(a) AC + CB + AC Y [PQRS] = ∑ (0, 8, 12)
(b) BC + AC + CB + ACB
(c) ABC + AC + CB + CB
(d) ABC + ABC + ACB + ABC
GATE-2004
Ans. (d) : Y = AC + CB
(
Y = AC ( B + B ) + CB A + A )
Y = ABC + ABC + ABC + ACB
167. AB can be equivalently expressed as:
(a) A.B (b) A+B Y= PRS + QRS
(c) A + B (d) A + B
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I Y = R S [ P + Q ]
Ans. (c) : From De-Morgan's theorem- So X = Y
AB = A + B 170. The dual of A + B + C is
168. The Boolean expression A+A. B + AB can be (a) A.B.C (b) ( A + B ) + C
simplified as:
(a) AB (b) A ⊕ B (c) ( A + B ) .C (d) A + B.C
(c) ' A + B (d) A+B Nagaland PSC CTSE (Degree)-2017, Paper-II
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I Ans. (a) : Dual function of any logic occurs when AND
Ans. (d) : Y = A+A. B + AB gate converted into OR gate and OR gate converted into
Y = ( A + AB ) + AB AND gate. 1 is converted into 0 or 0 is converted into 1.
So, the dual of A + B + C will be A.B.C.
= A(1 + B) + AB Q 1+ B = 1
171. Minimum number of complementary CMOS
= A + AB
transistors pair will be required to implement
= (A + A ) (A + B)
function, F = ABC + ( A + B + C ) are
= (A + B)
(a) 6 (b) 7
169. If the function X, Y are X = R + P′Q + R′S and
(c) 8 (d) 9
Y = P′Q′ R′ S′ + P Q′ R′ S′ + P Q R′ S′ (where
represent complement). Which of the following ISRO Scientist- May, 2017
is true? Ans. (d) : Given that,
(a) X = Y
(b) X = Y′
(
F = ABC + A + B + C )
(c) no direct relation between X and Y To implement this function we can draw CMOS circuits
(d) insufficient data in following way.
Ans. (b) :
X=R +PQ+RS
X = R +S+ P Q

174. Simplify x + y . yz( )
(a) xyz (b) x + y + z
(c) xyz (d) xy + yz
(
Ans. (c) : x + y .yz )
= x.y.( y + z )
= ( x.y ) . ( y + z )
= xyy + xyz
= xyz
Z = ABC + A + B + C
175. In Boolean Algebra, AB + AB' is equivalent to
(
Z = ABC + A + B + C ) (a) 0 (b) 1
So, from above figures total number of CMOS = 9. (c) A (d) B
172. Simplify the function represented in sum of RRB SSE 03.09.2015, Shift-I
min-terms: Ans. (c) : AB + AB′
F(A, B, C, D, E) =Σ(0, 1, 2, 3, 8, 9, 16, 17, 20, 21, A(B + B′)
24, 25, 28, 29, 30, 31)
=A.1
(a) AD + (C + D) + ABC + (A + B + C) =A
(b) ADE + (C + E)D + ABCD + AEC 176. In Boolean Algebra, A'(A + B') is equivalent to
(a) A'B (b) AB
(c) ADB + (C + B) + CDE + (B + C + D)
(c) AB (d) A'B'
(d) AC + (D + E) + AE + (C + D + E) RRB SSE-03.09.2015, Shift-III
ISRO Scientist- May, 2017 Ans. (d) : A′ ( A + B′ )
Ans. (a) : F(A, B, C, D, E) =Σ(0, 1, 2, 3, 8, 9, 16, 17,
= A′A + A′B′
20, 21, 24, 25, 28, 29, 30, 31)
= 0 + A′B′
= A′B′
177. In Boolean Algebra, A+A+A+......+A is the
same as :
(a) Zero (b) A
(c) nA (d) An
RRB SSE 21.12.2014, (Red)
Ans. (b) : A+A+A+ ....... + A = A
Y = ABC + CD + AD + ABC 178. Consider the following truth table in Boolean
Y = AD + C + D + A BC + A + B + C Algebra.
173. ( A + B + C + D )( A + B + C + D )( BC + BC ) and
find which literal are not present
(a) A, C,D (b) A, B, C
(c) B, C, D (d) B, A, D
Ans. (a) : Given that-
Which of the four options A, B, C, D represent
(
(A + B + C + D) (A + B + C + D) BC + BC ) the function
(A + B + C + D) (A + B + C + D) B(C + C)  F = xy + xy′ ?
  QC + C = 1
(a) A (b) B
Solve by K-map- (c) C (d) D
Ans. (b) :
Y=B
So here only B literal is Present and A,C,D are not
present.

Since given function in SOP form 184. f(A,B,C,D) = π(0, 1, 4, 5, 8, 9, 12, 13) the
Hence, 1 - high simplified expression in POS.
0 - low (a) f = A+B+D (b) f = A+D
F = XY + XY (c) f = C (d) f = A+B
F=B BEL-2015
179. If A' + AB = 0, find the values of A and B. Ans. (c) :
(a) A = 1 and B = 1 (b) A = 1 and B = 0
(c) A = 0 and B = 1 (d) A = 0 and B = 0
UPPCL AE-05.11.2019
Ans. (b) : F = A '+ AB = 0
If A =1 and B= 0
Then, F = 0 + 1× 0 = 0
F = 0+0⇒ F =0 F=C
180. There are 4 variables in the Boolean function 185. AB + AB, write the simplified expression
and the value of the function is 1. Find the (a) A (b) AB
number of cells in the K-Map which will
contain a 1 when SOP expression is used. (c) B (d) AB
BEL-2015
(a) 12 (b) 0 Ans. (c) : AB + AB
(c) 16 (d) 14 = B (A + A)
UPPCL AE-05.11.2019
Ans. (c) : For 4 variable- =B (Q A + A = 1)
No. of SOP =24 =16
186. Simplify the following Boolean expression
181. There are 3 variables in the Boolean function
and the value of the function is 0. Find the Y = AB + BC + AC
number of cells in the K-Map, which will (a) A + BC (b) AB + BC
contain a 0 when SOP expression is used.
(a) 8 (b) 2 (c) A + BC (d) A + BC
(c) 4 (d) 0 SAIL- 2014
UPPCL AE-05.11.2019 Ans. (b) : Y = AB + BC + AC
Ans. (a) : For n variable function, 2n will be SOP and
POS form.
When n= 3
Number of SOP form = 23
=8
182. The number of distinct Boolean expressions of
four variables is− Y = BC + AB
(a) 1024 (b) 65536 187. Simplify the following Boolean expression
(c) 16 (d) 256
RRB JE-01.09.2019, 3:00 PM – 5:00 PM ( )
Y = A.B + A.B + A.B
BSNL(JTO)-2002
Ans. (b) : We know (a) ( A + B)( A + B ) ( A + B)
n
n distinct Boolean expression 2 2 (b) AB + AB + BA
4
= 22 (n = 4) (c) AB
= 216 (d) AB
= 65536 SAIL- 2014
183. Which of the following types is best suited to
represent the logical values? Ans. (c) : A.B + A.B + AB
(a) Boolean (b) Character = AB.AB.AB
(c) Integer (d) Double
RRB JE-01.09.2019, 3:00 PM – 5:00 PM = ( A + B )( A + B ) .( A + B )
Ans. (a) : Boolean is the best suited to represent the = ( A + AB + BA ) ( A + B )
logical value.
Boolean algebra is mostly used in computer science. It = A (1 + B + B ) ( A + B )
is a data type that has one of the two possible value = A ( A + B)
which represent the two truth values of logic and
Boolean algebra. = AB

188. Find the expression for 193. Which of the following statement is not
Y = ∑ m ( 0, 2, 3,7,14 ) + d (1,6,9,13 ) correct?
(a) X + X Y = X
(a) AB + AC + CD
(b) X.( X + Y) = XY
(b) AB + AC + ACD + BCD (c) X + X Y = X
(c) AB + AC + BCD (d) ZX + Z X Y = ZX + ZY
(d) AB + AC RRB SSE 02.09.2015, Shift-I
SAIL- 2014 Ans. (a) :
Ans. (c) : ( )
(a) X + XY = X + X ( X + Y ) = X + Y
(b) X ( X + Y ) = XX + XY = XY
(c) X + XY = X (1 + Y ) = X
(d) ZX + ZXY = Z  X + XY  = Z ( X + X ) ( X + Y )
= ZX + ZY
194. The operation x ⊕ y represents
Y = AB + CA + BCD (a) x – y (b) xy + xy
189. Find number of redundancy terms in the (c) xy + x y (d) x − y
following expression
IES - 1991
Y = AB + BC + A
(a) 8 (b) 1 Ans. (c) : X⊕ Y = X Y +X Y ( from XOR operation)
(c) 2 (d) 4 = XY+XY
SAIL- 2014
Ans. (c) : 195. Considering X and Y as binary variables, the
equivalent Boolean expression for Y(X + Y) is
(a) X (b) Y
(c) XY (d) X + Y
Ans. (b) : Y (X+Y)
From the K-map the common pair is redundancy term, = YX + YY = YX + Y
So, here Redundancy term is 2. = Y (X+1)
190. In Boolean Algebra, A (A + B') is equivalent to: = Y
(a) 0 (b) 1 196. In Boolean Algebra, A + AA' is equivalent to
(c) A (d) B (a) 0 (b) 1
RRB SSE 03.09.2015 Shift-II (c) A (d) A
Ans. (c) : A ( A + B )
Ans. (c) : A+AA' = A (Q AA' = 0)
= A.A + AB 197. Minterms corresponding to decimal number 15
= A (1 + B ) is
(a) ABCD (b) ABCD
=A
191. Considering X and Y as binary variables, the (c) A + B + C + D (d) A + B + C + D
equivalent Boolean expression of (X.Y)'is TRB Poly. Lect. -2012
(a) X'+Y (b) X+Y' Ans. (a) : For (15)10 → (1111)2
(c) X'+Y' (d) X'.Y' So, minterm = ABCD
RRB SSE 01.09.2015, Shift-II 198. F = v + vw + vwx + vwxy + vwx yz, where
Ans. (c) : (X.Y)' = X' + Y' from demorgan's theorem minimized Boolean function F is
192. Considering X and Y as binary variables, the (a) vwxyz (b) v+w+x+y+z
equivalent Boolean expression for X(X+Y) is (c) 1 (d) 0
(a) X (b) Y LMRC AM (S&T)-13.05.2018
(c) XY (d) X+Y
Ans. (b) : F = v + vw + vwx + vwx(y + yz)
RRB SSE 02.09.2015, Shift-I {A + AB = A + B}
Ans. (a) : X (X+Y) F = v + wv + vwx + vwx ( y + z )
= X.X. + XY
= X+XY F = v + vw + v w {x + x(y + z)}
= X (1+Y) F = v + vw + vw { x + y + z}
=X
F = v + v {w + w ( x + y + z )} Ans. (b) : Output
EX− NOR
F = v + v {w + x + y + z}
x y Output
F= v+w +x+y+z
0 0 1
199. The minimized form of the Boolean expression
F(A, B, C) = ∏(0, 2, 3) is 0 1 0
(a) A + BC (b) A + BC 1 0 0
(c) AC + B (d) ABC + AB 1 1 1
BSNL(JTO)-2009 p = x y z + xyz + xyz + xyz
Ans. (a) : F (A, B, C) = π (0, 2, 3) This output Boolean function behave like as an EX-
F ( A,B,C ) = ∑ m (1, 4,5,6,7 ) NOR gate.
p = x ⊙ y⊙z
or p = x ⊕ y ⊕ z
203. The complement of the Boolean expression
F = ( X + Y + Z )( X + Z ) ( X + Y )
Y = A + BC (a) XYZ+XZ+YZ (b) XYZ+XZ+XY
200. Which one of the following Boolean expressions (c) XYZ+XZ+YZ (d) XYZ+XY
is NOT correct ? DRDO-2008
(a) x + y = x y (b) x + y = x y Ans. (b) : F = ( X + Y + Z )( X + Z ) ( X + Y )
(c) x + y = x + y (d) x + y = xy
F = ( X + Y + Z )( X + Z ) ( X + Y )
BSNL(JTO)-2009
Ans. (c) (a) x + y = x.y = ( X + Y + Z) + ( X + Z) + ( X + Y )
(b) x + y = x.y = XYZ + XZ + X.Y
204. The Boolean function F(A, B, C, D) =Σ(0, 6, 8,
(c) x + y = x.y ≠ x + y 13, 14) with don't care conditions d(A, B, C, D)
(d) x + y = x.y = Σ(2, 4, 10) can be simplified to
201. A Boolean function can be expressed (a) F = BD + CD + ABC
(a) as sum of maxterms or product of minterms (b) F = BD + CD + ABCD
(b) as product of maxterms or sum of minterms
(c) partly as product of maxterms and partly as (c) F = ABD + CD + ABC
sum of minterms (d) F = BD + CD + ABCD
(d) partly as sum of maxterms and partly of DRDO-2008
minterms Ans. (b) : f (A,B,C, D) = ∑ ( 0,6,8,13,14 )
BSNL(JTO)-2009
Ans. (b) : A Boolean function can be expressed as Don't care condition d ( A, B,C, D ) = ∑ ( 2,4,10 )
product of maxterms or sum of minterms.
202. For the truth table given in figure, the
minimized Boolean expression is
F = BD + CD + ABCD
205. In case a problem has no don't care states
which of the following is a correct statement?
(a) The information in a truth table is not
sufficient to complete a Karnaugh map
(b) The information in a Karnaugh map is not
(a) p=x yz+x yz+x yz+x yz sufficient to complete a truth table
(b) p = x⊕y⊕z (c) The information in a truth table is sufficient
to complete a Karnaugh map
(c) p = x( y ⊕ z ) + x ( y ⊕ z )
(d) Truth table has no relationship with its
(d) p = x ⊕ yz Karnaugh map
BSNL(JTO)-2009 BSNL(JTO)-2002
Ans. (c) : Don't care (x) condition in K maps Ans. (d) :
The useful concepts in simplifying the output
expression using K-map is the concept of "Don't care".
The "Don't care" condition allow us to replace the
empty cell of a K-map to form a grouping of the
variable which is larger than that of forming group
without don't care while forming group of cells, we can
consider a Don't care cell as 1 or 0, we can also ignore
that cell. Therefore the don't care, condition can help
form a larger group or cell.
206. The function f(A,B) = ∏ M (0,1,2) represents
(a) NAND gate (b) NOR gate
(c) AND gate (d) OR gate,
UPPCL AE-16.11.2013 Y = AB + AC + ABC
Ans. (c) : f(A ,B) = ∏ M (0, 1, 2) = 210. The expression for the truth table given below
By K-map in POS form is given by:
f = A.B AND Gate
207. ( )
A B+C+D after using distribution law
expression is _____.
(a) AB + AC + AD (b) ( A + B) ( C + D )
(
(c) B A + C + D ) (d) None
NPCIL-2015
Ans. (a) : After using distribution law expression will
be ⇒ A ( B + C + D ) (a) AB' C +ABC'
(b) (A+B+C') (A'+B'+C')
⇒ AB + AC + AD (c) A'B'C+ABC
208. How many cells will be there in the K-Map to (d) (A+B'+C') (A'+B'+C')
solve in a 4 variable Boolean expression using DFCCIL Executive (S&T) 11.11.2018, 4:30 to 6:30PM
K-Map? Ans. (b) : There are 3-variable quantities in the given
(a) 64 (b) 16 expression. Here 8-block k-map will be required.
(c) 24 (d) 32 F (A, B, C) = π (1, 7)
UPPCL AE-05.11.2019
Ans. (b) : For n no. of variable –
No. of cells in K-map = 2n.
When n = 4, no. of cells = 24 =16
209. Figure shows a section of a Programming Logic
Device (PLD).
(
POS form = A + B + C ) ( A + B + C)
211. The number of essential prime implicates for
the function
Y = A'B'C'D + A'BCD' + AB'C'D + ABC'D'
is given by –
(a) 1 (b) 2
(c) 3 (d) 4
Ans. (c) : In the given function there are 4-variable then
The Boolean expression implemented in the with the help of k-map.
PLD is : Prime Implicates:- A group of square or rectangle
(a) AC + AB + ABC (b) AC + AB + ABC made up of bunch of adjacent mintems which is allowed
(c) AB + AC + ABC (d) AB + AC + ABC by definition of k-map are called prime implicants (PI)
DRDO-2009 i.e. all possible groups formed in k-map.

Ans. (a) : De Morgan's theorem
First- A.B.C + ........... + B = A + B + C + ...... + b +
Second- A + B + C + ............ + b = A.B.C..........b
217. Consensus theorem is
(a) A'B+A'C+BC=A'B+A'C
(b) AB+A'C'+BC=AB'+A'C
(c) AB+A'C+BC=AB+A'C
(d) AB+A'C'+BC=A'B'+A'C
Ans. (c) : Consensus theorem
Hence, the required number of essential prime
AB + AC + BC = AB + AC
Implicants = 3.
212. The Boolean function AB+AC is equivalent to 218. Which type of Boolean algebra law do the
_____. following laws belong to?
(a) AB + AC + BC Law 1 : A + A.B = A
(b) A'B'C' + ABC' + A'BC Law 2 : A (A + B) = A
(c) ABC + A'BC + B'C' (a) Associate laws
(d) ABC + ABC' + AB'C (b) Double negation laws
DFCCIL Executive (S&T) 11.11.2018, 4:30 to 6:30PM (c) Distributive laws
Ans. (d) : F = AB +AC (d) Absorption laws
Q C + C = 1  Ans. (d) : (i) A + A.B = A
  L.H.S.
 B + B = 1 A + A.B.
( )
= AB C + C + AC(B + B) A (1 + B) – By absorption law
= ABC + ABC + ABC + ABC A.1
=A
= ABC + ABC + ABC So, it's an Absorption law.
213. Find out the equivalent of AB+A'+B'. (ii) A (A + B) = A
(a) B (b) 1 L.H.S
(c) AB (d) A A (A + B)
DFCCIL Executive S&T-17.04.2016, Shift-II A.A + AB
Ans. (b) : F = AB+A'+B' A + AB
F = A '+ AB + B' ( x '+ x y = x '+ y ) A (1 + B)
A.1 = A
= A '+ B + B' (Q x + x ' = 1) So, A (A + B) = A is also an Absorption Law.
= A '+ 1 = 1 219. The theorem to which the given two powerful
214. Simplify the expression AB + A + AB : laws in Boolean algebra belong to, is:
(a) = 1 (b) = 0 Law 1 : A + B = AB
(c) = A (d) = A Law 2 : AB = A + B
TNTRB AE– 2017 (a) De Morgan's theorem
Ans. (b) : AB + A + AB (b) Transposition theorem
(c) Consensus theorem
= AB.A.AB (d) Included factor theorem
= AB.A.AB
=0 Ans. (a) De Morgan's first theorem- According to De
Morgan's first theorem A NOR gate is equivalent to a
215. Which of the following Boolean expression is
bubbled AND Gate
incorrect?
(a) A + AB = A + B A + B = A.B
(b) A+AB= B De Morgan's second theorem - According to De
(c) (A+B) (A+C) = A+BC Morgan's second theorem, a NAND gate is equivalent
(d) (A+B’) (A+B) = A to a bubbled OR gate
TNTRB AE– 2017 AB = A + B
Ans. (b) : A + AB 220. Which of the following statements about the K-
A (1+ B) maps is INCORRECT?
=A (a) In K-maps, don't care terms are used only if
216. De Morgan's Theorem is they help in reducing the expression.
(a) (AB)'=A'+B' (b) (AB)'=A'+B Otherwise, they need not be considered
(c) (AB)'=A+B' (d) (AB)'=A+B (b) A two-variable K-map expression can have 4
UPRVUNL AE– 11.06.2014 possible combinations of the input variables
(c) The binary number designations of the rows 224. The expression A ⊕ B is equal to _______.
and columns of the K-map are in Gray code
(a) A ⊕ B (b) A ⊕ B
(d) The five-variable map may contain 2-squares,
4-squares, 8-squares, or other combinations (c) A + B (d) None of these
involving four blocks of K-map having 16 KVS TGT (WE)- 2016
squares each Ans. (b) : A ⊕ B = AB + AB = AB . AB
( ) ( )( )
Ans. (d) : Karnaugh Map (K-map) is a method of
simplifying Boolean algebra expressions.
( )( )
= A + B . A + B = AA + AB + AB + BB
• The karnaugh map reduces the need for extensive A ⊕ B = AB + AB (Ex - NOR logic)
calculations.
• Number of cell in 2 Variable K-map = 22 = 4 and A ⊕ B = AB + AB = AB + AB (Ex - NOR logic)
3
3-Variable K-map = 2 = 8 225. Simplified expression of
4 Variable K-map = 24 = 16 Y = (A + B)(A + AB)C + A(B + C) + AB + ABC
• The "Don’t care" condition allow us to replace the is
empty of a K-map and form a grouping of the (a) Y = C(A + B) + A(B + C)
variable which is larger than that of original group.
(b) Y = C(A + B) + A(B + C)
While forming group of cells we can consider a
don't care cell as 1 or 0 or we can also ignore that (c) Y = A(B + C) + B(A + C)
cell. (d) Y = C(A + B) + B(A + C)
221. How many variables do 16 squares eliminate? KVS TGT (WE)- 2014
(a) 7 (b) 4 (a) : Simplified expression can be given as -
(c) 1 (d) 11
Y = (A + B)(A + AB)C + A(B + C) + AB + ABC
Ans. (b) : = (A + B) ( A + A ) (A + B)  C + A(B + C) + B(A + AC)
= (A + B) (A + B C + AB + AC + B (A + A)(A + C) 

= AC + ABC + ABC + AB + AC + B(A + C)
= AC + ABC + ABC + AB + AC + AB + BC
= AC + BC + AB + AC
So, 16 squares eliminate 4 variables. = C(A + B) + A(B + C)
222. If A + B = A + C and AB = AC, then which of 226. The value of A + B is :
the following is true? (a) A.B (b) A.B
(a) B = C (b) B + C = 0
(c) B = 2C (d) B = A + C (c) A. B (d) A . B
KVS TGT (WE)- 2016 KVS TGT (WE)- 2018
Ans. (a) : Given that - Ans. (b) : According to Demorgan's theorem -
A+B = A+C ⇒ B = C  x + y = x.y 
And, AB = AC (
A + B = A.B )  
 xy = x + y 
Q B=C
223. The expression A + AC + ACD + ACDE + ......
227. { }
A + A ⋅ B can also be represented as:
is equal to _______. (a) A (b) B
(a) A (b) A + C (c) A + B (d) A + B
(c) A + D (d) A + E KVS TGT (WE)- 2018
KVS TGT (WE)- 2016 Ans. (c) : Given that,
Ans. (a) : Given that -
= A + AC + ACD + ACDE
A + A⋅B { }
= A[1 + C + CD + CDE] From distributive law
= A[1 + CD + CDE] = A + A.B { }
= A [1 + CD (1+E)]
= A [1 + CD] Q{(1 + x ) = 1} Annulment's law
( )
= A + A . ( A + B) , Q A + A = 1
=A = ( A + B)

4. The following function was to be realized using
(iii) Logic Gates 2-input AND Gate and OR Gate. However
during the fabrication all 2-input AND were
1. F = AB + CD + E will be implemented with mistakenly substituted by 2-input NAND gates.
how many minimum number of NAND gates? (A.B).C + (A'.C).D + (B. C).D + A.D Where (')
(a) Three (b) Four is the compliment of the variable.
(c) Five (d) Six What is the function finally realized?
UPPSC Poly. Tech. Lect.-22.03.2022, Paper -I (a) A'+B'+C+D' (b) 0
Ans. (b) : F = AB + CD +E (c) A'+B+C'+D' (d) 1
F = AB + CD + E RPSC ACF & FRO 23.02.2021
F = AB.CD.E Ans. (c) : Y = ( A.B ) .C + ( AC ) D + ( B.C ) .D + AD

Q 2 input AND gate mistakenly substituted by 2 input
NAND gate.
( ) ( ) ( ) ( )
Y = A.B C + A.C D + BC D + A.D
hence 4 NAND gate required Y = A.B + C + AC + D + BC + D + A + D

2. The input to a logic gate is A=1100 and = AB + C + AC + D + BC + D + A + D
B=1010. What will be the output, if the logic = AB + AC + B.C + A + D + C
gate is NAND gate? = AB + BC + A (1 + C ) + D + C
(a) 0110 (b) 1101
(c) 111 (d) 1011 = A + AB + BC + D + C
UPRVUNL AE -19.07.2021, Shift-II = A + B + BC + D + C
Ans. (c) : Y = A+ B+ D+C {Q1 + C = 1}
5. Which of the following are universal gates?
1. AND 2. NAND
3. OR 4. NOR
5. NOT
(a) 1, 2, 3, 4 and 5 (b) 1, 3 and 4 only
(c) 2, 3 and 5 only (d) 2 and 4 only
NLC GET - 24.11.2020
Nagaland PSC (Degree) - 2018, Paper - II
OPSC Poly. Lect. (Instrumentation) - 2018, Paper-I
KVS TGT (WE)-2018
Nagaland PSC CTSE (Degree) - 2017, Paper-II
Output = 0111 So, option is c KVS TGT (WE)- 2017
RRB SSE - 21.12.2014 (Green)
3. Consider the logic circuit shown in figure SAIL - 2014
below. The function f1, f2 and f (in canonical IES-2011, 2009
sum of products form in decimal notation) are Ans. (d) : Universal gates are -
NAND gate and NOR gate.
• All gates are implement by NAND gate and NOR
gate.
f1 = (w,x, y, z) = ∑(8, 9, 10)
f2 = (w, x, y, z) = ∑(7, 8, 12,13, 14, 15)
f = (w, x, y, z) = ∑(8, 9)
The function f3 is Basic gates - AND, OR, NOT
(a) ∑ (8) (b) ∑ (9) Universal gates -NAND, NOR
(c) ∑ (1, 8, 9) (d) ∑ (8. 10. 12) Special purpose gates - Ex-OR and Ex-NOR
RPSC ACF & FRO 23.02.2021 6. A GATE, which cannot be used as an inverter
Ans. (b) : is _______.
(a) NOR (b) AND
f x = f1.f 2 (AND gate) (c) NAND (d) X-NOR
= ∑ ( 8,9,10 ).∑ ( 7,8,12,13,14,15 ) KVS TGT (WE)- 2016
f x = ∑ (8) Ans. (b) : AND gate cannot be used as an inverter.
NOT gate or inverter is a logic gate. Which
f = f x + f3 (OR gate) complements it's input.
∑ (8,9 ) = ∑ (8) + f3
f3 = ∑ ( 9 )

7. Obtain the logical function of the following 10. The function (A ⊕ B) is to be realized using
circuit. only 2-input NAND gates. The minimum
number of 2-input NAND gates required for
such a realization is
(a) 3 (b) 4
(c) 5 (d) 6
Gate - 2016, IES-2012,2011,2004
ISRO Scientist Engg. - 2006
(a) Y = A NAND B (b) Y = A OR B Ans. (b) :
(c) Y = A XOR B (d) Y = A XNOR B
NLC GET -24.11.2020
Ans. (c) :
Y = A.A.B.B.A.B
=  A.A.B  +  B.A.B 
   
8. The Boolean function Y = AB + CD is to be
realized using only 2-input NAND gates. The
( ) ( )
= A.A.B + B.A.B
minimum number of gates required is = A ( A + B) + B ( A + B)
(a) 2 (b) 3
(c) 4 (d) 5 = AA + AB + AB + B.B
Nagaland PSC (Degree) 2018, Paper-II Y = A.B + A.B = A ⊕ B
Mizoram PSC IOLM -2018, Paper II The minimum number of gate required to impliment
Nagaland PSC (CTSE) Diploma-2017, Paper II A⊕B is "4"
KVS TGT (WE)- 2017
Logic Number of NAND Number of NOR
UTVNL AE-2016, GATE-2007
Gate Gate required Gate required
Ans. (b) : Y = AB + CD NOT 1 1
Y = AB + CD AND 2 3
OR 3 2
Y = AB.CD EX-OR 4 5
EX-NOR 5 4
11. Number of NAND gates required for EX-NOR
implementation
(a) 4 (b) 6
3, 2-input NAND gates. (c) 5 (d) 8
9. The output of a logic gate is 1 when all its input TSP S C M a na g e r ( Eng g . ) - 20 15, RPSC Lect. - 2011
are at logic 0. Then the gate is either Ans. (c) :
(a) A NAND or an EX-OR Gate
(b) A NOR or an EX-NOR Gate
(c) An OR or an EX-NOR Gate
(d) An AND or an EX-OR Gate
TANGEDCO- 2015
MPPSC Forest Service Exam. -2014 Q = A.B.A.B
IES - 2003, 1995, Gate - 1994
Ans. (b) : = A.B + A.B
= AB + AB
Y =A B
Hence, 5 NAND gates requires for EX-NOR
implementation.
12. For the logic circuit shown in below figure, the
required input condition (A,B,C) to make the
output Y = 1 is

(a) 1, 0, 1 (b) 0, 0, 1 1 1
(c) 1, 1, 1 (d) 0, 1, 1 0 0 0 0
Input
(e) 0, 1, 0 1 1
CGPSC SO 14.02.2016
IES-2004, (GATE-2000) 0 0 0 0
1 1
A B C
Ans. (d) : According to option Input   0 0 0 0
0 1 1 
15. The output equivalent circuit of following
circuit is
for Y = 1 (A = 0; B = 1; C = 1)
13. Which gate corresponds to the action of (a) INVERTER (b) AND
parallel switches ? (c) OR (d) NOR
(a) AND gate (b) OR gate ISRO Scientist Engg.-2016
(c) NAND gate (d) NOR gate Ans.(c):
RRB JE - 31.08.2019, 10:00 AM to 12:00 PM
Ans. (b) : OR gate corresponds to the action of parallel
switches
Y = A.B
Y =A+B
Y = A + B = OR Gate
Y=A+B 16. Which of the following statement is correct?
(a) NAND and NOR functions are commutative
and associative
(b) Both NAND and NOR functions are neither
• AND Gate corresponds to the action of series
switches. commutative nor associative
(c) NAND and NOR functions are associative
Y = AB but not commutative
(d) NAND and NOR functions are commutative
but not associative
Ans. (d) : NAND and NOR function are commutative
14. If the input signals (A & B) and output signals but not associative.
are as shown in the figure then the circuit NAND function –
element is Checking NAND gate is commutative-
A.B according to commutative
A.B = B.A
From demorgan's law -
A.B = A + B
A + B = A.B
(a) AND Gate (b) OR Gate Both LHS and RHS will be equal
(c) NOR Gate (d) XOR Gate So NAND gate commutative
ISRO Scientist Engg.-2016 Checking NAND gate associative-
Ans. (c): NOR gate A.B.C should be equal be equal to A.B.C
Input Output Let if A= 1, B=1 and C = 0
A B Y = A+B L.H.S = A.B.C = 1.1.0
0 0 1 = 0.0 = 1
0 1 0
R.H.S. = 1.1.0 = 1.1 = 0
1 0 0 L.H.S. ≠ R.H.S
1 1 0 So, NAND gate is not associate

NOR function- 18. In the figure shown, the output Y is required to
Checking NOR gate is a commutative- be Y = AB + CD . The gates G1 and G2 must
L.H.S = A + B be, respectively.
From De Morgen’s law
A + B = A.B
Now apply this to RHS then we get
B+A = B+A
LHS = RHS
NOR is also commutative (a) NOR, OR (b) OR, NAND
Now checking NOR gate associate property- (c) NAND, OR (d) AND, NAND
A + B + C should be equal to A + B + C
Gate - 2015, Set-II
Let if A = 1, B = 1 and C = 0
Ans. (a) :
LHS = A + B + C
= 1+1+ 0
= 0 + 0 =1
RHS = 1 + 1 + 0
= 1 + 0 = 0 LHS ≠ RHS
19. If c = 0 is the given logic circuit, find y.
So, NOR gate is not associate.
17. A bulb in a staircase has two switches, one
switch being at the ground floor and the other
one at the first floor. The bulb can be turned
ON and also can be turned OFF by any one of
the switches irrespective of the state of the (a) A'B + AB' (b) A + B
other switch. The logic of switching of the bulb (c) A – B (d) AB
resembles Nagaland PSC (CTSE) Diploma-2017, Paper II
(a) an AND gate (b) an OR gate Nagaland PSC CTSE (Degree)-2017, Paper-II
(c) an XOR gate (d) a NAND gate GATE-2014
Nagaland PSC (Degree) - 2018, Paper II Ans. (a) :
Mizoram PSC IOLM - 2018, Paper II
Nagaland PSC CPSE (Degree) - 2017, Paper II
Gate - 2013
Ans. (c) : Let the switch at the one of the floor be
labeled 'A' and the switch on the other floor be labeled
as 'B'.
The truth table for the required response is as shown :-
Switch A Switch B Y Y = A + B + AB
0(Up) 0(Up) 0 ( OFF )
= (A + B).(AB)
0(Up) 1( Down ) 1( ON )
1(Down) 0(Up) 1( ON ) (
= ( A + B) . A + B )
1(Down) 1( Down ) 0 ( OFF ) = AB + BA
20. For the gate in the given figure the output will
be………
Y = A⊕B
This is the output expression for an XOR gate. In the
staircase wiring, high output is obtained when both the
inputs are different.
(a) 0 (b) 1
(c) A (d) A
GATE - 1997
Ans. (d) : The given circuit is Ex-NOR Gate
Y = AB + AB
Y = A0 + A.0
Y=A

21. The logic gate circuit shown in the figure
realizes the function Y = AB + A + B( ) ( )
= A + B + (AB)
= A(1 + B) + B
= A+B
(a) XNOR (b) XOR = AB
(c) Half Adder (d) Full Adder 24. Tick the True statement
DMRC AM S&T-2020 (a) OR and NOT gates are necessary and
Nagaland PSC (CTSE) Diploma-2017, Paper II sufficient for realization of any logic function
Ans. (b) : (b) AND and NOT gates are necessary and
sufficient for realization of any logic function
(c) NOR gates are sufficient to realize any logic
function
(d) NAND gates are not sufficient to realize any
function
TNPSC AE - 2018
F1 = X.XY Ans. (c) : NAND and NOR gates are universal gate.
Hence these two gates (NAND or NOR) are sufficient
F2 = Y.XY to realize any Boolean expression.
25. Odd parity generator uses ............. logic
F = X.XY.Y.XY (a) XNOR (b) XOR
F = X.XY + Y.XY (c) Sequential (d) OR
F = X.XY + Y.XY Ans. (b) : Odd parity generator uses XOR logic.
F = X (X + Y) + Y(X + Y) • A parity bit is an extra bit that is added to a data word
and can be either odd or even parity.
F = XX + XY + YX + YY
26. Minimum number of 2-input NAND gates that
F = XY + YX will be required to implement the function:
F= X⊕Y Y = AB + CD + EF is
Hence given circuit is a Ex-OR gate. (a) 4 (b) 5
22. An OR gate has 4 inputs. One input is high and (c) 6 (d) 7
the other three are low. The output ISRO Scientist Engg.-2008
(a) is low Ans. (c) :
(b) is high
(c) is alternately high and low
(d) may be high or low depending on relative
magnitude of inputs
Ans. (b) : For OR Gate
Youtput = A + B + C + D
when A = 1, B = C = D = 0
Youtput = 1 High. So, the required 6 2-input NAND gates to implement
the given function.
23. The output Y is
27. The output Y of a NOR gate for input A and B
is
(a) A + B (b) A + B
(c) A + B (d) AB
Ans. (b) :
(a) Y = AB (b) Y = AB
(c) Y = AB (d) Y = AB
TNPSC AE - 2018
28. An EX-OR gate can be converted into an
Ans. (a) :
inverter by
(a) Permanently connecting one input to 1
(b) Permanently connecting both input to 1
(c) Permanently connecting one input to 0
(d) Permanently connecting both inputs 0

Ans. (a) : For EX-OR gate 33. The POS form of expression is suitable for
Y = AB + AB circuit using
(a) NAND (b) NOR
(c) XOR (d) AND
Ans. (b) : POS form of a Boolean expression is suitable
for circuit implementation using NOR Gate. NOR Gate
is the type of Universal Gate.
34. Which of the following is a single input logic
gate
An inverter using EX-OR Gate by connecting one of the (a) NAND (b) INVERTER
inputs to logic 1. (c) AND (d) OR
29. In general, the logic gates whose all output MPPSC Forest Service Exam.-2014
entries are 0 except for one entry Ans. (b) : Inverter is work on single input and output is
(a) AND or NOR (b) OR or AND invert of input.
(c) NAND or NOR (d) EX-OR or OR
TNPSC AE-2013 Inverter is single input logic gate.
Ans. (a) : 35. The following is equivalent to
(a) OR gate (b) NAND gate

(c) EX-OR gate (d) None of these
Ans. (b) :
30. The output is "1" for like inputs and "0" for
unlike inputs. This statement is representative
of which logic gate? If input A, B and output Y = A.B
(a) AND (b) OR A.B is output of NAND gate.
(c) EX-NOR (d) NAND 36. For a NAND gate, when one or more inputs are
TNPSC AE-2013 low then the output will be
Ans. (c) For EX-NOR Gate (a) Low
(b) High
(c) Alternately high and low
(d) High or low depending on relative magnitude
of inputs
Ans. (b) : NAND Gate truth table -
Input Output
31. Which of the following is the universal logic
gate A B Y
(a) NAND (b) OR 0 0 1
(c) AND (d) INVERTER 0 1 1
MPPSC Forest Service Exam.-2014 1 0 1
Ans. (a) : A universal gate is a logic gate which can
1 1 0
implement any Boolean function without the need to
use any other type of logic gate. The NOR gate and 37. Which one of the following is equivalent to x' ?
NAND gate are universal gate. (a) x X - OR 0 (b) 1 NOR x
32. De- Morgan's theorem says that (c) x AND x (d) x X-NOR 0
(a) An AND gate is equivalent to a bubbled RPSC LECTURER-10.01.2016
NAND gate Ans. (d) : X-NOR = A B + A B put A = X and B = 0
(b) A NAND gate is equivalent to a bubbled OR Then,
gate
(c) NAND gate is equivalent to a AND gate = x.0 + x. 0
(d) NAND gate is always complimentary to an = 0 + x.1
AND gate = x
38. Five panelists are required to elect a sixth
Ans. (b) : De- Morgan theorem says that member to the panel. If any of the panelists
A.B = A + B votes against a member, the member is
A.B is output of the NAND gate disqualified. What would be the appropriate
electronic circuit to be used in the electronic
A + B is output of the bubbled OR gate voting machine to implement the above rule?
(a) XOR (b) XNOR Truth Table
(c) OR (d) AND
Ans. (d) : When one panelists votes against any one
member, the member is disqualified. So, we can say one
input is low, output will be low. Hence this
implementation occurs in AND gate.
39. Consider the statements below:
A. If the output waveform from an OR gate is
the same as the waveform at one of its
inputs, the other input is being held
permanently LOW.
B. If the output waveform from an OR gate is
always HIGH, one of its input is being held
permanently HIGH
The statement, which is always true, is
(a) Both A and B
(b) Only A
(c) Only B
Ans. (a) : Both statement is correct. The output
waveform from an OR gate is the same as wave form at
one of its input, the other input is being held = AB+AC+BC
permanently low because OR gate provide the output
when only one input is high. 42. A circuit outputs a digit in the form of 4 bits. 0
40. An OR gate may be imagined as is represented by 0000, 1 is represented by
(a) switches connected in series 0001, ......, 9 by 1001. A combinational circuit is
(b) switches connected in parallel to be designed which takes 4 bits as input and
(c) MOS transistors connected in series output as 1, if the digit is ≥ 5, and 0 otherwise.
(d) None of these If only AND, OR and NOT gates may be used,
RPSC Vice Principal ITI-2016 what is the minimum number of gates
Ans. (b) : required?
(a) 4 (b) 3
(c) 2 (d) 1
IES-2017
Ans. (b)
IN P U T O UTPUT
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
An OR gate may be imagined as switches connected in 0 1 1 0 1
parallel. 0 1 1 1 1
1 0 0 0 1
41. An electric power generating station supplies 1 0 0 1 1
power to three loads A, B and C. Only a single
generator is required when any one load is
switched on. When more than one load is on,
an auxiliary generator must be started. The
Boolean equation for the control of switching of
the auxiliary generator will be
(a) AA + BB + CC (b) ABC + BCA + CAB
(c) AB + AC (d) AB + AC + BC Y = A + BC + BD
IES-2019 = A + B.(C + D)
Ans. (d) : According to the question A, B, C are three = OR + AND + OR
loads, when more than one load is on the auxiliary Hence, minimum number of gate required to implement
generator must be started. the output expression = 3

43. The output of a NOR gate is :
(a) high if all of its inputs are high
(b) low if all of its inputs are low
(c) high if all of its inputs are low
(d) high if only one of its inputs is low
IES-2017
Ans. (c) : NOR Gate is a digital logic gate that What values are to be selected for I and J?
Implement logical Gate. (a) I = 0 and J = B (b) I = 1 and J = B
True table (c) I = B and J = 1 (d) I = B and J = 0
IES-2010, 2006
Ans. (b) :
Z= (A+I) ( A +J)
According to option
I=1,J=B
If all inputs are low then output is high. Z = (A+1) ( A + B)
44. The minimum number of gates required to Z = ( A + B)
realize the function AB + C (using NAND 47. Match List-I with List-II and select the correct
gates only) is answer using the code given below the lists
(a) 2 (b) 3 List-I List-II
(c) 4 (d) 6 A. AND gate 1. Boolean complementation
IES-2015 B. OR gate 2. Boolean addition
C. NOT gate 3. Boolean multiplication
Ans. (a) : Y = AB + C
Codes:
A B C
(a) 3 1 2
(b) 1 2 3
(c) 3 2 1
Y= (A.B).C (d) 1 3 2
=(AB)+ C IES-2010
45. Consider the following gate network Ans. (c) : AND Gate-
Which one of the following gates is redundant?

(a) Gate No. 1 (b) Gate No. 2 OR Gate-
(c) Gate No. 3 (d) Gate No. 4
IES-2011
Ans. (b) :
NOT Gate-
Input Output
The output of the circuit is
= w + wx + xyz A Y=A
= w (1 + x ) + xyz
0 1
1 0
= w + xyz
48.
Output of Gate No.2 xw can be removed.
Hence gate no.2 is reduntant.
46. The circuit shown below is to be used to
implement the function Z = f(A, B) = A + B
The values of I and J are
The output' X of the above logic circuit is: (a) 0 (b) 1
(a) AB + CD + EF (c) AB + AB (d) (A * B) *(A * B)
(b) AB + CD + EF IES-2008
(c) (A + B)(C + D)(E + F) GATE-1993
(d) (A + B)(C + D)(E + F) Ans. (b) :
IES-2010
Ans. (a) :
(
X = AB CD EF ) Let, A⊙ B = X X ⊙X = 1
= AB + CD + EF So,
= AB + CD + EF Y = (A⊙ B )⊙(A⊙ B ) = X⊙X
49. The Boolean expression for the output of the = X.X + X.X
below logic circuit is = X+X
=1
52. For the logic circuit given below, what is the
simplified Boolean function?
(a) Y = AB + AB + C (b) Y = A + AB + C
(c) Y = A ⊕ B + C (d) Y = AB + C
IES-2010
Ans. (a) :
(a) X = AB + C (b) X = BC + A
(c) X = AB + AC (d) X = AC + B
Y = ( A ⊕ B ) .C IES-2007
Ans. (b) :
= A⊕B+C
= AB + AB + C
= AB .AB + C
= ( A + B) ( A + B) + C
Y = AB + AB + C Now,
50. In NOR-NOR configuration, the minimum = (A+B). (B.C) + A
number of NOR gates needed to implement the = ABC + B.C + A
switching function X + XY + XYZ is: = ABC + BC + A
(a) 5 (b) 3 = BC (A + 1) + A = BC + A
(c) 2 (d) 0 53. The black box in the figure shown below
IES-2010 consists of a minimum complexity circuit that
uses only AND, OR and NOT gates. The
Ans. (d) : Y = X + X Y + X Y Z
function f(x,y,z) = 1 whenever x, y are different
= X + XY (1 + Z ) and 0 otherwise. In addition the 3 inputs x, y, z
= X + XY (1 + Z = 1) are never all the same value. Which one of the
following equations leads to the correct design
= X (1 + Y ) .(1) for the minimum complexity circuit?
= X.(1)
=X
So zero (0) NOR gate is required to implement the
switching function X + XY + XYZ . (a) x'y + xy' (b) x + y'z
51. The output of the circuit shown in the figure is (c) x'y'z' + xy'z (d) xy + y'z + z'
equal to IES-2007
Ans. (a) :

x y z f (x,y,z) X(P,Q,R) = π ( 0,5)
0 1 1 or 0 1
1 0 1 or 0 1 (
X = (P + Q + R ) P + Q + R )
• Additional since it is given that x,y,z are never all = PP + PQ + PR + PQ + QQ + QR + PR + QR + RR
the same value. = PR + PR + PQ + PQ + Q.Q + QR + QR
• The same value hence xyz = 000 and xyz =111
xyz + xyz + xy z + xyz = (P ⊕ R ) + Q(P + P +1+ R + R )
so, F(x,y,z) = xy(z + z) + xy(z + z) = ( P ⊕ R ) + Q (1)
= xy + xy = (P ⊕ R ) + Q
54. The Boolean expression Y(A, B, C) = A + BC is = XOR + OR
to be realized using 2-input gates of only one Hence the function can be realized using OR and XOR
type. What is the minimum number of gates Gate.
required for the realization?
(a) 1 (b) 2 57. What is the Boolean expression A⊕ B
(c) 3 (d) 4 or more equivalent to?
IES-2006 (a) AB + AB (b) AB + AB
Ans. (c) : Y= A + BC (c) B (d) A
Y = A + BC IES-2004
Ans. (b) : EX-OR Gate -
= A.BC
Y = A.BC
= A⊕B
= AB + AB
58. The output of a two level AND-OR gate
network is F. What is the output when all the
Hence, the minimum number of gates required are 3 for gates are replaced by NOR gates?
realization. Where FD is the dual function of F.
55. Which one of the following logical operations is (a) F (b) F
performed by the digital circuit shown below?
(c) FD (d) FD
IES-2004
Ans. (c) : Let us consider an example of AND-OR Gate
(a) NOR (b) NAND

(c) EX-OR (d) OR
IES-2006
Ans. (c) : F = ( WX + YZ ) ……………………(i)
Now we replace all the Gates with NOR gates then
Y = (A B ) + ( A B)
Y = A⊕B FD = W + X + Y + Z
Hence, EX-OR operation is performed by given digital
circuit. = W + X.Y + Z
56. The Boolean expression X (P,Q,R) = π (0 , 5) is = (W + X) (Y+Z)…………………….(ii)
D
to be realized using only two 2-input gates. From equation (i) and (ii) it is clear that F is dual of F.
Which are these gates? 59. How is inversion achieved using EX-OR gate?
(a) AND and OR (b) NAND and OR (a) Giving input signal to the two input lines of
(c) AND and XOR (d) OR and XOR the gate tied together.
IES-2006 (b) Giving input to one input line and logic zero
Ans. (d) : to the other line.
(c) Giving input to one input line and logic one to
the other line.
(d) Inversion cannot be achieved using EX-OR
gate
IES-2002

Ans. (c) : EX-OR gate A square wave is generated when a circuit output
alternates between 0 and 1 for the given circuit output
keeps changing from 0 to 1 and 1 to 0.
Y = A⊕B = AB + AB Hence, given circuit will generate a square wave.
Check when A = 1, B = X 62. Which one of the following figures represents
the coincidence logic?
(a)
then output Y = X
and when A = 0, B = X
wthen output Y = X (b)

Hence inversion using EX-OR gate is achieved by giving
input to one input line and logic one to the other line.
60. If the output of a logic gate is '1' when all its
inputs are at logic '0', the gate is either
(a) a NAND or NOR (c)
(b) an AND or an EX-NOR
(c) an OR or a NAND
(d) an EX-OR or an EX-NOR
IES-2001 (d)
Ans. (a) : NAND Gate-
IES-2000, 1996, 1993

Ans. (a) :
NOR Gate-
F = A B +A B = A ⊙ B
• EX-NOR logic is called as coincidence logic
F = A B +A B
• EX-NOR gate-
NAND and NOR Gate are called universal gates 63. Which one of the following circuits is the
because all gates are achieved by using NAND and minimized logic circuit for the circuit shown in
NOR gate . figure below?
61. The circuit shown in the given figure
(a) is an oscillating circuit and its output is a (a)

square wave
(b) is one whose output remains stable in '1' state
(c) is one whose output remains stable in '0' state (b)
(d) gives a single pulse of 3 times propagation
delay
IES-2001 (c)
Ans. (a) :
(d)
IES-2000

Ans. (b) F2 = X. Y
Hence,
Figure (I) and figure (II) entirely different
66. The given figure shows a NAND gate with
input waveforms A and B
F = A.B.C + C + A
= A+B+C+C+A (Q A + A = A )
F = A+B+C (Q C + C = C)
hence, boolean, F = A + B + C can be replaced by using
given logic circuit. The correct output waveform X of the gate is
(a)
(b)
64. The circuit shown in the given figure realizes
the function (c)
(d)
IES-1999
Ans. (d) :
(a) ( A + B + C )( DE ) (b) ( A + B + C)( DE )
(c) ( A + B + C)( DE ) (d) ( A + B + C)( DE )
IES-2000
Ans. (a) :
NAND Gate Truth table
F = A + B + C + (D + E)
= (A + B + C)(D + E)
= (A + B + C)(D.E)
from truth table it is clear that the correct waveform for
65. The logic operations of two combinational output X is option (d).
circuits given in Figure-I and Figure-II are 67. Y = f (A, B) = ΠM (0, 1, 2, 3) represents (M is
Maxterm)
(a) NOR gate
(b) NAND gate
(c) OR gate
(d) A situation where output is independent of input
IES-1999
(a) entirely different (b) identical
Ans. (d) : Y = f(A,B) = πM(0,1,2,3)
(c) complementary (d) dual
IES-2000
Ans. (a) :
Y = f(A, B) = 0
While output is always 0 i.e. it is independent of input
68. The circuit shown in fig. is equivalent to
F1 = (X + Y) + X
= (X+ Y ). X
= X. X + X Y (∴ X X =0)
=X Y (Y Y = 0 ) (a) (b)

(c) (d) Ans. (d) :
IES-1998
Ans. (d) : According to option
Y = (A+B) (C+D) ( A.B ) . ( C.D )
=
=
= A + B+C+ D
72. The circuit shown in the figure is functionally
69. The output Y of circuit shown in the figure is equivalent to
(a) (A + B) C + DE (b) AB + C + (D + E) (a) NOR gate (b) OR gate

(c) (A + B) C + D + E (d) (AB + C) DE (c) EX-OR Gate (d) NAND gate
IES-1998 IES-1997
Ans. (a) : Ans. (c) :
Y= (A + B).C + (D.E)
Y= (A+B).C+(D.E) Y = (A.B).(B.A)
70. The output X of the logic circuit shown in the
figure is Y= (A.B) + (B.A)
Y= (A.B) + (B.A) = A ⊕ B
Y=EX-OR Gate
73. A three-input NAND gate is to be used as an
(a) A + BC (b) BC inverter. Which one of the following measures
(c) AB (d) AB + C will achieve better results?
IES-1997 (a) The two inputs not used are kept open
(b) The two inputs not used are connected to
Ans. (c) : ground (0 level)
(c) The two inputs not used are connected to
logic (1 level)
(d) None of above
IES-1996
Ans. (c) :
= (A+ B ).(B+BC)
= (A+ B ).B(1+C) [Q1 + C = 1]
= (A+ B ).B ∴ F = X.YZ
= AB+B. B ∴ BB = 0 if Z = 0 then F = 1= Z (inverter)
= AB if Z = 1 then F = 0
Hence the given NAND gate works as inverter.
71. When two gates with open collector outputs are
tied together as shown in the figure, the output 74. The minimized logic circuit for the circuit
obtained will be shown in fig. is
(a) (b)
(a) A + B + C + D (b) A + B + C + D
(c) ( A + B)( C + D ) (d) A + B + C + D (c) (d)
IES-1997 IES-1996
Ans. (b) Ans. (a) :
F1= X + XYZ + Z
= X + X+Y+ Z+ Z Y= (A.B).C .(D.E)
= X + X +Y + Z+ Z
= X +Y+ Z = (A.B).C + D.E
From the option (b) = (A.B).C + (D.E)
= (A + B).C + (D.E)
77. Which one of the following sets of gates are
F2 = X.Y.Z best suited for parity checking and parity
= X+Y+Z generation?
Hence F1 = F2 (a) AND, OR, NOT gates
(b) X-OR, X-NOR gates
75. In the figure shown, X2X1X0 will be 1's (c) NAND gates
complement of A2A1A0 if (d) NOR gates
BEL - 2015
IES-1995
Ans. (b) : X- OR and X- NOR gate are used for parity
checking and parity generation.
78. The circuit shown in figure is equivalent to :
A 0 = A1 = A 2
(a) Y = 0 (b) Y = 1
(c) Y = A 0 = A1 = A 2 (d) Y = A0 = A1 = A2
IES-1996
Ans. (b) : (a)
(b)
A0⊕Y = X0 –––––(1)
A1⊕Y = X1 –––––(2) (c)
A2⊕Y = X2–––––(3)
According to question X0 = A 0 , X1 = A1 , X2 = A 2
A0⊕Y = A 0 –––––(4)
A1⊕Y = A1 –––––(5) (d)
A2⊕Y = A 2 –––––(6)
from equation 4, 5 & 6
A0⊕Y = A1⊕Y = A2⊕Y IES-1995
let Y = 1 Ans. (a) :
A 0 = A1 = A 2
76. The circuit shown in the following figure
realizes the function
as we know that
(a) ( A + B ) C + DE (b) (A + B) C + D + E → A+ B+C

(c) AB + C = DE (d) AB + C (D + E)
IES-2005, 1996 A.B.C = A. B. C

79. The output Y for the logic circuit shown in the 82. The gates whose output is LOW if and only if
given figure is all the inputs are high, is
(a) NAND (b) NOR
(c) OR (d) AND
Nagaland PSC CTSC - 2015, Paper-II
IES-1993
Ans. (a) : NAND Gate
(a) AB (b) A + B
Truth Table
(c) AB (d) A + B
IES-1995
Ans. (a) :
83. The negative logic AND gate shown in the given

figure is equivalent to a positive logic
Y = (A + A )(A. B ) + A B
= AB + AB
(a) AND gate (b) OR gate
= AB (c) NAND gate (d) NOR gate
80. The logic circuit shown in the given figure can IES-1993
be minimized to Ans. (d) :
(a) = A.B = A.B

(b) Negative AND gate is equivalent to NOR gate.
84. The open collector wired circuit shown below
(c) functions as :
(d)
IES-1995
Ans. (d) (a) EX-NOR (b) AND
(c) EX-OR (d) NOR
IES-1992
Ans. (c) :
F = X + (X + Y)
= X . (X + Y)
= X.(X+Y)
=X+ XY
= X(1+Y) ∴ 1+Y = 1 Y = (A.B).(A.B)
=X = (A + B) (A + B) Q A.A = 0
81. Which one of the following is equivalent to
AND-OR realization? = (A + B) . (A+B) B.B = 0
(a) NAND-NOR realization = A A +A B + A B+B B
(b) NOR-NOR realization = A B + A B = EX-OR
(c) NOR-NAND realization 85. Which of the following is a coincidence logic
(d) NAND-NAND realization circuit :
TNPSC AE-2008, IES-1994
Ans. (d) : (a)
(b)
Y1= AB+CD
Y2 = AB.CD = AB+CD (c)

Hence, NAND-NAND realization is equivalent to AND
–OR realization.
(d) Ans. (c) : As per given circuit.
The output of the circuit

IES-1992 X = AB
Ans. (a) : Which is bubble AND Gate.
89. What will be the value of Y in the given digital
circuit?
F = x.y + xy = x  y = EX-NOR
EX-NOR gate is known as coincidence logic.
86. The Boolean function F = AB + CD + E can be (a) a+b+c (b) a+b+c'
realized as (c) abc (d) abc'
Ans. (d) : Given in digital circuit-
(a) (b)
In this a NOT and AND gate have been used.

(c) (d) Output of NOT gate, c' then
output, Y= abc'
90. Boolean expression for the output of XNOR
IES-1991 (equivalence) logic gate with inputs A and B is
Ans. (a) (a) AB + AB (b) AB + AB
(c) (A + B)(A + B) (d) (A + B)(A + B)
GATE-1993
Ans. (b&c) : Boolean expression for XNOR logic gate
is-
A.B + A.B
F = A.B.C.D.E
= A.B + C.D + E
= AB + CD + E By solving option 'C', XNOR logic's expression will
87. For the circuit shown below the output F is achieve so,
given by ( A + B ) .( A + B )
= A.A + A.B + A.B + B.B A.A = 0
= A.B + A.B B.B = 0
Hence, option b & c both are correct.
(a) F = 1 (b) F = 0
91. For the logic circuit shown in Figure, the
(c) F = X (d) F = X output is equal to
IES-1999
Ans. (b) :
EXOR Gate Truth table (a) ABC (b) A + B + C

(c) AB + BC + A + C (d) AB + BC
GATE-1993)
Ans. (b) :
if input is same then output is '0' but when input is

different then output is '1'
88. The following circuit is of a:
Y = (A.B) + (B.C) + A + C
(a) Bubble NOR gate (b) Bubble NAND gate
(c) Bubble AND gate (d) AND gate = A+B+B+C+A+C
KVS TGT (WE)- 2018 = A+B+C

92. 7404 is a:
(a) Triple 3-input NAND gate
(b) Quad 2-input AND gate
(c) Hex inverter ∴ 2 unit
(d) Quad 2-input NAND gate f require 1 NOR Gate 1 OR Gate.
96. Which of the following Boolean Expressions
Ans. (c) : The 7404 is a high speed CMOS logic Quad correctly represents the relation between P, Q,
NOT Gate. The 7404 is also known as Hex inverter. R and M1 ?
93. What is the minimum number of gates
required for implementation of
Y = A + BC + AC
(a) 4 (b) 6 (a) M1 = (P OR Q) XOR R
(c) 3 (d) 5 (b) M1 = (P AND Q) XOR R
KVS TGT (WE)- 2014 (c) M1 = (P NOR Q) XOR R
(c) : As per question - (d) M1 = (P XOR Q) XOR R
GATE-2008
y = A + BC + AC
Ans. (d) :
= A + AC + BC =(P⊕Q)⊕R
= A (1 + C ) + BC
= A + BC
X = PQ
Y=P+Q
Z = (P+Q) ( PQ )
94. In the figure, the LED = (P+Q) . ( P + Q )
= P P + P Q +P Q +Q Q
= 0 +P Q + PQ+ 0
= P Q + PQ
Z = (P⊕Q) Put the value Z = P ⊕ Q
M1 = Z⊕R M1 = (P⊕Q)⊕R
(a) emits light when both S1 and S2 are closed. 97. Match the logic gates in Column A with their
(b) emits light when both S1 and S2 are open. equivalents in Column B.
(c) emits light when only of S1 and S2 is closed.
(d) does not emit light, irrespective of the switch
positions.
GATE-2001
Ans. (d) : For LED to be on output of NAND gate = 0.
NAND gate output never becomes Zero(0) as the one of
the input of NAND gate is always Zero(0). No
condition of s1 and s2 gives output of NAND gate is 0, (a) P-2, Q-4, R-1, S-3 (b) P-4, Q-2, R-1, S-3
so LED will be never glow. (c) P-2, Q-4, R-3, S-1 (d) P-4, Q-2, R-3, S-1
95. A Boolean function f of two variables x and y is GATE-2010
defined as follows : Ans. (d) :
f(0, 0) = f(0, 1) = f (1, 1) = 1; f(1, 0) = 0
Assuming complements of x and y are not (P)
available, a minimum cost solution for realizing
f using only 2-input NOR gates and 2-input OR (Q)
gates (each having unit cost) would have a total
cost of (R)
(a) 1 unit (b) 4 unit
(c) 3 unit (d) 2 unit
TANGEDCO AE- 2018, GATE-2004
Ans. (d) : f = Σm(0, 1, 3)
(S)

98. For the output F to be 1 is the logic circuit
shown, the input combination should be
(a) F = XYZ + XYZ (b) F = XYZ + XYZ

(a) A =1, B = 1, C = 0 (b) A =1, B = 0, C = 0 (c) F = XYZ + XYZ (d) F = XYZ + XYZ
(c) A =0, B = 1, C = 0 (d) A =0, B = 0, C = 1 GATE-2014, Set-I
GATE-2010 Ans. (a) :
Ans. (d) :
F = (X⊕Y).(KZ)
When input, A = 0 (X ⊕ Y) KZ + KZ ( )
B=0
C=1 {(
( X ⊕ Y ) X ⊕ Y Z + (X ⊕ Y)Z ) }
P = A B+A B
= 0 0+0. 0
Z = A B +AB
= 0 . 0 +0.0
(
=  Z ( X ⊕ Y )( X ⊕ Y ) + Z X ⊕ Y ( X ⊕ Y ) 
 ) 
= 0+0 = 1.1 + 0 as we know A.A = A, A.A = 0
=0 = 1 =  Z ( X ⊕ Y ) + 0
The X- NOR gate gives result '1' when it has even
F = XYZ + XYZ
number of 1's at the input.
101. A 3-input majority gate is defined by the logic
99. The output Y in the circuit below is always "1" function M(a, b, c) = ab + bc + ca. Which one of
when the following gate is represented by the
function
M(M(a,b,c),M(a,b, c),c) ?
(a) 3-input NAND gate (b) 3-input XOR gate
(c) 3-input NOR gate (d) 3-input XNOR gate
Gate - 2015, Set-I
Ans. (b) : M(a,b,c) = ab + bc + ca
(a) two or more of the input P, Q, R are "0" M ( a, b, c ) = ab + bc + ca
(b) two or more of the inputs P, Q, R are "1"
(c) any odd number of the inputs P, Q, R is "0" = ( a + b ).( b + c ).( c + a )
(d) any odd number of the inputs P, Q, R is "1" M ( a, b, c ) = ab + bc + ca
Nagaland PSC (CTSE) Diploma-2017, Paper-II
GATE-2011 M(M ( a, b, c ), M ( a, b, c ) , c) = M ( a, b, c )c.M ( a, b, c ) +
Ans. (b) : M ( a, b, c )c + M ( a, b, c ) .c
( )
= ab + bc + ca ( ab + bc + ca ) + ( ab + bc + ca )c +
( ab + bc + ca ) c
= ( a + b )( b + c ) ( c + a )( ab + bc + ca ) +
F = (PQ)(QR)(PR) ( a + b )( b + c ) ( c + a ) c + ( ab + bc + ca ) c
= (PQ) + (QR) + PR = ( a c + b ) ( a + c )( ab + bc + ca ) + ( a c + b ) ( a + c ) .c + abc
= PQ + QR + PR
( )( ) (
When, any two or more inputs of the above circuit are = ab + ac + bc ab + bc + ac + ab + ac + bc c + abc )
‘1’ then the output F will be always ‘1’. = abc + bca + cab + abc
100. The output F in the digital logic circuit shown F = a⊕b⊕c
in the figure is
102. A universal logic gate can implement any 104. A NAND circuit with positive logic will operate
Boolean function by connecting sufficient as
number of them appropriately. Three gates are (a) AND with negative logic
shown. (b) AND with positive logic
(c) OR with negative logic
(d) NOR with negative logic
Ans. (d) :
Positive logic NAND gate is equal to negative
logic NOR gate and vice-versa.
Which one of the following statements is Negative logic NAND gate is equal to positive
TRUE? logic NOR gate and vice versa.
(a) Gate 1 is a universal gate. Positive Logic Gate  Negative Logic Gate
(b) Gate 2 is a universal gate. Positive logic gate Negative logic gate
(c) Gate 3 is a universal gate.
(d) None of the gates shown is a universal gate.
GATE-2015, Set-3
Ans. (c)
105. What is output ‘Z’ of an EX-OR gate, where all

While G1 and G2 are basic gate but G3 is universal gate inputs are set at A
by which every gate can be obtained.
103. The output of the combinational circuit given (a) Z = A (b) Z = A
below is (c) Z = 1 (d) Z = 0
Ans. (d) :
Z = AA + AA
(a) A + B +C (b) A(B + C)
(c) B(C + A) (d) C(A + B) Z = AA + AA
Nagaland PSC (CTSE) Diploma - 2017, Paper-II Z = 0
GATE-2016, Set-1 106. If the input to the below digital circuit
Ans. (c) : consisting of cascade of 20 XOR gates is X, then
the output Y is equal to:
(a) 0 (b) 1
Y = ABC⊕AB⊕BC (c) X (d) X
CGPSC SO 14.02.2016
=  A.B.C.AB + ABC.A.B ⊕ BC GATE-2002
= [ (A + B + C) .AB + ABC.( A + B )] ⊕ BC Ans. (b) :
= ( 0 + 0 + ABC ) + ( 0 + 0 )  ⊕ BC
= AB C ⊕(BC)
= (ABC) .BC+ AB C . BC Output after first XOR gate = X ⊕ 1 = X
Output after second XOR gate = X ⊕ X = 1
= (A + B + C) BC+ AB C . (B + C)
After even number of stages the output will be 1.
= A BC+BC+AB C So, output after 20 XOR gate = 1
= ABC + BC (1 + A ) + ABC 107. For a NAND gate output is low when input are
____.
= ABC + BC + ABC + ABC (a) 0, 0 (b) 0, 1
= BC (1 + A ) + AB ( C + C ) (c) 1, 1 (d) 1, 0
RRB JE- 01.09.2019, 3:00 PM - 5:00 PM
= BC + AB
NPCIL-2015
= B ( C+A) UPRVUNL AE– 11.06.2014
Ans. (c) : We got NAND gate with the help of AND 111. How many numbers of NOR gates required to
and NOT gate. For a NAND gate output is low when realized AND gate.
both input are high (a) 2 (b) 4
Symbol of NAND ⇒ (c) 3 (d) 5
Truth table of NAND Gate -
Ans. (c) : 3 NOR gates are required to realize AND
Inputs Output
gate.
A B Y = A.B
0 0 1
0 1 1
1 0 1
1 1 0
108. 7400 IC means (indicate) _____. Y = A + B = A.B = A.B
(a) 2-input NAND (b) 2-input AND Boolean expression of AND gate [Y = A.B]
(c) 2-inpu OR (d) 2-inpu NOR 112. Determine the Boolean function of the
NPCIL-2015 following circuit.
Ans. (a) : 7400 - Quad 2 - input NAND gates
7408 - Quad 2 - input AND gates
7432 - Quad 2 - input OR gates
7402 - Quad 2 - input NOR gates
109. The circuit shown in the figure converts
(a) X = A + B (b) X = AB + AB
(c) X = AB (d) X = AB
NLC GET -24.11.2020
Ans. (b) : X = ( A + B ) . ( A + B )
X = ( A.A ) + ( A.B ) + ( AB ) + ( B.B )
X = A.B + A.B
(a) BCD to binary code 113. The output Z = ?
(b) Binary to excess-3 code
(c) Excess-3 to Gray code
(d) Gray to binary code
Ans. (d) : In the given circuit we see that AND and OR
gate is used as a buffer. The output of one bit will be (a) AC AB (b) ABC
input for next gate that is XOR gate. So that's why the
given circuit is Gray to binary bode. (c) ABC + ACB (d) ABC + CB
⊕
⊕
110. Y = A B A , where ⊕ represents XOR, is ISRO Scientist December, 2017

equal to: Ans. (b) :
(a) B (b) AB
(c) A (d) A
UPPCL AE-05.11.2019
Ans. (a) : Y = A ⊕ B ⊕ A
Y = ( AB + AB ) ⊕ A
( )
Y = AB + AB ⋅ A + ( AB + AB ) A Z = ( A + C ) A.B + ABC
Y = ( AB.AB ) A + AB
Z = ABC + ABC
Z = ABC
= (A + B) ( A + B ) .A + AB 114. Following circuit implements a
Y = ( AA + AB ) ( AA + AB ) + AB
Y = ( A + AB ) . ( AB ) + AB
Y = AB + AB
Y = B(A + A) Q  A + A = 1 (a) de-multiplexer (b) multiplexer
(c) Y = I0 ( A 0 + A1 ) (d) Y = I0 ( A1 + A 0 )
Y=B
Ans. (b) (d) Availability of large numbers of only NOT
gates is sufficient to realize any
combinational circuit
BSNL(JTO)-2002
Ans. (b) : Universal logic gates are the logic gates that
are capable of implementing any Boolean function
without requiring any other type of gate. A universal
Output Y = A 0 I0 + A1 I0 gate is a logic gate which can implement any Boolean
function without the need to use any other type of logic
It is equivalent to a 2 × 1 MUX circuit. So given circuit gate. The NOR and NAND gate are universal gates. this
is multiplexer. means that you can create any logical Boolean
115. The Boolean function F = AD + BD can be expression using only NOR gates or only NAND gates.
realized by 117. In the given network of AND and OR gates f
can be written as :
(a)
X 0 X1X 2 .......X n + X1X 2 ......X n +

(a)
(b) X 2 X 3 ......X n .......X n
(b) X 0 X1 + X 2 + X 3 + ....... + X n −1 .X n
(c) X 0 + X1 + X 2 + .......X n
X 0 X1X 3 ....X n −1 + X 2 + X 3 + X 5 ......X n −1 + .....
(d)
(c) ............ + X n − 2 + X n −1 + X n
Ans. (d) :
(d)
output at gate (1) = X0X1

output at gate (2) = X0X1 +X2
DRDO-2008 output at gate (4)= (X X +X )X + X
0 1 2 3 4
Ans. (d) : output at gate (6)= (X0X1X3+X2X3+X4)X5+X6
= X0X1X3X5+X2X3X5+X4X5+X6
output at nth gate

Solve - f n = X 0 X1X 3 ....X n −1 + X 2 + X 3 + X 5 ......X n −1 + ....
K = A.D = A + D ........ + X n − 2 + X n −1 + X n
M = B.D = B + D 118. For the switch circuit, taking open as 0 and
f = ( A + D ) .( B + D ) closed as 1, the expression for the circuit is Y.
f = A.D + B.D
116. Which of the following statements is true?
(a) Availability of large numbers of only AND (a) A + (B+C) D (b) A +BC+D
gates is sufficient to realize any (c) A (BC+D) (d) None of these
combinational circuit ISRO Scientist Engg.-2006
(b) Availability of large numbers of only NAND Ans. (c) : Switch B and C connected in series, so this is
gates is sufficient to realize any called AND gate
combinational circuit
(c) Availability of large numbers of only OR
gates is sufficient to realize any Switch D is connected in parallel to B and C switches
combinational circuit so it is called OR gate

BC + D Ans. (c) :
Again a switch A is connected in series to (BC + D).
Z = ABC
5 NAND Gate
The expression for the circuit is:- 122. The output F in the digital logic circuit shown
Y = A (BC + D) in the figure is
119. What will be the output of the following circuit,
if point-P is stuck at 1?
(a) Y = AB + AB + C
(b) Y = AB + AB + C
(a) A+B+C (b) A'B'C' (c) Y = A⊕ B + C
(c) (ABC)' (d) 0
ISRO Scientist Engg.-2013 (d) Y = AB + C
Ans. (b) :
Ans. (c) :
Y = ( A ⊙ B ) .C where -
Y = (A + B + C) ⊕ P ∴ A ⊙ B = A ⊕ B
Y = A⊕B+C  
( )
= A + B + C .P + ( A + B + C ) .P
Y = AB + AB + C
= ( ABC ) .1 + ( A + B + C ) .0 where, P = 1 123. The Boolean expression Y (A,B,C)=A+BC is to
be realized using 2-input gates of only one type.
Y = ABC P=0 What is the minimum number of gates
120. The Boolean expression for the output of the required for the realization?
logic circuit shown in the figure is (a) 1 (b) 2
(c) 3 (d) 4 or more
Ans. (c) : We know that A + BC = (A + B) (A + C)
three gate requires to implement this function.
(a) Y = AB + AB + C (b) Y = AB + AB + C
(c) Y = AB + AB + C (d) Y = AB + AB + C
Ans. (b) :
124. What are the minimum numbers of NOT gates

and 2-input OR gates required to design the
logic of the driver for 7 segment display?
Y = ( A ⊕ B ) .C (a) 3 NOT and 4 OR (b) 2 NOT and 4 OR
(
= ( A ⊕ B) + C Q A ⊕ B = A  B ) (c) 1 NOT and 3 OR (d) 2 NOT and 3 OR
(
= A  B + C Q A  B = AB + AB )
Ans. (d) : 2 NOT gate and 3 OR gate both have two
input variable will required to design to logic of the
= AB + AB + C driver for 7 segment display.
121. The minimum number of 2-input NAND gates 125. The output Y of the circuit shown below is
required to implement the Boolean function Z
= AB'C, assuming that A, B and C are
available, is
(a) 2 (b) 3
(c) 5 (d) 6 (a) 0 (b) X
GPSC Asstt. Prof. 11.04.2017 (c) 1 (d) X
GATE-1998 UPPCL AE- 31.12.2018
Ans. (b) 129. The circuit shown in the figure is functionally
equivalent to
F1 = X (a) NOR gate (b) OR gate

F2 = X ⊕ X = XX + XX ( A ⊕ B = AB + AB) (c) EX-OR gate (d) NAND gate
RPCS Lect.-2011
F2 = 1
Ans. (c) :
Y = F2 X = 1.X = X
Y=X
126. The Boolean expression X = AB + CD represents
(a) Two ORs ANDed together
(b) Two ANDs ORed together Y = AB.AB
(c) A 4-input AND gate
Y = AB + AB
(d) EX-OR gate
Y = A ⊕ B → EX − OR gate
TNPSC AE-2014
Ans. (b) : X = AB + CD 130. The circuit shown in figure realizes the
function:
127. To implement the Boolean function F(A,B,C) =

π (0, 2, 4, 5, 6) with NOR. NOR logic how many (a) (A + B + C) (DE) (b) (A + (B + C) (DE)
number of 2-input NOR gates are required?
(a) 3 (b) 2 (c) (A + B + C) (DE) (d) (A + B + C) (DE)
(c) 6 (d) 5 IES - 1992
TNPSC AE-2013 Ans. (d) :
Ans. (a) : F = π[ 0, 2, 4, 5, 6]
F = (B + C)(B + C)(A + C)
Y = A+ B+C+D+ E
= (A + B + C) (D + E)
Hence total 3 NOR gate will use.

Y = A + B + C D.E ( )( )
128. Logic expression for Y in terms of logical 131. The following circuit can be represented as
variables A and B is
(a) f(A, B, C) = C
(b) f(A, B, C) = ∑(0, 1, 2, 5, 6, 7)
(c) f(A, B, C) = ∑(0, 2, 4, 6)
(d) None of the above options
(a) A + B (b) A + B Ans. (c) :
(c) A + B (d) A + B
Ans. (d) : Y = A.B
Y =A+B

From the circuit –
Y = AB.CD + EF
F1 = A + B = AB
Y = AB.CD.EF
F2 = A⋅F1 = A⋅ AB = 0
Y = 6 NAND Gate
F3 = B⋅F1 = B⋅ AB = 0 135. Which of the following gates is also called 'all
F4 = F2 ⋅ F3 ⋅ C = C or nothing gate'?
(a) AND (b) OR
F5 = F2 ⋅ F3 ⋅ F4 = C (c) NOR (d) XOR
F6 = F4 ⋅ C = C ⋅ C = 0 KVS TGT (WE)- 2016
Ans. (a) : AND is also called all or nothing gate,
F = C⋅C = C because it produces high only when all its input are high
in all other respects its output is low.
136. The combination of NAND gate is given bellow.
Which one of the following output logic gate is
formed by this combination.
F = ∑ (0, 2, 4, 6)
132. Minimum number of two input NAND gates
required to realize the logic function
( AB + AB ) is
(a) 5 (b) 3 (a) AND (b) NOT
(c) OR (d) Ex-OR
(c) 6 (d) 4
Ans. (c) :
Ans. (d) : The number of 2-input NAND gates required
to implement a 2-input XOR gate is 4.
• The output of a 1st NAND gate = A

133. Which one of the following gate is also known • The output of a 2 NAND gate = B
nd
as equivalence gate? • The output of a 3rd NAND gate = A.B

(a) NOR (b) AND = A+B
(c) Ex-OR (d) Ex-NOR
= OR Gate
Ans. (d) : Ex-NOR gate is also called equivalence gate 137. What is the output Y for the logic circuit shown
because when all its inputs are equal or equivalent then in the figure?
its output is 1(High).
Truth table of Ex-NOR
A B Y (Output)
0 0 1 (High)
0 1 0 (low)
1 0 0 (low)
1 1 1 (High)
(a) AB + AB (b) AB + A + B
134. Number of 2 input gate required to design Y =
AB + CD+EF (c) AB + AB (d) A + B
(a) 2 (b) 3 ESE-2022
(c) 4 (d) 6 Ans. (d) :
BEL-2015
Ans. (d) : Y = AB + CD + EF
Y=Y
Y = AB + CD + EF
Y = AB.CD.EF Y=P+Q …..(i)
Y = AB.CD + EF S = A + A = A.A = 0

T = A.B In the above diagram, find out the correct
U = A. B expression of Y.
(a) Y = (A’ + B’) C + (DE)
P = S.T = 1(A.B) = A.B
(b) Y = (A’+B) C + (DE)’
Q = U = A.B = A + B (c) Y = (A’ + B’) C+(DE)’
from equation (i) (d) Y = (A +B) C’ + (DE)’
Y = P + Q = A.B + B + A LMRC AM- 16.07.2021
= B(1 + A) + A Ans. (c) :
Y = A+B
138. The minimum number of two input NAND
gates required to realize f(A,B,C) = AB + BC
+CA is
(a) 5 (b) 6
P = A.B.C
(c) 7 (d) 8
TSTRANSCO AE- 2018 = A.B + C = A.B + C
Ans. (b) : Q = DE
( ) (
Y = PQ = A.B + C .DE = A.B.C + DE )
( )
= A + B .C + DE
141. How can we use the X-NOR gate as an

inverter?
hence 6 NAND gate required to realize (a) By trying all but one input terminal to logic 1
f (A, B, C) = AB +BC + CA and feeding the signal to be inverted to the
139. remaining terminal
(b) By tying all input terminal to logic 0 and
feeding the system to be inverted to the other
terminal
(c) By connecting one input terminal to logic 0
and feeding the signal to be inverted to the
Find the correct expression of X. other terminal
(a) X = AB + (AB)’ (b) X = A +B’ (d) By connecting two input terminals to logic 1
(c) X = A’ B’ + (AB)’ (d) X = A’ B’ +AB and feeding the signal to be inverted to the
LMRC AM- 16.07.2021 remaining channel
Ans. (d) : DFCCIL Executive S&T 29.09.2021, 12:30 to 2:30PM
Ans. (c) : When one input terminal is connected by
logic 0 and the other terminal is inverted the X-NOR
Gate acts like an inverter.
142. The given truth table of a logic gate belong to:
Truth Table
Output at P = A.B A Q
Output Q = AB
0 1
Then output at X = P + Q
1 0
= A.B + AB
(a) the NOR gate (b) the NAND gate
140. (c) the NOT gate (d) the XOR gate
Ans. (c) : The logic gate shown in the figure is a NOT
gate, NOT gate inverts the input, if the input logic is 0,
The output logic will be 1 and if the input logic is 1 then
the output logic will be 0.

X =A⊕B
(iv) Combinational Logic Circuits
Y =A+B
1. The number of 3-to-8 decoders needed to wire = AB
up a 4-to-16 decoder is: = AB
(a) 0 (b) 2
(c) 1 (d) 3
UPPSC Poly. Tech. Lect.-22.03.2022, Paper –I
UPPCL AE-05.11.2019
Hence, the given logic function is half adder.
Ans. (b):
Given decoder To be implemented
Required 4. Consider the 2-bit multiplexer (MUX) shown in
decoder the figure. For OUTPUT to be the XOR of C
and D, the values for A0, A1, A2 and A3 are
3×8 4×16 2+0= 2
_____.
2×4 3×8 2+0 = 2
3×8 6×64 8+1= 9
4×16 6×64 4+0 = 4
4×16 8×256 16+1= 17
2. In a half subtractor circuit with X and Y as
inputs, the output borrow (B) and difference (D
= X – Y) are given by
(a) B = X ⊕ Y, D = XY
(b) B = XY, D = X ⊕ Y
(a) A0 = 0, A1 = 0, A2 = 1, A3 = 1
(c) B = XY, D = X ⊕ Y (b) A0 = 1, A1 = 0, A2 = 1, A3 = 0
(d) B = XY, D = X ⊕ Y (c) A0 = 0, A1 = 1, A2 = 1, A3 = 0
UPPSC ITI Principal/Asstt. Director-09.01.2022 (d) A0 = 1, A1 = 1, A2 = 0, A3 = 0
Ans. (b) : Half subtractor Circuit GATE-2022
Input Output Ans. (c) : Output = CDA 0 + CDA1 + CDA 2 + CDA 3
X Y Difference Borrow
By putting
(D) (B)
A 0 = A 3 = 0 and A1 = A 2 = 1
0 0 0 0
0 1 1 1 Then output = = 0 + CD + CD + 0 = CD + CD = C ⊕ D
1 0 1 0 5. The logic circuit realized by the circuit shown
1 1 0 0 in the given figure will be
Difference (D) = X ⊕ Y
Borrow (B) = XY
3. Identify logic function given below -
(a) B ☼ C (b) F = B ⊕ C
(a) Half Adder (b) Full Adder (c) A ☼ C (d) F = A ⊕ C
(c) Half Subtractor (d) Multiplier RPSC ACF & FRO 23.02.2021
UPPSC Poly. Tech. Lect.-22.03.2022, Paper -I RPSC VP/Suptd. ITI 05.11.2019
Ans. (a) IES - 1999, GATE - 1992
Ans. (d) : According to given logic circuit
X = AB.AB
F = S1 S 0 I0 + S1S0 I1 + S1 S 0 I2 + S1S0 I3
(
= A+B A+B )( ) F = A BC + ABC + ABC + ABC
= A.B + AB F = AC(B + B) + AC(B + B)
= AB + AB F = AC ×1 + AC ×1
= AB + AB F = A⊕C
6. A half adder can be constructed using Ans. (d) : A decade counter counts from 0 to 9. It has 4
(a) One X-OR and one OR gate with their inputs flip flop, the steps skipped are 10 to 15 or 1010 to 1111.
connected in parallel 9. For the given circuit, which output gives logic
(b) One X-OR and one OR gate with their inputs function A.B.C.D?
connected in series
(c) One X-OR and one AND gate
(d) Two X-NOR gates
IES - 2015
Ans. (c) :
For Half adder -

Input Yout
A B S C (a) X (b) Y
0 0 0 0 (c) X+Y (d) Z
0 1 1 0 UPRVUNL AE -19.07.2021, Shift-II
1 0 1 0 Ans. (d) : Z = ABCD
1 1 0 1 X = ABCD + ABCD
Y = ABCD + ABCD
So, a half adder can be constructed using one XOR and
one AND gate.
7. Consider the circuit shown below with 2 : 1
MUX, The output f is given by
Where (') is the complement of the variable.
(a) X'Y' + XY (b) X'Y + XY'

(c) X' + Y' (d) X + Y
Ans. (a) :
10. The addition of 3-bit is performed using which

adder?
(a) Full adder (b) Flip-flop
(c) Counter (d) Half adder
Output = X.1 + X.0 UPRVUNL AE -19.07.2021, Shift-II
=X Ans. (a)
Output (f) = YI0 + YI1
= YX + XY
f = XY + XY
8. A decade counter skips .
(a) 0101 to 1111 (b) 1001 to 1111 The full adder extends the concept of the half-adder by
(c) 1100 to 1111 (d) 1010 to 1111 providing an additional carry-in (Cin) input. Three
UPRVUNL AE -19.07.2021, Shift-II inputs (A, B and Cin) and two outputs (sum and carry).
11. Consider the following statements: Ans. (d) : Inputs = 1024
A multiplexer Output = 1
1. Selects one of the several inputs and Select line = S
transmits it to a single output. Inputs = 2S
2. Routes the data from a single input to one 1024 = 2S
of many outputs. S = 10
3. Converts parallel data into serial data. 14. Which logic device is called a data distributor?
4. It is a combinational circuit. (a) Multiplexer (MUX)
Which of the above statements are correct? (b) Demultiplexer (DEMUX)
(c) Encoder
(d) Decoder
(c) 1, 3 and 4 only (d) 2, 3 and 4 only
IES – 2020, 2016, 2008 Ans. (b) : A demultiplexer (also known as data
distributor) is defined as a circuit that can distribute or
TNPSC AE-2008
deliver multiple output from a single input.
Ans. (c) : Multiplexer - Selects one of the several
15. A DEMUX with an 8-bit select input has :
inputs and transmits it to a single output [multiple
(a) one data input and 256 data outputs.
Inputs & Single output]
(b) one data input and 16 data outputs.
(c) one data input and 64 data outputs.
(d) one data input and 128 data outputs.
Ans. (a) : A DEMUX
no. of select line (S) = 8
• Converts parallel data into serial Data.
no. of input line = 1
• It is a combinational circuit. no. of output line = Y
• It is also called Data selector Y = 2S
• Many to one circuit. Y = 28 = 256 data
• From multiple input only one input is selected (as 16. What is the minimum number of universal
connect) to the output with respect to select line. gates needed to realise full subtractor?
12. How many inputs and outputs does a half- (a) 8 (b) 9
subtractor have? (c) 10 (d) 11
(a) 2 inputs and 2 outputs APPSC Poly. Lect. 15.03.2020
(b) 3 inputs and 2 outputs Ans. (b) : Universal gates are NAND and NOR. So any
circuit in digital electronics can be realised using these
(c) 2 inputs and 3 outputs
universal gates. So a full subtractor can be made by
(d) 3 inputs and 3 outputs using 9 universal gates (NAND gate).
Ans. (a) : Half-subtractor have two input A, B and
difference D, Borrow B. so it is works on 2 inputs and 2
outputs.
(Full Subtractor using NAND gate)

17. A full adder can be made out of……….
(a) two half adders
13. How many select lines are needed in a (b) two half adders and a OR gate
multiplexer (MUX) with 1024 inputs and one (c) two half adders and a NOT gate
output? (d) three half adders
(a) 16 (b) 14
Nagaland PSC- 2018 Diploma, Paper II
(c) 12 (d) 10 Nagaland PSC (CTSE) Diploma-2017, Paper II
APPSC POLY. LECT. 14.03.2020 UJVNL AE-2016, IES - 1997
Ans. (b) : A full adder can be made out of a two half 20. In the below circuit, X is given by
adder and one OR gate.
(a) X = ABC + ABC + ABC + ABC

(b) X = ABC + ABC + ABC + ABC
(c) X = AB + BC + AC
18. For a binary half-subtractor having two inputs (d) X = AB + BC + AC
A and B, the correct sets of logical expressions ISRO Scientist Engg.-2016
for the output D (= A minus B) and X (= BARC Scientific Officer-2016
borrow) are IES - 2010, GATE -2007
(a) D = AB + AB, X = AB Ans. (a) :
(b) D = AB + AB, X = AB
(c) D = AB + AB, X = AB
(d) D = AB + AB, X = AB
TNPSC AE - 2018
Nagaland PSC CTSE (Degree)-2017, Paper-II Let for Y, Let for X
IES-2016, 2003 Truth Table : Truth Table :
GATE - 2014, GATE - 1999
A B Y Y C X
Ans. (c) : Half subtractor is a type of combinational
logic circuit which is used to subtract two bits therefore 0 0 A B I 0 =0 0 0 YC I 0 = 0
it will result into two output that is difference and 0 1 AB I1 = 1 0 1 YC I1 = 1
borrow 1 0 AB I = 1 1 0 YC I 2 = 1
2
1 1 AB I3 = 0 1 1 YC I3 = 0
Output (Y) = A BI0 + ABI1 + ABI 2 + ABI3
= A B.0 + AB.1 + AB.1 + AB.0
Difference, D= AB + AB = A⊕B Y= AB + AB
Borrow, B0 = A B Output ,X = Y CI0 + YCI1 + YCI 2 + YCI3
Truth table -
= Y C.0 + YC.1 + YC.1 + YC.0
A B Difference Borrow
0 0 0 0 X = YC + YC
0 1 1 1
Put the value of Y -
1 0 1 0 X = (AB + AB).C + (AB + AB)C
1 1 0 0
= [ (A + B) (A + B)C ] + ABC + ABC
19. Without any additional circuitry, an 8:1 MUX
can be used to obtain = [ (A+ B )( A +B)].C + ABC + ABC
(a) some but not all Boolean functions of 3 = (A A +AB+ A B + BB ).C+ ABC + ABC
variables
(b) all functions of 3 variables but none of 4 = ABC+ A B C + ABC + ABC
variables X = ABC + ABC + A BC + ABC
(c) all functions of 3 variables and some but not
all of 4 variables 21. A 2-bit binary multiplier can be implemented
(d) all functions of 4 variables using
TANGEDCO AE- 2018 (a) 2 input ANDs only
Nagaland PSC CTSE- 2015, Paper-II (b) 2 input XORs and 4 input AND gate only
GATE - 2003 (c) Two input NORs and one XNOR gate
Ans. (c) : Without any additional circuitry, an 8:1 MUX (d) XOR gates and shift registers
can be used to obtain all functions of 3 variables and Nagaland PSC 2018, Diploma Paper-II
some but not all of 4 variables. GPSC Asstt. Prof. 11.04.2017
Nagaland PSC CTSE- 2015, Paper-II Ans. (a)
GATE - 1997
Ans. (b) : A 2-bit binary multiplier can be implemented
using 2 input XORs and 4 input AND gate only.
22. The following switching functions are to be
implemented using a decoder:
f1 = ∑ m(1, 2, 4, 8,10,14)
f2 = ∑ m(2, 5, 9,11)
f3 = ∑ m(2, 4, 5, 6, 7)
The minimum configuration of the decoder
should be
(a) 2 - to - 4 lines (b) 3 - to - 8 lines
(c) 4 - to - 16 lines (d) 5 - to - 32 lines
Sikkim PSC SI (Mains)-2018 Y= A I0 + AI1
RPSC LECTURER-10.01.2016 = A (0) +AB
IES - 2015, IES - 1994 Y = A.B
Ans. (c) : Given Functions :- Y1 = A × 1 + A × 0
f1 = ∑m (1,2,4,8,10,14)
f2 = ∑m (2,5,9,11) Y1 = A
f3 = ∑m (2,4, 5,6,7) So, F = BA + BA = A ⊕ B
In above functions, the highest value can assume is AND Gate - 1MUX
m(14) X-OR Gate - 2 MUX
m(14) = 1110 4 bits 25. The sum (S) of A and B in a half Adder can be
So minimum configuration for the above functions of implemented by using K NAND gates. The
the decoder should be 4 to 16 lines. value of K is
23. Which one of the following can be used as (a) 3 (b) 4
parallel to serial converter? (c) 5 (d) None of these
(a) Decoder (b) Digital counter
(c) Multiplexer (d) Demultiplexer
Nagaland PSC-CTSE- 2015, Paper-II
Ans. (b) : In half-adder,
IES – 2004, 2000
sum (s) = A ⊕ B = AB + AB
Ans. (c) : Multiplexer- Multiplexer is a combinational
logic circuit which have many data input and single
output depending on select or control inputs one of the
input line is transferred to the output based on the
values of selection lines. Hence it is known as " Many
to one circuit OR parallel to serial converter. So, required '4' 2-input NAND gates
Ex.- (4×1) MUX Hence, the value of K = 4
26. For designing a HA required no. of NAND
gates are ____.
(a) 4 (b) 5
(c) 9 (d) None
LMRC AM (S & T) - 13.05.2018
NPCIL-2015
• It is parallel to serial converter.
Ans. (b) : For designing a Half Adder circuit. We
• It is known as Data selector circuit. required 5 NAND gates. Half Adder is a logic circuit
• It is also known as universal logic circuit. for the addition of two one-bit numbers.
24. What are the minimum number of 2-to1 → Symbol of HA -
multiplexers required to generate a 2-input
AND gate and a 2-input EX-OR gate ?
(a) 1 and 2 (b) 1 and 3
(c) 1 and 1 (d) 2 and 2
Nagaland PSC (Degree) 2018 (Paper-II)
Mizoram PSC Jr. Grade - 2018 (Paper-II) • Total number of NAND gates required to construct
GATE - 2009 half adder ⇒ 5
Truth table of Half adder - 30. Consider the multiplexer based logic circuit
shown in the figure
Inputs Outputs
A B Sum ( S ) Carry ( C )
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
27. When a binary adder is used as BCD adder, the Which one of the following Boolean functions is
sum is realized by the circuit ?
(a) Correct when it is less than 9. (a) F = WS1S2 (b) F = WS1 + WS2 + S1S2
(b) Correct when it is larger than 9. (c) F = W + S1 + S2 (d) F = W ⊕ S1 ⊕ S2
(c) Correct when it is less than 16.
(d) None of these.
GATE – 2014, Set-III
Nagaland PSC- 2018, Diploma Paper-II Ans. (d) :
Nagaland PSC CTSE - 2015, Paper-II
Ans. (a) : If we try to add two decimal digit in BCD
with a 4 - bit ripple carry adder we will get a binary sum
ranging from 0 to 9. When the binary sum is less than or
equal to 9, it correctly represents the sum in BCD.
28. How many 3 to 8 line decoders with an enable
input are needed to construct a 6 to 64 line
decoder without using and other logic gates? Y = W S1 + W S1 = W⊕S1
(a) 11 (b) 10 Y = W ⊕ S1 = W S1 = WS1 + W S1
(c) 9 (d) 8 output F = Y S2 +S2 Y
TSTRANSCO AE-2018
IES - 2017 = (W S1 + W S1 )S2 + S2 (W S1 + W S1 )
TRB Poly. Lect. -2012 = S2 S1 W + S1 S2 W + S1S2 W + S1S2 W
Ans. (c) : Number of 3-to-8 decoders are needed to F = W⊕S1⊕S2
construct a 6 to 64 line decoder
31. To add two m-bit numbers, the required
 64  8  number of half adders is
 = 8  +  = 1 (b) 2m–1
 8  8  (a) 2m–1
= 8+1 (c) 2m+1 (d) 2m
=9 Nagaland PSC (Degree) 2018, Paper-II
29. Dynamic hazard only arises in a Nagaland PSC CTSE (Degree)-2017, Paper-II
(a) Sequential circuit Ans. (a) : We know that in order to realize a full adder,
(b) Combination circuit two half adders are required.
(c) Sequential and combinational circuit So, to add 2m-bit, we need (m-1) full adders.
(d) None of these The the total number of half adders needed
= 2 (m–1) +1
= 2m–2+1
= 2m–1
Ans. (c) : Dynamic hazards - Dynamic hazards are a
series of changes of a single state that happen several 32. The Inputs of an 8×1 multiplexer for the
times in a row when the signal is expected to change implementation of the following function are Y
state only once. (A,B,C,D) = ∑ m (0,2,3,4,5,8,9,10,11,12,13,15)
Dynamic hazards often occur in larger logic circuit (a) D0 = D' , D1 =1, D2=1,D3=0, D4=1,D5=1,
where there are different routes to the output and routes D6=1,D7=D
have different delays. (b) D 0 = D , D1=1, D2=1, D3=0, D4=1, D5=1,
In combinational circuits, delays in logic gates (NAND, D 6=1,D7 = D'
NOR) may cause dynamic hazards. (c) D 0= D', D1=1,D2=1,D3=0,D4=1,D5=1,D6=1,

In sequential circuits delays by flip-flop may cause D 7 = D'
dynamic hazards. (d) D0= D, D1=1, D2=1, D3=0, D4 =1,D5 =1,
So, the dynamic hazards problem occurs combination D6=1, D7=D
and sequential circuit both. TNPSC AE- 2019
Ans. (a) (a) Y = BC + A (b) Y = C
(c) Y = AC’ + BC (d) Y = B
Ans. (d)
X = 0AB + 1AB + 0AB + AAB

X = 0 + AB + 0 + AB
X = B(A + A)
X=B
Y = CB + CB
33. The Boolean function realized by circuit below Y = B(C + C)
is
Y = B Q (C + C = 1)
35. In a digital system, there are three inputs A, B
and C. The output should be high when at least
two inputs are high. The Boolean expression
for the output is :
(a) AB + BC + AC
(b) ABC + ABC + ACB + ABC
(c) ABC + ABC + ABC
(d) AB + BC + AC
IES - 1997
(a) BCD + BCD (b) A ( BD + CD )
Ans. (a,b) :
(c) ABCD (d) A ⊕ D A B C Y
UPPCL AE- 31.12.2018 0 0 0 0
Ans. (d) : 0 0 1 0
ABCIo + ABCI1 + ABCI 2 + ABCI3 + ABCI 4 + ABCI5 0 1 0 0
+ ABCI6 + ABCI7 0 1 1 1
put I0 = I1 = I2 = I3 = D and 1 0 0 0
I4 = I5 = I6 = I7 = D 1 0 1 1
f = ABCD + ABCD + ABCD + ABCD + ABCD 1 1 0 1
+ ABCD + ABCD + ABCD 1 1 1 1
f = AD ( BC + BC + BC + BC ) + AD ( BC + BC + BC + BC ) For output
f = ( AD + AD )( BC + BC + BC + BC )
f = A ⊕ D ( B + B)
output = BC + AC + AB
f = A⊕D
SOP form
34. In the following circuit, Y can be expressed as: output = A BC+A B C +AB C +ABC
36. Which resource of FPGA implements
combinational logic functionality?
(a) Block RAM
(b) Configurable Logic Block (CLB)
(c) Routing Switch Matrix
(d) All of above
Ans. (b) : Configurable logic block of FPGA C1 = 1 and C0 = 0 then O2 is high → Y = R
implements combinational logic functionality. C1 = 1 and C0 = 1 then O3 is high → Y = S
A configurable logic block (CLB) is the basic repeating∴ So the given circuit acts like 4:1 multiplexer with
logic resource on an FPGA. inputs P, Q, R and S and selection inputs C1 and C0.
When linked together by routing sources the
components in CLBs execute complex logic function, 39. Which device has one input and many outputs?
CLBs contain smaller components including flip-flop (a) Multiplexer (b) Demultiplexer
look-up tales. (c) Counter (d) Flip flop
37. The logic function implemented by following Nagaland PSC (CTSE) Diploma-2017, Paper II
4:1 MUX is Ans. (b) : A demultiplexer or demux is a device takes a
single input line and routes it to one of several digital
output lines. It is a process taking information from one
input and transmitting over one of many output.
40. A 4 : 1 multiplexer requires _____data
selection line.
(a) 4 (b) 2
(c) 1 (d) 16
(a) Z = X AND Y (b) Z = X OR Y Nagaland PSC (CTSE) Diploma-2017, Paper II
(c) Z = X XOR Y (d) Z = X XNOR Y Ans. (b) : For 2n :1 mux requires n data select so 4:1
2
ISRO Scientist Engg.-2013 mux, 2 : 1, n = 2 data selection line required.
Ans. (c) : 41. The number of inputs and outputs of a full
adder are
(a) 3 and 2 respectively
(b) 2 and 3 respectively
(c) 3 and 4 respectively
(d) 2 and 4 respectively
Ans. (a) : The number of inputs and outputs of a full
Z = I0 XY + I1XY + I2 XY + I3 XY adder are 3 and 2 respectively.
42. Parallel adders is
Z = XXY + YXY + XXY + 0XY
(a) Sequential circuit
Z = 0 + YX + XY + 0
(b) Combinational circuit
Z = YX + XY (c) Either sequential or combinational circuit
Z = X⊕Y (d) None of the above
or Nagaland PSC (CTSE) Diploma-2017, Paper II
Z = X XOR Y Ans. (b) : A parallel adder is a combination of several
38. The functionality implemented by the circuit adder connected in cascaded form. So parallel adder is
below is the example of combinational circuit.
43. Subtractors are designed using ______ ICs.
(a) digital (b) analog
(c) subtractor (d) adder
TNPSC AE - 2018
Ans. (d) : Subtractor are designed using adder ICs.
Because the substractor can be designed using the same
approach as an adder. As with an adder in the general
case of calculation on multi-bit number.
44. Compared to a parallel adder, a serial adder is
(a) Faster and requires more hardware
(b) Slower and requires more hardware
(a) 2-to-1 multiplexer (b) 4-to-1 multiplexer (c) Faster and requires less hardware
(c) 7-to-1 multiplexer (d) 6-to-1 multiplexer (d) Slower and requires less hardware
Nagaland PSC (CTSE) Diploma-2017, Paper II GPSC Asstt. Prof. 11.04.2017
Ans. (b) : When, Ans. (d) : A serial adder is used to add two binary
C1 = 0 and C0 = 0 then O0 is high → Y = P numbers in serial form. Compared to a parallel adder, a
C1 = 0 and C0 = 1 then O1 is high → Y = Q serial adder is slower and requires less hardware.
45. Combinational circuit (a) ABC (b) A ⊕ B ⊕ C
(a) Always contains memory elements (c) A + B + C (d) A B C
(b) Never contains memory elements UKPSC Assistant Radio Officer Screening Exam.-2011
(c) May sometimes contain memory elements ISRO Scientist Engg.-2007
(d) Contains only memory Ans. (c)
Ans. (b) : A combinational circuit consist of logic gates
whose output at any instant of time are determined
directly from present combination of inputs without
regards to previous output.
Example– Adder, substractor, encoder, decoder
46. The minimum number of 2:1 multiplexers
required to realize a 4 :1 multiplexer is
(a) 6 (b) 5
Q = ABC + AB + AB + AB
(c) 4 (d) 3
Mizoram PSC IOLM -2018, Paper II Q = ABC + AB + A ( B + B )
4 2 Q = ABC + AB + A
Ans. (d) : Number of MUX = +
2 2 Q = A ( BC + B ) + A
=2+1
=3 Q = A ( B + B) ( B + C) + A
47. Digital system has been divided by Q = A ( B + C) + A
(a) Combinational and Sequential
(b) Synchronous and asynchronous Q = AB + AC + A
(c) High level logic and Low level logic Q = AB + A + C
(d) Sum of product and product of Sum Q = ( A + A ) ( A + B) + C
Ans. (a) : A digital system is divided into two part. Q = A+B+C
Combinational and sequential circuit. Combinational 51. How many full adder(s) are required in a serial
circuit does not contain any memory while sequential adder to perform 8-bit addition?
circuit contain memory. (a) Two (b) One
48. A pulse train can be delayed by a finite number (c) Three (d) Eight
of clock periods using TNPSC AE-2014
(a) A serial-in serial-out shift register Ans. (b) :
(b) A serial-in-parallel-out shift register
(c) A parallel-in-serial-out shift register
(d) A parallel-in-parallel-out shift register
Ans. (a) : A pulse train can be delayed by a finite number
of clock periods by using a serial in serial out shift
register. This is done by using shift register, using D-FF
we can delay serial input signal to appear at serial O/P.
49. In a multiplexer, the numbers of selection lines One full adder is required in a serial adder to perform 8-
are n. The size of multiplexer is- bit addition.
(a) 2n × n, (b) n × 1, 52. Implementation of Boolean function of n
(c) 1 × 2n (d) 2n × 1, variables with a multiplexer that has n
UPPCL AE-16.11.2013 selection inputs for the total number of
minterms of
Ans. (d) : For n selection line
(a) 2n (b) 4n
size of mux = 2n : 1
(c) n2 (d) 2n
50. In combinational logic circuit shown in figure TNPSC AE-2014
has an output
Ans. (d) : Multiplexers (MUX)– It is a combinational
circuit that selects binary information from one of many
input lines and directs it to single output line.
The selection of a particular input line is controlled by a
set of selection lines. Generally there are 2n input lines
or number of minterms and 'n' selection lines whose bit
combinations determine which input is selected.
53. Match List-I with List-II as per the codes given Ans. (c) :
below:
List – I List - II
A. A digital circuit → 1. Active low
designed to keep
track of a number
of events
B. A group of flip flops → 2. Negation
used to store a 4-bit parallel adder
binary number A N- bit parallel adder requires 'n' full adder to perform
C. A circuit that will → 3. Register the operation.
invert a digital level 57. Which of the following circuits
D. An action occurs → 4. Counter converts/convert a binary number on the input
when the input is to a one-hot encoding at the output?
low 1. 3 to 8 binary decoder
A B C D 2. 8 to 3 binary decoder
(a) 4 3 2 1 3. Comparator
(b) 3 2 4 1 Select the correct answer using the code given
(c) 4 1 2 3 below.
(d) 1 2 3 4 (a) 1 only (b) 2 only
TNPSC AE-2014 (c) 3 only (d) 1, 2 and 3
Ans. (a) : IES - 2017
A digital circuit designed to keep track of a Ans. (a) :
number of events is called counter circuit.
Register is a group of flip flops used to store a
binary number.
Negation is a circuit that will invert a digital
level. It is also called the logical complement or
invert circuit.
Active low is an action occurs when the input is
low.
54. In a 4-stage BCD adder, the highest number
that can be added and maximum sum possible
respectively are One hot refers to a group of bits which is the legal
(a) (9, 9), 18 (b) (10, 9), 19 combinations of values a single high '1' bit and the other
(c) (9, 9), 19 (d) (10, 10), 20 all low '0'.
Nagaland PSC CTSE (Degree)-2016, Paper-II It is used for state machine indication.
Ans. (a) : In a 4-stage BCD adders highest number can So, it can find by using a 3 to 8 decoder.
be added 9 & 9 and maximum possible sum = (9 + 9) =
18. 58. If only one multiplexer and one inverter are
55. The size of PROM needed to implement a dual allowed to be used to implement any Boolean
8-to-1 multiplexer with common selection function of n variables, what is the maximum
inputs would be size of the multiplexer needed?
(a) 256 K x 2 (b) 512 K x 2 (a) 2n–2 line to 1 line (b) 2n–1 line to 1 line
(c) 1024 K x 2 (d) None of these (c) 2n+1 line to 1 line (d) 2n+2 line to 1 line
Mizoram PSC Jr. Grade -2018, Paper-II IES - 2017
Ans. (b) : No. of input = 8 + 8 + 3 = 19 No. of Ans. (b) : If only one multiplexer and one inverter are
output = 2 allowed to be used to implement any Boolean function
size of PROM = 219 × 2 of n variables maximum size of MUX required = 2n–
1
= 512 × k × 2 ×1
= 512 × 2 k 59. Consider the following statements with respect
56. The number of full adders in a 4-bit parallel to combinational circuit:
adder will be 1. The output at any time depends only on the
(a) two (b) three present combination of inputs.
(c) four (d) six 2. It does not employ storage elements.
RPCS Lect.-2011 3. It performs an operation that can be specified
Nagaland PSC CTSE- 2015, Paper-II logically by a set of Boolean functions.
Which of the above statement are correct? 62. For an n-bit binary adder, what is the number
(a) 1 and 2 only (b) 1 and 3 only of gates through which a carry has to
(c) 2 and 3 only (d) 1, 2 and 3 propagate from input to output?
IES - 2016 (a) n (b) 2n
Ans. (d) : Combinational circuit :- (c) n2 (d) n + 1
The output at any time depends only on the Present IES - 2016
combination of inputs. Ans. (b) : For an n-bit binary Adder the number of
It does not employ storage elements. gates through which a carry has to propagate from input
It performs an operation that can be specified to output is 2n.
logically by a set of Boolean functions. 63. The functionality implemented by the circuit
Example: Encoder, Decoder, Multiplexer, DE-Multiplexer below is
etc.
60. What are the two types of basic adder circuits?
(a) Half adder and full adder
(b) Half adder and parallel adder
(c) Asynchronous adder and synchronous adder
(d) One's complement adder and two's
complement adder.
IES - 2016
Ans. (a) : Half adder and full adder are the two types of
basic adder circuits.
(a) 2-to-1 multiplexer (b) 4-to-1 multiplexer

(c) 7-to-1 multiplexer (d) 6-to-1 multiplexer
GATE-2016, Set-I
S = AB + AB = A⊕B, C = AB
Ans. (b) :
C1 C0 O0 O1 O2 O3 Y
0 0 1 0 0 0 P
0 1 0 1 0 0 Q
1 0 0 0 1 0 R
sum, S = A BC + ABC + ABC + ABC =A⊕B⊕C 0 1 0 0 0 1 S
carry C = AB + BC + CA The two selection input C1 and C 0 of decoder are
61. Consider the following statements: handling 4 output. It will behave as 4 to 1 multiplexer.
1. An 8-input MUX can be used to implement 64. The Boolean function 'f' implemented as shown
any 4 variable functions. in the figure using two input multiplexers is
2. A 3-line to 8-line DEMUX can be used to
implement any 4 variable functions.
3. A 64-input MUX can be built using nine
8-input MUXs.
4. A 6-line to 64-line DEMUX can be built
using nine 3-line to 8-line DEMUXs.
Which of the above statements are correct? (a) A B C + ABC (b) ABC + A B C
(a) 1, 2, 3, and 4 (b) 1, 2 and 4 only (c) A BC + A B C (d) A B C + A B C
(c) 3 and 4 only (d) 1, 2 and 3 only
CGPSC SO 14.02.2016
IES – 2016,2004
IES - 2014
Ans. (c) :
Gate - 2005
• A 64- input MUX can be built using nine 8-input
MUXs- Ans. (a) :
 64  8 
=  = 8  +  = 1
 8  8 
= 8+1
=9
• A 6- line to 64-line DEMUX can be built using nine output of 1 stage E = BC + BC
st
3-line to 8-line DEMUXs. E = B⊕C

output of 2nd stage, f = E0 + E.A Truth Table :-
f = E.A B C Y
f= ( BC + BC ).A 0 0 I0 = A
f = ABC + ABC 0 1 I1 = A
65. An array multiplier is used to find the product 1 0 I2 = 1
of a 3 bit number with a 4 bit number. How 1 1 I3 = 0
many 4 bits adders are required to perform
multiplication? ` F(A,B,C) = BC.I0 + BC.I1 + BC.I 2 + BC.I3
(a) 1 (b) 2 = BCA + BCA + BC.1 + BC.0
(c) 3 (d) 4
IES - 2013 = ABC + A BC + BC(A + A) [A+ A = 1]
Ans. (b) : An array multiplexer is used to find the
product of a 3 bit number with a 4 bit number, then 2,4
bit adders are required to perform multiplication
because when we multiply 3 bit number with a 4 bit F(A,B,C) = ∑(1,2,4,6)
number then we get the result in greater than 4 bit.68. Consider the following statements :
66. A bus organized processor consists of `15 1. A multiplexer is analogous to a rotary
registers. The number of selection lines in each switch.
multiplexer and in the destination decoder are 2. A decoder is a combinational logic circuit
respectively: that converts binary information from 'n'
(a) 2 and 4 (b) 4 and 2 input lines to a maximum of 2n distinct
(c) 4 and 4 (d) 4 and 8 elements at the output.
IES - 20113. The Boolean expression for the output
Ans. (c) : A bus organized processor consists of 15 difference 'D' from a full subtractor is
registers the number of selection lines , n , then exactly the same as the output sum 'S' from
2n ≥ 15 a full adder.
2n 24 Which of the above statements is/are correct?
n 4 (a) 2 and 4 only (b) 4 only
(c) 1 and 3 only (d) 1, 2 and 3
In the destination decoder -
IES - 2010
Selection line = log 2 N = log 2 15 4
Ans. (c) : 1 and 3 only
67. A 4 ×1 MUX is used to implement a 3-input • A multiplexer is analogous to a rotary switch.
Boolean function as shown below. The Boolean • The boolean expression for the output difference
function F (A,B,C) implemented is 'D' from a full subtractor is exactly the same as the
output sum 'S' from a full Adder.
Full Adder :-
sum ,S = A⊕B⊕C
carry, C = AB + BC + CA
Full subtractor :-
Difference , D = A⊕B⊕C
Borrow B0 = AB + AC + BC
(a) F(A, B, C) = ∑ (1, 2, 4, 6) 69. Which of the following circuits come under the
class of combinational logic circuits?
(b) F(A, B, C) = ∑ (1, 2, 6) 1. Full adder 2. Full subtractor
(c) F(A, B, C) = ∑ (2, 4,5, 6) 3. Half adder 4. J-K flip-flop
5. Counter
(d) F(A, B, C) = ∑ (1,5, 6) Select the correct answer from the codes given
IES - 2010 below:
Ans. (a) : (a) 1 only (b) 3 and 4
(c) 4 and 5 (d) 1, 2 and 3
IES - 2009
Ans. (d) : A combinational logic circuit consists of
logic gate. In combinational circuit present output
depends on present input only, and no feedback is
present. In combinational no memory is present.

Ex. 1- Full adder, 2- Full subtractor, 3- Half adder Select the correct answer using the code given
Combinational circuit Sequential circuit below :
(a) 1, 3 and 4 (b) 2, 3 and 4
Half adder, Full adder, Half Flip-Flop, Counter and
subtractor, Full subtractor, shift register etc. (c) 1 and 2 only (d) 2 and 3 only
Multiplexer, Demultiplexer, IES – 2013, 2008
Encoder, Decoder etc. Ans. (c) : A digital multiplexer is a combinational logic
70. Consider a multiplexer with X and Y as data circuit which have many data input and single output
inputs and Z as control input. Z = 0 selects depending on select or control input, one of the input
line is transferred to the output so it is known as many
input X and Z = 1 selects input Y. What are the
to one switch, it is known as universal logic and data
connections required to realize the 2-variable
selecter.
Boolean function f = T + R, without using any
It is used to parallel to serial conversion.
additional hardware?
(a) R to X, 1 to Y, T to Z
(b) T to X, R to Y, T to Z
(c) T to X, R to Y, 0 to Z
(d) R to X, 0 to Y, T to Z
IES - 2009
Ans. (a) : According to question :- Y = output = S1S0 I0 + S1S0 I1 + S1S0 I 2 + S1S0 I3
73. When two 16-input multiplexers drive a 2-
input MUX, what is the result ?
(a) 2-input MUX (b) 4-input MUX
output = XZ + YZ ............(ii) (c) 16-input MUX (d) 32-input MUX
Q we need output IES - 2007
f = T+R Ans. (d) :
f = T+R (T+ T )
f = T(1+R)+R T
f = T+R T ..........(ii)
Q if we take X= R, Y = 1 and Z = T
Then, the mux output
X Z +YZ The total number of input is the 32-input MUX.
R T +1×T 74. Consider the following statements : For 3 input
variables a, b, c; A Boolean function y = ab +
T+ T R..........(iii) bc + ca represents
So the option (a) is correct. 1. a 3-input majority gate
71. With which decoder it is possible to obtain 2. a 3-input minority gate
many code conversions ? 3. carry output of a full adder
(a) 2 line to 4 line 4. product circuit for a, b and c
(b) 3 line to 8 line Which of the above statements are correct?
(c) not possible with any decoder (a) 1 and 4 only (b) 2 and 3 only
(d) 4 line to 16 line decoder (c) 1 and 3 only (d) 3 and 4 only
TNTRB AE– 2017, IES - 2009 IES – 2011, 2007
Ans. (d) : With 4 line to 16 line decoder it is possible to Ans. (c) : According to question
obtain many code conversion. A decoder that converts Variables a, b, c; Boolean
binary information from n input line to a maximum 2n y = ab + bc + ca represents
output line. 3 input majority gate, and carry output of full adder.
4×16 decoder A full adder is used to add 3 bits.
72. A digital multiplexer can be used for which of

the following ?
1. Parallel to serial conversion
2. Many-to-one switch sum = a⊕b⊕c
3. To generate memory chip select Carry == ab+bc+ca
4. For code conversion so correct answer is option (c) 1 and 3 only

75. Which one of the following statements is when V1 < V2 then output voltage goes to negative
correct? saturation voltage.
(a) Static 1 hazard may occur in a 2-level AND- So, the comparators output voltage either high or low.
OR gate network Hence, we can say that it is a 1-bit quantizer and used
(b) Static 0 hazard may occur in a 2-level AND- for conversion of analog to digital.
OR gate network 78. Consider the following statements :
(c) Dynamic hazards may occur in a 2-level OR- A 4 : 16 decoder can be constructed (with
AND gate network enable input) by :
(d) Essential hazards may occur in a 1. using four 2:4 decoders (each with an
combinational logic circuit. enable input) only.
IES - 2007 2. using five 2:4 decoders (each with an
Ans. (a) : Static 1 Hazards - It occurs in a two level enable input) only.
sum of product (SOP) implementation with AND-OR 3. using two 3:8 decoders (each with an
enable input) only.
gate network.
4. using two 3:8 decoders (each with an
Static 0 Hazards - It occurs in a two level product of enable input) and one inverter.
sum (POS) implementation with OR-AND gate Which of the statements given above is/are
correct ?
network. (a) 2 and 3 (b) 1 only
Dynamic Hazards - Dynamic Hazard occurs only in (c) 2 and 4 (d) None of the above
multilevel circuits where the output must make a IES - 2005
Ans. (c) : Decoder 4 : 16 can be constructed by
transition from 0 to 1 or 1 to 0.
• 2 : 4 decoder
Essential Hazards - It occurs in asynchronous  16  4 
sequential circuit and it caused by unequal delays along  = 4  +  = 1
 4  4 
two or more paths that originate from an equivalent
input. Essential hazards cannot be corrected by adding =4+1=5
redundant gates as in static hazards. So, Using five, 2:4 decoders
76. What is the number of select lines required in a
single input n-output demultiplexer ?
(a) 2 (b) n
(c) 2n (d) log2 n
IES - 2006
Ans. (d) : We know that, in Demultiplexer -
2m = n
Taken logarithm in both side
log 2 2 m = log 2 n
m = log 2n
77. How can the voltage comparator shown in the
circuit given below be used in the analog-to-
digital conversion ? • 3 : 8 decoder
16
=2
8
So, Using two, 3 : 8 decoders
(a) As a 1-bit quantizer (b) As a 2-bit quantizer

(c) As a 4-bit quantizer (d) As a 8-bit quantizer
IES - 2006
Ans. (a) :
Output voltage V0 = A ( V1 − V2 )
when V1 > V2 then output voltage goes to positive
saturation voltage.

79. What is the output f(x, y) of the multiplexer Ans. (c) : A full adder can be constructed using two half
resulting from the input logical values ? adder and an OR gate.
1 Full Adder = 2H.A. +1 OR Gate

(a) An EXOR gate (b) A NOR gate
• Two four bit parallel adders can be cascaded to
(c) An AND gate (d) A NAND gate construct 8-bit parallel adder.
IES - 2005 • Ripple carry adder is a combinational logic circuit.
Ans. (a) : According to question the output value. It is used for the purpose of adding two n-bit binary
in mux.4×1 numbers. In ripple carry adder, the addition time
f = XY.0+XY×1+XY×1+XY.0 depends upon the number of bits. It is also known
as n bit parallel adder.
f =0 + XY + XY + 0
• Carry look-ahead reduces the propagation delay so,
f = XY + XY = X ⊕ Y it speed up the addition process and it gets more
So this is an EXOR gate. complicated as the number of bits increase.
80. A 1-bit full adder takes 20 ns to generate carry- 82. Consider the following statements :
out bit and 40 ns for the sum bit. What is the A half-adder
maximum rate of addition per second when 1. is a half-subtractor also.
four 1-bit full adders are cascaded ? 2. has two outputs CH = x.y and SH = x ⊕ y
(a) 107 (b) 1.25 × 107 for the two inputs x and y.
(c) 6.25 × 10 6
(d) 105 3. has two outputs CH = x + y and SH = x ⊕ y
IES - 2005 for two inputs x and y.
Ans. (a) : Let the binary output to be added be (A4 A3 4. is a combinational circuit.
A2 A1) and (B4 B3 B2 B1). A four bit adder using cascade Which of the statements given above is/are
connection .four 1 bit full adder as shown below here, correct ?
(represented carry & represented for sum) (a) 1, 3 and 4 (b) 1, 2 and 4
KVS TGT (WE)-2018
IES - 2005
Ans. (b) : According to question in half adder
40ns 40+20 40+40 40+60

=40 =60 =80 =100 S = A⊕B
It is clear the above circuit each addition requires 100 C = AB
ns.
Therefore maximum rate of addition that can be where S = Substractor
performed by this 4 bit adder B = Borrow
S = A⊕B
1 109
= B = AB
100ns 100
A half adder is also half substractor because its sum and
= 107 addition /sec.
substractor is same
81. Which one of the following statements is not Both half adder and half substractor is a combinational
correct ? circuit.
(a) A full adder can be constructed using two
83. Consider the following circuit:
half-adders and an OR gate.
(b) Two four bit parallel adders can be cascaded
to construct 8-bit parallel adder.
(c) Ripple carry adder has addition time
independent of the number of bits.
(d) Carry look ahead is used to speed up the
parallel addition.
IES - 2005
In the above TTL circuit, S2 to S0 are select IES - 2002
lines and X7 to X0 are input lines. S0 and X0 are Ans. (a) : The combinational logic circuit depend on
LSBs. What is the output Y? only present input
(a) Indeterminable (b) A ⊕ B EXAMPLE - MUX, ROMs
(c) A ⊕ B (d) C ⊕ B ⊕ A • ROMs are built using decoder and Encoders, so
IES - 2004 ROM is combinational circuit.
Ans. (a) : In the given circuit, one input of OR gate is • D- latch is a sequential logic circuit .
open in TTL logic is equivalent to connecting it to logic • Given circuit is a sequential circuit because it's
output depends on present input and past output
both.
Y = S0 S1S2 X 0 + S0 S1S2 X1 + S0S1S2 X 2 + S0S1S2 X 3 86. The number of 4-line-to-16-line decoders
required to make an 8-line-to-256-line decoder
+S0 S1S2 X 4 + S0 S1S2 X 5 + S0S1S2 X 6 + S0S1S2 X 7 is
Y= S0 S1S2 .1 + 0 + 0 + S0S1S2 .1 + 0 + S0 S1S2 .1 + S0S1S2 .1 + 0 (a) 16 (b) 17
( )
(c) 32 (d) 64
Y = A B C + D + AB ( C + D ) + AB ( C + D ) Mizoram PSC IOLM -2018, Paper II
(
+ AB C + D ) IES - 2001
Ans. (b) : NO. of decoders (4×16) decoders required
( )
Y = C + D ( A B + AB ) + ( C + D ) ( AB + AB ) realizing 8 line to 256 line decoder is
256 16
Y = ( C + D )( A ⊕ B ) + ( C + D )( A ⊕ B ) = +
16 16
Let x = (C + D), y = A ⊕ B =16+1
= 17
Then, x ⊕ y = x ⊙ y = x y + xy
87. The circuit shown in the given figure is
Hence, Y = ( C + D ) ⊕ ( A ⊕ B )
84. The addition of two binary variables A and B
results into a SUM and a CARRY output.
Consider the following expressions for the
SUM and CARRY outputs.
1. SUM = A.B + A.B 2. SUM = A.B + A.B
3. CARRY = A.B 4. CARRY = A + B
Which of these expressions are correct?
(a) 1 and 3 (b) 2 and 3
(a) an adder circuit
(c) 2 and 4 (d) 1 and 4
(b) a substractor circuit
IES - 2003
(c) a comparator circuit
Ans. (b) : Truth table of SUM and CARRY (d) a parity generator circuit
SUM = AB + AB IES – 2001, 1995
CARRY = A.B Ans. (c) : A comparator is a circuit, which compares the
A B Sum = AB + AB CARRY = A.B two inputs that are applied to it and produces an output
0 0 0 0 and the comparator output indicates which one of the
input is greater or lesser.
0 1 1 0
1 0 1 0
1 1 0 1
85. Consider the following digital circuits :
1. Multiplexers
2. Read Only Memories
3. D-latch
4. Circuit as shown
According to given circuit
Z1 = X + Y = X.Y = XY
Which of these come under the class of Z2 = (X + Y) + (X + Y) = X.Y + X.Y
combinational circuits? = XY + X.Y
(a) 1 and 2 (b) 3 and 4
(c) 1, 2 and 3 (d) 1, 2, 3 and 4 Z3 = X + Y = X.Y

According to comparator rule.
(1) X > Y
(2) X = Y sum = A⊕B⊕C
(3) X < Y carry out = AB + BC + CA
for Z1 = X Y 90. The half-adder circuit in the given Figure has
X=1Y=0 inputs AB = 11
X Y = 1× 0 =1
for Z2 = XY+ X Y
X=Y=1
1 ×1+ 1 . 1
=1+0 The logic level of P and Q outputs will be
=1 (a) P = 0 and Q = 0 (b) P = 0 and Q = 1
For Z3, A = 0 B = 1 (c) P = 1 and Q = 0 (d) P = 1 and Q = 1
= XY IES - 2000
Ans. (b) : Half adder is used to add two bits and gives
= 0 .1 two output sum and carry.
= 1.1 According to given circuit and given A, B = 1
=1 Q P = sum (A⊕B)
According to this selection this is a comparator circuit. Q = carry (AB)
88. The control logic for a binary multiplier is
sum (P) = A B + A B
specified by a state diagram. The state diagram
has four states and two inputs. To implement it = 1. 1 + 1 .1
by the sequence register arid decoder method = 1.0+0.1
(a) two flip-flops and 2 × 4 decoders are needed =0
(b) four flips-flops and 2 × 4 decoders are needed carry = A.B
(c) two flip-flops and 3 × 9 decoders are needed = 1.1
(d) four flip-flops and 3 × 9 decoders are needed =1
IES - 2001 so P = 0 and Q = 1
Ans. (a) : Given, 4 states and input = 2 91. Match List-I (Circuits) with List-II (Types of
Then, integration level) and select the correct answer
∵ 2n = 4
List-I List-II
2n = 22
A. Full adder 1. VLSI
n=2 B. Magnitude comparator 2. SSI
∴ 2 flip flops are required C. Programmable logic array 3. MSI
m = 2 Input Codes:
So, We need A B C
= m × 2n (a) 2 3 1
= 2 × 22 (b) 3 2 1
= 2 × 4 decoder (c) 1 3 2
89. Which one of the following statements correctly (d) 2 1 3
defines the full-adder? IES - 1999
An adder circuit Ans. (b) : Full Adder- Full adder is a combinational
(a) having two inputs used to add two binary logic circuit . The full adder has a three input and two
digits. It produces their sum and carry as output .Full adder is a medium scale integration (MSI)
outputs. circuit.
(b) having three inputs used to add two binary • Magnitude comparator is a combinational circuit that
digits plus a carry. It produces their sum and compares two binary numbers and check for three
carry as outputs. condition i.e. equal, less than or greater than.
(c) used in the least significant position when 1 - A<B
adding two binary digits with no carry-in to 2- A>B
consider. It produces their sum and carry as 3- A=B
outputs.
• Magnitude comparator circuit is a small scale
(d) having two inputs and two outputs. integration (SSI).
UPRVUNL AE-2016, IES - 2000 • A programmable logic array is a kind of
Ans. (b) : Full adder is a combinational logic circuit, it programmable logic device used to implement
is used to add three bits and we get two output as sum combinational logic circuit. Programmable logic
and carry. array is a very large scale integration (VLSI) circuit .

92. The circuit shown in the given figure is a
(a) AB + BC + CA + BC
(a) Full adder (b) Full subtractor (b) A ⊕ B ⊕ C
(c) Shift register (d) Decade counter (c) A ⊕ B
IES - 1998 (d) ABC + ABC + ABC + ABC
Ans. (b) : According to given question , IES - 1997
D = A⊕(B⊕C) ––––––(i) Ans. (b&d) :
E = A ( B⊕C) + BC
E = A ( B C + B C) + BC
E = A B C + A B C+ BC(A+ A )
E = ABC + A BC + ABC + ABC
E = C ( AB + AB ) + AB ( C + C )
= This circuit is a 4×1 MUX
E = C ( A ⊙ B ) + AB
The output F = S1 S0 I0 + S1S0 I1 + S1 S0 I2 + S1S2 I3
( )
E = C A ⊕ B + AB ....... (ii)
F = A BC + ABC + ABC + ABC
According to above answer .
F = A ( BC + BC ) + A ( BC + BC )
D is a Difference and E is a Barrow of full substractor.
so answer is a full substractor F = A ( B ⊕ C) + A ( B ⊙ C)
( )
93. The function 'F' implemented by the
multiplexer chip shown in the figure is : F = A ( B ⊕ C) + A B ⊕ C (B ⊙ C = B ⊕ C)
F = A⊕ B⊕C
95.Which one of the following statements is
correct?
(a) In serial adder, if d and D, respectively, are
the full adder and flip-flop delay, then the
time required to perform n bit addition is
[n(d + D)]
(b) Maximum delay in n bit parallel adder is 'nd',
where d is delay of full adder
(a) A (b) B (c) If d is the delay of two-level circuit, then the
(c) AB (d) AB + AB total delay of a carry look ahead adder is only
3d.
IES - 1998
(d) Delay of D flip flop is always less than T flip
Ans. (b) :This is a 4× 1 MUX flop.
IES - 1996
Ans. (b) : Delay in n-bit binary parallel adder :
Output F= S1 S 0 I 0 + S1 S0 I1 + S1 S 0 I2 + S1S2 I3
Put the value of I0,I1,I2,I3 and S1,S0
TS = ( N − 1) t C + max(t c , t s )
= A B.0 + A B.1+A B .0+AB.1
F = A B+AB TC = Nt C
= B( A +A) Where, TS = Delay for N - bit (SUM)
=B TC = Delay for N- bit (CARRY)
94. The output 'F' of the multiplexer circuit shown tS = Delay for each FA (SUM)
in the figure will be tC = Delay for each FA (CARRY)
for N = 4 (c) Input combination at that time and the
TS = 3t C + t C previous input combination
(d) Present output and the previous output
TC = 4t C Nagaland PSC- 2018, Diploma Paper-II
So, maximum delay in n-bit parallel adder is nd. IES - 1994
96. A full-adder can be implemented with half- Ans. (a) : Combinational circuit consist of input
adders and OR gates. A 4-bit parallel full variable logic gates and output variables as shown . The
adder without any initial carry requires input and output are two values. The values of output
(a) 8 half-adders. 4-OR gates variables depend only on the present values of the
(b) Three bit parity checker inputs. The output does not depend on the previous
(c) 7 half-adders, 4-OR gates output
(d) 7 half-adders, 3-OR gates
IES - 1994
Ans. (d) : let's assume 4 bit binary
Full adder = (2n – 1) half adder + (n – 1) OR Gate 99. A carry look ahead adder is frequently used for
addition because it
= (2 × 4 –1) half adder + (4 – 1) OR Gate
(a) Is faster (b) Is more accurate
4 bit → 7 half-adder +3 OR Gate
(c) Used fewer gates (d) Costs less
97. Which one of the following will give the sum of
full-adder as output? Nagaland PSC - 2018, Diploma (Paper-II)
(a) Three input majority circuit IES - 1993
(b) Three bit parity checker Ans. (a) : A carry look ahead adder (CLA) or fast adder
(c) Three bit comparator is a type of electronics adder used in digital logic.
(d) Three bit counter A CLA Improves speed by reducing the amount of time
IES - 1994 required to determine carry bits.
Ans. (b) : Three bit odd parity checker gives the sum of 100. A 4-line-to-1-line multiplexer shown in figure-I
full adder as output. (the same as per IEEE convention is shown in
figure-II) is fed with three logic inputs A, B and
X Y Z ODD Parity C as shown. The output of the multiplexer will
0 0 0 0 be
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1 (a) ∑ m(0,1, 2, 4) (b) ∑ m(0,3,5, 7)
(c) ∑ m(3,5, 6, 7) (d) ∑ m(1, 2,5, 6)
IES - 1993
Ans. (c) : Output f = S1 S 0 I0 + S1 S0 I1 + S1 S 0 I2 + S1S0 I3
in this question selector line are B and C
S0 = B, S1 = C
F = XYZ + XYZ + XYZ + XYZ Input , I0 = 0, I1= A, I2 = A, I3 = 1
= X ( YZ + YZ ) + X ( YZ + YZ ) S0S1 value put in Output
= X ( Y ⊕ Z) + X (Y Z) f = BC.0 + BCA + BCA + BC.1
= X ( Y ⊕ Z) + X ( Y ⊕ Z) = 0 + ABC + ABC + BC(A + A) { A + A = 1}
= X⊕Y⊕Z = ABC+ABC+ABC+ABC
= sum of full adder = ∑m (3,5,6,7)
98. A Combinational circuit is one in which the 101. The output f(x, y) of the multiplexer shown in
output depends on the figure-I (the same as per IEEE convention is
(a) Input combination at that time shown in figure-II resulting from the input
(b) Input combination and the previous output logical values is
Ans. (a) : High = 1, Low = 0
output = S1 S 0 (X1 ) + S 0 S1 (X 2 ) + S0 S1 (X 3 ) + S1S2 (X 4 )
→ X1,X2,X3 are high and X4 are low
= S1 S 0 (.1) + S 0 S1 (1) + S0 S1 (1) + S1S2 (0)
= S1 S 0 + S 0 S1 + S0 S1 {A+ A =1}
= S 0 (S1 + S1 ) + S0 S1
(a) An EXOR gate (b) A NOR gate
(c) An AND gate (d) A NAND gate = S 0 + S0 S1
IES - 1993 = ( S + S )( S + S )
0 0 0 1
Ans. (a) :
= S0S1
output f = XY(0)+XY(1) + XY(1)+XY(0)
NAND Gate
f = XY + XY 104. How is the operation dependent on A and B?
f = X ⊕Y
An EXOR Gate
answer using the codes given below the lists :
List-I List-II (a) HI for A and B is LO
A. Multiplexer 1. Sequential memory (b) Independent of A and B
B. Shift – Register 2. Converts decimal (c) LO for A and B is HI
number to binary (d) HI for A or B is LO
C. Encoder 3. Data selector IES - 1991
Codes : Ans. (b) :
A B C
(a) 1 2 3
(b) 2 3 1
(c) 3 1 2 1st mux output
(d) 1 2 2
IES - 1992 = A × 1 + A.1
Ans. (c) : Multiplexer - Data selector
= A + A = 1(high)
Shift Register - Sequential memory
Encoder - Converts decimal number to binary second mux output
Multiplexer :- A multiplexer is used if a complex logic = B × 1 + B.1
circuit is to be shorted by a number of input signals that = B+B
is any one of the input can be selected to appear as the = 1(high)
output. first MUX both input are high, output will be high and
Shift Register :- A shift register is a sequential memory independent of 'A'
in which information is shifted one position at a time second MUX both input are high, output will be high
when one clock pulse is applied. and independent of 'B'
Encoder :- The encoder converts dominate input to a 105. The circuit shown in the figure has 4 boxes
coded binary. each described by inputs P, Q, R and outputs
103. In the figure shown Y, Z with Y = P ⊕ Q ⊕ R Z = RQ + PR + QP
X1 High X2 High
X3 High X4 Low The circuit acts as a
S1 and S0 are control inputs. (a) 4 bit adder giving P + Q
This multiplexer is equivalent to (b) 4 bit subtractor giving P - Q
(a) NAND gate (b) AND gate (c) 4 bit subtractor giving Q - P
(c) OR gate (d) EXNOR gate (d) 4 bit adder giving P + Q + R
IES - 1991 GATE - 2003
Ans. (b) : Let, The output Z can be represented by
P = 1101 (a) PQ + PQS + QRS
Q = 1001 (b) PQ + PQR + PQS
yn = Pn⊕Qn⊕Rn
(c) PQR + PQR + PQRS + QRS
Z = RnQn+ Pn R n + Q n Pn
(d) PQR + PQRS + PQRS + QRS
constructing truth table
GATE - 2008
Pn Qn Rn Zn Yn
Ans. (a) : I3 = P, I2 = PQ, I1 = P, I0 = (P+ Q )
1 1 0 0 0
output Z = R SI0 + RSI1 + RS I 2 + R SI3
1 0 0 0 1
= R S (P + Q) + R SP + R SP Q + R SP
0 0 0 0 0
= RSP + RSQ + RSP + RSPQ + RSP
1 1 0 0 0
So that, Rn+1 = Zn using k-map
Z4 = Rs (MSB)
Hence output is 0100 which shows that it is 4 bit
subtractor giving P – Q
y = P⊕Q⊕R
106. The output Y of a 2-bit comparator is logic 1
whenever the 2-bit input A is greater than the
2-bit input B. The number of combinations for
which of the output is logic 1 is: Z = PQ+P Q S+ Q R S
(a) 4 (b) 6 109. The Boolean function realized by the logic
(c) 8 (d) 10 circuit shown is
Ans. (b) : The only possible combinations for 2-bit
comparator for which logic is 1 when 2-bit input A is
22n − 2n
greater than 2-bit input is-
2
Where n = number of bit
24 − 22 12
A>B = = =6
2 2
So, there are only 6 combinations. (a) F = Σm(0, 1, 3, 5, 9, 10, 14)
107. The minimum number of 2-to-1 multiplexers (b) F = Σm(2, 3, 5, 7, 8, 12, 13)
required to realize a 4-to-1 multiplexer is (c) F = Σm(1, 2, 4, 5, 11, 14, 15)
(a) 1 (b) 2 (d) F = Σm(2, 3, 5, 7, 8, 9, 12)
(c) 3 (d) 4 TSTRANSCO AE- 2018
Nagaland PSC (Degree) 2018, Paper-II GATE - 2010
UPRVUNL AE-11.06.2014 Ans. (d) : I = C, I = D, I = C, I = C.D
0 1 2 3
GATE - 2004
Ans. (c) : 4×1 MUX making by 2×1 mux F = S1S0 I0 + S1S0 I1 + S1S0 I 2 + S1S0 I3
4  2  = S1S0C + S1S0 D + S1S0C + S1S0 ( C D )
 = 2  +  = 1
2  2  = ABC + ABD + ABC + ABC D
= 2+1
= ABCD + ABCD + ABCD + ABCD + ABCD
=3
+ ABCD + ABCD
108. For the circuit shown in the following figure,
I0-I3 are inputs to the 4 : 1 multiplexer, R(MSB) F = ∑ m ( 2,3,5,7,8,9,12 )
and S are control bits. 110. The logic function implemented by the circuit
below is (ground implies a logic '0')

(a) F = AND (P, Q) (b) F = OR (P, Q)
(c) F = XNOR(P, Q) (d) F = XOR (P, Q)
GATE - 2011
Ans. (d) :
output f = S1 S0 I0 + S1S0 I1 + S1S0 I 2 + S0S1I3

F = P Q (0) + P Q (1) + P Q (1) + P Q (0)
F = PQ+ PQ
F = P⊕Q GATE - 2014, Set-III
F = XOR(P,Q) Ans. (a) : In Half subtractor :
Difference - X⊕Y
111. In the circuit shown, W and Y are MSBs of the
Borrow - XY
control inputs. The output MSBs is given by
option (a) correct ,
(a) F = WX + WX + YZ
(b) F = WX + WX + YZ
output , D
(c) F = WXY + WXY
D = X I0 + XI1
(d) F = (W + X)YZ
D = XY + XY
GATE - 2014, Set-III D = X⊕Y
Ans. (c) : Ground input = 0, I0 = I3 = 0 output B = XI0 + XI1
Vcc→ input = 1, I1= I2 = 1 B = XY + 0
MUX 1 :-
B = XY
output Q = W XI0 + W X I1 + W X I 2 + W X I3 113. An 8-to-1 multiplexer is used to implement a
logical function Y as shown in the figure. The
Q = WX + WX output
MUX 2 :- input I2 = I3 = 0 , I0 = I1 = Q
Output F = Y Z I0 + Y Z I1 + YZ I 2 + Y Z I3
F = WXYZ+ WXYZ+ WXYZ+ WXYZ
F = WXYZ+ WXYZ+ WXYZ+ WXYZ
F = W X Y(Z + Z) + W X Y (Z + Z)
F = WXY+ WXY
112. If X and Y are inputs and the Difference (D =
(X - Y) and the Borrow (B) are the outputs, (a) Y = ABC + ACD (b) Y = ABC + ABD
which one of the following diagrams (c) Y = ABC + ACD (d) ABD + ABC
implements a half-subtractor ? GATE - 2014, Set-IV
Ans. (c) : Ans. (d) : A 1 to 8 demultiplexer with data input Din,
Output Y = S2 S1 S0 I0 + S2 S1S0 I1 + S2S1S0 I2 + S2S1S0 I3 address input S0, S1, S2 (with S as the LSB) and Y0 to
Y7 as the eight demultiplexer output is to be designed
+S2 S1S0 I 4 + S2 S1S0 I5 + S2S1S0 I6 + S2S1S0 I7 using 2 to 4 decoder (with enable input E and address
Put the value, I0, I2, I4, I5, I7 = 0 input A0 and A1.
I1 I3 = D
I6 = 1
y = A BC D + A BCD + A BC
y = A CD ( B +B) +A B C
y = A CD + A BC
114. Which of the following statements about the
arithmetic circuit is INCORRECT?
(a) A half-subtractor is an arithmetic circuit that The LSB of D-Mux should be mapped to address lines
subtracts one binary digit from another of the decoder
(b) A half-adder is an arithmetic circuit that adds R → S0
to binary digits and S → S1
(c) A full adder is an arithmetic circuit that adds input to both decoder should be same so
one binary digit and a carry i.e, 3 bits P → Din
(d) A full-subtractor is an arithmetic circuit that NOT Gate along with OR Gate in case to select one
subtracts one binary digit from another decoder at a time so Q → S2
considering a borrow P → Din
DFCCIL Executive S&T 29.09.2021, 12:30 to 2:30PM Q → S2
Ans. (c) : Half Adder- A logic circuit for the addition R → S0
of two one bit number is referred to as a Half Adder. S → S1
Full Adder- It Performs the arithmetic sum of the three 116. A, B and Cin are the three inputs of a full adder
input bits i.e. addend bit, augend bit and carry bit. circuit and D0, D1, ….., D7 are the inputs of 8 :1
Half subtractor (H.S) - The half subtractor is a multiplexer. S2 (MSB), S1 and S0 (LSB) are the
combinational circuit which is used to perform selection lines of the multiplexer. To implement
subtraction of two bit. It has Input, minuend and the expression of sum of full adder circuit using
Subtrahend and two output the difference and borrow this multiplexer, the connections of the input
output. ports and selection lines are
115. A 1-to-8 demultiplexer with data input Din, (a) D0 = D3 = D5=D6 = D0, = D2=D4 = D7 = 1, S2
address inputs S0, S1, S2 (with S0 as the LSB) = A, S1 = B and S0 = Cin
and Y0 to Y7 as the eight demultiplexed (b) D0 = D3 = D5 = D6 = 1, D1 = D2 = D4 = D7 =
0, S2 = Cin, S1 = B and S0 = A
outputs, is to be designed using two 2-to-4
(c) D0 = D2 = D3 = D6 = 0, D1 = D4 = D5 = D7 =
decoders (with enable input E and address
1, S2 =A, S1 = B and S0 = Cin
inputs A0 and A1) as shown in the figure Din,
S0,S1 and S2 are to be connected to P, Q, R and (d) D0 = D1 = D5 = D7 = 1, D2 = D3 = D4 = D6 =
S, but not necessarily in this order. The 0, S2 = Cin, S1 = B and S0 = A
respective input connections to P, Q, R and S ESE-2022
terminals should be Ans. (a) : Full adder input - A, B and C in
Multiplexer input - D0, D1, ……..D7
Input Sum
A B Cin 0
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
(a) S2, Din, S0, S1 (b) S1, Din, S0, S2
1 1 0 0
(c) Din, S0, S1,S2, (d) Din, S2,S0, S1
GATE - 2015, Set-II 1 1 1 1

S = ∑ m(1, 2,4,7) SUM = ∑ m (1,2,4,7 )
Cout = AB + ABCin + ABCin ................. (i)

Given that - S1 = A & S0 = B
then the output
Y = ABI0 + ABI1 + ABI 2 + ABI3 ......... (ii)
So that, after comparing equation (i) & (ii) we find
D0 = D3 = D5 = D6 = 0 I0 = 0, I1 = Cin , I 2 = Cin , I3 = 1
D1 = D2 = D4 = D7 = 1
S2 = A1 , S1 = B and S0 = Cin 118. Consider the circuit shown in the figure.
117. A 4:1 multiplexer is to be used for generating
the output carry of a full adder. A and B are
the bits to be added while Cin is the input carry
and Cout is the output carry. A and B are to be
used as the select bits with A being the more
significant select bit.
The Boolean expression F implemented by the
circuit is
(a) XYZ + XY + YZ
(b) XYZ + XZ + YZ
(c) XYZ + XY + YZ
(d) XYZ + XZ + YZ
Which one of the following statements correctly GATE - 2017, Set-II
describes the choice of signals to be connected Ans. (b)
to the inputs I0, I1, I2 and I3 so that the output is
Cout ?
(a) I0 = 0, I1 = Cin , I 2 = Cin and I3 = 1
(b) I0 = 1, I1 = Cin, I2 = Cin and I3 = 1
(c) I0 = Cin, I1 = 0, I2 = 1 and I3 = Cin
(d) I0 = 0, I1 = Cin, I2 = 1 and I3 = Cin
GATE - 2016 , Set-II output P = X Y + X0
Ans. (a) : P= XY
Output equation is :- P = X.Y = X + Y = X + Y
Y = S1S0 I0 + S1S0 I1 + S1S0 I 2 + S1S0 I3 output F = ZP + ZP
Truth table of full adder
F = Z X Y + Z(X + Y)
A B Cin SUM CARRY
F = XYZ + XZ + YZ
0 0 0 0 0
119. A four-variable Boolean function is realized
0 0 1 1 → 0
using 4 × 1 multiplexers as shown in the figure.
0 1 0 1 → 0
0 1 1 0 1
1 0 0 1 → 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 → 1
CARRY = ∑ m ( 3,5,6,7 ) The minimized expression for F(U, V, W, X) is

(a) (UV + UV)W (a) Demultiplexer (b) Encoder
(c) Multiplier (d) Decoder
(b) (UV + UV)(WX + WX)
(c) (UV + UV)W Mizoram PSC Jr. Grade-2015, Paper-II
(d) (UV + UV)(WX + WX) Ans. (a) : Demultiplexer - A combinational logic
circuit which is used to send data coming from a source
GATE - 2018 to two or more separate destination is called as
Ans. (c) : demultiplexer. But the output will be same.
MUX 1 :- 122. If A and B are two inputs of the 2-bit adder

P = U V I0 + U V I1 + U V I 2 + U V I3 then it can be used for subtraction by
(a) Inverting the output
P = UV + UV
(b) Inverting the carry-in
MUX 2 :- output
(c) Inverting the B input
F = W X P + WXP + WX0+ W X0 (d) Grounding the B input
= W P(X + X) Punjab PSC Poly. Lect. 20.08.2017
Ans. (c) : In order to transform a normal adder into a
= WP subtractor, we need to invert the second operand (B)
F = W(UV + UV) and add 1 [by setting Cin = 1, when control m = High
(1)].
120. The figure below shows a multiplexer where S1
and S0 are the select lines. I0 to I3 are the input
data lines, EN is the enable line, and F(P, Q, R)
is the output. F is
The input carry Cin must be equal to 1 when subtraction

is performed.
A=A
B=B
Cin = 1
123. To implement n-bit parallel adder requires
(a) Q + PR (b) P + QR ______ full adders
(c) PQ + QR (d) PQR + PQ (a) n (b) n − 1
GATE - 2020 (c) n + 1 (d) none
Ans. (c) : Output F = P Q I0 + P Q I1 + P Q I2 + P Q I3
Ans. (a) : A n-bit parallel adder requires n full adders to
F = P Q R + P Q (0) + P Q R + P Q (1) perform the operation. Parallel adders normally
incorporate carry look ahead logic to ensure that carry
F = P QR + PQR + PQ propagation between subsequent stages of addition does
F = Q R (P + P) + P Q not limit addition speed.
124. Multiplexer can be named as
F = QR + PQ (a) Data Selector
(b) One to many circuit
121. A combinational logic circuit which is used to (c) Serial to parallel converter
send data coming from a source to two or more (d) None
separate destinations is called as TSPSC Manager (Engg.) - 2015
Ans. (a) : Multiplexer named as data selector, many to 129. A full subtractor can be constructed from two
one circuit and parallel to adder converter etc. half subtractors and a
(a) 2-input NAND gate (b) 2-input NOR gate
(c) 2-input OR gate (d) 2-input AND gate
IES - 2013
Ans. (c) : Two Half Subtractors and one OR gate is
required to implement a full substractor.
125. How many data inputs are there in a decoder
having 64 output lines?
(a) 1 (b) 64
(c) 6 (d) 12
TNPSC AE- 2019
Ans. (c) : A decoder have many inputs and many
outputs. It is combinational logic circuit that converts 130. A full adder circuit is constructed from two 2
binary information from ‘n’ bit input lines to a input Ex OR gates, two 2-input AND gate and a
maximum 2n unique output lines such that only one (a) 2-input OR gate (b) input Ex-NOR gate
output line is activated for each one of possible (c) 2-input AND gate (d) 2 input NAND gate
combinations of input. Nagaland PSC- 2018, Diploma Paper-II
Input lines = n Ans. (a) : A full adder can be implement by using two
Output lines (m) = 2n 2-input EX-OR gates, two 2-input AND gates and one
64 = 2n 2-input OR gate.
26 =2n
n=6
126. The expression for sum of A and B in the half
adder is given by
(a) AB (b) A + B
(c) A ⊕ B (d) AB
Nagaland PSC- 2018, Diploma Paper-II SUM = Cin ⊕ A ⊕ B
Ans. (c) : For Half adder Cout = AB + Cin ( A ⊕ B)
131. A binary to decimal decoder is called 1 of 10
decoder because
(a) at a time one input is high
(b) Output is high only if all inputs are high
(c) Only one of its output lines is high at a time
S= A⊕B (d) It has 10 output lines
127. A Decoder combinational circuit is nothing but Nagaland PSC- 2018, Diploma Paper-II
a Demultiplexer without Ans. (d) : It is also known as BCD to decimal
(a) control inputs (b) data inputs converter.
(c) enable inputs (d) none of these A binary to decimal decoder is called 1 of 10 decoder
Nagaland PSC- 2018, Diploma Paper-II because it has 10 output lines. It accept an input value
consisting of binary coded decimal integer value and
Ans. (c) : The decoder is a combinational circuit which active one specific.
can accept many inputs and generate the decoded A binary to decimal decoder applied to the four inputs,
output. The de-multiplexer has selection lines to allow results in a high level at the selected one of 10 decimal
the input to follow one of the selected paths for decoded outputs.
generating it at the output.
Decoder combinational circuit is a de-multiplexer
without enable inputs or selection lines.
128. A multiplexer combinational circuit has n data
input, m control inputs and one output, then
(a) 2m = n (b) 2n = m
n
(c) m = 2 (d) n2 = m
Ans. (b) : No. of data input = n 132. A 7477 decoder drives
No. of control input = m (a) Seven segment display(b) Relays
(c) Diode matrix (d) Nixie tube
then m = 2 n Nagaland PSC- 2018, Diploma Paper-II
Ans. (a) : A 7477 decoder drives seven segment Initially test signal was at logic Low.
display. It is a BCD code decoder to 7 segment display. ⇒ x = 0, y = 1
133. In the full adder, denoting sum by S and carry
by C. output(f ) = x.y = 1
(a) S = 1 when two or more inputs are unity. Initially output was HIGH
(b) C = 1 when two or more inputs are unity. Let assume test signal is switched to logic at t = 0 msec.
(c) C = 1 when all the inputs are unity. x=1
(d) S = 1 when all the inputs are unity. As there are three NOT gates, the delay of signal to
Nagaland PSC- 2018, Diploma Paper-II reach y input is 3t0 msec.
Ans. (b) : In full adder - At, t=2t msec, y=0 ⇒ remains as before
Sum S = A ⊕ B ⊕ C
f = xy = 1
Carry = AB + C (A ⊕ B) Carry will be one
when two or more input are one. NAND gate also has delay of t0 msec.
134. A 4 to 1 multiplexer to realize a Boolean AT, t=4t0 msec, f becomes high
function F(X,Y,Z) is shown in the figure below.
The inputs Y and Z are connected to the
selectors of the MUX (Y is more significant).
The canonical sum of product expression for
F(X,Y,Z) is:
At, t=0 msec, x=1, y=1

At, t=100 msec.
f= xy = 0
(a) ∑ m(2,3, 4, 7) (b) ∑ m(1,3,5, 7)
Output pulses from High → Low → High
(c) ∑ m(0, 2, 4, 6) (d) ∑ m(2,3,5, 6)
OPSC Poly. Lect. (Instrumentation)-2018, Paper-I At, o < t < t 0 , f = High
Ans. (a) : From given MUX At, t 0 < t < 4t 0 , f = Low
F = Y ZI0 + YZI1 + YZI 2 + YZI3 At, t = 4t0, f = High
= Y ZX + YZ.0 + YZ X + YZ 136. One 2:1 MUX can be used to realize:
(a) NOT gate (b) XOR gate
= X Y Z + XYZ + YZ
(c) AND gate (d) All of the above
= XY Z + XYZ + YZ ( X + X ) OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
= XYZ + XYZ + XYZ + XYZ Ans. (d) : Multiplexer is a combinational circuit which
= ∑ m ( 2,3,4,7 ) have many data input and single output depending on
select or control input, one of the input line is
135. Consider the logic circuit with input signal transferred to the output, hence it is known as many to
TEST shown in the figure. All gates in the
figure shown have identical non-zero delay. one circuit or universal logic circuit or data selector
The signal TEST which was at logic LOW is circuit
switched to logic HIGH and maintained at logic Note- Mux is an universal Logic gate.
HIGH. The output: 137. One 16:1 Multiplexer can be implemented
using:
(a) Five 4:1 MUX
(a) Stays LOW throughout (b) Two 8: 1 MUX and one OR gate
(b) Pulses from LOW to High to LOW
(c) Two 8: 1 MUX and one 2:1 MUX
(c) Stays HIGH throughout
(d) Pulses from HIGH to LOW to HIGH
MPSC HOD Govt. Poly. - 2013
Ans. (d) :In the given logic circuit, every gate has an
identical non-zero delay. Ans. (d) : 16:1 MUX by 4:1 MUX
16 4
= 4MUX ⇒ = 1MUX
4 4
∴ Total number of 4:1 MUX = 4+1=5

16:1 MUX by 8:1 MUX 143. The number of half adders required to add m-
bit number is
16
= 2 MUX (a) 2m + 1 (b) 2m - 1
8 (c) 2m (d) 2m -1
Hence, 2, 8:1 MUX and one OR gate or One 2:1 MUX MPPSC Forest Service Exam.-2014
required for implementation. Ans. (d) : The number of bit = m
Note- MUX is an universal logic gate. The number of half adder required = 2m – 1
138. For a Full adder ts = 30 nsec, tc = 20 nsec, if 4 Half adder has two input line only.
full adder cascaded than output will show after 144. Which is showing multiple switching
______. parameter
(a) 90nsec (b) 110 nsec (a) MUX (b) Encoder
(c) 50 nsec (d) 30 nsec (c) Decoder (d) Adder
AAI-2015 BEL-2015
Ans. (a) : Time delay for output if 4 full adder Ans. (a) : MUX shows multiple switching parameter.
cascaded = 3×ts = 3×30 = 90 nsec. 145. In a 4×1 MUX, to get the Ex- OR equation at
139. Which is combinational circuit ____. output, the values of I0, I1, I2, I3 should be –––––
(a) MUX (b) Flip-Flop (a) I0 = 0, I1 = 1, I2 = 1, I3 = 0
(c) Counter (d) None (b) I0 = 1, I1 = 0, I2 = 0, I3 = 1
NPCIL-2015 (c) I0 = 0, I1 = 0, I2 = 1, I3 = 1
(d) I0 = 1, I1 = 1, I2 = 0, I3 = 0
Ans. (a) : MUX is combinational circuit which have
SAIL- 2014
many data input and single output. In combinational
circuit the value of output variables depend only on the Ans. (a) :
present value of input. The output does not depend on
the previous output.
140. Without any additional circuitry an 8:1 MUX
can be used to obtain
(a) Some but not all Boolean functions of 3
variables
(b) All function of 3 variables but none of 4 To get
variables Y = A ⊕ B = AB + AB
(c) All functions of 3 variables and some but not Let = I0= I3 = 0
all of 4 variables And I1 = I 2 = 1
(d) All functions of 4 variables
Then y = S1 S0 I0 + S1S0 I1 + S1 S0 I 2 + S1S0 I3
Ans. (c) : Without any additional circuitry an 8:1 MUX = 0 + S1S0 + S1 S0 + 0
can be used to obtain All functions of 3 variables and = AB + AB = A ⊕ B
some but not all of 4 variables.
146. Number of 1-bit full adders required to
141. A 16-bit serial adder needs how many Full construct 5-bit serial full adder are :
Adders? (a) Five (b) Two
(a) 3 (b) 1 (c) One (d) Four
(c) 2 (d) 0 MPSC HOD Govt. Poly. -2013
UPPCL AE-05.11.2019 Ans. (a) : For n-bit full adder, n-bit serial full adder
Ans. (b) : In serial adder bits are added in a pair at a will be required.
time. It uses a single full adder circuit for performing n- so, N = 5
bit addition. 147. In a half adder having two inputs A and B two
142. The number of 4:1 MUXs needed to build a outputs S (Sum) and C (Carry) the Boolean
16:1 MUX is: expression for S and C are
(a) 5 (b) 3 (a) S = AB + AB and C = A + B
(c) 6 (d) 4
(b) S = AB + AB and C = AB
UPPCL AE-05.11.2019
Ans. (a) : 16:1 mux will be implemented by 4:1 mux. (c) S = AB + AB andA + B
16 4 (d) None of these
No. of 4:1 mux = +
4 4 MPPSC Forest Service Exam.-2014
= 4 +1 Ans. (b) : Option (B) is correct.
=5 Truth table of half adder.
(a) I1 + I3 + I5 + I7 (b) I 2 + I3 + I6 + I7
(c) I 4 + I5 + I6 + I7 (d) I1 + I3 + I 4 + I7
BSNL(JTO)-2002,2001
Ans. (b) : Encoder is shown below-
148. Consider the output A and B with I0, I1, I2 and
I3 as input
A = I3 I2 I1 + I 3
B = I3 I1 + I 3
The above circuit is
(a) 4 : 1 multiplexer (b) De-multiplexer
(c) BCD circuit (d) Priority encoder
ISRO Scientist December, 2017 I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0
Ans. (d) : 0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
It cannot be a Mux, De-Mux and BCD circuit because 0 0 0 1 0 0 0 0 1 0 0
of number of input and output available. It is a priority 0 0 1 0 0 0 0 0 1 0 1
encoder circuit.
0 1 0 0 0 0 0 0 1 1 0
149. The 4 : 1 multiplexer implemented as
1 0 0 0 0 0 0 0 1 1 1
∴ Y1 = I 2 + I3 + I6 + I7
152. A gate having two inputs (A, B) and one output
(Y) is implemented using a 4-to-1 multiplexer
as shown in figure below. A1 (MSB) and A0 are
the control bits and I0–I3 are the inputs to the
Then Y = ? multiplexer.
(a) ∑ (1,6,3,7 ) (b) ∑ (1, 2,5,7 )
(c) ∑ ( 2,3, 4,5) (d)∑ (1,3, 4,7 )
Ans. (a) : I0 = 0, I1 = Ā, I2 = A, I3 = 1
Output Y = BCI0 + BCI1 + BCI 2 + BCI3
= BC.0 + BCA + BCA + BC.1
= 0 + ABC + ABC + BC ( A + A ) The gate is :
= ABC + ABC + ABC + ABC (a) NAND (b) NOR
∴ Y = ∑ (1,6,3,7 ) (c) XOR (d) OR
DRDO-2009
150. By using only 4 : 1 MUX, it is possible to
realize: Ans. (d) : Y = I0 A1A 0 + I1A1A 0 + I 2 A1A 0 + I3 A1A 0
(a) Any 3 variable function = AAB + BAB + AAB + BAB
(b) Only 2 variable function = AB + AB + AB
(c) Any 2 and 3 variable function = AB + AB + AB
(d) Few 3 variable functions
LMRC AM (S&T)-13.05.2018 = AB + B ( A + A )
Ans. (d) : By using (4:1) MUX any two variable = AB + B (1)
function can be implemented while some of three
variable functions can also be implemented. = AB + B
151. An eight lines to three lines encoder is shown in = A + B
figure. The output Y1 is Hence, option 'd' is correct the gate is OR gate.
153. The Boolean function F(A, B, C) = ∏(0, 2, 4, 7)
is to be implemented using a (4 × 1) multiplexer
shown in figure. Which one of the following
choices of inputs to multiplexer will realize the
Boolean function ?
155. If a 4-to-1 MUX (shown below) realizes a three-
variable function f (X,Y,Z) = XY + XZ . then
which of the following is correct?
(a) ( I0 , I1 , I 2 , I3 ,S1 ,S0 ) = (1,0, A, A,C, B )

(b) ( I0 , I1 , I 2 , I3 ,S1 ,S0 ) = (1,0, A, A, B,C ) (a) I0 = X I1 = 0, I 2 = X, I3 = X
(b) I0 = 0 I1 = 1I2 = Y, I3 = X
(c) ( I0 , I1 , I 2 , I3 ,S1 ,S0 ) = ( 0,1, A, A,C, B )
(c) I0 = X, I1 = 1.I 2 = 0, I3 = X
(d) ( I0 , I1 , I 2 , I3 ,S1 ,S0 ) = ( 0,1, A, A, B,C ) (d) I0 = X, I1 = 0, I 2 = X, I3 = Z
BSNL(JTO)-2009 BSNL (JTO)-2006
Ans. (d) : From option (d)
Ans. (a) : Output f = YZI0 + YZI1 + YZI2 + YZI3
I0 = 0, I1 = 1, I2 = A, I3 = Ā, S1 = B, S2 = C
Output Y = BCI0 + BCI1 + BCI 2 + BCI3 By putting I0 = I 2 = I3 = X
And I1 = 0
= 0 + BC + BCA + BCA
= BC + ABC + ABC = YZX + 0 + YZX + YZX
= BC ( A + A ) + ABC + ABC ( )
= XZ Y + Y + YZX Z + Z ( )
= ABC + ABC + ABC + ABC = XZ + YZ + XZ + YZXZ
SOP = ∑ m ( 5,1,6,3) = XZ + XY
POS from = Π (0, 2, 4, 7) 156. The logic realized by the adjoining circuit is
So, option (d) is correct.
154. For the multiplexer shown in figure, the
Boolean expression for the output Y is
(a) F(A, B,C) = A ⊕ B

(b) F (A, B,C) = A ⊕ C
(c) F (A, B, C) = A B
(d) F(A, B, C) = A C
(a) AB + BC + AC (b) AB + BC + AC BSNL (JTO)-2006
(c) AB + BC + AC (d) AB + BC + AC Ans. (a) : F = BCA 0 + BCA1 + BCA 2 + BCA 3
DRDO-2008 By putting A0 = A1=A
Ans. (c) : Output Y = ABCI0 + ABCI1 + ABCI2 + And A 2 = A 3 = 0 = A
ABCI3 + ABCI 4 + ABCI5 + ABCI6 + ABCI7 Then,
Y = ABC + ABC + ABC + ABC F = BCA + BCA + BCA + BCA
Y = ∑ m (1, 4,5,7 ) ( ) (
= AB C + C + AB C + C )
= AB + AB = A ⊕ B
157. The gates G1 and G2 in the figure have
propagation delays of 10 nsec and 20 nsec
respectively. If the input Vi makes an abrupt
change from logic 0 to 1 at time t = t0, then the
Y = AB + BC + AC output waveform V0 is
(a)
(b)
(c)
(d)
IES-1994
Ans. (b) :
GATE-2002
Ans. (b) :
X =A+ B+ B
= A+ B + B
= A+ B
A B X= A + B
Time G1 G2 0 0 1
Input Output Input Output 0 1 0
t0 0 1 0 1 1 0 1
t1 1 1 1 1 1 1 1
t2 1 0 1 1 Output of the given figure will be as option (b) is
correct-
t3 1 0 1 0
159. Expression for Y(A, B, C) in figure, where A, B
and C are boolean variable is :
(a) AB + ABC (b) A + BC

158. The output (X) waveform for the below
combination circuit for the inputs as A and B (c) AB + BC (d) (AB+AB)C
(waveform shown in the figure) will be BSNL(JTO)-2002,2001
Ans. (c) : MUX output-
Y = S1S0 I0 + S1S0 I1 + S1S0 I 2 + S1S0 I3
Y = AB + ABC + ABC
Y = AB + BC ( A + A )
Y = AB + BC
160. How many AND, OR and EXOR gates are
required for the configuration of full adder?
(a) 1, 2, 2 (b) 2, 1, 2
(c) 3, 1, 2 (d) 4, 0, 1
Ans. (b) 1.7 − 0.4
= × 100
2.2 − 0.4
1.3
= × 100 = 72.2%
1.8
163. The output of the circuit shown in Fig. is
______.
Full adder can be implement with 2 AND, 1 OR and

2Ex-OR gates.
161. Two binary digits are applied to the inputs of a (a) 0 (b) X
two-input AND gate. The output of the logic (c) A (d) 1
can generate DFCCIL Executive (S&T) 11.11.2018, 4:30 to 6:30PM
(a) BORROW OUT of a half subtractor Ans. (b) :
(b) CARRY OUT of a half-adder
(c) SUM output of a half-adder
(d) DIFFERENCE output of a half-adder
Ans. (b) : For AND gate
Y = A.B We know that, output of MUX is-
Truth Table
( Y = SI 0 + SI1 )
Sum of half adder (S) = AB + AB = A ⊕ B Therefore
Carry out of a half adder ( C ) = AB Y2 = 0.1 + 1.1
Y is similar as the carry out of half adder. Y2 = 1
162. The input waveform Vi and the output and Y1 = X.0 + Y2 .0
waveform V0 of a Schmitt NAND are shown in Y1 = X
the given figures.
and output, Y = A.1 + Y1.1
The duty cycle of the output waveform will be
Y = Y1
Y=X (Q Y1 = X )
164. Minimum number of half adders, full adders
and AND gates required to implement 2×3
Multiplier is given as
(a) 1, 2, 6 (b) 1, 1, 6
(c) 2, 2, 6 (d) 2, 1, 6
Ans. (d) :
(a) 100% (b) 85.5%

(c) 72.2% (d) 25%
IES-1999
Ton Ton
Ans. (c) : Duty cycle = × 100 = ×100
Ttotal Ton + Toff To implement 2×3 Multiplier, 2 half Adder, 1 full adder
T = Ton + Toff and 6 AND gate.

165. In a decoder, if the input lines are 4 then number Y = S1S2 I0 + S1S2 I1 + S1S2 I 2 + S1S2 I3
of maximum output lines will be:
From this expression it is clear that multiplexer is the
(a) 2
combination of AND and OR.
(b) 16
169. 5:32 decoder circuit can be implemented with
(c) 8
_____.
(d) 4
(a) One 2: 4 decoder and four 3:8 decoders
(b) Four 3:8 decoders
Ans. (b) : In a decoder 'n' input line hence, number of
maximum output lines = 2n. (c) Two 3:8 decoders
As given, input line n = 4 (d) Eight 2:4 decoders
So, Number of maximum output lines
= 24 = 16 Ans. (a) : 5:32 decoder circuit can be implemented with
one 2 : 4 decoder and four 3 : 8 decoders.
166. In a multiplexer, if there are 4 input lines and
1 output line, then number of selection lines
will be:
(a) 2
(b) 3
(c) 0 (d) 1
UPRVUNL AE-2016
Ans. (a) : In multiplexer-
Number of input line = 2
n
Where, n = Number of selected line.

So, 4 = 2n
22 = 2n
n=2
Then number of selection line will be 2
5:32 Line Decoder

170. Two signals fa and fb are given as input to EX-
OR to measure phase difference. The average
output voltage will be
167. A 12-bit parallel subtractor needs how many
Full Adders?
(a) 14 (b) 12
(c) 18 (d) 16
UPPCL AE-05.11.2019
Ans. (b) : For n-bit parallel substractor, n-full adder are
needed. The parallel binary subtractor is formed by the
combination of all full adder with subtrahend
complemented input. So for 12-bit parallel substractor,
12 full adder needed.
168. Digital multiplexer is basically a combinational
logic circuit to perform the operation.
(a) AND -AND (b) OR-OR
(c) AND-OR (d) OR-AND
Ans. (c) : We know that for two select line the output of
multiplexer is give by
Ans. (b) :
(d) None of these Sum S = AB + AB

ISRO Scientist December, 2017 = A⊕B
Ans. (a) : Two signals are given fa and fb as input to
EX-OR to measure phase difference. The duty cycle is
50%.
Borrow C = A.B
So, thus the given circuit is a half substractor circuit. It
is also known as two bit substractor circuit. Total 5
number of NAND/NOR gate required to construct half
substractor.
172. Consider a binary adder for the binary
addition of three input bits denoted by A, B, C.
The Boolean expressions to generate the sum
bit is
(a) AB + BC + AC
(b) A ⊕ B ⊕ C
According to the question we have to take average
(c) ABC + ABC
value. So that's why we have to pass this throw an
integrator circuit. So option (a) will satisfy this (d) (A + B + C) ( A + B + C )
condition. UPPCL AE- 31.12.2018
Ans. (b) : For 3-input adder
Adder S = A ⊕ B⊕C
carry C = AB + BC + CA
173. Which of the following statements about the
demultiplexers is INCORRECT?
(a) 1-line to 8-line demultiplexer consist of eight
171. The circuit is formed as shown below. The AND gates, all of them connected to a single
output S and C implement line data input
(b) It is used as anti-clock demultiplexers in
synchronous data transmission systems in the
receivers and security monitoring system etc.
(c) It takes single input and distributes it over
several outputs
(d) It takes one input data source and selectively
distributes in to 1-of-N output channels just
(a) two bit adder with sum and carry, like a multi-position switch
respectively DFCCIL Executive S&T 29.09.2021, 12:30 to 2:30PM
(b) two bit subtractor with sum and borrow, Ans. (b) : Demultiplexer is not used as anticlock
respectively demultiplexers in synchronous data transmission
systems in the receivers and security monitoring system
(c) S = AB + AB;C = AB etc. demultiplexer is also known as demux or data
(d) None of these distributor. If 'm' is the number of select lines then
m
ISRO Scientist December, 2017 output (n) of demux can be given as - (n = 2 ).
4. A J-K Flip\-Flop may be used as T - Flip-Flop
(v) Sequential Logic Circuits by connecting,
(a) outputs to inputs in inverting mode
(b) both the inputs
1. If the following counter is initially at 0000 state
then after 6th clock ABCD will be - (c) both the inputs using a inverter
(d) output to corresponding input
Ans. (b) :
(a) 0111 (b) 0011

(c) 0001 (d) 1000
UPPSC Poly. Tech. Lect.-22.03.2022, Paper –I
TANGEDCO-2015
Ans. (b) : Initially ABCD = 0000
CLK A B C D A = D B = A C = B D = C T Qn Q n +1 J K
1st 0 0 0 0 1 0 0 0 0 0 0 0 x
2nd 1 0 0 0 1 1 0 0 0 1 1 x 0
3rd
1 1 0 0 1 1 1 0 1 0 1 1 x
4 th
1 1 1 0 1 1 1 1 1 1 0 x 1
J=K=T
5th 1 1 1 1 0 1 1 1
6th 0 1 1 1 0 0 1 1 the Moore and Mealy models:
After 6 clock, it will become 0011 1. In the Mealy circuit, the final output
2. If the input to T-flip-flop is 100 Hz signal, the depends only on the present state of
final output of the three T-flip-flops that are memory elements.
connected in cascade is 2. In the Moore circuit, output can change in
(a) 1000 Hz (b) 500 Hz between the clock edges if the external
(c) 333 Hz (d) 12.5 Hz inputs change.
LMRC AM- 16.07.2021 3. The implementation of a logic function in
Mealy circuit needs more number of states
TSGENCO AE-2015
than Moore circuit.
UPRVUNL AE-11.06.2014
Ans. (d) : When n - flip-flop are cascaded then final (a) 1 and 2 only (b) 1 and 3 only
output frequency, (c) 1, 2 and 3 (d) 2 and 3 only
f 100 ESE-2021
f out = inn = 3
2 2 Ans.(c) : In Mealy circuit, the final output depend
f out = 12.5Hz upon present state as well as the present input.
In Moore circuit output can change in between the clock
3. D input of a clocked D-flip-flop receives an edges when state change occur.
input A ⊕ Q n where A is an external logic input
6. In JK flip-flop which combination will toggle
and Qn is the output of the nth D-FF before the the output?
clock appears. The circuit works as (a) J = 0, K = 0 (b) J = 1, K = 1
(a) EX-OR gate (b) T-FF (c) J = 1, K = 0 (d) J = 0, K = 1
(c) D-FF (d) JK-FF NLC GET -24.11.2020
RPSC ACF & FRO-23.02.2021 DFCCIL Executive S&T-17.04.2016, Shift-II
RPSC VP/Suptd. ITI, 05.11.2019 UPRVUNL AE-2016
IES – 2015 Ans. (b) : When J = K = 1 then the race condition is
Ans. (b) : Logic circuit according to the question - occurs that means both output wants to be high.
Hence there is toggle condition is occurs.
7. Ring, shift and Johnson Counters are :
(a) Synchronous Counter
(b) Asynchronous Counter
Qn+1 = A ⊕ Qn (c) True Binary Counter
=D (d) Synchronous and true Binary Counter
Hence, the logic circuit works as a T flip-flop. APPSC Poly. Lect. 15.03.2020

Ans. (a) : For Ring, shift and Johnson Counter all the Ans. (c) : D = Q n & all flip flops are clocked at same
flip flops are triggered at same time. Hence they are time. Hence, it is Johnson counter.
called synchronous counters.
14. A master-slave flip-flop has the characteristic
8. A sequential circuit with twelve states will have :
that
(a) 10 flip-flops (b) 8 flip-flops
(a) change in the input immediately reflected in
(c) 12 flip-flops (d) 4 flip-flops the output
APPSC POLY. LECT. 14.03.2020 (b) change in the output occurs when the state of
Ans. (d) : A sequential circuit consist of their sections the master is affected
labeled present state next state and output for 12 state (c) change in the output occurs when the state of
2 n ≈ 12 ≈ 24 the slave is affected
So number of flip-flop is 4. (d) both the master and the slave states are
9. The output of a clocked sequential circuit is affected at the same time
independent of the input. The circuit can be RRB JE-01.09.2019, 3:00 PM – 5:00 PM
represented by a/an : Mizoram PSC IOLM -2018, Paper II
(a) mealy machine TANGEDCO AE-2018
(b) moore machine Nagaland PSC (Degree) 2018, Paper-II
(c) combinational circuit Mizoram PSC IOLM-2018, Paper-II
(d) neither moore nor mealy machine GATE - 2004
APPSC POLY. LECT. 14.03.2020 Ans. (c) : • Master slave flip-flop constructed by 2 JK
flip-flops first FF called master is driven by positive
Ans. (b) : The output clocked sequential circuit is
clock pulse and second FF called slave is driven by
independent of input. the circuit can be represented by a
negative clock pulse.
moore machine.
10. A Modulo-10 counter has______states.
(a) 1024 (b) 512
(c) 16 (d) 10
• During positive clock pulse master gives intermediate
Ans. (d) : A Modulo-n counter has n states. A module output, but slave does not respond. During negative
10 counter has 10 states. clock pulse, slave FF activate and it copied the previous
11. In order to generate a 1 Hz clock from a 60 Hz output of the master flip-flop and previous output.
• It is basically used to avoid race around condition.
clock, we need to cascade the_____counter with
the_____counter. • So the above discussion change in the output occurs
(a) modulo-10, modulo-6 when the state of the slave is affected.
(b) modulo-16, modulo-4
15. An R-S latch is
(c) modulo-12, modulo-7
(a) combinational circuit
(d) modulo-12, modulo-6
(b) synchronous sequential circuit.
APPSC POLY. LECT. 14.03.2020 (c) one bit memory element
Ans. (a) : In order to generate a 1 Hz clock from a 60 (d) one clock delay element
Hz clock, we need to cascade the Modulo -10 counter Mizoram PSC IOLM-2018, Paper-II
with the Module-6 counter. Nagaland PSC (Degree) 2018, Paper-II
12. Which of the following represents D Flip-Flop? Mizoram PSC IOLM -2018, Paper II
(a) Data Flip-Flop (b) Delay Flip-Flop GATE – 1995
(c) Direct Flip-Flop (d) Decoder Flip-Flop
Ans. (c) : • R - S latch is a one bit memory element. It
is an Asynchronous which means that output of a latch
Ans. (b) : D (or Delay) flip-flop is a digital circuit used
depends on its input. A latch is a bi-stable multi-
to delay the change of the state of its output signal (Qn)
vibrator.
until the next rising edge of a clock timing input signal
• It has two states these states are high output and low
occurs. output. Latches are very similar to flip-flop, but are not
13. The circuit shown in diagram is : a synchronous device.
16. The race around condition exists in JK flip flop
if
(a) J = 0; K = 1 (b) J = 1; K = 0
(c) J = 1; K = 1 (d) J = 0; K = 0
IES-1992
(a) Ring counter (b) Ripple counter Nagaland PSC 2018, Diploma Paper-II
(c) Johnson counter (d) Mod-8 up counter Mizoram PSC Jr. Grade-2015, Paper-II
APPSC Poly. Lect. 15.03.2020 TS PSC Manager (Engg.) - 2015

Ans. (c) : • Race around condition in J-K flip flop Assuming the flip-flop was initially cleared and
occurs when J = K = 1 and if CLK = 1 For a long period then clocked for 6 pulses, the sequence at the Q
of time. Then output Q will toggle as long as CLK is output will be
high. (a) 010000 (b) 011001
17. The characteristic equation of the T-flip-flop is (c) 010010 (d) 010101
given by IES – 2014, 2011, 2004
(a) Q n +1 = TQ n (b) Q n +1 = TQ n + Q n T ISRO Scientist Engg. - 2011
GATE-1997
(c) Q n +1 = TQ n (d) Q n +1 = TQ n
Ans. (d) :
Mizoram PSC IOLM – 2018 (Paper-II)
TNPSC AE – 2013, IES – 2012, 2002
Mizoram PSC IOLM – 2010 (Paper-II)
ISRO Scientist Engg. – 2009
Ans. (b) : The "T" flip-flop is toggled when the set and
reset inputs alternatively changed by the incoming
trigger. In J-K flip-flop
Given, J = Q , K = 1
Q n T Q n +1 The flip-flop was initially cleared and then clocked for
0 0 0 6 pulses, the output of Q will be
0 1 1 Clock J K Q Q
1 0 1 Initially 0 0 1 0
1 1 0 1st → 1 1 1 0
Application of T-flip-flop- 2nd → 0 1 0 1
1. It is used in counter design.
2. These flip flops are used for constructing binary. 3rd → 1 1 1 0
3. They are used in frequency divider and shift 4th → 0 1 0 1
registers. 5th → 1 1 1 0
18. A 4-bit Modulo-6 ripple counter uses JK flip- th
→ 0 1 0 1
flop. If the propagation delay of each flip-flop The6 output of Q will be 0 1 0 1 0 1.
is 50ns then maximum clock frequency that can
be used is: 20. In the given figure shows a 4 bit serial in
parallel out right shift register. The initial
(a) 20 MHz (b) 5 MHz
contents as shown are 0110 After 3 clock pulses
(c) 10 GHz (d) 15 MHz the contents will be
TSTRANSCO AE-2018
IES - 2015
Ans. (b) : Propagation delay of each flip flop, = 50 ns (a) 0000 (b) 0101
Propagation delay of 4 flip-flop tpd = 4×50ns (c) 1010 (d) 1111
= 200 ns
1 UPPCL AE-16.11.2013
Maximum clock frequency fmax = RPSC Vice Principal ITI - 2016
Tmin
IES – 2003, GATE -1992
1
= Mizoram PSC Jr. Grade-2015, Paper-II
t pd Ans. (c)
1 • Given contents of the register at the starting is 0110.
=
200 × 10−9 • After 1st clock pulse → 1011
• After 2nd clock pulse → 0101
f max = 5MHz
• After 3rd clock pulse → 1010
19. In the J-K flip-flop we have J = Q and K = 1 as 21. Minimum number of J-K flip-flops needed to
shown in the figure. construct a BCD counter is
(a) 2 (b) 3
(c) 4 (d) 5
IES - 2003

Ans. (c) BCD counters by using JK flip-flop - 24. Which of the following flip-flops is used as
latch?
(a) JK flip-flop (b) D flip-flop
(c) RS flip-flop (d) T flip-flop
Ans. (c) :
• BCD counter is also known as binary counter or

Decade counter. Range = 0 to 9 No. of states N = 10
N ≤ 2n, 10 ≤ 2n, n 4 (Number of flip-flops)
• Minimum 4 JK flip-flop are needed to construct a
BCD counter.
• Number of states count by BCD counter = 0000 to Overall circuit is clocked SR LATCH.
1001. 25. D flip-flop can be made from J-K flip-flop by
22. Using S-R flip-flops and two additional gates a making:
J-K flip-flop can be realized. Which additional (a) J = K = 0 (b) J = K = 1
gates are required ? (c) J = 0, K = 1 (d) J = K
(a) NOR gates (b) NOT gates RPSC VP/Suptd. ITI 05.11.2019
(c) OR gates (d) NAND gates Ans. (d) : D flip-flop by using J-K flip-flop -
Ans. (d) : Conversion of SR to JK flip flop.
Qn D Q n +1 J K
0 0 0 0 ×
0 1 1 1 ×
1 0 0 × 1
1 1 1 × 0
K - Map for J -
S = JQn R = KQn
So the additional gate conversion of SR to JK required
NAND gate.
23. The Q output of a J-K FLIP-FLOP is '1'. The
output does not change when a clock-pulse is
applied. The inputs J and K will be respectively J=D
(where 'X' don't care state) K - Map for K -
(a) 0 and x (b) x and 0
(c) 1 and 0 (d) 0 and 1
IES – 1994, 1992
Ans. (b) : • The excitation-table of J-K Flip flop is –
K=D
J K Q n Q n +1
J=K
0 × 0 0
26. A five-bit asynchronous counter is shown in the
1 × 0 1 figure. If the clock input frequency is 22.4
× 1 1 0 MHz, what is the frequency at the output E?
× 0 1 1
When a output of J-K flip flop is 1 the Input of J-K- flip
flop must be (× and 0) respectively.
• Hence, (×,0) is time possible combination of input for (a) 700 kHz (b) 350 kHz
output Qn=1 (c) 150 MHz (d) 300 MHz
ESE-2022

Ans. (a) : Given that- Input frequency = 22.4 MHz. 29. A certain J-K flip-flop has propagation delay
MOD of counter (M) = 25 = 32 12 picoseconds. What is the largest MOD of a
input frequency counter that can be constructed from these J-K
Output frequency = flip-flops and operates up to 10 GHz?
MOD of counter (a) 64 (b) 128
22.4 × 106 (c) 256 (d) 512
= ESE-2022
32
Output frequency = 700 kHz ISRO Scientist Engg. 2009
27. What is the division factor of the following (c) : Given that propagation delay (tpd) = 12 pico
clock divider circuit? second
we know that -
1
f≤
n t PdFF
1
10 ×109 ≤
(a) 2 (b) 3 n ×12 ×10−12
(c) 1.5 (d) 2.5 1
n≤
ISRO Scientist Engg.-2013 10 ×10 ×12 ×10−12
9
Ans. (c) : n ≤ 8.33

CLK in D1 D2 Q1 Q 2 Q1 Q 2 CLK out So that number of flip flop required = 8 largest mod of
counter = 28 = 256
No 1 1 0 0 1 1 1
30. A mealy state machine's output depends on
Up 1 1 1 0 0 1 0
(a) State and outputs (b) Inputs
Down 0 1 1 1 0 0 0 (c) State (d) State and inputs
Up 0 1 0 1 1 0 0 ISRO Scientist Engg. 2009
Down 1 0 0 0 1 1 1 Ans. (d) : A mealy machine is a FSM whose output
depends on the present state as well as the present input.
31. In the following circuit, what sequence is
followed by A and B on rising edge of CLK
after reset is de-asserted?
Now the clock period can be seen has 1.5 which implies
frequency is divided by 1.5
28. Following shift register is initially loaded with
the bit pattern "1010". After how many clock
cycles will the content of shift register be
"1010" again?
(a) AB = 10, 11, 00, 10, 11, ….
(b) AB = 10, 01, 00, 11, 10, …
(c) AB = 10, 00, 01, 10, 00, …
(d) AB = 11, 01, 00, 10, 11, …
(a) 5 (b) 9
(c) 7 (d) 15
ISRO Scientist Engg.-2010 Ans. (a) : D = A ⊕ B = 1
Ans. (c) : During t0 all Q values are set to zero hence present state
D = 1 ⊕ 1= 0
Clock Q3 Q2 Q1 Q0
Initial 1 0 1 0
1 1 1 0 1
2 0 1 1 0
3 0 0 1 1
4 0 0 0 1
5 1 0 0 0
6 0 1 0 0
7 1 0 1 0 So, AB = 10, 11, 00, 10, 11, .........
It is clear that, after '7' clock cycle it reaches it's initial 32. The state transition diagram for a sequence
state. generator is shown in figure

33.
It is designed using D F/Fs and combinational

logic blocks L1, L2 & L3 and is initialized at (Q2
= 1, Q1 = 0, Q0 = 1) If Sys clock frequency is > 4* clk_ext
frequency. What is the functionality of above
circuit?
(a) Falling Edge detector with Pulse width of Qout
= one cycle of Sys clk
(b) Rising Edge detector with Pulse width of Qout
= one cycle of Sys clk
(c) Falling Edge detector with Pulse width of Qout
The minimized expressions for O0, O1 & O2 = one cycle of clk_ext
are:
(d) Rising Edge detector with Pulse width of
(a) O2 = Q2 O1 = Q1 O0 = Q0
Qout= one cycle of clk_ext
(b) O 2 = Q1.Q 0 O1 = Q0 .Q1.Q 2 + Q0 .Q1.Q 2 ISRO Scientist Engg.-2018
O 0 = Q0 .Q1.Q 2 Ans.(b): The above given with D-flip flop is level
(c) O 2 = Q1 O1 = Q0 + Q 2 O 0 = Q1.Q 2 triggered.
(d) None of above Q system clock > 4 * clk_ext, the time duration of
ISRO Scientist Engg.-2012 clock on is very less.
For first clock pulse only Q1 is passed through clk_ext
Ans. (c) : Q2 = 1, Q1 = 0, Q0 = 1
signal.
For second clock pulse clk_ext will go upto Q2.
For third clock pulse clk_ext will go upto Q3.
If Q2 = 1 and Q3 = 0 and Q2 & Q3 having a delay of one
clock pulse.
K - map of D2 Then, Qout = 1
Assume that system clock frequency
fsys clock = 6* clk_ext.
So O2 = Q1 Qout = 2Ts – Ts = One cycle of the system clock

O1 = Q 0 + Q 2 Hence, the functionality of the circuit is Rising Edge
O 0 = Q 1Q 2 detector with Pulse width of Qout = one cycle of Sys clk.

34. A pulse train with a frequency of 1MHz is 36. What is the functionality of following digital
counted using a modulo 1024 ripple-counter circuit? A is input data, CLK is system clock
built with J-K flip-flops. For proper operation and Y is output.
of the counter the maximum permissible
propagation delay per flip-flop stage is
(a) 100 n sec (b) 50 n sec
(c) 20 n sec (d) 10 n sec
IES - 2012
GATE - 1993 (a) Falling edge detection of input A
Ans. (a) : Given, (b) Clock division by 2
Pulse train frequency = 1MHz (c) Rising edge detection of input A
Modulo 1024 =210 = 2n (d) Clock division by 4
n = 10 TNTRB AE-2017
1 ISRO Scientist Engg. -2015
fmax = where tpd = propagation delay
n.t pd Ans. (a) : Falling edge detection of input A
1
tpd =
n.f max
1
tpd =
10 × 106 If A = 0
tpd = 100 nsec. Q=0
35. The following Finite State Machine (FSM) is then Q of IInd flip flop is 0
used to detect a particular pattern in input data ∴ output Y = 0
stream. Whenever the pattern is matched at if A=1
input, output is set to '1' or else output is Q=1
cleared to '0'. For which of the following data then, Y = 0
stream, output goes to '1' twice?
37. What is the frequency and duty cycle of output
Y, when CLK frequency is 1 MHz @ 50% duty
cycle?
(a)
0010011010010101
(b)
0101011000010101
(c)
0011011010010101
(d)
1100100101001010 (a) 500 KHz @ 50% duty cycle
ISRO Scientist Engg. -2015 (b) 500 KHz @ 25% duty cycle
Ans. (c) : The sequence will be (c) 250 KHz @ 50% duty cycle
0011011010010101 (d) 250 KHz @ 25% duty cycle
So, output goes '1' twice on the mark positions. ISRO Scientist Engg.-2013
Ans. (b) :
Present state Input Next Output
State Output
Clock pulse D1 D2 Q1 Q 2 Q1 Q 2
S0 0 S0 0 (Y)
1 S1 0 No CLK 1 0 0 0 1 1 0
S1 0 S0 0 Up 1 0 1 0 0 1 0
1 S2 0 Down 1 1 1 1 0 0 1
S2 0 S3 0 Up 0 1 0 1 1 0 0
1 S2 0 Down 0 0 0 0 1 1 0
S3 0 S0 0 Up 1 0 1 0 0 1 0
1 S1 1 Down 1 1 1 1 0 0 1

the given block is :
Process (CLK, d) begin
Here CLK and d are sensitivity list
After that no condition for CLK = 0
This block gives the circuits known as D-latch.
40. A counter is designed using J-K Flip-Flop as
shown in fig. Define its count sequence
• Now in the above diagram clearly output has double

the time period of clock pulse which means frequency
is half.
(a)000, 001, 010, 011, 100 & repeats
106 (b)100, 011, 010, 001, 000 & repeat
Output frequency f0 = = 500kHz
2 (c)
010, 011, 100, 000, 001 & repeats
TON (d)101, 110, 111, 000, 001, 010, 011, 100
So, Duty cycle = ×100 repeats
TON + TOFF
1
= × 100 Ans. (b): The given circuit is a 3-bit asynchronous
1+ 3 counter.
= 25%
38. An 8 bit ripple counter and an 8 bit
synchronous counter are made using flip flops
having a propagation delay of 10 ns each. If
the worst case delay in the ripple counter and
the synchronous counter be R and S
respectively, then From the analysis of the given circuit, it is clear that this
(a) R = 10 ns, S = 80 ns is a MOD-4 down counter and it starts counting from
(b) R = 40 ns, S = 10 ns 100 up to 000 and then it repeats. So its count sequence
= 100, 011, 010, 001, 000 & repeats.
(c) R = 10 ns S = 10 ns
(d) R = 80 ns, S = 10 ns 41. A 1 MHz clock signal is applied to a J-K Flip
ISRO Scientist Engg.-2013 Flop with J=K=1. What is the frequency of the
Flip-Flop O/P signal?
Ans. (d) : In synchronous counter, time delay is (a) 2MHz (b) 500 kHz
constant then S = 10 ns.
(c) 250 kHz (d) 500 MHz
but asynchronous counter time delay (R) = nTs
= 8 × 10
R = 80 ns Ans. (b): fs = 1 MHz
if (J = K = 1)
39. The following code will implement a ________
f 1 MHz
process (clk, d) begin then f 0 = s =
if (clk = ‘1’) then 2 2
q <=d; f 0 = 500 kHz
end if;
42. Which shift register counter requires the most
end process
decoding circuitry?
(a) Positive edge triggered D flip flop
(a) Johnson Counter (b) Ring Counter
(b) Negative edge triggered D flip flop
(c) D latch (c) Ripple Counter (d) MOD counter
(d) None of the above ISRO Scientist Engg.-2016
ISRO Scientist Engg.-2011 Ans. (a): Johnson counter is a modified ring counter
Ans. (c) : If (CLK = 1) then, where the invented output from the last flip-flop
connected to the input in the first. This register cycles
q < = d;
through a sequence of bit platform. The mode of
end if; Johnson counter is 2n if n flip-flop are used. Main
this is a latch process. advantage of Johnson counter is that it needs half the
Signal name < = Expression after delay number compared to the ring counter for same MOD.
Variable name := Expression 43. For one of the following conditions, clocked J-
The process is the keyword along with the begin and K flip-flop can be used as DIVIDE BY 2 circuit
'end'. where the pulse train to be divided is applied at
To end the process keyword is the end process. clock input.
(a) J = 1, K = 1 and the flip-flop should have Ans. (b) : Given that,
active HIGH inputs 4-bit up counter has preset input
(b) J = 1, K = 1 and the flip-flop should have (0101)2 = (5)10
active LOW inputs After 10 clock pulses it reaches 1111 then-
(c) J = 0, K = 0 and the flip-flop should have (1111)2 = (15)10
active HIGH inputs Therefore the modulus of the counter is = 1111–0101
(d) J = 1, K = 1 and the flip-flop should be a = 1010
negative edge triggered one in decimal, 1010 equal to 10
Mizoram PSC Jr. Grade - 2018, Paper-II So, it is a MOD-10 counter
ISRO Scientist Engg.-2007 46. A 4-bit synchronous counter uses flip-flops
Ans. (d) : with propagation delay time of 25 ns each. The
maximum possible time required for change of
state will be
(a) 25 ns (b) 50 ns
(c) 75 ns (d) 100 ns
Ans. (a) : The propagation delay time of each flip-flop
in given synchronous counter is 25 ns.
The clocked J.K flip flop can be used as a divide by 2 ∴ The maximum time required for change of state will
circuit when input J = K =1 is applied at clock input and also be 25 ns.
flip-flop has active high inputs. 47. If a counter having 10 FFs is initially at 0, what
This can be done if J-K flip-flop works in toggle mode count will if hold after 2060 Pulses
(J=1 and K=1) and flip-flop should be negative edge (a) 000 000 1100 (b) 000 001 1100
triggered. (c) 000 001 1000 (d) 000 000 1110
44. The circuit is a
Ans. (a) : Given counter has 10 FFs
So, that it will count [0]10 to [1023]10
i.e. from (0 to 2n –1)
∴ Total number of states of 10 FF = 1024 states
Now,
(a) Monostable MV (b) Astable MV 2060
(c) Adder (d) SR FF
−1024
Ans. (d) : Given circuit can be re-drawn as below:- 1036
−1024
0012
The value of counter after 2060 pulses is the same as
that after 12 pulses.
Convert decimal number 12 into binary i.e.
(0000001100)2. Hence, after 2060 pulses the count will
A B Q Q be (1100)2.
1 0 1 0 48. 74VHC273 is a
(a) Dual 4 to 1 Mux
0 0 1 0
(b) Quad 2 to 1 Mux
0 1 0 1 (c) Quad D type flip-flop
0 0 0 1 (d) Octal D type flip-flop
1 1 0 0 UPRVUNL AE– 11.06.2014
Ans. (d) : The 74HC 273 is an advanced high speed
So, the circuit is a SR flip-flop. CMOS octal D-type flip flop. In 74HC273 information
45. A 4-bit presetable UP counter has preset input signals applied to D inputs are transferred to the Q
0101. The preset operation takes place as soon outputs on the positive going edge of the clock pulse.
as the counter reaches 1111. The modulus of 49. Which of the following logic circuits do not
the counter is have no-change condition?
(a) 5 (b) 10 (a) D-FF (b) T-FF
(c) 11 (d) 15 (c) K-FF (d) SR-latch
ISRO Scientist Engg.-2007 ISRO Scientist Engg. -2020
Ans. (a) : D- flip flop does not have such an input Ans. (a) : Y = 1 when Q2 = Q1 = 1
condition here output always follows the input- For D-flip flop
Truth Table:- Qn + 1 = Dn
when Q1 = 0
then Q1 = 1
then first flip flop data is changed to 1. Q1 is connected
to IInd FF
50. What is the maximum clock frequency at Q2 = 1
which following circuit can be operated without input of AND gate is 1 then output (y ) = 1
timing violations? Assume that the 52. The circuit shown consists of J-K flip-flops,
combinational logic delay is 10 ns and the clock each with an active low asynchronous reset
duty cycle varies form 40% to 60% ( R D input). The counter corresponding to this
circuit is
(a) 100 MHz (b) 50 MHz (a) a modulo-5 binary up counter

(c) 40 MHz (d) 25 MHz (b) a modulo-6 binary down counter
ISRO Scientist Engg.-2010 (c) a modulo-5 down counter
(d) a modulo-6 binary up counter
Ans. (c) :
Ans. (a) :
∴ during 10ns, Flip-Flop 2 will not change The all flip-flops given in above figure, are in toggle
∴ (–) edge of clock come after 10ns mode J = K = 1, Qn+1 = Q n
So, flip-flop will change its state for every clock pulse.
Clock input is connected to Q0 or LSB and sequence
will be Q2Q1Q0.
40% of T = 10ns Q is connected to falling edge, So it is an up counter.
40 NAND gate is connected to R d input (reset). All flip-
T = 10ns flops will reset state when NAND gate output is zero.
100
NAND gate output = 0 when Q2 = Q0 = 1
100 × 10ns
T= So, Q2Q1Q0 = 101 or 111
40 In up counter 101 state occurs first, So counter counts
T = 25ns up 101 and total count = 000 to 100
1 1 Hence, the counter corresponding to this circuit is a
f= = −9 modulo-5 binary up counter.
T 25 × 10
fmax = 40MHz 53. A three bit pseudo random number generator
is shown. Initially the value of output Y = Y2 Y1
51. When the output Y in the circuit below is "1",
Y0 is set to 111. The value of output Y after
it implies that data has
three clock cycles is
(a) changed from "0" to "1"

(b) changed from "1" to "0"
(c) changed in either direction (a) 000 (b) 001
(d) not changed (c) 010 (d) 100
Nagaland PSC (CTSE) Diploma-2017, Paper II Nagaland PSC (CTSE) Diploma-2017, Paper II
GATE - 2011 GATE - 2015
Ans. (d) = Q 2Q1 + Q1Q 2
= Q 2 ( Q1 + Q1 )
Q1+ = Q 2
Q +2 = J 2 Q 2 + K 2Q 2
( )
= ( Q1 + Q 2 ) .Q 2 + Q1 + Q 2 .Q 2
= Q1Q 2 + Q1Q 2
= Q1 ( Q 2 + Q 2 )
So, The value of output Y after three clock pulse cycles
= 100 Q +2 = Q1
54. In the latch circuit shown, the NAND gates
have non-zero, but unequal proportion delays. Present state Next state
The present input condition is : P = Q = '0'. If
the input condition is changed simultaneously Q1 Q2 Q1+ = Q 2 Q 2+ = Q1
to P = Q = '1', the outputs X and Y are
0 0 0 1
0 1 1 1
1 1 1 0
(a) X = '1', Y = '1'
(b) either X = '1', Y = '0' or X = '0', Y = '1' 1 0 0 0
(c) either X = '1', Y = '1' or X = '0', Y = '0' 00 → 01 → 11 → 10 → 00 ...........
(d) X = '0', Y = '0' Hence, option 'c' is correct.
Nagaland PSC (CTSE) Diploma-2017, Paper II 56. In the figure shown, the initial state Q is 0. The
Ans. (b) : From the given figure output is observed after the application of each
clock pulse. The output sequence at Q is
If P = Q = 0 Then X = 1, Y = 1
If P = Q = 1 Then X = 1, Y = 0
or (a) 0000….. (b) 1010…..
X = 0, Y = 1 (c) 1111….. (d) 1000…..
55. A 2-bit synchronous counter using two J-K flip
flops is shown. The expressions for the inputs Ans. (c) : Here J = 1 K =Q
to the J-K flip flops are also shown in the Q +1 = JQ + KQ
figure. The output sequence of the counter
starting from Q1Q2 = 00 is Q +1 = Q + Q Q
Q +1 = Q + Q
Q +1 = 1 Always.
57. All the logic gates in the circuit shown have
finite propagation delay. The circuit can be
(a) 00 → 11 → 10 → 01 → 00…. used as a clock generator, if
(b) 00 → 01 → 10 → 11 → 00….
(c) 00 → 01 → 11 → 10 → 00….
(d) 00 → 10 → 11 → 01 → 00….
Ans. (c) : Next state equation at J.K flip-flop :-
(a) X = 0 (b) X = 1
Q n +1 = JQ n + KQ n (c) X = 0 or 1 (d) X = Y
Q1+ = JQ1 + KQ1 Nagaland PSC (CTSE) Diploma-2017, Paper II
( )
Ans. (b) : Next state equation of circuit-
= ( Q1 + Q 2 ) .Q1 + Q1 + Q 2 .Q1
Y+ = X ⊕ Y

200 200
f0 = =
23 8
f 0 = 25Hz
62.If a register has shift and parallel load
capabilities then it is called as
(a) Bi-directional shift register
(b) Uni-directional shift register
(c) Parallel in parallel out register
(d) Universal shift register
• At X = 0, circuit reach to stable state.
If Y = 0, it will remain 0 TNPSC AE - 2018
If Y = 1, it will remain 1 Ans. (d) : If a register has shift and parallel load
• At X = 1, circuit state goes to (0 to 1 or 1 to 0). capabilities then it is called as universal shift register. A
So circuit will not reach to stable state. universal shift register circuit consists of four D-flip-
Given circuit will be used as clock generator. flops and four multiplexers. The four multiplexers have
58. A counter has N flip flops. The total number of two common selection inputs S1 and S0.
states are
(a) N (b) 2N
(c) 2N (d) 4N
UKPSC Assistant Radio officer screening Exam-2011
Ans. (c) : Q One flip-flop have 2-states.
∴ N flip-flop have 2N - states.
59. The diagram shown is of a/an .
(a) synchronous counter 63.

(b) combinational circuit Present state Input Next state Output
(c) ring counter A B X A B Y
(d) asynchronous counter 0 0 0 0 0 0
0 0 1 0 1 0
Ans. (d) : In given diagram,
0 1 0 0 1 0
There are two flip-flops and both flip-flop have
different clock pulse. So it is asynchronous counter. 0 1 1 1 0 0
60. An 8-bit SISO mode needs clock pulses 1 0 0 1 0 0
to load an 8-bit number into a register. 1 0 1 1 1 0
(a) 4 (b) 18 1 1 0 1 1 0
(c) 8 (d) 2 1 1 1 0 0 1
UPRVUNL AE -19.07.2021, Shift-II The state equations and output equation of the
Ans. (c) : 1-bit SISO mode needs 1 clock pulses to load given state table for sequential circuits with T
∴ 8-bit SISO mode needs 8 Clock pulse flip–flops are
61. If the input to T-flip-flop is 200 Hz signal, the (a) TA = BX, TB = B ⊕ X, Y = AB
final output of the three T- flip-flops in cascade (b) TA = AX, TB = X, Y = AB
is: (c) TA = X, TB = X, Y = AB'
(a) 20 Hz (b) 12.5 Hz
(d) TA = X, TB = AX, Y = AB'
(c) 50 Hz (d) 25 Hz
UPRVUNL AE -19.07.2021, Shift-II TNPSC AE - 2018
Ans. (d) : Given, the input frequency fi = 200 Hz Ans. (a) : From table –
f TA = BX TB = B ⊕ X and
Output frequency f0 = in
2
Y = AB
Where, n = No. of FFs
64. For an n bit binary counter having 'n' number Ans. (b) : The MOD number of a Johnson counter will
of flip flops, specify the maximum possible be always equal to twice the number of flip-flops used.
range of bit count Johnson counter consists of '2n' number of states where
(a) 0 to 2n (b) 0 to 2n–1 'n' is number of flip-flops.
n +1
(c) 0 to 2 n+1
(d) 0 to 2 2 69. The performance gain that can be obtained by
improving some portion of a computer can be
TNPSC AE - 2018 calculated using
Ans. (b) : The maximum possible range of bit-count (a) Moore's law (b) Djikstra's algorithm
specify in n-bit binary counter consisting of 'n' number (c) Amdahl's law (d) Murphy's law
of flip-flop, the maximum possible range (0 to 2n–1). ISRO Scientist Engg.-2008
65. In the following state table, the equivalent Ans. (c) : The performance gain that can be obtained by
states are improving some portion of a computer can be calculated
using Amdahl's law.
Amdahl's Law states that the performance improvement
to be gained from using some faster mode of execution
is limited by the fraction of time the faster mode can be
used.
(a) (a, d) (b, c) (b) (a, c) (b, d) 70. A counter is designed with six stages of flip
(c) (a, b) (c, d) (d) (a, c) flops. Determine the output frequency at the
TNPSC AE - 2018 last (sixth) stage, when input frequency is
Ans. (c) : 1 MHz.
Present state Next stage Output (a) 1 MHz (b) 166 KHz
(c) 15.625 KHz (d) Zero
a c b 0 1
b d a 0 1
Ans. (c) : Given,
c a d 1 0
Modulus of counter = 26
d b d 1 0
Input frequency = 1MHz
equivalent state ⇒ (a, b) (c, d) Input frequency
66. Name the memory elements used in clocked Output frequency =
Modulus of counter
and asynchronous sequential circuits
(a) Time delay devices and registers 1× 106 1000000
= =
(b) Time delay devices and flip flops 26 64
(c) Time delay devices and counters = 15.625 kHz
(d) Time delay devices and latches 71. In a ripple counter how many changes in state
TNPSC AE - 2018 happen when count changes from 7 to 8?
Ans. (b) : Time delay devices and flip flops are the (a) 1 (b) 2
memory element used in clock and asynchronous (c) 3 (d) 4
sequential circuit because these two device has some ISRO Scientist Engg.-2008
memory. Ans. (d) :
67. The propagation delay of each flip flop is the State Counter value
highly limiting factor in the design of
7 0111
(a) Ring counter (b) Ripple counter
(c) Mod n counter (d) Up/down counter 8 1000
TNPSC AE - 2018 Each flip-flop has changed its output.
Ans. (b) : The propagation delay of each flip-flop is the Hence, 4 changes states will occur.
highly limiting factor in the design of ripple counter. 72. Which of the following represents the Moore
Propagation delay of ripple counter is the sum of model for sequential circuit?
propagation delay due to different flip-flop.
68. The mod number of a Johnson counter will be
always equal to ........ the number of flip flops
used
(a) same
(b) Twice
(c) 2N where N is the number of flip flops
(d) None of the these
ISRO Scientist Engg.-2008 ISRO Scientist Engg.-2008
Ans. (c) : Moore Model : In moore model the outputs
of the sequential circuit are synchronized with the clock
because they depend on only flip-flop outputs that are
synchronized with the clock.
The output depends only on present state value of There are 5 unique state in decreasing order.
sequential circuit no on inputs. Hence, it is MOD - 5 down counter.
75. The initial state of MOD-12 down counter is
0110. After 28 clock pulses, the state of the
counter will be -
(a) 1011 (b) 1010
(c) 0010 (d) 0001
73. The ‘T’ Flip-Flop derives its name from its UPPCL AE-16.11.2013
operation, which is-------. Ans. (c) : A mod-12 counter goes through 12 states in
(a) Toggle (b) Trigger one cycle of 12 clock pulses.
(c) Transistor (d) None of these It complete 2 cycles in 24 clock pulses.
Mizoram PSC IOLM -2018, Paper II In the rest 4 clock pulses, it moves down from
Ans. (a) : The 'T' flip flop derived its name from its (0110)2 = (6)10 – (4)10 = (2)10 = (0010)2
operating which is toggle because the output toggle 0 to 76. In a negative edge triggered J-K flip flop, in
1 and 1 to zero. order to have the output state 1,0,0,1 in the
74. The ripple counter shown in figure below with next successive four clock pulses, the inputs J-
state Q2Q1Q0 is a K are-
(a) 10,01,00,11 (b) 01,00,00,01
(c) 11,00,00,11 (d) 10,00,00,11
CGPSC SO-14.02.2016
UPPCL AE-16.11.2013
Ans. (d) : For JK flip-flop
Q n +1 = JQ n + KQ n
when output state 1, 0, 0, 1 than input will be
(a) MOD- 5 up counter 10,00,00,11
(b) MOD- 3 down counter 77. If the input of T flip flop is 100 signals, the final
(c) MOD- 5 down counter output of the three T flip flops in cascade is
(a) 12.5 Hz (b) 333 Hz
(d) MOD- 4 up counter
(c) 500 Hz (d) 1000 Hz
UPSC JWM-2016
UPPCL AE- 31.12.2018
Ans. (a) : Input frequency fi = 100 Hz
IES-2005
No. of T flip-flop n = 3
GATE-1999
f 100 100
Ans. (c) : final output frequency f0 = in = 3 = = 12.5Hz.
2 2 8
Q2 Q1 Q0 PRE = Q 2 Q1Q0 78. A MOD-16 ripple counter is holding the count
10012. What will be the count after 31 clock
1 1 1 0 pulses?
1 1 0 0 (a) 10002 (b) 10102
(c) 10112 (d) 11012
1 0 1 0 UPSC JWM-2016
Ans. (a) : The counter hold current count = (1001)2 =
1 0 0 0
(9)10 , means total 9 pulses are completed.
0 1 1 0 We required counts after 31 pulses.
So, the total clock pulses = 9 + 31 = 40
0− − − −1− − − −0− Preset will be high Mod-16 ripple counter counts 16 states and it will
repeat again.
0 0 1
For 2 cycles it will complete 32 clock pulses. The rest
0 0 0 counts after 31 clock = 40 – 32 = (8)10
= (1000)2

79. The minimum number of flip-flops required to 83. The modulus of a counter is
realize a mod-3 counter is (a) The number of flip-flops
(a) 3 (b) 8 (b) The actual number of states in its sequence
(c) 2 (d) 6 (c) The number of times it recycles in a second
UJVNL AE-2016 (d) The maximum possible number of states
Ans. (c) : For mode-3 counter, No. of flip flop should TNPSC AE-2014
be
Ans. (b) : The MOD-number indicates the number of
2n > 3.
states in counting sequence.
Hence n = 2.
For n-ffs, counter will have 2n different states and then
80. In______, the flip flop output transition serves this counter is said to be MOD-2n counter.
as a source for triggering other flip-flops.
(a) Ripple counter (b) Parallel adder 84. For the circuit shown, the clock frequency is f0
(c) Shift register (d) Serial adder and the duty cycle is 5%. For the signal at the
Q output of the Flip-Flop, _______.
Ans. (a) : In ripple counter the flip-flop output
transition serves as source for triggering other flip-flop.
In ripple counter with n-flip-flop, the total number of
states are 2n.
(a)
frequency is f0/4 and duty cycle is 50%
(b)
(c)
81. Frequency of the output of given circuit is (d)
frequency is f0 and duty cycle is 25%
GATE-2022
Ans. (a) : Here 2 flip-flop is used
(a) 125 Hz (b) 250 Hz So, this show 2-bit binary count
(c) 400 KHz (d) 1000 Hz
MSB LSB
UJVNL AE-2016
0 0
Ans. (a) : Given input frequency fi = 1 kHz
0 1
1 0
fi 1000 1 1
Now output frequency f0 = =
2n 23 Timing diagram
= 125 Hz.
82. The counter in figure is
(a) MOD 3 (b) MOD 6

(c) MOD 8 (d) MOD 7 From the timing diagram, output (Q) has frequency of
UKPSC Assistant Radio Officer Screening Exam.-2011 f0/4 and output duty cycle is 50%.
Ans. (a) : 85. How many flip flops are required to construct a
MOD-128 counter? What is the largest decimal
number that can be stored in a MOD-64
counter?
(a) Seven flip flops, largest decimal number is 63
(b) Five flip flops, largest decimal number is 63
(c) Seven flip flops, largest decimal number is 15
Preset condition = BC is indicate counter will reset at (d) Five flip flops, largest decimal number is 32
'011'. So it has 3 unit state. So it is a MOD 3 up counter. TNPSC AE-2014
Ans. (a) : If N = total number of states 90. A 4-bit Johnson counter is initialized to 0101.
n = number of FFs then Every time the state 1011 is reached, the
counter is re-initialized to 0000 at the next
N ≤ 2n clock active edge. Again when the state 0001 is
For n-FFs, counter 2n and MOD-2n counter 128 = 27 reached, the counter is initialized back to 0101
Hence n = 7 flip-flops. at the next clock active edge. The cycle length
The largest decimal number that can be stored in MOD- of the counter is
64 counter is = 63 (a) 8 (b) 16
86. A 4-bit synchronous counter uses flip-flops (c) 6 (d) 12
with propagation delay time of 15 ns each. The Mizoram PSC IOLM -2018, Paper II
maximum possible time required for change of MPPSC Forest Service Exam.-2014
state will be Ans. (d) : 4-Bit Johnson Counter
(a) 15 ns (b) 30 ns
(c) 45 ns (d) 60 ns
TNPSC AE-2008
Initial value– 0101
Ans. (a) : The maximum propagation delay (tpd) for
Reinitialized value – 0001
synchronous counter is given by
The cyclic length of counter is 12.
tpd = td
91. A shift register with the serial output connected
Hence td = 15 ns back to the serial input is a
87. The minimum number of flip-flops needed to (a) Feedback shift register
make mod-2 counter is (b) Shift register counter
(a) 1 (b) 2 (c) Universal shift register
(c) 3 (d) 4 (d) Serial to parallel converter
n
Ans. (a) : N = 2 Ans. (b) : Shift register is a type of digital circuit using
Where N = 2 a cascade of flip flop where the output of one flip flop is
2 = 2n connected to the input of the next.
(Minimum number of flip-flop) n = 1 A shift register with the serial output connected back to
the serial input is a shift register counter.
88. Metastability in D-flip-flop occurs when
92. The output of a JK flip-flop with asynchronous
(a) set-up time of input data is not meet preset and clear inputs is '1'. The output can be
(b) clock period is too large changed to '0' with one of the following
(c) set and reset are active simultaneously conditions by applying
(d) D and Q pins are shortened (a) J = 0, K = 0 and using a clock
TNPSC AE-2008 (b) J = 1, K = 0 and using the clock
Ans. (a) : Metastability in D-flip-flop occurs when - (c) Asynchronous preset input
• The input signal is an asynchronous signal. (d) J = 1, K = 1 and using the clock
• The clock skew/stew is too much (or rise and fall time
are more than the tolerable values). Ans. (d) : The output of a JK flip-flop with
asynchronous preset and clear inputs is '1'. The output
• The combinational delay is such that flip-flop data can be changed to '0' with one of the following
input changes in the critical window. conditions by applying asynchronous preset input.
• The input signal does not meet the setup time. By applying J = 1, K = 1 and using the clock.
89. A 4-bit mod-16 ripple counter uses J-K flip- 93. How many illegitimate states have a
flop having propagation delay of 50ns. The synchronous mod–6 counter?
maximum clock frequency that can be used is (a) 3 (b) 2
(a) 5 MHz (b) 20 MHz (c) 1 (d) 0
(c) 10 MHz (d) 15 MHz Nagaland PSC CTSE (Degree)-2016, Paper-II
MPPSC Forest Service Exam.-2014 TNPSC AE-2013
Ans. (a) : tpd = 50 nsec Ans. (b) : The no. of illegitimate states or unused states
1 in mod-6 counter
f max = = (2n) – mod value
n.t pd
= 23 − 6 = 2
Where,
n = number of flip-flop 94. Which of the following circuits can be used as
parallel to series converter?
1
f max = (a) Digital counter (b) Decoder
4 × 50 × 10−9 (c) De-Multiplexers (d) Multiplexers
f max = 5MHz Nagaland PSC CTSE (Degree)-2016, Paper-II
Ans. (d) : A parallel to series converter is also known as Ans. (c) : The basic SR flip-flop can be constructed by
multiplexer. cross coupling by NOR or NAND gates. Cross coupling
means that output of second gate is connect to the input
of first gate and vice-versa.
A MUX is a combinational logic circuit designed to

switch one of several inputs to a single common output
line. 98. Which of the following is not a sequential
circuit?
95. In S-R latch, when the SET input is made high, (a) flip-flop (b) counter
output Q becomes:
(c) register (d) decoder
(a) 0
(b) application not allowed
Ans. (d) : Counter flip-flop and register all are memory
(c) 1
elements.
(d) no change Hence these are sequential circuits while decoder is a
combination circuit.
Ans. (c) :
99. There is a negative edge-triggered R-S flip-flop
having active-Low R and S inputs and active-
High outputs. Identify the forbidden input
entry
(a) R = 0, S = 1 (b) R = 0, S = 0
(c) R = 1, S = 1 (d) R = 1, S = 0
CP S R Q Q n +1 State Ans. (c) : Truth table of SR flip-flop
1 0 0 0 0 No change
1 0 0 1 1
1 0 1 0 0 Reset
1 0 1 1 0
1 1 0 0 1 Set
1 1 0 1 1 forbidden condition
1 1 1 0 × Indeterminate
1 1 1 1 × 100. The counter that has a modulus of 64 should
0 × × 0 0 No change use a minimum of
0 × × 1 1 (a) Six flip-flops (b) Six J-K flip-flops
From truth table when set (S) input is made high (1), the (c) Six D- flip-flops (d) 64 T flip-flops
output Q becomes 1. Mizoram PSC Jr. Grade -2018, Paper-II
96. A counter displays a sequence of numbers. If a Ans. (a) : We know that–
reading corresponds to the hexadecimal N ≤ 2n
number F52E. The next readings are N = No. of MOD value
respectively n = No. of flip-flop
(a) F 52 F, F 520 (b) F 530, F 531
So, 64 ≤ 2n
(c) F52 F, F 530 (d) F 52 F, F 52 G Hence, minimum no. of n = 6 flip-flops.
101. A four-bit ripple counter and a four-bit
Ans. (c) : For a counter present state synchronous counter are made using flip-flops
+1 +1
= F52E  → F52F  → F530 having a propagation delay of 10 ns each. If the
worst case delay in the ripple counter and the
97. A basic S-R flip-flop can be constructed by synchronous counter be R and S respectively, then
cross-coupling which basic logic gates? (a) R = 10 ns and S = 40 ns
(a) AND or OR gates (b) R = 40 ns and S = 10 ns
(b) XOR or XNOR gates (c) R = 10 ns and S = 30 ns
(c) NOR or NAND gates (d) R = 30 ns and S = 40 ns
(d) AND or NOR gates Mizoram PSC Jr. Grade -2018, Paper-II
Mizoram PSC Jr. Grade-2015, Paper-II GATE - 2003
Ans. (b) : We know that - Ans. (c) : A shift register :- A n-bit shift register can
In ripple counter - be formed by connecting n flip-flop, 8 flip-flops are
Delay time (4 Td) = 4 × 10 required to constrict an 8-bit shift register each flip-flop
= 40 nsec stores a single bit of data.
If synchronous counter are clocked simultaneously, then It can be used to store 1 bit of information.
it worst delay will be equal to 10 ns. 106. A cascaded arrangement of flip-flop, where the
102. Which of the following flip-flops is used as output of one flip-flop drives the clock input of
universal flip-flop the following flip-flop, is known as
(a) JK flip-flop (b) D flip-flop (a) Synchronous counter (b) Ripple counter
(c) RS flip-flop (d) T flip-flop (c) Ring counter (d) Up counter
RPCS Lect.-2011 IES – 2019
Ans. (a) : JK flip flop is used as universal flip flop Ans. (b) : • Ripple counter is a asynchronous counter.
because by using its two inputs i.e, J and K, the other Ripple counter is a sequential circuit used to count the
flip flop can be implemented. clock pulse. It has a series of flip-flop connected
together.
• So, the ripple counter is a cascaded arrangement of
(No change)
(Reset)
flip-flop. The output of flip-flop drives by the clock
(Set) D-F/F T-F/F input of the following flip-flop.
• It is used in ring counter and Johnson counter
(Toggle) Asynchronous counters are used in MOD N ripple
103. Race condition always arises in counter.
(a) synchronous circuit 107. In a 4-stage ripple counter, the propagation
(b) asynchronous circuit delay of a flip- flop is 30 ns. If the pulse width
(c) combinational circuit of the strobe is 30 ns, the maximum frequency
(d) Encoder circuit at which the counter operates is nearly
RPCS Lect.-2011 (a) 9.7 MHz (b) 8.4 MHz
Ans. (b) : The race condition exists in an asynchronous (c) 6.7 MHz (d) 4.4 MHz
circuits when two or more binary state variables change IES – 2018
value in response to a change in an input variable, when Ans. (c) : Given, Propagation delay of flip-flop = 30 ns
unequal delays are encountered, a race condition may Pulse width of strobe = 30 ns
cause the state variable to change in an unpredictable Q 1 flip-flop propagation delay = 30 ns
manner. ∴ 4 flip-flop propagation delay = 4 × 30 ns
104. Master-Salve flip-flop is also called = 120 ns
(a) Pulse triggered flip-flop 1
(b) Latch f ( CLk ) =
max
120 ns + 30 ns
(c) Level triggered flip-flop
(d) Buffer 1
=
IES – 2020 150 ns
Ans. (a) : Master slave flip-flop is also called pulse 1000
triggered flip-flop. Master slave flip-flop complete its = MHz
operation only after the appearance of one full clock 150
pulse, so it is known as pulse trigged flip-flop. fCLk = 6.67 MHz
A master slave flip-flop can be constructed using two 108. For what minimum value of the propagation
JK flip-flop. delay in each flip-flop will a 10 bit ripple
First is called master is driven by the positive clock. counter skip a count, when it is clocked at 10
MHz?
Second is called the slave, driven by negative clock.
(a) 5 ns (b) 10 ns
(c) 20 ns (d) 40 ns
IES – 2018
Ans. (b) : Propagation delay is not affected even if the
counter skips a count (Number of flip-flop remain
same).
CLK ≤ n ( t pd ) ff
Master slave flip-flop used to remove race around f
condition in this condition slave, copy of master.
105. The number of flip-flop required to construct Where,
an 8-bit shift register will be fCLK → Clocked frequency
(a) 32 (b) 16 n → No. of flip-flop
(c) 8 (d) 4
IES – 2019
( t pd )ff → Propagation delay of flip-flop
The maximum input frequency limit,
(t )
pd ff =
TCLK
1
n f max =
Tmin
( t pd )ff = n.f1 = 10 ×101 MHz 1
CLk =
= 10 nsec. 150ns
109. In a master slave JK flip-flop f max = 6.67 MHz
(a) Both master and slave are positive edge- 112. Which one of the following statements best
triggered describes the operation of a negative-edge-
(b) both master and slave are negative edge- triggered D flip-flop ?
triggered (a) The logic level at the D input is transferred to
(c) master is positive edge triggered and slave is Q on NGT of CLK.
negative edge triggered (b) The Q output is always identical to the CLK
(d) master is negative edge triggered and slave is input if the D input is high.
positive edge triggered (c) The Q output is always identical to the D
input when CLK = PGT.
IES – 2018, 2006
(d) The Q output is always identical to the D
Ans. (c) : In a master slave JK flip-flop input.
IES – 2016
Ans. (a) : The logic level at the D inputs transferred to
Q on NTG of clock is best describes the operation of a
negative edge triggered D flip-flop.
• A master-slave flip-flop can be constructed by using

two JK flip-flop.
• In master slave JK flip-flop master is positive edge
triggered and slave is negative edge trigged.
• Master slave JK flip-flop is to avoid the race around CLK D Qn Qn
condition. 0 0 No change No change
110. If the input to a T flip-flop is a 100 MHz signal,
0 1 No change No change
the final output of three T flip-flop in a
cascadeis: 1 0 0 1
(a) 1000 MHz (b) 520 MHz 1 1 1 0
(c) 333 MHz (d) 12.5 MHz Qn+1 = D
IES – 2017 113. A 3-bit ripple counter is constructed using
Ans. (d) : Given, Input frequency fi = 100 MHz three T flip-flop to do the binary counting. The
n=3 three flip-flop have T-input fixed at
for n = 3 bit output frequency of flip-flop (a) 0, 0 and 1 (b) 1, 0 and 1
(c) 0, 1and 1 (d) 1, 1 and 1
Input frequency
= IES – 2016
2n Ans. (d) : 3 bit ripple counter by using T flip-flop.
100 Ripple counter is a Asynchronous counter, in this
= 3
2 counter to perform for counting the flip-flop working
100 under toggle mode.
= = 12.5MHz Hence, 3-bit ripple counter input of the T-flip-flop are
8
(1, 1, 1) to perform the function.
111. What is the maximum input frequency limit of
114. The initial content of a four-bit shift register is
a 3-bit Ripple counter configured around flip- 1000. What is the register content after it is
flops, with inherent propagation delay time tpd shifted four times to the right, with the serial
= 50 ns ? input being 111100?
(a) 6670 MHz (b) 667 MHz (a) 1111 (b) 1100
(c) 66.7 MHz (d) 6.67 MHz (c) 1000 (d) 0011
IES – 2016 IES – 2016
Ans. (d) : T ≥ n.( t pd ) Ans. (b) : In this question initial content is
ff
T = 3 × 50
= 150 nsec.

Input applied serial is, 1. Clock inputs of all the flip-flops of a
synchronous counter are applied from the
same source whereas those in an
asynchronous counter are from in different
After 1st clock - sources
2. Asynchronous counter has ripple effects
whereas synchronous counter has not.
3. Only J-K flip-flops can be used in
After 2st clock - synchronous counter whereas asynchronous
can be designed with any type of flip-flops
(a) 1, 2 and 3 (b) 1 and 3 only
After 3st clock - IES – 2015
Ans. (d) : 1. The clock input of all the individual flip-
flop within the counter are clocked together at the same
time by the same clock signal, so it is called
After 4st clock - synchronous counter. In asynchronous counter different
clock pulses are provided to flip-flops.
2. Synchronous counter does not have a ripple effect
whereas asynchronous counter has a ripple effect.
Hence, the content of shift register is 1100. 3. Any flip-flop can be used for synchronous counter
115. A flip-flop is a and asynchronous counter both.
(a) Combinational logic circuit and edge • According the above definition option (d), 1 and 2
sensitive are true.
(b) Sequential logic circuit and edge sensitive 118. The right side of a state equation represents
(c) Combinational logic circuit and level (a) Next state of flip-flop
sensitive (b) Present state of flip-flop
(d) Sequential logic circuit and level sensitive (c) Present state condition that makes the next
Mizoram PSC IOLM -2018, Paper II stage equal to 1
IES–2016 (d) None of the above
Ans. (b) : • Flip-flop is a sequential logic circuit. Flip- IES – 2014
flop is said to be edge sensitive or edge triggered, it is a Ans. (a) : The state equation of flip-flop
bi-stable multi-vibrator. Flip-flop is a device which
stores a single bit of data. for SR → Q n+1 = S + RQ n
• Flip-flop generate output at the positive or negative for JK → Q n+1 = JQ n + KQ n
edge of the clock signal. for T → Q n+1 = T ⊕ Q n
116. For an SR flip-flop, S and R are made equal to
1. What is the value of Q? for D → Q n+1 = D
(a) Unchanged (b) Clear to 0 • The right side of state equation represents the next
(c) Set to 0 (d) Indeterminate state of flip-flop.
Nagaland PSC 2018, Diploma Paper-II 119. Consider the circuit shown in the figure. The
IES – 2015 expression for the next state Q(t+1) is
Ans. (d) : In SR flip-flop, S and R are made equal to 1.
The value of Q is indeterminate.
(a) xQ(t) (b) x ⊕ Q(t)

(c) xQ(t) (d) x Q(t)
S R Q n +1 State CGPSC SO-14.02.2016
IES – 2014
0 0 Qn Hold state
Ans. (b) : Next state equation of SR flip-flop -
0 1 0 Reset Q ( t + 1) = S + RQ ( t )
1 0 1 Set From logic circuit -
1 1 1 Indeterminate R = x ⊙Q(t)
117. Which of the following statements regarding
S = x ⊕ Q(t)
binary counter are correct?
Q ( t + 1) = x ⊕ Q ( t ) + x ⊙ Q ( t ) Q ( t ) = Q1Q 0 + Q1Q 0
+
= x ⊕ Q ( t ) + x ⊕ Q ( t ) .Q ( t ) Q = Q1 ⊙ Q 0
0
= x ⊕ Q ( t ) 1 + Q ( t )  • Q1+ = J1Q1 + K1Q1

= Q 0 Q1 + Q 0 Q1
Q ( t + 1) = x ⊕ Q ( t ) +
Q = Q1 ⊕ Q0
1
The circuit is effectively working as T flip-flop.
J o = K 0 J1 K1 Q0 + Q1+
120. The outputs Q and Q of master slave S-R flip-
flop are connected to its R and S inputs Q1 Q0 Q0 0 0
respectively. The output Q when clock pulses 1 0 1 1 0
are applied will be
1 1 0 0 1
(a) Permanently 0
(b) Permanently 1 0 0 1 0 0
(c) Fixed 0 or 1 The circuit repeats the value of Q1 after three states
(d) Complementing with every clock pulse Hence, the circuit is a MOD - 3 counter.
UPPSC Poly. Tech. Lect.-22.03.2022, Paper-I 122. In a sequential circuit, the output at any instant
IES – 2014 of time depends.
Ans. (d) : (a) Only on the inputs present at that instant of
time
(b) On past outputs as well as present inputs
(c) Only on the past inputs
(d) Only on the present outputs
IES – 2013, 1994
Ans. (b) : A sequential circuit has a combination of
combination logic circuit and memory.
S R Q Q( t +1)
0 0 0 0
1 0 0 1
0 1 1 0
Sequential circuit produces an output based on current
1 0 0 1 input and past outputs. That means sequential circuit
• During positive clock master flip-flop gives the include memory element those are capable of storing
intermediate output, but slave does not respond. binary. Due to feedback, memory is present.
• During negative clock pulse, slave flip-flop activated
and it copied the previous output of master flip-flop and 123. The output Qn of a J-K flip-flop is zero. It
gives the final output. changes to 1 when a clock pulse is applied. The
• The output (Qn) when the clock applied will be like input Jn and Kn are respectively (X represents
don't care condition)
1→ 0→ 1→ 0→ 1→ 0 ........
Complementing with every clock pulse. (a) 1 and X (b) 0 and X
(c) X and 0 (d) X and 1
121. A circuit consists of two synchronously clocked
J-K flip-flop connected as follows: IES – 2013
J 0 = K 0 = Q 1 , J 1 = Q0 , K 1 = Q 0 Ans. (a) :
The circuit acts as a
(a) Counter of mod 2 (b) Counter of mod 3
(c) Shift-right register (d) Shift-left register
IES – 2014
Ans. (b) :
The output of Qn of J-K flip-flop is zero. It changes to 1

when a clock pulse is applied, the input Jn & Kn are 1
• Q +0 = J 0 Q 0 + K 0 Q 0 and × respectively.

124. If both inputs of S-R NAND Latch are low, the Ans. (c) : An 8 bit ripple up counter module
output will be
2 n = 28 = 256 , Means count = 0 to 255
(a) Unpredictable (b) Toggle
(c) Reset (d) Remain same After 127 clock pulses = 01111111 = 127
UPRVUNL AE-11.06.2014 After 128 clock pulses = 255
IES – 2012 After 129 clock pulses count will be 00000000
Ans. (a) : 130 clock pulses = 00000001
131 clock pulses = 00000010
Hence, the count after 135 clock pulse will be
S R Q n Q n +1 00000110.
0 0 1 1 Not allowed 128. A 4-bit ripple counter consisting of flip-flops
that each have propagation delay of 12 ns from
0 1 1 0 Set
clock to Q output. For the counter to recycle
1 0 0 1 Reset from 1111 to 0000, it takes a total of
1 1 Qn Qn Hold (a) 12 ns
When both inputs of a S-R NAND latch are low, the (b) 24 ns
output of both are high because the output of a NAND (c) 48 ns
gate is high. (d) 26 ns
Hence the output is unpredictable. IES – 2011
125. The highest speed counter is
(a) Asynchronous counter Ans. (c) : For n bit propagation delay = n. ( t pd )
ff
(b) Synchronous counter So for 4 bit ripple counter n = 4
(c) Ripple counter
(d) Ring counter Total delay time = n.( t pd )
ff
IES – 2012 = 4 × 12 ns
Ans. (b) : • Synchronous counter is a highest speed = 48 ns
counter, it is also called parallel counter its operation is 129. Which one of the following circuits converts a
each flip-flop is triggered with same clock signal at
JK flip-flop to T flip-flop?
same time.
• Synchronous counter is faster than Asynchronous
counter.
• It has complex circuit. It is used in moving machine
controlling, alarms clock and multiplexing. (a)
126. A bi-stable multi-vibrator that functions as a
voltage comparator with hysteresis is called
(a) T flip-flop (b) D flip-flop
(c) J-K flip-flop (d) Schmitt trigger
IES – 2012 (b)
Ans. (d) : • A Bi-stable multi-vibrator that function as a
voltage comparator with hysteresis is called Schmitt
trigger. It is an electronic circuit that adds hysteresis to
the input-output transition threshold with the help of
positive feedback.
• Hysteresis means it provides two different threshold
voltage level for rising and falling edge. (c)
• Schmitt trigger is a Bi-stable multi-vibrator and its
output remains in either of the stable states indefinitely.
127. An eight-bit binary ripple UP counter with a
modulus of 256 is holding the count 01111111.
what will be the count after 135 clock pulses? (d)
(a) 0000 0101 (b) 1111 1001 IES –2011, 1995
(c) 0000 0110 (d) 0000 0111 Ans. (a) : Excitation table for T flip-flop convert to J K
IES – 2011 flip flop.
Qn T Q n +1 J K Qn Q n +1 J K
0 0 0 0 × 0 0 0 ×
0 1 1 1 × 0 1 1 ×
1 0 1 × 0 1 0 × 1
1 1 0 × 1 1 1 × 0
Simplifying for T using K-map -
(a) 01011 (b) 01010

(c) 00110 (d) 00101
IES – 2010
Ans. (d) : The characteristic table of J-K flip-flop -
According to above discussion (a) is correct.
130. An X-Y flip-flop, whose characteristic table is

given below is to be implemented using J-K
flip-flop. This can be done making Hence, the sequence of Q is 00101.
132. The shift register shown in the given figure is
initially loaded with the bit pattern 1010.
Subsequently the shift register is clocked, and
with each clock pulse the pattern gets shifted
by one bit position to the right. With each shift,
the bit the serial input is pushed to the MSB
position. After how many clock pulses will the
(a) J = X, K = Y (b) J = X , K = Y content of the shift register become 1010 again?
(c) J = Y, K = X (d) J = Y K = X
IES – 2010
Ans. (d) : Lets we assume,
Qn is the present state and Qn+1 is next state.
X Y Q n Q n +1
0 0 0 1
0 0 1 1
(a) 3 (b) 7
0 1 0 0
0 1 1 1 (c) 11 (d) 15
1 0 0 1 IES – 2010
1 0 1 0 Ans. (b) :
1 1 0 0
1 1 1 0
This equation is compared to J-K flip-flop characteristic
equation -
So, J = Y, K = X
131. The J-K flip-flop shown below is initially reset,
D3+ = D 0 ⊕ D1 ⊕ D 2
so that Q = 0, if a sequence of four clock pulses
is then applied, with the J and K inputs as D +2 = D3
given in the figure, the resulting sequence of D1+ = D 2
values that appear at the output Q starting
with its initial state, is given by D 0+ = D1

Ans. (b) : The next state equation of D flip-flop is -
Qn+1 = D
From the given sequential circuit -
Q1+ = D1 = Q 0
Q +0 = D0 = Q0 + Q1
Hence, after 7 clock pulse will content of shift register

become 1010 again.
133. Analyze the sequential circuit shown below in
figure. Assuming that initial state is 00,
determine what input sequence would lead to
state 11? So, counts state (Q1 Q0) follows the sequence -
135. Which of the following measurements can be

done using a counter ?
1. Pulse duration
2. Interval between two pulses
3. Amplitude of the pulse
(a) 1–1 4. Rise time of a pulse
(b) 1–0 Select the correct answer from the codes given
(c) 0–0 below:
(d) State 11 is unreachable (a) 1 and 2 (b) 2 and 3
IES – 2010 (c) 1 and 4 (d) 2 and 4
Ans. (c) : Input of Flip-flop 'A' IES – 2009
)( ) (
Ans. (a) : Counter can use to measure like pulse
(
J A = QA X Q B X = QA + X ( QB + X ) ) duration and Interval between two pulses. It's also
measure fall time frequency period, phase angle event
K A = QB counting, time interval and pulse with counter we can
Flip-flop B inputs are JB= QA not measure amplitude of the pulse, rise time of a pulse.
K B = XQ A = X + Q A 136. Which of the following capabilities are
available in a Universal shift Register?
Let consider initial state 1-0
1. Shift left 2. Shift right
CL
K
Q
A
Q
B ( )
JA = QA + X (QB + X)QB
KA= JB=Q
A
KB=X
+QA 3. Parallel load 4. Serial add
Select the correct answer from the codes given
1 1 0 0 0 1 1 below:
1 1 (a) 2 and 4 only (b) 1, 2 and 3
Hence the initial sequence 1– 0 leads to state 1–1. (c) 1, 2 and 4 (d) 1, 3 and 4
134. For the circuit shown, the counter state (Q1,Q0) IES – 2009
follows the sequence Ans. (b) : A register that can store the data/shift the data
towards the left and right along with the parallel load
capacity is known as universal shift register. It can
operate both series and parallel modes. Unidirectional
and Bidirectional shift register are combined together to
get the design of universal shift register. It is also
known as parallel in parallel out shift register or shift
register with the parallel load.
(a) 00, 01, 10, 11, 00...... So, the option (b) correct - 1, 2 and 3
(b) 00, 01, 10, 00, 01..... 137. Which of the following circuits come under the
(c) 00, 01, 11, 00, 01...... class of sequential logic circuits?
(d) 00, 10, 11, 00, 10,..... 1. Full adder 2. Full subtractor
GATE - 2007 3. Half adder 4. J-K flip-flop
IES – 2010 5. counter
Select the correct answer from the code given Ans. (c) : (i) Flip-flop is a bi-stable multivibrator it is
below: used to store 1 bit of information. And flip-flop is a
(a) 1 and 2 (b) 2 and 3 sequential circuit.
(c) 3 and 4 (d) 4 and 5 (ii) Race around condition occurs when J-K flip-flop
IES – 2009 both input are 1.
Ans. (d) : Sequential logic circuit is a combination of J=K=1
combinational circuit and memory, sequential circuit When t(pd)ff < tpw then race around condition
produces an output based on current input and previous occur.
input variable. In this condition flip-flop is level triggered.
(iii) Master slave flip-flop used to avoid race around
condition.
It is used to store 1bit of information in flip-flop.
(iv) D flip-flop
EX - Sequential circuit is a flip-flop, counter and

register. Give to, J=D
Whereas full adder, full substractor, Half adder, Half K= D
subtractor is a combinational logic circuit. . Characteristic equation Qn+1 = D
So the option (d) 4 and 5 is correct. It is also known as transparent flip-flop because
138. Which of the following conditions should be gives same data at the output which given at the
satisfied to call an astable multivibrator circuit input.
using discrete components as a digital circuit? 140. Which of the following counter can be used to
1. A flip-flop is always a digital circuit. divide the clock frequency of a microprocessor
2. Only when we assign 1 and 0 to the high and by 5?
low levels of the input, a flip-flop is called a (a) 3 bit counter (b) 5 bit counter
digital circuit. (c) mod 3 counter (d) mod 5 counter
3. Only if the power supply voltage is maintained IES – 2009
at +5V or –5V, it is called a digital circuit. Ans. (d) : Mod-5 Counter - Mod-5 counter can be used
4. Only if it is in IC from, following the to divide the clock frequency of a microprocessor by 5.
technology of IC manufacture, it is called a digital f
circuit. f0 = i
5
Select the correct answer from the codes given It counts five clock pulses, cycling through the count
below: sequence 000, 001, 010, 011, 100 then resent back to
(a) 1 only (b) 2 and 3 000. It is skipped the states 101, 110 and 111.
IES – 2009
Ans. (a) : A flip-flop is always a digital circuit which
store one bit either 0 or 1. We can assign either 0 or 1 to
the high and low levels of the input. It does not
compulsory to the power supply voltage should be
maintained at +5V or –5V.
1. A flip-flop is used to store 1-bit of information.
2. Race-around condition occurs in a JK flip-flop
when both the inputs are 1.
3. Master-slave configuration is used in flip-flops
to store 2-bits of information.
4. A transparent latch consists of a D-type flip-
flop.
Which of the above statements is/are correct?
(a) 1 only (b) 1, 3 and 4
(c) 1, 2 and 4 (d) 2 and 3 only 141. The below circuit illustrates a typical
IES – 2009,2014,2000,1993 application of the JK flip-flops, What does this
ISRO Scientist Engg.- 2006 represent?
Ans. (a) : Characteristic table of J-K flip-flop -
(a) A sift register

(b) A data storage device
(c) A frequency divider circuit
(d) A decoder circuit
IES – 2008
Ans. (c) : The given circuit each flip-flop is divide the
frequency of it input by 2- The next state equation of J-K flip-flop is
f ( f0 ) f Q N +1 = JQ N + KQ N .
( f 0 )QA = in ( f 0 )QB = QA = in 144. Match List-I (circuit) with List-II (Application)
2 2 4
Hence, the given circuit is frequency divider circuit. and select the correct answer using the given
below the lists:
142. What is the frequency of the output Q for the List - I List -II
circuit shown in the figure? A. Ripple up counter 1. Division
B. Synchronous down 2. Multiplication
counter
C. Shift left register 3. To create delay
D. Shift right register 4. Transient states
(a) Twice the input clock frequency Codes:
(b) Half the input clock frequency A B C D
(a) 2 3 4 1
(c) Same as the input clock frequency
(b) 4 1 2 3
(d) Inverse of the propagation delay of the flip- (c) 2 1 4 3
flop. (d) 4 3 2 1
TNPSC AE - 2019 IES – 2006
IES – 2015, 2007 Ans. (d) : • In a ripple counter at a clock edge each data
Ans. (b) : bit much change before the next higher bit can change,
the apparent counts that exist during the clock transition
are called transients state.
• Synchronous down counter to provide delay.
• Multiplication can be done by shift left register.
• Division can be done by shift right register.
The frequency of the output is half of the input clock 145. Match List-I (Type of flip-flop) with List-II
frequency. (Symbol) and select the correct answer using
fin the code given below the lists:
Output frequency f 0 =
2 List-I List-II
Hence, frequency of output Qn is half the input clock A T flip-flop 1
frequency.
143. The characteristic equation of a flip-flop gives
the next state QN+1 in terms of the present state B Level- 2
QN and the inputs. Which one of the following triggered JK
is the characteristic equation of J-K flip-flop? flip-flop
(a) Q N +1 = JQ N + KQ N C Leading edge- 3
Triggered JK
(b) Q N +1 = J + KQ N flip-flop
(c) Q N +1 = KQ N + JQ N
D Trailing edge- 4
(d) Q N +1 = K + JQ N Triggered JK
flip-flop.
IES – 2007, 2006, 2003

A B C D Ans. (b) : • Register is a collection of flip-flop, Register
(a) 1 2 3 4 are logic units used for storing strings of bits, it can be
(b) 2 1 3 4 made of edge triggered. Latch is a electronic logic
(c) 1 2 4 3 circuit with two stable state latch are single bit storage
(d) 2 1 4 3 elements. Latch are made from level triggered flip-flop.
IES – 2005 So this is correct.
Ans. (d) : A - Flip-flop is a single input version of the • Both latch and register are temporary storage devices,
JK FF. so the option 2 is wrong.
• Latches are basic storage elements that is employed
cross coupled feedback connection.
B- Level triggered JK flip-flop

Firstly the master flip-flop is positive level
triggered.
• Latches are cross coupled so the option 3 is correct.

C- Leading edge triggered JK flip-flop. • A register and Latch both are binary storage, so the
this option is wrong from the above statement option (b)
is correct.
148. The total number of 1's in a 15-bit shift register
D - Trailing edge trigged JK flip-flop is to be counted by clocking into a counter
which is present to 0. The counter must have
which one of the following ?
(a) 4–bits (b) 5–bits
146. 12 MHz clock frequency is applied to a (c) 16–bits (d) 6–bits
cascaded counter of modulus-3, modulus-4 IES – 2004
counter, and modulus-5 counter. what are the
lowest output frequency and the overall Ans. (a) : 15 bit shift register having maximum 15 bit in
modulus, respectively ? 1's binary.
(a) 200 kHz, 60 (b) 1 MHz, 60 2n > N
(c) 3 MHz, 60 (d) 4 MHz, 12 Where,
IES – 2005 n → No. of counter in bit
Ans. (a) N → No. of shift register bit.
2 n > 15
2 n ≈ 24
Overall cascade modulus = 3 × 4 × 5
= 60 n≈4
f0 f Hence, to count total number of 1's in a 15 bit shift
Final output frequency = = 0 register, the count must be 4 bits.
3× 4 × 5 M
12 ×1000 149. Consider the following statements :
= × kHz For a master -slave J-K flip-flop,
3× 4 × 5
= 200 KHz 1. the toggle frequency is the maximum clock
frequency at which the flip-flop will toggle
147. Consider the following statements regarding reliably.
registers and latches:
2. the data input must precede the clock
1. Register are made of edge - triggered FFs
whereas latches are made from level- triggering edge transition time by some
triggered FFs. minimum time.
2. Registers are temporary storage devices 3. the data input must remain fixed for a
whereas latches are not. given time after the clock triggering edge
3. A latch employs cross- coupled feedback transition time for reliable operation.
connection. 4. propagation delay time is equal to the rise
4. A register stores a binary word whereas a time and fall time of the data.
latch dose not. Which of the statements given above are
(a) 1 only (b) 1 and 3 correct?
(c) 2 and 3 (d) 3 and 4 (a) 1, 2 and 3 (b) 1, 2 and 4
RPSC Vice Principal ITI-2016 (c) 1, 3 and 4 (d) 2, 3 and 4
IES – 2012, 2009, 2004 IES – 2009, 2004
Ans. (a) : For a master -slave J-K flip-flop- (c) A few combination of inputs and the present
• The toggle frequency is the maximum clock state
frequency at which the flip-flop will toggle reliably. (d) All the combinations of inputs and the present
• The data input must precede the clock triggering state
edge transition time by some minimum time. IES – 2003
• The data input must remain fixed for a given time Ans. (a) : • The Moore machine is a finite state
after the clock triggering edge transition time for machine whose output value are determined only by its
reliable operation. current state.
• Propagation delay is not equal to rise time and fall • It has also 6 tuples (Q, q0, Σ, O, δ, λ) output depends
time. only upon present state. If input change, output also
150. Match List–I (Digital Circuit) with List–II change, more number of states are required.
(Circuit Type) and select, the correct answer • There are less hardware requirement for circuit
using the codes given below the lists : implementation.
List–I List–II 153. A sequence detector is required to give a logical
A. BCD to 7-segment 1. Sequential circuit output of 1 whenever the sequence 1011 is
Decoder detected in the incoming pulse stream.
B. 4-to-1 Multiplexer 2. Combinational Minimum number of flip-flops needed to build
circuit the sequence detector is
C. 4 bit Shift Register 3. Neither (a) 4 (b) 3
sequential nor (c) 2 (d) 1
combinational IES – 2002
n
D. BCD Counter Ans. (c) : Given number of states 2 = 4
Codes : n=2
A B C D So, minimum number of flip-flop n = 2
(a) 2 1 2 1 154. Consider the following circuits (Assume all
(b) 3 2 1 3 gates to have a finite Propagation delay)
(c) 2 2 1 1 1.
(d) 3 1 2 3
IES – 2003
Ans. (c) : • BCD to 7-segment - A display coder is a 2.
combinational circuit which decodes and n-bit input
value.
• A digital decoder IC, is a device which converts one
digital format into another and one of the most
commonly used device for doing this is called the
binary codes decimal (BCD) to 7-segment display 3.
decoder.
• 4 to 1 multiplexer is combinational circuit.
• 4 bit shift register and BCD counter code is a
sequential circuit because its output depends upon 4.
present input and past output.
151. The number of unused states in a 4-bit Johnson
counter is
(a) 2 (b) 4 Which of these circuits generate a periodic
(c) 8 (d) 12 square wave output?
Nagaland PSC (CTSE) Diploma-2017, Paper II (a) 1 and 2 (b) 3 and 4
Ans. (c) : For n bit Johnson counter no. of state is 2n. (c) 2, 3 and 4 (d) 1, 2, 3 and 4
So the , for 4 bit no. of used state = 2 × 4 IES – 2002
=8 Ans. (c) :
And total no. of unused state in Johnson is = 2n –2n
Number of inverter is even so it
= 24 – 2 × 4 is a mono-stable multivibrator.
= 16 – 8 It produces output either 0 or 1.
=8 So, output waveform will not
Unused state in a 4-bit Johnson counter is 8. be a square wave.
152. The output of a Moore sequential machine is a
V0 switches between 0 and 1
function of
with 50% duty cycle. So, the
(a) All present states of the machine
output will be a square wave.
(b) All the inputs
V0 switches a square wave. 158. Symmetrical square wave of time period
100 µs can be obtained from square wave of
V0 is a square wave as time period 10 µs by using a
capacitor keeps charging and (a) divide by – 5 circuit
discharging. So, its output will
(b) divide by – 2 circuit
be a square wave.
(c) divide by – 5 circuit following by a divide by
155. The 54/74164 chip is as 8-bit serial-input-
–2 circuit
parallel-output shift register. The clock is 1
MHz. The time needed to shift an 8-bit binary (d) BCD counter
number into the chip is IES – 1999
(a) 1 µs (b) 2 µs Ans. (c) : Given, Time period (T) = 100 µs
(c) 8 µs (d) 16 µs 1
Input frequency (fi) =
IES – 2001 T
Ans. (c) : • In SIPO condition, the data is given in serial 1
= = 100 kHz
form at the input and output is taken in the parallel 10 × 10−6
form. 1
• So, the total time for shift as 8 bit binary number into Output frequency (f0) =
100 × 10−6
the chip is
Total time = nT f 0 = 10 kHz
CLK
1 Divide by fi 100
= = 20kHz Divide by f0 =
20
=10kHz
= 8× fi =100kHz
 → 
5 5
→ 
2
→
FCLK Input
-5circuit -2circuit output
1
= 8× 159. A three-bit shift register is shown in the given
106 figure
T = 8 µsec.
156. A ring counter consisting of five flip-flop will
have
(a) 5 states (b) 10 states
(c) 32 states (d) infinite states
IES – 2000 To have the content '000' again. the number of
Ans. (a) : • In a ring counter the number of states clock pulses required would be
depend upon the number of flip-flops. (a) 3 (b) 6
• The ring counter with "n" flip-flop will have n states. (c) 8 (d) 16
• Hence, ring counter consisting of 5 flip-flop will have IES – 1999
5 state. Ans. (b) : The figure represents Johnson ring counter. n
157. A T flip-flop function is obtained from a JK bit shift register will be mod 2n counter. Here n=3, so
flip-flop. If the flip-flop belongs to a TTL that register back to the initial stage after 6th clock
family, the connection needed at the input must
pulse.
be
(a) J = K = 1 (b) J = K = 0 160. In a negative edge triggered J-K flip-flop, in
(c) J = 1 & K = 0 (d) J = 0 & K = 1 order to have the output Q state 0, 0 and 1 in
TSTRANSCO AE-2018 the next three successive clock pulses, the J-K
IES – 2000 input states successive clock pulses , the J-K
input states required would be respectively
Ans. (a) : • Characteristic equation Q n +1 = TQ n + TQ n .
(a) 00, 00 and 10 (b) 00, 01 and 11
• The T flip flop may be obtain the J-K FF by making
(c) 00, 10 and 11 (d) 01, 10 and 11
both the inputs are the same.
That is J=K=1 . IES – 1999
Ans. (a,b) :
• In TTL family the FF, logic 1 input corresponding

floating input
J=K=1
After 37 clock pulse MOD - 16 = 5 state
J K Q Whereas it is a down counter so it will be 5 state down
1st pulse 2nd pluse 3rd pulse
0 0 0 No change from 0110 =
↓ ↓ ↓ 0110 – 0101 = 0001
0 1 0 Reset
0 0 1 163. Consider the following conditions :
1 0 1 Set
00 / 00 00 / 01 10 /11 1. t p < ∆t
1 1 − Toggle
Hence, both option (a,b) are correct. 2. ∆t < T
161. The characteristic equation of an SR flip-flop 3. t p > ∆t
given by 4. ∆t > T
(a) Q n +1 = S + RQ n (b) Q n +1 = RQ n + SQ n Where tp = pulse width, ∆t = propagation delay
(c) Q n +1 = S + RQ n (d) Q n +1 = S + RQ n and T = clock period. The race around
IES – 1999 condition in the flip-flop can be avoided if
conditions
Ans. (a) : (a) 1 and 2 are satisfied (b) 1 and 4 are satisfied
(c) 2 and 3 are satisfied (d) 3 and 4 are satisfied
IES – 1998
Ans. (a) : Race around condition occur when -
1. J = K = 1
2. ∆t < T
it is occur only in level trigger.
R S Qn Q( n +1) To avoid race around condition, the clock duration
become lesser than propagation delay.
0 0 0 0
1. tp < ∆t
0 0 1 1 2. ∆t < T
0 1 0 1 Hence, option (a) is correct.
0 1 1 1 164. For the design of sequential circuit having nine
states MINIMUM number of memory elements
1 0 0 0
required is :
1 0 1 0 (a) 3 (b) 4
1 1 0 × (c) 5 (d) 9
IES – 1997
1 1 1 ×
Ans. (b) : Given, 9 states in sequential circuit.
If the number of memory element in sequential circuit is
n the total number of states will be
= 2n
9 = 2n {23 = 8}
2 ≈2
4 n
n≈4
Q( n +1) = S + RQ Hence, The number of memory elements required is 4.
165. The schematic shown in the figure represents
162. The initial state of MOD.16 Down counter is
0110. After 37 clock pulses, the state of the
counter will be
(a) 1011 (b) 0110
(c) 0101 (d) 0001
IES – 1999
(a) Divide by seven counter.
Ans. (d) : MOD of counter = 16
(b) Divide by five counter.
Initial state = 0110
(c) Binary coded decimal counter
After each 16th clock pulse initial state will be repeat
(d) Divide by twelve counter
So clock 32 = 0110
33rd = 0111 IES – 1997
34th = 1000 Ans. (c) : The above given fig. represents binary coded
35th = 1001 decimal counter. BCD or decade counter circuit a
36th = 1010 binary coded decimal is a serial digital counter that
37th = 1011 count 0 to 9 and the sequence repeats again.

166. Shift register with associated waveform is 169. The input pulses to the different stages of the
shown in the following figure. Which of these counter shown in the following figure must be
is/are correct? of
(a) Constant frequency and constant width

(b) Constant frequency but variable width
(c) Variable frequency but constant width
(a) X1 alone (b) X2 alone (d) Variable frequency as well as variable width
(c) X3 alone (d) X1 X2 and X3 IES – 1996
IES – 1997 Ans. (d) : The above given circuit is a mod-8 ripple
Ans. (a) : The above given fig. is a serial-in-serial-out counter (with 3 flip-flops)
shift register. The output waveform of this circuit will Input frequency of first FF = f0
be as according to the waveform given in option 'a' Time duration = T0
only.
f
167. A 4-bit binary ripple counter uses flip-flops Output frequency at Q 0 = 0
with a propagation delay time of 25 ns each . 2
The maximum possible time required of change Time duration = 2T0
of state will be f
(a) 25 ns (b) 50 ns Output frequency at Q1 = 0
4
(c) 75 ns (d) 100 ns We can see that the input clock pulse to different flip-
IES – 1997 flop of counter has variable frequency and the variable
Ans. (d) : Propagation delay for each flip flop = 25 ns time duration i.e. variable pulse width.
for 4 bit binary ripple counter Time duration = 4T0
The maximum total time = n × t(pd)
170. An input frequency of 12 KHz is applied to the
T = 4 × 25 ns
J–K flip–flops arrangement shown in the given
T = 100 ns.
figure. The resulting output frequency will be
168. State transition table and state transition
(a) 24 KHz (b) 12 KHz
diagrams are the part of the design step in the
case of (c) 6 KHz (d) 3 KHz
(a) Combinational circuits
(b) Amplifier circuits
(c) Delay circuits
(d) Sequential circuits
Nagaland PSC (Diploma) 2018, Paper-II
IES – 1995
IES – 1996
Ans. (d) : The above given counter is ripple counter
Ans. (d) : • State transition and state transition
diagrams are the part of the design step in the case of where
sequential circuit. no. of flip – flop = 2
• State transition table - In sequential logic, A state In ripple counter frequency of n flip flop the output
transition table is a table showing what state (state frequency will be
of the case of non deterministic finite automation) a Input frequency
finite-state machine will move to based on the f out =
M
current state and other inputs.
where M = Modulus of the counter
• State transition diagram - State transition
diagrams describes all of the states that an object f
f o = inn
can have, the event under which an object state 2
(transition). It represent the value of object attributes 12 KHz
at a given time. f=
22
• Initial state - Represent state when the system is
started. 12 × 103
=
• Final state - Represent the status of system at the 4
end of operation. = 3 KHz

171. Which of the following characteristics are 173. The block diagram shown in the given figure
necessary for a sequential circuit ? represents
1. It must have at least six gates.
2. It must have some feedback.
3. Its output should depend on some past value.
Codes:
(a) 1, 2 and 3 (b) 1 and 2
(c) 2 and 3 (d) 1 and 3
IES – 1995
Ans. (c) : • Sequential circuit produces on output based (a) Modulo-3 ripple counter
on current input and previous input variables. That (b) Modulo-5 ripple counter
(c) Modulo-7 ripple counter
means sequential circuit include memory elements that
(d) Modulo-7 synchronous counter
are capable of storing binary information. Example -
IES – 1994
flip flop/latch.
Ans. (c) :
• Hence, it must have same feedback, it output should

depend on some post value codes.
172. Given A=1, B=1, Qn=0 and Pn= 1, what will be The given figure is a ripple counter because Q0 of 1st
nd
output Qn+1 and Pn+1 when the clock input flip-flop is connected to the clock of 2 flip-flop.
(CLK) is applied? Q0 is LSB and Q2 is MSB because clock pulse is
applied in first flip-flop Q0.
The counter will count 000 to 110 (7 states)
So, it is a mod-7 ripple counter.
All flip-flop will be clear at Q0=Q1=Q2=1
It is a MOD-7 ripple counter.
174. A 4-bit synchronous counter uses flip-flops
with propagation delay time of 15ns each. The
maximum possible time required for change of
(a) Qn+1 = 0, Pn+1 = 0 (b) Qn+1 = 0, Pn+1 = 1 state will be
(c) Qn+1 = 1, Pn+1 = 0 (d) Qn+1 = 1, Pn+1 = 1 (a) 15 ns (b) 30 ns
IES – 1995 (c) 45 ns (d) 60 ns
Ans. (c) :
IES – 1994
Ans. (a) : • In synchronous counter clock input of all
the individual flip flop within the counter all clocked
together at the same time by the same clock signal.
Tpd = td
where, td = Propagation delay of each FF.
• So the maximum possible time
td = 15 ns for each flip-flop
At initial state A = B = 1, Qn = 0, Pn = 1 • Hence, the total required time for 4-bit synchronous
When clock = 1 (high) counter will be 15 ns.
Then, output of gate '1' = 0 and 175. A divide-by-78 counter can be realized by using
output of gate '2' = 1 (a) 6 no's of mod-13 counters
So, the output of gate '3' = 1 and (b) 13 no's of mod-6 counters
The output of gate '4' = 0 (c) One mod-13 counter following by one mod-6
counters
Hence, for input clock Qn + 1 = 1
(d) 13 no's of mod-13 counters
Pn + 1 = 0 IES – 1994
Ans. (c) : • In MOD- N counter, if applied input Ans. (a) :
frequency is "f" the output frequency is f/N.
f f
Foutput = =
13 × 6 78
One mod-13 counter following by one mod-6 counters.
176. Which one of the following circuits converts an After the analysis of the above graph, It is clear that
RS Flip-Flop to T Flip-Flop? output is High only when input A = B = 1(High) or
A = B = 0 (Low)
Output is low when,
A = 0 (Low) and B = 1 (High)
A = 1 (High) and B = 0 (Low)
Hence, the black box is an EX-NOR logic circuit or
coincidence logic circuit.
178. Which one of the following can be used to
change data from spatial code to temporal
code?
GATE-1991 (a) Shift registers
IES – 1994 (b) Counters
(c) A/D converters
Ans. (c) : Excitation table -
(d) Combinational circuits
Q Q n +1 T S R Nagaland PSC 2018 Diploma, Paper-II
0 0 0 0 × IES – 1993
0 1 1 1 0 Ans. (a) : • Data can be changed from spatial code to
temporal code by shift register.
1 0 1 0 1
(PISO) shift register convert spatial code to temporal
1 1 0 × 0 code.
K-map for S and R - • SIPO shift register convert temporal code to spatial
code.
179. Which of the following is not a characteristic
of a flip-flop?
(a) The flip-flop is a bi-stable device with only
two stable states
(b) The flip-flop has two input signal
(c) The flip-flop has two output signal
(d) The outputs are complement of each other.
According to above discussion -
IES – 1993
Ans. (b) : • The memory element in a sequential circuit
are called flip-flops. Flip flop has two output, one is the
normal value and other is the complement value of the
stored bit.
• Flip flop is a bi-stable device with only two stable
state. SR JK flip flop have two inputs while D and T
177. If the input and signals of a black box are as flip-flop have single input,
given in the following figure then the black box • So we can say that the flip-flop has two or one input
is a/an signal.
Hence, according to above discussion option (b) is
Input A correct.
180. Which of the following flip-flop cannot be
Input B converted to D-type (delay) flip-flop
(a) S–R flip-flop
output (b) J–K flip-flop
(a) Coincidence circuit (b) EX OR circuit (c) Master slave flip–flop
(c) JK Flip-Flop (d) R-S Flip-Flop (d) None of the above
IES – 1994 IES – 1992
Ans. (d) : • SR, JK and T flip can be converted by D
CLK J0 K0 J1 K1 Q 0 Q1
flip-flop. Above all flip flop can be observe by
execution table. Initially 0 1 0 1 0 0
• Master slave flip flop is also implemented using D flip 1st CLK 0 1 0 1 0 0
flop. nd
2 CLK 0 1 0 1 0 0
• So all flip-flop converted by excitation table. From the above analysis it is clear that the state of
• Hence, the option (d) is correct. counter will not change by applying of clock pulse. The
181. The difference between sequential and circuit does not works as a counter.
combinational circuit is that 183. Which type of counter is shown in the figure
(a) Combinational circuits store bits
(b) Combinational circuits have memory
(c) Sequential circuits store bits
(d) Sequential circuits have memory
Nagaland PSC 2018 Diploma, Paper-II (a) Synchronous (b) Johnson
IES – 1992 (c) Ring (d) None
Ans. (c & d) : IES – 1992
Combinational Sequential circuit Ans. (d) :
circuit
1 Combinational circuit 1 Sequential circuit
depend on only which output depend
present input. on present input and
previous output. Given,
2 It has no 2 It has feedback • Above counter is Asynchronous (ripple down
feedback/memory. path/memory. counter).
3 It has better 3 It is slower than •In Asynchronous counter we do not use universal
performance than combinational clock.
sequential circuit, it is circuit. It has no •So the synchronous counter has synchronous counter
faster than sequential. better performance. has one global clock which drives each flip-flop. So
4 Elementary building 4 It elementary output change in parallel.
blacks for building blocks are • Johnson and Ring counter is a synchronous counter.
combination circuit flip-flop. • Hence,According to option (d) is correct.
are logic gate. 184. What will be the state of the output after the
5 It is used for 5 It is mainly used for third clock cycle?
arithmetic as well as storing data.
Boolean operation.
• Hence, option (c) and (d) is correct.
182. The circuit shown below is :
QA QA
(a)
LO LO
(b) HI LO
(c) LO HI
(a) 2:1 scalar (d) HI HI
(b) 4:1 scalar IES – 1991
(c) Up-down counter Ans. (d) : At initial state T = 1
(d) None Then QA = 0, QB = 0
IES – 1992
Ans. (d) : CLK TA TB QA QB
Initial 1 1 0 0
1 1 1 1 1
2 1 1 0 0
3 1 1 1 1
Hence, After 3rd clock cycle the output
Given that J0 = Q1, J1 = Q0 QA = 1 (High)
K 0 = Q1 , K1 = Q 0 QB = 1 (High)

185. Find radix of the system shown in the figure D2 = A ⊕ S
below:
= Q1 ⊕ S
D 2 = Q1S + Q1S − − − − − − (i)
• for Ex-NOR gate
D2 =A S
(a) 2 (b) 4 D 2 = AS + AS − − − − − (ii)
(c) 6 (d) 8 Comparing equation (i) & (ii) we find-
IES – 1992 A = Q1
Ans. (a) : At initial state T = 1
Hence, Input A is connected to Q1
then QCQBQA = 000
st
After applying clock pulse (1 clock) 187. A finite state machine (FSM) is implemented
QCQBQA = 111 using the D flip-flops A and B, and logic gates,
For next clock pulse (2nd clock) as shown in the figure below. The four possible
QCQBQA = 000 states of the FSM are QAQB = 00, 01, 10 and 11.
After next above analysis it is clear that the given circuit
has only two stable states.
Hence, the radix of the system = 2
186. The digital logic shown in the figure satisfies
the given state diagram when Q1 is connected
to input A of the XOR gate.
Assume that XIN is held at constant logic level

throughout the operation of the FSM. When
the FSM is initialized to the QAQB = 00 and
clocked, after a few clock cycles, it starts
cycling through
(a) all of the four possible states if XIN = 1
(b) three of the four possible if XIN =0
(c) only two of the four possible states if XIN =1
(d) only two of the four possible states if XIN = 0
GATE – 2017, Set-1
Ans. (d) : from the given circuit:-
Suppose the XOR gate is replaced by an XNOR = Q A ⊕ Q B = Q +A
gate. Which one of the following options
preserves the state diagram ? = Q A .X in = Q +B
(a) Input A is connected to Q 2 Now we assume X in = 0
(b) Input A is connected to Q2
(c) Input A is connected to Q1 and S is Q +B = 1
complemented Present state Next state
(d) Input A is connected to Q1 QA QB Q +A = Q A ⊕ Q B Q +B = 1
GATE – 2014, Set-1 0 0 0 1
Ans. (d) : In the given circuit – 0 1 1 1
1 0 1 1
1 1 0 1
• there is only two unique state of the four possible

state if Xin= 0
When Ex-OR gate is replaced by Ex-NOR gate, then Now we assume Xin = 1
we find A = ?
• for Ex-OR gate- Q +B = Q A

Present State Next state
+
QA QB Q = QA ⊕ QB
A Q +B = Q A
0 0 0 1
0 1 1 1 Combining the both cases -
1 0 1 0
1 1 0 0
• There is only three unique state of the four possible

state if X in = 1 Hence, the correct option is 'b'.
• Hence, according to option (d) is correct. 189. The 74157 is a
188. The state transition diagram for the circuit (a) Dual 4 to 1 Mux
shown is (b) Quad 2 to 1 Mux
(c) Quad D type flip-flop
(d) Octal D type flip-flop
Ans. (b) : 74157 is a quad 2 to 1 high performance
multiplexer/demultiplexer bus switch.
74153-dual 4 to 1 MUX
74157- Quad 2 to 1 MUX
74175- Quad D type flip-flop
7432-Quad 2 input OR gate
7400- Quad 2 input NAND gate
7486-Quad 2 input EX-OR gate
7408- Quad 2 input AND gate
190. Time taken to enter a byte in parallel shift
register using clock of 5 MHz is_________.
(a) 0.2 micro seconds
(b) 5 micro seconds
(c) 40 micro seconds
(d) 1.8 micro seconds
UPRVUNL AE-2016
Ans. (a) : Total time taken can be given as-
1
T=
f
Given, f= 5MHz
1 1
∴T= = = 0.2 × 10−6
GATE - 2019 5MHz 5 ×106
Ans. (b) : (i) we assume select line A= 0 = 0.2 µ sec
Q n +1 = D 191. The circuit given below is a
Q n +1 = 1
(ii) Now assume select line A = 1
Q n +1 = D = Q n
Q n +1 = Q n
(a) J-K Flip-flop
Present state Next state Present state Next State
(b) Johnson's counter
Qn Q n +1 = 1 Qn Q n +1 = Q n (c) R-S latch
0 1 0 1 (d) None of above.
1 1 1 0 TN TRB AE-2017

Ans. (c) : Ans: (c)
A B Q n +1
0 0 Q n (Previous)
Characteristics equation of J-K flip-flop
0 1 0
1 0 1
• Q +0 = J 0 Q 0 + K 0 Q 0
1 1 Nonvalid
= Q1 Q0 + 1 Q 0
• The above given circuit is SR latch circuit.
Q +0 = Q1 + Q 0
• SR latch is also called as set/ reset latch
• Q1+ = J1 Q1 + K1 Q1
• It has two input S and R and two output Qn and Q n .
= Q0 Q1 + 1Q1
192. A switch-tail ring counter is made by using a
+
single D flip-flop. The resulting circuit is a Q = Q 0 Q1
1
(a) SR flip-flop (b) JK flip-flop Present State Next State

(c) D flip-flop (d) T flip-flop Q0 Q1 Q +0 Q1+
0 0 1 0
GATE - 1995
0 1 0 0
Ans. (d) : Switch tail ring is also called Johnson 1 0 0 1
counter or twisted ring counter so we use single D flip
1 1 1 0
flop the inverted operation of D is given to input as
itself so it behave like T FF.
In switch tail ring counter using single D FF it Q is There is three unique state, so circuit is MOD – 3
connected to its input by AND gate so its becomes T Counter,
FF. Hence,
(k = 3), option ‘c’ is correct.
194. In fig. below, A = 1 and B = 1. The input B is

now replaced by a sequence 101010..... , the
outputs x and y will be
When enable = 1 then output is toggled.
Present state Present input Next input
Q D=Q Q+
0 1 1
1 0 0 (a) fixed at 0 and 1, respectively
(b) x = 1010 ...... while y = 0101 .....
Next state = Present state (c) x = 1010 ...... and y = 1010 ......
193. Figure shows a mod-K counter, Here K is equal (d) fixed at 1 and 0, respectively
to GATE - 1998
Ans. (a) :
The given circuit,

(a) 1 (b) 2 when we apply A = B = 1
(c) 3 (d) 4 The x=y
GATE - 1998 y=x

A = 1 and B = 0 (a) 0.833 kHz
y=1 (b) 1.0 kHz
x=0 (c) 0.91 kHz
A = 1 and B = 1 (d) 0.77 kHz
x=y=0 GATE - 2000
y = x =1 Ans. (b) : The above counter a mod-10 counter output
frequency of counter
x is fixed at '0'
f
y is fixed at '1' f 0 = in
Hence, according to above discussion option (a) is N
correct. where,
195. A sequential circuit using D Flip-Flop and logic N →MOD –N Value
gates is shown in the figure, where X and Y are f = 10KHz = 1kHz
0
the inputs and Z is the output. The circuit is 10
197. For the ring oscillator shown in the figure
propagation delay of each inverter is 100 pico
sec. What is the fundamental frequency of the
oscillator output ?
(a) S-R Flip-Flop with inputs X = R and Y = S (a) 10 MHz (b) 100 MHz
(b) S -R Flip-Flop with inputs X = S and Y = R (c) 1 GHz (d) 2 GHz
(c) J - K Flip-Flop with inputs X = J and Y =K GATE - 2001
(d) J - K Flip-Flop with inputs X = K and Y = J Ans. (c) : T = ntpd
GATE - 2000 T = 5 × 100 P sec.
Ans. (d) :
1
Frequency of ring oscillator (f) =
2T
1
=
2 × 500 × 10−12
According to above figure 1
= −9
D = XZ + ZY .......... (i) 10
When we convert D flip flop to J K flip-flop f = 1GHz
D = JQ + KQ ......... (ii)
Compare equation (ii) &(i) 198. The digital block in the figure is realized using
Y = J and X = K two positive edge triggered D-flip-flops.
Assume that for t < Q1 = Q2 = 0. The circuit in
196. In the figure, the J and K inputs of all the four
the digital block is given by :
flip-flops are made high The frequency of the
signal at output Y is

(a) P - 3, Q - 2, R - 1 (b) P - 3, Q - 1, R - 2
(c) P - 2, Q - 1, R - 3 (d) P - 1, Q - 2, R - 2
GATE - 2004
Ans. (b) : P. Shift register - Shift register is a digital
memory. Shift register commonly used in converters
that from state parallel data to serial data and serial data
to parallel data convert.
Q - Counter - counter is a sequential circuit. A digital
circuit which is used to counting pulse, it is also used in
frequency division. Frequency division uses divide by-
2 toggle flip flops binary counter to reduce the
frequency of the output clock signal.
R-Decoder - Decoder is a combinational logic circuit
which have n input the output will be 2n. It is used in
addressing in memory conversion.
201. In the modulo- 6 ripple counter shown in the
figure, the output of the 2-input gate is used to
clear the J-K flip-flops.
GATE - 2001
Ans. (c) : The given above diagram is two negative
edge triggered (b, d) are possible whereas option (c) is
positive edge triggered,
Hence, the option (c) is correct.
199. A 0 to 6 counter consists of 3 flip flops and a The 2-input gate is
combination circuit of 2 input gate(s). The (a) a NAND gate (b) a NOR gate
combination circuit consists of (c) an OR gate (d) an AND gate
(a) one AND gate GATE - 2004
(b) one OR gate Ans. (c) :
(c) one AND gate and one OR gate
(d) two AND gates
GATE - 2003
Ans. (d) :
• 0 to 6 counter must be reset when it count 7 (1 1 1)
Cleared input is zero

the output of 2 gate = 0
to cleared the flip flop
This combination circuit consists of two AND gates.

200. Choose the correct one from among the
alternatives A, B, C, D after matching an item
from Group-1 with the most appropriate item
in Group-2 unused state CBA = 110
Group-I Group-II Output 2 input gate = 0
P. Shift register 1 Frequency CBA = 00A
division C=1=0
Q. Counter 2 Addressing in B=1=0
memory chips Whenever both input are zero the output are must be
R. Decoder 3 Serial to zero.
parallel data This function can be done only OR gate.
conversion Hence, the option (c) is correct.

202. The present output Qn of an edge triggered JK (a) S = 0 C0 = 0 (b) S = 0 C0 = 1
flip-Flop is logic 0. If J = 1, then Qn +1 (c) S = 1 C0 = 0 (d) S = 1 C0 = 1
(a) cannot be determined (b) will be logic 0 GATE - 2006
(c) will be logic 1 (d) will race around Ans. (d) : In the given circuit initially
GATE - 2005 Q1 = Q 2 = Q3 = 0
Ans. (c) : Excitation table for J K flip flop - S =0 C =1
o 0
• Apply 1st Clock pulse:-
D1 = 1 Q1 = D1 = 1
D2 =1 Q2 = D2 = 1
C0 = 1 D3 = 1 Q3 = D 2 = 1
Above excitation table Sum (S) = 1+1+1
when Qn edge triggered of J-K flip-flop = 0 =1
and J = 1 Carry (C0) = 1
then Qn+1 = 1 • Apply 2nd Clock pulse:-
Hence, the Qn+1 will be logic (1). D1 = 1 Q1 = D1 = 1
203. The given figure shows a ripple counter using D2 = 1 Q 2 = D 2 = 1
positive edge triggered flip-flops.
If the present state of the counter is Q2Q1Q0 = C 0 = 1 D 3 = 1 Q 3 = D3 = 1
011, then its next state (Q2Q1Q0) will be Carry (C0) = 1
Hence, the option ‘d’ is correct
205. Two D-flip-flops, as shown below, are to be
connected as a synchronous counter that goes
through the following Q1Q0 sequence
00 → 01→ 11 → 10 → 00 → .........
(a) 010 (b) 100 The inputs D0 and D1 respectively should be
(c) 111 (d) 101 connected as
GATE - 2005
Ans. (b) :
Present State Present Input Next State (a) Q1 and Q0 (b) Q0 and Q1
Q 2 Q1Q 0 T2 T1T0 Q +2 Q1+ Q0+ (c) Q1Q0 and Q1Q 0 (d) Q1 Q0 and Q1Q0
011 111 100 GATE - 2006
Where Q0 = 1 (triggered T1) Ans. (a) :
Q1 = 1 (triggered T2)
204. For the circuit shown in the figure below, two
4-bit parallel-in serial out shift registers loaded
with the data shown are used to feed the data to
a full adder. Initially all the flip-flops are in
clear state. After applying two clock pulses, For sequential circuit
The outputs of the full adder should be - Next state = (Present state + Present input)
Present State Next State Flip −Flop(input)
Q1 Q0 Q1+ Q0+ D1 D0
m0 0 0 0 1 0 1
m1 0 1 1 1 1 1
m3 1 1 1 0 1 0
m2 1 0 0 0 0 0
{In D flip - flop = Q}
D1 = F ( Q1 ,Q0 ) = m1 + m 2 = Q1Q0 + Q1Q0 = Q 0
D 0 = F ( Q1 ,Q0 ) = m 0 + m1 = Q1Q0 + Q1Q0 = Q1
From the above discussion
D1(FF) = Q0
D0(FF) = Q1
Option (a) Q1 and Q0 is correct.
206. The following binary values were applied to the
X and Y inputs of the NAND latch shown in the
figure in the sequence indicated below : Which of the following waveforms correctly
X = 0, Y = 1; represents the output at Q1 ?
X = 0, Y = 0;
X = 1, Y = 1;
The corresponding stable P, Q outputs will be
(a) P = 1, Q = 0; P = 1, Q = 0; P = 1, Q = 0 or P =
0, Q = 1
(b) P = 1, Q = 0; P = 0, Q = 1 or P = 0, Q = 1; P =
0, Q = 1
(c) P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 0 or P =
0, Q = 1
GATE - 2008
(d) P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 1
GATE - 2007 Ans. (b) :
CLK
Ans. (c) : • X = 0, Y=1
t1
T
Q0
t1+∆T
2T
Q1
• X= 0, Y = 0
t1+2∆T
4T
th
1
The output of flip-flop is   of clock frequency and
4
• X= 1, Y=1 2∆T is the propagation delay of 2-flip-flop.
Hence, option 'b' is correct.
208. For the circuit shown in the figure, D has a
transition from 0 to 1 after CLK changes from
1 to 0. Assume gate delays to be neglible
• Hence correct option is ‘c’ correct.

207. For each of the positive edge-triggered J-K flip-
flop used in the following figure, the
propagation delay is ∆T.

Which of the following statements is true ? If Input (P1,P2) are first made (0,1) and then after few
(a) Q goes to 1 at the CLK transition and stays at second made (1,1)
1. Corresponding stable output (Q1, Q2 )
(b) Q goes to 0 at the CLK transition and stays at • for NAND • for NOR
0. first (1,0) then (1,0) first (1,0) then (0,0)
(c) Q goes to 1 at the CLK transition and goes to 210. What are the counting states (Q1, Q2) for the
0 when D goes to 1. counter shown in the figure below ?
(d) Q goes to 0 at the CLK transition and goes to
1 when D goes to 1.
GATE - 2008
Ans. (c) :
(a) 11, 10, 00, 11, 10, .......

(b) 01, 10, 11, 00, 01, .......
(c) 00, 11, 01, 10, 00, .......
(d) 01, 10, 00, 01, 10, .......
GATE - 2009
From the circuit analysis are above given figure it is
clear that Q goes to 1 at the CLK transition and goes to Ans. (a) : All the flip-flop have common clock
0 when D goes to 1. pulse so this given circuit is synchronous counter
209. Refer to the NAND and NOR latches shown in • Q1+ = J1Q1 + K1Q1 • Q +2 = J 2 Q 2 + K 2 Q 2
the figure. The inputs (P1, P2) for both the = Q 2 Q1 + Q 2 Q1 = Q1 .Q 2 + 1Q 2
latches are first made (0, 1) and then, after a
few seconds, made (1, 1). The corresponding Q1+ = Q1 Q2 Q +2 = Q1Q 2
stable outputs (Q1, Q2) are
Present State Next state
+
Q1 Q2 Q = Q2
1 Q1 Q +2 = Q1 .Q 2
0 0 1 1
0 1 0 0
1 1 0 0
(a) NAND : first (0, 1) then (0, 1) NOR: first (1,
0) then (0, 0) 1 1 1 0
(b) NAND : first (1, 0) then (1, 0) then (1, 0)
NOR: first (1, 0) then (1, 0)
(c) NAND: first (1, 0) then (1, 0) NOR: first (1, The sequence will be 11,10,00,11,10
0) then (0, 0) 211. Assuming that all flip-flops are in reset
(d) NAND: first (1, 0) then (1, 1) NOR: first (0, conditions initially, the count sequence
1) then (0, 1) observed at QA in the circuit shown is
GATE - 2009
Ans. (c) :
(a) 0010111... (b) 0001011...

(c) 0101111... (d) 0110100...
GATE - 2010
Ans. (d) : As we know –
D flip-flop follow the input D to Q (at CLK) from the
given figure-
D A = QB ⊕ QC
DB = QA
DC = Q B

In this circuit, the race around
(a) does not occur
(b) occurs when CLK = 0
(c) occurs when CLK = 1 and A = B = 1
(d) occurs when CLK = 1 and A = B = 0
GATE - 2012
Ans. (a) :
the sequence of QA will be :-

Q n = 0110100
212. Two flip-flops are connected as a synchronous
counter that goes through the following QBQA • In this circuit A = S
B=R
sequence 00 → 11 → 01 → 10 → 00 → ...
• So this circuit is SR flip-flop.
The connections to the inputs DA and DB are • Race around condition occurs in the JK flip-flop.
(a) QA = QB , DB = QA When,
(b) D A = Q A , D B = Q B J=K=1
• Hence the race around condition does not occur in the
(c) D A = (Q A Q B + Q A Q B ), D B = Q A SR flip-flop.
(d) D A = (Q A Q B + Q A Q B ), D B = Q B 214. The state transition diagram for the logic
circuit shown in
Nagaland PSC (CTSE) Diploma - 2017, Paper -II
GATE - 2011
Ans. (d) : In D- flip-flop –
Q n +1 = D n
The given sequence (Q B Q A ) −
Next state sequence will be ( Q +B Q A+ ) -
D B = QBQ A + QBQA D A = QBQA + Q BQA

= Q B (Q A + Q A ) DA = QB QA
DB = QB GATE - 2012
Ans. (d) :
Hence, the correct option is (d)
213. Consider the given circuit
• Consider (A = 0) • Consider (A = 0)

Q n +1 = D = Y = Q n Q n +1 = D = Y = X1 = Q n
Q n +1 = Q n Q n +1 = Q n
Qn Q n +1 = Q n Qn Q n +1 = Q n
0 1 0 0
1 0 1 1
Output graph like as W3

Hence, the value of waveform W3 is correct.
216. The outputs of the two flip-flops Q1, Q2 in the
Both state diagram are combined. figure shown are initialized to 0, 0. The
sequence generated at Q1 upon application of
clock signal is
So the right option of this question is 'd'

215. In the circuit shown, choose the correct timing
diagram of the output (Y) from the given
waveforms W1, W2, W3 and W4.
(a) 01110... (b) 01010...
(c) 00110... (d) 01100...
GATE - 2014, Set-II
Ans. (d) :
From the circuit

J1 = Q 2 K1 = Q 2
J 2 = Q1 K 2 = Q1
So the value (sequence) of Q1 is
present Present Input Next State
state
(a) W1 (b) W2
Q1 Q2 J1 K1 J 2 K 2 Q1+ Q +2
(c) W3 (d) W4
0 0 1 0 0 1 1 0
GATE – 2014, Set-II
1 0 1 0 1 0 1 1
Ans. (c) : There are two D-flip-flop connected with
0 1 0 1 0 1 0 0
AND gate.
The output of D-flip-flop Y = Q1.Q2. Hence the sequence of Q 1 = 0110
when we give which clock output will be same. 217. The circuit shown in the figure is a
Y = Q1Q 2 (Q1 = X1, Q 2 = X 2)
Y = X1.X 2
From the given figure,
CLK X1 X2 Y
0 0 0 0 (a) Toggle Flip-Flop
(b) JK Flip Flop
0 0 1 0
(c) SR Latch
0 1 0 0 (d) Master Slave D Flip Flop
0 1 1 1 GATE - 2014, Set-II

Ans. (d) : 219. The circuit shown consists of J-K flip-flops
each with an active low asynchronous reset
( R d input). The counter corresponding to this
circuit is
• The above given circuit is master slave D flip flop. D

type master/slave flip-flop consist of a pair D latch.
• In this circuit master flip-flop works on the positive
cycle of clock and slave flip-flop works on the negative (a) a modulo-5 binary up counter
cycle of clock. (b) a modulo-6 binary down counter
218. The figure shows a binary counter with (c) a modulo-5 binary down counter
synchronous clear input. With the decoding (d) a modulo-6 binary up counter
logic shown, the counter works as a
GATE - 2015, Set-III
Ans. (a) : In the given figure-
Clock input is connected to Q0 (LSB)
Q 2 Q1 Q 0
Now sequence will be ↓ ↓
MSB LSB
CLK Q 2 Q1 Q0 R d = Q 2 Q 0
(a) mod-2 counter (b) mod-4 counter 0 0 0 0 1
(c) mod-5 counter (d) mod-6 counter 1 0 0 1 1
Nagaland PSC (CTSE) Diploma - 2017, Paper-II 2 0 1 0 1
GATE - 2015, Set-II
3 0 1 1 1
Ans. (c) :
4 1 0 0 1
........................................
5 1 0 1 ..............
0
6 0 0 0 1
There are 5 unique state in increasing order

So it is MOD – 5 up counter.
Hence, option “a” is correct.
When the CLEAR = 1 the normal operation can take 220. For the circuit shown in the figure, the delay of
place whenever the output will be reset. the bubbled NAND gate is 2 ns and that of the
For clear signal = Q3☼Q2 counter is assumed to be zero.
CLK Q3 Q2 Q1 Q0 CLR = Q3 ⊙ Q 2
0 0 0 0 0 0⊙0 = 1
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 0
5 0 0 0 0 1
→ After 4 clock the CLEAR = 1 is 0. If the clock (Clk) frequency is 1 GHz, then the
→ Since it is clear & valid state. counter behaves as a
→ Counter is clear after 0100. (a) mod-5 counter (b) mod-6 counter
→ It will count from 0 to 4 so the no. of state is 5. (c) mod-7 counter (d) mod-8 counter
Hence, it is MOD-5 counter GATE - 2016, Set-III

Ans. (d) : In given figure, the NAND gate will reset (a) B (b) A
the counter. (c) A + B (d) A
RESET = Q 2 Q1 Q 0 TSPSC Manager (Engg.) - 2015
= Q 2 + Q1 + Q 0 Ans. (a) : Q n +1 = J Q n + K Q n
= A. 1 + B.1
CLK Q 2 Q1 Q0 RESET = Q 2 + Q1 + Q0
=B
0 0 0 0 1 223. Read the following statements:
1 0 0 1 1 i. Gate is a combinational logic.
2 0 1 0 1 ii. JK Flip-flop in toggle mode is not
combinational logic
3 0 1 1 1
iii. MSJK Flip-flop suffers from race-around
4 1 0 0 1 iv. Counter are sequential circuits.
5 1 0 1 1 Which choice is correct?
6 1 1 0 0 (a) i, ii (b) i, ii, iv
(c) ii, iii, iv (d) i, ii, iii
• The 3-bit synchronous will start the count until all the APGENCO AE- 23.04.2017
bits becomes 1 as soon as all bits are 1, the output of
NAND will become 0 and the bits will be reset. Ans. (b) :
Combinational Circuit Sequential Circuit
• If delay of the bubbled NAND gate is 0 the given
counter behave like MOD-6 counter but here delay of • No feedback is present Feedback is present
bubbled NAND gate is 2ns so it will count two more • No memory is present Memory is present
clock before it resets the counter, e.g. half adder, full adder e.g. flip - flop, counter
∴ So the given 3-bit synchronous behave like MOD-8 and gate register.
counter. • J-K flip-flop
221. In the latch circuit shown, the NAND gates
have non-zero, but unequal propagation delays.
The present input condition is: P = Q = '0'. If
the input condition is changed simultaneously
to P = Q = '1', the outputs X and Y are
224. The basic R-S flip-flop is

(a) A mono-stable multi-vibrator
(b) A bi-stable multi-vibrator
(c) An astable multi-vibrator
(a) X = '1', Y = '1' (d) A Schmitt trigger
(b) either X = '1', Y = '0' or X = '0', Y = '1' Nagaland PSC (Degree) 2018, Paper-II
(c) either X = '1', Y = '1' or X = '0', Y = '0' Ans. (b) : The basic R-S flip-flop is a bi-stable multi-
(d) X = '0', Y = '0' vibrator.
GATE - 2017, Set-II 225. In a JK flip-flop, J is connected to Q and K is
Ans. (b) : connected to Q outputs. The JK flip-flop
converts into a
(a) R-S flip flop
(b) D flip flop
(c) T flip flop
(d) Clocked R-S flip flop
When P = 0, Q = 0 ⇒ X = 1, Y=1 Ans. (c) :
When P = 1, Q = 1 ⇒ X = 1, Y=0
or or
X=0 ,Y = 1
Hence, the correct option is “B”
222. In a positive edge triggered JK flip-flop, the
present state Qn is set to high (1). If the inputs
J = A and K = B then next state Qn+1 will be
Next state equation of J-K flip-flop Ans. (d) : Output clock frequency
Q n +1 = JQ n + KQ n Input clock frequency.
=
J = Qn K = Qn Mod
Q n +1 = Q n Q n + Q n Q n 20 kHz
=
16
Q n +1 = Q n → toggle mode (i.e. T-flip-flop) = 1.25 kHz
226. What is the other name of Johnson counter? 230. The decoding error of the counter can be
(a) Ring counter avoided by
(b) Ripple counter (a) Increasing propagation delay of flip-flops
(c) Up-down counter used in the counter.
(d) Twisted ring counter (b) Using very fast logic gates
Nagaland PSC (Degree) 2018, Paper-II (c) Using the strobe signal
Ans. (d) : A Johnson counter is a modified ring counter (d) Reducing the propagation delay of flip-flops
in which the output from the last flip-flop is inverted used in the counter
and feedback as an input to the first, it is also called as
IES-2001
inverse feedback counter or Twisted ring counter.
227. The number of T flip-flops required to realize a
mod-5 counter is Ans. (d) : The decoding error in the counter can be
(a) 3 (b) 5 avoided by reducing the propagation delay of flip-flops
(c) 2 (d) 10 in the counter.
Nagaland PSC (Degree) 2018, Paper-II 231. The state diagram depicts the truth table of
UPRVUNL AE-2016
Ans. (a) : Mod-5 counter means 5 counts, so at least 3-
bits required to represent.
(a) Johnson counter (b) Up counter

(c) Ring counter (d) Ripple counter
TNPSC AE- 2019
Ans. (c) :
N=5
N ≤ 2n
5 ≤ 2n
n 3
So, we will require 3 T F/F.
Ring counters-
228. Modulo-6 asynchronous counter uses
It is simplest shift register counter.
(a) Four flip-flops (b) Eight flip-flops
It is also called end carry counter.’’
(c) Three flip-flops (d) Two flip-flops
Nagaland PSC (Degree) 2018, Paper-II In this only one bit is high and it made to circulate
Mizoram PSC IOLM-2018, Paper-II around the register as long as clock pulses are applied
Ans. (c) : Given, 232. To convert RS flip flop into JK flip-flop
N=6 (a) R=KQ', S=JQ (b) R=KQ, S=JQ
N≤2 n
where n= number of flip-flop (c) R=KQ, S=JQ (d) R=KQ, S=JQ
6 ≤ 2n TNPSC AE- 2019
n 3 Ans. (b) : R-S flip flop into JK flip-flop
MOD-6 asynchronous counter will require 3 flip-flops Here the inputs to the combination circuit are J and K. S
and will count from 000 to 101, rest of the states are
and R are the output of the available flip-flop (i.e. S-R
invalid.
ff).
229. The output frequency of a mod-16 counter,
clocked from a 20 kHz clock input signal is
(a) 20 kHz (b) 52 kHz
(c) 625 kHz (d) 1.250 kHz

233. To make the output Q as -----------and --------- 238. The flip flops used in shift-register are
the preset and clear inputs are used in flip-flops generally
(a) 0,0 (b) 1,0 (a) SR flip flop (b) JK flip flop
(c) 0,1 (d) 1,1 (c) D flip flop (d) T flip flop
TNPSC AE- 2019 Nagaland PSC 2018, Diploma Paper-II
Ans. (b) : The preset input drives the flip-flop to a set
(1) state while the clear input drives it to reset (0) stable. Nagaland PSC (CTSE) Degree - 2016, Paper-II
Ans. (c) : The flip flops used in shift-register are
234. The graph used for the possible merging of
states in an asynchronous sequential circuit is generally D flip flop.
(a) Merger diagram (b) Flow diagram 239. The number of flip flops required to make a
(c) Timing diagram (d) State diagram mod-19 counter is
TNPSC AE- 2019 (a) 4 (b) 5
Ans. (a) : Merger diagram will merge different row by (c) 6 (d) 7
following some rules. Stable state and unstable state will Nagaland PSC 2018, Diploma Paper-II
be merge and result in to stable state but some state will Ans. (b) : For MOD - 19 counters
be there. Stable state and blank can be merge into stable
state 2n ≥ 19
235. In JK flip flop, if we input K with the inverted Here n = 5 minimum value.
form of what we input J, the resulted flip flop is 240. The disadvantage of an open shift register is
(a) SR flip flop (b) JK itself that
(c) D flip flop (d) T flip flop (a) Both shift left and shift right operations can
Nagaland PSC 2018, Diploma Paper-II not be performed
TSPSC Manager (Engg.) - 2015 (b) The quantity stored is lost at every shift
Ans. (c) : In J-K flip flop, if we input K with the pulses
inverted form what we input J, the resulted flip flop will (c) The register is reset when read-out is over
be D-flip-flop. Hence it delay the value. (d) All of these
Ans. (a) : Shift Registers is a group of flip-flops used to
store multiple bits of data. The bits stored in such
registers can be made to move within the registers and
in/out of the registers by applying clock pulse.
If shift register is open then both shift left and right
operations can't be performed.
241. The purpose of introducing feedback loop in a
236. Shifting a register to left by one bit position digital counter circuit is
equivalent to (Binary Code). (a) To improve stability
(a) Division by 2 (b) Multiplication by 2 (b) To improve distortion
(c) Addition of 2 (d) Subtraction of 2 (c) Synchronous input and output pulses
Nagaland PSC 2018, Diploma Paper-II (d) To reduce the number of input pulses to reset
UPRVUNL AE-2016 the counter
Ans. (b) : Shifting a register to left by one bit position Nagaland PSC CTSE- 2015, Paper-II
equivalent to (Binary Code) multiplication by 2. Ans. (d) : The purpose of introducing feedback loop in
a digital counter circuit is to reduce the number of input
pulse to reset the counter.
242. In a ring counter 1 to N clock pulse the scale
237. The minimum Number of flip-flops required in for the counter is
a counter to count 60 pulses is: (a) N : 1 (b) N : 2
(a) 1 (b) 6 (c) N : 10 (d) N : 100
(c) 8 (d) 10 Nagaland PSC CTSE- 2015, Paper-II
Nagaland PSC 2018, Diploma Paper-II UPRVUNL AE-11.06.2014
TSPSC Manager (Engg.) - 2015 Ans. (a) : In a ring counter 1 to N clock pulses the scale
Ans. (b) : Number of flip flop are required to construct for the counter is N:1.
a 60 pulse counter, must satisfy 243. The n, stage register results in a delay of
2 n ≥ clock pulse (a) (n – 1) T (b) 2nT
(c) n2T (d) nT/2
2n ≥ 60
the minimum satisfying value. n = 6 Kerala PSC Lecturer (NCA) 04.07.2017
Ans. (a) : The n stage register results in a delay of (a) carry-ripple counter
( n − 1) T . (b) carry-ripple through adder
(c) carry-ripple through binary
244. Sixty capsules are to be filled in bottles (d) carry-ripple through subtractor
automatically employing an electronic counter ESE-2022
the number of flip-flops in such a counter will Ans. (b) : Addition of two n-bit numbers A and B can
be be carried out using n consecutive full adders in an
(a) 4 (b) 5 arrangement, which is known as carry-ripple through
(c) 6 (d) 7 adder.
Nagaland PSC CTSE (Degree) - 2016, Paper-II 54
247. The chip is an 8-bit serial-in-parallel-
Nagaland PSC CTSE- 2015, Paper-II 74164
Ans. (c) : For sixty capsules are to be filled in bottles. output shift register. The clock is 1 MHz. The
2n ≥ 60 time needed to shift a 8-bit binary number into
Minimum value of the chip is
(a) 1 µs
26 ≥ 64
(b) 2 µs
n=6 (c) 8 µs
245. A S-R flip flop with a clock input can be (d) 16 µs
converted to a 'D' flip flop using RPSC Vice Principal ITI-2016
(a) Two inverters n
( )
Ans. (c) : Time needed to shift a 8-binary number =
(b) The flip flop outputs Q & Q connected to its f clk
inputs 8
So, time = 6 = 8 µ sec.
(c) One inverter 10
(d) Not possible 248. The initial content of a four bit register is
Mizoram PSC IOLM -2018, Paper II 1000. What is the register content after it is
ISRO Scientist Engg.-2008 shifted four times to the right, with the serial
Ans. (c) : Step 1- We construct the characteristic table input being 111100?
(a) 1111
of D flip-flop and excitation table of S-R flip-flop.
(b) 1100
D Q n Q n +1 S R (c) 1000
0 0 0 0 × (d) 0011
0 1 0 × 1 Mizoram PSC IOLM-, Paper-III
Ans. (b) : The initial content 1000
1 0 1 1 ×
Serial input bit 111100
1 1 1 × 0
Step 2- Using the K-map we find the Boolean
expression of S and R in terms of D.
249. Draw FSM diagram
S=D R= D
Now we construct the circuit diagram of the conversion
of S-R flip-flop in to D flip-flop.
A S-R flip-flop with a clock input can be converted to a

'D' flip-flop using one inverter. (a) (b)
246. Addition of two n-bit numbers A and B can be
carried out using n consecutive full adders in
an arrangement, which is known as

T flip flop
(c) (d) None Q +n+1 = JQ n + K Q n
Q n +1 = TQ n + T Q n
Q[J = K = T]
Q n +1 = T ⊕ Q n
Ans. (a) : FSM stands for finite state machine. It is a 252. A 5-bit serial adder is implemented using two
mathematical model of sequential logic circuit. FSM 5-bit shift registers, a full-adder and a D flip-
has finite inputs, outputs and number of states. These flop. The two binary words to be added are
are of two types. 11011 and 11011. The sum of the two numbers
1. Mealy state machine is stored in one of the shift registers and the
2. Moore state machine carry in the D flip-flop. Assuming that the D
According to given circuit in question, its FSM diagram flip-flop is set initially, the content of the sum
is shown in option (a) shift register and the D flip-flop, respectively,
are
250. In figure below, U1 is a 4-bit binary
(a) 10111 and 0 (b) 11011 and 1
synchronous counter with synchronous clear.
Q0 is the LSB and Q3 is the MSB of the output. (c) 11101 and 0 (d) 10111 and 1
The circuit shown in figure represents a : BSNL(JTO)-2009
2 binary words - 11011 and 11011
∴
(a) mod 2 counter (b) mod 3 counter 253. Excitation table of flip-flop is given below:
(c) mod 4 counter (d) mod 5 counter
Qn Qn+1 A B
DRDO-2009
Ans. (d) : 0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Characteristic equation of the flip-flop will be:
(a) Q m +1 = AQ n + BQ n
(b) Q n +1 = AQ n + BQ n
(c) Q n +1 = AQ n + BQ n
The circuit represents a mod 5 counter because the (d) Q n +1 = AQ n + BQ n
process are repeating after 5th clock pulses.
BSNL (JTO)-2006
251. The characteristics equation of the T flip-flop is
given by Ans. (c) : Excitation table of given flip-flop can be
shown as Q( n +1) = AQ n + BQ n
(a) Qn+1 = TQn (b) Qn+1 = TQn + TQn
The excitation table is of J-K flip-flop.
(c) Qn+1 = TQn (d) Qn+1 = TQn 254. The output of the circuit shown below is
BSNL(JTO)-2009
Ans. (b) : (a) A pulse train of duration 0.5 sec
(b) A pulse train of duration 2 sec.
(c) A pulse train of duration 1sec.
(d) A pulse train of duration 5 sec

Ans. (b) Truth-Table
Qn PRE CLR Qn+1
0 0 0 Invalid
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 Invalid
1 0 1 1
1 1 0 0
The flip-flop must be T-flip-flop with active high input. 1 1 1 1
1 257. The sequence detected by the state diagram
T= shown below is ______.
F
1
T=
1/ 2
T = 2 sec.
255. The current state of Q2Q1Q0-100 for the circuit
below. The next state will be_____.
(a) 1110 sequence detector without overlap

(b) 1110 sequence detector with overlap
(c) 1101 sequence detector without overlap
(a) 101 (b) 111 (d) 1101 sequence detector with overlap
(c) 001 (d) 110 DFCCIL Executive (S&T) 11.11.2018, 4:30 to 6:30PM
DFCCIL Executive (S&T) 11.11.2018, 4:30 to 6:30PM Ans. (c) : In the state diagram, we can see that at last
Ans. (a) : As given that, we will get sequence 1101101, we can use one bit in
Initial state = 100 overlapping but here we did not use any bit of the
At every flip-flop, previous detected sequence for detection of the next
sequence so it is non overlapping type.
J=K=1, and Q ⊕ CLK = 1 258. Race around condition is associated with
So, it is an up counter, ______.
Then next state will be 101. (a) Combinational circuits
256. When two asynchronous active low inputs (b) Sequential circuits with level triggered clock
PRESET and CLEAR are applied to a J-K flip- (c) Sequential circuits
flop, the output will be ______. (d) Both Sequential and Combinational circuits
(a) 0 (b) Undefined DFCCIL Executive (S&T) 11.11.2018, 4:30 to 6:30PM
(c) Previous state (d) 1 Ans. (b) : Race around condition is associated with
DFCCIL Executive (S&T) 11.11.2018, 4:30 to 6:30PM sequential circuits with level triggered clock and the
Ans. (b) : • Asynchronous inputs can set or reset the output of the flip-flop becomes ambiguous and erratic.
flip-flop regardless of the status of clock pulse. Note : Race around condition occurs only in level
• When PRESET input is active low then output of triggered flip flop.
flip-flop is going to set (Q = 1, Q = 0 ) Race around condition occurs because of the feedback
connection.
• When CLEAR input is active low then output of
259. Which of the following flip-flops has a single
flip-flop is going to reset (Q = 0, Q = 1 ) control input?
• When both are active low or high then we will get (a) The gated D-latch
invalid state of flip-flop. (b) The edge triggered J-K flip-flop
(c) The edge triggered T flip-flop
(d) The edge triggered S-R flip-flop
Ans. (c) : Edge triggered T flip-flop gives a single
control input. If both the inputs of JK flip-flop are
connected together then T flip-flop is built. T flip-flop
has only one input terminal as T.

4. The 14 pin TTL integrated circuit with four,
(vi) IC Logic Families two inputs gates inside is IC7486.
(a) AND (b) XOR
1. Match the following for the TTL logic family: (c) NAND (d) NOR
1) Fan Out a) 10 n UPRVUNL AE -19.07.2021, Shift-II
2) Output Current with HIGH O/P b) 0.4 Ans. (b) : In IC7486, 14. pin TTL Integrated circuit
3) Noise Margin c) 10 with four, two inputs have XOR gates.
4) Time Delay d) IOH • IC 7486 is a quad two input XOR gate
(a) 1 – d, 2 – c, 3 – a, 4 – b • IC 7400 is a quad two input NAND gate
(b) 1 – c, 2 – d, 3 – b, 4 – a • IC 7402 is a quad two input NOR gate
(c) 1 – b, 2 – a, 3 – c, 4 – d • IC 7404 is a Hex inverter
(d) 1 – a, 2 – b, 3 – d, 4 – c • IC 7408 is a quad two input AND gate
UPPCL AE-30.03.2022 • IC 7432 is a quad two input OR gate
Ans. (b) : Correct match of TTL logic family is given 5. IC 74 HC00 series belong to,
below- (a) High Speed TTL IC
1. Fan out -10 (b) High Speed CMOS IC
2. Output current with high output - I0H
(c) Low power Schottkey TTL
3. Noise margin - 0.4
(d) MSI family
4. Time delay - 10n
2. Which among the bipolar logic families is
specifically adopter for high speed Ans. (b) : IC 74 HC00 series belong low power, high
applications? speed, CMOS logic gate.
(a) Diode Transistor Logic (DTL) 6. Which of the following is 'true' for an ECL
(b) Transistor Transistor Logic (TTL) circuit ?
(c) Emitter Coupled Logic (ECL) I. Switching speed is highest among
(d) Integrated Injection Logic (I2L) commercially available logic families
UPRVUNL AE-19.07.2021 II. ECL logic block usually produces output
APPSC Poly. Lect.- 15.03.2020 and it's complement also
RPSC VP/Suptd. ITI- 05.11.2019 III. Total current flow in an ECL remains
Nagaland PSC (Diploma) -2018, Paper-II
relatively constant regardless of logic state
RPSC LECTURER.-10.01.2016 IV. ECL also called Merged transistor logic
UPRVUNL AE-11.06.2014 (a) II, III and IV (b) I, II and III
RPSC Lect.- 2011 (c) I and IV (d) II and IV
Ans. (c) : Emitter coupled logic (ECL) are used for high RPSC ACF & FRO 23.02.2021
speed application. Hence there is no saturation problem
Ans. (b) :
occurs. In electronic emitter-coupled logic is a high-
speed integrated circuit bipolar transistor logic family. ECL (Emitter coupled logic) is a non saturated
ECL uses an overdriven bipolar junction transistor digital logic family.
differential amplifier with single ended input and This logic family has the lowest propagation delay
limited emitter current to avoid the saturated region of of any family and is used mostly in system
operation and its slow turn off behaviour. requiring very high-speed operation.
3. Which of the following is true in case of 7. The TTL NAND gate has high speed, low rise
Sampling frequency in ADC? time and low fall time due to
(a) Sampling frequency should be less than (a) Inclusion of multi-emitter transistor
highest frequency in signal (b) Use of diode in circuit
(b) Sampling frequency should be equal to (c) High input resistance
highest frequency in signal (d) Low output resistance
(c) Sampling frequency should be as low as RPSC ACF & FRO 23.02.2021
possible
Ans. (a) : The TTL NAND gate has high speed low rise
(d) Sampling frequency should be at least twice
time and low fall time due to inclusion of multi-emitter
that of highest frequency in signal
transistor.
UPPCL AE-30.03.2022
As the TTL technology progressed, additional and
Ans. (d) : Whenever analog signal is sampled with a improvements were added to the point where this logic
frequency ‘f’ then converted digital signal has more is widely used in the design of digital system.
frequency than analog signal. The discrete output signal
8. The following diode circuit gives which logic
by ADC could be 'f ', ( ±f ) , ( ±2f ) etc.
function?
(a) AND (b) OR
(a) OR gate with negative logic (c) NAND (d) NOR
(b) AND gate with negative logic UPPCL AE-30.03.2022
(c) AND gate with positive logic Ans. (c) : From given CMOS circuit output can be
given as-
(d) OR gate with positive logic y = AB
UPRVUNL AE -19.07.2021, Shift-II Truth table of the circuit
Ans. (c) :
So the given circuit is NAND gate.

11. Which integrated circuits are broadly used in
the radio frequency and audio frequency
Hence given circuit is an AND gate with positive logic. amplifiers?
(a) Only digital
9. Which of the following technology results in (b) Only linear
least power dissipation? (c) Both linear and digital
(a) CMOS (b) ECL (d) Non-linear
DMRC AM S&T-2020
(c) TTL (d) NMOS
Ans. (b) : Analog I.C. that is also known as linear IC's
IES - 2020 are broadly used in radio frequency and audio frequency
APPSC Poly. Lect. 15.03.2020 amplifiers because the amplifier shows a linear
Nagaland PSC - 2018 (Diploma), Paper-II relationship in input and output.
12.
RPSC Vice Principle ITI - 2016
TSGENCO AE-2015, TNPSC AE-2014
Ans. (a) : CMOS logic family has least power
dissipations.
CMOS logic family built with both N-channel and P- The NOR gate feeds five gates. What is the
channel metal oxide semiconductor FET. minimum value of β to drive all these gates into
saturation when V0 is high?
PMOS logic family built with P-channel metal oxide
(a) 7.1 (b) 1.5
semiconductor FET (MOSFET). NMOS logic family (c) 5.0 (d) 3.2
built with N-channel metal oxide semiconductor UPMRC AM - 2020
FET(MOSFET). Ans. (a) : The figure above represents the circuit
equivalent of the given figure assuming that all the
10. The circuit shown in the following figure is a other four such transistors get into saturation with
_____ gate. VBE(ON) = 0.8

(a) Increase IOL
(b) Reduce IOH
(c) Increase speed of operation
(d) Reduce power dissipation
Nagaland PSC CTSE 2015, Paper-II
GATE-1999
Ans. (c) : Darlington pair is a "CC-CC" combination
having
Now, using super-position, we can write. (i) high input impedance & low output impedance.
100 650 (ii) used in output stage of TTL to increase speed
V0 = 3.6 × + 0.8 × (iii) high current gain
650 + 100 650 + 100
15. In standard TTL, the 'totem pole' refers to
V0 = 0.48 + 0.69
(a) Multi-emitter input stage
V0 = 1.17 V (b) The phase splitter
For the transistor saturate (c) Open collector output stage
1.17 − 0.8 0.37 (d) The output buffer
IB = = = 0.74mA Nagaland PSC (Degree) 2018, Paper II
0.5 0.5
3.6 − 0.2 3.4 GPSC Assitt. Prof. 11.04.2017
IC = = = 5.23mA Nagaland PSC CTSE-2015, Paper II
0.65 0.65 TRB Poly. Lect. -2012
5.23 IES-2011, GATE-1997
Now, βmin = = 7.1
0.74 Ans. (d) : TTL ‘totem pole’ refers to the output buffer.
13. The figure of merit of a logic family is given by
(a) Gain bandwidth product
(b) (Propagation delay time) × (power
dissipation)
(c) (fan-out) × (propagation delay time)
(d) (noise margin) × (power dissipation)
Nagaland PSC (Degree)2018, Paper-II
KVS TGT (WE)- 2018, 2017
RPSC Lect. 2011
IES-2008, 2007, 2000
ISRO Scientist- 2011
IES-1994 TTL circuit are classified as :
Ans. (b) : Figure of merit (FOM) (i) Tristate logic (high impedance logic)
FOM = tpd × PD(avg) pico joules (ii) Totem pole logic (active pull up)
Where tpd = propagation time delay. (iii) open collector logic (passive pull up)
PD = power dissipation. the main advantage of TTL with a "totem-pole" output
Propagation time delay :- this is the average transition stage is the low output resistance at output logic '1' also
delay time for the signal to propagate from input to addition of an active pull up circuit in the output of the
output when signal changes its value. This determines gate which results in reduction of propagation delay.
how fast the logic system can operate. 16. Commercially available ECL gate use two
t +t ground lines and one negative supply in order
t pd = PHL PHL ns to
2 (a) Reduce power dissipation
tPHL– Delay time going from high logic to low logic. (b) Increase fan-out
tPHL– Delay time going from low logic to high logic. (c) Reduce loading effect
Power dissipation :- It is determined by the current Icc (d) Eliminate the effect of power line glitches on
which draws from the Vcc supply. the biasing circuit
PD(avg) = ICC × Vcc mW Nagaland PSC (Degree) 2018, Paper-II
• for the best operation of IC's, figure of merit should be GATE-1999
small as possible.
Ans. (d) : ECL gate uses two ground lines and one
14. A Darlington emitter follower circuit is negative supply to eliminate the effect of power line
sometimes used in the output TTL gate glitches on the biasing circuit.
17. The noise margin of a TTL gate is about • Gate required is four nMOS and four pMOS.
(a) 0.2 V (b) 0.4 V • Transistor required 6 nMOS and 6 pMOS.
(c) 0.6 V (d) 0.8 V • For not gate one nMOS and one pMOS required.
Nagaland PSC CTSE (Degree)-2017, Paper-II 21. The logic function implemented by following
Nagaland PSC CTSE 2015, Paper-II circuit can be represented as
GATE-1998
Ans. (b) : Noise margin - Noise immunity refers to the
circuit's ability to tolerance noise without charges in
output voltage.
A quantitative measure is called noise margin.
Logic family Noise margin (Volt)
DTL 0 - 75
HTL 4-5
TTL 0.4
ECL 0.16
18. Which of the following is non-saturating? (a) Y = [(AB) + (B+C) + (B+D)]'
(a) TTL (b) CMOS (b) Y = [(AB) + (A+C) + (B+D)]'
(c) ECL (d) Both (1) and (2) (c) Y = [(AB)' + (A+C)' + (AB+D)']
Nagaland PSC (Diploma)- 2018, Paper-II (d) Y = [(AB) + (A+C) + (AD)]'
Nagaland PSC (CTSE) Diploma-2017, Paper II ISRO Scientist Engg. -2020
SAIL-2014
Ans. (c) : An emitter coupled logic has high speed Ans. (d) : Output Y = AB + ( A + C ) + A ( B + D )
integrated circuit bipolar transistor logic family due to Y = AB + A + C + AB + AD
high speed it is a non-saturating device. ( )
Parameters of ECL- Y = AB + ( A + C ) + AD {Q AB + AB = AB}
Fan out 25 22. Write a Boolean expression for Z in terms of A,
Noise margin 250 mV B, C, D and E. You need not simplify the
Power dissipation/gate 25 mW expression.
Propagation delay 2 ns
Clock frequency 600 MHz
19. In a Schottky TTL gate, the Schottky diode
(a) increases the propagation delay
(b) increases the power consumption
(c) prevents saturation of the output transistor
(d) keeps the transistor in cut-off region
DRDO-2008
Ans. (c) : Schottky TTL gate, is used, it prevents the
transistor to go into saturation and thereby reduces the
{ }
(a)  ( A + B ) .( D.E ) + C 

{ }
time required to switch from saturation cut-off.
(b)  ( A.B ) + ( D + E ) .C 
20. For CMOS implementation of 2 input XOR  
logic gate, how many nMOS and pMOS
transistors are required?
(a) 2 nMOS and 2 pMOS
{  }
(c)  ( A.B ) + ( D + E ) .C 

(b) 3 nMOS and 3 pMOS (d) False
(c) 6 nMOS and 6 pMOS ISRO Scientist Engg.-2010
(d) 8 nMOS and 8 pMOS Ans. (b) :
Ans. (c) :

In NMOS circuit, if the transistors are connected in Ans. (c) : Power consumption by CMOS IC =
series → AND operation if parallel connected → OR Pstatic + Pdynamic
operation. For f1 = 10 MHz,
So, From the given circuit. Pconsumed = 100 mW = P1
Z = [{(A.B) + (D + E)}.C] For f2 = 15 MHz
23. The Boolean equation for Y in the following Pconsumed = 140 mW = P2
circuit is P1 = Pstatic + Pdynamic
100 mW = Pstatic + Kf1
100 mW = Pstatic + K(10MHz) ........(i)
Similarly, P2 = 140mW = Pstatic + K (15 MHz) ...(ii)
Pstatic = 20mW (Q K = 8)
26. High State noise margin of standard TTL and
5V CMOS logic gate are
(a) 0.4V, 0.4V (b) 0.4V, 1V
(a) Y= (A(B+C)+D)’ (b) Y= A(B+C)+D (c) 1V, 0.4V (d) 1V, 1V
(c) Y= (A+BC)D (d) Y=((A+BC)D)’ ISRO Scientist Engg.-2018
ISRO Scientist Engg.-2014 Ans.(b):
Ans. (a) : From the above circuit:- TTL CMOS
B and C are OR input so output = (B + C)
Noise - Margin 0.4V 1.5V
together
Power dissipation 10W 0.01W
(B + C) is AND with A
A (B+ C) is OR with D Fan - in 12 -14 > 10
So, N MOS Act as invertor, Fan out 10 More than 50
We will get - 27. Power consumed in a CMOS circuit operating
Y = (A(B + C) + D) at frequency f is proportional to:
(a) VCC (b) VCCf
Note - For NMOS parallel →OR 2 2
Series → AND (c) VCC f (d) VCC f2
and PMOS vice-versa. ISRO Scientist Engg. -2015
24. Which logical function is implemented by Ans. (c) : Power consumed (P) ∝ V 2
CC
following Transmission Gate based circuit?
P∝f
2
P ∝ VCC f
Where VCC = supply voltage
f = operating frequency.
(a) Y=XNOR(A,B) (b) Y=OR(A,B)
28. Schottky clamping is resorted in TTL gates
(c) Y=AND(A,B) (d) Y=XOR(A,B)
ISRO Scientist Engg.-2014 (a) to reduce propagation delay
(b) to increase noise margins
Ans. (d) : PMOS conducts when gate signal is 0 (low)
and NMOS conducts when gate signal is 1 (high) (c) to increase packing density
So, (d) to increase fan-out
Then, Nagaland PSC (Degree) 2018, Paper-II
A = 0, Y = B Nagaland PSC (CTSE) Degree-2017, Paper-II
A = 1, Y = B GPSC Asstt. Prof.- 11.04.2017
Y = AB + AB ISRO Scientist Engg.-2013
Y = A⊕B Ans. (a) : Schottky clamping is resorted in TTL gate to
Y = XOR ( A, B ) reduce propagation delay. A schottky transistor is a
combination of a transistor and a schottky diode that
25. A digital CMOS IC operating at 10 MHz clock prevents the transistor from saturating by diverting the
frequency consumes 100 mW power; the same excessive input current. It is also called a schottky
IC operating at 15 MHz clock frequency clamped transistor.
consumes 140 mW power. What is the static
power consumption of the IC? 29. _______ has the maximum fan out capacity
(a) 10 mW (b) 15 mW (a) MOS (b) CMOS
(c) 20 mW (d) 40 mW (c) ECL (d) RTL
ISRO Scientist Engg.-2014 ISRO Scientist Engg.-2011
Ans. (b) : CMOS has the maximum fan out capacity. 33. If a logic circuit has a fan out of 4 then the
Parameter family of CMOS- circuit
Fan out 50 (a) has 4 input
Noise margin 1.5 V (b) has 4 outputs
Power dissipation/gate 0.1 mW (c) can drive maximum of 4 inputs
Propagation delay 50 ns (d) gives output 4 times the input
Supply voltage 5V Nagaland PSC (CTSE) Diploma-2017, Paper II
30. Silicon dioxide is used in ICs Ans. (c) : A logic circuits has a fan out of 4 means
(a) Because it facilitates the penetration of circuit can drive maximum of 4 input. Fan out is the
diffurants term that defines the maximum number of digital input
(b) Because of its high heat conduction that the output of a single logic gate can feed. Most
(c) To control the location of diffusion and to transistor, transistor logic (TTL) gate can feed up to 10
protect and insulate the Si Surface other digital gates or devices.
(d) To control the concentration of diffurants Thus a typical TTL gate has a Fan out of 10.
34. The switch that has the fastest speed of
Ans.(c): Silicon dioxide(SiO2) is used in ICs to control operation is………..switch
the location of diffusion and to protect and insulate the
Si surface during Ion implantation, SiO2 is used as a (a) Electronic (b) Mechanical
making layer to protect the surface from damage. The (c) Electromechanical (d) None of the above
oxide layer is patterned by the photolithographic Nagaland PSC (CTSE) Diploma-2017, Paper II
process. Ans. (a) : An electronic switch has fastest speed of
31. Which of the following digital integrated circuit switching. It is because of logic circuitry. An electronic
cannot be used as wired logic connections? switch is an electronic component or devices that can
(a) Totem-pole TTL gate switch an electrical circuit interrupting the current or
(b) Open collector TTL gate diverting if from one conductor to another. Electronic
(c) Totem-pole output with 3-state gate switches are considered binary devices because they can
(d) Emitter coupled logic be on or off.
35. For the circuit in figure, identify the Boolean
Ans. (a) : Open collector TTL gate, Totem pole output
with 3-state gate and emitter coupled logic used as function implemented
wired logic connections, but Totem pole TTL gate IC
can not be used as wired logic connections.
32. A CMOS digital circuit consumes P watts of
dynamic power while operating at 20 MHz
clock frequency and 5V supply. What will be
its dynamic power consumption if the clock
frequency is increased to 40 MHz and supply
voltage is decreased to 2.5 V?
(a) P/4 (b) P/2
(c) P (d) 2P
Ans. (b) : In case of CMOS only dynamic power loss (a) y = ( A + B + C ) D (b) y = A.B.C + D
occur and it is
2 (c) y = ABC + D (d) y = (A + B + C) D
P0 = CfV f1 = 20 MHz
PD ∝ fV 2
f2 = 40 MHz TNPSC AE – 2018
So, TNTRB AE-2017
PD1 V22 f 2 Ans. (a) :
= 2
P V1 f1
PD1 (2.5)2 × 40MHz
=
P (5) 2 × 20MHz
6.25 × 2
PD1 = ×P
25
2
PD1 = P
4
PD1 = P/2

41. The current hogging takes place in
(a) RTL (b) HTL
(c) DCTL (d) TTL
Ans. (c) : The current hogging takes place in - 'DCTL'
logic (Direct Coupled Transistor Logic Family).
• It limit the fan out of the family.
42. Which of the following logic family has least
propagation delay?
36. In CMOS inverter when the output is at logic 1, (a) ECL
______ transistor conducts and ______ (b) CMOS
transistor is in off state. (c) BiCMOS
(a) NMOS, PMOS (b) PMOS, NMOS (d) CMOS and BiCMOS
(c) NMOS, NMOS (d) PMOS, PMOS DFCCIL Executive S&T-17.04.2016, Shift-II
TNPSC AE - 2018 Ans. (a) : Emitter coupled logic (ECL) is the fastest
Ans. (b) : In CMOS inverter when the output is at logic among all digital logic families. ECL has least
1, P-MOS transistor conducts and N-MOS transistor is propagation delay (1-2ns). ECL is a non saturated logic.
in off state. N-MOS constructed with n-type source is Propagation delay of CMOS 70ns.
constructed with p-type source & drain and n-type 43. The p-type substrate in a conventional pn-
substrate. junction isolated integrated circuit should be
37. For CMOS family LOW input and HIGH connected to
input are defined as __ and __ respectively. (a) No where, i.e. left floating
(a) 0V to +1.5V and +3.5V to +5V (b) A dc ground potential
(b) +3.5V to +5V and 0V to +1.5V (c) The most positive potential available in the
(c) 0V to +0.4V and +3.5V to +5V circuit
(d) 0V to +0.8V and +2.4V to +5V (d) The most negative potential available in the
UPRVUNL AE-2016 circuit
Ans. (a) : For CMOS family low input and HIGH input Nagaland PSC CTSE (Degree)-2017, Paper-I
are defined as 0V to +1.5V and +3.5V to +5V. Ans. (c) : The P-type substrate in a conventional p-n
38. Commercially available ECL gates use two junction isolated integrated circuit should be connected
ground lines and one negative supply in order to the most positive potential available in the circuit.
to 44. For a typical CMOS process, the minimum
(a) Increase fan-out feature size is set to be λ = 25 µm. The
(b) Reduce loading effect minimum line width of process is set to be
(c) Reduce power dissipation ______.
(d) Eliminate the effect of power line glitches or (a) 100µm (b) 12.5µm
biasing circuits
(c) 50 µm (d) 25 µm
Nagaland PSC (CTSC) Degree - 2017, Paper-II
UPSC JWM-2016
Ans. (c) : Lambda based design rules-
Ans. (d) : Commercially available ECL gates use two
ground lines and one negative supply in order to • Lambda based design rules define scalable rules
eliminate the effect of power line glitches or the biasing based on Lambda (Which is half of the minimum
circuit. channel length)
39. Name the logic family which has always one • This rule is designed on the basis of single parameter
output transistor conducting λ .
(a) I2L (b) RTL Given, λ = 25 µm
(c) DTL (d) CMOS ∴ minimum line width = 2λ
UJVNL AE-2016 = 2 × 25
Ans. (d) : Logic family is a group of electronic logic = 50 µm
gates. Member of logic family which has always one 45. In TTL family, the Totem-pole circuit on the
output transistor conducting is CMOS. output is used to provide____.
40. The current mode logic (CML) is same as (a) Active pull up and active pull down
(a) LSI (b) CMOS (b) Inactive output state
(c) TTL (d) ECL (c) Active pull down
RPSC LECTURER-10.01.2016 (d) Active pull up
Ans. (d) : The current mode logic (CML) or source DFCCIL Executive S&T-17.04.2016, Shift-II
coupled logic (SCL) is same as Emitter-coupled logic Ans. (a) : In TTL logic family, the totem-pole at the
(ECL). ECL is a high-speed integrated circuit bipolar output is used to provide active pull up and active pull
transistor logic family. down.
46. One of the following materials is not used a Ans. (d) : Four Input AND Gate
substrate for the fabricating of MIC's
(a) Glass (b) NiCr
(c) Garret (d) Berrylia
Ans. (c) : Garret is not used as substrate for the
fabricating of MIC's. • All switch must be high for the output to be high.
47. Packaging density is high in • TTL logic can be used in digital circuit.
(a) Diode (b) BJT • Digital circuit are non-linear circuit.
(c) CMOS (d) All of these
Nagaland PSC CTSE (Diploma)-2018, Paper-I 52. The main disadvantage of DTL logic circuits is
KVS TGT (WE)-2016 (a) Medium speed
Ans. (c) : A new high performance CMOS technology (b) Very large power supply voltage
is developed which provide high packing density. High (c) High cost
speed CMOS LSIS. The Hi-CMOS technology utilizes 3 (d) Very large gate propagation delay
µm photolithographic techniques and device structure IES-2016
dimension are reduced.
Ans. (d) : DTL:- Diode Transistor Logic:-
48. Thin gate oxide in a CMOS process is
preferabilly grown using Basic Gate NAND
(a) Wet oxidation (b) Dry oxidation Fan - in 10
(c) Epitaxial deposition (d) Ion implementation Fan - out 8
Mizoram PSC Jr. Grade -2018, Paper-I Power Dissipation 8 to 12 mw
Ans. (b) : Dry oxidation is used to achieve high-quality Noise Margin 0.7
oxide growth. Dry oxidation produces a very good Propagation Delay 30 n sec
quality of oxide that's why dry oxidation is preferred Polarity Bipolar
over wet oxidation to grow this gate oxide in CMOS-
fabrication. • Main Disadvantage of DTL Logic circuit is very large
Dry oxidation is used to form thin oxide films and give gate propagation delay
better electrical properties. It is slow compare to wet 53. For Emitter-Coupled Logic (ECL), the
oxidation.
switching speed is very high because
49. The unused inputs of CMOS logic family (a) Negative logic is used
should never be left open. They should
(a) Preferably be grounded (b) The transistors are not saturated when they
(b) Preferably be tied to +VDD are conducting
(c) Be tied to logic LOW or logic HIGH level or (c) Multi-emitter transistors are used
another used input. (d) Of low fan-out
(d) Preferably be connected to one of the used KVS TGT (WE)-2017
inputs IES-2016
Ans. (b) : Emitter Coupled Logic (ECL):-
Ans. (a) : All unused input should tied to either VCC or
ground because CMOS logic has very high input • ECL, the switching speed is very high because
impedance, any input impedance, any open input might transistors are not saturated when they are conducting.
result in a false output value due to influence of • It is the fasted logic among the all hence called "
surrounding electric field. current mode logic".
50. The fan out TTL logic gate is about : • It provides wired 'OR' logic
(a) 5 (b) 10
• It used negative power supply to avoid noise and
(c) 20 (d) 50
glitches.
Ans. (b) : Fan-out is the number of gates inputs driven • Propagation delay in ECL circuit is 1 n sec.
by the output of another single logic gate. The fan out of •Noise margin in ECL logic circuit is 0.3 Volt.
TTL logic gate is about 10. 54. What is the correct sequence when the logic
51. Which one of the following statements is families TTL, ECL, IIL and CMOS are
correct? arranged in descending order of fan-out
(a) TTL logic cannot be used in digital circuits. capabilities?
(b) Digital circuits are linear circuits. (a) CMOS, TTL, ECL and IIL
(c) AND gate is a logic circuit whose output is
(b) IIL, TTL, ECL and CMOS
equal to its highest input.
(d) In a four-input AND circuit, all inputs must (c) IIL, ECL, TTL and CMOS
be high for the output to be high. (d) CMOS, ECL, TTL and IIL
IES-2016 IES-2015
Ans. (d) : 57. For a transistor used as a switch td is delay
time, tr is rise time, ts is storage time and tf is
Logic Family FAN - OUT FAN - IN
the fall time. Then turn-on time tON and turn-
CMOS 50 8 off time tOFF are respectively
ECL 25 5 (a) (td + ts) and (tr + ts) (b) (td + ts) and (ts + tr)
TTL 10 8 (c) (tr + ts) and (td + tf) (d) (td + tr) and (ts + tf)
IIL 8 5 IES-2012
Descending order of fan-out capability Ans. (d) : Transistor Switching Time :-
CMOS, ECL, TTL, IIL
• On Time t o n = t r + t d
55. The circuit shown in figure is
where
tr = rise time
td = delay time
• OFF Time t off = t s + t f
ts = storage time
tf = Fall time
• The switching time for a simple transistor is as
follows :- ts = 120ns, td = 252ns, tr = 13ns, tf = 12 ns
58. In locations where the humidity is low, ICs
(a) OR gate (b) NOR gate based on one of the following technologies
(c) NAND gate (d) AND gate should be handled only after grounding the
body. The technology is
IES-2014
(a) TTL (b) CMOS
Ans. (c) : (c) DTL (d) I2L
IES-2012
Ans. (b) : The location where the humidity is low, the
CMOS technology should be handled only after
grounding the body.
59. CMOS logic families are associated with
1. Low power dissipation
2. High noise immunity
3. Low fan-out
4. Comparatively high logic voltage swing
M1 and M2 are connected in series:- Which of these statements are correct?
therefore (a) 1, 2 and 4 only (b) 1, 2 and 3 only
(c) 2, 3 and 4 only (d) 1, 2, 3 and 4
KVS TGT (WE)-2018, BEL-2015, IES-2011
Ans. (a) : CMOS :- complementary metal oxide-
semiconductor.
Important characteristics:-
(1) Low static power consumption
56. The switching speed of ECL is very high, (2) High noise immunity.
because the transistor : (3) High logic voltage swing.
(a) Are switched between cut-off and saturation
(4) High fan out (50).
region.
(5) Reduce the complexity of the circuit.
(b) Are switched between active and saturation
region (6) The high density of logic function on a chip.
(c) Are switched between active and cut-off 60. Match List-I with List-II and select the correct
region answer using the code given below the list :
(d) May operate in any of the three regions List-I List-II
GPSC Asstt. Prof. -11.04.2017 A. TTL 1. Low power consumption
IES-2013, 1992 B. ECL 2. High speed
C. CMOS 3. Low propagation delay
Ans. (c) • Emitter coupled logic switching speed is very
high because the transistor are switched between active Codes :
and cut-off region. A B C
• ECL is a non saturated logic. (a) 1 3 2
(b) 2 3 1
• ECL mode from OR/NOR Gate.
(c) 1 2 3
• Power dissipation in ECL is 40 to 55 mw. (d) 2 1 3
• Figure of merit in ECL 55–160 IES-2011
Ans. (b) Ans. (a) : As given that,
Logic families Property VOH = 5V, VOL = 1V
TTL - High speed (Saturated logic) VIH = 3.5V, VIL = 2V
ECL - Low propagation delay (2nsec) NMH = VOH –VIH
CMOS - Low power consumption (0.1mW) = 5 – 3.5
= 1.5 V
answer using the code given below the list : NML = VIL – VOL
List-I List-II =2–1
A. DCTL 1. Multiple collectors = 1V
B. ECL 2. Current hogging Hence, NMH and NML ]will 1.5V and 1V respectively.
C. I2L 3. High speed 64. Which of the following statements is not
Codes : correct?
A B C (a) Propagation delay is the time required for a
(a) 2 3 1 gate to change its state.
(b) 1 3 2 (b) Noise immunity is the amount of noise which
(c) 2 1 3 can be applied to the input of a gate without
(d) 1 2 3 causing the gate to change state.
IES-2011 (c) Fan-in of a gate is always equal to fan-out of
the same gate.
Ans. (a) :
(d) Operating speed is the maximum frequency at
Logic family Property which digital data can be applied to a gate.
• DCTL Current hogging problem IES-2009
• ECL High speed (non-saturated)
Ans. (c) : • Propagation delay:- propagation delay is
• I 2L Multiple collectors. the time between presentation of input and change of
62. Processing of MOS ICs is less expensive than output to a new logic level. For modern solid state logic
bipolar ICs primarily because they gates propagation delays are in the range of
(a) Use cheaper components nanosecond.
(b) Need no component isolation • Noise immunity:- the noise immunity of a logic
(c) Require much less diffusion steps circuit means the ability of a logic circuit to tolerate
(d) have very high packing density noise voltages on its inputs . Noise immunity is defined
IES-2010 as the amount of noise a logic circuit or system can
Ans. (d) : : Metal oxide semiconductor IC (MOS IC) tolerate, without being amplified beyond unity gain.
based on MOSFET structure have found wide • Operating Speed:- the maximum frequency at which
application in the digital field. It has some advantage digital data can be applied to a gate called operating
over bipolar IC’s. speed.
(1) Reduction in Size:- MOS IC's are more suitable •Fan-in and fan-out are not equal to the same gate.
than bipolar IC's in applications like large scale 65. Which of the following output configurations
integration (LSI) and very large scale integration are available in a TTL gate?
(VLSI). They are also used in memory chip and micro 1. Open collector output
processor this is because MOS IC's dose not occupy as
much surface when compared to a bipolar epitaxial 2. Totem-pole output
double diffusion transistor IC. 3. Tristate output
(2) Simple Fabrication process:- When compare to Select the correct answer from the codes
bipolar IC, the Fabrication process of a MOS IC is given below :
more simple and cost effective as the entire process (a) 1 only (b) 1 and 2 only
constitutes only one diffusion step to from the source (c) 2 and 3 only (d) 1, 2 and 3
and drain region. But bipolar IC process almost 4 step IES-2009
are required. Ans. (d) : TTL (transistor- transistor logic)
(3) Operating power small • TTL circuits are classified as:
(4) smaller leakage current (i) Tristate logic (High Impedance logic)
(5) Higher frequency stability
(ii) Totem pole logic (Active pull up)
(6) High packing density.
NOTE:- the only drawback of MOS IC is that the (iii) open collector logic (Passive pull up)
operating speed is less when compared to bipolar IC's. • Tristate logic is used in bus oriented system.
thus they are not used for very high speed application. • totem pole logic does not provide wired logic'1'
63. A particular logic family has VOH=5V, VOL=1V, 66. Which one of the following logic families can be
VIH=3.5 and VIL=2V. The Noise margins values operated using a supply voltage from 3V to
NMH and NML. will be: 15V.
(a) 1.5V, 1V (b) 5V, 1V (a) TTL (b) ECL
(c) 1V, 1.5V (d) 4.1V, 5V (c) PMOS (d) CMOS
DFCCIL Executive (S&T) 11.11.2018, 4:30 to 6:30PM IES-2009
Ans. (d) : Logic families Supply Voltage (i) The base resistance used in the RTL is not used in
(1) CMOS - 3 to 15 V the I2L gate.
(2) TTL - 3 to 7 V (ii) Multiple collector transistor are used this region
have higher density of integration.
(3) ECL - –2 to –5V (iii) In place of collector resistance used in RTL PNP
(4) N-MOS - 5 to 12 V transistor is used for load in I2L logic gate.
67. The threshold voltage for each transistor in the 69. Consider the following statements:
figure shown below is 2.0 V. What are the 1. CMOS gates require very little power
values of Vi for this circuit to work as an when they are not hanging states.
inverter? 2. Transmission gates are widely used in
(a) –5 V and 0 V (b) –5 V and 5 V CMOS designs.
(c) 0 V and 5 V (d) –3 V and 3 V 3. CMOS circuits have considerable
resistance to noise.
correct?
(c) 1 and 3 only (d) 1, 2 and 3
IES-2007
IES-2008, GATE-1998 Ans. (d) : CMOS gates require very little power
Ans. (a) : Given - when they are not hanging states.
Threshold voltage (VT) Transmission gates are widely used in CMOS
For NMOS = 2 V designs.
PMOS = –2 V CMOS circuits have considerable resistance to noise.
NMOS will be ON when VGS > VT All statements are true.
(a) If we take Vi = 0 V (logic 1) 70. Consider the following statements describing
→ VG–VS = 0 – (–5) = 5 the property of a complementary MOS
∴ VGS > VT (CMOS) inverter :
Hence, NMOS - ON 1. It is a combination of an n-channel FET
PMOS - OFF and a p-channel FET.
(b) If we take Vi = –5 V 2. There is power dissipation when the input
PMOS will be ON when VGS < VT carriers the logical 1 signal.
VGS = VG - VS = –5 –0=–5 < VT 3. There is no power dissipation when the
Hence, NMOS - ON input carries the logic 1 signal
PMOS - OFF 4. There is power dissipation during
Hence, the circuit will work as an inverter when Vi = – transition from 0 to 1 or from 1 to 0.
5V Which of the statements given above are
correct :
68. Why does an I2L (Integrated Injection Logic)
have higher density of integration than TTL? (a) 1, 2 and 3 (b) 2, 3 and 4
(a) It does not require transistors with high (c) 1, 3 and 4 (d) 1, 2 and 4
current gain and hence they have smaller IES-2006
geometry. Ans. (d) : CMOS is a combination of NMOS and
(b) It uses multi-collector transistors. PMOS is fabricated as twin tube. Various logic
(c) It does not require isolation diffusion. function can be realized using CMOS. They are
(d) It uses dynamic logic instead of static logic. characterized by lower power dissipation and excellent
IES- 2008, 2007 noise immunity.
Ans. (b) : I2L Logic ( Integrated-Injection Logic) • Power Dissipation :- Power Dissipation in CMOS is
I2L Basic circuit- of two types.
(a) Static :- It will be present during logic '0' or Logic
'1' input.
(b) Dynamic :- It will be present during logic level
transition .
Pd( dynamic ) = Cfv 2DD
The main feature of integrated injection logic is its high Where C - capacitance
packing density means more circuits can be built into f - frequency
the chip. So this family is mainly used for LSI function vDD - Supply voltage
and it is not used for individual gates in SSI packages. 71. Match List-I (TTL Nos.) with List-II
• The operation of I2L basic gate similar to RTL but (Significance) and select the correct answer
there are some differences in them:- using the code given below the lists :

List-I List-II Ans. (c) : • HTL – (High threshold logic)- HTL circuit
A. 74 LS 00 1. Low power/ low speed has excellent noise immunity and more logic swing
B. 74 H 00 2. High speed/high power
C. 7400 3. Basic NAND Gate Basic Gate NAND
D. 74 L 00 4. Low power Schottky Fan - out 10
Codes : Power dissipation 55 mw
A B C D Propagation delay 90 n sec
(a) 4 2 3 1 • CMOS- (Complementary Metal Oxide
(b) 3 1 4 2 Semiconductor) - High fan out
(c) 4 1 3 2
(d) 3 2 4 1 Basic Gate NAND/NOR
IES-2005 Fan - out More than 50
Ans. (a) : • 74LS00 Series - ( low power Schottky Power dissipation 0.1 mW
TTL or LSTTL) 74LS00 series has less power Propagation delay 70 n sec
dissipation (2mw per gate) than the 745 series but •I2L (Integrated Injection Logic)- I2L logic has best
slower speeds (propagation delay 9.5ns) . In this also figure of merit
transistors with schottky diodes are used but the value
of registers becomes more than 745 series. Propagation delay 25 - 2500 nsec
•74 H 00 Series - 74 H series is the high speed range Noise Margin 0.35 V
with low propagation delay (6ns) but high power Fan in 5
dissipation (23 mw per gate ) Fan - out 8
• 7400 - Quad 2-input NAND gate • ECL (Emitter coupled logic) - High speed of operation
• 74L00- Low power /low speed and non - saturated logic.
72. In the circuit given below, both transistors have Basic Gate OR/NOR
the same VT. What is approximate value of the
highest possible output voltage Vout, if Vin can Power dissipation 40 - 55 mw
range from 0 to VDD? (Assume 0 < VT <VDD) Propagation delay 1 n sec
74. Find Y = ?
(a) (x + y).z (b) (x + y)+z

(a) VDD- VT (b) VDD (c) (x.y)+z (d) (x.y).z
(c) VT (d) 0 BARC Scientific Officer-2016
IES-2005 Ans. (a) : Y = (x+y).z
Ans. (a) : The given circuit is inverter by NMOS Vin
range from 0 to VDD NMOS will on when VGS > VT
When Vin = 0
T1 is ON state
T2 is OFF state
Then Vout = VDD − VT
73. Match List-I (Logic Gates) with List-II 75. Match List-I (Logic Gates) with List-II (Power
(Characteristics) and select the correct answer dissipation per gate in mW) and select the
using the code : correct answer using the code given below the
List-I List-II lists :
A. HTL 1. High Fan-out List-I List-II
B. CMOS 2. Highest speed of operation A. DTL 1. 55
C. I2L 3. High noise immunity B. TTL 2. 10
D. ECL 4. Lowest product of power C. ECL 3. 8
and delay D. MOS 4. 1
Codes : 5. 40
A B C D Codes :
(a) 3 2 4 1 A B C D
(b) 4 2 3 1 (a) 3 5 4 2
(c) 3 1 4 2 (b) 1 2 5 4
(d) 4 1 3 2 (c) 3 2 5 4
IES-2010, 2007, 2006, 2004, 1994 (d) 1 5 4 2
KVS TGT (WE)-2014 IES-2002
Ans. (c) Ans. (b)
Logic families Power dissipation Logic familes Noise margin
(a) DTL 8-12 mW RTL 0.02V
(b) TTL 10 mW DTL 0.75V
(c) ECL 40-55 mW HTL 4 - 5V
TTL 0.4V
(d) MOS 02-10 mW
ECL 0.16V
(e) RTL 12 mW MOS 1.5V
(f) HTL 55 mW According question increasing order - RTL → ECL →
(g) CMOS 0-0.1 mW DTL → MOS.
76. Match List-I with List-II and select the correct 79. In the negative logic system,
answer using the code given below the lists : (a) The more negative of the two logic 'levels
List-I List-II represents a logic '1' state
(b) The more negative of the two logic levels
A. TTL 1. Low propagation delay represents a logic 'o' state
B. ECL 2. Low power consumption (c) All input and output voltage level are
C. MOS 3. Higher packing density on negative
Si wafer (d) The output is always complement of the
D. CMOS 4. Saturated bipolar logic intended logic function.
5. High fan-out IES-2001
Codes : Ans. (a) : • If the signal that activates the logic gate has
A B C D for its high (1) level a voltage more negative than for its
low (0) level then the polarity of the logic is called
(a) 3 2 4 1
negative logic.
(b) 4 2 3 1
80. The voltage levels of a negative logic system
(c) 3 1 4 2 (a) Must necessarily be negative
(d) 4 1 3 2 (b) May be negative or positive
KVS TGT (WE)-2014 (c) Must necessarily be positive
IES-2002, 1996 (d) Must necessarily be 0 V and –5 V
Ans. (d) : (a) TTL- saturated bipolar logic RRB SSE-01.09.2015, Shift-III
(b) ECL- low propagation delay (non- saturated logic) IES-1999
(c) MOS- Higher packing density on Si wafer Ans. (b) : The voltage level of a negative logic system
(d) CMOS- low power consumption, High fan out. may be negative or positive.
Positive logic Negative Logic
77. The open collector output of two 2-input 1 0
NAND gates are connected to a common pull- 5 –5
up resistor. If the inputs of the gates are A, B 4 2
and C, D respectively, the output is equal to -3 –7
(a) AB.CD (b) AB + CD High Low
(c) AB + CD (d) AB.CD 81. The load resistance RL between X and Y in the
switch shown in Figure-I.
IES-2002
Ans. (a) :
78. Consider the following logic families :

1. MOS 2. DTL CANNOT be replaced by
3. RTL 4. ECL
The sequence of these logic families in the
order of their increasing noise margin is
(a) 3, 4, 1, 2 (b) 3, 4, 2, 1 (a) (b)
(c) 4, 3, 1, 2 (d) 4, 3, 2, 1
IES-2001

Note :- A standard TTL VOL = 0.4 V
84. TTL circuits with active pull-up are preferred
because of their suitability for
(c) (d) (a) Wired-And Operation
(b) Bus operated system
(c) Wired logic operation
(d) Reasonable dissipation and speed of
IES-1999 operation.
Ans. (d) : The major advantage of MOS technology is IES-1998
that it can be used not only as a switch, but as a resister Ans. (d) : TTL circuits with active pull-up are preferred
as well. The base and emitter of the transistor can never because of their suitability for optimum power
be connected directly as the transistor will remain in dissipation and speed of operation.
OFF state. 85. Consider the following statements regarding
82. Consider the following statements regarding configuration of TTL devices:
ICs: 1. The output impedance of totem pole
1. ECL has the least propagation delay. transistor is high.
2. TTL has the largest fan-out. 2. Open collector output devices have low
switching speed.
3. CMOS has the biggest noise margin.
3. Power consumption of Schottky devices is
4. TTL has the lowest power consumption. high.
Which of these statements are correct? 4. Tri-state output devices have high
(a) 1 and 3 (b) 2 and 4 switching speed.
(c) 3 and 4 (d) 1 and 2 Of these statements:
IES-1999 (a) 1 and 2 are correct
Ans. (a) : ECL has the least propagation delay (b) 1, 3 and 4 are correct
(2 nsec). (c) 2 and 3 are correct
TTL has the highest speed in saturated logic. (d) 2, 3 and 4 are correct
CMOS has the biggest noise margin (1.5 V) IES-1998
83. For a logic family, Ans. (c) : TTL circuit are classified as :-
(i) Tristate logic (High impedance logic)
VOH is the minimum output high level voltage
(ii) Totem pole logic (active pull up)
VOL is the maximum output low level voltage (iii) open collector logic ( Passive pull up)
VIH is the minimum acceptable input high level
• Power consumption of Schottky device is high.
voltage
• Open collector output devices have low switching
VIL is the maximum acceptable input low level speed.
voltage
86. The schematic shown in the figure indicates
The correct relationship among these is
(a) VIH > VOH > VIL > VOL
(b) VOH > VIH > VIL > VOL
(c) VIH > VOH > VOL > VIL
(d) VOH > VIH > VOL > VIL
IES-1999
Ans. (b) : Voltage Parameters -
(i) High Level Input Voltage (VIH) - The minimum
voltage at which the input can be considered at logic 1
level is called VIH.
(a) CMOS NOR gate
Note: A standard TTL VIH = 2V
(b) CMOS NAND gate
(ii) Low Level Input Voltage (VIL) - The maximum (c) CMOST AND gate
voltage at which the input can be considered at logic 0
(d) CMOS transmission gate
level is called VIL.
IES-1997
Note:- A standard TTL VIL = 0.8V
Ans. (d) : CMOS transmission gate – Connecting
(iii) High Level Output Voltage (VOH) - The
minimum voltage at which the output can be considered PMOS and NMOS device together in parallel is known
at logic 1 Level is called VOH. as transmission gate. It is made by a complementary
Note :- A standard TTL VOH = 2.4 V MOSFET (ie P channel and n channel). It is given input
(iv) Low Level Output Voltage - (VOL) - C and its complementary signal C . If C = 1 then the
The maximum voltage at which the output can be gate transmits the input signal output (VO = Vi ) and if C
considered at logic '0' level is called VOL. = O then there is no transmission.

87. Output of the circuit shown below when S = 1 Ans. (b) : Since the given logic is wired and logic.
and S = 0 will be _____.
Hence, E = ABCD = AB + CD
89. Which one of the following logic functions is
implemented by the gates when their open
collector type outputs are tied together as
shown in the given figure?
(a) f = AB + C + D (b) f = AB + ( C + D )
(c) f = AB + (C + D) (d) f = AB + C + D
IES-1996
(a) P and High Impedance state respectively
(b) High Impedance state and P' respectively Ans. (d) : Output of NAND gate = A.B
(c) 0 and 1 respectively Output of NOR gate = C + D
(d) X and P respectively Now when both gate output tied together then
Ans. (b) : In given logic family PMOS and NMOS are
Y = A.B .C + D ( )
connected in series. = ( A.B ) + ( C + D )
In CMOS, if Input is HIGH–
PMOS → OFF, NMOS → ON 90. The circuit shown in the given figure is a
If input is LOW-
PMOS → ON, NMOS→ OFF
Now, when S = 1
(a) Positive logic OR circuit

(b) Negative logic OR circuit
(c) Positive logic NAND circuit
(d) Negative logic NAND circuit
When S = 0
IES-1995
Ans. (b) :
A B Y A B Y
0V 0V 0V 0 0 0
0V −5V −5V ⇒ 0 1 1
−5V 0V −5V 1 0 1
Hence, When S = 1, S = 0, then the output will be high
−5V −5V −5V 1 1 1
impedance state and P respectively.
88. The output of the gate circuit shown in the 0 = Logic '0' and –5 = logic '1'. The circuit is a negative
given figure is OR logic circuit.
91. The logic function performed by the circuit
given in the figure is
(a) (A + B) (C + D) (b) AB + CD (a) Y0 = XlX2 (b) Y0 = Xl + X2

(c) AB + CD (d) (A + B)(C + D) (c) Y0 = X1 X 2 (d) Y0 = X1 + X 2
IES-1996 IES-1995
Ans. (c) : If any one of the input is '1' the output is '0' Ans. (c) :
because one of the transistor is in the ON state. Hence,
truth table is -
X1 X2 Y = X1.X 2
0 0 1
0 1 0
1 0 0 Y = ( A + B ).( C + D )
1 1 0
95. In CMOS implementation of a NAND gate:
92. If the various logic families are arranged in the (a) All the PMOS and NMOS are in series
ascending order of their fan-out capabilities, (b) The two PMOS are in parallel and two
the sequence will be NMOS are in series
(a) TTL, ECL, IIL, CMOS (c) All the PMOS and NMOS are in parallel
(b) ECL, TTL, IIL, CMOS (d) The two PMOS are in series and two NMOS
(c) IIL, TTL, ECL, CMOS are in parallel
(d) TTL, ECL, CMOS, IIL UPMRC AM - 2020
IES-1995 Ans. (b) : In CMOS implementation of a NAND Gate,
Ans. (c) : the two PMOS in parallel and two NMOS are in seies
used. CMOS is a combination of PMOS and NMOS.
Logic families Fan out CMOS is used in µ processors, µ controller, static RAM
PIL 4 and other digital circuit.
DCTL 4 96.
DTL 8
I2L 8
HTL 10
TTL 10
ECL 25
CMOS 50
Ascending order of fan out. The diode cut in voltage is 0.6 V and voltage
I2L < TTL < ECL< CMOS drop across the conducting diode is 0.7V If
V1 = 10V and V2 = 0V then:
93. In positive logic, the transistor gate in the
(a) V0 = 0.7V (b) V0 = 8.37V
circuit below is an
(c) V0 = 3.87V (d) V0 = 4.07V
UPMRC AM - 2020
Ans. (b) : V1 = 10 V, V2 = 0 V
We assume the Diode D1 is forward biased and D2 is
reverse bias
(a) AND gate (b) NOR gate

(c) NAND gate (d) OR gate
Ans. (b) : In positive logic, the transistor gate in the
Applying KCL and V0 we get
circuit below is a NOR gate
V0 + 0.7 − 10 V0
94. The open collector of the gates are connected + =0
together as shown in the given figure. The logic 2k 18k
expression for Y will be 9 ( V0 − 9.3) + V0 = 0
9V0 − 83.7 + V0 = 0
10V0 = 83.7
V0 = 8.37
97. Two voltage given as -2 V and -1V in positive
logic convention represent:
(a) A + B + C + D (b) A + B + C + D
(a) -2V is logic 1 and -1 V is logic 0
(c) (A + B) (C + D) (d) AB + CD (b) -5 V is logic 0 is some circuit and 1 in the
IES-1994 other
(c) -2 V is logic 0 and -1 V is logic 1 Ans. (b) : Given that -
(d) -5 V is logic 1 in some circuits and 0 in the I = – 0.4 mA
OH max
other
DFCCIL Executive (S&T) 11.11.2018, 4:30 to 6:30PM IOLmax = 8 mA
Ans. (c) :Positive logic convention represents higher I = 20 µA
IH max
voltage corresponds to logic ‘1’ and lower voltage
corresponds to logic ‘0’. Then –2V is represents to logic I ILmax = –0.1 mA
‘0’ and –1V represents to logic ‘1’. IOH(max) 0.4 × 10−3
98. Following figure represents Hence (Fan out)H = = = 20
I IH(max) 20 × 10−6
IOL(max) 8 × 10−3
(Fan out)L = = = 80
I IH(max) 0.1× 10−3
Fan out = min of ( Fan out ) H , ( Fan out )L 
Hence, Fan out = 20
101. For the NMOS logic gate shown in figure, the
(a) AND (b) OR logic function implemented is
(c)NAND (d) XOR
Ans. (c) : From the following circuit –
It is clear that both diode D1 and D2 are connected in
opposite ways and is connected in parallel. So it is a
NAND circuit diagram.
99. Figure shows the circuit of a gate in the
Resistor Transistor Logic (RTL) family. The (a) ABCDE (b) (AB + +C).(D + E)
circuit represents a
(c) A.(B + C) + D.E (d) (A + B).C + D.E
GATE-1997
Ans. (c) :
(a) NAND (b) AND

(c) NOR (d) OR
GATE-1992
Ans. (d) : The truth table of the given Fig is -
∴ F = A ( B + C ) + DE
V11 V12 T1 T2 T3 V0
0 0 OFF OFF ON 0 102. The gate delay of an NMOS inverter is
dominated by charge time rather than
0 1 OFF ON OFF 1 discharge time because
1 0 ON OFF OFF 1 (a) the driver transistor has a larger threshold
1 1 ON ON OFF 1 voltage than the load transistor
From the table we can see that output V0 will be low (b) the driver transistor has larger leakage
when all the input are low and if any of the input is high currents compared to the load transistor
then the output will be high. (c) the load transistor has a smaller W/L ratio
Hence, the circuit will represent OR gate. compared to the driver transistor
100. The inverter 74 AL S01 has the following
specifications:
GATE-1997
IOH max = -0.4 mA, IOL max = 8 mA, IIH max = 20
µA, IIL max = -0.1 mA. Ans. (c) : In NMOS inverter, if load transistor has
smaller W/L ratio as compared to driver, then inverter is
The fan out based on the above will be dominated by charge time.
(a) 10 (b) 20
103. In the TTL circuit in the figure, S2 and S0 are
(c) 60 (d) 100 select lines and X7 and X0 are input lines. S0
GATE-1997 and X0 are LSBs. The output Y is
One of three output circuit configuration commonly
TTL versions referred to -
1. Totem-pole output
2. Open collector output
3. Tri-state output
106. The DTL, TTL, ECL and CMOS families gate
of digital ICs are compared in the following 4
columns
(P) (Q) (R) (S)
(a) indeterminate
(b) A ⊕ B Fan out is DTL DTL TTL CMOS
minimum
(c) A ⊕ B
Power TTL CMOS ECL DTL
(d) C(A ⊕ B) + C(A ⊕ B) consumption
GATE-2001 is minimum
Ans. (b) : The input of floating is passed by TTL logic Propagation CMOS ECL TTL TTL
gate as logic 1. delay is
Hence S2 = 1 minimum
The correct column is
(a) P (b) Q
(c) R (d) S
Given, S0 = A, S1 = B, S2 = C + 1 = 1 GATE-2003
and x0, x3, x5, x6 = 1 Ans. (b)
x1, x2, x4, x7 = 0 Parameter DTL ECL TTL CMOS
For 8 to 1 multiplexer, there are total eight inputs and 3
selection lines. Basic gate NAND OR- NAND NAND
NOR -NOR
For 8 to 1 multiplexer the output
Fan out 8 25 10 50
Y = S0 S1S2 x 0 + S0 S1S2 x1 + S0S1S2 x 2 + S0S1S2 x 3
Power 8-12 40-55 10 0.1
+S0 S1S2 x 4 + S0 S1S2 x 5 + S0S1S2 x 6 + S0S1S2 x 7 consumption
Y = 0 + 0 + 0 + AB + 0 + AB + 0 + 0 (mw)
Y = AB + AB Propagation 30 2 10 70
delay (ns)
Y=A⊕B
• Minimum. Fan out - DTL
104. The circuit in the figure has two CMOS NOR-
gates. This circuit functions as a : • Minimum. Power consumption - CMOS
• Minimum propagation delay (ns) - ECL
107. Given figure is the voltage transfer
characteristic of
(a) flip-flop
(b) Schmitt trigger
(c) monostable multi-vibrator
(d) astable multi-vibrator
GATE-2002 (a) an NMOS inverter with enhancement mode
Ans. (c) : The circuit functions as a monostable transistor as load
multivibrator. (b) an NMOS inverter with depletion mode
transistor as load
105. The output of the 74 series gate of TTL gates is (c) a CMOS inverter
taken from a BJT in
(d) a BJT inverter
(a) totem pole and common collector
configuration GATE-2004
(b) either totem pole or open collector Ans. (c) :
configuration
(c) common base configuration
(d) common collector configuration
GATE-2003
Ans. (b) : The output of the 74 series of TTL gate is
taken from a BJT in either totem pole or open collector
configuration.

At Vin = 0
Vout = high
And
At Vin = high
Vout = 0
Very close to be ideal inverter - CMOS.
Hence, correct option is C.
108. The figure shows the internal schematic of a
TTL AND-OR-Invert (AOI) gate. For the
inputs shown in the figure, the output Y is (a) 1 V (b) 2 V
(c) 3 V (d) 4 V
GATE-2005
Ans. (c) : Given That - VTh = 1 V
K1 = 36 µA/V2
K2 = 9 µA/V2
(a) 0 (b) 1 VD = ?
(c) AB (d) AB I D1 = I D2 ( Sat. mode)
GATE-2004
( ) ( )
2 2
Ans. (a) : For TTL logic floating input = 1 K1 VGS1 − VTh = K 2 VGS2 − VTh
When give input 1
⇒ 36 ( 5 − V0 − 1) = 9 ( V0 − 0 − 1)
2 2
Than -
4 ( 4 − V0 ) = ( V0 − 1)
2 2
2 ( 4 − V0 ) = ( V0 − 1)
109. The transistors used in a portion of the TTL V0 = 3V

gate shown in the figure have a β = 100. The 111. The circuit diagram of a standard TTL NOT
base-emitter voltage of is 0.7 V for a transistor gate is shown in the figure. When Vi = 2.5 V the
in active region and 0.75 V for a transistor in modes of operation of the transistors will be
saturation. If the sink current I = 1 mA and the
output is at logic 0, then the current IR will be
equal to
(a) 0.65 mA (b) 0.70 mA

(c) 0.75 mA (d) 1.00 mA (a) Q1 : reverse active;(b) Q1 : reverse active;
GATE-2005 Q2 : normal active; Q2 : saturation;
Ans. (c) : Given that - β = 100 Q3 : saturation; Q3 : saturation;
VBE = 0.7 V - Active region Q4 : cut-off Q4 : cut - off
VBE = 0.75V - Saturation region (c) Q1 : normal active; (d) Q1 : saturation;
Sink current I = IC = 1 mA Q2 : cut-off; Q2 : saturation;
IR = ? Q3 : cut-off; Q3 : saturation;
Hence when the output is at logic '0'. Q4 : saturation Q4 : normal active
Transistor 2 is in saturation and transistor 3 in cut off. GATE-2007
Hence, VBE (Sat.) = IR.1k Ans. (b) : For transistor Q1, Vi = 2.5V and base
0.75 connected to 5V ⇒ Q1 is in reverse active, hence
IR = = 0.75mA
1k current flows from base to collector of Q1. It implies Q2
IR = 0.75 mA and Q3 goes into saturation and Q4 is cut-off mode.
So,
110. Both transistors T1 and T2 shown in the figure,
have a threshold voltage of 1 Volts. The device Q1 : Reverse active
parameters K1 and K2 of T1 and T2 are Q2 : Saturation
respectively, 36 µA/V2 and 9 µA/V2. The output Q3 : Saturation
voltage V0 is Q4 : Cut-off
112. The logic function implemented by the In the given figure -
following circuit at the terminal OUT is • A + B (as A || B)
• C series with (A + B) in N channel.
• C (A + B) [reverse in P]
• Y = C (A + B)
Y = C ( A + B)
= C+A+B
Y = AB+ C
(a) P NOR Q (b) P NAND Q Hence option (a) is correct.
(c) P OR Q (d) P AND Q 115. In the circuit shown below Q1 has negligible
GATE-2008 collector-to-emitter saturation voltage and the
diode drops negligible voltage across it under
Ans. (d) : From the circuit in N-MOS → PQ in series forward bias. If Vcc is +5 V, X and Y are digital
and in P-MOS → PQ in parallel. signals with 0 V as logic 0 and Vcc as logic 1, the
So, P.Q = P AND Q Boolean expression for Z is
Hence, option (d) is correct.
113. The full forms of the abbreviations TTL and
CMOS in reference to logic families are
(a) Triple Transistor Logic and Chip Metal Oxide
Semiconductor
(b) Tristate Transistor Logic and Chip Metal
Oxide Semiconductor
(c) Transistor Transistor Logic and
Complementary Metal Oxide Semiconductor (a) XY (b) XY
(d) Tristate Transistor Logic and Complementary (c) XY (d) XY
Metal Oxide Silicon GATE-2013
GATE-2009 Ans. (b) :
Ans. (c) : TTL - Transistor Transistor Logic
CMOS - Complementary Metal Oxide Semi-conductor
Hence, option 'c' is correct.
114. In the circuit shown
• The TTL circuit has output of X .

• The diode is ideal for Y = 1 i.e. reverse voltage of
diode is 0V hence Z and Y are open circuit.
Hence Z = X
For Y = 0 i.e. reverse voltage of diode is zero hence Z =

0.
(a) Y = AB + C (b) Y = (A + B)C So that as per description of the questions, when the
transistor Q1 and diode both are OFF then only output
(c) Y = (A + B)C (d) Y = AB + C Z=1.
GATE-2012 Hence Z = XY
Ans. (a) : 116. In the following circuit employing pass
transistor logic, all NMOS transistors are
identical with a threshold voltage of 1 V.
Ignoring the body-effect, the output voltages at
P, Q and R are,

(a) 4 V, 3 V, 2 V (b) 5 V, 5 V, 5 V Ans. (a) :
(c) 4 V, 4 V, 4 V (d) 5 V, 4 V, 3 V
GATE- 2014, Set-I
Ans. (c) :
Threshold voltage (VT) = 1 V

For the Ist pass transistor logic -
VD = 5
VG – VT = 5 – 1 = 4 V
VD > VG –VT • Check by NMOS these are series
VS = VG – VT y = A.B.C
VP = VD2 = VS − VT = 4 V
= A + B + C.
For 2nd pass transistor logic - Therefore the output will be ( A + B + C )
VD = 5
118. In the circuit shown, diodes D1, D2 and D3 are
VG – VT = 4 V ideal, and the inputs E1, E2 and E3 are '0 V' for
VD > VG – VT logic '0' and '10 V' for logic '1'. What logic gate
does the circuit represent ?
VQ = VD3 = 4 V
For 3rd pass transistor logic -
VD = 5 V
VG –VT = 4 V
VD > VG –VT
VR = 4 V
Hence, output voltages at P, Q and R are 4 V, 4 V and 4
V respectively.
(a) 3 input OR gate (b) 3 input NOR gate
117. The output (Y) of the circuit shown in the (c) 3 input AND gate (d) 3 input XOR gate
figure is GATE-2015, Set-III
Ans. (c) : Given that -
0 Volt - logic '0'
10 Volt - logic '1'
Case 1 - If any input is logic 0 (i.e. 0V) then
corresponding diode is 'ON' an due to ideal diode output
voltage V0 = 0
Case 2- when all the diode are off i.e. when all of E1 =
E2 = E3 = 10 Volts, then the current across the 1 kΩ
resistor = 0 and V0 = 10V.
Hence the given circuit is a 3 input AND gate.
119. An SR latch is implemented using TTL gates as
shown in the figure. The set and reset pulse
(a) A + B + C (b) A + B.C + A.C inputs are provided using the push-button
switches. It is observed that the circuit fails to
(c) A + B + C (d) A.B.C
work as desired. The SR latch can be made
GATE-2014, Set-II functional by changing
(a) OR (b) XOR
(c) NAND (d) AND
(a) NOR gates to NAND gates GATE - 2016, Set-III
(b) inverters to buffers Ans. (d) :
(c) NOR gates to NAND gates and inverters to
buffers
(d) 5 V to ground
Ans. (d) : • In the TTL logic gate, it will considered as
logic 1 when it will open and or floating end. When B = 1 and B = 0
• For the circuit to work as on S & R latch, S & R Hence M1 is ON while M2 is OFF.
should act as logic-0 as well as logic 1 on requirement. So that output Y = A
• Hence if we connect 5 V battery to ground then Now is B = 0 and B = 1
pressing the switches allow logic '0' while open the That M1 is OFF and M2 is ON
switches allow logic 1. So that output Y = 0
• Now if we connect set which is equal to 5 volt then it The output logic 1 when
will considered as logic 1, hence circuit cannot act as Y = A.B.B = A.B
SR latch. Hence, the circuit shown perform logic functionality of
• So that for the above circuit to work as an SR latch 5 AND gate.
volt battery should connect to ground. 122. The logic f(X, Y) realized by the given circuit is
120. The circuit shown in the figure is
(a) An AND gate (b) An OR gate

(c) A XOR gate (d) A NAND gate (a) NOR (b) AND
(c) NAND (d) XOR
GATE-2018
Ans. (b) : This figure represent for An OR gate. Ans. (d) : The truth table for given logic -
X Y Z
0 0 0
0 1 1
1 0 1
1 1 0
( )
Output f ( X, Y ) = X.Y + ( X.Y )
B A OUT = ( X.Y ). ( X.Y )

0 0 0
0 1 1 = ( X + Y ) .( X + Y )
1 0 1 = XX + XY + XY + YY
1 1 1 = XY + XY
121. The logic functionality realized by the circuit = X⊕Y
shown below is Hence, the logic realized by given circuit is XOR gate.

123. In the circuit shown, A and B are the inputs (a) NML decreases and NMH increases.
and F is the output. What is the functionality of (b) No change in the noise margins.
the circuit ? (c) Both NML and NMH increase.
(d) NML increases and NMH decreases.
GATE-2019
Ans. (d) : For dynamic operation, the condition is
described by the time response during Switching
condition The behavior of the CMOS inverter for static
conditions of operation is described by voltage Transfer
characteristics
VOH = VDD
βn µ n co x ( W / L )
Kr = =
(a) XNOR (b) SRAM Cell βp µ p cox ( W / L )
(c) XOR (d) Latch  NM L = VIL − VOL 
GATE-2019  
Ans. (a) : The truth table for the given circuit is -  NM H = VOH − VIH 
∴ W ↑→ NM ↑ 
A B Y  P L

0 0 1  WP ↑→ NM H ↓ 
0 1 0 126. In the circuits shown, the threshold voltage of
1 0 0 each NMOS transistor is 0.6 V. Ignoring the
1 1 1 effect of channel length modulation and body
The given logic XNOR. bias, the values of Vout 1 and Vout 2 respectively,
in volts, are
124. In the circuit shown, what are the values of F
for EN = 0 and EN = 1, respectively ?
(a) 0 and 1 (b) Hi - Z and D

(c) Hi- Z and D (d) 0 and D
GATE-2019
Ans. (b) : NMOS is ON when VG is high and PMOS is
ON when VG is low.
Case I- When EN = 0 (a) 1.8 and 2.4 (b) 2.4 and 1.2
O/P of NAND = 1 (c) 1.8 and 1.2 (d) 2.4 and 2.4
PMOS = OFF GATE-2019
O/P of NOR = 0 Ans. (a) :
NMOS = OFF
Hence O/p = High impedance (Hi - Z)
Case-I Now if EN = 1
Output of NAND = D
If D = 1, D = 0
And D = 0 then D = 1 For the pass transistor logic
Hence PMOS - OFF VD = VG – Vth (Vth = threshold voltage)
And O/P of NOR = D V G2 = V G1
So that the output F = D = D (inverter operation) So,

125. A standard CMOS inverter is designed with VD1 = VG1 − Vth
equal rise and fall times (β n = β p). If the width Given = VG1 = 3V
of the PMOS transistor in the inverter is
increased, what would be the effect on the Vth = 0.6 V
LOW noise margin (NML) and the HIGH noise VD1 = 3 – 0.6
margin NMH ? = 2.4V
VD2 = VG2 – Vth = Vout1 131. Among all the logic families the CMOS has
= 2.4 – 0.6 become the most preferred for VLSI and ULSI
= 1.8 V because :
(a) It is the fastest.
Vout1 = 1.8V (b) It is most immune to noise.
VD = VG1 – Vth (c) It’s design is the easiest.
Given VG1 = 3V, Vth = 0.6V (d) It consumes no static power.
VD = 3 – 0.6 APPSC POLY. LECT. 14.03.2020
= 2.4 V Ans. (d) : Among all the logic families the CMOS has
VD2 = VG2 = Vth become the most preferred for VLSI and ULSI because
3 – 0.6 = 2.4V it consumes no static power.
VD3 = VG3 – Vth = 3 – 0.6 = 132. The following logic families have their
Vout2 = 2.4V propagation delay. Arrange them from lowest
127. The propagation delay for ECL IC family is propagation delay to highest propagation
approximately delay.
(a) 2ns (b) 10ns 1. TTL (Standard) 2. ECL
(c) 25ns (d) 50ns 3. Low power CMOS 4. DTL
Kerala PSC Lecturer (NCA) 04.07.2017 (a) 2, 1, 4 and 3 (b) 2, 4, 1 and 3
UPRVUN AE-11.06.2014 (c) 4, 2, 3 and 1 (d) 1, 2, 3 and 4
Ans. (a) : ECL IC family has propagation delay
approximately 2ns. It is old technology and the speed t +t
Ans. (a) : t pd = PHL PLH speed of operation is related
due to the facts that the transistor never enter saturation. 2
128. The switching speed of ……. is lowest to the propagation delay, so it is advantages to have
(a) TTL (b) ECL smaller t pd .
(c) I2L (d) CMOS
Ans. (d) : ECL offers propagation delay of 2ns. CMOS
logic consumes very low power dissipation because,
there is zero static power dissipation means power
dissipation will occur only when P-MOS i.e. pull up
transistor is ON. However CMOS is slowest among the
given logic family because of high input impedance,
133. In standard TTL gates, the totem pole output
takes more time for charging and discharging.
stage is primarily used to
129. The most widely used bipolar technology for (a) increase the noise margin of the gate
digital ICs (b) decrease the output switching delay
(a) DTL (b) TTL (c) facilitate a wired OR logic connection
(c) ECL (d) None (d) increase the output impedance of the circuit
TSPSC Manager (Engg.) - 2015 APGENCO AE- 23.04.2017
Punjab PSC Poly. Lect. -20.08.2017 KVS TGT (WE)-2016
Ans. (b) : TTL- Transistor transistor logic (TTL) is the Ans. (b) : In TTL the output stage has two transistor
most widely used bipolar technology for manufacturing amplifiers (on CE and another CC) connected in push
digital integrated circuits. This is mainly due to the fact pull configuration to act as current sink and source at
that it was one of the first to be developed. Because of output stage.
their widespread use, TTL chips are also the least The main advantage of TTL with a "totem - pole"
expensive and most accessible of the logic types within output stage is the low output resistance at output
the category of TTL gates there several different logical "1" also addition of an active pull up circuit in
performance classes. No of fan out of TTL is 10 and the output of the gate which results in reduction of
noise margin about 0.4 V. propagation delay.
130. Fan-out for the 74 series is 134. The worst case input voltage (VIL for low input
(a) 4 (b) 5 and VIH for high input) and the worst case
(c) 8 (d) 10 output voltage of VOL for low output and VOH
TSPSC Manager (Engg.) - 2015 for high output) for 7400 TTL are :
Ans. (d) : Fan out - One output can drive upto 10, 74LS (a) VIL,max = 0.8V, VIH,min = 2V, VOL,max = 0.4V,
inputs, but many more 74HCT inputs. VOH,min = 2.4V
Gate propagation time - About 10ns for a signal to (b) VIL,max = 0.6V, VIH,min = 2V, VOL,max = 0.4V,
travel through a gate. VOH,min = 2.8V
Frequency - Up to about 35 MHz (under the right (c) VIL,max = 0.4V, VIH,min = 2.4V, VOL,max = 0.8V,
conditions). VOH,min = 2V
(d) VIL,max = 0.4V, VIH,min = 2.8V, VOL,max = 0.6V, 138. The IC type number 74C00 belongs to
VOH,min = 2V (a) Standard TTL logic family
APPSC Poly. Lect. 15.03.2020 (b) High speed TTL family
UPRVUNL AE-2016 (c) CMOS family pin compatible with TTL
Ans. (a) (d) none of these
Ans. (a) : The 7400 IC using NAND Gate are most
generally used transistor - transistor logic (TTL) device.
It can be built with 4 independent 2 input NAND gate.
139. The logic family that has the highest noise
immunity of the following is
∆0 Noise-margin = VIL − VOL (a) CMOS (b) TTL
= 0.8 V – 0.4 V (c) ECL (d) DTL
= 0.4 V Nagaland PSC- 2018, Diploma Paper-II
High state noise margin or immunity. Ans. (a) : The two most important characteristic of
VOH (Minimum output voltage for high out state)= 2.4V CMOS device are high noise immunity and low power
dissipation.
140. Negative NOR (a NOR in the negative positive
logic system) becomes a Positive
(a) NAND (b) NOR
(c) OR (d) none of these
Ans. (a) :
135. Which one of the following is not a
characteristic of RTL logic families?
(a) High switching speed (–) Ve NOR gate    (+) Ve NAND gate
(b) Poor noise immunity Hence (–) Ve NOR gate to equivalent to (+) Ve NAND
(c) Low power dissipation gate.
(d) Fan out is 5 141. Which of the following logic has the fanout of
Nagaland PSC (Degree) 2018, Paper-II more than 50?
Ans. (c) : RTL logic families have high speed, less (a) TTL (b) 4-ηs ECL
noise immunity, high power dissipation. (c) 8-ηs ECL (d) CMOS
136. The output of logic circuit as shown in figure is Nagaland PSC CTSE- 2015, Paper-II
given by : Ans. (d) : While choosing a particular digital IC for an
application, its specification or characteristics should be
taken into account.
FAN–IN: The number of inputs that can be connected
to a logic gate is called its Fan in.
Fan-out: The number of units that can be connected to
the output of a logic gate is called its Fan-out.
FAN out → TTL ECL CMOS
(a) Y = ABC (b) Y = ABC 10 25 more than 50
142. Some of MOS families are PMOS, NMOS,
(c) Y = A + B + C (d) Y = A + B + C
CMOS. The family dominating the LSI field
MPSC HOD Govt. Poly. -2013 where low power consumption is necessary is –
Ans. (d) : In the diagram when all of three diode, in (a) NMOS (b) CMOS
which one is conducting, Vout will occurs. So, (c) PMOS (d) Both NMOS and PMOS
Y = A+ B+C Nagaland PSC CTSE- 2015, Paper-II
137. Extremely low power dissipation and low cost Ans. (b) : CMOS stands for complementary – MOS, in
per gate can be achieved in the following IC: which both p-Channel and n-Channel enhancement
(a) ECL (b) CMOS MOSFET devices are fabrication on same chip. This
(c) TTL (d) MOS causes density to be reduced and complex fabrication
Nagaland PSC (Degree) 2018, Paper-II process. However, CMOS device negligible consume
power and hence are preferred over MOS devices in
Ans. (b) : • CMOS IC's have low power dissipation & battery operated applications.
low cost per gate.
143. MOS logic gates have no current hogging
• CMOS used in computer memory. problem because the gate terminal has
• Microprocessor designs (a) High impedance
• Flash memory chip designing (b) Low input impedance
(c) Zero impedance 148. The Boolean expression for the following
(d) Compensating effect circuit is
Ans. (a) : A MOS logic gates have very high input
impedance. Which provides excellent insulation this is
due to the fact that SiO2 layer is inside the gate which
prevents current hogging problem.
144. NMOS devices have _______ switching speeds
and ______ on-state resistance; as compared
with PMOS devices.
(a) slower, higher (b) faster, lower
(c) faster, higher (d) slower, lower (a) AB + AC + BC (b) A + BC
NIELIT Scientists- 2017 (c) A + B (d) A + B + C
Ans. (b) : In NMOS devices, we have high mobility of IES - 1995
electrons than holes in PMOS. Consequently higher Ans. (d) :
conductivity and lower on state resistance.
145. In a 3-input CMOS NAND gate, the substrate
terminals of NMOS transistors are grounded
(lowest potential available in the circuit) and
the substrate terminals of PMOS transistors
are connected to VDD (maximum positive
potential in the circuit). Which of the following
transistors may suffer in this circuit from body
bias effect?
(a) 2 NMOS transistors (b) 2 PMOS transistors
(c) 1 NMOS transistors (d) 1 PMOS transistors Y = ( B + C ) .A + A B + ( A + B ). C
Ans. (a) : Body bias effect:- Y = AB+A C + A B + AC + B C
• It is used to dynamically adjust the threshold voltage Y = B(A + A ) + A ( C + C ) + B C QA + A = 1
(Vt) of a CMOS transistor.
Y = B + A + BC QB + B = 1
• The voltage difference between the source (Vs) and
the body voltage (Vb) effect the threshold voltage (Vt) Y = A +( B + B )( B + C ) QC + C = 1
• So 2-NMOS transistors suffer body bias effect. Y=A+B+C
146. The output of the 74 series of TTL gates is 149. CMOS inverter has_____regions of operation
taken from a BJT in
(a) three (b) four
(a) Totem pole and common collector
configuration (c) two (d) five
(b) Either totem pole or open collector Nagaland PSC CTSE (Diploma)-2017, Paper-I
configuration Ans. (d) : CMOS inverter has five distinct regions of
(c) Common base configuration operation which can be determined by plotting CMOS
(d) Common collector configuration inverter current versus input voltage.
Nagaland PSC CTSE (Degree)-2017, Paper-II 150. Find Y
Ans. (b) : When output of the 74 series gate of TTL
gates is taken from BJT then the configuration is either
totem pole or open collector configuration.
147. Among the following logic families, the one
having the lowest power dissipation and highest
noise margin is
(a) Schottky TTL (b) TTL
(c) ECL (d) CMOS
BSNL (JTO)-2009
Ans. (d) :
Logic Basic Gate Power Noise
Parameter dissipation Margin
TTL NAND 12-22 0.4 (a) (A + B)C + D (b) ( A + B) C + D
(mW)
(c) ( A.B ) + C  .D (d) ( A.B ) + C  .D
ECL OR/NOR 40-5 (mW) 0.3
CMOS NAND/NOR 0.1 (mW) 1.5 BARC Scientific Officer-2016
Ans. (b) When T = 1, then for output Y.
AND gate (A3) + MUX (1) + AND gate (A2) + MUX
(2) propagation delay (tpd) = 2 + 1 + 2 + 1 = 6 nano sec.
So, maximum propagation delay of the circuit is 6 nano
sec.
152. How many bits can be compared in parallel
using one 74LS85 chip?
(a) 3 (b) 2
(c) 4 (d) 8
UPPCL AE-05.11.2019
And. (c) : 74LS85 is a 4bit magnitude comparator of
two binary format input. 74LS85 can compare two 4 bit
binary data and output can be given in 3 bit parallel
form.
153. A 4-bit XS-3 parallel adder needs _____4-bit

parallel adder IC 74LS83S.
(a) 3 (b) 2
(c) 4 (d) 1
UPPCL AE-05.11.2019
Ans. (b) : A 4 bit XS-3 parallel adder needs two 4 bit
parallel adder 1C 74LS83S. the circuit diagram as
shown below.
Check by NMOS
Y = (A + B).C + D
151. The propagation delays of the XOR gate, AND

gate and multiplexer (MUX) in the circuit
shown in the figure are 4ns, 2ns and 1 ns,
respectively.
154. What is the difference between a 7400 and a

7411 IC?
(a) 7400 has four two-input AND gates; 7411 has
three-three input NAND gates
(b) 7400 has four two-input NAND gates; 7411
If all the inputs P, Q, R, S and T are applied has three-three input AND gates
simultaneously and held constant, the (c) 7400 has two four-input NAND gates; 7411
maximum propagation delay of the circuit is has three three-input AND gates
(a) 3 ns (b) 6 ns (d) 7400 has two four-input AND gates; 7411 has
(c) 5 ns (d) 7 ns three three-input NAND gates
RRB JE-01.09.2019, 3:00 PM – 5:00 PM
GATE-2021
Ans. (b) : IC − 7400 is a Quad 2 input NAND gate IC ,
Ans. (b) : Case - (I) T = 0 it consist of 4-AND gate of two input, it is a 4-Pin IC.
At T = 0, for MUX 1 → XOR gate output will IC 7411 is a 3- input AND gate IC in which 3, 3 input
propagate to next stage. NAND gate are used. it is also a14 pin IC.
For MUX 2 - AND gate 1 (A1), output will propagate 155. The IC used for making a bidirectional
which is available to MUX 2 at t = 2 nano sec. universal shift register is-
So, for Y output only, AND 1 (A1) + MUX (2) is (a) 7489 (b) 7494
necessary propagation delay = 2 + 1 = 3 nano sec. (c) 74194 (d) 7495
Case - (II) T = 1 RRB JE- 31.08.2019, 10 AM-12 PM
Ans. (c) : IC 74194 is used to make bidirectional 159. The expressiontory is given by :
universal shift register.
IC 74194 4-bit Bidirectional universal shift Register
7798 4 bit data Select/storage Resister
7494 4 bit shift Register, dual asynchronous presets
7495 4 bit shift Register, Parallel in, Parallel out
serial Input.
156. What Boolean function does the following
circuit represent?
(a) AB (b) AB
(c) A + B (d) None of these
Ans. (b) :
(a) A[F + (B + C). (D + E)]

(b) A[F + (B + C). DE]
(c) A[F + (BC + DE)]
(d) A[F (B + C) + (D + E)]
IES - 1995
Ans. (a) :
AB ; act as 2-input 'NAND gate'.

160.
B and C are paralleld switch then (B + C)

D and E are paralleld switch then (D + E)
F is paralleld to (B + C) and (D + E) then → F + (B +
C). (D + E) and this total is in series with A The given circuit operates as a:
Hence, {( B + C ).( D + E ) + F }.A (a) NAND gate (b) Flip flop
(c) NOR gate (d) Comparator
157. Which logic family circuit needs a pull up UPMRC AM - 2020
resistor?
Ans. (b) : The given circuit operates as a flip-flop.
(a) Open collector TTL
161. The specifications given for a TTL logic family
(b) ECL
gate are as follows :
(c) RTL IOH = –400 mA, IOL = 8 mA, IIH = 20 mA, and
(d) DTL IIL = –0.36 mA. Fan out is :
SAIL- 2014 (a) 10 (b) 18
Ans. (a) : Open collector TTL logic(Digital Logic (c) 20 (d) 22
Gates with open collector) outputs need to connect to an DRDO-2009
external pull-up resistor between their output pin and IOH
the dc power supply to make the logic gate perform the Ans. (c) : Fan-out (high) =
I IH
intended logic function.
IOH = 400 × 10–3 , IIH = 20 × 10–3
158. 74LSB8 represents which one?
400 × 10−3
(a) 4 × 1 multiplexer = = 20
(b) Micro controller 20 ×10−3
(c) 3 to 8 decoder I 8 ×10−3
Fan-out (low) = OL = = 22.22
(d) None I IH 0.36 ×10−3
SAIL- 2014 If fan-out (low) fan-out (high) are not same,
Ans. (c) : 74LSB8 represents 3 to 8 decoder format The fan-out is chosen as the smaller of two
only. So, fan -out of gate = 20
162. The diodes in the circuit shown are ideal. A Ans. (b) : Output voltage of weighted resistor DAC can
voltage of 0 V represents logic 0 and + 5 V be given as
represents logic 1. The logic function Z realized V = gain × resolution × decimal value of digital input
0
by the circuit for logic inputs and is
3. In an 8 bit D/A converter, the reference voltage
is 10 V. The voltage represented by 00110011
will be nearly.
(a) 2.0 V (b) 2.5 V
(c) 1.0 V (d) 4.0 V
(a) Z = X + Y (b) Z = XY
Ans. (a) : Given that, n = 8 bit ( 0110011) 2 = ( 51)10
(c) Z = X + Y (d) Z = XY
Nagaland PSC (CTSE) Diploma-2017, Paper II Vref = 10v
Ans. (b) : When only one diode or at a time two diode Resolution = v ref
are OFF output Z will give the output. 2n − 1
Hence it is a AND circuit 10
= 8 = 0.03921
Z = XY 2 −1
Output voltage V0 = Resolution × Decimal equivalent
= 0.03921 × 51
(vii) A/D and D/A Converters V0 = 2V
1. An 8-bit D/A converter has step size of 20 mV. 4. An n-bit A/D converter is required to covert an
The full-scale output and the resolution will be analog input in the range of 0 - 5 V to an
nearly. accuracy of 10 mV. The value of n should be,
(a) 8 (b) 10
(a) 5.1 V and 0.3% (b) 4.6 V and 0.4%
(c) 16 (d) 9
(c) 5.1 V and 0.4% (d) 4.6 V and 0.3%
IES-2019 Ans. (d) : Input voltage = 5V
accuracy =10mV
Ans. (c) : Resolution is defined as the smallest change
in the Analog output voltage corresponding to a change input voltage
accuracy =
of one bit in the digital output. 2n − 1
n=8 5
Step size = 20 mV 10×10–3 = n
2 −1
V0 = (2n –1) × Step size 5
V0 = (28 –1) × 20 mV 2 −1 =
n
10 × 10−3
V0 = 255 × 20 × 10–3
V0 = 5100 × 10–3 5000
2n − 1 =
(Full scale output) V0 = 5.1 V 10
n
1 2 = 501
Resolution = n × 100%
2 −1 n9
1 5. Dual-slope integration type Analog-to-Digital
%R = 8 × 100%
2 −1 converters provide
1 1. Higher speeds compared to all other types
%R = × 100% of A/D converters
255 2. Very good accuracy without putting
% R = 0.392% extreme requirement on component
% R  0.4% stability.
2. How is the output voltage of Weighted Resistor 3. Good rejection of power supply hum.
DAC calculated? 4. Poor resolution compared to all other types
(a) Vo = Decimal value of Digital Input / (gain × of A/D converters for the same number of
resolution) bits.
(b) Vo = gain × resolution × Decimal value of Which of these statements are correct?
Digital Input (a) 2 and 3 only (b) 3 and 4 only
(c) Vo = (gain + resolution) / Decimal value of (c) 4 and 1 only (d) 1, 2, 3 and 4
Digital Input APPSC POLY.LECT.14.03.2020
(d) Vo = (gain + resolution) × Decimal value of Nagaland PSC (Degree) - 2018 Paper-II
Digital Input Nagaland PSC (Degree) - 2018 Diploma Paper-II
UPPCL AE-30.03.2022 IES-2013, IES-2011, Gate-1998
Ans. (a) : Dual-slope integration type ADC converter
provides :-
• In dual slope ADC the Integrator generates two
different ramps so the conversion time is high, it has
very good accuracy without putting extreme
requirement on component stability. It is generally
used in digital voltmeters.
• Dual-slope integration type ADC have good rejection
of power supply hum.
• So, the option (a) (2 and 3) is correct only.
6. The conversion time for a 10-bit successive
approximation A/D converter, for a clock for n – bit DAC
frequency of 1 MHz is • It requires a total of 2N resistor, where n is the
(a) 1 µs (b) 5 µs number of bits.
(c) 10 µs (d) 15 µs • It requires only 2 different values of resistors R and
APPSC Poly. Lect. 15.03.2020 2R.
IES-2015, 2014 9. The number of comparators required for
Ans. (c) : The conversion time for Successive implementing an 8-bit flash analog-to-digital
approximation type ADC - converter is
(a) 8 (b) 128
 1 
= n × TCLK ∵ TCLK =  (c) 255 (d) 256
 f CLK  Mizoram PSC Jr. Grade -2018, Paper-II
1 Nagaland PSC (CTSE) Diploma-2017, Paper II
= 10 × Nagaland PSC CTSE (Degree)-2017, Paper-II
FCLK
10 Mizoram PSC AE/SDO 2012-Paper-I
=
1MHz ISRO Scientist Engg.-2008
GATE - 2003
10
= Ans. (c) : No. of comparator = 2 n
− 1
1× 106
No. of bit (n) = 8
= 10 µs
Number of comparator = 28–1 = 255
7. The output voltage is related to the following
10. The fastest ADC among the following is
equation:
(a) Successive approximation type
VA = k  2 N-1 b N-1 + 2N-2 B N-2 + 2....2b1 + b 0  (b) Dual slope type
(Where k is a proportionality factor and bn are (c) Sigma-Delta ADC
bits). This is an example of: (d) Flash converter
(a) Encoder (b) ADC
(c) Decoder (d) DAC
UPMRC AM - 2020
Ans. (d) : The digital output can be represented in IES - 2015
binary equivalent as given equation - ISRO Scientist Engg.-2008
VA = K (2n–1 bn–1 + 2n–2 bn–2 +………2b1+b0)
Ans. (d) : • The fastest ADC among the following is
Where - flash converter.
K → proportionality factor
Type of ADC Conversion time
It is a constant value of DAC
Flash 1. TCLK
successive approximation type n. TCLK
Dual slope (2n + 1) TCLK
Counter type (2n – 1) TCLK
• The successive approximation A/D converter has
8. The number of resistors required for an N bit shorter conversion time compared to the counter
DAC in the case of R–2R ladder is: ramp A/D converter.
(a) N (b) 2N 11. A 10-bit A/D converter is used to digitize
(c) 3N (d) 2 analog signal in the 0 to 5 V range. What is the
UPMRC AM - 2020 approximate value of the maximum peak to
Ans. (b) : R-2R ladder resistor DAC - It as a summing peak ripple voltage that can be allowed in the
amplifier with an R-2R ladder network as shown below. d.c. supply voltage?

(a) 100 mV (b) 50 mV Ans. (a) : Given, Number of bits (n) = 10
(c) 25 mV (d) 5.0 mV Vfs = 10.23 V
(e) 20 mV V
Punjab PSC Poly. Lect. 20.08.2017 Resolution = n fs
2 −1
CGPSC SO 14.02.2016
10.23
IES-2010, 2006 = 10
2 −1
Ans. (d) : Vfs = 5 V, n = 10 bit
10.23
V =
Maximum peak to peak ripple voltage = n fs 1023
2 −1 = 10 mV
5 15. A 12-bit ADC is employed to convert an analog
= 10
2 −1 voltage of zero to 10 volts. The resolution of the
5 ADC is
= (a) 2.44 mV (b) 24.4 mV
1024 − 1
= 0.0048V (c) 83.3 mV (d) 1.2 V
= 4.8 ×10–3 Nagaland PSC (CTSE) Diploma-2017, Paper II
≃ 5 mV Nagaland PSC CTSE- 2015, Paper-II
IES-1997
12. The number of comparator in a 4-bit flash Ans. (a) : Given, Number of bits (n) = 12
ADC is Vfs = 10
(a) 4 (b) 5
Vfs
(c) 15 (d) 16 Resolution = n
Mizoram PSC IOLM-2018, Paper-II 2 −1
Nagaland PSC- 2018, Diploma Paper-II 10
= 12
GATE - 2000 2 −1
Ans. (c) : Number of comparator in 4 bit flash type 10
=
ADC is 4096 − 1
n=4 10
Comparator = 2n – 1 =
4095
= 24 – 1 = 0.00244
= 15 = 2.44 × 10–3
13. The resolution of a 4-bit counting ADC is 0.5 R = 2.44 mV
volts. For an analog input of 6.6 Volts, the 16. The number of comparator circuits required to
digital output of the ADC will be build a three-bit simultaneous A/D converter is
(a) 1011 (b) 1101 (a) 7 (b) 8
(c) 1100 (d) 1110 (c) 15 (d) 16
DFCCIL Executive (S&T) 11-11-2018, 4:30 to 6:30PM Nagaland PSC CTSE (Degree)- 2016, Paper-II
Nagaland PSC CTSC-2015 Paper-II Nagaland PSC CTSE- 2015, Paper-II
GATE - 1999 IES- 2008, 2001, GATE - 2002
Ans. (d) : Given Ans. (a) : Required comparator to build 3 bit
Resolution = 0.5 V Simultaneous A/D convertor = 2n –1
Vin = 6.6 Volts = 23 –1 [ ∵ n = 3]
V
Resolution = n in =8–1
2 −1 =7
6.6 17. A 12 bit ADC is operating with a 1 µs clock
2n − 1 = = 13.2
0.5 period and the total conversion time is seen to
2 n = 14.2 be 14 µs. The ADC must be of
Hence, (1110 )2 = (14 )10 (a) Flash type
(b) Counting type
14. A 10-bit D/A converter provides an analog (c) Integrating type
output which has a maximum value of 10.23 (d) Successive Approximation type
volts. The resolution is GPSC Asstt.Prof. -11.04.2017
(a) 10 mV (b) 20 mV IES - 2012
(c) 15 mV (d) 25 mV ISRO Scientist Engg.-2011, 2009
Mizoram PSC IOLM - 2018, Paper-II Ans. (d) : • Successive approximation type- in SAR,
Mizoram PSC Jr. Grade-2015, Paper-II ADC conversion time independent of input analog
IES-2012, 1994 voltage.
n = 12 Ans. (c) : • 1- bit magnitude comparator - A comparator
Tclk = 1µsec used to compare two bits is called a single bit
Maximum conversion time = nTclk + (EOC) + (SOC) comparator.
= 12×1µsec +1µsec +1µsec • It consists of two inputs each for two single bit
T = 14 µsec numbers and three outputs to generate less than, equal
18. 10 bit A/D converters, the quantization error is to and greater than between two binary numbers.
given by (in percent)
(a) 1 (b) 2
(c) 0.1 (d) 0.2
1
Ans. (c) : Quantization error (in percent) = n × 100 22. The output Y of a 2-bit comparator is logic 1
2
Where n is the ADC's resolution in bits. whenever the 2-bit input A is greater than the
2-bit input B. The number of combination for
 1  which the output is logic 1, is
So,  10  × 100
2  (a) 4 (b) 6
= 0.09765 Which is approximately equal to 0.1 (c) 8 (d) 10
Hence, option (c) is correct. TSGENCO AE-2015, Gate - 2012
19. One input terminal of high gain comparator Ans. (b) : Total possible combination = 22n
circuit is connected to ground and a sinusoidal A = B : 2n
voltage is applied to the other input, the output A ≠ B : 22n – 2n
of comparator will be
(a) A sinusoid 22n − 2n
A>B:
(b) A full rectified sinusoid 2
(c) A half rectified sinusoid 22n − 2n
(d) A square wave A<B:
Nagaland PSC (Degree) 2018, Paper-II 2
UPRVUNL AE-2016 22n − 2n
A > B,
Ans. (d) : • A square wave 2
22×2 − 22
=
2
= 6
23. In a D/A converter made with binary weighted
Comparator is a device which compares two analog resistors, it is difficult to maintain high accuracy
signals and produces the logical output high '1' or low as the number of bits increases, because
'0'. (a) as the resistance values of the most significant
• When we apply analog signal at comparator's positive bits becomes larger, the circuit takes long
input then it is known as non inverting and when analog time to settle
signal is applied at comparators negative terminal then (b) obtaining stable and precise resistors with a
it is known as inverting input. large spread in their values is very difficult
20. Which logic gate is a basic comparator? (c) the LSB resistance consume too much of
(a) NOR (b) NAND current and power
(c) EX-NOR (d) AND (d) the finite gain of the OP-AMP increases
APPSC POLY. LECT. 14.03.2020 inaccuracies
Ans. (c) : • An EX-NOR gate is a basic comparator, TSGENCO AE-2015
because its output is '1' (High) only if its two input bits Ans. (b) : In a digital to analog converter made with
are equal. binary weighted resister, it is difficult to maintain high
• Digital - Comparator are used in central processing accuracy as the number of bit increase because
units and microcontrollers. Example - CMOS4063, obtaining stable and precise resistor with a large spread
4585 and TTL7485, 74682. in their value is very difficult.
21. How many inputs and outputs does a 1-bit 24. Which of the following ADCs uses over
magnitude comparator have? sampling in its operation
(a) 2 inputs and 2 outputs (a) Sigma - delta ADC
(b) 3 inputs and 2 outputs (b) Counter ramp convertor
(c) 2 inputs and 3 outputs (c) Successive Approximation Register ADC
(d) 3 inputs and 3 outputs (d) Flash Convertor
APPSC POLY. LECT. 14.03.2020 ISRO Scientist Engg. 2009
Ans. (a) : • Sigma - delta ADCS uses over sampling in 1 0.5T 7A
( −1) − 1)
T ∫0
n
its operation. Cn = A.e −7 nωt dt =
2πn
Now from the given condition we have
A
0.05A <
πn
Therefore, n < 6.366
Sigma - delta has high resolution it does not require any • The maximum allowable harmonic is 6.366, but the
external components. clock source will produce only odd harmonics of
• An analog signal first undergoes the process of 250 MHz. The highest possible harmonic lesser than the
sampling before it is applied ADC for conversion into a maximum allowable 6.366 is 5
digital output. The 5th harmonic of 250 MHz is 1250 MHz. So the
25. A 5 bit DAC has a current output. For a digital board should be designed for 1250 MHz.
input of 10100, an output current of 10 mA is 27. Following waveform shows output of a 4 bit
produced. What will be the output current for DAC with 5V reference voltage. The 4 bit
a digital input of 11101? digital input of DAC is connected to 4 bit up
(a) 14.5 mA counter, the one bit input of DAC Is stuck at
(b) = 10 mA ‘0’, which is this bit?
(c) = 100 mA
(d) Not possible to calculate
Ans. (a) : Digital input = (10100)2 = (20)10
output current = 10mA
Analog output = K × digital input
10 mA = K ×20
1 (a) Bit – 0 (LSB)
K= (b) Bit - 1
2
again, (c) Bit - 2
Digital input = (11101)2 = (29)10 (d) Bit – 3 (MSB)
then current output = K × digital input ISRO Scientist Engg.-2014
1 V 5
= × 29 Ans. (c) : Step size = Rn = = 0.3125
2 2 16
I = 14.5mA 2.5V will be =
2.5
=8
26. A digital board has a unipolar square clock of 0.3125
250 MHz. If the clock on the board at all places 3.4375
3.437 will be = = 11
should have all the harmonic components 0.3125
which have more than 10% of DC value, the Step No. Q3 Q2 Q1 Q0
board has to be designed for at least - 0 0 0 0 0
(a) 250 MHz (b) 750 MHz 1 0 0 0 1
(c) 1250 MHz (d) 2500 MHz 2 0 0 1 0
ISRO Scientist Engg.-2014 3 0 0 1 1
Ans. (c) : 0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
Let us now compute the exponential Fourier series 8 1 0 0 0
coefficients for this periodic wave form 9 1 0 0 1
1 T 10 1 0 1 0
Cn = ∫ x(t) e− Jωt dt
T 0 11 1 0 1 1
• The average voltage 8 1 0 0 0
1 T 9 1 0 0 1
Vavg = ∫ x(t) dt 10 1 0 1 0
T 0 11 1 0 1 1
0 0 0 0 0
1 T
A dt = 0.5A {10% of this valueis 0.05A}
0.5t ∫0
Vavg = According to above table, we can see Q2 is stuck at 0.
It is not changing with respect to the input.
according to So, Bit-2 is stuck at zero.
28. Minimum number of bits required to represent 2 n − 1 = 250
maximum value of given analogue signal with
2 n = 251
0.1% accuracy is :
(a) 8 bits (b) 9 bits 2 n  256
(c) 10 bits (d) 12 bits 2 n  28
ISRO Scientist Engg.-2012 n8
Ans. (c) : Given that,
32. A 12-bit ADC has input signal range of ± 1V.
Accuracy = 0.1%
The signal to quantization noise ratio if a sine
1 wave signal with 0.25 V peak voltage is given as
=
1000 input is:
1 1 (a) 62 dB (b) 72 dB
n
= (c) 74 dB (d) 48 dB
2 1000
n  10 bit
Ans. (a) : Given that:
29. In Sigma delta ADC, high bit accuracy is Vmax = 1V, Vmin = –1V, n = 12
achieved by step size is given as:
(a) Over sampling and noise shaping V −V 2 2 1
(b) Over sampling ∆ = max n min = 12 = =
(c) Under sampling 2 2 4096 2048
(d) None of the above As input signal has a peak value of 0.25V, So only have
ISRO Scientist Engg.-2006 1024 levels so n' = 10 as signal to quantization ratio
(SQNR) = 1.8 + 6n = 1.8 + 6×10 = 61.8 dB  62 dB .
Ans. (a) : • In sigma delta ADC, high bit accuracy is
achieved by over sampling and noise shaping. 33. A 10-bit DAC has a step size of 10mV. What is
• In a sigma-delta ADC, the digital filter averages the 1- its Full scale O/P voltage and the percentage
bit data stream, improves the ADC resolution, and resolution?
removes quantization noise that is outside the band of (a) 10.24V, 0.2% (b) 10.23V, 0.5%
interest. (c) 10.23V, 0.1% (d) 10.24V, 0.1%
• It determines the signal bandwidth, settling time, and ISRO Scientist Engg.-2016
stopband rejection. Ans. (c): n = 10 bit
30. The A/D converter used in a digital voltmeter Step size = 10mV
could be (1) successive approximation type (2)
Flash converter type (3) Dual slope converter fullscale
step size =
type. The correct sequence in the increasing 2n − 1
order of their conversion times is Full scale voltage = Step size × 2n–1
(a) 1, 2, 3 (b) 2, 1, 3 = 10 × 10−3 × ( 210 − 1)
(c) 3, 2, 1 (d) 3, 1, 2
ISRO Scientist Engg.-2007 = 10 × 10 −3 × 1023
ISRO Scientist Engg.-2006 = 10.23 V
Ans. (b) : The correct sequence in the increasing order 1
of their conversion times is % Resolution = n × 100
2 −1
• Flash type conversion time =Tclk 1 100
• Successive approximation type conversion time = n = 10 × 100 = = 0.09%  0.1%
2 −1 1023
Tclk
• Dual slope conversion = 2n+1 Tclk 34. For a 10-bit digital ramp ADC using 500kHz
n+1 clock, the maximum conversion time is
Hence, Tclk < n Tclk < 2 Tclk
(a) 2048 µS (b) 2064 µS
31. The resolution of a D/A converter is
approximately 0.4% of its full-scale range. It is (c) 2046 µS (d) 2084 µS
(a) An 8-bit converter (b) A 10-bit converter ISRO Scientist Engg.-2016
(c) A 12 bit converter (d) A 16 bit converter Ans. (c): n = 10 bit, f = 500 kHz
ISRO Scientist Engg.-2006, IES-2006 1
Ans. (a) : Given, TCLK =
f
Resolution of DAC = 0.4%
1
1 TCLK = × 10−3
Resolution of D/A converter = n 500
2 −1 TCLK = 2µs
1
% Resolution = n
2 −1
×100 digital ramp ADC conversion time = ( 2n − 1) .TCLK
100 = (210–1) × 2µs
2n − 1 =
0.4 = 2046µs
35. Maximum value of signal to noise ratio of an 8- Ans. (d) : Logic '1' corresponding to '+5V'
bit ADC with an I/P range of 10 V will be Logic '0' corresponding to '0V'
(a) 50 dB (b) 43.8 dB −R f
(c) 48.9 dB (d) 49.8 dB V0 = Vi
ISRO Scientist Engg.-2016 R1
Ans.(d): n = 8 bit V V V V 
(SNR)dB = 1.8 + 6n V0 = −100 KΩ  1 + 2 + 3 + 4 
 R1 R 2 R 3 R 4 
= 1.8 +6 ×8
= 49.8 dB  5 0 5 5 
= −100 KΩ  + + + 
36. Number of comparators needed to build a 6-bit  100KΩ 200KΩ 400KΩ 800 KΩ 
simultaneous A/D converter is  1 1 1 
(a) 63 (b) 64 = −500  + + 
(c) 7 (d) 6  100 400 800 
ISRO Scientist Engg.-2007= −6.875V
Ans. (a) : Given, 39. A sample and hold amplifier is connected to an
n = 6 bit ADC. The acquisition time of the sample and
The number of comparators required for n-bit flash-type hold amplifier is 10 µsec and the conversion
ADC = 2n – 1 time of the ADC is 15 µsec. What is the highest
= 26 – 1 possible data rate?
(a) 100K samples (b) 400K samples
= 64 – 1
(c) 40K samples (d) 66K samples
= 63
37. A sample-and-hold (S/H) circuit, having a
Ans. (c) : Total time = acquisition time + conversion
holding capacitor of 0.1 nF, is used at the input of
an ADC (analog-to-digital converter). The time
conversion time of the ADC is 1 µsec, and during = (10 + 15)µs
this time, the capacitor should not lose more than = 25 µs
0.5% of the charge put across it during the 1
sampling time. The maximum value of the input So, Data rate =
total time
signal to the S/H circuit is 5V. The leakage
current of the S/H circuit should be less than 1
=
(a) 2.5 mA (b) 0.25 mA 25 × 10−6
(c) 25.0µA (d) 2.5 µA Data rate = 40K samples
40. An 8 bit DAC has a full scale output of 2 mA
Ans. (d) : Given that, and full scale error of ± 0.5%. If input is
Holding capacitor (C) = 0.1 nF 10000000 the range of outputs is………
Conversion time of ADC = 1 µ sec (a) 994 to 1014 µA (b) 990 to 1020 µA
Leakage current of S/H (sample-and-hold) (c) 800 to 1200 µA (d) none of the above
dv Nagaland PSC (CTSE) Diploma-2017, Paper II
IC = C
dT fullscale
Ans. (a) : Step size of DAC =
0.5% × 5 2n − 1
= 0.1× 10−9 ×
1× 10−6 2 × 10−3
= 8
5
= 0.1× 10−3 × 3 × 5 2 −1
10 = 7.8 × 10–6
= 2.5 µA = 7.8 µA
38. Determine the output voltage of a network (10000000)2=(128)10,
shown in figure if the digital input is 1011 Ideal output will be →
= 128 × 7.8 µA
= 998.4 µA  1004µA
Error will be →
= ± 0.5% × 2mA
= ± 10 µA
Range of output = (1004 ± 10) µA
= (1014 to 994) µA
41. A single channel signal acquisition system with
0-10 V range consists of a sample and-hold
(a) –3.875 V (b) –4.875 V circuit with worst case drop rate of 100 µ V/ms
(c) –5.875V (d) –6.875V and 10-bit ADC. The maximum conversion
ISRO Scientist Engg.-2007 time for the ADC is
(a) 49 µs (b) 0.49 ms (a) 10 mV (b) 12.55 mV
(c) 4.9 ms (d) 49 ms (c) 7.45 mV (d) 2.55 mV
Nagaland PSC (CTSE) Diploma-2017, Paper II ISRO Scientist Engg.-2008
full scale Ans. (b) : Given,
Ans. (d) : Step size of ADC (∆) = Full scale input voltage = 2.55 V
2N − 1
10 10 Cumulative error = 2.55 mV.
= 10 = We know that,
2 − 1 1023
= 9.77 × 10–3 V Full scale input voltage
Quantization error =
∆/2 2n − 1
Maximum conversion time = 2.55 2.55
drop rate = 8 = V
2 − 1 255
9.77 ×10−3
= Maximum error = Quantization error + cumulative error
2 × 100 × 10−6 2.55
= 48.87 msec = + 2.55mV
≈ 49 msec. 255
= 10 mV + 2.55 mV
42. For an 8-bit Digital to Analog Convertor,
reference voltage is 10 V. The full-scale output Maximum error = 12.55mV
is
46. A single channel digital storage oscilloscope
(a) 9.961 V (b) 5.550 V
uses a 10 bit, 107 samples per second ADC. For
(c) 8.500 V (d) 8.996 V a 100 kHz sine wave input, the number of
UPRVUNL AE -19.07.2021, Shift-II samples taken per cycle of the input will be
Ans. (a) : For full scale voltage (VFS) (a) 107 (b) 104
3
V (d) 102
= Rn ( 2n − 1)
(c) 10
2 GPSC Asstt. Prof. 11.04.2017
Ans. (d) : Sampling frequency = 107 sample/sec
= 8 ( 2 − 1)
10 8
2 Signal frequency = 100KHz = 105 Hz
2550 The number of samples taken during one cycle
= will be -
256
VFS = 9.961 V 107
= 5
= 102
43. Find the output voltage range of a 4-bit DAC 10
with minimum output voltage 3.5 V and 47. The voltage comparator can be used in A/D
maximum output voltage 9.5 V. conversion as a
(a) – 9.5 V (b) 9.5 V (a) 1-bit quantizer (b) 2-bit quantizer
(c) 6 V (d) 12 V (c) 4-bit quantizer (d) 8-bit quantizer
UPRVUNL AE -19.07.2021, Shift-II Mizoram PSC AE/SDO 2012-Paper-I
Ans. (c) : Vmax = 9.5V, Vmin = 3.5V
Ans. (d) : When an ADC has a comparator that first for
Output voltage range = Vmax – Vmin each decoded voltage ranges. Direct conversion is fast,
= 9.5–3.5 = 6V. typically 8 bits of resolution.
44. The 8 bit DAC produces 1.0 V for a digital
input of 00110010. What is the largest output it
can produce?
(a) 5 V (b) -5V
(c) 5.5 V (d) 5.10 V
Ans. (d) : Given,
Analog output = 1.0 V
Digital input = (00110010)2
= (50)10
1 • A voltage input (VIN) signal is applied to one input of
step size = = 20mV the comparator while a reference voltage (VREF) to
50 the other. A comparison of the two voltage levels at
n
Full scale output = (2 –1) × (step size) the comparator’s input is made to determine the
= (28–1) × 20mV comparators digital logic output state either a "1" or
= 5.1 V '0'.
45. An 8 bit ADC has a full scale input of 2.55 V. If • In general, 2n–1 comparator, would be required for
other cumulative errors are 2.55 mV, conversion of an n-bit binary output, where n is
determine the maximum error typically in the range from 8 to 16 bit.

48. The main advantage of a successive 1 1 5
approximation ADC is that = 8×  +  = 8×
(a) it is independent of its chopper frequency  2 8  8
(b) it has high series mode rejection Vout = 5V
(c) it can operate faster than other ADCs 53. What would be the percentage resolution of an
(d) its conversion time can be varied 8-bit digital to analog (D/A) converter?
Mizoram PSC AE/SDO 2012-Paper-I (a) 0.392% (b) 0.444%
Ans. (c) : • Successive approximation ADC is the (c) 0.222% (d) 0.692%
advanced version of digital ramp type ADC which is UPSC JWM-2016
designed to reduce the conversion and to increase the Ans. (a) : The percentage resolution (%R) of an n-bit
speed of operation . DAC is
• The SAR ADC will use widely data acquisition 1
techniques of sampling rates higher than 10kHz and %R = n ×100 , (n = 8)
speed is higher compared to counter type ADC. 2 −1
• So, it can operate faster than other ADCs. %R =
100
= 0.392%
49. Which of the following terms is not associated 255
with a S/H circuit? 54. Main drawbacks of the Binary weighted
(a) conversion time (b) acquisition time resistor D/A converter is
(c) aperture time (d) sample time (a) Wide range of resistor values
Mizoram PSC AE/SDO 2012-Paper-I (b) High reference voltage
Ans. (a) : • Conversion time is not associated with a (c) More no. of switches
sample and hold circuit. (d) High power requirement
• (S/H) circuit conversion time is ratio of total TNPSC AE-2013
transaction time to successful time. Ans. (a) : Main drawback of the binary weighted
50. A digital frequency converter can be converted resistor digital to analog converter is wide range of
to DVM by addition of a suitable resistor values.
(a) VCO (b) D/A converter 55. A 0-10 volt analog to digital converter requires
(c) power amplifier (d) Op-Amp to have a resolution of 0.025%. The rms value
Mizoram PSC AE/SDO 2012-Paper-I of quantization error will be
(a) 176 micro volt (b) 705 micro volt
Ans. (b) : • A digital frequency converter can be (c) 352 micro volt (d) 1410 micro volt
converted to DVM by addition of a suitable D/A
converter.
• D/A converter changes digital output to analog output. Ans. (a) : We know that
51. D/A converters are generally Vi
Number of step =
(a) Weighted resistor network Resolution
(b) Binary ladder network 1000
=
(c) Either (a) or (b) 0.025
(d) Neither (a) nor (b) = 40,000
Mizoram PSC IOLM -2018, Paper II full scale voltage
(Quantization error)rms =
Ans. (b) : • D/A converters often convert finite Number of step × 2
precision time series data to a continually varying 10
physical signal. =
• A D/A converter is a binary ladder network. 40000 × 2
52. A 4-bit D/A converter have a full scale output 1
=
voltage of 8V. The output voltage when the 5656.85
input is 1010 is - = 176 µV
(a) 160 V (b) 16 V 56. A successive approximation A/D converter has
(c) 5 V (d) 80 V a resolution of 20 mV for an analog input of
UPPCL AE-16.11.2013 2.17 V, what will be the digital output?
Ans. (c) : Given the input signal is 1010 (a) 01101100 (b) 01101101
The full scale voltage is 8V. (c) 01101011 (d) None of these
a3 = 1 a2 = 0 a1 = 1 a0 = 0 MPPSC Forest Service Exam.-2014
For 4-bit D/A output voltage is - Ans. (a) : Step size = 20 mV = 0.02 V
Input voltage = 2.17 V
a a a a 
Vout = V  n1−1 + n 2−2 + n 3−3 + n 4−4  2.17
 2 2 2 2  Number of slope = = 108.5
0.02
 1 0 1 0   (108)10
= 8 + + + 
 2 4 8 16  = (01101100)2

57. The output of a R-2R ladder for an input 1010 62. The average conversion time of an ADC using
will be an eight stage counter with a clock frequency of
(a) 6.25 (b) 5.25 2MHz is
(c) 3.125 (d) -5.25 (a) 128 µs (b) 64 µs
MPPSC Forest Service Exam.-2014 (c) 32 µs (d) 256 µs
Ans. (c) : Given, input = 1010–(4bit) Mizoram PSC IOLM-2010, Paper-II
n=4 Ans. (a) : Number of clock pulse required for n – bit
VA + 2VB + 4VC + 8VD Conversion = 2n – 1
also, Vout = Maximum conversion time = (28 – 1) TCLK
2n
= (28 – 1) × 0.5 × 10–6
8×5 + 4× 0 + 2×5 + 0
= = 127.5µsec
16 ≈ 128 µ sec.
{Let high value (1) = +5V, Low value (0) = +0V}
63. The resolution of N-bit system D/A converter is
40 + 10 50 (a) 1/2N (b) 1/ (2N–1)
= = = 3.125V N
16 16 (c) 2 –1 (d) 2N
58. Which one of the following is an element which UPPCL AE-30.03.2022
samples the continuous signal into sequence RPCS Lect.-2011
pulses appearing at regular interval of time? Ans. (b) : Resolution of DAC is change in analog
(a) D/A Converter (b) Sampler voltage corresponding to one LSB bit increment at the
(c) Coupler (d) A/D Converter input.
DFCCIL Executive S&T-17.04.2016, Shift-II V I
Ans. (b) : Sampler : Sampling is the process of Resolution = N r or N r
2 −1 2 −1
converting continuous time analog signal into a Where, N = number of binary bits
discrete-time signal by taking the "samples" at discrete-
time intervals. Vr or Ir = Reference voltage or reference current
corresponds to logic 1.
Sampling analog signals make them discrete in time but
still continuous valued. 1
Resolution = N for VR = 1 unit.
59. Sample and hold circuit is utilized in 2 −1
(a) Multiplexer (b) Analog to digital converter 64. A linear ramp ADC uses a 10 bit counting
(c) Amplifier (d) None of these register and a 15 kHz clock frequency. The
MPPSC Forest Service Exam.-2014 register output is 1111111111 when the input
voltage is 100 mV. The required ramp rate-of-
Ans. (b) : • Analog to digital converter is used to change and the ADC conversion time are
convert analog signal into digital signal. nearly
• This process is utilized using sample and hold circuit. (a) 1.5 V/s and 75 ms (b) 2.5 V/s and 90 ms
60. Among the following types of A/D converters, (c) 1.5 V/s and 90 ms (d) 2.5 V/s and 75 ms
name the one which the analog signal is IES-2020
sampled at a frequency much higher than the Ans. (a) : Given,
Nyquist rate Counting bit register (n) = 10
(a) Tracking type A/D converter clock frequency = 15 kHz
(b) Dual-slope integrating-type A/D converter Vin = 100 mV
(c) Half-flash A/D converter The resolution of an ADC will be
(d) Sigma-Delta A/D converter
V 100mV
Mizoram PSC Jr. Grade -2018, Paper-II R = n in = 10
Ans. (c) : The most common type of ADC are flash 2 −1 2 −1
successive and signal delta is the half-flash ADC. It has 100mV
R=
sample frequency much higher than Nyquist rate. 1023
61. Calculate the full-load voltage given that the The ramp rate of change = Resolution × Clock
power supply has 5% voltage regulation and an frequency
open circuit voltage of 28 V DC. 100mV
(a) 26.67 V (b) 46.15 V R= × 15kHz
1023
(c) 25 V (d) 16 V ≈ 1.46 V/s
UPRVUNL AE– 11.06.2014 ≈ 1.5 V/s
V − VF1 2n − 1
Ans. (a) : %VR = n1 ×100% ADC conversion time =
Vn Fclk
5 28 − VV.L 210 − 1 1023
= = =
100 28 f clk 15 × 103
VFL = 28 − 1.4 = 26.6 Volt = 68.2 msec.≈ 75 msec.

65. An 8-bit DAC produces Vout = 0.05 V for a 68. An ADC has a total conversion time of 200 µs.
digital input of 00000001. The full scale output What is the highest frequency that its analog
will be nearly. input should be allowed to contain?
(a) 12.8 V (b) 17.8 V (a) 2.5 kHz (b) 25 kHz
(c) 22.8 V (d) 27.8 V (c) 250 kHz (d) 0.25 kHz
IES-2020 IES-2018
Ans. (a) : Given, V0 = 0.05, bit (n) = 8 bit 1
Vfs = ? Ans. (a) : Max frequency =
2f s
Vfs 1
V0 = n (D)10 f max =
2 2 × 200 µ sec
(00000001)2 = (1)10
1
V f max =
0.05 = fs8 × (1)10 400 × 10−6
2
1000 × 103
V f max =
0.05 = fs × (1)10 400
256
fmax = 2.5 kHz
Vfs = 0.05 × 256
Vfs = 12.80 V 69. Which one of the following Analog-to-Digital
Converters (ADC) does not use a DAC?
66. The resolution of 6-bit DAC will be nearly. (a) Digital ramp ADC
(a) 4.6% (b) 3.2% (b) Successive approximation ADC
(c) 1.6% (d) 1.2% (c) Single-slope ADC
IES-2020 (d) Counting ADC
UPSC Poly.Lect.10.03. 2019 IES-2017
Ans. (c) : We know Ans. (c) : • A single slope ADC (Analog to Digital
1 converter) does not use a DAC.
%DAC Resolution is - % R = n ×100%
2 −1 • These reduce design complexity and improve
1 measurement quality, in dual slope and single slope
% R = 6 × 100% ADCs instead of using a DAC with a ramped output.
2 −1 We used op-amp circuit called integrator to generate a
1 saw tooth wave.
% R = ×100%
63 70. A 12- bit A/D converter has a full-scale analog
100 input of 5V. Its resolution is:
%R = % (a) 1.22 mV (b) 2.44 mV
63
% R = 1.58% (c) 3.66 mV (d) 4.88 mV
% R ≈ 1.6% IES-2017
67. The output voltage from a 5-bit ladder type Ans. (a) : Given, Vfs = 5 V
DAC that has a digital input of 11010, and by Number of bits (n) = 12
assuming 0 = 0V and 1= +10 V, is nearly. V
(a) 26.0 V (b) 16.3 V Resolution = n fs
2 −1
(c) 10.3 V (d) 8.1 V 5 5
IES-2019 = 12 =
2 − 1 4096 − 1
RPSC Vice Principal ITI-2016, IES-2001
5
Ans. (d) : Given, Number of bits (n) = 5 =
Output voltage 4095
= 0.00122
1
V0 = n  2n −1 × b n −1 + 2n − 2 × b n − 2 + ..... + 21 × b1 + 20 × b0  = 1.22 mV
2 71. How would a binary number 0010 be
Here n = 5 & b4 b3 b2 b1 b0 = 11010 represented by a 4-bit binary word. If the
1 range of voltage is 0 to 10V?
V0 = 5  24 × 1 + 1× 23 + 0 × 22 + 1× 21 + 0 × 20  × 10 V
2 (a) 0.666V (b) 1.333V
1 (c) 0.333 V (d) 2.000V
V0 = × [16 + 8 + 0 + 2 + 0] ×10 V IES-2016
32
1 Ans. (b) : Voltage Range = Vmax - Vmin
V0 = [ 26 × 10] V = 10 - 0
32 = 10
260 Given as n = 4 bits
V0 = V
32 V
V0 = 8.1 V Resolution = n fs
2 −1
10 10 2 It contains a comparator, a DAC and a successive
= = = approximation register.
2 − 1 15 3
4
A successive approximation A/D convertor consists
Analog Voltage = Resolution × Decimal equivalent of a comparator, a successive approximation register
2 (SAR) output latches and a D/A converters.
= × ( 0010 )2
3 The basic principle is that binary regression, in which
2 4 analog input is compared with DAC reference
= ×2 = voltage which is repeatedly divided half.
3 3 For n-bit conversion, the conversion time for different
Analog Voltage = 1.33 V ADC are:-
72. An A-to-D converter in which one sub-circuit is
a D-to-A converter is Counter type ADC : ( 2n − 1) TCLK
(a) Parallel A/D converter Successive approximation type ADC: nTCLK
(b) Dual slope A/D converter Flash type ADC : TCLK
(c) Successive approximation A/D converter Dual slope ADC : ( 2n +1 − 1) TCLK
(d) Extended parallel type A/D converter
IES-2016 The successive approximation A/D converter has a
shorter conversion time compared to the counter
Ans. (c) : • An A to D converter in successive ramp A/D converter.
approximation register type A/D converter uses D to A
converter as a sub circuit. 74. A counter type 8-bit A/D converter is driven by
a 500 kHz clock. What are the maximum
• But parallel type A/D converter and dual slope A/D counts. average conversion time and maximum
converter do not use a D/A converter of a sub circuit. conversion rate respectively?
(a) 256 counts, 200 × 10–6 sec and 1000
conversions/sec
(b) 256 counts, 256 × 10–6 sec and 1953
conversions/sec
(c) 128 counts, 256 × 10–6 sec and 1200
conversions/sec
(d) 128 counts, 200 × 10–6 sec and 1000
conversions/sec
In SAR ADC - IES-2015
1. Number of clock pulse required for n - bit conversion Ans. (b) : For a counter type
=n
Number of bits (n) = 8
2. Maximum conversion time = n × TCLK Maximum counts for counter type = 2n = 28 = 256
3. In SAR ADC, conversion time is independent of
input analog voltage. Average conversion time = ( 2n −1 ) TCLK
73. When a large number of analog signals is to be
= ( 28−1 )
1
converted to digital form, an analog
multiplexer is used. The A-to-D converter most f CLK
suitable in this case will be 1

=2 × 7
(a) Forward counter type 500 × 103
(b) Up-down counter type 1
(c) Successive approximation type = 128 × msec
500
(d) Dual slope type
1 1000
IES-2016 = 128 × × msec
500 1000
Ans. (c) : The conversion time of successive
= 128 × 2 µs = 256 µs
approximation ADC is less than forward counter type,
up-down counter, and dual-slope ADC. Maximum conversion rate = Number of conversion per
second
Successive approximation A/D converter-
f
= n
2
500 ×103
=
28
= 1953 Conversions/sec.
75. In an 8-bit D/A converter, the reference voltage
used is 10 V. What voltage is represented by
10100001?
(a) 0.00392V (b) 6.314 V
(c) 6.288V (d) 5.814V
It is capable of high speed and reliable. IES-2015

10 Vfs
Ans. (c) : V0 = (Decimal equivalent of binary) 10 = × 20
2N 2n
=
28
( 2 + 25 + 1)
10 7 Vfs 10mA
2n
=
20
............. (1)
V0 = 6.289V • Input for 11101
76. A 4-bit D/A converter gives an output voltage V
of 4.5 V for an input code of 1001. The output Ioutput = fsn × (decimal equivalent of 11101)
2
voltage for an input code of 0110 is 10 mA
(a) 1.5 V (b) 2. 0 V Ioutput = × 29
20
(c) 3.0 V (d) 4.5 V
I0 = 14.5 mA
TANGEDCO AE- 2018
IES- 2015, 1996 79. In which of the following types of A/D
Ans. (c) : Given that, converter does the conversion time almost
double for every bit added to the device?
Output voltage for 1001 = 4.5V =V01
(a) Counter type A/D converter
For a 4 bit D/A converter with VR reference voltage-
(b) Tracking type A/D converter
 b 23 + b 2 22 + b1 21 + b0 20  (c) Single-slope integrating type A/D converter
V01 = VR  3 
 24  (d) Successive approximation type A/D converter
IES-2012
For 1001-
Ans. (a) : In a counter type ADC the conversion time
 23 + 2 0  almost double for every bit added to the device.
V01 = VR  4  ………(i)
 2  Conversion time for counter type ADC
 22 + 21  T = 2 n × clock
For 0110 V02 = VR  4  ………..(ii) When we take n = 2
 2  T = 22 TCLK
Now put V01 =4.5 in equation (i) T = 4 TCLK
9 We take
4.5 = VR  
 16  n=3
T = 23 TCLK
VR = 8V T = 8 TCLK
Put VR value in equation (ii) When we increase every bit (n) the conversion time
6 double.
V02 = 8 × = 3 V02 = 3V 80. An analog voltage of 3.41 V is converted into 8-
16
bit digital form by an A/D converter with a
77. A dual slope analog to digital converter uses N- reference voltage of 5V. The digital output is
bit counter. When the input signal Va is being
(a) 1001 1001 (b) 1111 0001
integrated, the counter is allowed to count up
to the value (c) 1011 0111 (d) 1010 1110
(a) Equal to 2N – 2 IES-2012
(b) Equal to 2N – 1 Ans. (d) : Given, Vfs = 5 V
(c) Proportional to Va Number of bits (n) = 8 bits
(d) Inversely proportional to Va V 5 5
Resolution of A/D converter = fsn = 8 =
Nagaland PSC (Degree) - 2018, Pape-II 2 2 256
IES-2014 Resolution = 0.0195 V
Ans. (b) : Dual slope integrating type ADC counts up to Analog voltage × N = Resolution
the value which is equal to 2N–1. When input voltage Va (0.0195) × N = 3.41 V
is integrated the counter is allowed to count maximum 3.41
upto 2N–1, N=
0.0195
78. A 5-bit D/A converter has a current output. If = 174.87
an output current lout = 10 mA is produced for
≃ (174 )10
a digital input of 10100, the value of Iout for a
digital input of 11101 will be N = (10101110 ) 2
(a) 12.5 mA (b) 13.5 mA
81. Consider the following statements for an N-bit
(c) 15.5 mA (d) 14.5 mA DACs:
IES-2014 1. R-2R ladder type is based on dual slope
Ans. (d) : • Input for 10100 integration
Vfs 2. R- 2R requires resistors of large spread in
Output = n × (decimal equivalent of 10100)
2 values
3. R-2R requires roughly 2N resistors • According to above circuit.
4. R-2R requires roughly N Number of A - Output port
resistors. B - D/A converter
Which of these statements are correct? C - Comparator
(a) 3 only (b) 1 only D - Successive approximation register (SAR)
(c) 1 and 3 (d) 2 and 4 • So the option (c) 4 - 2 - 1 - 3 is correct.
IES-2011
83. In which one of the following types of analog to
Ans. (a) : • R-2R ladder type DAC uses voltage scaling digital converters the conversion time is
and identical resistors and requires only 2N resistors for practically independent of the amplitude of the
N bit input digital signal. analog signal ?
• R-2R ladder does not base on dual slop integration (a) The dual slope integrating type
because it is a ADC technique. (b) Successive approximation type
• R-2R ladder uses two types (P, 2R) of resistor only (c) Counter ramp type
thus it avoids large resistance spread. (d) Tracking type
Hence, statement 3 is correct. IES-2009
82. Consider the below block diagram of a Ans. (b) : Successive approximation type of analog to
successive approximation A/D converter. digital converters the conversion time is practically
Match List-I (Block) with List-II (Name) and independent of the amplitude of the analog signal,
Select the correct answer using the codes given
successive approximation type ADC depend upon
below the list. number of bits only.
List -I 84. The resolution of a DAC depends on which of
the following?
(a) The number of bits
(b) Monotonocity
(c) Reference voltage
(d) The values of resistance
IES-2009
1
Ans. (a) : Resolution of DAC = n
List -II 2 −1
1. Comparator Where n = Number of bits
2. D/A converter So the resolution of a DAC depends on the number of
3. Successive approximations register bits.
4. Output port 85. Given below are three types of converters:
Codes: 1. Successive approximation type
A B C D 2. Weighted resistor type
(a) 4 1 2 3 3. R-2R ladder type
(b) 3 1 2 4 Which of these type are D to A converters?
(c) 4 2 1 3 (a) Only 1 and 2 (b) Only 2 and 3
(d) 3 2 1 4 (c) Only 1 and 3 (d) 1, 2 and 3
IES-2010 IES-2006
Ans. (c) : Ans. (b) : Weighted resister type and R - 2R ladder type
converter is a DAC and successive approximation type
is a ADC.
So, the option (b) is correct.
86. Match List-I (Type of N-bit ADC) with List-II
(Characteristics) and select the correct answer
List-I List-II
• Standard block diagram of SAR type ADC is A. Flash 1. Integrating
Converter Type
B. Successive 2. Fastest
Approximation converter
C. Counter 3. Maximum
ramp conversion
time=N bits
D. Dual slope 4. Uses a DAC in
its feedback
path

Codes: 89. The output voltage V0 with respect to ground of
A B C D A B C D the R-2R ladder network shown in the given
(a) 1 4 3 2 (b) 1 3 4 2 figure is
(c) 2 4 3 1 (d) 2 3 4 1
IES-2012, 2009, 2004
Ans. (d) : • Flash converter is the fastest converter
among all, it is also known as parallel comparator type
ADC.
• Successive Approximation type converter has
maximum conversion time n × TCLK so the conversion
time depends only upon the number of bits.
• Counter ramp ADC has maximum conversion time
(a) 1V (b) 2V
(2n–1) TCLK.
(c) 3V (d) 4V
It uses a DAC in its feedback path.
IES-1999
• Dual slope ADC used a integrator so it is used
integration type ADC, it is slowest ADC. it is most Ans. (a) :
accurate ADC therefore mostly used in digital For n-bit R-2R ladder
voltmeter. 2n −1 Vn + .... + V2 22 + V1 21 + V0 20
87. A 10-bit ADC with full-scale output voltage of VA =
2n
10.24 V is designed to have a ±LSB/2 accuracy.
If the ADC is calibrated at 25°C and the
operating temperature ranges from 0°C to
50°C, then the maximum net temperature
coefficient of ADC should not exceed
(a) ±200µV/°C (b) ±400µV/°C
(c) ±600µV/°C (d) ±800µV/°C
IES-2003
VFS = 10.24V , n = 10 bits
V 10.24 22 × 0 + 21 × 4 + 20 × 0
Resolution = FS = 10 = 0.01 V V0 =
2n 2 23
Change in output = ± 10 mV 8
V0 =
LSB 10mV 8
Accuracy = ± = V0 = 1V
2 2
± 5 mV 90. The resolution of an-n-bit D/A converter with a
Let T be temperature coefficient maximum input of 5V is 5mV. The value of ‘n’
is
T × ( 50 − 25) = ± 5mV
(a) 8 (b) 9
5mV (c) 10 (d) 11
T=± = ± 0.2 mV/ºC
25 IES-1998
= ± 200 µV/ºC Ans. (c) : Given, Resolution = 5 mV
88. An 8-bit D/A converter has a full scale output Vfs = 5 V
voltage of 20 V. The output voltage when the n = ?
input is 11011011, is V
(a) 160 mV (b) 78 mV Resolution = n fs
(c) 20 V (d) 17 V 2 −1
IES-2001 2 − 1 =
n 5
Ans. (d) : Output voltage (V0) 5 ×10−3
= Resolution × decimal equivalent of binary number 2 − 1 = 1000
n
(11011011)2 → (219)10 2 n = 1001

V 2n ≃ 210
= n fs × ( D )10 n ≃ 10
2 −1
20 91. In a 4-bit weighted-resistor D/A converter, the
= 8 × ( 219 )10 resister value corresponding to LSB is 16 KΩ.
2 −1 The resistor value corresponding to the MSB
20 will be
= × 219
255 (a) 1KΩ (b) 2KΩ
= 0.078 × 219 = 17.082 (c) 4KΩ (d) 16KΩ
V0 ≃ 17 V IES-1997,1994
Ans. (b) : For a n-bit weighted resistor type D/A The correct sequence of the ascending order in
terms of conversion times of these ADC’S is
(a) 3, 2, 4, 1 (b) 2, 3, 4, 1
(c) 4, 1, 3, 2 (d) 3, 2, 1, 4
IES-1996
Ans. (c) : Type of ADC Conversion time
(i) Successive approximation ADC - n. TCLK
(ii) Dual Ramp ADC - 2n +1.TCLK
(iii) Counter Method ADC - (2n –1).TCLK
(iv) Simultaneous ADC - TCLK
So, increasing conversion time is 4, 1, 3, 2.
Hence, option 'c' is correct.
If weight of MSB resistor is R0 then the weight of LSB
n–1
resistor is 2 /R. 95. Flash ADC is
(a) A serial ADC
R
RMSB = n −01 (b) A parallel ADC
2 (c) Partly serial and partly parallel ADC
Given that, n = 4 R0 = 16KΩ (d) Successive approximation ADC
16 IES-1994
RMSB = 4−1
2 Ans. (b) : Flash type ADC is a parallel ADC because a
RMSB = 2 KΩ set of a comparators is in parallel so it is called as
92. A D/A converter has 5V full scale output parallel comparator type ADC.
voltage and an accuracy of +0.2%. The It is the fastest ADC among all.
maximum error for any output voltage will be
(a) 5 mV (b) 10 mV
(c) 20 mV (d) 25 mV
IES-1996
TANGEDCO - 2015
Ans. (b) : Given that, VFS = 5V , Accuracy = 0.2%
Error = (VFS × Accuracy)
0.2
Error = × 5 = 0.01
100
=10mV
93. In successive-approximation A/D converter,
offset voltage equal to 1/2 LSB is added to the
D/A converter’s output. This is done to
(a) Improve the speed of operation
(b) Reduce the maximum quantization error
All comparator are parallel so this is a parallel ADC.
(c) increase the number of bits at the output
(d) Increase the range of input voltage that can be 96. The disadvantage of a counter type A/D
converted converter as to comparator type A/D converter
is that
IES-1996
(a) The resolution is low
Ans. (b) : In successive-approximation A/D converter, (b) Longer conversion time is required
offset voltage equal to 1/2 LSB is added to the D/A (c) The circuitry is more complex
converter’s output to reduce the maximum quantization
(d) Its stability is low
error.
IES-1994
For SAR type ADC :-
• Number of clock pulse required for n-bit conversion = Ans. (b) : Conversion time of counter type is 2n times
n the clock period hence its conversion time is very long,
as comparator type ADC.
• Maximum conversion time = n × TCLK
• Due to conversion time, its is speed is less.
• It's conversion time is independent of input analog
voltage. 97. Which one of the following is a D to A
conversion technique?
94. Consider the Analog to Digital converters given (a) Successive approximation
below: (b) Weighted resistor technique
1. Successive Approximation ADC (c) Dual slope technique
2. Dual Ramp ADC (d) Single slope technique
3. Counter method ADC APGENCO AE-23.04.2017
4. Simultaneous ADC IES-1993
Ans. (b) : Weighted register and R-2R ladder technique Ans. (c) : The following circuit represents NOR gate.
is a D to A conversion technique. Inputs Output
While successive approximation, dual slope technique
A B Y=A + B
and single slope technique is a A to D converter.
0 0 1
98. For a D/A converter, the resolution required is
0 1 0
50 mV and the total maximum output voltage is
10V. The number of bits required is 1 0 0
(a) 7 (b) 8 1 1 0
(c) 9 (d) 200 When both inputs are low, the output will be high.
TANGEDCO-2015 101. Match the List-I (type of 8-bit ADC) with List-
II (Maximum conversion time in clock cycles.)
IES-1991
List-I List II
Ans. (b) : Given, R = 50 mV A. Successive approximation 1. 1
Vfs = 10 V B. Dual-slope 2. 8
Number of bits (n) = ? C. Parallel Comparator 3. 16
Vfs 4. 256
Resolution = 5. 512
2n − 1
Maximum conversion time for 8 bit ADC in
10
50 ×10−3 = n clock cycles
2 −1 Code
5 1 GATE - 1994
=
1000 2n − 1 Solution. (A-2,B-5,C-1) : Given that, n = 8
2n –1= 200 1. For successive approximation -
2n = 201 Tmax = nTclk
n = 7.65 Tmax = 8 TCLK
n = 8 bits 2. For dual-slope
Tmax = 2n+1 TCLK
99. The resolution for N bit D/A converter system = 28+1 TCLK
is = 512 TCLK
1 1 3. For parallel comparator
(a) N (b) N
2 2 –1 Tmax = TCLK
(c) 2N–1 (d) 2N 102. For an ADC, match the following if
APGENCO AE-23.04.2017 List - I
IES-1991 (A) Flash converter
(B) Dual slope converter
Ans. (b) : The resolution for n bit D/A system is
(C) Successive Approximation Converter
Vfs List - II
Resolution =
2n − 1 (1) Requires a conversion time of the order of a
Let Vfs = 1V few seconds
1 (2) requires a digital-to-analog converter
So, Resolution = (3) minimizes the effect of power supply
2 −1
n
interference.
100. The following circuit represents which logic? (4) requires a very complex hardware
(5) It is a tracking A/D converter.
GATE - 1995
Solution (A-4,B-3,C-2) : A. Flash converter requires a
very complex hardware. It is fastest ADC among all, it
is also known as parallel comparator type ADC.
B. Dual slope converter minimizes the effect of
power supply interference, it is most accurate ADC
(a) NAND (b) EX-NOR
therefore mostly used in digital voltmeter.
(c) NOR (d) INVERTER C. Successive approximation converter requires a
SAIL- 2014 digital to analog converter.
103. An 8 bit successive approximation analog to (a) 8 (b) 6
digital converter has full scale reading of 2.55 (c) 5 (d) 7
V and its conversion time for an analog input
of 1 V is 20 µs. The conversion time for a 2 V
input will be GATE - 2004
(a) 10 µs (b) 20 µs Ans. (d) : The minimum required no. of bits
(c) 40 µs (d) 50 µs 2n ≥ 100
GATE - 2000 2n ≥ 27
Ans. (b) : In successive approximate type ADC n≥7
conversion time depends upon the number of bits only.
106. A 4-bit D/A converter is connected to a free-
Hence conversion time for a 2 V input will also 20 µs.
running 3-bit UP counter, as shown in the
104. The circuit shown in the figure is a 4 bit DAC following figure. Which of the following
waveforms will be observed at V0 ?
The input bits 0 and 1 are represented by 0 and

5 V respectively. The OP AMP is ideal, but all
the resistances and the 5 V inputs have a
tolerance of ± 10%. The specification (rounded In the figure shown above, the ground has been
to the nearest multiple of 5%) for the tolerance shown by the symbol
of the DAC is
(a) ±35% (b) ±20%
(c) ±10% (d) ±5%
GATE - 2003
Ans. (a) : This DAC called weighted resister DAC -
⇒ Not considering tolerance -

1 1 1 1   8 + 4 + 2 +1  GATE - 2006
V0 = −5R  + + + = 
 R 2R 4R 8R   8  Ans. (b) : V0 ∝ output of DAC
V0 = −9.375 V D3 D 2 D1 D0
CLK Q 2 Q1 Q 0 V
⇒ Considering ± 10% tolerance - ( Q2 ) ( 0 ) ( Q1 ) ( Q0 ) 0
 1.1R 1.1R 1.1R 1.1R  0 0 0 0 0 0 0 0 0
V0 = −5.5  + + +
 0.9R 1.8R 3.6R 7.2R  1 0 0 1 0 0 0 1 1
V0 = −12.604 2 0 1 0 0 0 1 0 2
3 0 1 1 0 0 1 1 3
So, % error =
( −12.604 ) − ( −9.375 ) × 100 4 1 0 0 1 0 0 0 8
( −9.375 ) 5 1 0 1 1 0 0 1 9
−3.229 6 1 1 0 1 0 1 0 10
= × 100 = 0.344 ×100 7 1 1 1 1 0 1 1 11
−9.375
 35% So output is sudden change after decimal 3
Hence, ± 35% So option 'b' is correct.
105. A digital system is required to amplify a binary
encoded audio signal. The user should be able
to control the gain of the amplifier from a
minimum to a maximum in 100 increments.
The minimum number of bits required to
encode, in straight binary, is
107. The output of a 3-stage Johnson (twisted-ring) 108. Consider a four bit D to A converter. The
counter is fed to a digital-to-analog (D/A) analog value corresponding to a digital signals
converter as shown in the figure below. Assume of values 0000 and 0001 are 0 V and 0.0625 V
all states of the counter to be unset initially. respectively. The analog value (in Volts)
The waveform which represents the D/A corresponding to the digital signal 1111 is
converter output V0 is _____.
(a) 0.2 (b) 0.3
(c) 0.9375 (d) 1.0
GATE - 2015, Set-I
Ans. (c) : Given, n = 4 bit
Step size (Resolution) = 0.0625 V
Digital signal = (1111)2 → (15)10
Output voltage = Resolution × decimal value
= 0.0625 × 15
= 0.9375
109. In an N bit flash ADC, the analog voltage is fed
simultaneously to 2N-1 comparators. The
output of the comparators is then encoded to a
binary format using digital circuits. Assume
that the analog voltage source Vin (whose
output is being converted to digital format) has
a source resistance of 75 Ω as shown in the
circuit diagram comparator is 8 pF.
The input must settle to an accuracy of 1/2 LSB
even for a full scale input change for proper
conversion. Assume that the time taken by the
thermometer to binary encoder is negligible.
GATE - 2011
Ans. (a) : If the flash ADC has 8 bit resolution, which one
of the following alternatives is closest to the
maximum sampling rate ?
(a) 1 megasamples per second
(b) 6 megasamples per second
(c) 64 megasamples per second
(d) 256 megasamples per second
GATE - 2016, Set-II
Sequence of Johnson counter-
Ans. (a) :
Q2 Q1 Q0 D2 D1 D0 V0
0 0 0 0 0 0 0
1 0 0 1 0 0 4
1 1 0 1 1 0 6
1 1 1 1 1 1 7
0 1 1 0 1 1 3
0 0 1 0 0 1 1 Number of capacitors required for an 8-bit flash
0 0 0 0 0 0 0 converter = 28 − 1 = 255
Since, all capacitor are in parallel, then Ans. (a) : The analog level represented by the MSB 7
Ceq = 255 × C = 255 × 8pF = 2040pF = 2.04nF bit digital code = 20 × No. of levels.
= 1 × 500 mV = 500 mV
Given, Input must settle to an accuracy of 1 LSB 113. In a 8 bit counter type analog to digital
2
1 1 1 1 Vin converter which is driven by 500 kHz clock.
= × n Vin = × 8 Vin = The maximum conversion time will be:
2 2 −1 2 2 −1 510
(a) 542 µs (b) 524 µs
1 Vin
So, VC (With LSB) = Vin − (c) 512 µs (d) 484 µs
2 510
( )
−t UPSC Poly.Lect.10.03. 2019
Then, VC = Vin 1 − e τ
Ans. (c) : Given, Number of bits (n) = 8, f = 500 kHz
Maximum conversion time for counter type ADC
Q  τ = R eq C eq = 75Ω × 2.04nF = 153ns ec  = (2n–1) TCLK.
Vin −
Vin
510 (
−t
= Vin 1 − e 153ns ) = ( 28 − 1) ×
1
500 × 10 Hz
3



1
∵ TCLk = 
f
509 −t
= 1 − e 153ns = 510 µs ≃ 512 µs
510 114. The voltage resolution for n-stage ladder
−t
0.9980 = 1 − e 153ns network is given as
−t V V
−0.002 = e 153ns (a) REF n +1
(b) REF
Take ln at both side 2 2n
t V V
−6.214 = (c) REF (d) REF
153ns 2n −1 n −1
t = 950.835ns Nagaland PSC (Degree) 2018, Paper-II
1 1 Ans. (b) : The voltage resolution for n-stage ladder
∴ f= = = 1.0517 MHz V
t 950.835ns network R = REF
Hence, F ≅ 1megasample per second 2n
115. A digital-to-analog converter with a full scale
110. The number of comparators carried out in a 5 output voltage of 3.5 V has a resolution close to
bit flash type A/D converter is 14 mV. Its bit size is
(a) 31 (b) 32 (a) 4 (b) 8
(c) 5 (d) 3 (c) 16 (d) 32
Kerala PSC Lecturer (NCA) 04.07.2017 Nagaland PSC (Degree) 2018, Paper-II
Ans. (a) : Flash A/D also known as parallel A/D.
Ans. (b) : Given, Resolution (R) = 14 mV
For 5 bit flash No. of comparator = 25 – 1
Vfs = 3.5 V
= 32 – 1
Vfs
= 31 ∵ Resolution ( R ) = n
111. The resolution of 4-bit ADC is 0.5 volt, for an 2 −1
analog input of 6.6 volts, the digital output is: 3.5
2 −1 =
n
(a) 1011 (b) 1101 14 × 10−3
(c) 1100 (d) 1110 2 n = 251
Punjab PSC Poly. Lect. 20.08.2017 n ≃8
116. The resolution of Digital-to-Analog converter is
Vfs governed by which one of the following (where
Ans. (d) : Resolution =
2n – 1 n is the number of digital inputs)?
6.6 2
⇒ 0.5 = (a) 2n (b)
2n – 1 n
n
⇒ 2 – 1 = 13.2 (c) 2n (d) 2n
n
⇒ 2 = 14.2 ≃ 14 = (1 1 1 0) Nagaland PSC (Degree) 2018, Paper-II
∴ n = 4 bits Ans. (c) : The resolution
n
of Digital-to-Analog converter
112. A 500 mV level is to be converted into a 7 bit is governed by 2 .
digital code, the analog levels represented by Where 2 → is total number of digital inputs for which
n
the MSB will be: we will find the respective analog output.
(a) 250 mV (b) 300 mV 117. A 12 bit successive approximation ADC
(c) 400 mV (d) 500 mV outputs binary codes 1111 1111 1111 and 0000
0000 0000 for the analog inputs of +10.0V and
UPSC Poly.Lect.10.03. 2019 -10.0V respectively. Find its resolution
(a) 4.6 mV (b) 2.86 mV Ans. (b) : For n-bit DAC output voltage is
(c) 2.44 mV (d) 4.88 mV
–V  a n –1 a n –2 a 
TNPSC AE- 2019 V0 =  1
+ 2 + ..... + 0n  R F
R  2 2 2 
Ans. (d) Given that,
n =12, input voltage = 10–(–10) = 20V digital input is 1010 and the reference voltage is 5 volt.
V a 3 = 1, a 2 = 0, a 1 = 1, a 0 = 0
Resolution = n ref Output voltage (V0) -
2 −1
–5  1 0 1 0 
20 20 V0 = R + + +
= 12 =
2 − 1 4095 R  2 4 8 16 
Resolution = 4.88 mV 5
= –5 ×
118. How many bits are required for a DAC so that 8
its full scale output is 10mA and its resolution V0 = –3.125 Volt
is less than 40 µA. 121. For an ADC resolution is 5mV. Full scale
(a) 8 bits (b) 9 bits output is 20V, number of bit required to
(c) 10 bits (d) 11 bits represent the output is
(e) 12 bits (a) 14 (b) 25
CGPSC SO 14.02.2016 (c) 9 (d) 12
Ans. (a) : Given, Resolution or step size = 40 µA OPSC Poly. Lect. (Instrumentation)-2018, Paper-I
Ifs = 10 mA AAI-2015
I Ans. (d) : For n -bit D/A
Q R = nfs Output voltage (V0) = Resolution × decimal equivalent
2 −1 of binary input
10mA 3 V
2 −1 =
n
× 10 Resolution = n fs
40mA 2 −1
2 − 1 = 250
n Given that,
2n = 251 resolution = 5 mV
n8 Vfs = 20
−3 20
119. A 12 bit DAC has a full scale output of 15V. 5 × 10 = n
The value of Vout for an input code of 2 −1
011010010101 is 20 20
2n − 1 = = × 104
(a) 0.617 mV (b) 6.17 mV 5 ×10−3 5
(c) 0.617 V (d) 6.17 V 2n = 4000 + 1
(e) 617 mV 2n = 4001
CGPSC SO 14.02.2016
n = 12bit
Ans. (d) : Given, Number of bits (n) = 12
Vfs = 15 V 122. A voltmeter of range (0-5V) having resolution
Binary Number = 0 1 1 0 1 0 0 1 0 1 0 1 of 0.05V then the minimum no. of bit required
to design the DAC is _____
Q ( 0 11 0 1 0 0 1 0 1 0 1) 2 = (1685 )10  (a) 7 bit (b) 5 bit
Q Vout = Resolution × Decimal equivalent of binary (c) 9 bit (d) 11 bit
number BARC Scientific Officer-2016
V Ans. (a) : For n-DAC -
QR = n fs
2 −1 Vfs
15 Resolution =
= = 0.0036 2n − 1
4096 − 1 Given that,
∴ Vout = 0.0036 × 1685 Vfs = 5V
= 6.06  6.17 V resolution = 0.05 V
120. A 4-bit R/2R digital-to-analog (DAC) converter V
resolution = n fs
has a reference of 5 volts. What is the analog 2 −1
output for the input code 0101? 5
(a) 0.3125 V 2n − 1 =
(b) 3.125 V 0.05
(c) 0.78125 V 2 n − 1 = 100
(d) None of the above options 2n = 101
NIELIT Scientists- 2017 n = 7bit
123. The term digitization refers to 2 n  214
(a) conversion of analogue into digital n = 14
(b) conversion of digital into analogue 14 bit will give more than 10000 count. So option (d) is
(c) use of analogue form of electricity correct
(d) a form of changing physical quantities 128. In speech processing system, ADC is used to
RRB SSE 21.12.2014, (Yellow) digitize human voice. Voice is converted into
Ans. (a) : The term digitization refers to conversion of electrical signal by microphone which gives
analogue into digital. output in the range 0- 5 V. It is desired that
124. The number of comparator circuits required to ADC should be able to detect amplitude
build a three-bit simultaneous A/D convertor variation of atleast 0.02 V. To achieve this the
is: required resolution of ADC is :
(a) 7 (b) 8 (a) 5 bit (b) 7 bit
(c) 15 (d) 16 (c) 8 bit (d) 10 bit
RRB JE-01.09.2019, 3:00 PM – 5:00 PM MPSC HOD Govt. Poly. -2013
Nagaland PSC- 2018, Diploma Paper-II Ans. (c) : V = 5 V, Vr = 0.02
Ans. (a) : For n bit ADC 5
Resolution ≥ n
Comparator = 2n – 1 2
Given that n = 3 500
2 ≥
n
Comparator = 23 – 1 0.02
=7 2 ≥ 250
n
125. Given VOH = 4V, VIH = 3.2V, VIL = 2V, n = 8 bit

VOL = 1.5V, find noise margin?
129. An n-bit A/D converter is required to convert
(a) 0.8 (b) 2.5 analog input in range of 0-5V to an accuracy of
(c) 0.5 (d) 2 10 mV. The value of 'n' should be:
SAIL- 2014 (a) 8 (b) 10
Ans. (c) : Given that VOH = 4V (c) 16 (d) 9
VIH = 3.2 V LMRC AM (S&T)-13.05.2018
VIL = 2V Ans. (d) : We know that ,
VOL = 1.5 V Full scale voltage
NMlow = VIL – VOL = 2 – 1.5 = 0.5V Step size =
2N − 1
NMhigh = VOH – VIH = 4 – 3.2 = 0.8 Given that,
126. The number of comparators in a parallel full scale voltage = 5
conversion type 8-bit A to D converter is accuracy = step size = 10mV
(a) 8 (b) 16 Full scale voltage
(c) 255 (d) 256 step size =
TRB Poly. Lect. -2012 2n − 1
5000
Ans. (c) : For n-bit comparator 2n − 1 =
n
Number of converter = 2 –1 Q n = 8 10
number of converter = 28 – 1 2n – 1 = 500
= 255 2n = 501 ⇒ 2n  29
127. An analog voltage signal whose highest n=9
significant frequency is 1 kHz to be digitally
130. A 10 bit ADC has a range of ±5 V. The
coded with a resolution of 0.01% covering the
resolution of the ADC is approximately
voltage range of 0 to 10 V. To avoid loss of
information, the minimum number of bits in (a) 10 mV (b) 100 mV
digital code should be : (c) 0.5 V (d) 1 V
(a) 4 (b) 8 BSNL(JTO)-2002, 2001
(c) 10 (d) 14 Ans. (a) : Given that n = 10 bit
OPSC Poly. Lect. (Instrumentation)-2018, Paper-II Vfs = ±5
1 1 1 V −V
Ans. (c) : Vr = 0.01% of (10) ⇒ × × 10 = Resolution = maxn min
100 100 1000 2 −1
V 5 − ( −5 )
Vr = n = 10
2 −1 2 −1
10 = 0.0097
2n − 1 = Resolution  10 mV
1/1000
131. An increase in the value of the hold capacitor 135. What is the number of comparators required
in a sample-and-hold circuit results in : for a 3-bit flash Analog to Digital Converter?
(a) decrease in the acquisition time and decrease (a) 5 (b) 9
in the droop rate (c) 7 (d) 3
(b) decrease in the acquisition time and increase UPRVUNL AE– 11.06.2014
in the droop rate Ans. (c) : Number of comparators for 3-bit flash analog
(c) increase in the acquisition time and increase to digital converter
in the droop rate
= 2 n − 1 = 23 − 1 = 7
(d) increase in the acquisition time and decrease
in the droop rate 136. Which of the following A/D converter is used in
DRDO-2009 Digital Storage Oscilloscope (DSO)?
Ans. (d) : An increase in the value of the hold capacitor (a) Ramp type
in a sample-and-hold circuit results in increase in the (b) Successive approximation type
acquisition time and decrease in the droop rate. (c) Dual slope type
132. For an 8-bit digital-to-analog converter having (d) Parallel
reference voltage of 8 V, the least significant 4 Nagaland PSC CTSE (Degree)-2017, Paper-I
bits of the input are grounded and the most Ans. (b) : Successive approximation type used in digital
significant 4 bits are driven by 4 bit data from storage oscilloscope because of it’s high speed.
a binary counter. The maximum obtainable A successive approximation A/D convertor consists of a
peak-to-peak amplitude of a waveform at the comparator, approximation resister (SAR), output
output of the digital-to-analog converter is : latches.
(a) 4 V (b) 6 V It is capable of high speed and is reliable.
(c) 7.2 V (d) 7.5 V 137. In which of the following types of A/D
DRDO-2009 converter does the conversion time almost
Ans. (d) : Maximum peak to peak voltage amplitude- double for every bit added to the device?
23 × 2 4 4 (a) Successive approximation type A/D converter
= 8 ( 28 − 24 ) = ( 2 − 1)
8
2 28 (b) Single slope integrating type A/D converter
1 15 (c) Counter type A/D converter
= (16 − 1) = = 7.5V (d) Tracking type A/D converter
2 2 RRB JE- 31.08.2019, 10 AM-12 PM
133.
Ans. (c) : For every bit added to the device in counter
Input (bit string) Output (in Volts) type A/D converter, conversion time almost double.
000 0.0 Comparison of ADCs;-
010 2.1
ADC Conversion Time
100 4.0
110 5.9 Flash type ADC TC = 1Tclk
The input versus output characteristics of a SAR type ADC TC = n Tclk
digital-to-analog converter is given in the table
shown above: (
Counter type ADC T = 2n − 1 T
C clk )
The converter is exhibiting 138. A 10-bit D/A converter is calibrated over the
(a) offset error (b) statistical error full range from 0 to 10 V. If the input to the
(c) linearity error (d) hysteresis error D/A converter is 13A (in hex), the output
BSNL (JTO)-2006 (rounded off to three decimal places) is
Ans. (a) : As per given input versus output _______ V.
characteristics of a digital-to-analog converter is given (a) 3.069 (b) 0.3
in the table shown above, the converter is exhibiting (c) 0.5 (d) 1.0
offset error. GATE - 2020
134. An ADC normally used in a digital multi-meter
is of Ans. (a) : (13A )16 = (314)10
(a) Dual slope integration type Output voltage = Resolution × Decimal equivalent of
(b) Voltage to frequency converter type binary number
(c) Flash (or parallel) type V
(d) Successive approximation type = n ref × 314
2 −1
10 − 0
Ans. (a) : Dual slope integration type ADC normally = 10 × 314
used in digital multi-meter. 2 −1
• These are use in the precision application. 3140
=
• Dual slope ADC used in application as multi-meter, 1023
digital multi-meter. = 3.069 V
139. The reference voltage of an 8-bit linear R-2R VFS
ladder D/A converter is 8V. What is the output Ans. (b) : Vout = n × Decimal equivalent
2 −1
voltage corresponding to 10001010 Given that, n = 6, VFS = 5
(a) 4.3125 V (b) 5.0624V D = 010110 = (22)10
(c) 1.296 V (d) 0.6328 V 5
TSTRANSCO AE- 2018 Vout = 6 × ( 22 )
2 −1
Ans. (a) : We know that ( R − 2R ) ladder D/A converter Vout = 1.74V
Vref
Output voltage Vout = × (decimal equivalent of
2n (viii) Semiconductors Memories
binary input voltage)
As per question 1. In the DRAM cell in the figure, the Vt of the
Vref = 8V NMOSFET is 1 V. For the following three
combinations of WL and BL voltages.
n = 8 bits
(10001010)2 = 1× 27 + 0 + 0 + 0 + 1× 23 + 0 + 1× 2 + 0 = 138
Then,
8
Vout = × 138
28
= 4.3125V (a) 5V; 3 V; 7 V (b) 4 V; 3 V; 4 V
140. Which are the two basic operations performed (c) 5 V; 5 V; 5 V (d) 4 V; 4 V; 4 V
in ADCs ? BPSC Asst. Prof. - 12.04.2022
(a) Counting and Approximation GATE - 2001
(b) Addition and Comparison Ans. (b) :
(c) Quantization and Coding
(d) Counting and Addition
UPPCL AE-30.03.2022
Ans. (c) : Analog to digital converter (ADC) is such a
device which converts analog signals (like sound, force,
pressure etc.) into digital signal.
Analog Digital

Input
→ SAMPLE → HOLD → QUANTIZE → ENCODER 
Output
→ (i) Condition for ON state OF NMOS is
Basic operations performed in ADC are quantization VGS ≥ VT (Threshold voltage)
and coding. VG − VS ≥ VT
141. For the input analog voltage range up to 12 V, VG − VT ≥ VS
the resolution for a 12-bit A/D converter is:
Worst case condition VSmax = VG − VT
(a) 29.3 mV (b) 0.293 mV
(c) 293 mV (d) 2.93 mV (ii) If VD < VG – Vt then VS = VD
UPPCL AE-30.03.2022 (iii) If VD > VG – Vt then VS = VG – VT
Given VT =1 V
V So,
Ans. (d) : Resolution = n ref
2 −1
WL C BL
Where
VG VS VD
Vref = 12V
Check the option (b) -
n = number of bits = 12
If VD ≥ VG − Vt
12
Then, Resolution = 12 = 2.93mV
2 −1 VD ≥ 4 − 1
142. 6 bit DAC is applied input 010110. The V D=3
converted analog output is _______ V. (LOW = So, VS = VG − Vt
0V, HIGH = +5V) =4–1
(a) 3.44V (b) 1.72V =3V
(c) 0.833V (d) 0.417V VS = C = 3V
TN TRB AE-2017
UPRVUNL AE-2016 VG = WL = 4V

2. Which one of the following memories is 4. RAM and ROM chips are not available in
primarily used to store machine microcode, a variety of physical sizes.
desktop bootstrap loaders, and video game Which of the above statements are correct?
cartridges? (a) 1 and 2 only (b) 1, 3 and 4 only
(a) Mask-programmed ROM (c) 2, 3 and 4 only (d) 1,2, 3 and 4
(b) Static-RAM ESE-2021
(c) Dynamic-RAM Ans. (a) : Integrated circuit RAM chips are available in
(d) Non-Programmed ROM both static and dynamic modes. RAM is volatile and
ESE-2021 temporary storage. Data is vanished when power is cut
Ans. (a) : Mask programmed ROM used to store off. And DRAM consists of 1 Transistor and 1 capacitor
machine micro code, bootstrap loaders, and videogame and it stores the binary information in the form of
cartridges. It is also called program memory, bootstrap electric charges. SRAM a complex circuit because it is
memory, combinational circuit and function generator consists of 6 transistor.
in the case of a mask programmed ROM, the ROM is RAM and ROM chips are available in a only one size.
programmed at the manufacturers site according to the So statement 1 & 2 only correct.
specifications of the customer. 6. To realize a 512k×8 memory, how many 32k×4
A photographic negative, called a mask, is used to store memory chips are needed?
the required data on the ROM chip. (a) 64 (b) 32
A different mask would be needed for storing each (c) 16 (d) 14
different set. APPSC POLY. LECT. 14.03.2020
3. Which one of the following systems provides a Ans. (b) : memory = 512 k × 8
mechanism for translating program-generated
memory chip storage = 32 k × 4
addresses into correct main memory locations?
512 ×1024 × 8
(a) Virtual memory system no. of chips =
(b) Main memory system 32 × 1024 × 4
(c) Physical addresses system no. of chips = 32
(d) Memory space system 7. The number of cells in a 1k×4 memory is :
ESE-2021 (a) 1024 (b) 2048
Ans. (a) : Virtual memory systems provides a (c) 4096 (d) 4000
mechanism for translating program generated addresses APPSC POLY. LECT. 14.03.2020
into correct main memory location. It enables a Ans. (c) : The number of cells in a
computer to be able to compensate shortages of physical = 1 K × 4 memory is
memory by transferring pages of data from random
= 1 × 1024 × 4
access memory to disk storage. This process is done
temporarily and is designed to work as a combination of = 4096
RAM and space on the hard disk. 8. The PAL has ______and _____.
4. Addressing of a 32K × 16 memory is realized (a) AND, OR fixed
using a single decoder. The minimum number (b) AND array programmable, ORs array fixed
of AND gates required for the decoder is (c) AND/OR programmable
(a) 28 (b) 219 (d) AND array fixed, OR array progammable
(c) 2 15
(d) 232 UPMRC AM - 2020
GATE-2021 Ans. (b) : The PAL has AND array programmable, ORs
Ans. (c) : Any memory size is given by = 2K × m array fixed. PAL full form is programmable array logic.
K = address line It is a type of PLD's [Programmable logic devices].
m = data line 9. A PLA can be used:
Eq. - 1 KB memory = 210 × 8 (a) As a dynamic memory
Now ⇒ 32 K × 16 memory (b) To realise a combinational logic
(c) As a microprocessor
215 × 16
(d) To realise a sequential logic
⇒ for this memory 16 × 215 decoder required.
Nagaland PSC (Degree) - 2018, Paper-II
So number of AND gate are require = 215
5. Consider the following statements regarding TNPSC AE-2008, GATE - 1994
memory:
Ans. (b) : A programmable logic array (PLA) is a kind
1. Integrated circuit RAM chips are available of programmable logic device used to implement
in both static and dynamic modes. combinational logic circuit. The PLA has a set of
2. The dynamic RAM stores the binary programmable AND gate planes which link to a set of
information in the form of electric charges programmable OR gate planes.
that are applied to capacitors.
Programmable Programmable
3. The static RAM is easier to use and has 
Input → AND → OR 
Output →
shorter read and write cycles. Array Array

10. Which of the following statement is true for Codes:
programmable logic array (PLA)? A B C D
(a) Fixed AND array and fused programmable
(a) 4 1 3 2
OR array
(b) Fused programmable AND array and fixed (b) 3 2 4 1
OR array (c) 4 2 3 1
(c) Fused programmable AND array and fused (d) 3 1 4 2
programmable OR array TSPSC Manager (Engg.)-2015
(d) None of these
Nagaland PSC (CTSE) Diploma-2017, Paper II IES-2006
ISRO Scientist- May, 2017 Ans. (c) : PLD is a programmable logic device. It is
Ans. (c) : A programmable logic array (PLA) is a type electronic component used to build reconfigurable
of logic device than can be programmed to implement digital circuit. It is built from array and OR array.
various kind of combinational logic circuits. So this has
a number of AND and OR gate which are linked EPROM :- Erasable Programmable Read Only
together to give output. Programmable logic Array Memory combination of AND gate permanently
fused programmable AND array and fused hardware OR-gate programmable.
programmable OR array is used. Fixed Programmable
11. A typical cell, for a dynamic RAM can be PROM  input
→ AND — OR 
output
→
implemented by using how many MOS Array Array
transistors?
(a) Six (b) Five PLA - PLA stand for programmable logic array. In PLA
(c) One (d) Two both AND and OR gate programmable.
TNTRB AE– 2017
BPSC Polytechnic Lecturer-2014 
inputs
→ Programmable — Programmable  output
→
AND Array OR Array
IES-2002, GATE- 1995
Ans. (c) : In DRAM, a capacitor is used to stored bit of GAL - GAL devices are reprogrammable based on
data along with a MOSFET. DRAM will store bits of EEPROM technology. The generic design of GAL
data in what's called a storage or memory cell consisting devices is able to emulate a wide variety of PAL, EPLD
of capacitor and a transistor. and IEEL devices.
PAL - PAL combination of programmable AND array
and fixed OR array.
Programmable Fixed

input
→ AND — OR outputs
→
Array Array
So, the option (c) 4, 2, 3, 1 is correct.
13. The access time of a word in 4 MB main
memory is 100 ms. The access time of a word in
So, one MOS transistor is used. a 32 kb data cache memory is 10 ns. The
12. Match List-I (Programmable Logic Device) average data cache bit ratio is 0.95. The
with List-II (Function) and select the correct efficiency of memory access time is……..
answer using the code given below the lists: (a) 9.5 ns (b) 14.5 ns
List-I List-II (c) 20 ns (d) 95 ns
A. EPROP 1. AND- gate
programmable, OR-gate Nagaland PSC (CTSE) Diploma-2017, Paper II
permanently hardwired. Ans. (b) : Access time = bit ratio × tc + (1-bit ratio) × ta
B. PLA 2. Both AND and OR-gates = 0.95 ×10 +0.05 ×100
programmable. = 9.5 +5
C. GAL 3. AND-gate = 14.5 ns
programmable,
OUTPUT permanently 14. Semiconductor memories are
hardwired but may be (a) Volatile
taken through register, or (b) Non volatile
tri-state gate
(c) Volatile, small size
programmable.
D. PAL 4. (d) Non-volatile, small size
AND-gate permanently
hardwired OR-gate Nagaland PSC (Degree) 2018, Paper-II
programmable. Nagaland PSC CPSE -2015, Paper-II

Ans. (d) : Semiconductor Memory is a digital 18. A source with memory is known to be
electronics semiconductor device used fo digital data (a) Markov source
storage, such as memory. It is non-volatile, small size. (b) stochastic source
(c) consists of long sequence of symbols
(d) none of these
Ans. (b) : A source with memory is known to be
stochastic source.
19. A combinational PLD with both programmable
AND and OR arrays is called:
15. In a binary source, 0's occur three times as (a) PLA (b) PAL
often as 1's. What is the information contained (c) RAM (d) ROM
in the 1s?
(a) 0.415 bit (b) 0.333 bit UPPCL AE-05.11.2019
(c) 3 bit (d) 2 bit Ans. (a) : A combinational PLD with both
ISRO Scientist Engg. -2015 programmable AND and OR arrays is called PLA.
Ans. (d) : In a binary source, 0s occur three times as PROM → Programmable OR logic & fixed AND array
often as 1s. So the probability of P (0) and P (1) is given PAL → Programmable AND logic & fixed OR array
as: PLA → Programmable AND logic & programmable
P (0) = 3 P (1) .......(i) OR logic.
We know that 20. Which of the following circuit exhibits memory?
P (0) + P (1) = 1 .......(ii) (a) Astable multivibrator
From equation (i) and equation (ii) (b) Bistable multivibrator
1 (c) NAND Gate
P (1) = (d) Ex-OR Gate
4
The information contained in the 1s is given as: Nagaland PSC CTSE (Degree)-2016, Paper-II
1 Ans. (b) : Bistable multivibrator is stable in either state.
I = log 2 It can be flipped from one state to other an external
P(1) trigger pulse.
1 This circuit is also known as a flip-flop. It can store one
= log 2
1/ 4 bit of information and widely used in digital logic and
log 2 4 = 2 bits. computer memory.
21. An DRO memory can be converted into NDRO
16. Which of the following digital devices requires memory by employing
an external refresh circuit?
(a) Decade counter (b) Storage registers
(a) FLASH memory (b) E2PROM
(c) Address registers (d) Inhibit lines
(c) SRAM (d) DRAM
Ans. (b) : A DRO memory can be converted into
Ans. (d) : DRAM memory cell is made up of a NDRO memory by employing storage register.
transistor and a capacitor within an integrated circuit
and a data bit is stored in the capacitor. 22. A 32 kB RAM is formed by 16 numbers of a
Since transistor always leak a small amount, the particular type of SRAM IC. If each IC needs
capacitors will slowly discharge, causing information 14 address bits. What is the IC capacity?
stored in it to drain. (a) 32 kbits (b) 16 kbits
That is why DRAM has to be refreshed to retain data. (c) 8 kbits (d) 4 kbits
17. A computer employs RAM chips of 256 × 8 and IES-2018
ROM chips of 1024 × 8. The system needs 2K Ans. (b) : Total capacity is 32 kB
Bytes of RAM and 4KB of ROM and four 32 k × 8 bits = 256 k bits
interface units. How many ROM and RAM 14 bits address gives 16 k location
chips are needed? 256
(a) ROM = 4 chips; RAM = 8 chips Capacity of each IC =
16
(b) ROM = 8 chips; RAM = 4 chips = 16 k bits
(c) ROM = 4 chips; RAM = 4 chips
23. Consider the following statements comparing
(d) ROM = 8 chips; RAM = 8 chips static RAM with dynamic RAM:
TNPSC AE - 2018 1. In static RAM, typical cell requires more
Ans. (a) : ROM RAM number of transistors than the dynamic RAM.
4 kB 2 kB 2. Power consumptions per bit of static RAM is
4×210×8 2×210×8 less than that of dynamic RAM.
4(1024×8) 23(256×8) 3. Dynamic RAM is less expensive than the static
4 chips 8 chips RAM.
No. of chips × No. of memory location
(a) 1, 2 and 3 (b) 1 and 2 only Total capacity =
(c) 2 and 3 only (d) 1 and 3 only × No. of data line
IES-2016 Total no. of bits in memory system = 8 × 4 × 212 bits
Ans. (d): In static RAM- Six CMOS transistors, = 4 × 212 Bytes
more expensive = 4 × 4 × 210 Bytes
In dynamic RAM- one MOSFET and one capacitor, = 16 k Bytes
less expensive. Where-
24. Four memory chips of 16×4 sizes have their 210 = 1kilobyte
address buses connected together. This system
28. Among memory types, the abbreviation
will be of size
MPDRAM stands for
(a) 64 × 4 (b) 32 × 8 (a) Multi port Dynamic Random Access Memory
(c) 16 × 16 (d) 256 × 1 (b) Multipoint Dynamic Random Access Memory
IES-2015, 2001 (c) Multipoint Disk Random Access Memory
Ans. (c) : Memory size = 16 × 4 (d) Multi port Dimensional Random access
= 2A × D Memory
Size of memory is = 4×4 ×16 = 16 × 16 IES-2012
25. A semiconductor RAM has a 12-bit address Ans. (a) : MPDRAM stands for Multi port Dynamic
register and an 8-bit data register. The total Random Access Memory and also multi port DRAM. A
number of bits in the memory is dynamic RAM that contains, in addition to the
(a) 256 bits (b) 4,096 bits conventional random-access data and address port a
(c) 32,768 bits (d) 10,48,756 bits serial-access port that allows serial access to a portion
IES-2014 of the stored data in a way that is independent of the
normal RAM data terminals and in which simultaneous
Ans. (c) : A = Address register = 12 bit serial and random operation may be executed.
D = Data register is 8 bit
29. Consider the following statement of a DRAM:
Memory size = 2A × D
1. Bit is stored as a charge.
= 212× 8
2. It is made of MOS transistors.
= 212 × 23 3. Speed of DRAM is faster than processors.
= 215 4. Each memory cell requires six transistors.
= 32768 bits Which of these statements are correct.
26. Which one of the following statement is (a) 1 and 2 only (b) 2 and 3 only
correct? (c) 3 and 4 only (d) 1, 2, 3 and 4
(a) PROM contains a programmable ‘AND’ IES-2012
array and a fixed ‘OR’ array.
Ans. (a) : 1- DRAM stands for Dynamic Random
(b) PLA contains a fixed ‘AND’ array and a Access Memory in this memory bit is stored as a
programmable ‘OR’ array. charge.
(c) PROM contains as fixed ‘AND’ array and a 2- DRAM consist of/ made of one capacitor and one
programmable ‘OR’ array. MOSFET.
(d) PLA contains a programmable ‘AND’ array 3- Due to small internal circuitry, large storage
and fixed ‘OR’ array capacity is available.
IES-2013, GATE-1992 4- It's cost less compared to SRAM.
Ans. (c) : PROM is known as programmable read only 5- It has high storage density.
memory it include both AND array & OR array. 30. The difference between PLA and ROM is
PROM contains a fixed 'AND' array and a (a) PLA is sequential, ROM is combinational
programmable 'OR' array. (b) PLA is combinational ROM is sequential
PAL - contains - programmable AND array followed by (c) PLA is economizes on the number of min-
fixed OR array. term to implement Boolean functions
PLA - programmable AND array followed by (d) PLA has fixed AND array, ROM has fixes
programmable OR array. OR array
27. A memory system has a total of 8 memory IES-2011
chips, each with 12 address lines and 4 data Ans. (c) : Difference b/w PLA and ROM is PLA is
lines. The size of the memory system is economizes on the number of minterm to implement
(a) 16k bytes (b) 32k bytes boolean function.
(c) 48k bytes (d) 64k bytes ROM is made of an AND gates array and OR gates
IES-2012 array.
Ans. (a) : The size of memory = 2A × D PLA is made of programmable AND, programmable
A = Address bus = 12 OR array,
Location = 212 PLA is used for the synthesis of SOP and POS
Data line = 4 canonical forms.

31. ROM is used to store table for multiplication of Ans. (c) : Chips required to design the memory system
two 8-bit unsigned integers. The size of the Size of memory to be designed
ROM required is =
(a) 256×8 (b) 64k×8 given memory size (capacity)
(c) 4k×16 (d) 64k×16 32 kilobytes
=
IES-2010 212 × 4
Ans. (d) : When we multiply two 8-bit number can go 32 × 210 × 8
up to 16-bit. =
212 × 4
So, we need 16 bit for each of the multiplication.
= 16
The number of result = 216 is possible
Hence, to store 216 numbers each of 16 bits. 35. A single ROM is used to design a
combinational circuit described by a truth
So, the size of ROM required. table. What is the number of address lines in
= 216 × 16 {Where 210 = 1K} the ROM?
(a) Number of input variables in the truth table.
= 210 × 26 × 16 { 26 = 64} (b) Number of output variables in the truth table.
= 64 k × 16 (c) Number of input plus output variables in the
truth-table.
32. Which one of the following has the shortest
(d) Number of lines in the truth-table.
access time?
(a) NMOS EPROMs (b) NMOS RAM IES-2006
(c) CMOS RAM (d) Bipolar static RAM Ans. (a) : The block diagram for the RAM is as given
IES- 2010 below:
Ans. (d) : Bipolar static RAM has shortest access time. 2K × n
Static RAM has access times is low near about 10 nano K inputs →  → n outputs
(address) ROM (data)
second, the access time of memory should be fast
enough to keep up with the CPU. SRAM chips built • It consists of K input line and n output line.
with the bipolar IC process became practical for high- • The K input lines is used to take the input address
speed computer application. from where we want to access the content of the
33. Match List-I with List-II and select the correct ROM.
answer using the code given below the Lists: 36. In PLAs (Programmable Logic Arrays), the
List-I List-II number of inputs equal to
(Type of Memory) (Used As) (a) Number of AND gates
A. DRAM 1. Cache Memory (b) Number of OR gates
B. SRAM 2. Main memory (c) Number of product terms
C. Parallel Access 3. BIOS memory (d) Number of Buffer inverter gates
Registers TNPSC AE - 2018
D. ROM 4. CPU registers Ans. (d) : In PLAs (Programmable logic arrays), the
Codes: number of inputs equal to number of buffer inverter
gates. A programmable logic array is a device used to
A B C D build a reconfigurable digital circuit.
(a) 1 4 2 3
(b) 3 4 2 1 37. Consider the following statements:
(c) 1 2 4 3 1. MOSFET ROMs have much larger capacities
than those of the BJT ROMs
(d) 3 2 4 1
2. BJT ROMs are faster than the MOSFET
IES-2009 ROMs.
Ans. (c) : 3. BJT RAM memories can be static or dynamic.
List-I (Type of Memory) List-II (Used As) Which of the statements given above is/are
A. DRAM 1 Cache Memory correct?
B. SRAM 2 Main memory (a) 1 only (b) 1 and 2 only
C. Parallel Access Registers 3 CPU registers (c) 2 and 3 only (d) 1, 2 and 3
D. ROM 4 BIOS memory IES-2006
Ans. (b) : MOSFET structure is inherently more
34. A memory system of size 32 kbytes is required complex than an BJT's structure MOSFET are ideal for
to be designed using memory chips which have high power applications whereas BJT are more
12 address lines and 4 data lines each. What is commonly used in low current applications MOSFET
the number of such chips required to design the occupy less space in IC, MOSFET become more
memory system? dominant in the production of large capacity IC
(a) 4 (b) 8 memories.
(c) 16 (d) 32 BJT ROM are faster than the MOSFET ROMs
IES-2008 because they lack the short of parasitic capacitance.
In BJT RAM memory- Codes:
DRAM store data in MOSFET only whereas SRAM A B C A B C
store data in BJT and MOSFET. (a) 2 1 3 (b) 1 3 2
According to above definition option (b) is correct only (c) 3 2 1 (d) 3 1 2
1 and 2 are correct and 3 is incorrect. IES-2000
38. A ROM is to be used to implement a “square” Ans. (a) : Semiconductor memory - Semiconductor
which output the square of a 4-bit number. memory is a digital electronics semiconductor device
What must be the size of the ROM? used for digital data storage, it is uses combinational
(a) 16 address lines and 16 data lines logic circuit.
(b) 4 address lines and 8 data lines Ferrite core memory - Magnetic core memory, or
(c) 8 address lines and 8 data lines ferrite core memory is an early form of Random Access
(d) 4 address lines and 16 data lines Computer memory it uses small magnetic ceramic rings
the core through which wire are threaded to store
IES-2004 information. Via the polarity of the magnetic field they
Ans. (b) : Maximum 4 bit no. is 2n – 1 contain, such memory is often just called memory.
24 – 1 = 15 This is called destructive read out.
2
its binary no. = 1111 = (15) Magnetic tape memory - In magnetic tape only one
it square = (11100001)2 side of the ribbon is used for storing data, it is thin
The square of 4 bit the maximum bit is 8. plastic ribbon to store data, it is a non-volatile memory.
In the 8 bit word size of data is 4 bits and address lines 41. Which one of the following statements is
will be 4 bits. correct?
So, the ROM size is address line is 4 and 8 data line. (a) RAM is a non-volatile memory whereas
ROM is a volatile memory
(b) RAM is a volatile memory whereas ROM is a
39. PLA stands for: non-volatile memory
(a) Partial Logic Array (c) Both RAM and ROM data is not lost when
(b) Predictable Logical Array power is switched off
(c) Parabolic Logic Array (d) Both RAM and ROM are non-volatile
(d) Programmable Logic Array memories but in RAM data is lost when
DFCCIL Executive S&T-17.04.2016, Shift-II power is switched off.
Ans. (d) : A Programmable logic array (PLA) is a kind IES-2000
of programmable logic device used to implement Ans. (b) : RAM is a volatile memory whereas ROM
combinational logic circuit. The PLA has a set of is a non-volatile memory.
programmable AND gate plane. Which link to set of RAM ROM
programmable OR gate planes, which can then be 1 Random Access 1 Read Only
conditionally complemented to produce an output. Memory Memory.
2 It is a form of 2 It is a form a
temporary memory permanent or non-
where the memory volatile memory in
content is lost if power which the contents
is switched off. are stored
permanents.
3 It is used to form the 3 It is used to form
working memory of the BIOS chip of
computer. the computer.
4 RAM is a read/write 4 ROM is a Read
memory. Only Memory.
40. Match List-I (Memory elements) with List-II List-I (Memories) List-II (Particular
(Properties) and select the correct answer using characteristic)
the codes given below the lists: A. Static PL 1. Erasable
List-I List-II memory programmable
A. Semiconductor 1. Destructive B. CCD memory 2. Ultra high speed
memory read out C. ECL memory 3. Stores large
B. Ferrite core 2. Combinational volume of date
memory logic D. GAL memory 4. Does not need
C. Magnetic tape 3. Non-volatile refreshing
memory 5. Non-volatile
Codes: 64 lines are divided in 8 group of lines. Which are fed
A B C D to 8 to 1 mux. (S0 to S7)
(a) 4 3 2 1 So from here we can say that it contains 5 to 32 decoder
(b) 4 2 3 1 and 8 to 1 mux. 32 NAND Gate are needed for decoder
(c) 5 1 2 3 8 × 9 = 72 and for 8 × 1 mux each needed 9 NAND
(d) 3 5 2 1 Gates so total number of NAND Gate = 72 + 32 = 104
IES-1997 44. Which one of the following statement is not
Ans. (a) : Static memory - Static RAM does not need true for static random access memory
refreshing in SRAM data lost when power is removed. (SRAM)?
Static memory used BJT and MOSFET. (a) Static RAM stores data in the form of charge
CCD memory - CCD stands for "Charged Coupled (b) They have low capacity, but offer high speed
Device" CCD are used in digital cameras and video (c) It does not require periodic refreshing
cameras to record stile and moving images, it stores (d) They are made up of six CMOS transistor
large volume of data. ISRO Scientist December, 2017
ECL memory - Emitter coupled logic is a high speed Ans. (a) : Static RAM does not stores data in the form
integrated circuit ECL is sometimes called current of charge. Static Random Access memory is a type of
steering logic (CSL). ECL memory has ultra high speed. RAM that holds data in a static form.
GAL - Generic array logic (GAL) memory is Erasable They have low capacity; but offer high speed and it
programmable. does not require periodic refreshing.
According to above definition option (a) is correct. They are made up of six CMOS transistor.
43. The number of NAND gates required for two 45. A dynamic RAM consists of
dimensional addressing of 256×8 bit ROM (a) 6 transistors
using 8 to 1 selectors is:
(b) 2 transistors and 2 capacitors
(a) 16 (b) 48
(c) 1 transistor and 1 capacitor
(c) 64 (d) 104
(d) 2 capacitors only
IES-1992
Nagaland PSC -2018 Diploma, Paper-II
Ans. (d) : Two dimensional addressing of (256 × 8) bit
GATE - 1994
ROM = 2048 bit in ROM from there we can say that
ROWs = 256 and Columns = 8. Ans. (c) : Dynamic RAM - Dynamic RAM consist of 1
transistor and 1 capacitor. DRAM used MOSFET, it is
While using two dimensional addressing, the memory
cells in (32 × 64) matrix. 32 horizontal lines generates slower than SRAM, its power dissipation is low DRAM
address while on other hand 64 line vertical are used as used as main memory, its require refreshing.
the memory matrix. 46. If the input X3, X2, X1, X0 to the ROM in the
Total number of bits is 32 × 64 = 2048. So there are 8 figure are 8 4 2 1 BCD numbers, then the
lines are specified as output. So there for we use 8 to 1 outputs Y3, Y2, Y1, Y0 are
line selectors. Column address gives input to each mux.
So this whole arrangement known as the dimensional
addressing.
(a) gray code numbers

(b) 2 4 2 1 BCD numbers
(c) excess-3 code numbers
GATE - 2002
Ans. (b) :
The clock to the register is shown, and the data

on the W bus at time t1 is 0110. The data on the
bus at time t2 is
(a) 1111 (b) 1011
(c) 1000 (d) 0010
GATE - 2003
At time t1 the data on the w bus is = 0110
At time t2 the data on the bus = ?
Data at t1 = 0110 = (6)10
and it data value at that address is = 1010
Now 1010 i.e. 10 is acting as address at time t2 and data
at that instant is 1000.
48. If WL is the Word Line and BL the Bit Line,
an SRAM cell is shown in
It is 8421 BCD to 2421BCD. So option (b) is correct.

47. In the circuit shown in the figure, A is parallel-
in-parallel- out 4 bit register, which loads at the
rising edge of the clock C. The input lines are
connected to a 4 bit bus, W. Its output acts as
the input to a 16 × 4 ROM whose output is
floating when the enable input E is 0. A partial
table of the contents of the ROM is as follows

Ans. (b) 1 0 0 1
(a)  (b) 
0 1  1 0 
1 0 1 1
(c)  (d) 
1 0  0 0 
GATE - 2018
B0 B1
2×2 ROM array = W0  D00 D 01 
Where, WL = Word line
W1  D10 D11 
BL = Bit line
WL and BL are used to read and write from to the cell. Now when W0 = VDD , B0 = VDD, otherwise B0 = 0
SRAM - In SRAM data is stored like FF. SRAM is And when W1 = VDD , B1 = VDD , otherwise B1 = 0
faster than DRAM. In SRAM power dissipation is more That is why B0 = W0 and B1 = W1
SRAM used as cache memory.
49. In a DRAM, B0 B1
(a) periodic refreshing not required Hence W0 1 0
(b) information is stored in a capacitor W1  0 1 
(c) information is stored in a latch 51. Memory that losses its contents when power is
(d) both read and write operations can be lost is
performed simultaneously (a) Non volatile (b) Volatile
GATE - 2017, Set-II (c) Flash memory (d) Static memory
Ans. (b) : DRAM is a Dynamic Random Access Kerala PSC Lecturer (NCA) 04.07.2017
Memory. In DRAM information is stored in a capacitor. Ans. (b) : The memory that losses its contents when
In DRAM power dissipation is low. DRAM used as a power is loss is known as volatile. A volatile memory is
a computer memory that requires power to maintain the
main memory. Its required refreshing.
stored information. RAM is volatile memory.
50. A 2 × 2 ROM array is built with the help of 52. The 2732 is a 4096 'xx' 8 EPROM. How many
diodes as shown in the circuit below. Here W0 address lines does it have?
and W1 are signals that select the word lines (a) 8 (b) 12
and B0 and B1 are signals that are output of the (c) 1600 (d) 2732
sense amps based on the stored data Kerala PSC Lecturer (NCA) 04.07.2017
corresponding to the bit lines during the read
Ans. (b) : For a 4096 × 8 EPROM the no. of address
operation. line will be = log2 4096
= log2 212
= 12
53. A computer has a 2 Mb memory. The decimal
equivalent of 2 Mb will be:
(a) 2,000 000 (b) 2,048,546
(c) 2,097,152 (d) 2,194,304
Ans. (c) : 2 Mb memory = 2 × 220
= 2,097,152
54. Each cell of a static random Access Memory
contains
B0 B1 (a) 6 MOS transistor
(b) 4 MOS transistor and 2 capacitors
W0  D00 D01  (c) 2 MOS transistor and 4 capacitors
W1  D10 D11  (d) 1 MOS transistor and 1 capacitors
Bits stored in the ROM Array Nagaland PSC (Degree) 2018, Paper-II
During the read operation, the selected word GATE - 1996
line goes high and the other word line is in a Ans. (a) :
high impedance state. As per the Static RAM Dynamic RAM
implementation shown in the circuit diagram Each cell of a SRAM Each cell of a DRAM
above, what are the bits corresponding to Dij contains 6- MOS contains 1-MOS
(where i = 0 or 1 and j = 0 or 1) stored in the transistors transistor and 1
ROM ? capacitor

It has lower access time, It has higher access Ans. (b) : TTL RAM cell is implemented multiple
so it is faster compared time, so it is slower than emitter technology. It store 1 bit of information. It is
to DRAM SRAM. nothing but a flip flop.
It is costlier than DRAM It costs less compared to 60. With the availability of 16 × 4 memory size,
SRAM how many ICs (memory chips) will be required
55. 1024 × 1 capacity RAM chips are available for for the expansion of its word size in order to
a PC system, Which requires a memory obtain 16 × 8 memory?
capacity of 1024 bytes. Find out the number of (a) 2 (b) 4
RAM chips. (c) 8 (d) 16
(a) 1 (b) 2 Nagaland PSC- 2018, Diploma Paper-II
(c) 4 (d) 8 Ans. (a) : Availability of memory m1 = 16 × 4
TNPSC AE- 2019 Required memory m2 = 16 × 8
Ans. (d) : RAM chips of capacity 1024×1 = 1024 bits m2 = 16 × 8
Required, for capacity of 1024 bytes m2 = 2 ×(16×4)
= 1024×8 bits
m 2 = 2m1
1024 × 8
No. of chips needed = =8 Hence 2 memory required
1024
61. Which parameter of read cycle timing
56. If a programmable Array Logic (PAL) has 10 characteristics defines the maximum time delay
input pins, the number of inputs to each of the between the beginning of read pulse and output
AND gates is buffers arriving at active state from Hi-z
(a) 10 (b) 5 condition?
(c) 1 (d) 20 (a) Read to output valid time
TNPSC AE- 2019 (b) Read to output active time
Ans. (d) : It consist of a set of AND gate whose I/P can (c) Access time
be programmed and whose O/P are connected to the OR (d) Output tristate from read time
gate.
Initially all the connection are fused due to which Nagaland PSC- 2018, Diploma Paper-II
output of each AND Gate is zero and hence the output Ans. (b) : Read to output active time of read cycle
is also zero. BY removing the cross we can include a timing characteristic defines the maximum time delay
literal in the logic expression. between the beginning of read pulse and output buffers
Every input have their complement input also. arriving at active state from Hi - Z condition.
So, for 10 input pin = 10×2=20 inputs of AND gate. 62. PROM stands for
57. What is the other name given for associative (a) Programmable Read Only Memory
memory? (b) Pre-fed Read Only Memory
(a) Cache memory (c) Pre-required Read Only Memory
(b) Virtual memory (d) Programmed Read Only Memory
(c) Content Addressable memory Nagaland PSC- 2018, Diploma Paper-II
(d) Auxiliary memory Ans. (a) : PROM is stands for programmable read only
TNPSC AE- 2019 memory. A programmable read only memory is a form
Ans. (c) : Associative memory is also known as content of digital memory where the setting of each bit is locked
addressable memory. It is used in speed searching by a fuse or antifuse.
applications. 63. The ROM chips are mainly used to store
58. The flash memories find application in (a) System files (b) Root directories
(a) Super computers (b) Mainframe systems (c) Boot files (d) Driver files
(c) Distributed systems (d) Portable device Nagaland PSC- 2018, Diploma Paper-II
Nagaland PSC- 2018, Diploma Paper-II Ans. (c) : The ROM chips are mainly used to store boot
Ans. (d) : The flash memory low power requirement files required for system startup.
enables them to be used in a wide range of hand held Read Only Memory (ROM) is storage data, that
device. A flash drives has been developed to provide permanently stores data in a chip built into computer.
faster operation but with lesser space. Flash memory is ROM is non-volatile memory.
used in portable device. 64. The contents of the EPROM are erased by
59. What is the bit storage capacity of TTL RAM (a) Overhanging the chip
cell? (b) Exposing the chip UV rays
(a) 0 (b) 1 (c) Exposing the chip IR rays
(c) 4 (d) 16 (d) Discharging the Chip
Nagaland PSC- 2018, Diploma Paper-II Nagaland PSC- 2018, Diploma Paper-II
Ans. (b) : To erase the content of the EPROM the chip Ans. (b) :
is exposed to the UV rays which dissipate the charge on • In a semiconductor memory chip, each bit of binary
the transistor. data is staged is a high circuit called a memory cell
EPROM is non volatile kinds of memory. consisting of one to several transistors.
EPROM stands for erasable programmable Read Only • The two major categories of semiconductor memories
Memory. he the RAM and ROM.
65. Which among the following ROMs exhibit/s the • These are the fastest memory.
necessity of eliminating the PROM from the
circuit?
(a) EPROM (b) EEPROM
(c) Both (a) and (b) (d) None of the above
Ans. (a) : EPROM exhibit the necessary of elimination
of PROM from the circuit. EPROM memory is an
erasable programmable read only memory.
66. A RAM chip has capacity of 1024 x 1 bits. 69. A variant of ______ is called flash memory.
Number of such RAM chips required to (a) Virtual memory (b) Cache memory
construct a memory of 2048 bytes are : (c) EEPROM (d) RAM
(a) Two (b) Four RRB SSE-03.09.2015, Shift-III
(c) Eight (d) Sixteen Ans. (c) : Flash memory is an electronic Non-volatile
MPSC HOD Govt. Poly. -2013 computer memory storage medium that can be
RAM to construct electrically erased and reprogrammed so we can say that
Ans. (a) : Number of chip = flash memory is technically a variant of EEPROM.
RAM capacity
2048 70. Which circuit is having both programmable
n= gates
1024
(a) ROM (b) PLA
n=2 (c) PAL (d) MUX
67. Consider the following statements regarding BEL-2015
PROM/EPROM: Ans. (b) : PLA- It consists of a set of AND gate whose
1. The erasable programmable ROM using input can be program and a set of OR gate whose input
ultra-violet erasing is known as EPROM. can also be programmed.
2. The ROM that makes use of the electrical
71. EPROM is based on:
voltage for erasing is known as electrically
(a) TTL logic (b) FAMOS
alterable ROM.
3. A PROM can be programmed many times (c) Magnetic RAM (d) Bipolar transistors
after fabrication. UPMRC AM - 2020
Which of the above statements are correct? Ans. (b) : EPROM is based on FAMOS technique.
(a) 1 and 2 only (b) 1 and 3 only EPROM technology is sometimes called floating gate
(c) 1, 2 and 3 (d) 2 and 3 only avalanche MOS (FAMOS)
ESE-2021 It can be program as many number of times as we want
Ans.(a) : EPROM can be program as many number of the data can be erase by expose to uv light.
times as we want and the data can be erase by exposes 72. Virtual memory is a _________________
to U-V light EPROM can be erase electrically rather (a) Volatile memory of unlimited capacity
than by the use of U-V rays. (b) Non-volatile memory of unlimited capacity
In PROM the data to be store is done by user with the (c) A technique to execute smaller program into
help of device is called ROM programmer larger memory
It can only the programmed once. (d) A technique to execute larger programs into
Hence, 1 and 2 only correct. smaller memory
68. Which of the following is the fastest memory RRB SSE 02.09.2015, Shift-II
cell Ans. (d) : Virtual memory is a technique to execute
(a) Core memory larger programs into smaller memory.
(b) Semiconductor memory Virtual memory is a space where large programs can
(c) Double memory store themselves in form of pages while their execution,
(d) Super conductor memory and only the required pages or portions of processes are
Nagaland PSC CTSE- 2015, Paper-II located into main memory.
05.
Advanced Electronics
1. One form of NMOS circuit logic that minimizes 4. The process of evaporating a metal in an inert
power dissipation and maximizes device atmosphere and allowing it to condense on the
density is called surface of a cold finger, which is kept at liquid
(a) pass transistor logic nitrogen temperature of 77K, is known as
(b) sequential logic circuit (a) d.c. arc method
(c) NMOS SRAM cell
(b) gas-phase condensation
(d) NMOS transmission gate
(c) sonohydrolysis
IES - 2019
(d) flame pyrolysis
Ans. (a) : One form of NMOS circuit logic that
minimizes power dissipation and maximizes device IES - 2019
density is called Pass transistor logic (PTL). The basic Ans. (b) : The process of evaporating a metal in an inert
element of pass networks is MOS transistors with atmosphere and allowing it to condense on the surface of a
signals provided to gate as variable and source as a 'pass cold finger, which is kept at liquid nitrogen temperature of
variable' and it passes logic value from input to output 77K, is known as gas-phase condensation.
when device is on and goes to high impedance state in 5. Which of the following constraints are to be
DFF stock. considered by the designer while designing an
2. When there is no clock signal applied to CMOS embedded system?
logic circuits, they are referred to as 1. Selecting the microcontroller as a controlling
(a) complex CMOS logic circuits
device.
(b) static CMOS logic circuits
(c) NMOS transmission gates 2. Selecting the language to write the software
(d) random PMOS logic circuits 3. Partitioning the tasks between hardware and
IES - 2019 software to optimize the cost
Ans. (b) : Static CMOS logic circuits has no clock Select the correct answer using the code given
signal and complementary NMOS pull-down and below:
PMOS pull-up networks to implement logic gates or (a) 1, 2 and 3
logic functions in integrated circuits. However dynamic (b) 1 and 2 only
gates use a locked PMOS pull-up. (c) 1 and 3 only
3. Consider the following processes: (d) 2 and 3 only
1 Sol-gel process IES - 2019
2. Electrodeposition Ans. (a) : In an embedded system design, the task of a
3. Plasma-enhanced vapour decomposition designer is –
4. Gas-phase condensation
5. Sputtering technique • Selecting the appropriate hardware i.e.
The above processes are related to microcontroller as a controlling device.
(a) analysis of nano-powders • Selecting the language to write the software.
(b) sintering of nano-powders • Partitioning the tasks between hardware and
(c) synthesis of nano-powders software to optimize the cost.
(d) microwave sintering of nano-powders 6. The frequency response and the main lobe
IES - 2019 width for rectangular window are
Ans. (c) : Synthesis of nano powders can be defined as
ωN ωN
powdered materials with individual particles. In sin sin
2 4π 2 and π
synthesis of nano-powders scale or materials with (a) and (b)
ω N ω N
crystalline in nanometer scale and some processes are sin
below like – 2 2
• Sol-gel process ω ωN
sin sin
• Electrodeposition 2 2π 2 and 8π
(c) and (d)
• Plasma-enhanced vapour decomposition ωN N ω N
sin sin
• Gas-phase condensation 2 2
• Sputtering technique IES - 2019
Advanced Electronics 867 YCT
Ans. (a) : For rectangular window, Ans. (a) : Mealy Machine :– A mealy machine is
ωN defined as a machine in theory of computation whose
sin
2 output values are determine by both its current state and
Frequency response →
ω current inputs.
sin
2 Moore Machine :– A Moore machine is defined as a
4π machine in theory of computation whose output values
Main lobe width → are determined only by its current state.
N
7. The two advantages of FIR filters over IIR 10. The LSI technology used in
filters are (a) RTL (b) ECL
(a) they are guaranteed to be stable and non- (c) DTL (d) NMOS
linear AAI-2015
(b) they are marginally stable and linear Ans. (d) : The MOS family that dominants the LSI
(c) they are guaranteed to be stable and may be technology is NMOS (N-type Metal-Oxide
constrained to have linear phase Semiconductor).
(d) they are marginally stable and non-linear 11. The VLSI/ULSI technique is used fabricate
IES - 2019 (a) ECL (b) MOS
Ans. (c) : The advantages of FIR filters over IIR
(c) CMOS (d) TTL
filters are -
BEL-2015
FIR IIR
Ans. (c) : The VLSI/ULSI (Very Large Scale
• Linear phase • IIR filters are non-linear
Integration/Ultra Large Scale Integration) technique is
characteristic phase characteristic.
used fabricate CMOS.
• Linear phase property • IIR filters can become
implies that the phase more difficult to 12. The Medium Scale Integration (MSI) has
is a linear function of implement and distort (a) more than 100 transistor
the frequency adjustments (because of (b) less than 100 transistor
• FIR filters are always feedback). (c) less than 10 transistor
stable i.e for a finite Which can alter the poles (d) more than 1000 transistor
input, the output is and zeros and make the UKPSC Assistant Radio Officer Screening Exam.-2011
always stable. filters unstable. Ans. (a) : The Medium Scale Integration (MSI) has
8. In EPROMs, applying a high voltage to the number of transistor per chip is around 100 to 1000.
upper gate causes electrons to jump through 13. Which of following devices are VLSI?
the thin oxide onto the floating gate through (a) Microprocessor Pentium–4
the process known as (b) SL 100 BJT
(a) mask programming (c) Waveguide
(b) one-time programming (d) Optical fibre
(c) avalanche injection or Fowler-Nordheim UKPSC Assistant Radio Officer Screening Exam.-2011
tunneling Ans. (a) : Microprocessor Pentium-4 device is under
(d) erasing VLSI.
IES - 2019
14. Which of the following parameter is improved
Ans. (c) : In EPROMs, applying a high voltage to the by introducing pipelining in digital design?
upper gate causes electrons to jump through the thin
(a) Area (Gate count)
oxide onto the floating gate through the process known
(b) Maximum clock frequency
as avalanche injection or Fowler-Nordheim.
(c) Power dissipation
9. The finite state machine in which
(d) Noise
1. the output is a function of the current state
and inputs
2. the output is a function on only the current Ans. (b) : Pipelining is a famous design technique used
state to boost-up the operation of data path in a
Which of the following machines are microprocessor. Maximum clock frequency is improved
respectively correct for these styles? by introducing this technique.
(a) Mealy machine and Moore machine 15. Assuming ideal conditions, the speed up
(b) Moore machine and Mealy machine obtained from a balanced N stage pipeline is
(c) State machine and Mealy machine (a) 2 N (b) N2
(d) State machine and State machine (c) N (d) N!
IES - 2019 ISRO Scientist Engg.-2008
Ans. (c) : Let each stage take T units of time. (a) 2 NMOS transistors (b) 2 PMOS transistors
So, N state units of time = N × T (c) 1 NMOS transistor (d) 1 PMOS transistor
N×T IES - 2018
Hence, speed up from N stage pipeline = =N Ans. (a) : Body bias is the voltage at which the body
T
The speed up factor cannot be greater than number of terminal (4th terminal of MOS) is connected. Body
stages in pipeline. Hence, the speedup will be equal to effect occurs when body (or substrate) of transistor is
N. not biased at some level as that of source.
16. Comparing the time T1 taken for a single
instruction on a pipelined CPU with time T2
taken on a non-pipelined but identical CPU we
can say that
(a) T1 = T2
(b) T1 > T2
(c) T1 < T2
(d) T1 = T2 + time taken for one instruction fetch
cycle
TNPSC AE-2014
Ans. (a) : In computer science, instruction pipelining is
a technique for implementing instruction-level
The potential difference between the source and body is
parallelism within a single processor.
present at two transistors (M2 and M3) only.
Comparing the time T1 taken for a single instruction on
a pipelined CPU with time T2 taken on a non-pipelined 19. In large radar installations, it is required to
but identical CPU we can say that T1 = T2. translate the angular position of a shaft into
digital information. This is most generally
17. Consider the following opinions regarding the
achieved by employing a code wheel. For
advantage and disadvantage of a Mealy model:
unambiguous sensing of the shaft position, one
1. Advantage: Less number of states (hence less
employs a/an
hardware)
(a) Octal code
Disadvantage: Input transients are directly
(b) BCD code
conveyed to output
2. Advantage: Output remains stable over entire (c) Binary Gray code
clock period (d) Natural binary code
Disadvantage: Input transients persist for long IES - 2018
duration at output Ans. (c) : In large radar installations, it is required to
Which of the above is/are correct? translate the angular position of a shaft into digital
(a) 1 only (b) 2 only information. This is most generally achieved by
(c) Both 1 and 2 (d) Neither 1 nor 2 employing a code wheel. For unambiguous sensing of
IES - 2018 the shaft position, one employs a Binary Gray Code.
Ans. (a) : Mealy Model-A state machine which uses Quantize data converts into digital coded form by the
only input actions. So that the output depends on the code wheel and analog data converted into digital data
state and also on inputs is called a mealy model. by A/D converter.
Advantage- Mealy model requires fewer number of 20. Consider the following statements pertaining to
states than the Moore model. So it has less number of FIR filters:
hardwares. 1. These are non-recursive and hence stable.
Disadvantage- Mealy model provide outputs 2. These have high coefficient sensitivity.
instantaneously that is instantly upon receiving input 3. These have linear phase characteristics.
but the output is not hold after which clock cycle and 4. These are realized using feedback structures.
input transients are directly conveyed to output. Which of the above statements are correct?
18. In a 3-input CMOS NAND gate, the substrate (a) 1 and 4 (b) 2 and 3
terminals of NMOS transistors are grounded (c) 1 and 3 (d) 2 and 4
(lowest potential available in the circuit) and IES - 2018
the substrate terminals of PMOS transistors
Ans. (c) : Properties of FIR filters –
are connected to VDD (maximum positive
potential available in the circuit). Which of the • These are non-recursive and hence stable.
following transistors may suffer in this circuit • These have linear phase characteristics.
from body bias effect? • FIR filter consume low power.

• FIR filter require more memory as compare to IIR. • The impulse response of the analog filter is not
• Delay is more in FIR. preserved.
• FIR filters are usually designed to be linear phase. • Bilinear transformation only preserved the
magnitude response of the analog filter.
• It has no feedback.
24. What are the conditions which are necessary
21. Which one of the following refers to the
for using a parallel port?
frequency ωk in the frequency response of an
(a) Initializing by placing appropriate bits at the
FIR filter?
control register
16π 8π (b) Calling on interrupt whenever a status flag
(a) (k + α) (b) (k + α)
M M sets at the status register
4π 2π (c) Interrupting servicing (device driver)
(c) (k + α) (d) (k + α)
M M programming
IES - 2018 Select the correct answer using the code given
Ans. (d) : The frequency response of an FIR filter, below:
2π
Frequency (ωk) = (k + α) (c) 1, 2 and 3 (d) 2 and 3 only
M IES - 2017
M –1 Ans. (c) : In computing, a parallel port is a type of
k = 0, 1, 2, ........ for M = odd
2 interface found on early computers (Personal and
M otherwise) for connecting peripherals,.
k = 0, 1, 2, ........ – 1 for M = even
2 The necessary conditions are –
1 • Initializing by placing appropriate bits at the control
α = 0 or register.
2
22. In VLSI n-MOS process, the thinox mask • Calling on interrupt whenever a status flag sets at
(a) patterns the ion implantation within the the status register.
thinox region • Interrupting servicing (device driver) programming.
(b) deposits polysilicon all over the thinox region 25. An 'Assembler' for a microprocessor is used
(c) patterns thickox regions to expose silicon for
where source, drain or gate areas are required (a) Assembly of processor in a production line
(d) grows thickox over thinox regions in gate (b) Creation of new programmers using different
areas modules
IES - 2017 (c) Translation of a program from assembly
Ans. (c) : In VLSI n-MOS process, the think mask language to machine language
patterns thickox region to expose silicon where source, (d) Translation of a higher level language in to
drain or gate area are required and masking is done with English text
the photo-resist element. It is then etched to expose the
selected areas of the polysilicon gate and drain and
source areas to make connections. Ans. (c) : An assembler is a type of computer program
that interprets software programs write in assembly
23. Consider the following statements with respect
to bilinear transformation method of digital language into machine language code and instructions
filter design: that can be executed by a computer.
1. It preserves the number of poles and thereby 26. The micro programming is a technique
the order of the filter. (a) For programming the microprocessor
2. It maintains the phase response of the analog (b) For writing small programs effectively
filter. (c) For programming the control steps of a
3. The impulse response of the analog filter is computer
not preserved. (d) For programming output/input routines
Which of the above statements are correct? Nagaland PSC CTSE- 2015, Paper-II
(a) 1, 2 and 3 (b) 1 and 2 only
(c) 1 and 3 only (d) 2 and 3 only Ans. (c) : The micro programming is a technique for
IES - 2017 programming the control steps of a computer.
Ans. (c) : In the bilinear transformation of a digital Note– The control signals associated with operations
filter, using the trapezoidal role is – are saved in special memory units inaccessible by the
• It preserves the number of poles and thereby the programmer units inaccessible by the programmer as
order of the filter. control words.

06.
Power Electronics & Drives
1. SMPS normally use Ferrite core transformers Ans. (c) : Given,
in place of Iron core because of Firing angle = 300
(a) Higher saturation flux density Power factor of a single phase thyristor-
(b) Lower core loss Controlled bridge rectifier
(c) Higher electrical conductivity 2 2
(d) Lower thermal conductivity = cos α
UPPSC ITI Principal/Asstt. Director-09.01.2022 π
Ans. (b) : SMPS (Switch Mode Power supply) normally 2 2
= × cos300
use ferrite core transformers in place of Iron core because π
of lower core loss. Ferrite have high resistivity so low 2 2 3
eddy current loss hence, lower core loss. = ×
π 2
2. Buck-Boost converter is one of the, = 0.78
(a) AC - DC converter
5. Which of the following statements about pnpn
(b) DC - AC converter/Inverter diode is FALSE?
(c) controlled Rectifier
(a) This device works as a switch and is
(d) DC – DC converter fabricated to have current ratings of several
RPSC ACF & FRO 23.02.2021 hundred volts
Ans. (d) : Buck-Boost converter is a DC to DC (b) It is the first member of thyristor family
converter. In buck-boost converter, the output voltage (c) It has three junctions identified as J1, J2 and
may be less or more than the input voltage, hence the (d) It consists of four layers of semiconductor of
name buck-boost converter. The output voltage polarity material of pnpn structure
is opposite to that of the input voltage. DFCCIL Executive S&T 29.09.2021, 12:30 to 2:30PM
3. For harmonic distortion reading of D2 = 0.1, Ans. (a) : pnpn diode is called shockley diode. The
D3 = 0.02 and D4 = 0.01, with I1 = 4A and RC = pnpn diode is the first member of the thyristor family
8Ω, calculate the total harmonic distortion but it does not work as a switch and its voltage rating is
(THD) fundamental power component (P1), also low.
and total power (P).
(a) THD = 0.1; P1 = 64 W and P = 64.64 W
(b) THD = 0.2; P1 = 32 W and P = 32.32 W
(c) THD = 0.1; P 1 = 32 W and P 32.32 W
(d) THE =0.2; P1 = 64 W and P = 64.32
Ans. (a) : % THD = ( )
D 22 + D32 + D 24 + ......... × 100
% THD = (0.1)2 + ( 0.02 ) + ( 0.01) ×100

2 2
6. When the pnpn diode is biased such that the p
= 10.24% side is more positive than the n side, the
The fundamental power calculated using the equation is junction J1 and J3 are:
2 2 (a) Forward biased (b) Reverse biased
I1 R C (4) × 8 (c) Control biased (d) Feedback biased
P1 = = = 64W
2 2 DFCCIL Executive S&T 29.09.2021, 12:30 to 2:30PM
The Total power C Ans. (a) :
2
P = (1 + THD )P1
(
= 1 + ( 0.1) 64
2
)
= 64.64 W
4. Calculate the power factor of a single-phase SCR is a four layer pnpn semiconductor device. Its
thyristor-controlled bridge rectifier if the three terminal are anodes, cathode and gate, when anode
firing angle is 30º. is made positive than cathode, then junction J1 and J3
(a) 0.686 (b) 0.866 are in forword bias and junction J2 is in reverse bias
(c) 0.78 (d) 0.9 and leakage current flows in the SCR. This time SCR
LMRC AM- 16.07.2021 forward blocking occurs in state of off state.
Power Electronics & Drives 871 YCT

7. DC choppers belong to the category of, (a) (i) Flyback converter (ii) Forward converter
(a) DC – DC converter (b) (i) Forward converter (ii) Flyback converter
(b) AC – DC converter (c) Both are forward converters
(c) Inverter (d) Both are flyback converters
(d) AC – AC converter ISRO Scientist Engg. -2020
RPSC ACF & FRO 23.02.2021 Ans. (a) : (i) In flyback converter both switch off and
Ans. (a) : A chopper is a high speed on/off on simultaneously.
semiconductor switch. Chopper is a static device that (ii) Both switch are forward converter base also both the
converts fixed D.C input voltage to a variable D.C switch operate simultaneously.
output voltage directly. 12. Which of the following is false for a thyristor?
8. Which of the following is control element in A. Thyristor is a majority-carrier device
Silicon Controlled Resistor (SCR)? B. The forward-bias portion of thyristor's i-v
(a) Gate (b) Anode characteristics has two stable operating
(c) Cathode (d) Source regions.
KVS TGT (WE)- 2016 C. The forward-bias portion of thyristor's i-v
characteristics has one stable operating
Ans. (a) : Gate is a control element in SCR. region.
The gate is used to trigger the equipment into D. The negative gate current turns off the
operation by the application of low voltage. thyristor.
9. For a type A chopper, DC source voltage is 240 (a) A, B (b) B, C, D
V. Calculate the average output voltage is the (c) A, C, D (d) B, C
duty cycle is 0.4. Take a voltage drop of 4V ISRO Scientist Engg. -2020
across the chopper when it is on. Ans. (c) : Basically the thyristor is a four layer
(a) 95.2 V (b) 90.2V semiconductor device with three p-n junctions. It is
(c) 94.4 V (d) 96 V minority carrier device.
LMRC AM- 16.07.2021 Commutation of thyristor is not possible by applying
Ans. (c) : Given value, negative gate current. In i-v characteristics of a thyristor
Source voltage, Vs = 240 the forward bias portion of thyristor consist of two
Duty cycle = 0.4 stable operating region. Which is forward blocking
Voltage drop = 4V mode and forward conduction mode. In this way
Average output voltage = ( Vs − 4 ) × 0.4 statement A, C, D are wrong.
13. Following are the applications of a Buck and
= ( 240 − 4 ) × 0.4 Boost converters respectively
= 94.4V A. Regulated DC power supplies
10. A TRIAC is similar to B. Regenerative braking of DC motors
C. DC motor speed control
(a) two parallel connected thyristors
(b) two back to back (anti-parallel) connected (a) A, B (b) B, C
thyristors (c) A, C (d) B, A
dv
(c) Thyristors with larger rating Ans. (a) : Buck converter- It is a step down converter
dt because the output voltage will be less than the input
(d) Bipolar Junction Transistor voltage.
RPSC ACF & FRO 23.02.2021 It is use in regulated dc power supply.
Ans. (b) : A TRIAC is similar to two back to back Boost converter- In this converters the output voltage
(anti-parallel) connected SCRS. A TRIAC is bipolar and is greater than the input voltage so, it is a step up
bilateral power electronic device. converter.
11. Identify the converter topologies from the It is use in regenerative braking of DC motor
figures given below: So A & B is the correct.
14. An inductor is connected in series with SCR to
protect it from
(a) Excessive high voltage
(b) Excessive high dv/dt
(c) excessive high di/dt
(d) Excessive large forward current
BSNL(JTO)-2002
IES-2006
Ans. (c) : An inductor is connected in series with SCR 19. Which semiconductor power device out of the
di following is not a current triggered device?
to protect it from excessive high . (a) Thyristor
dt
(b) GTO
(c) Triac
(d) MOSFET
Ans. (d) : A power semiconductor device is a
semiconductor device used as a switch or rectifier in
15. In order to obtain static voltage equalization in power electronics. MOSFET is a semiconductor power
series connected SCRs, connections are made device but NOT a current triggered device. In MOSFET
of the flow of current from source to drain is controlled by
(a) One resistor across the string input voltage.
(b) Resistors of different values across each SCR Hence it is a voltage controlled device.
(c) Resistors of same values across each SCR
20. The triac can be used only in
(d) One resistor in series with the string
GPSC Asstt. Prof. 11.04.2017 (a) inverter
Mizoram PSC IOLM-2010, Paper-II (b) rectifier
Ans. (c) : Equal voltage distribution is obtained by (c) chopper
connecting a suitable resistance across every SCR such (d) amplifier
that each parallel combination has the same resistance. GPSC Asstt. Prof. 11.04.2017
These type of circuit is known as equalizing circuit. Ans. (c) : A TRIAC triode for alternating current also
16. A triac is a…………..switch bidirectional triode thyristor is a three terminal
(a) Bidirectional (b) Unidirectional electronic component that conducts current in either
(c) Mechanical (d) None of the above directional when triggered. Triac can be used only in
Nagaland PSC CTSE (Diploma)-2017, Paper-I chopper.
KVS TGT(WE)-2017 21. Which of the following does not cause
Ans. (a) : A triac is conduct in both the directions. A permanent damage of an SCR?
triac is thus a bidirectional thyristor with three (a) High current
terminals. It is used extensively for the control of power (b) High rate of rise of current
in ac circuits. (c) High temperature rise
17. An SCR triggered by a current pulse through (d) High rate of rise of voltage
its gate can be turned off by GPSC Asstt. Prof. 11.04.2017
(a) giving another pulse of the same polarity to IES-2015
the gate
(b) by giving pulse so the cathode Ans. (d) : With the high rate of rise of voltage, thyristor
(c) by giving pulse to the anode becomes turn on and comes in forward conduction
(d) by reversing the polarity of anode and mode and it does not cause any damage to SCR.
cathode voltage 22. The gate current required to turn on an SCR is
RPSC Vice Principal ITI-2016 (a) Few amperes
IES-2012, 2001 (b) Few milliamperes
Ans. (d) : An silicon controlled rectifier (SCR) can (c) Almost equal to anode current
triggered by a current pulse through gate can be turned
(d) About 50% of anode current
off by reversing polarity of anode and cathode voltage.
18. The operating state that distinguishes a silicon
controlled rectifier (SCR) from a diode is Ans. (b) : SCR (Silicon Controlled Rectifier) is a four
(a) Forward conducting state layer solid state current controlling device. The gate
(b) Forward blocking state current required to turn on an SCR is few milliamperes.
(c) Reverse conducting state 23. When a thyristor is negatively biased,
(d) Reverse blocking state (a) All the three junctions are negatively biased
GPSC Asstt. Prof. 11.04.2017 (b) Outer junctions are positively biased and
Ans. (b) : In order for gate triggering to occur, the inner junction is negatively biased
thyristor should be in the forward blocking state. The (c) Outer junctions are negatively biased and
operating state that distinguishes a silicon controlled inner junction are positively biased
rectifier (SCR) from a diode is forward blocking state. (d) The junction near the anode is negatively
Because normal diodes works only in two operating biased and the one near cathode is positively
mode i.e. forward conduction mode and reverse biased
blocking mode. GPSC Asstt. Prof. 11.04.2017
Ans. (c) : When a thyristor in negatively biased outer 29. SCR can be used in
junctions are negatively biased and the inner junctions (a) oscillator (b) regulator
are positively biased. (c) amplifier (d) Light dimming
Ans. (b) : SCRs are mainly used in devices where the
control unit of high power possibly coupled with high
voltage.
Hence it is a power regulator.
30. When a UJT is turned ON, the resistance
between emitter terminal and lower base
terminal…………
(a) Remains the same (b) Is decreased
24. Which semiconductor device acts like a diode (c) Is increased (d) None of the above
and two resistors? Nagaland PSC CTSE (Diploma)-2017, Paper-I
(a) SCR (b) triac Ans. (b) : The UJT is three terminal, semiconductor
(c) diac (d) UJT device which exhibits negative resistance and switching
Mizoram PSC AE/SDO 2012-Paper-I characteristics for use as a relaxation oscillator in phase
Ans. (d) : A UJT is a three terminal semiconductor control applications.
switching device. It is like a two resistor and a diode When a UJT is turned ON, the resistance between
circuit. emitter terminal and lower base terminal is decreased.
25. Which semiconductor device behaves like two
SCRs?
(a) UJT (b) triac
(c) JFET (d) MOSFET
Ans. (b) : Triac is a power electronics device connected
like two SCR in anti parallel (back to back connection).
26. After firing an SCR, the gating pulse is
removed. Then the current in the SCR will 31. An SCR remains turned on if the anode
(a) remain same current is more than the
(b) fall to zero (a) Breakdown current (b) Trigger current
(c) rise up (c) Holding current (d) Threshold current
(d) rise a little then fall to zero Mizoram PSC IOLM -2018, Paper I
Mizoram PSC AE/SDO 2012-Paper-I Ans. (c) : If the anode current is greater than the
Ans. (a) : As the current in SCR is independent of gate holding current, SCR fails to turn off even when it is in
current, so after removing gate pulse the current will conducting mode and a reverse voltage is applied
remain same. between the anode and cathode.
Since the anode current only depends on the load 32. In order to make an SCR off, it is necessary to
connected through the thyristor. Its dependency on gate make
current is zero. (a) Anode voltage less than the breakover voltage
27. Power diode are used with (b) Gate current zero
(a) heat sinks (b) reverse bias (c) Anode current less than the hold current
(c) forward bias (d) at room temperature (d) None of these
Mizoram PSC AE/SDO 2012-Paper-I UJVNL AE-2016
Ans. (a) : A power diode is a type of diode that is IES-1999
commonly used in power electronics circuits, due to Ans. (c) : SCR could be off only if anode current less
high ratings. To control the temperature rise heat sinks than the holding current.
are used. 33. The frequency of oscillation of an UJT
28. An a.c. regulator can be designed with relaxation oscillator is
(a) two diodes (b) two tunnel diodes  1 
(a) f = R1ln  (b) f = R1 C l n [1 – n]
1 − n 
(c) two zener diodes (d) none of these
1 1
Ans. (c) : As such a simple voltage regulator circuit can (c) f = (d) f =
be designed using zener diode to maintain a constant  1  R1Cln(1 − n)
R1Cln  
DC output voltage across the load in spite of variation 1− n 
in the input voltage or changes in the load current. TNPSC AE-2013

Ans. (c) : An UJT relaxation oscillator is a type of RC 38. Which of the following thyristors can be used
oscillator where the active element is UJT for high frequency of operation?
1 (a) TRIAC
f= (b) DIAC
 1 
R1C ln   (c) SCR
1− n 
(d) GTO
Where n = Intrinsic stands off ratio
34. An SCR can be switched from a non –
Ans. (d) : GTO thyristors can be used for high
conducting state to a conducting state by
frequency of operation.
applying
i. A voltage with high dv/dt 39. The SCR would be turned OFF by voltage
ii. Voltage greater than forward break over reversal of applied anode-cathode ac supply
voltage frequency of
iii Negative gate current with positive anode (a) 10 kHz
voltage (b) 10 Hz
iv. Positive gate current with positive anode (c) 5 kHz
voltage (d) 5 Hz
Which of the following is correct? RPSC LECTURER-10.01.2016
(a) i, ii and iii are correct Ans. (c) : For inverter grade SCR typical turn off time
(b) ii, iii and iv are correct (toff) is 5 to 50 µ sec while 50 to 100 µsec for converter
(c) i, ii and iv are correct grade SCR
(d) i and iv are correct Hence, Supply frequency of 5 kHz will turn off the SCR
MPPSC Forest Service Exam.-2014 by voltage reversal
Ans. (c) : An SCR is a three terminal device. It is 1
bipolar and unidirectional. It will switch on when we because = 200µ sec .
5kHz
apply positive anode to cathode voltage with positive
40. The characteristic of UJT shown in Figure
triggering. It can also turned on by dv/dt rating.
exhibits η = 0.5, VV = 1V, IV = 10 mA, IP = 20
35. Which statement is correct for a UJT?
µA and VP = 14V. The value of R1 that will
(a) Low firing current
ensure proper turn on and turn off must be
(b) Used as a wave form generator
(c) Has a stable negative resistance characteristics
(d) All options are correct
Ans. (b) : The UJT (Unijunction transistor) is a three
terminal semiconductor device which exhibits negative
resistance and switching characteristic for use as a
relaxation oscillator in phase control application and
low firing angle. When a UJT is used for triggering an
SCR, the wave shape of the voltage obtained from the (a) 800 K Ω > R1 > 2.9 KΩ
UJT circuit is a sawtooth wave. (b) 2.9 K Ω > R1 > 800 KΩ
36. The number of terminals present in IGBT is (c) 2.9 K Ω > R1 > 2 KΩ
(a) 2 (b) 3 (d) 800 K Ω > R1 > 200 KΩ
(c) 4 (d) 5 TNPSC AE - 2018
RPSC LECTURER-10.01.2016 Ans. (a) : For proper turn ON and turn OFF of UJT
VBB − VP V − VV
Ans. (b) : An insulated-gate bipolar transistor (IGBT) is > R 1 > BB
a 3-terminal power semiconductor device primarily IP IV
used as an electronic switch. 30 − 14 30 − 1
> R1 >
37. How is the GTO turned off ? 20 µA 10 mA
(a) By using a commutation circuit
800 KΩ > R 1 > 2.9 KΩ
(b) By applying reverse gate pulse
(c) By using a latch circuit 41. A Triac has three terminals viz…………..
(d) By reverse anode current pulse (a) Drain, source, gate
RPSC LECTURER-10.01.2016 (b) Two main terminal and a gate terminal
Ans. (b) : The GTO can be turned on by a gate signal (c) Cathode, anode, gate
and can also be turned off by applying reverse gate (d) None of the above
pulse. Nagaland PSC CTSE (Diploma)-2017, Paper-I
Ans. (b) : Triac–An SCR is a unidirectional device as it Ans. (b) : An SCR combines the features of a rectifier
can conduct from anode to cathode only and not from and transistor. It consists of two diodes connected back-
cathode to anode. But TRIAC is directional. to-back with a gate connection. It is widely used as a
switching device in power control applications.
46. An SCR is a………….triggered device
(a) Voltage
(b) Current
(c) Voltage as well as current
42. A diac has…………terminals Nagaland PSC CTSE (Diploma)-2017, Paper-I
(a) Two (b) Three
(c) Four (d) None of the above Ans. (b) : SCRs are triggered only by currents going
Nagaland PSC CTSE (Diploma)-2017, Paper-I into the gate. The SCR combines the rectifying features
of diodes and the on-off control features of transistors.
Ans. (a) : DIAC is a device which has two terminal and SCRs are generally used in power switching
three layer. applications.
It is a bidirectional device which is commonly used to
trigger such as TRIAC. 47. In an SCR circuit, the angle of conduction can
be changed by……….
(a) Changing anode voltage
(b) Changing gate voltage
(c) Reverse biasing the gate
Ans. (b) : In on SCR circuit, the angle of conduction
can be changed by the variation in firing angle or
43. An SCR has three terminals viz…………. variation of conduction of SCR by delaying the
(a) Cathode, anode, gate application of gate current.
(b) Anode, cathode, grid 1. Phase sifting gate control–The phase angle of the
(c) Anode, cathode, drain gate voltage is changed with respect to the anode
(d) None of the above cathode voltage
Nagaland PSC CTSE (Diploma)-2017, Paper-I 2. Pulse triggering- In this triggering the gate drive
Ans. (a) : Thyristor is a four layer 3-junction, 3- consists of a single pulse appearing periodically or a
terminal semi-controlled p-n-p-n semiconductor sequence of high frequency pulses which is also
switching device. called as carrier frequency gating.
48. If firing angle in an SCR circuit is increased,
the output……….
(a) Remains the same (b) Is increased
(c) Is decreased (d) None of the above
44. An SCR is sometimes called………. V
(a) Triac (b) Diac Ans. (c) : Vo = m (1 + cos α )
2π
(c) Unijunction transistor (d) Thyristor
Where, α = firing angle
Nagaland PSC CTSE (Diploma)-2017, Paper-I hence, the firing angle is an SCR circuit is increased,
Ans. (d) : An SCR is sometimes called thyristor. It is the output is decreased.
four layer PNPN device. It is a rectifier with a control
element. 49. When a thyristor and transistor as a switch are
compared, true statement is
(a) Thyristor requires turn off circuit while
transistor does not.
(b) The voltage drop of thyristor is less than
transistor.
(c) Thyristor requires a continuous gate current.
(d) Transistor does not draw continuously base
current.
Ans. (a) : There is a turn off circuit (commutation
45. An SCR combines the features of……….. circuit) necessary to turn off the thyristor. But in
(a) A rectifier and resistance transistor there is no need to turn off circuit.
(b) A rectifier and transistor 50. A thyristor equivalent of a thyratron tube is a
(c) A rectifier and capacitor (a) Diac (b) Triac
(d) None of the above (c) SCR (d) BJT
Ans. (c) : A Thyristor is also called a silicon controlled 55. Once the SCR starts conducting a forward
rectifier. A thyristor equivalent of a thyratron tube is current, its gate loses control over
SCR. (a) Anode circuit voltage only
51. How many SCR are to be connected in series (b) Anode circuit current only
with 800 V rating to be used for 3 kV circuit (c) Anode circuit current and voltage
using derating factor of 15%? (d) Anode circuit current, voltage and time
(a) 3 (b) 4 Mizoram PSC IOLM-2010, Paper-II
(c) 5 (d) 6 Ans. (c) : Once SCR start conducting a forward current,
Mizoram PSC Jr. Grade -2018, Paper-I is gate loses control over anode circuit voltage and
current because once a SCR in forward conducting
Ans. (c) : mode it can be off by commutation circuit.
Total string voltage / current rating 56. In UJT, maximum value of charging resistance
String efficiency =
 individual voltage / current  is associated with
n × 
 rating of one SCR  (a) Peak point
where, n No. of SCR (b) Valley point
Derating factor = 1 – string efficiency (c) Any point between peak and valley point
string efficiency = 1 – 0.15 (d) After the valley point
= 0.85 Mizoram PSC IOLM-2010, Paper-II
3000 Ans. (a) : In an UJT, maximum value of charging
hence, 0.85 = resistance is associated with peak point. A UJT
n × 800 (unijunction transistor) is a device that is formed a
3000 single junction of p-type and n-type semiconductor
n= = 4.41 ~ 5
0.85 × 800 57. Which of the following devices does not have
52. An SCR can be brought to forward conducting negative resistance characteristics
state with gate circuit open when the applied (a) UJT (b) Tunnel diode
voltage exceeds (c) SCR (d) FET
(a) Forward breakover voltage RPCS Lect.-2011
(b) Reverse breakdown voltage Ans. (d) : FET is a device which not have negative
(c) 1.5V resistance characteristics. FET is a three terminals
(d) Peak non-repetitive off-state voltage device, source, drain and gate. It is known as a unipolar
Mizoram PSC IOLM-2010, Paper-II transistors. FET is a voltage control device.
Ans. (a) : An SCR can be brought to forward 58. The turn-off time of thyristor is 30 µ sec at
conducting state with gate circuit open when the applied 500C its turn-off time at 1000C will be
voltage exceed the forward breakdown voltage. In this (a) same (b) 15 µ sec
process once the SCR goes in conduction mode. (c) 60 µ sec (d) 100 µ sec
RPCS Lect.-2011
53. In thyristor, holding current is
Ans. (c) : As temperature increases, turn off time of
(a) More than latching current
thyristor increases but not linearly i.e. it
(b) Less than latching current increases/decreases gradually so turn of time of
(c) Equal to latching current
thyristor will be more than 30 µ sec but is not 4 times at
(d) Very small
1000C. where 60µ sec is more suitable turn off time at
Mizoram PSC IOLM-2010, Paper-II 1000C.
Ans. (b) : The holding current in SCR, is the current 59. In a thyristor, the minimum current required
which hold the conduction state of SCR. It is less than to maintain the device in the 'ON' state is called
the latching current. (a) Latching current (b) Ignition current
IL  2IH (c) Holding current (d) Avalanche current
54. Forward voltage drop during SCR turn-on is IES-2015, 2005
1.5V this drop remains Ans. (c) : Holding current- The minimum current
(a) Remains constant and is independent of load required to maintain the device in on state is called
current holding current an holding current of SCR is that
(b) Increases slightly with load current minimum value of current below which anode current
(c) Decreases slightly with load current must fall to come in OFF state.
(d) Varies linearly with load current Holding current is related to the turn off process of
Mizoram PSC IOLM-2010, Paper-II the SCR.
Ans. (b) : The forward voltage drop during SCR on Latching current is related to the turn ON process
of the SCR.
state is 1⋅5V. When current through SCR increase drop
Latching current is always more than holding
will increase, due to some internal resistance. current.
60. An SCR has an anode supply of sine voltage (a) expedite the generation of triggering pulses
200 Vr.m.s, 50 Hz applied through a 100Ω (b) delay the generation of triggering pulses
resistor and fired at an angle of 60º. Assuming (c) provide a constant voltage to UJT to prevent
no voltage drop, the r.m.s. value of the output erratic firing
voltage is nearly (d) provide a variable voltage to UJT as the
(a) 90 V (b) 126 V source voltage changes
(c) 166 V (d) 200 V IES-2014
IES-2014
Ans. (c) : The purpose of connecting a zener diode in a
UJT circuit, used for triggering thyristors, is to provide
Vrms = 200V, Vm = 200 2 a constant voltage to UJT to prevent erratic firing.
The function of zener diode is to clip the rectified
1 π 2
( )
2π ∫α
Vrms = V m sin 2
ω td ω t voltage to a standard level (Vz) , which remains
constant except near the Vdc to zero.
2
Vm 1 π 64. When UJT is used for triggering an SCR, the
= × ∫ (1 − cos 2ωt ) dωt wave shape of the signal obtained from UJT
2π 2 α
circuit is
π
Vm2  sin 2ωt  (a) Sine wave
=  ωt −  (b) Saw tooth wave
4π  2 α
(c) Trapezoidal wave
1/ 2
V  1  (d) Square wave
= m  π − α + sin 2α  IES-2014
2 π 2 
1/ 2
Ans. (b) : When UJT is used for triggering an SCR, the
200 2  π  wave shape of the signal obtained from UJT circuit is
=  π − + 0.433  = 126.7V  126V
2 π  3  sawtooth wave.
UJT- UJT is a three terminal semiconductor device
61. In a GTO, anode current begins to fall when which show negative resistance and switching
gate current characteristics. It can be used in gate pulse, timing
(a) is negative peak at time t = 0 circuits and trigger generator applications.
(b) is negative peak at time t = storage period
(c) just begins to become negative at t = 0
(d) just begins to become positive at t = 0
IES-2014
Ans. (b) : In GTO, anode current begins to fall when
gate current is negative peak at time t = storage time.
During ts, the negative gate current rises to a particular 65. Which type of protection is provided for SCR
value and prepares the GTO turning OFF by flushing by connecting the snubber circuit across it?
out the stored carriers. dv
GTO- Gate turn OFF thyristor is a special thyristor (a) protection
which is high power semiconductor device. dt
di
62. An SCR is turned off when its turn-off time is (b) protection
(a) less than the circuit time constant dt
(c) Over-voltage protection
(b) greater than the circuit time constant
(d) Over-current protection
(c) less than the circuit turn-off time
IES-2013
(d) greater than the circuit turn-off time BSNL(JTO)-2001
IES-2014
dv
Ans. (c) : An SCR is turned off when its turn-off time is Ans. (a) : For protection of SCR, snubber circuit is
less than circuit turn-off time. dt
Circuit turn off time- It is defined as the time during used.
which a reverse voltage is applied across a thyristor Snubber circuit is made by resistance and capacitor in
series across thyristor.
during its commutation process.
SCR turn off time < circuit turn off time.
If the circuit turn off time is less than the SCR turn off
time then forward bias voltage gets applied across even
before the thyristor could reason its forward blocking
capabilities and gets turn off again or the device turn In RC snubber circuit,
off is unsuccessful. Resistance is connected in series with capacitor to
63. The purpose of connecting a Zener diode in a protect from high value of discharging current.
UJT circuit, used for triggering thyristors, is to Protection of thyristor-
dv Which of these statements are correct?
High protection- Snubber circuit is provided across (a) 1, 2, 3 and 4 (b) 1 and 2 only
dt
SCR. (c) 2 and 4 only (d) 3 and 4 only
di IES-2011
High protection- Connect a inductor in series with Ans. (b) : SCR- Silicon controlled rectifier
dt
SCR. SCR is a three junction device.
Thermal protection- Provide heat sink in SCR. J1, J3 is forward bias, J2 is reverse bias.
1. Speed of operation of MOSFET is more
than the speed of operation of SCR.
2. SCRs have lower power loss than
MOSFETs.
3. The current in conducting state can easily
be controlled through the gate in SCR.
4. MOSFET is not a current-triggered device.
The correct statements are:
(a) 1 and 4 only (b) 1 and 2 only • To turn on SCR, VAK increased so much that a
(c) 2 and 3 only (d) 1, 2, 3 and 4 breakdown occurs at J2, SCR turn on.
IES-2012 • To turn it OFF, VAK is reversed and it cannot be
Ans. (a) : Statement (1) and statement (4) are correct. turned ON.
• Speed of operation of MOSFET is more than the • Gate terminal is used to turn on SCR by giving a
speed of operation of SCR pulse of proper polarity.
• Gate triggering is used in SCR to turn on SCR but • Once SCR is ON by means, gate terminal losses its
once when it goes on conducting state, there is not any control over SCR, so statement 3 is wrong.
control of gate current on SCR. • Gate recovery time is part of turn off time in which
• MOSFET is voltage controlled device, i.e.; recombination of charge takes place, so statement 4
It is not a current-triggered device. is wrong.
67. Which one of the following statements is Thus by elimination, option b is the correct choice.
correct about SCR? 69. Which one of the following devices can be
(a) SCR is constructed using an npn and pnp turned 'ON' or 'OFF' by applying gate signal?
transistor by connecting base of one transistor (a) SCR (b) SCS
to collector of the other transistor.
(c) Triac (d) UJT
(b) To switch off an SCR, gate current must be
reduced below certain threshold value. IES-2008
(c) Higher levels of gate currents in SCR cause it Ans. (b) : SCS-SCS stands for silicon controlled
to conduct at lower anode-to-cathode switch. A SCS is turn on by applying a positive voltage
voltages. between the anode gate and cathode terminals. It may
(d) The higher the gate current in SCR, the higher be turned off (forced commutation) by applying
the holding current to switch off. negative voltage between anode and cathode terminals,
IES-2011 or simply by shorting these two terminals together.
Ans. (c) : Higher level of gate currents in SCR cause it
to conduct at lower anode to cathode voltage.
When gate current is applied in SCR, SCR turns on and
forward blocking state changes to forward conduction
state. At this period forward anode to cathode voltage
is also applied. This anode to cathode forward voltage
can be reduced by higher gate current applied in SCR.
1. In a silicon controlled rectifier (SCR), if the
cathode gate is reverse-biased, then the SCR
cannot fire at all.
2. The turn-on time of an SCR increases with 70. The turn-on time of an SCR is 5 µs. Its trigger
temperature. pulse should have which one of the following?
3. After an SCR is turned on, it can be made to
turn off again by reverse biasing the gate. (a) Short rise time with pulse width = 2.5µs
4. Gate recovery time is the minimum time (b) Long rise time with pulse width = 3µs
that the anode voltage must be maintained (c) Short rise time with pulse width = 6µs
below holding voltage VH to turn off the (d) Short rise time with pulse width = 5µs
SCR. IES-2007
Ans. (c) : Trigger pulse should be short rise time. The Active region- Active region is the region between cut
turn on time of a SCR is 5 µs . Then pulse width should off and saturation region in a bipolar junction transistor.
In this region collector- base junction remains reverse
be more than turn off time and i.e.,
biased and base- emitter junction is in forward biased.
Short rise time with pulse width 6 µs . Pinch off voltage- Pinch off voltage refers the threshold
Turn on time SCR voltage below which device turn off.
TON = t d + t r + t p In FETs, the pinch off voltage is the value of VDS when
drain current reaches constant saturation value.
Width of trigger pulse > Turn of time of scr 73. Match List-I (Power Device) with List-II
Turn ON time generally (1 to 4 µ sec) (Maximum operation frequency) and select the
71. What are the different methods followed to correct answer using the codes given below the
take p-n-p-n device from its conducting state to lists:
the non-conducting state? List-I List-II
1. Reducing the anode current below the A. Bipolar transistors 1. 1 MHz
holding value. B. Power MOSFET 2. 100 kHz
2. Reducing the gate current to zero C. Silicon controlled 3. 1 kHz
3. Reducing the gate voltage to zero rectifier
4. Reducing anode voltage below the holding D. Insulated gate bipolar 4. 10 kHz
value. transistor.
Codes:
A B C D
below:
(a) 3 2 4 1
(a) 1 and 2 (b) 2 and 3 (b) 4 1 3 2
(c) 1 and 4 (d) 3 and 4 (c) 3 1 4 2
IES-2006 (d) 4 2 3 1
Ans. (c) : SCR can be turn off by forced commutation IES-2006
and natural commutation process. Ans. (c) : Devices Operational frequency
PNPN device can be convert from conducting to non- Bipolar transistors - 1 kHz
conducting state by - Power MOSFET - 1 MHz
• Reducing the gate current below the holding values. Silicon controlled rectifier - 10 kHz
• Reducing anode voltage below the holding value that Insulated gate bipolar transistor - 100 kHz
is forced commutation Operational frequency of devices are in order of as
So statement 1 and 4 are correct. below -
Power MOSFET>IGBT>SCR>Bipolar transistor
72. Match List-I (Device) with List-II (Associated
Term) and select the correct answer using the 74. In an SCR circuit, the anode is grounded. The
codes given below the lists: voltages at the gate and cathode at a particular
List-I List-II working condition are measured to be –50V
A. Diode 1. Pinch off voltage and –55V, respectively. Based on this
observation, it could be inferred that
B. SCR 2. Holding current
(a) The SCR is in forward blocking mode
C. BJT 3. Forward resistance
(b) The SCR is in forward conducting mode
D. FET 4. Active region
(c) The SCR is in reverse blocking mode
Codes: (d) The SCR is damaged
A B C D IES-2005
(a) 3 4 2 1
Ans. (b) : SCR is in forward conducting mode when
(b) 1 2 4 3
anode to cathode voltage is positive and gate voltage
(c) 3 2 4 1
with respect to cathode is positive
(d) 1 4 2 3
IES-2006
Ans. (c) : Diode - Forward resistance
SCR - Holding current
BJT - Active region
FET - Pinch off voltage
Forward resistance- The opposition offered by diode
to DC flowing current in forward bias condition is
known as DC forward resistance or static resistance.
Holding current-Holding current of SCR is that
minimum value of current below which anode current VAK=0–(–55)=55V
becomes zero and thyristor must fall to come in OFF VGK =–50+55=5V
state. So that SCR is in forward conducting mode.

75. Match List-I (Semiconductor Device) with List- 78. Match List-I (SCR Rating) with List-II
II (Application) and select the correct answer (Protective element) and select the correct
using the codes given below the lists: answer using the codes given below the lists:
List-I List-II List-I List-II
A. Triac 1. Used in HVDC system A. di/dt limit 1. Snubber circuit
B. IGBT 2. Used in pulse generation B. dv/dt limit 2. Heat sink
C. SCR 3. Used in motor control C. i2t limit 3. Series reactor
circuits D. Junction 4. Fuse
D. UJT 4. Used in ac regulators temperature limit
Codes: Codes:
A B C D A B C D
(a) 1 3 4 2 (a) 3 1 2 4
(b) 4 2 1 3 (b) 3 1 4 2
(c) 1 2 4 3 (c) 1 3 4 2
(d) 1 3 2 4
(d) 4 3 1 2
IES-2002
IES-2005
Ans. (b)
Ans. (a) : The devices with their applications are
di/dt limit- Series reactor (inductor in series with SCR)
mentioned as below -
dv/dt limit- Snubber circuit consists of series
Device Application combination of resistance and capacitance in parallel
TRIAC - Used in HVDC system with SCR.
IGBT - Used in motor control circuits i2t limit- Fuse has heat dissipation (i2R) limit when
SCR - Used in AC regulators current flows more than maximum allowed value the
UJT - Used in pulse generation fuse will melt down due to excessive heat.
76. Consider the following statements: An SCR, Junction temperature limit- Heat sink is designed as
from its OFF state, can be made ON by- per junction temperature limit.
1. increasing its anode voltage 79. Between the peak point and the valley point of
2. increasing its gate current UJT emitter characteristics we
3. decreasing its gate voltage have…….region
4. decreasing its anode current (a) Saturation
Which one of the following statements is (b) Negative resistance
correct? (c) Cut-off
(a) Either 1 or 2 (b) Either 1 or 3 (d) None of the above
(c) Either 2 or 4 (d) Either 3 or 4 Nagaland PSC CTSE (Diploma)-2017, Paper-I
IES-2004 Ans. (b) : Between the peak point and valley point of
Ans. (a) : An SCR from its OFF state can be turn on by- UJT emitter characteristics have negative resistance
1. Increasing the anode-cathode voltage above region.
forward breakdown voltage.
2. By increasing gate current or gate voltage.
77. In the forward blocking region of a silicon
controlled rectifier, the SCR is
(a) In the off-state
(b) In the on-state
(c) Reverse biased
(d) At the point of breakdown
TANGEDCO- 2015 80. Consider the following statements:
IES-2003 A four-layer PNPN device having two gate
Ans. (a) : In the forward blocking region of an silicon leads can turned on by applying a
controlled rectifier. The SCR is in the OFF state region. 1. positive current pulse to the cathode gate
2. positive current pulse to the anode gate
In forward blocking mode ( VAK < VBO ) junction J2 is 3. negative current pulse to the anode gate
reverse bias so that anode current is very small. 4. negative current pulse to the cathode gate
Which of these statements is/are correct?
(a) 1 alone (b) 1 and 3
(c) 2 alone (d) 2 and 4
IES-2000
Ans. (d) : A four layer PNPN device having two gate
leads can turned on by applying.
Above, latching current, SCR goes ON forward i. Positive current pulse to anode gate
conduction mode and SCR turn on from off state. ii. Negative current pulse to cathode gate.
84. Which one of the following statements
regarding the two transistor model of the
p-n-p-n four layer device is correct ?
(a) It explains only the turn ON portion of the
device characteristic
(b) It explains only the turn OFF portion of the
device characteristic
(c) It explains only the negative region portion of
PNPN devices having two gate is used for silicon the device characteristic
controlled switch. (d) It explains all the region of the device
81. Consider the following statements: characteristics.
The turnoff time of an SCR can be reduced by IES-1997
1. Quick withdrawal of the gate voltage. Ans. (d) :
2. Reducing lifetimes by doping with gold.
3. Applying a negative voltage pulse to the
gate of these statements:
IES-1998
Ans. (a) : The turn off time of an SCR can be reduced
by-
i. Quick withdrawal of gate voltage.
ii. Reducing lifetimes by doping with gold.
iii. Applying a negative voltage pulse to the gate. It explains all the reason of the device characteristic.
82. The ON voltage and forward break over 85. Match List-I (Device) with List-II (Property/
voltage of an SCR depend on the item associated with it) and select the correct
(a) gate current alone answer.
(b) bandgap of the semiconductor alone List-I List-II
(c) gate current and the semiconductor bandgap A. BJT 1. Pinch-off effect
respectively. B. FET 2. Controlled rectification
(d) semiconductor bandgap and the gate current C. SCR 3. Negative resistance
respectively characteristics
IES-1997 D. Tunnel diode 4. Punch-through effect
Ans. (c) : The ON voltage and forward break over Codes:
voltage of a SCR depend on the semiconductor bandgap A B C D
and the gate current respectively. (a) 1 3 2 4
As bandgap decreases the on voltage of SCR also (b) 1 2 3 4
decreases. VBF also decreases by decreasing the gate (c) 4 1 2 3
current.
(d) 1 4 3 2
83. An incremental model of a solid state device is IES-1996
one which represents the
(a) ac property of the device at the desired Ans. (c) :
operating point BJT - Punch through effect
(b) dc property of the device at all operating FET - Pinch off effect
points SCR - Controlled rectification
(c) complete ac and dc behaviour of the device at Tunnel diode - Negative resistance characteristic
all operating points Punch through effect- An emitter to collector
(d) ac property of the device at all operating breakdown which can occur in a junction transistor with
points very narrow base region at sufficiently high collector
IES-1997 voltage.
Ans. (a) : An incremental model of a solid state device When the space-charge layer extends completely across
is one which represents the AC properties of the device the base region.
at desired operating point. Pinch off effect- Pinch- off leads to channel pinching
Solid state device are electronic device in which that leads to current saturation behaviour under high
electricity flows through solid semiconductor crystals source-drain bias.
(silicon, gallium, arsenide, germanium etc.) rather than By using SCR triggering, controlled rectification can be
vaccum tubes. possible.
Tunnel diode having negative resistance characteristics. The above graph depicts
(a) drain characteristic of a MOSFET
(b) drain characteristic of an IGBT
(c) volt-ampere characteristic of a triac
(d) volt-ampere characteristic of an SCR
IES-2000
Ans. (c) : The graph depicts volt-ampere characteristic
of a TRIAC.
86. The average on state current for an SCR is 20A

for a conduction angle of 120º. The average on-
state current for 60º conduction angle will be
(a) 20 A (b) Less than 20 A
(c) 10 A (d) 40 A
Ans. (b) : Given, A TRIAC is a three terminal electronic equipment
For 1200 conduction angle, component that conducts current in either direction
Iav = 20A, from factor = 1.878 when triggered.
For 60 conduction angle, θ = 180 − 60
0 0 0
θ = 1200
Iav = m (1 + cos1200 )
I
2π
I
Iav = m
4π
1/ 2
 I 2m  π − θ 1 2  88. A thyristor equivalent of thyratron tube is
I rms =   + sin θ  (a) SCR (b) UJT
 2π  2 4 
(c) Diac (d) Triac
1/ 2
I π 1  Nagaland PSC CTSE (Degree)-2018, Paper-I
I rms = m  + × ( −0.866 ) 
2π  6 4  Ans. (a) : The silicon controlled rectifier is a solid state
I rms = 0.221I m equivalent of thyratron tube. The gate anode and
cathode of SCR correspond to the grid, plate and
I 0.221I m
Form factor = rms = = 2.776 cathode of thyratron for this reason SCR is sometimes
Iav I m / 4π called thyristor.
I rms 89. Which of the following device used for high
Iav =
form factor frequency applications?
0
For 120 conduction angle (a) Diac (b) Triac
I (c) SCR (d) BJT
20 = rms SAIL- 2014
1.878
Irms = 37.56 Ans. (c) : Application of SCR
37.56 SCR device used for high frequency Application.
For 600 conduction angle Iav = = 13.53 The silicon controlled rectifier (SCR) is used in
2.776
0 (AC) voltage stabilizers.
For 60 conduction angle, The silicon controlled rectifier (SCR) is used as
Iav less than 20A switch.
87. It is used in choppers.
The silicon controlled rectifier (SCR) is used in
inverters.
90. Which one of the following statements is NOT
true ?
(a) For SCRs to be in the conduction state, the
forward anode current must be greater than
the latching current.
(b) For SCRs to be in the forward blocking state,
the forward anode current must be lower than
the holding current.
(c) When SCRs are in the conduction state, they 94. An SCR has a turn on time of 4 µs. The gate
can be turned off by applying suitable gate pulse should be of duration about
pulses. (a) 2 µs. (b) 5 µs.
(d) When avalance breakdown takes place, SCRs,
(c) 20 µs. (d) 50 µs.
enter into the conduction state.
BSNL(JTO)-2009 KVS TGT (WE)- 2014
Ans. (c) : For SCRs to be in the conduction state. The Ans. (b) According to the question, turn on time of SCR
forward anode current must be greater than the latching = 4 µs and gate pulse duration should be slightly greater
current. For SCR to be in the forward blocking state. than the turn on time of the about 5 µs.
The forward anode current must be lower than the (a) Ton = t d + t r + t s
holding current. The avalanche breakdown take place. (b) td = Delay time
SCRs enter in to conduction state. (c) tr = Rise time
91. A power diode has lightly doped n type (d) ts = Spread time
substrate sandwiched between heavily doped p 95. Two Thyristors of same rating and same
and n regions
specification
(a) to increase reverse breakdown voltage (a) Will have equal turn on and off period
(b) to reduce ohmic loss under forward bias
(b) Will have equal turn on but unequal turn off
(c) to decrease switching time of the power diode
period
(d) to improve transient behaviour of the diode
(c) May have equal or unequal turn on and turn
BSNL (JTO)-2006
off periods
Ans. (d) : A power diode has lightly doped n type (d) Will have unequal turn on and turn off periods
substrate sandwiched between heavily doped p and n
KVS TGT (WE)- 2014
regions to improve transient behaviour of the diode.
(c) : Two Thyristors whose rating and specification are
92. An ideal thyristor is driving an R-L load of same. Their turn on and turn off periods should be equal
impedance Z. Input AC voltage Vs =Vm sin ωmt. or unequal because SCR same as diode and only one
If thyristor if fired at an input phase angle of
direction current conduct device.
90º. What will be the output voltage and output
current across R-L load as the instant of firing? 96. The two transistor equivalent circuit of SCR is:
(a) Output voltage is Vm and output current is (a) (b)
Vm/Z
(b) Output voltage and output current are both
zero
(c) Output voltage is zero and output current is
delayed by an angle 90º
(d) Output voltage is Vm and output current is
zero (c) (d)
BSNL (JTO)-2006
Ans. (d) : An ideal thyristor is driving an R-L load of
impedance Z. Input AC voltage Vs =Vm sin ωmt. If
thyristor if fired at an input phase angle of 90º. Then the
output voltage and output current across R-L load as the KVS TGT (WE)- 2017
instant of firing, output voltage will be Vm and the Ans. (d) : Two transistor analogy of SCR combination
output current will be zero. of n-p-n and p-n-p transistor SCR is a three terminal
93. In a DIAC the breakdown voltages are related device anode, cathode and gate terminal.
with the following equation:
(a) VBR1 = VBR 2 ± 0.1 VBR 2
(b) VBR1 = 2VBR 2
VBR 2
(c) VBR1 =
2
3
(d) VBR1 = VBR 2 97. A TRIAC is :
2
KVS TGT (WE)- 2018 (a) four terminal device
(b) bilateral device
Ans. (c) : Breakdown voltage in a Diac.
(c) two terminal device
VBR 2 (d) unilateral device
VBR1 =
2 KVS TGT (WE)- 2017
Ans. (b) : TRIAC– A TRIAC (triode for alternating 1
current) also bidirectional triode thyristor is a three =
 1 
terminal electronic device that conducts current in either 10 × 103 × 0.1× 10−6 × ln  
direction when triggered.  1 − 0.8 
It is define as three terminal AC switch which is 1 1000
f= =
different from the other SCR, It will conduct in both  1  ln(5)
positive and negative half cycle of AC signal. 10−3 × ln  
 0.2 
1000
f= = 621.33Hz
1.609
f  620Hz
100. Which device is used in relaxation oscillator?
(a) SCR (b) diac
(c) triac (d) UJT
98. An UJT, the p-type emitter is………..doped GPSC Asstt. Prof. 11.04.2017
(a) Lightly (b) Heavily Ans. (d) : The UJT is a three-terminal, semiconductor
(c) Moderately (d) None of the above devices which exhibits negative resistance and
Nagaland PSC CTSE (Diploma)-2017, Paper-I switching characteristics for use as a relaxation
Ans. (b) : oscillator in phase control application.
101. It is required to deliver an output DC power of
500 W to a resistive load. The transformer
rating required in case of half-wave,
conventional full-wave and bridge rectifiers,
respectively, is
(a) 1.7 kW, 616 W, 871 W
• The device has only junction, So it is called the (b) 1.7 kW, 871 W, 616 W
unijunction device. (c) 616 kW, 1.7 W, 871 W
• In a Unijunction transistor, the emitter is heavily (d) 871 kW, 616 W, 1.7 W
doped while the N-region is lightly doped, so the Mizoram PSC Jr. Grade -2018, Paper-II
resistance between the base terminals is relatively high, Ans. (b) : Transformer utilization factor
typically 4 to 1 kilo ohm when the emitter is open. Pdc
(TUF) =
99. Assume the intrinsic standoff ratio for the UJT Rating of secondary winding
is 0.8 for the relaxation oscillator circuit given Half wave rectifier (TUF) = 0.2865
below. The frequency of oscillation of this Center taped full wave rectifier TUF = 0.573
circuit is approximately equal to Bridge rectifier TUF = 0.8106
500
for half wave rectifier = 0.2865 =
Vs ⋅ Is
500
Vs.Is = = 1745.2 W = 1.7 kW
0.2865
Center taped
500
0.573 =
Vs Is
(a) 1.43 kHz (b) 620 Hz 500
Vs Is = = 872.6 Watt
(c) 7 kHz (d) 1.6 kHz 0.573
ISRO Scientist Engg.-2010 Bridge rectifier
Ans. (b) : Given, 500
0.8106 =
Intrinsic stand-off ratio (η) = 0.8 Vs Is
R1 = 100Ω, R2 = 39Ω, R3 = 10kΩ, C1 = 0.1µF 500
 1  Vs Is = = 616.67 Watt
We know, T = R 3 C1l n   0.8106
1− η  102. A six pulse thyristor rectifier bridge is
So, Oscillation frequency connected to a balanced 50 Hz, three phase AC
1 1 source. Assuming that the DC output current
f= = of rectifier is constant, the lowest frequency
T  1  harmonic component in the AC source line
R 3 C1l n  
 1− η  current is
(a) 100 Hz (b) 150 Hz 400 sin θ = 200
(c) 250 Hz (d) 300 Hz 200
GPSC Asstt. Prof. 11.04.2017 Sin θ =
400
Ans. (c) : In a six pulse thyristor bridge rectifier, the
−1  1 
harmonics present are 6K ± 1 θ = sin  
So the harmonics are = 5, 7, 11, 13 2
lowest harmonic component = 5th θ = 300
harmonic frequency = 50Hz π–θ = 180– 30 = 150º
5th harmonic frequency = 5f = 250Hz 107. A single-phase full-wave AC phase controller
103. For a single phase half-wave controlled feeds power to a resistive load of 100 Ω from a
rectifier has 400sin314t as the input voltage 220 V, 50 Hz supply. What will be the rms
and R as the load. For a firing angle of 600 for output voltage at delay angles α1 = α 2 = α = π/2
the SCR, the average output voltage is of both transistors ?
(a) 400/π (b) 300/π
220
(c) 240/π (d) 200/π (a) V (b) 2 × 220 V
Mizoram PSC IOLM-2010, Paper-II 2
V (c) 2 ×110 V (d) 2 × 220 V
Ans. (b) : Average output voltage V0 = m (1 + cos α )
2π ISRO Scientist December, 2017
400 Ans. (a) : Single phase midpoint controlled converter is
= (1 + cos 60º ) given –
2π
400 3 300 The rms output voltage is given by
= × = V Vm  sin 2α 
1/ 2
2π 2 π V0(rms) = (π − α) +
104. In controlled rectifiers, the nature of load 
2π  2 
current is continuous or discontinuous π
(a) Does not depend on type of load and firing There Vm = 200 2, α =
2
angle delay Therefore,
(b) Depends both on the type of load and firing
π  sin ( π ) 
1/ 2
angle delay 220 2 
(c) Depends only on type of load V0(rms) =  π −  + 
2 π  2 2 
(d) Depends only on the firing angle delay
1/ 2
Mizoram PSC IOLM-2010, Paper-II 220 2  π  
Ans. (b) : In controlled rectifier, the nature of load =   + 0 
2 π  2  
current depends on load nature as well as firing delay
220
angle. Continuous and discontinuous mode depends on = V
load type. 2
105. The effect of source inductance on the 108. A freewheeling diode in a phase controlled
performance of a single-phase and three-phase rectifier
full converter is to (a) improves the line power factor
(a) Reduce the ripples in the output load current (b) enables inverse operation
(b) Make discontinuous current as continuous (c) is responsible for additional reactive power
(c) Reduce output voltage (d) is responsible for additional harmonics
(d) Increase the load voltage IES-2015
Mizoram PSC IOLM-2010, Paper-II Ans. (a) : Improves the line power facto a free
Ans. (c) : When source inductance present in circuit for wheeling diode placed across the inductive load will
some time all diode or SCR will conducts Hence o/p provide a path for the release of energy stored in
voltage decrease and conduction time increase. inductor while the load voltage drops zero...... as a
106. A single-phase one pulse controlled circuit has result the load current is transferred from the main
resistance and counter emf load and 400 sin thyristor to FD, allowing the thyristor to regain its
314 t as the source voltage for a load counter forward blocking capability.
emf of 200 V, the range of firing angle control 109. In a thyristor DC chopper, which type of
will be commutation results in best performance?
(a) 300 to 1500 (b) 300 to 1800 (a) Voltage commutation
0 0
(c) 60 to 120 (d) 600 to 1800 (b) Current commutation
RPCS Lect.-2011 (c) Load commutation
Ans. (a) : The range of firing angle control for single (d) Supply commutation
phase one pulse controlled circuit is θ to π–θ. GPSC Asstt. Prof. 11.04.2017
V= 400 sin 314t Ans. (a) : In a thyristor DC chopper voltage
Vm = 400 commutation type of commutation results in best
E = 200 V performance.
110. A step down chopper is operated in the Ans. (b) : For firing angle range 0º ≤ α ≤ 90º converter
continuous conduction mode in steady state act as rectifier for firing angle range 90º ≤ α ≤ 180º
with constant duty ratio D. If Vo is the converter acts as inverter with suitable dc source in the
magnitude of the DC output voltage and if Vs is load circuit. The suitable dc source may be back emf.
the magnitude of the DC input voltage, the Solar cell or battery etc.
ratio Vo/Vs is given by 115. Inverters find applications in
(a) D (b) 1 – D (a) UPS (b) DC drives
(c) 1/(1 – D) (d) D/1 – D (c) HVAC transmission (d) rectifiers
GPSC Asstt. Prof. 11.04.2017 GPSC Asstt. Prof. 11.04.2017
Ans. (a) : In steady state with a constant duty ratio = DAns. (a) : An uninterruptible power supply is an
output voltage = Vo electrical apparatus that provides emergency power to a
input voltage = Vs load when the input power source or main power tails.
Vo Inverters find applications in UPS.
=D 116. A single phase voltage source square wave
Vs
inverter feeds pure inductive load. The
111. The duty cycle of a pulse of width 2 waveform of the load current will be
microsecond and repetition frequency 4kHz is (a) sinusoidal (b) rectangular
(a) 0.5 (b) 0.06 (c) trapezoidal (d) triangular
(c) 0.008 (d) 0.8 GPSC Asstt. Prof. 11.04.2017
Mizoram PSC AE/SDO 2012-Paper-I Ans. (d) : A single phase voltage source square wave
Ans. (c) : Duty cycle = Pulse width × frequency inverter feed pure inductive load. The waveform of the
= 2×10−6 × 4×103 load current will be triangular.
= 8 ×10−3 117. A voltage source inverter is normally employed
= 0.008 when
112. In dc chopper if Ton is the on-time and f is the (a) Source inductance is large and load
chopping frequency, then output voltage in inductance is small
terms on input voltage, Vs is given by (b) Source inductance is small and load
(a) Vs*Ton/f (b) Vs.* f / Ton inductance is large
(c) Vs/f*Ton (d) Vs*f*Ton (c) Both source and load inductance are small
Mizoram PSC IOLM-2010, Paper-II (d) Both source and load inductance are large
Ans. (d) : V0 = α ⋅Vs
Ans. (b) : A voltage source inverter is normally
T employed when source inductance is small and load
V0 = on × Vs
T inductance is large.
V0 = Ton ⋅ f ⋅ Vs 118. The output voltage waveform of a three phase
square wave inverter contains
113. A step-down chopper, fed from a 120 volt DC (a) Only even harmonics
source, operates a DC motor whose armature (b) Both even and odd harmonics
e.m.f. and armature resistance are 100 volt and (c) Only odd harmonics
0.5Ω respectively. With the magnitude control (d) Both triple harmonics
ratio 0.6, the quadrant of operation DC motor GPSC Asstt. Prof. 11.04.2017
is Ans. (c) : The output voltage waveform of a three phase
(a) First (b) Second square wave inverter contains only odd harmonics.
(c) Third (d) Fourth 119. Which of the following circuits can be used as a
BSNL (JTO)-2006 DC transformer
Ans. (a) : First quadrant operation, (a) Controlled rectifier using SCRs
Chopper ON = V0 = Vs (b) Magnetic amplifier
Chopper Off = V0 = 0 (c) Inverter
Step down chopper because load voltage 0 & average (d) None of these
voltage is less than supply voltage. UJVNL AE-2016
Power flow from source to load (P0 – +ve) Ans. (c) : A DC transformer is generated by adding a
114. For a single phase fully controlled converter number of overdriven mosfets to an AC Transformer.
bridge operating with continuous load current, Hence a inverter circuit can be used as a DC
the converter will operate in inverting mode for transformer.
triggering angle, α, such that: 120. The primary function of a phase inverter is to
(a) 0 < α < π / 2 (b) π / 2 < α < π change the phase of a signal by
(c) π / 4 < α < 3π / 4 (d) α < π (a) 90º (b) 120º
BSNL (JTO)-2002 (c) 360º (d) 180º
BSNL (JTO)-2001 TNPSC AE-2014
Ans. (d) : A phase inverter is simply an amplifier 126. Which of the following components convert
configured in such a way to give the original amplified fixed DC to variable DC?
signal and another signal 180 out of phase to drive the (a) Rectifiers (b) Choppers
push pull amplifier. (c) Cycloconverters (d) Inverters
121. In the NMOS inverter RRB JE- 31.08.2019, 10 AM-12 PM
(a) The driver and active load are enhancement GPSC Asstt. Prof. 11.04.2017
type Ans. (b) : A chopper is an electronics device that
(b) The driver is enhancement type and load converts fixed dc input to a variate output voltage
depletion type directly. It is also known as dc to dc conveters and dc
(c) The driver is depletion type and load transformer because of similar to the transformer of the
enhancement type ac circuit, choppers are used to step up and step down
(d) Both driver and load are depletion type the output dc value.
127. Figure shows some load voltage versus load
Ans. (a) : In the NMOS inverter both driver and load
current plots. Which one of them is NOT valid
are enhancement type.
for the classification of dc-dc converters.
122. Which of the following is correct for inverters?
(a) VSI and CSI both require feedback diodes
(b) Only CSI requires feedback diodes
(c) GTOs can be used in CSI
(d) Only VSI requires feedback diodes
Ans. (d) : the main difference between current source
inverter and voltage source inverter is that VSI requires
feedback diodes while CSI does not requires any
feedback diode.
123. From circuit design simplicity and economy
point of view, one of the following
configurations for a converter is the best.
Which is that?
(a) Push-pull DC-DC converter using one
transformer
(b) Ringing choke converter
(c) Push-pull converter using two transformers
(d) None of these (a) P (b) Q
Kerala PSC Lecturer (NCA) 04.07.2017 (c) R (d) S
Ans. (b) : Ringing choke converter–This is also BSNL(JTO)-2009
known as self oscillating fly back converter. Ans. (d) : (P) First quadrant type A chopper
The circuit design economy point of view, ringing
choke converters are best.
124. A push pull inverter provides a
(a) Highly regulated output
(b) Constant DC output
(c) Square wave output
(d) None of these Power is positive
Kerala PSC Lecturer (NCA) 04.07.2017 Suitable for forward motoring application.
Ans. (c) : A push pull conversion is a type of DC-DC (Q) Second quadrant type B- chopper
converter, a switching converter that uses a transformer
to change the voltage of DC power supply. A push pull
amplifier has square wave output.
125. The electronic circuit that converts AC to DC
where the DC output peak value can be greater
than the AC input peak value is- Power in negative
(a) Voltage multiplier (b) Clipper Suitable for forward regenerative braking.
(c) Amplifier (d) Clamper (R) Type C – chopper (or) two quadrant type A-chopper
RRB JE- 31.08.2019, 10 AM-12 PM
Ans. (a) : The voltage multiplier is a type of diode
rectifier circuit which can produce an output voltage
many times greater than of the applied input voltage.
Voltage multipliers are similar in many ways to
rectifiers in that they convert ac to dc.
e.g. a voltage doubler is voltage multiplier circuit which
has a voltage multiplication factor of two.
Power is positive and negative. Ans. (b)
Suitable for forward motoring and forward regenerative
braking.
(S) It is not valid for the classification of dc-dc
converter.
curve A = Re-entrant limiting mode

Curve B = Current limiting mode
130. What is the peak to average power ratio for
the signal x(t)=Asin( ωt) with 50% duty cycle?
(a) 0 dB (b) 1 dB
128. Which of the following statements about the (c) 3 dB (d) 6 dB
working of SCR is INCORRECT? ISRO Scientist Engg.-2018
(a) To open the SCR, reduce the supply voltage Ans.(d): D = 1/2, x(t) = Asin(ωt)
to zero P ∝ A2
(b) Applying small positive voltage to the gate is 2
the normal way to close an SCR because P ∝  A  × 1
avg  
break over voltage is usually much greater  2 2
than supply voltage
A2
(c) There are two ways to turn on the SCR. One Pavg ∝
of the methods is to keep the gate open and 4
make supply voltage lesser to the break Ppeak ∝ A
2
overvoltage Ppeak A 2
(d) An SCR has two states i.e., either it does not = 2 ×4 = 4
conduct, or it conducts heavily. Therefore, Pavg A
SCR behaves like a switch P
DFCCIL Executive S&T 29.09.2021, 12:30 to 2:30PM Power gain in dB = 10log peak
Ans. (c) : Turn ON method of SCR :– Pavg
(a) Thermal Triggering :– The width of depletion = 10log 4
layer in a semiconductor decreases with increasing = 6 dB
temperature. Therefore, if voltage between the anode 131. A High speed digital subsystem requires three
and cathode in the thyristor is equal to the break down voltages V1, V2 and V3 with 1 : 2 : 1 power
voltage, then the SCR becomes ON when the ratings, respectively. The power supply is
temperature rises. designed with the distribute power conversion
(b) Radiation Triggering :– SCR can also be turned scheme as shown in the following figure. What
On by bombarding it with a light photon. is the overall power conversion efficiency ?
(c) Voltage Triggering
(d) dv Triggering
dt
(e) Gate Triggering
129. Identify A and B current limiting techniques in
a.c. to d.c. power supplies respectively, in the
graph below.
4 × η1 × η2 × η3 η1 × η2 × η3
(a) (b)
η2 η3 + 2 × η3 + η2 η2 η3 + 2 × η3 + η2
4 × η1 × η2 × η3 2 × η1 × η2 × η3
(c) (d)
η2 η3 + η2 + η3 η2 η3 + η2 + η3
V
(a) Current limiting mode, Constant Current Ans. (a) : efficiency ( η ) = out
Vin
mode
(b) Re-entrant limiting mode, Current limiting Vout = V1 + V2 + V3 , V1 : V2 : V3 ::1: 2 :1 = 4V
mode Let V1 = V then V2 = 2V and V3 = V
(c) Current limiting mode, Fold back limiting mode V V
(d) Fold back limiting mode, Re-entrant limiting V1 + 2 + 3
Vout η2 η3
mode Vin = =
ISRO Scientist Engg.-2018 η1 η1

2V V  2 1  3 × 1000
V+ + V 1 + +  String efficiency =
η1 η3 η2 η3  n × 800
= =  3 × 1000
η1 η1 n ×8 =
75
Vout 4V n=5
∴η = =
Vin  2 1  135. __________ is the device which acts like an N-
1+ η + η  P-N and a P-N-P transistor connected base-to-
V 2 3  base and emitter-to-collector.
 η1  (a) TRIAC (b) SCR
 
  (c) UJT (d) DIAC
4η1 RRB JE- 31.08.2019, 10 AM-12 PM
= Ans. (b) : An SCR-Silicon controlled rectifier is 4
2 1
1+ + layered solid-state current controlling device. It has
η2 η3 PNPN or NPNP structure with three P-N junctions and
4 × η1 × η2 × η3 three terminals. The operation of SCR is similar to a
= PNP and NPN transistors connected base to collector
η2 η3 + 2 × η3 + η2
and emitter to base.
132. Which of the following statements is TRUE for
DC switched mode power supply?
(a) It cannot provide isolation between input and
output as in rectifiers.
(b) It cannot remove ripple as in DC switching
mode regulators.
(c) It has two stage conversions : dc-ac and ac-
dc.
(d) It is a type of chopper circuit. 136. The latching current of an SCR is 4 mA. Find
BSNL(JTO)-2009 the minimum width of gate pulse required to
Ans. (d) : For all type of chopper circuit. The output successfully turn on the SCR if source voltage
is 100 V and inductance in the circuit is 0.1
voltage value is controlled by periodic closing and
Henry
opening of the switching used in the circuit. (a) 2 micro second (b) 2.5 micro second
(c) 0.4 micro second (d) 4 micro second
Ans. (d) : We know that for R.L. circuit
For L circuit
di
V = L⋅
133. A Silicon Controlled Resistor (SCR) is made up dt
of silicon and not germanium because ∆I
100 = 0.1×
(a) silicon is inexpensive ∆T
(b) silicon is mechanically strong 0.1× 4 × 10−3
(c) silicon has small leakage current ∆ T =
100
(d) silicon is tetravalent ∆T = 4 µ sec
KVS TGT (WE)- 2016
137. A 3 –phase full convertor takes a voltage of 200
Ans. (c) : SCR is made of silicon instead of Germanium
V. Calculate the supply power factor, if the
because silicon has less leakage current. charging current in the battery is 20A. Given
Silicon crystals have higher temperature tolerance than
the power delivered to the load is 3500 2W .
germanium crystal.
(a) 0.875 (b) 0.65
134. A circuit uses SCR of 800V rating after which (c) 0.75 (d) 0.725
the derating is 25% then the SCR in series. LMRC AM- 16.07.2021
(a) 4 (b) 5
Ans. (a) : Given,
(c) 6 (d) 8 Vrms = 200V
KVS TGT (WE)- 2014 Constant current I0 = 20A
(b): Derating = 1– string efficiency Q Each SCR conduct for 1200 for every 1800.
String efficiency = 1–0.25 Therefore in case if output current I0 then rms value of
= 0.75 source current is
Total voltage 2π 1
String efficiency = I rms = I20 × ×
n × Voltage across SCR 3 π

I rms = I0 2 / 3 Range of firing angle –
α to 180 − α
I rms = 20 2 / 3
Irms = 16.33A 30º to 150º
And power delivered to the load is 3500 2W . Now we 141. A 3-phase full wave bridge rectifier yields
know that for 3 − φ ____diodes.
P (a) three (b) eight
cos φ = (c) four (d) six
3VI
LMRC AM- 16.07.2021
3500 2 Ans. (d) : A 3-phase full wave bridge rectifier yields six
cos φ =
3 × 200 × 16.33 diodes.
cos φ = 0.875 142. Which one of the following can be used in the
138. How many diodes are present in a single phase, lighting system for power interruptions?
full-wave, mid-point convertor? (a) Diac (b) Triac
(a) 2 (b) 6 (c) SCR (d) SCS
(c) 3 (d) 4 DFCCIL Executive S&T-17.04.2016, Shift-II
LMRC AM- 16.07.2021 Ans. (c) : SCR can be used in the lighting system for
Ans. (a) : 2 diodes are present in a single phase, full- power interruptions. SCR circuit are widely used for
wave, mid-point converter. power control of both DC and AC systems.
139. What will be the one cycle surge current of a SCR (Silicon controlled Rectifier) is a three terminal, 4
SCR if it has half cycle surge current rating of Layer, current controlled semiconductor device.
5000 A for 50 Hz supply? 143. A single phase full wave mid-point thyristor
(a) 2345.89A (b) 3456.09A uses a 220/200 V transformer with central tap
(c) 3535.53A (d) 1232.66A on the secondary side. The PIV per thyristor
DFCCIL Executive S&T-17.04.2016, Shift-II will be:
Ans. (c) : Equating the energies involved in a cycle and (a) 282.84 V (b) 333.98 V
a half cycle for SCR (c) 789.87 V (d) 556. 34 V
I 2T = Isc2
×t DFCCIL Executive S&T-17.04.2016, Shift-II
1 1 Ans. (a) :
T time limit for one cycle · = =
f 50
T
t = (Time limit for half cycle)
2
2 2 T
I × T = Isc × Vrms = 100 V
2
I 5000 Vm = 100 2 V
I = sc =
2 2 PIV = 2 Vm
I = 3535.53A = 200 2 = 282.84 V
140. A single phase one pulse controlled circuit has 144. Identify the given symbol.
a resistance and counter emf load 200 sin (512t)
as the source voltage for a load counter emf of
100 V, the range of firing angle control will be:
(a) 30º to 110º (b) 0º to 30º
(c) 120º to 150º (d) 30º to 150º
Ans. (d) :
(a) SIDAC
(b) TRIAC
(c) DIAC
Assume, firing angle α is - (d) PHOTO THYRISTOR
then 200 sinα = 100 DFCCIL Executive S&T-17.04.2016, Shift-II
100 1
sin α = = Ans. (b) : The symbol given is that of the TRIAC. The
200 2 TRIAC is three terminal electronic device, when
α = 30º triggered, can conduct current in both directions.

07.
Control System
(c) Mathematical analysis involves approximations
(i) Mathematical Modeling of (d) System has large negative phase angle at high
Dynamic Linear Continuous frequencies
System Nagaland PSC (Degree) 2018, Paper-II
1. In Force-Voltage Analogy Nagaland PSC CTSE- 2015, Paper-II
(a) Force is analogous to current Mizoram PSC IOLM-2010, Paper-II
(b) Mass is analogous to capacitance Ans. (a) : Despite the presence of negative feedback,
(c) Velocity is analogous to current control system still have problems of instability because
(d) Displacement is analogous to magnetic flux of component used have nonlinearity there is always a
linkage variations as compared to ideal characteristic.
LMRC AM-16.0.2021 5. The transfer function of a tachometer is of the
IES-2016 form
Ans. (c) : In force voltage analogy, velocity is K
(a) Ks (b)
analogous to current. On comparison between s
differential equation of mechanical system and K K
(c) (d)
electrical system- s +1 s ( s + 1)
d2x dx UJVNL AE-2016
M + B + Kx = F ………..(i)
dt 2 dt BEL-2015
2
dq dq 1 Nagaland PSC CTSE- 2015, Paper-II
L 2 +R + q = V ………….(ii) Ans. (a) : For tachometer y(t) = e (t) and x (t) = θ (t)
dt dt C
1 dθ ( t )
Where, K = M=L e(t) ∝
C dt
B=R F=V E (s) = K ⋅ s θ(s)
Force is analogous to voltage, mass is analogous to E ( s )
inductance and displacement is analogous to charge. = K ⋅s
θ (s )
2. The charge q in the electrical system is
analogous to which thermal system quantity? T (s ) = K ⋅ s
(a) Heat flow (b) Temperature 6. Consider a mechanical system shown in figure.
(c) Resistance (d) Capacitance Masses are free to slide over frictionless
APPSC Poly. Lect. 15.03.2020 horizontal surface. The equation of motion of
Ans. (a) : In the analogy system, charge in the electrical mass m1 is
system is analogous to heat flow in thermal system. 1
3. In mechanical translational system, mass is

analogous to which rotational system
component?
(a) Torque
(b) Moment of inertia
(c) Angular displacement x1 + (λ1 + λ 2 )x& 1 + λ 2 x& 2 – (k1 + k 2 )
m1&&
(a)
(d) Angular velocity x1 – k 2 x 2 = F2
APPSC Poly. Lect. 15.03.2020 x1 + (λ1 – λ 2 )x& 1 + λ 2 x& 2 – (k1 + k 2 )
m 2 &&
Ans. (b) : Mass in mechanical translational system is (b)
x1 – k 2 x 2 = F1
analogous to moment of inertia in rotational system.
4. Despite the presence of negative feedback, m1&&x1 + (λ1 + λ 2 )x& 1 − λ 2 x& 2 + (k1 + k 2 )
(c)
control system still have problems of instability x1 – k 2 x 2 = F1
because of
x1 + (λ1 – λ 2 )x& 1 + λ 2 x& 2 – (k1 − k 2 )
m1&&
(a) Components used have non-linearities (d)
(b) Dynamic equations of the subsystems are not x1 – k 2 x 2 = F2
known exactly ISRO Scientist Engg.-2018
Control System 892 YCT
Ans.(c): Free body diagram for mass m1 Ans. (c) : An automatic washing machine is a open loop
control system. Other example of open loop control
system is traffic signals, bread toaster etc.
12. The main draw-back of a feedback system is
(a) inaccuracy (b) inefficiency
(c) insensitivity (d) instability
Differential equation for mass m1 RPCS Lect.-2011
x1 + k l x1 + λ1x& 1 + k 2 ( x1 − x 2 ) + λ 2 ( x& 1 − x& 2 )
F1 = m1&& Ans. (d) :The main drawback of feedback system is
instability (It mean undesired / persistent oscillations of
x1 + ( λ1 + λ 2 ) x& 1 − λ 2 x& 2 + ( k1 + k 2 ) x1 − k 2 x 2
= m1&& output variable)
7. The common range of step size in stepper 13. In position control systems, Tachogenerator
motor which are interfaced with micro feedback is used to :
processor based systems is (a) Increase the effective damping in the system
(a) 0º to 10º (b) 10º to 29º (b) Decrease the effective damping in the system
(c) 0.9º to 30º (d) 0.3º to 45º (c) Decrease the steady state error
TNPSC AE - 2018 (d) Increase the steady state error
Ans. (c) : The high number of teeth allows the motor to IES-2016
achieve a small step size down to 0.9º while maximum Ans. (a) : A tachogenerator can be found in various
step size is 30º. kinds of machine tool and other equipment where the
measurement of speed and direction is essential.
8. In a synchro error detection, the output voltage
Let standard 2nd order system representing the position
is proportional to [ω(t)]n, where ω(t) is the
control system and employing a tachogenerator
rotor velocity and n equals to feedback is given as.
(a) –2 (b) –1
(c) 1 (d) 2
Ans. (c) : In a synchro error detector, output Voltage is
proportional to ω(t)
V0 ∝ [(ωt)]n
for n = 1 The characteristic equation is given by-
V0 ∝ω(t) 1 + G (s) H (s) = 0
ω2n
9. In a speed control system, output rate feedback 1+ × (1 + sK b ) = 0
is used to s ( s + 2ξωn )
(a) Limit the speed of motor
s 2 + 2ξωn s + ωn2 K bs + ωn2 = 0
(b) Limit the acceleration of motor
(c) Reduce the damping of the system s 2 + ( 2ξωn + ωn2 K b ) s + ωn2 = 0
(d) Increase the gain margin On the comparison with standard 2nd order
Mizoram PSC IOLM -2018, Paper II characteristic equation-
Ans. (c) : In a speed control system, the output rate s 2 + 2ξ'ω'n s + ωn'2 = 0
feedback is used to reduce the damping. So that the
ω'2n = ω2n ; ω'n = ωn
output should be smooth.
10. The mathematical model of a system is linear, 2ξω n = 2ξωn + ωn K b
' ' 2
if it obeys the principle of 2ξωn + ω2n K b ωK

(a) Superposition ξ' = = ξ+ n b
2ω'n 2
(b) Homogeneity
 ωK 
(c) Reciprocity Damping value become  ξ + n b  which is greater
(d) Superposition and Homogeneity  2 
Nagaland PSC CTSE (Degree)-2016, Paper-II than ξ . Hence, tachogenerator feedback is used to
Ans. (d) : The mathematical model is linear if it obeys increase the effective damping of the system.
both homogeneity & superposition. 14. In a closed loop system for which the output is
11. An automatic washing machine is the speed of a motor, the output rate control
can be used to :
(a) A single feedback control system
(a) Limit the speed of the motor
(b) A multi-feedback control system
(b) Limit the torque output of the motor
(c) An open loop control system (c) Reduce the damping of the system
(d) None of these (d) Limit the acceleration of the motor
Nagaland PSC CTSE (Degree)-2016, Paper-II IES-2015
Ans. (a) : When the speed of this motor is to be I − I0
controlled, a tacho-generator is used to detect the speed K=
H − H0
and is attached to the motor. A tachogenerator can be
found in various kinds of machine tool and other Given, I0 = 4mA, H0 = 2m, H = 3m, I = 20 mA.
equipment where the measurement of speed and 20 − 4
Then, K = = 16
direction is essential. 3− 2
The voltage and frequency increases with a rise of the When relay closes at I = 12mA, H = H1
rotational speed. Thus rotational speed of the motor is I = I0 + K ( H1 − H 0 )
controlled.
12 = 4 + 16 ( H1 − 2 )
15. In a servo-system, the device used for providing
derivative feedback is known as : 8
H1 − 2 =
(a) Synchro (b) Servomotor 16
(c) Potentiometer (d) Tachogenerator H1 = 2.5m
IES-2014 When relay opens, I = 10 mA, H = H2
Ans. (d) : In a servo-system, the device used for I = I0 + K(H 2 − H 0 )
providing derivative feedback is known as
10 = 4 + 16 ( H 2 − 2 )
tachogenerator.
6
Transfer function of the tachogenerator is given as- = ( H2 − 2)
T(s) = sKs 16
The block representation of tachogenerator which is 6
used as derivative feedback is shown below: H 2 = + 2 = 2.375
16
Hysteresis zone = (H1–H2)
= 2.5–2.375 = 0.125 m
18. Which of the following is the response of a
s spring-mass-damper with under-damping?
16. A Tachometer has a sensitivity of 5V/1000 rpm.
The Gain constant of the Tachometer is : (a)
(a) 0.48 V/rad/sec (b) 0.048 V/rad/sec
(c) 4.8 V/rad/sec (d) 48 V/rad/sec
IES-2014
Sensitivity (Vg) = 5V/1000 rpm (b)
Vg
Gain constant of tachometer (Kr) =
ω
2π× N
Where, ω =
60 (c)
N = speed in rpm
5 × 60
Gain constant = = 0.048V / rad / sec
2π ×1000
17. A liquid level controller linearly converts a
displacement of 2m to 3m into 4-20 mA control (d)
signal. A relay serves as two position controller
to open and close an inlet valve. Relay closes at
12 mA and opens at 10 mA. The hysteresis
IES-2010
zone is :
Ans. (d) : Damping is a reduction vibration over a
(a) 0.1m (b) 0.125m
period of time.
(c) 0.15m (d) 0.2m
ξ < 1 for underdamped system
IES-2014
ξ = 1 for critical damped system.
Ans. (b) : The controller converts displacement into
control signal linearly, displacement and control signal ξ > 1 for overdamped system.
is related as- Roots for underdamped system is
I = I0 + K ( H − H 0 ) ……………(i) s = −ξωn ± jωn 1 − ξ 2
Where I0 is control signal at displacement H0. Roots lies in the left half of s-plane, hence the response
From equation (i) of the system will be decaying amplitude of oscillations.

19. Which of the following can be used as a The block diagram of pneumatic control system is
tachogenerator in control system? shown below, in which flapper nozzle, error detector
(a) Microsyn (b) DC servomotor and amplifier or pilot relay are major components.
(c) AC servomotor (d) Magnetic amplifier
IES-2009
Ans. (c) :
(i) AC servomotor can be used as a tachogenerator in
control system.
(ii) DC servomotor is used as an actuator to drive a
load. • Advantages of pneumatic control over hydraulic
(iii) Magnetic amplifier is used as a transducer and control are-
also used in nuclear power applications. 1. Normal operating pressure of pneumatic system is
very much lower than that of hydraulic system.
(iv) Microsyn is variable reluctance transducer, and it is
based on the principle of rotating differential 2. Simple in construction and easy to maintain.
transformer. 3. There is no any return pipes are required when air
is used.
20. In case of d.c. servomotor, the back-emf is
4. Relatively inexpensive power systems.
equivalent to an ‘‘electric friction’’ which tends
to : 5. Relatively high power amplification for operating
the final control elements.
(a) improve stability of the motor
6. It is insensitive to temperature changes.
(b) slowly decrease stability of the motor
7. It is explosion proof as well as fire proof.
(c) very rapidly decrease stability of the motor
Some disadvantages of pneumatic system over
(d) have no effect on stability hydraulic systems are-
IES-2008 1. It has slow response of final control elements and
Ans. (a) : In DC servomotor, back emf is equivalent to termination lag.
an electric friction and acts as a damping in field control 2. Their operation gets difficult under freezing
motors which improves stability of motor. conditions.
21. The input to a controller is : 3. Their output power is considerably less than those
(a) sensed signal of hydraulic system.
(b) error signal 4. Lubrication of the rotational parts is difficult.
(c) desired variable value 5. At low velocity the accuracy of pneumatic
(d) signal of fixed amplitude not dependent on actuators is poor
desired variable value. 23. Consider the following statements for a.c. series
IES-2008 motors :
Ans. (b) : The input to a controller is error signal. The 1. The rotor is designed so that its R/X ratio is
basic control loop is shown below- small.
2. dT/d ω < 0 where T and ω are torque and
speed respectively
3. The reference and control voltages should be
in phase quadrature, but their magnitudes
need not be equal.
Which of the statement given above are
22. Consider the following statements for correct?
pneumatic and hydraulic control systems : (a) 1, 2 and 3 (b) 1 and 2
1. The normal operating pressure of (c) 2 and 3 (d) 1 and 3
pneumatic control is very much higher IES-2004
than that of hydraulic control. Ans. (b) : The torque speed characteristic of servo
2. In pneumatic control, external leakage is motor is given as-
permissible to a certain extent, but there
should be no leakage in a hydraulic control
Which of the statements given above is/are
correct?
(a) 1 only (b) 2 only • For linear characteristics (X/R) ratio should be
(c) Both 1 and 2 (d) Neither 1 nor 2 small i.e. R is high with negative slope (dT/d ω)<0
IES-2008 i.e. when angular speed of rotor is increased then
Ans. (c) : The operating pressure of pneumatic control torque is reduced.
is very much higher than that of hydraulic control and • For better angular acceleration, diameter of rotor
also no leakage is permitted in hydraulic system. should be small so it can offer less inertia.

24. A tachometer feedback is used as an inner loop Given that M=1, k=1, f(t)= δ ( t ) , Lets take B = 0
in a position control servo-system. What is the
effect of feedback on the gain of the sub-loop d2x
+ x = δ(t)
incorporating tachometer and on the effective dt 2
time constant of the system? Now, taking Laplace transform, we get-
(a) Both are reduced s2X (s ) + X (s ) = 1
(b) Gain is reduced but the time constant is
increased X ( s ) ( s 2 + 1) = 1
(c) Gain is increased but the time constant is
1
reduced X (s) =
(d) Both are increased. s2 + 1
IES-2004 Taking inverse Laplace transform we get-
Ans. (a) : A tachometer feedback is used as an inner x ( t ) = sin t
loop in a position control servo-system, with the use of
feedback, the gain and the effective time constant both 27. Which one of the following relations holds good
are reduces. for the tachometer shown in the given figure?
25. The mechanical system shown below has its
pole(s) at
(a) V2(s) = skt ω(s) (b) V2(s) = kts2θ(s)

(c) V2(s) = kts2 ω(s) (d) V2(s) = ktsθ(s)
IES-2001
(a) – K/D (b) – D/K Ans. (d) : Mathematical representation of given system
(c) – DK (d) O, – K/D is-
IES-2002 V ( t ) = k d θ ( t )
2 t
Ans. (a) : The mathematical representation of given dt
mechanical system is After taking Laplace transform we get,
dy V2 ( s ) = k t sθ ( s )
D. + k ( y − x ) = 0 ………….(i)
dx 28. Consider the following servomotors:
By taking Laplace transform of equation (i) we get- 1. AC two-phase servometer
DsY ( s ) + K  Y ( s ) − X ( s )  = 0 2. DC servomotor
3. Hydraulic servomotor
Y (s) K K/D 4. Pneumatic servomotor
= =
X ( s ) Ds + K s + K / D The correct sequence of these servomotors in
Pole = s+K/D =0 increasing order of power handling capacity is :
s = -K/D (a) 2, 4, 3, 1 (b) 4, 2, 3, 1
(c) 2, 4, 1, 3 (d) 4, 2, 1, 3
26. Consider the mechanical system shown in the
IES-2000
given figure. If the system is set into motion by
unit impulse force, the equation of the resulting Ans. (c) : The sequence of servomotors in increasing
oscillation will be: order of power handling capacity is given as-
DC servomotor used in low power applications where as

(a) x(t) = sint (b) x(t) = 2 sin t
hydraulic servomotor used in high power applications.
1 29. Match List-I (Functional components) with
(c) x(t) = sin2t (d) x(t) = sin 2t
2 List-II (Devices) and select the correct answer.
A. Error detector 1. Three-phase FHP
Ans. (a) : The mathematical representation of given
induction motor
mechanical system is-
B. Servomotor 2. A pair of synchronous
d2x dx
M. 2 + B. + Kx = f ( t ) transmitter and control
dt dt transformer
C. Amplifier 3. Tachogenerator d 2 y(t) dy(t)
D. Feedback 4. Armature controlled FHP a2 + a1 + a0 y(t) = x(t)?
dt 2 dt
d.c. motor
(a) 1 and 2 (b) 1 and 3
5. Amplidyne
(c) 2 and 4 (d) 1, 2 and 4
Codes :
IES-1999
A B C D
(a) 2 4 1 5 Ans. (a) : The differential equation
2
(b) 4 2 5 3 d y(t) dy(t)
a2 + a1 + a 0 y(t) = x(t) are second order
(c) 2 4 5 3 dt 2 dt
(d) 1 2 3 5 system so we should require two storing elements, i.e. L
IES-2000 and C and resistance (R) in electrical circuit and K, B
Ans. (c) : The correct match of functional components and M in mechanical circuit.
with the corresponding devices are- Here, block diagram of (1) and (2) gives the second
Error detector- A pair of synchronous transmitter and order differential equation.
control transformer. 32. When a human being tries to approach an
Servomotor-Armature controlled FHP dc motor object, his brain acts as:
Amplifier- Amplidyne (a) an error measuring device
Feedback-Tachogenerator (b) a controller
30. Consider the following statements relating to (c) an actuator
synchros : (d) an amplifier
1. The rotor of the control transformer is IES-1999
either disc shaped Ans. (b) : When a human being tries to approach an
2. The rotor of the transmitter is so object the brain acts as a controller. Brain takes the
constructed as to have a low magnetic signal (error signal) and gives the respective command
reluctance. to execute.
3. Transmitter and control transformer pair 33. In hydraulic controllers, the advantage of
is used as an error detector. flapper valve over piston valve is the :
Which of these statements are correct? (a) High sensitivity
(a) 1, 2 and 3 (b) 1 and 2 (b) Better rigidity
(c) 2 and 3 (d) 1 and 3
(c) Higher hydraulic power control
IES-1999
(d) Control action being immune to friction and
Ans. (c) : The rotor of the transmitter is so constructed dirt.
as to have a low magnetic reluctance, by providing a IES-1998
uniform air gap.
Transmitter and control transformer pair is used as an Ans. (b) : In hydraulic controllers, the advantage of
error detector. flapper valve over piston valve is having the better
rigidity.
The rotor of the control transformer is not in disc shape,
it is made cylindrical so that air gap is uniform. 34. In the field-controlled motor, the entire
31. Consider the following systems: damping comes from :
(a) The armature resistance
(b) The back emf
1. (c) The motor friction and load
(d) Field resistance
IES-1998
Ans. (c) : In the field controlled motor, the entire
2. damping comes from the motor friction and load, it is
equivalent to electric friction, which improves stability
of motor.
35. Which of the following rotors are used in a
3. two-phase ac servomotor?
1. Solid iron motor
2. Squirrel cage rotor
3. Drag cup rotor
4. Select the correct answer using the codes given
below:
(a) 1, 2and 3 (b) 1, and 2
Which of these systems can be modelled by the (c) 2 and 3 (d) 1 and 3
differential equation, IES-1998
Ans. (c) : Following type of rotors are used in 2-φ ac Ans. (d) : The block diagram of a hybrid servo system.
servomotor -
(i) Squirrel cage rotor
(ii) Drag cup rotor
for accurate positioning servo motor is required. This is
possible when inertia of rotor is low solid iron motor
has larger value of inertia. Error is amplified by using amplifier then this amplified
36. Which of the following components can be used signal fed to dc servomotor which change the angular
as a rotating amplifier in a control system? position of output then demodulate the signal and
finally provide this signal to loads, as shown in the
1. An amplidyne
block diagram above.
2. A separately excited dc generator
3. A self-excited dc generator 39. In case of synchro error detector, the electrical
zero position of control transformer is obtained
4. A synchro when angular displacement between rotors is :
Select the correct answer using the codes given (a) Zero (b) 45°
below:
(c) 90° (d) 180°
Codes:
IES-1995
(a) 3 and 4 (b) 1 and 2
(c) 1, 2 and 3 (d) 1, 2, 3 and 4 Ans. (c) : In case of synchro error detector electrical
zero is obtained when induced voltage in the rotor of
IES-1997
control transformer is zero. The expression for induced
Ans. (b) : The following components can be used as a voltage is given by
rotating amplifier in a control system-
e ( t ) = KVr cos φ sin ωc t
• An amplidyne
• A separately excited dc generator φ = angular displacement between rotors
37. Which of the following can work as error for e(t) =0, φ must be 900. Hence, angular displacement
detecting devices? between rotor is 900.
1. A pair of potentiometers 40. Consider the following for a variable
2. A pair of synchros reluctance stepper motor used in system :
3. A differential transformer 1. The stator torque acting on the rotor is a
4. A Metadyne function of angular misalignment between
5. A control transformer stator and rotor teeth.
(a) 1, 2 and 5 (b) 2, 3, 4 and 5 2. There are two positions of zero torque :
(c) 1, 3, 4 and 5 (d) 1, 2, 3 and 4 θ = 0°, 180°/T (T = number of rotor teeth)
IES-1996 3. Both the torque zero positions are stable
Ans. (a) : A pair of potentiometer, a pair of synchros 4. As the stator is excited, the rotor is pulled into
and a control transformer can work as an error detecting the nearest minimum reluctance position.
devices. Of these statements.
Differential transformer used as a measuring device for (a) 2, 3 and 4 are correct
force, pressure and acceleration. (b) 1, 2 and 3 are correct
Metadyne is used to generate constant current, and used (c) 1, 2 and 4 are correct
as power amplifier. (d) 1, 3 are 4 are correct
38. The system represented by the block diagram IES-1995
in the following figure is a hybrid servo system. Ans. (c) : The graph between torque and angular
position is given as-
The components labelled 1, 2, 3 and 4

respectively
(a) amplifier, demodulator, dc servomotor and 1800
Torque become zero at θ = 00 and θ = ,
load T
(b) Demodulator, amplifier, dc servomotor and Where T = Number of rotor teeth.
load At θ = 00 , slope is negative, it is a stable position i.e. as
(c) Demodulator, dc servomotor, amplifier and slightly disturbance in either of direction from this point
load
1800
(d) Amplifier, dc servomotor, demodulator and bring back to original position. Whereas at θ = , it
load T
IES-1996 is an unstable position with positive slope.
41. Which one of the following is the best Ans. (d) : The synchro is an electromagnetic transducer,
controller, to use for an electrically heated amplidyne is a power amplifier, servomotor work as an
temperature controlled liquid heater? actuator and RC network is used in compensator, to
(a) Two position controller compensate phase of the output of control system.
(b) Proportional position controller 46. The most commonly used input signal (s) in
(c) Floating controller control system is/are
(d) Single-position controller (a) Step function
IES-1994 (b) Ramp or velocity function
Ans. (a) : Two position controller is the best controller (c) Accelerating function
to use for an electrically heated temperature controlled (d) All of the above
liquid heater. Nagaland PSC (Degree) 2018, Paper-II
42. The ac motor used in servo applications is a Ans. (a) : The most commonly used input signal in
(a) Single-phase induction motor control system is step function.
(b) 2–φ induction motor In step function, output always follows input.
(c) 3–φ induction motor Unit step signal:-
(d) Synchronous motor.
IES-1993
Ans. (b) : 2 − φ induction motor is used in servo
application and low power rating devices. The phase
angle between two starter winding is 900 and the
angular phase difference between each phase winding
of a three-phase induction motor is 120º.
47. _______ is defined as the time delay that a
43. In position control system, the device used for signal component of frequency ω undergoes as
providing rate feedback voltage is called- it passes from the input to output of the system.
(a) Potentiometer (a) Phase delay
(b) Synchro transmitter (b) Group delay
(c) Tacho generator (c) Frequency deviation
(d) None (d) Latency
IES-1993 ISRO Scientist Engg.-2011
Ans. (c) : In position control system, tachogenerator is
Ans. (a) : Phase delay of linear time invariant system is
used for providing rate feedback voltage is called Tacho
generator, provides a voltage magnitude is directly defined as the time delay that signal component of
proportional to speed and also it can be used to increase frequency ω expression of each component of
the damping of the system. sinusoidal input signal.
44. A synchro transmitter receiver unit is a 48. A first order instrument is characterised by
(a) 2-φ ac device (a) Time constant only
(b) 3-φ ac device (b) Static sensitivity and time constant
(c) DC device (c) Static sensitivity only
(d) Single phase ac device (d) Damping coefficient and static sensitivity
IES-1993 RRB SSE 01.09.2015 Shit-I
Ans. (d) : A synchro transmitter receiver unit is a 1-φ ac Ans. (b) : First order of instrument is characterized by
device. There are basically four types of synchros static sensitivity and time constant.
namely as transmitter, receiver, transformers and 49. Phase of the transfer function of the following
differentiators. circuit is :
answer, using the codes given below the lists :
List-I List-II
A. Synchro 1. Amplifier
B. Amplidyne 2. Actuator
C. Servo motor 3. Compensator (a) tan −1 (1/ ωRC ) (b) tan −1 ( ωRC )
D. RC network 4. Transducer (c) tan −1 ( RC / ω) (d) tan −1 ( ω / RC )
Codes:
A B C D ISRO Scientist December, 2017
(a) 1 2 3 4 Ans. (a) : Given circuit in s-domain-
(b) 4 3 2 1
(c) 3 2 4 1
(d) 4 1 2 3
IES-1994
By voltage division rule- (ii) Block Diagram & Signal Flow
R
V0 = Vi Graph
R + 1/ Cs
1. For the signal flow graph shown in the figure,
V (s ) R R R
H (s) = 0 = = = C(s)
Vi ( s ) R +1/Cs R + 1 R−
j the value of is
R(s)
jωC ωC
Then phase (θ) -
 1/ ωC 
θ = 0º – tan–1  − 
 R 
 1 
θ = tan −1  
 ωRC  G1G 2 G 3 G 4
(a)
50. For proper working of a damper, the time 1 − G1G 2 H1 − G 3 G 4 H 2 – G 2 G 3 H 3
constant should be + G1G 2 G 3 G 4 H1H 2
(a) large G1G 2 G 3 G 4
(b) equal to signal time-period (b)
1 + G1G 2 H1 + G 3 G 4 H 2 + G 2 G 3 H 3
(c) zero
(d) less than 5 times the signal time period + G1G 2 G 3 G 4 H1H 2
TNPSC AE-2013 1
(c)
Ans. (a) : A shock absorber or damper is a mechanical 1 + G1G 2 H1 + G 3 G 4 H 2 + G 2 G 3 H 3
or hydraulic device designed to absorb and damp shock + G1G 2 G 3 G 4 H1H 2
impulse. Hence time constant should be large.
1
51. There are 2 systems: (d)
a. An automatic washing machine 1 − G G H
1 l 1 − G 3 4 H 2 – G 2 G 3 H3
G
b. An automatic intensity adjustable light bulb + G1G 2 G 3 G 4 H1H 2
Which of these systems will be more sensitive to BPSC Asst. Prof. - 12.04.2022
the variation in system's gain? GATE-2015, Set-II
(a) Data is insufficient Ans. (b)
(b) Automatic intensity adjustable light bulb
(c) Both will be equally sensitive
(d) Automatic washing machine
Ans. (d) : Automatic intensity adjustable light bulb is
an example of a closed loop system that controls the Forward path ( P1 = 1×G1×G2×1×G3×G4 =G1G2G3G4)
light intensity automatically as required depending on Loop gains L1 = – G1G2H1, L2= – G3G4H2
the daylight condition with the help of feedback sensors L3= – G2G3H3
connected to it. Two non touching loops-
Hence on automatic washing machine is more sensitive L1L 2 = G1G 2 G 3G 4 H1H 2
to the variation in system gain as compared to an
automatic intensity adjustable light bulb. ∆ = 1 + ( G1G 2 H1 + G 3 G 4 H 2 + G 2 G 3 H 3 ) + G1G 2 G 3 G 4 H1H 2
52. In force current analogy, electrical capacitance ∆1 = 1 − 0 = 1
is analogous to: By Mason’s gain formula-
(a) Voltage (b) Force C ( s ) P1∆1
(c) Compliance (d) Mass =
R (s ) ∆
LMRC AM- 16.07.2021
Ans. (d) : In force current analogy, electrical G1G 2 G 3 G 4
=
capacitance is analogous to mass. 1 + G1G 2 H1 + G 3 G 4 H 2 + G 2 G 3 H 3 + G1G 2 G 3 G 4 H1H 2
F↔I 2. For the signal flow graph shown in the figure,
Mass (M) ↔capacitance (C) determine the overall transmittance relating C
and R.
1
Spring constant (K) ↔
L
1
Damper (B) ↔
R

G1 + G 2 G1 + G 2 5. The block diagram of a closed-loop control
(a) (b) system is shown in the figure. R(s), Y(s), and
1 − G1H1 + G 2 H1 1 + G1H1 − G 2 H1
D(s) are the Laplace transforms of the time-
G1 + G 2 G1G 2 domain signals r(t), y(t), and d(t) respectively.
(c) (d)
1 + G1H1 + G 2 H1 1 + G1H1 + G 2 H1 Let the error signal be defined as e(t) = r(t) –
UPPSC Poly. Tech. Lect.-22.03.2022, Paper -I y(t). Assuming the reference input r(t) = 0 for
MPSC HOD Govt. Poly. -2013 all, the steady-state error e(∞), due to a unit
Ans: (c) From block diagram reduction, G1 and G2 are step disturbance d(t), is ______ (rounded off to
in parallel, So G = G1 + G2 two decimal places).
C G1 + G 2
=
R 1 + ( G1 + G 2 )( H 1 ) GATE-2022
Sol.
C G1 + G 2
=
R 1 + G1H1 + G 2 H1
3. For the signal flow graph shown in figure, the
number of forward points and number of loops
are respectively
Given that,
(a) 3 and 4 (b) 4 and 3 e( t ) = r (t ) − y( t ) , r(t) = 0
(c) 4 each (d) 3 each R (s) = 0
Ans. (a) : Number of forward path = 3 1
[abcdef, abdef, abcf] E (s ) −s ( s + 10 )
=
Number of individual loop = 4 [ded, bdefb, cfbc, bdefb D ( s ) 1 + 10
] s ( s + 10 )
E (s ) −1
=
D ( s ) s ( s + 10 ) + 10
4. The response c(t) of a system to an input r(t) is E ( s ) = −1

given by the following differential equation: D ( s ) s + 10s + 10
2
ess = limsE ( s )
2
d c(t) dc(t)
+6 + 5c(t) = 4r(t) s →0
dt 2 dt
−D ( s )
The transfer function of the system is given by ess = lims × 2
(assume zero initial conditions) s →0 s + 10s + 10
4 5 D(s) → unit step disturbance
(a) G(s) = 2 (b) G(s) = 2
s + 6s + 5 s + 6s + 4 −1
ess =
6s s+6 10
(c) G(s) = 2 (d) G(s) = 2 ess = –0.1
s + 6s + 5 s + 6s + 5
BPSC Asst. Prof. - 12.04.2022 6. Consider the following block diagram in the
figure.
Ans. (a) : Given, differential equation-
d 2C ( t ) dC ( t )
+6 + 5C ( t ) = 4r ( t )
dt 2 dt
So, s 2 C ( s ) + 6sC ( s ) + 5C ( s ) = 4R ( s ) b
C(s)
C ( s ) s 2 + 6s + 5 = 4R ( s ) The transfer function is
R(s)
C (s) 4 G1G 2
= 2 (a) (b) G1G2+G1+1
R ( s ) s + 6s + 5 1 + G1G 2
G1 G −3
(c) G1G2+G2+1 (d) Ans. (c) : Closed loop gain ( T ) = =
1 + G1G 2 1 − GH 1 + 3 × 0.5
RPSC ACF & FRO 23.02.2021 −3 −6
= =
NIELIT Scientist -2017 2.5 5
Mizoram PSC Jr. Grade-2015, Paper-II 9.
GATE-2014, Set-III
Ans. (c) :
Calculate the transfer function of the given

system.
Converting the block diagram into signal flow graph- GH G
(a) (b)
(1 − GH ) (1 − GH )
G GH
(c) (d)
P1=G1G2, P2=1×G2=G2, P3 = 1×1=1 (1 + GH ) (1 + GH )
There are No loop gain paths LMRC AM- 16.07.2021
There are No two non touching loops
Ans. (b) : Transfer function of positive feedback
∴∆ = 1 − 0 = 1
G
∆1 = 1, ∆ 2 = 1, ∆ 3 = 1 system (T) = .
( GH )
1 −
C ( s ) ( G1G 2 × 1) + ( G 2 ×1) + (1 ×1)
∴ = 10. The block diagram of a feedback system is
R (s) 1− 0 shown in the figure.
= G1G 2 + G 2 + 1
7. The unit impulse response of a certain system is
found to be e–8t. Its transfer function is .
1 1
(a) (b) 2
s −8 s +8
1 1 Y(s)
(c) 2 (d) The transfer function of the system is
s +4 s +8 X(s)
G + G 2 + G1G 2 H G1 + G 2
APPSC Poly. Lect. 14.03.2020 (a) 1 (b)
BARC Scientific Officer-2016 1 + G1H 1 + G1H + G 2 H
NPCIL-2015 G + G2 G + G 2 + G1G 2 H
(c) 1 (d) 1
Ans. (d) : As we know 1 + G1H 1 + G1H + G 2 H
Transfer function = L{Impulse response} GATE-2021
Given, Impulse response (IR) = e–8t Ans. (c) : Signal flow graph
So,
T.F = L{e–8t}
1 1
= Q L{ e–at } =
s+8 s+a
8.
Forward path
g1 = G 1
g2 = G2
Individual loop = –G1H
Calculate the closed loop gain of the given G1 + G 2 G + G2
Transfer function = = 1
system. 1 − ( −G1H ) 1 + G1H
11 11
(a) (b) − 11. Find out the sensitivity of a closed loop system
5 5 with respect to H, the feedback sensor is
6 6
(c) − (d)
5 5
LMRC AM- 16.07.2021
TNTRB AE-2017
(a) Zero (b) One V2 ( s )
13. The transfer function of the circuit
1 -GH V1 ( s )
(c) (d)
1+ GH 1+ GH shown below is
Ans. (d) :
0.5s + 1 3s + 6
From the above circuit- (a) (b)
s +1 s+2
G (s) s+2 s +1
T(s) = –––––(i) (c) (d)
1 + G (s) H (s) s +1 s+2
sensitivity due to the variation in H(s) LMRC AM-16.07.2021
∂T(s)/T(s) ∂T ( s ) H ( s )
STH = = × Ans. (d) : Draw circuit in s-domain
∂H(s)/H(s) ∂H(s) T ( s )
from equation (i)
∂  G (s )  H (s )
STH =  .
∂H ( s )  1 + G ( s ) H ( s )  G (s )
1 + G (s) H (s) 10000 104
Z1 = =
s s
 G ( s )  H ( s ) 1 + G ( s ) H ( s ) 
2
=− × 104
G (s) Z2 = 104 +
1 + G ( s ) H ( s ) 
2
s
G (s ) H (s ) Z2
STH = − V2(s) = V1(s) .
1 + G (s ) H (s ) Z1 + Z2
12. Find out overall transmittance by signal flow V2 (s) 104 + 104 / s
= 4
graph technique in given figure V1 (s) 10 104
+ 104 +
s s
V2 (s) 1 + 1/ s
=
V1 (s) 1 + 2 / s
V2 (s) s + 1
=
V1 (s) s + 2
(a) ab+c (b) abc+c
ab ab 14.
In a closed loop control system
(c) (d) (a) Control action is independent of output
1- ab 1- bc (b) Output is independent of input
RPSC ACF & FRO 23.02.2021 (c) There is no feedback
Ans. (d) : By using SFG technique (d) Control action is dependent on output
DMRC AM S&T-2020
Ans. (d) : Closed loop control system-the closed loop
system is given below.
The gain of the forward path's
P1 = ab ∆1 = 1– 0
Individual loop gain
L1 = bc
So, ∆ = 1– bc So, in closed loop system in which the control action
By using Mason's gain formula- depend on the output this type of system have a
P1∆1 ab tendency to oscillate.
T.F. = =
∆ 1 − bc Ex. Speed control of one motor.

15. Find the overall transfer function for the (c) Number of poles = 1, and number of zeros =
following system. 3
(d) Number of poles = 3, and number of zeros =
2
NLC GET -24.11.2020
s +1
T (s) =
Y ( s ) 2s + 4 Y (s ) 2s + 4 s (s2 + 4)
(a) = 2 (b) = 2
R (s) s R ( s ) s + 2s + 4 Number of poles
Y (s ) 4s + 2 Y (s ) 2s + 4 = Highest power of s in denominator = 3
(c) = 2 (d) = 2 Number of zeros = highest power of s in numerator = 1
R ( s ) s + 4s + 2 R ( s ) s + 4s + 2
18. Find transfer function G(s) = C ( s ) R ( s ) for
NLC GET -24.11.2020
the differential equation.
Ans. (b) : Given Block diagram can be simplified as -
d 3c d 2c dc d 2r dr
+3 + 7 + 5c = + 4 + 3r
dt 3 dt 2 dt dt 2 dt
s2 + 3
(a)
 4  1   2s + 4  3s 2 + 7s + 5
Y (s )  2 +    2 
 s  s 
= 
s 
= s 2 + 4s + 3
R (s)  4  
1  +4
2s (b)
1 +  2 +   (1) 1 +  2  3s 2 + 4s 2 + 7s + 5
 s  s   s 
Y (s ) 2s + 4 s2 + 2
= (c) 3
R ( s ) s 2 + 2s + 4 s + 2s 2 + 6s + 5
16. Determine the location of poles and zeros of the s 2 + 4s + 3
transfer function: (d) 3
s + 3s 2 + 7s + 5
Y (s) =
( s + 2 )( s + 4 ) APPSC Poly. Lect. 15.03.2020
s ( s + 1)( s + 3 ) Ans. (d) Given, differential equation is-
Poles: s = 0, − 1, −3 Poles: s = − 2, −4 3
d c
2
d c dc
2
d r dr
(a) (b) + 3 + 7 + 5c = + 4 + 3r ……..(i)
Zeros : s = −2, −4 Zeros : s = 0, −1, −3 dt
3
dt
2
dt dt
2
dt
Poles: s = 2,4 Poles: s = 0, 1, 3 By Laplace transform of equation (i) we get-
(c) (d)
Zeros : s = 0, 1, 3 Zeros : s = 2, 4 s3C(s)+3s2C(s)+ 7sC(s)+5C(s)= s2R(s)+4sR(s)+3R(s)
NLC GET -24.11.2020 ( s3 + 3s 2 + 7s + 5 ) C ( s ) = ( s 2 + 4s + 3) R ( s )
Ans. (a) : Given,
C (s)
( s + 2 )( s + 4 ) Transfer function G ( s ) =
Y (s) = R (s )
s ( s + 1)( s + 3 )
Poles are the roots of denominator of given transfer C (s) s 2 + 4s + 3
= 3
function by making denominator = 0 R ( s ) s + 3s 2 + 7s + 5
s ( s + 1)( s + 3) = 0
19.
So, poles: s = 0, –1,–3
Zeros are the roots of numerator of given transfer
function by making numerator = 0
( s + 2 )( s + 4 ) = 0
So, zeros: s =–2, –4
The transfer function of the above feedback
17. Determine the number of poles and zeros of the
control system is
s +1
transfer function (a) T=H/G+GH (b) T = G/1+GH
s (s2 + 4 ) (c) T= H/H+GH (d) T=G/G+GH
(a) Number of poles = 2, and number of zeros = DMRC AM S&T-2020
3 C (s) G
(b) Number of poles = 3, and number of zeros = Ans. (b) : Transfer function = =
1 R ()
s 1 + GH

20. The open loop dc gain of the unity negative 1 Cs
feedback system with closed-loop transfer Ans. (d) : Vo = Vin
R + 1 Cs
s+4
function 2 is
s + 7s + 13
4 4
(a) (b)
13 9
(c) 4 (d) 13
ISRO Scientist-May 2017
Vo 1
NIELIT Scientist -2017 =
TRB Poly. Lect. 2012 Vin 1 + sRC
Ans. (b) : 23. Negative feedback in a closed-loop control
G (s) system does not
Closed loop transfer function = , for unity (a) reduce the overall gain
1 + G (s) H (s)
(b) reduce bandwidth
negative feedback system open loop transfer function (c) improve disturbance rejection
(G(s) H(s)) can be found by subtracting the numerator
term from the denominator term. (d) reduce sensitivity to parameter variation
Given, APGENCO AE- 23.04.2017
Nagaland PSC CTSE-2015, Paper-II
s+4
Closed loop transfer function= 2 GATE-2015, Set-I
s + 7s + 13 Ans. (b) : Effects of negative feedback in a control
Num system are-
Open loop transfer function =
Den − Num 1. Negative feedback reduces gain.
s+4  G (s) 
Open loop transfer function = 2
s + 7s + 13 − s − 4 gain = 
 1 + G (s) H (s) 
s+4
= 2 2. Negative feedback reduces distortion, noise,
s + 6s + 9 sensitivity to parameter variation as well as
 s+4  improves bandwidth.
Open loop dc gain =  2 
 s + 6s + 9 at s =0 3. Gain × Bandwidth = constant. So, gain reduces and
Bandwidth increases.
4
= 24. The closed-loop transfer function C(s)/R(s) of
9 the system represented by the block diagram
21. Signal flow graph is used to find- in the figure is:
(a) Stability of the system
(b) Controllability of the system
(c) Transfer function of the system
(d) Poles of the system
Mizoram PSC IOLM, 2018 Paper-II
Nagaland PSC CTSE- 2015, Paper-II 1 1
GATE- 1995 (a) (b)
(s + 1) 2 (s + 1)
Ans. (c) : Signal flow graph can be used to represent (c) s + 1 (d) 1
linear system only. Signal flow graph (SFG) is a graph IES-2018
which represents a set of equations. It consists of nodes
Nagaland PSC CTSE (Degree) - 2017, Paper-II
and branches such that each branch of signal flow graph
GATE - 2010
having an arrow which represents the flow of signal. It
used for transfer function of the system. Ans. (b) :
22. The transfer function of a first order RC
lowpass filter is:
1
(a) (b) R + sC
sRC
1 There are only one forward path i.e. P1 = ABC
(c) 1 + sRC (d)
(1 + sRC ) Forward path gain P1 =
1
, ∆ =1
DFCCIL Executive S&T-17.04.2016, Shift-II (1 + s ) 1
UPPCL AE-05.11.2019 Individual loops L1 = ABCDA
( −1) =  −
1 1  Ans. (c) : The effects which occur in negative feedback
L1 = , L 2 = ABDA
(1 + s )  s +1
system are-
1. Reduction in gain
 1   1  2. Increase in bandwidth
L 2 =  −  ( −1) =  , ∆ = 1 − ( L1 + L 2 )
 ( )
1 + s  s +1  3. Reduction in noise
Increase in distortion is not caused by negative
By using Mason’s gain formula feedback.
C ( s ) P1∆1 Distortion refers to the error in the open loop system
Transfer function = =
R (s ) ∆ and it has many oscillations in the output and is reduced
in case of negative feedback.
C (s) 1/ ( s + 1) 1 27. The sensitivity of a closed-loop system gain
= =
R (s)  −1 1  1+ s changes and load disturbances depends upon
1−  +  (a) Forward gain (b) Loop gain
 s +1 s +1
(c) Frequency (d) All of these
25. The open-loop transfer function of a unity
feedback control system is
Ans. (d) : Sensitivity is defined as the change in the
1
G(s) = output with respect to the change in the parameter
(s + 2) 2 variations and change in input and load disturbance
The closed loop transfer function poles are depends upon frequency, loop gain and forward gain.
located at : 28. Static error coefficients are used as a measure
(a) – 2, – 2 (b) – 2, – 1 of the effectiveness of closed-loop systems for
(c) – 2, + 2 (d) – 2 ± j1 specified
IES-2014, 2013 (a) Position input signal
ISRO Scientist Engg.-2009 (b) Velocity input signal
IES-2000 (c) Acceleration input signal
(d) All of these
1
G(s) = Ans. (d) : Static error coefficients are used as a measure
(s + 2)2 of the effectiveness of closed loop system for specified
For unity feedback control system. acceleration, velocity and position of input signal.
29. Two RC circuits each having transfer function
 1 
1 + sτ  are connected in cascade. The over
Closed loop transfer function, all transfer function of the combination is :
C(s) G(s)
= 1 1
R(s) 1+ G(s) (a) (b)
1/(s + 2) 2
(1 + sτ )
2
(1 + 3sτ + s2 τ2 )
=
1+1/(s + 2) 2 2 1
(c) (d)
1 + sτ 1 + (1 + sτ )
2
C(s) 1
=
R(s) s 2 + 4s + 5 Nagaland PSC CTSE (Degree)-2016, Paper-II
Poles of closed loop transfer function 1
= roots of s2+ 4s+5 Ans. (a) : Each RC circuit having TF = , if they
1 + sτ
Then, s 2 + 4s + 5 = 0 are cascaded, overall TF will be
−4 ± 16 − 20 −4 ± 2 j 1 1 1
= = = × =
2 2 1 + sτ 1 + sτ (1 + sτ ) 2
So poles are at – 2 ± j. 30. Feedback control system are basically
26. Which one of the following effects in the system (a) Low pass filters (b) High pass filters
is not caused by negative feedback? (c) Band pass filters (d) Band stop filters
(a) Reduction in gain Nagaland PSC CTSE (Degree)-2016, Paper-II
(b) Increase in bandwidth Ans. (a) : Feedback control system are basically a low-
(c) Increase in distortion pass filter.
(d) Reduction in noise 31. The effect of negative feedback on distortion
RPSC VP/Suptd. ITI 05.11.2019 and bandwidth is
Mizoram PSC IOLM - 2018, Paper -II (a) Both distortion and bandwidth get decreased
(b) Both distortion and bandwidth get increased Ans.(a): Given that
(c) Distortion is reduced and bandwidth is A + kA 2
increased T= 1
A 3 + kA 4
(d) Distortion is increased and bandwidth is
decreased Sensitivity of transfer function with respect to k .
RPSC LECTURER-10.01.2016 ∂T
%changein T T
Ans. (c) : Distortion is reduced and bandwidth is STk = =
% changein k ∂k
increased. In negative feedback, the feedback signal, is k
out of phase with the input signal and thus opposes it. ∂ T k
Negative feedback reduces gain of the amplifier. It also STk =
reduces distortion, noise and instability. This feedback ∂k T
increases bandwidth. ∂  A + kA 2  k
=  1 ×
32. A system is described by the transfer function ∂k  A 3 + kA 4   A1 + kA 2 
100  
G(S)= . The dc gain of the system  A3 + kA 4 
(s + 1)(s + 100)  A ( A + kA ) − A ( A + kA )  ( A + kA ) k
is . = 2 3 4 4 1 2
 3 4
(a) 0.25 (b) 0.5  ( A3 + kA 4 ) 2

 ( A 1 + kA 2)
(c) 1 (d) ∞
Mizoram PSC IOLM -2018, Paper II =  A 2 A 3 + kA 2 A 4 − A 4 A1 − kA 2 A 4  k
 
100  ( 3
A + kA 4)  ( 1 kA 2 )
A +
Ans. (c) : G(S)=
(s + 1)(s + 100) k ( A 2 A 3 − A 4 A1 )
STk =
For DC gain put s = 0 ( A3 + kA 4 ) ( A1 + kA 2 )
100 100 36. The total number of feedback loops of the
=
( 0 + 1)( 0 + 100 ) 100 signal flow graph is, where R is input and C is
output.
DC gain = 1
33. In second order system, which among the
following remains independent of gain (k) ?
(a) Open loop poles (b) Closed loop poles
(c) Both (a) and (b) (d) None of these
k.G(s)
Ans. (c) : We know that T(s) =
1 + G(s)H(s)
zero G(s) = 0
poles 1 + G(s).H(s) = 0
poles and zeros both are independent from K. (a) 3 (b) 4
34. By using feedback in control systems, the (c) 5 (d) 6
sensitivity to parameter variation is improved. ISRO Scientist Engg. -2020
This is achieved at rate the cost of Ans. (c) : Feedback loop is also known as self loop or
(a) Stability individual loop.
(b) Loss of system gain Self loop:- It is a path which originates and terminates
(c) Transient response on the same node.
(d) Reliability
Ans. (a) : A feedback can either make a system stable
or unstable. By using feedback in control system the
sensitivity increased. It always reduce the noise gain.
35. A sensitivity of transfer function
T=(A1+kA2)/(A3+kA4) with respect to
parameter k is given by
(a) k(A2A3–A1A4)/((A3+kA4)(A1+kA2))
(b) (A2A3–A1A4)/((A3+kA4)2) Feedback loop :-
L1 = 9×10 L3 = 6×7 L5 = 4×5×7
(c) k(A2A3–A1A4)/((A3+kA4) ) 2
L2 = 13 L4 = 12
(d) (A2A3–A1A4)/((A3+kA4)(A1+kA2))
Hence, there are 5 feedback loop.
37. Feedback control systems are the equivalent transfer function is :
(a) insensitive to both forward and feedback path s3 + 5s 2 + 6s s 3 + 5s 2 + 6s
parameter changes (a) 3 (b)
s + 7s 2 + 12s + 3 s 3 + 5s 2 + 4s − 3
(b) less sensitive to feedback path parameter changes
than to forward–path parameter changes s 2 + 5s + 4 s3 + 5s + 4
(c) 3 (d) 3
(c) less sensitive to forward–path parameter s + 7s + 12s + 3
2
s + 5s 2 + 4s − 3
changes than to feedback path parameter ISRO Scientist Engg.-2012
changes Ans. (c) :
(d) equally sensitive to forward and feedback
path parameter changes
TNPSC AE - 2018
Ans. (c) : Feedback control systems are less sensitive to
forward–path parameter changes than to feedback path
parameter changes.
38. For the network shown in the figure Vi(t) is the From block diagram
input and i(t) is the output. The transfer s +1 s+3
G(s) = , H(s) =
I(s) s(s + 2) s +4
function of the network is
Vi (s) G (s)
T.F. = (Q negative feed back)
1 + G (s) H (s)
s +1
s(s + 2)
=
1+
( s + 1) × ( s + 3)
C C s (s + 2) (s + 4)
(a) (b)
RCs + LCs + 1
2
LCs + RCs + 1
2
=
( s + 4 )( s + 1)
(c)
Cs
(d)
Cs (s 2
+ 2s ) ( s + 4 ) + ( s + 1)( s + 3)
RCs 2 + LCs + 1 LCs 2 + RCs + 1
ISRO Scientist Engg. 2009 s 2 + 5s + 4
T.F. =
Ans. (d) : The circuit transform into s-domain s3 + 7s 2 + 12s + 3
40. The signal flow diagram for a certain feedback
control system is shown in figure
a9 a8
a1 a2 a3 a7
x1 x2 x3 x4 a4 x5
apply KVL
a5
1
Vi(s) = I(s)R + I(s)sL + I(s)
Cs a6
 1  Now consider the following set of equations for
Vi(s) = I(s)  R + sL +  the nodes
 Cs  1. x2 = a1x1 + a9x3
I(s) 1 2. x3 = a2x2 + a8x4
or =
Vi (s) R + sL + 1 3. x4 = a3x3 + a5x2
Cs 4. x5= a4x4 + a6x2
I(s) Cs Which of the following are correct?
= (a) 1, 2 and 3 (b) 1, 3 and 4
Vi (s) s 2 LC + sRC + 1
(c) 2, 3and 4 (d) 1, 2 and 4
39. For a negative feedback system shown in Ans.(d): An output node is a node that has only one or
figure, more incoming branches.
So, here to write the equation all the incoming branches
at the node are considered.
At node x2
x2 = a1x1 + a9x3
At node x3 Ans. (b) : In the zero-order hold system method, the
continuous signal is reconstructed from its samples by
holding the given sample for an interval until the next
sample is received.
x3 = a8x4 + a2x2
At node x4
x4 = a7x4 + a6x2 + a3x3 x(t) = δ(t)

At node x5 Take Laplace transform
X(s) = 1
y(t) = u(t) – u(t – T)
Take Laplace transform
x5 = a6x2 + a4x4 − Ts
41. What is the transfer function of the network Y(s) = 1 − e
given below? s s
(1 − e −sT )
Hence, Y(s) =
s
44. What is the overall transfer function of the
block diagram shown in the figure ?
(a) (a+1)/(2s+1) (b) 1/(1+s)

(c) 1/(2s+1) (d) 1/(s2+2s+1)
Ans. (b) : The circuit transformed into s-domain
G1G 2 + G 2 G 3 G1G 3 + G 2 G 3
(a) (b)
1 + G 2 H1 1 + G 3 H1
G1G3 + G 2 G 3
(c) G1G 2 + G 2 G 3 (d)
apply voltage division rule- 1 + G 2G3 H1
 1 Mizoram PSC IOLM -2018, Paper II
1 +  Ans. (a) : The given block diagram representation can
V2 ( s ) = V1 (s) 
s
 1  be reduced to –
 1 + + s + 1
 s 
 s + 1 
 
V2 ( s ) = V1 (s) 2  s 
 s + 2s + 1  Or
 
 s 
V2 (s) ( s + 1)
=
Vl (s) ( s + 1)2
V2 (s) 1
=
V1 (s) s + 1 Hence overall transfer function will be-
42. The most inexpensive switch is………..switch C G G + G 2G 3
T.F. = = 1 2
(a) Electronic (b) Mechanical R 1 + G 2 H1
(c) Electromechanical (d) None of the above
Nagaland PSC (CTSE) Diploma-2017, Paper II 45. The main purpose of feedback in a control
Ans. (a) : The most inexpensive switch is Electronic system is
switch because it has high switching process. (a) To have a reduced time constant
(b) To make the system more stable
43. The transfer function of a zero-order hold
system is (c) To decrease the response error
–sT –sT (d) Sensitivity of the system is increased
(a) (1/s)(1 + e ) (b) (1/s)(1 – e )
(c) 1–(1/s)e–sT (d) 1+(1/s)e–sT UPPCL AE-16.11.2013
OPSC Poly. Lect. (Instrumentation)-2018, Paper-II Ans. (b) : A feedback in control system increase
GPSC Asstt. Prof. 11.04.2017 stability, reduce time constant and decrease sensitivity.
46. For a given signal flow diagram, the transfer Ans. (a) : If the poles of system lie on the right hand
function is- side of s-plane the response time will increase
exponentially.
51. Signal flow diagram of following analog
computer circuit is
(a) 1/(1–H0)(1–H1) (b) 1/1–H1H0

(c) 1/1–H1 (d) 1/(1–H0)
LMRC AM S&T -13.05.2018
UPPCL AE-16.11.2013
Ans. (c) : C = R + CH1
C – CH1 = R
C 1
=
R 1 − H1
1. The effect of feedback is to reduce system error
2. Feedback increases the system gain at one
frequency but reduces the system gain at another
frequency
3. Feedback can cause an originally stable system to
become unstable
(a) 1, 2 and 3 (b) 2 and 3 only
UPSC JWM-2016
Ans. (d) : The effect of feedback is to reduce system
error.
Feedback can cause an originally stable system to
become unstable
48. The DC gain of the system represented by the
1
transfer function P(s) = is
s +1
(a) 1 (b) 2 ISRO Scientist Engg.-2018
(c) 5 (d) 10 Ans.(a):
UJVNL AE-2016 s 2y −sy
1
Ans. (a) : P(s) =
s +1
2
1
DC gain ⇒ lim P ( s ) = lim −3
s →0 s→0 s + 1
=1 4
49. Positive feedback is the same as
(a) Frequency synthesis (b) Negative feedback
(c) Degeneration (d) Regeneration
UKPSC Assistant Radio Officer Screening Exam.-2011 −1
⇒ Integrator operation means multiplication of
Ans. (d) : Positive feedback circuit is also called s
regenerative circuit. As output voltage continuously
increasing that's why positive feedback circuit very
often used in unstable mode for oscillator.
50. What is the time response of a system whose
poles lie on the right hand side of s-plane?
(a) Exponentially increasing
(b) Exponentially decreasing 52. What is an ideal value of network function at
poles?
(c) Sinusoidal oscillations (a) Zero (b) Unity
(d) Step response (c) Infinity (d) Finite and non-zero
RPSC LECTURER-10.01.2016 Nagaland PSC CTSE (Diploma)-2017, Paper-I
Ans. (c) : For ideal value of network function the pole 57. Consider the following open-loop transfer
should be at infinite. The value of complex frequency, function:
which make the network function infinite when K(s + 2)
G=
substitute the denominator of a network function that is (s + 1) (s + 4)
called poles of network function. The characteristic equation of the unity
53. Transfer admittance function is the ratio of negative feedback will be:
Laplace transforms of_______ (a) (s + 1) (s + 4) + K (s + 2) = 0
(a) Current at one port to voltage at other port (b) (s + 2) (s + 1) + K (s + 4) = 0
(b) Voltage at one port to current at other port (c) (s + 1) (s – 2) + K (s + 4) = 0
(c) Current at one port to current at other port (d) (s + 2) (s + 4) + K (s + 1) = 0
(d) Voltage at one point to voltage at other port IES-2019
Nagaland PSC CTSE (Diploma)-2017, Paper-I Ans. (a) : Given that,
Ans. (a) : Transfer admittance is defined as the ratio of K (s + 2)
Open loop transfer functions, G(s)=
current transform at one port to the voltage transfer at ( s + 1)( s + 4 )
other port and denoted as Characteristic equation for unity negative feedback–
I (s) 1 + G(s) = 0, for unity feedback H(s)=1
Y21 = 2
V1 (s) K (s + 2)
1+ =0
I1 (s) (s +1)(s + 4)
Y21 =
V2 (s) (s + 1) (s+ 4) + K (s + 2) = 0
58. Consider the following statements regarding a
54. Network function 4s/(s+1)(s+3) has parabolic function:
(a) one zero and two poles 1. A parabolic function is one degree faster
(b) one zero and one pole than the ramp function.
(c) two zeros and one pole 2. A unit parabolic function is defined as
(d) one zero and no pole  t2
RPSC Vice Principal ITI-2016  , for t > 0
f(t) =  2
Ans. (a) : Given,  0 otherwise
4s 3. Laplace transform of unit parabolic
( s + 1)( s + 3) 1
function is 3 .
so from here we can see that it has one zero and two s
pole. Which of the above statements are correct?
55. In a feedback system, feedback factor of 0.1 is (a) 1 and 2 only (b) 1 and 3 only
used with forward gain of 10. The sensitivity of (c) 2 and 3 only (d) 1, 2 and 3
the system with respect to the feedback element IES-2019
is Ans. (d) : A parabolic function is defined as
(a) -0.5 (b) 0.5  t2

(c) -0.9 (d) 0.9 f(t) =  2 for t > 0
RPSC Vice Principal ITI-2016  0 for t ≤ 0
Ans. (a) : Given that, t2
H = 0.1 G = 10 or f(t) = u(t)
2
−GH −10 × 0.1 −1  t2  2! 1 1
STH = = = = −0.5
1 + GH 1 + 0.1×10 2 L [unit parabolic function] = L  u(t)  = 3 . = 3
2  s 2 s
56. The number of the integrators in the transfer unit ramp function is defined as
function G(s) = (s+3)/s2(s+5) are f (t) = tu(t)
(a) zero
(c) two
(b) one
(d) four f(t) =
0{
t for t > 0
t≤0
RPSC Vice Principal ITI-2016 i.e. A parabolic function is one degree faster than ramp
Ans. (c) : The pole lies on the origin indicates the function.
integrators in the transfer function. Hence all three statements are correct.
s+3 59. The price for improvement in sensitivity by the
Given function G(s) = 2 use of feedback is paid in terms of
s (s + 5)
(a) Loss of system gain
So, the number of the integrators = 2 (b) Rise of system gain
(c) Improvement in transient response, delayed 63. The sensitivity S TK of transfer function
response
(d) Poor transient response (1 + 2K)
T= with respect to the parameter K
IES-2019 (3 + 4K)
Ans. (a) : By the use of negative feedback, sensitivity is given by:
improves but the gain of the system is reduces and K 3K
bandwidth improves. Because gain and BW are (a) (b)
inversely related. 3+ K 2
2 + 4K + K 2
1 2K 4K
Gain ∝ (c) (d)
BW 3 + 10K + 8K 2
2 + 5K + 7K 2
60. Consider the following statements for signal IES-2012
flow graph: Ans. (c) : Given that,
1. It represents linear as well as non-linear systems. (1+ 2K)
2. It is not unique for a given system. T=
Which of the above statements is/are correct? (3 + 4K)
(a) 1 only (b) 2 only K ∂T
(c) Both 1 and 2 (d) Neither 1 nor 2 Sensitivity STK =
T ∂K
IES-2018
Ans. (b) : Signal flow graph is not applicable to non- K ∂  (1 + 2K) 
=  
linear system. It is only applicable for linear system and T ∂K  (3 + 4K) 
signal flow graph is not unique because it depends upon
the variable and equations. For a single system there can K  2 (3 + 4K) − (1 + 2K) × 4 
= × 
be different signal flow graph with different conditions. T  (3 + 4K)2 
61. In control systems, excessive bandwidth is NOT
employed because :
(a) Noise is proportional to bandwidth K  2 
= × (3 + 4K)  2 
(b) It leads to low relative stability (1 + 2K)  (3 + 4K) 
(c) It leads to slower response
(d) Noise is proportional to the square of the 2K
STK =
bandwidth 3 + 10K + 8K 2
IES-2013
64. What is the unit impulse response of the system
Ans. (a) : Excessive bandwidth is not employed in
shown in figure for t ≥ 0 ?
control system because noise is directly proportional to
bandwidth. i.e. Noise ∝ BW. The product of gain and
bandwidth is always constant.
(a) 1 + e–t (b) 1 –e–t
62. A system is described by the transfer function
(c) e–t (d) –e–t
2s + 5
G(s) = . The dc gain of the system is: IES-2011
(s + 5) (s + 4)
(a) 0.25 (b) 0.5 Ans. (b) :
(c) 1 (d) ∞ C(s) 1
IES-2012 Transfer function = =
Ans. (a) : Given that, R(s) s (s +1)
2s + 5 When input is impulse then response is impulse response.
G(s) =
(s + 5) (s + 4) r (t) = δ(t)
⇒ R(s) = 1
 2 
5 1 + s  1 1 1
 5  So C(s) = = −
 s  s s (s + 1) s (s + 1)
5 1 +  4  1 + 
 5  4 Take inverse laplace transform.
 2  c(t) = (1 − e − t )u(t)
1 + s 
 5 
65. Given the differential equation model of a
 s  s 
4 1 + 1 +  physical system, determine the time constant of
 5  4  the system :
for Dc gain , s = 0 dx
Then,
(1 + 0 ) 40
dt
+ 2x = f(t)
4 (1 + 0 )(1 + 0 ) (a) 10 (b) 20
DC gain = 0.25 (c) 1/10 (d) 4
IES-2011
Ans. (b) : Given, To get the transfer function from d(s) to y(s) we make
Differential equation– R(s) = 0.
dx Then block diagram reduced to
40 + 2x = f (t)
dt
Take Laplace transform–
40sX(s)+2X(s) = F(s)
X(s)[40s + 2] = F(s)
X(s) 1
Transfer function = = y(s) 2/(3s +1)
F(s) (40s + 2) Transfer function = =
d(s)  2 
1/ 2 1+ 3×  
T.F. =  (3s +1) 
(1 + 20s)
y(s) 2
K =
Compare this equation with where d(s) (3s +1) + 6
(1 + sT)
T = time constant. y(s) 2
Hence, time constant T = 20. =
d(s) (3s + 7)
66. A linear time-invariant system is initially at
rest, when subject to a unit-step input, gives a ω
68. Consider the function where F(s) is the
response y(t) = te–1, t > 0. The transfer function s2 + ω2
of the system is : Laplace transform of f(t). What is the steady
1 1 state value of f(t)?
(a) (b) (a) Zero
(s + 1) 2 s(s + 1) 2
(b) One
s 1
(c) (d) (c) Two
(s + 1) 2 s +1 (d) A value between – 1 and +1
IES-2010 IES-2009
Ans. (c) : Given that, Ans. (d) : Given that,
Response y(t) = t e–1, t > 0
when input r(t) = unit step input u(t) ω
F(s) = 2
r (t) = u(t) s + ω2
⇒ R(s) = 1/s We know that,
1 ω
⇒ Y(s) = Laplace transform of (sin ωt) u(t) = 2
(s + 1) 2 s + ω2
–1
So, f(t) = L [F(s)]
Y(s) 1/(s +1)2
Then transfer function = = f(t) = (sin ωt) u(t)
R(s) 1/s The value of sin ωt lies between – 1 and + 1.
Y(s) s Hence steady state value of f(t) lies between – 1 and + 1.
=
R(s) (s +1) 2 69. What is the characteristic of a good control
system?
(a) Sensitive to parameter variation
67. (b) Insensitive to input command
(c) Neither sensitive to parameter variation nor
sensitive to input commands.
(d) Insensitive to parameter variation but
The transfer function from d(s) to y(s) is : sensitive to input commands.
2 2 Mizoram PSC IOLM, 2018 Paper-II
(a) (b) IES-2009
3s + 7 3s + 1
6 2 IES - 2005
(c) (d) Ans. (d) : A good control system is insensitive to
3s + 7 3s + 6
parameter variation and highly sensitive to input
IES-2010
commands.
Ans. (a) : Given block diagram–
An effective control system should not only be used to
look for identify faults, but it should programmed in
such a way that it can suggest solution to faults.
70. A negative-feedback closed-loop system is
supplied with an input of 5V, the system has a
forward gain of 1 and a feedback gain of 1.
What is the output voltage?
(a) 1.0 V (b) 1.5V Ans. (c) : Higher the system gain may result in
(c) 2.0V (d) 2.5V instability of the system while large error causes
IES-2009 inaccuracy, not instability.
Ans. (d) : Given that, input = 5V, forward gain = 1 73. The impulse response of a linear time invariant
feedback gain = 1 system is given as g(t) = e–t, t > 0.
Block diagram– The transfer function of the system is equal to :
(a) 1/s (b) 1/[s(s + 1)]
(c) 1/(s+1) (d) s/(s+1)
IES-2008
Ans. (c) : Impulse response g(t) = e–t, t > 0
1
Gain = g(t) = e–t u(t)
1+1 Transfer function = Laplace transform of impulse response
Output voltage 1 T.F. = L [g (t)] = L [e–t u(t)]
=
Input voltage 1 + 1 T.F. =
1
1 (s + 1)
Output voltage V = ×5
1+1 74. A control system whose step response is 0.5
(1 – e–2t) is cascaded to another control block
V = 2.5 Volt
whose impulse response is e–t what is the
71. In closed loop control system, what is the transfer function of the cascaded combination?
sensitivity of the gain of the overall system, M 1 1
to the variation in G? (a) (b)
(s + 1) (s + 2) s (s + 1)
1 1 1 0.5
(a) (b) (c) (d)
1 + G(s)H(s) 1 + G(s) s(s + 2) (s + 1) (s + 2)
G(s) G(s) IES-2007
(c) (d)
1 + G(s)H(s) 1 + G(s) Ans. (a) : Given that,
IES-2009, 2000 Step response y(t) = (1 – e–2t) × 0.5
Ans. (a) : Consider a closed loop control system with On taking laplace transform-
forward gain G and feedback gain H. 1 1 
⇒ Y(s) = 0.5  − 
 s (s + 2) 
1  (s + 2) − s 
Y(s) =  
2  s (s + 2) 
C(s) G(s)
Gain of overall system = = 1
R(s) 1 + G(s)H(s) Y(s) =
s(s + 2)
G(s)
Let, M= r(t) = u(t)
1 + G(s)H(s)
1
Sensitivity of gain to the variation of G R(s) =
s
G ∂M G ∂  G 
SGM = =   Y(s) 1/s(s + 2)
M ∂G M ∂G 1 + GH  so, T.F. = =
R(s) 1/s
G 1 + GH − GH  1
=   G1 =
M  (1 + GH) 2  (s + 2)
G 1 Impulse response = e–t Q L[IR] = TF
= ×
G /(1 + GH) (1 + GH)2 Transfer function = G2 = 1/(s+1)
1
= (1 + GH ) ×
(1 + GH )2 Hence transfer function of the cascaded combination–
C(s)
1 = G1G 2
SGM = R(s)
1 + GH
C(s) 1 1 1
1 = . =
or SGM = R(s) (s + 2) (s +1) ( s + 1)( s + 2 )
1 + G(s) H(s)
75. If the initial conditions for a system are
72. Which of the following may result in instability
problem? inherently zero, what does it physically mean?
(a) Large error (b) High selectivity (a) The system is at rest but stores energy
(c) High gain (d) Noise (b) The system is working but does not store
energy
IES-2009
(c) The system is at rest or no energy is stored in 78. Consider the following amplifier with –ve
any of its parts feedback:
(d) The system is working with zero reference
input
IES-2007
Ans. (c) : If the initial condition of a system is
inherently zero that means the system is at rest or no
energy is stored in any of its parts. If the closed-loop gain of the above amplifier is
76. The unit step response of a system is 1 – e–1 (1 + t). + 100, the value B will be:
Which is this system? (a) – 9 × 10–3 (b) + 9 × 10–3
–3
(a) Unstable (b) Stable (c) –11 + 10 (d) + 11 × 10–3
IES-2002
(c) Critically stable (d) Oscillatory
Ans. (b) : By converting the following amplifier into
IES-2006 block diagram–
Unit step response y(t) = 1 – e–t (1 + t)
By taking Laplace transform–
1 1 1 Given,
Y(s) = − −
s (s + 1) (s + 1)2 Y(s)
Closed loop gain = = 100
(s + 1)2 − s(s + 1) − s R(s)
Y(s) = 1000
s (s + 1)2 100 =
1+ ( B×1000 )
1
Y(s) = 100 (1 + (B × 1000)) = 1000
s (s + 1) 2 1 + (B × 1000) = 10
and input r (t) = u (t) B = +9 ×10−3
R (s) = 1/s
79. Consider the following single-loop feedback
Y(s) 1/ s (s + 1) 2 structure illustrating the return difference:
So, Transfer function = =
R(s) 1/ s
1
T.F. =
(s + 1)2
The roots of characteristic equation of transfer function The return difference for A is -
is – 1 and –1. (a) 1 –Aβ (b) 1 + Aβ
1 + Aβ Aβ
Hence the given system is stable. (c) (d)
Aβ 1 − Aβ
IES-2002
Feedback in control system can be used
Ans. (b) : Return difference measure the effect of
1. to reduce the sensitivity of the system to the feedback with respect to a specified element in the
parameter variations and disturbances. closed loop system.
2. to change time constant of the system The return difference is given by-
3. To increase loop gain of the system FA = 1 − A loop
Which of the statements given above are A loop = −G ( s ) H ( s )
correct?
A loop = − Aβ (as shown in the signal flow graph)
(a) 1, 2 and 3 (b) 1 and 2
(c) 2 and 3 (d) 1 and 3 FA = 1 − ( −Aβ )
IES-2004 FA = 1 + Aβ
Ans. (b) : Feedback in control system can be used to 80. The unit step response of a particular control
reduced the sensitivity of the system to the parameter system is given by c(t) = 1 – 10e–t. Then its
variation and disturbance. transfer function is:
Feedback in control system can also be used to change 10 s−9
the time constant of the system and also reduced the (a) (b)
s +1 s +1
loop gain if feedback is negative and increased if 1 − 9s 1 − 9s
feedback is positive. (c) (d)
s +1 s(s + 1)
Hence only statement 1 and 2 is correct.
IES-2001
Ans. (c) : Given that, From dominant pole concept, there are two dominant pole
Unit step response c(t) = 1 – 10 e–t (0 and – 1) and two insignificant poles (– 15 and – 20).
On taking laplace transform - Convert the given transfer function in time constant
1 10 form.
C(s) = − 600
s (s + 1) T.F. =
s (s +1)15 (1+ s/15) 20 (1+ s/20)
−9s + 1
C(s) = 600/300
s (s + 1) =
And input is r(t) = u(t) s (1+ s) (1+ s/15)(1+ s/20)
R(s) = 1/s 2
T.F. =
C(s) ( −9s + 1) / s (s + 1) s (1+ s)(1+ s/15) (1+ s/20)
So, transfer function = =
R(s) 1/ s Neglecting the insignificant poles (– 15 and – 20).
1 − 9s 2
T.F. = we get T.F. =
(s + 1) s (s +1)
81. Which of the following are related to rational 83. Consider the following expressions which
transfer function of a system? indicate the step of impulse response of an
1. Ratio of Fourier transform of output to initially relaxed control system
input with zero initial conditions 1. [5 – 4e–2t]u(t) 2. [e–2t + 5] u(t)
2. Ratio of Laplace transform of output to
3. δ(t) + 8e–2tu(t) 4. δ(t) + 4e–2t u(t)
input with zero initial conditions
Those which correspond to the step and
3. Laplace transform of system impulse
response. impulse response of the same system include.
4. Laplace transform of system unit step (a) 1 and 3 (b) 1 and 4
response (c) 3 and 4 (d) 2 and 4
Select the correct answer using the codes given IES-2000
below : Ans. (a) : Let step response y(t) = [5 – 4e–2t] u(t)
(a) 1 and 4 (b) 2 and 3 we know that , the derivative of step response gives
(c) 1 and 3 (d) 2 and 4 impulse response.
Nagaland PSC (Degree) 2018, Paper-II d
Nagaland PSC CTSE (Degree) - 2016, Paper-II then impulse response = [ y(t)]
dt
IES-2000
d
GATE- 1995 I.R. = [5 − 4e −2 t ]u(t)
Ans. (b) : From the definition of transfer function, dt
Transfer function is the ratio of Laplace transform of d d
= [5 − 4e −2 t ] [u(t)] + u(t). [5 − 4e −2t ]
output to the Laplace transform of input with all initial dt dt
conditions is equal to zero, or = [5 − 4e −2 t ]δ(t) + [8e −2 t ]u(t)
Transfer function is the Laplace transform of impulse
response. = 5δ(t) − 4e −2t δ(t) + 8e −2t u(t)
L(output) We know that,
T.F. = = L (impulse response). x(t)δ(t – t0) = x(t0)δ(t – t0)
L (input) initialcondition=0
x(t)δ(t – 0) = x(0)δ(t)
82. A system with transfer function Then,
600
can be approximated by = 5δ(t) − 4e −2×0 δ(t) + 8e −2 t u(t)
s(s + 1)(s + 15) (s + 20)
the system : I.R. = δ(t) + 8e −2t u(t)
2 40 If step response is y(t) = [5 + e −2t ]u(t)
(a) (b)
s(s + 1) s(s + 20) dy(t)
600 40 then Impulse response =
(c) (d) dt
s(s + 15) (s + 20) (s + 1)(s + 20) d −2 t
IES-2000 I.R. = [5 + e ]u(t)
dt
Ans. (a) : Given that, = [5 + e −2 t ]δ(t) − 2e −2 t u(t)
600
T.F. = = e −2 t δ(t) + 5δ(t) − 2e −2 t u(t)
s (s +1) (s +15) (s + 20)
Here poles are 0, – 1, – 15 and – 20. I.R. = 5δ(t) − e−2t u(t).

84. If the open-loop transfer function of the system Ans. (a) : Given, signal flow graph–
K(s + 10)
is G(s)H(s) =
s(s + 8) (s + 16) (s + 72)
Then a closed loop pole will be located at
s = – 12 when the value of K is :
(a) 4355 (b) 5760
(c) 9600 (d) 9862 Forward path–
IES-2000 P1 = rsu, ∆1 = 1 – gf , L1 = ts
Ans. (b) : Given that, P2 = efh, ∆2 = 1 – ts, L2 = gf
open loop transfer function, ∆ = 1 – (individual loop gain) + (two non-touching loop
K (s +10) gain)
G(s) H(s) = = 1 – (ts + gf) + (tsgf)
s (s + 8) (s +16)(s + 72)
= 1 – ts – gf + tsgf
so, closed loop transfer function characteristic equation
∆ = (1 – st) (1– fg)
1 + G(s) H(s) = 0
By Mason’s gain formula–
K ( s + 10 ) 2
1+ =0
s ( s + 8 )( s + 16 )( s + 72 ) x2 ∑P ∆
K =1
K K
=
s ( s + 8 )( s + 16 )( s + 72 ) + K ( s + 10 ) = 0 x1 ∆
Given, one pole s = – 12, it will satisfy the C.E. x 2 P1∆1 + P2 ∆ 2 rsu (1 − fg) + efh (1 − st)
– 12 (– 12 + 8) (– 12 + 16) (–12 + 72) + K (– 12 + 10) = 0 = =
x1 ∆ (1 − st)(1 − fg)
– 12 × (– 4) × 4 × 60 = 2K
x2 rsu efh
K = 5760 = +
x1 (1 − st) (1 − fg)
85. When all the roots of characteristic equation 87. The transfer function of the system shown in
are found in the left half of s-plane, the system the given figure is:
response due to initial condition will :
(a) Increase to infinity as time approaches
infinity
(b) Decreases to zero as time approaches infinity
(c) Remain constant for all time
(d) be oscillating ABC
(a) O / R =
IES-2000 1 + ABC
Ans. (b) : If all the roots of characteristic equation are A+ B+C
(b) O / R =
lies in left half of s-plane then system is stable. Then the 1 + AB + AC
system response due to initial condition (natural ΑB + AC
response) decreases to zero as time approaches to (c) O / R =
ABC
infinity because system is stable.
AB + AC
(d) O / R =
1 + AB + AC
IES-1998
Ans. (d) : Given block diagram,
86. For the signal flow diagram shown in the given

figure, the transmittance between x2 and x1 is:
Block B and C are connected in parallel.
rus efh rus efh

(a) + (b) + A(B + C)
1 − st 1 − fg 1 − fg 1 − st So, O/R =
1 + A(B + C)
efh rsu rst rsu
(c) + (d) + AB + AC
1 − ru 1 − eh 1 − eh 1 − st O/R =
IES-1998 1 + AB + AC
88. A signal flow graph is shown in the following P 1 = G2 G4 G6
figure. Consider the following statements P 2 = G2 G9 G7
regarding the signal flow graph: P 3 = G3 G5 G7
1. There are three forward paths P 4 = G3 G8 G6
2. There are three individual loops P5 = G2 G9 (–H2) G8 G6
3. There are three non-touching loops of these P6 = G3 G8 (–H1) G9 G7
statements
There are three individual loops -
l1 = –G4 H1 , l2 = –G5 H2 , l3 = G8 (–H1) G9 (–H2)
90. The signal flow graph of a closed-loop system is
shown in the figure, where TD represents the
disturbance in the forward path: The effect of
the disturbance can be reduced by:

IES-1998, 1993
Ans. (d) : Given signal flow graph -
(a) Increasing G2(s) (b) Decreasing G2(s)
(c) IncreasingG1(s) (d) DecreasingG1(s)
IES-1997
Ans. (c) : R(s) = 0, Transfer function due to disturbance
is given as-
C (s) −G 2 ( s )
=
TD ( s ) 1 + G1 ( s ) G 2 ( s ) H1 ( s )
There are three forward path,
p1 = b1 b3 b8 b9 b10 Let, G1 ( s ) G 2 ( s ) H1 ( s ) >>> 1
p2 = b1 b4 b9 b10
p3 = b1 b6 b10 C (s) −1
So, = .........(i)
There are four individual loop, TD ( s ) G1 ( s ) H1 ( s )
l1 = b 2 b 3 , l2 = b 5 b 8 From above equation it is clear that disturbance signal
l3 = b 7 , l4 = b 2 b 4 b 5 on output C(s) can be reduced by increasing G1(s).
There are three non-touching loop - Change in G2(s) will have small effect because it is
L1 = b2 b 3 b7 , L2 = b5 b8 b7 , L3 = b2 b4 b5 b7 present in numerator and denominator both.
89. The signal flow graph of system shown in the 91. The closed-loop system shown in the figure is
figure, the number of forward paths and the subjected to a disturbance N(s), the transfer
individual loops will be respectively. function C(s)/N(s) is:
(a) 5 and 2 (b) 5 and 3 G1 (s)G 2 (s) G1 (s)

(a) (b)
(c) 6 and 2 (d) 6 and 3 1 + G1 (s)G 2 (s)H1 (s) 1 + G1 (s)H1 (s)
RPCS Lect.-2011
IES-1997 G 2 (s) G 2 (s)
(c) (d)
Ans. (d) : 1 + G 2 (s)H1 (s) 1 + G1 (s)G 2 (s)H1 (s)
IES-1997
Ans. (d) : Given block diagram ,
To calculate C(s)/ N(s), make R(s) = 0

There are six forward path -
Then block diagram reduce to - Open loop sensitivity with respect to slightly variation
in G
G ∂T1
STG1 =
T1 ∂G
So, Transfer function G ∂
= (G) {T1 = G for open loop}
C(s) G 2 (s) G ∂G
= STG1 = 1
N(s) 1 + G1 (s)G 2 (s)H1 (s)
92. The transfer function T(s) of the system shown Closed loop sensitivity with respect to G.
in the following figure is given by : G ∂T2
STG2 =
T2 ∂G
G
∴ T2 = for closed loop
1 + GH
G ∂  G 
G1 (s)G 2 (s) STG2 =  
(a) T(s) = G /(1 + GH) ∂G 1 + GH) 
1 − G 2 (s)
 (1)(1 + GH ) − G ( 0 + H ) 
(b) T(s) =
G1 (s) ⇒ = (1 + GH )  
1 − G1 (s)G 2 (s)  (1 + GH )2 
G1 (s)  1 
(c) T(s) = = ( + )
1 − G1 (s)G 2 (s) 1 GH  2
 (1 + GH ) 
G 2 (s)
(d) T(s) = 1
1 + G1 (s)G 2 (s) STG2 =
1 + GH
IES-1996 So, the ratio of open loop sensitivity to the closed loop
Ans. (a) : Given block diagram - sensitivity.
ST1 1
G
= = 1 + GH
ST2
G 1/(1 + GH)
Block diagram can reduce to - 94. From the signal flow graph shown in the figure,
the value of x6 is:
x1
x6
T(s) =
C(s) G1 (s)G 2 (s)
=
x4 x5
R(s) 1 − G 2 (s) x2
93. Consider a control system shown in the given
figure. For a slight variation in G, the ratio of x3
open loop sensitivity to closed-loop sensitivity (a) de (ax1 + bx2 + cx3)
will be given by: (b) (a + b + c) (x1 + x2 + x3) (d + e)
(c) (ax1 + bx2 + cx3) (d + e)
(d) abc de (x1 + x2 + x3)
IES-1992
Ans. (a) : Given signal flow graph -
x1
1
(a) (b) 1 + GH x6
(1 + GH) x4 x5
1 x2
(c) (d) 1 – GH
(1 − GH)
IES-1995 x3
Ans. (b) : From given signal flow graph -
x4 = ax1 + bx2 + cx3
and x5 = dx4
and x6 = ex5
x6 = dex4
x6 = de (ax1 + bx2 + cx3)
95. From the figure shown below, the Transfer (c) Branch gain
function of the signal flow graph is: (d) Path gain
TNTRB AE– 2017
Ans. (a) : The product of branch gains encountered in
traversing the loop is loop gain.
T12 T22 98. The impulse response of a certain system is
(a) (b) Sin2t. The system transfer function is
1 − T22 1 − T12
T12 T22 1 2
(c) (d) (a) (b)
1 + T22 1 + T12 s2 + 2 s2 + 2
IES-1992 2 s
(c) (d) 2
Ans. (a) : Given signal flow graph - s +4
2
s +4
Ans. (c) : Impulse response y(t) = sin2t
T.F. = L{impulse response}
Here only one-forward path So, T.F. = L{sin2 t }
P1 = T12 , ∆1 = 1
and ∆ = 1 – (individual loop gain) + (gain of two non- 2
T.F. = 2
touching loops) s +4
∆ = 1 – T22 99. In the signal flow graph of figure the gain c/r
By Mason's gain formula - will be
1 5
∑P ∆
k =1
k k
Transfer function =
∆
P∆
T.F. = 1 1
∆ (a) 11/9 (b) 22/15
(c) 24/23 (d) 44/23
T12
T.F. = GATE- 1991
1 − T22
Ans. (d) :
96. A block diagram of a negative feedback system 5
is as shown in fig. below. If G=
X0
infinity, then the closed loop gain is
Xi
Here, P1 = 1×2×3×4×1 = 24
P2 = 1×5×1=5
Loop gains L1 = –2, L2 = –3, L3=–4, L4 = –5
Two non touching loop- (–2) (–4)
L21 = 8
∆ = 1 + ( 2 + 3 + 4 + 5 ) + 8 = 23
(a) Infinity (b) 0.5 ∆1 = 1 − 0 = 1
(c) 0 (d) 2 ∆ 2 = 1 − ( −3 ) = 4
TSTRANSCO AE- 2018
By mason’s gain formula =
Ans. (d) : Transfer function P∆ + P ∆ 24 × 1 + 5 × 4 44
c/r = 1 1 2 2 = =
X0 G 1 1 ∆ 23 23
= = = =2
X i 1 + 0.5G 1 + 0.5 0 + 0.5 100. In the signal flow graph of figure, y/x equals
G
97. The product of branch gains encountered in
traversing the loop is: (a) 3 (b) 5/2
(a) Loop gain (c) 2 (d) None of the above
(b) Forward path gain GATE- 1997
Ans. (c)
Here forward path P1 = 5 × 2 × 1 = 10

Loop gains L1 = 2 × −2 = −4
∆ = 1 − ( L1 )
∆ =1+ 4 = 5
∆1 = 1 − 0 = 1
P1∆1 10 × 1
Then, = T.F. = = =2
∆ 5
101. The equivalent of the block diagram in the Z3 (s) –Z3 (s)
(a) ,
figure is given as Z2 (s) + Z3 (s) + Z4 (s) Z1 (s) + Z3 (s)
–Z3 (s) –Z3 (s)
(b) ,
Z2 (s) – Z3 (s) + Z4 (s) Z1 (s) + Z3 (s)
Z3 (s) Z3 (s)
(c) ,
Z2 (s) + Z3 (s) + Z4 (s) Z1 (s) + Z3 (s)
–Z3 (s) Z3 (s)
(d) ,
Z2 (s) – Z3 (s) + Z4 (s) Z1 (s) + Z3 (s)
GATE-2001
Ans. (c) :
LMRC AM (S&T)-13.05.2018
GATE-2001
Ans. (d) :
Applying KVL in loop-1

Vi ( s ) = I1 ( s ) Z1 ( s ) + ( I1 ( s ) − I2 ( s ) ) Z3 ( s )
Vi ( s ) Z3 ( s )
I1 ( s ) = + I2 (s )
Z1 ( s ) + Z3 ( s ) Z1 ( s ) + Z3 ( s )
Applying KVL in loop-2
Shifting the take off point after the block. 0 = I 2 ( s ) Z2 ( s ) + I2 ( s ) Z4 ( s ) + ( I 2 ( s ) − I1 ( s ) ) Z3 ( s )
I 2 ( s ) ( Z2 ( s ) + Z3 ( s ) + Z4 ( s ) ) = I1 ( s ) Z3 ( s )
Z3 (s)
I2(s) = I1(s)
Z2 (s) + Z4 (s) + Z3 (s)
I2 ( s )
from given SFG = G 2 (s )
102. An electrical system and its signal-flow graph I1 ( s )
representations are shown in the figure (a) and
Z3 (s)
(b) respectively. The values of G2 and H, ∴ G2(s) =
Z2 (s) + Z3 (s) + Z4 (s)
respectively are
1 − (be + cf + dg) bedg
(a) (b)
abc 1 − (be + cf + dg)
abcd
(c)
1 − (be + cf + dg) + bedg
1 − (be + cf + dg) + bedg

Z3 ( s ) (d)
∴ H (s) = abcd
Z1 ( s ) + Z3 ( s ) GATE-2004
103. The signal flow graph of a system is shown in Ans. (c) :
C(s)
the figure. The transfer function of the
R(s)
system is
Forward path-
P1 = abcd
Loop gains L1 = be, L2= cf, L3 = dg
There are 1-two non touching loop = L1×L3
L1L3 = bedg
(a)
6
(b)
6s ∆ = 1 − ( be + cf + dg ) + bedg
s + 29s + 6
2
s + 29s + 6
2
∆1 = 1 − 0 = 1
s(s + 2) s(s + 27)
(c) 2 (d) 2 By mason’s gain formula-
s + 29s + 6 s + 29s + 6
x 5 P1∆1 abcd
GATE- 2003 = =
x1 ∆ 1 − ( be + cf + dg ) + bedg
Ans. (d) :
105. The input-output transfer function of a plant
100
H(s) = . The plant is placed in a unity
s(s + 10)2
negative feedback configuration as shown in
the figure below.
From given signal flow graph-

P1 = 1× 1 = 1
−2 −3 −24
Loop gains L1 = ,L 2 = , L3 =
s s s
The signal flow graph that does not model the
There are 1-Two non touching loop-
plant transfer function H(s) is
 −2  −3   6 
L 21 =    =  2 
 s  s   s 
 2 3 24  6
∆ = 1+  + +  + 2
s s s  s
 3 24  s + 27
∆1 = 1 +  +  =
s s  s
C ( s ) P1∆1 ( s + 27 ) / s
Then, T.F = = =
R (s ) ∆  2 3 24  6
1+  + +  + 2
s s s  s
s ( s + 27 ) GATE-2011
= Ans. (d) : From Mason’s gain formula-
s + 29s + 6 2
104. Consider the signal flow graph shown in the From the option (a)
figure. 100
s3 100
T.F.= =
 10 10  100 s3 s 2 + 20s + 100
1+  +  + 2 ( )
 s s  s
s2

100 −2
= L3 =
, L 4 = −4
s ( s + 10 )
2 s2
2 4 2 s 2 + 2s + 4s + 4s 2 + 2
From the option (b) ∆ = 1+ + + 4 + 2 =
100 s s s s2
100 5s + 6s + 2
2
T.F.= s3 = =
1+ + 2 (
20 100 s s 2 + 20s + 100 ) and, ∆1 = 1
s2
s s
100 ∆2 = 1
=
s ( s + 10 )
2
P∆ +P ∆
By Mason’s gain formula- = 1 1 2 2
From the option (c) ∆
100  1 1   s +1 2
 × 1 + × 1 × s 2  ×s
3 100 Y (s)  s 2
s   s2 
T.F. = s = = =
U (s)
1+ (
20 100 s s 2 + 20s + 100
+ 2 ) 5s 2 + 6s + 2 5s 2 + 6s + 2
s s s +1
= 2
100 5s + 6s + 2
=
s ( s + 10 )
2
107. For the following system,
From the option (d)
100
3 100.s 2 100
T.F. = s = 3 2 =
1+ 2 (
100 s s + 100 ) (
2
s s + 100 )
s Y(s)
So, option (a), (b), (c), satisfy given plant transfer When X1(s) =0, the transfer function is
X 2 (s)
function H(s), only option (d) does not model H(s).
106. The signal flow graph for a system is given s +1 1
(a) (b)
Y(s) s 2
s +1
below. The transfer function for this s + 2 s +1
U(s) (c) (d)
system is s(s + 1) s(s + 2)
GATE-2014, , Set-II
Ans. (d) :
s +1 s +1
(a)
5s + 6s + 2
2
(b)
s + 6s + 2
2 When X1 ( s ) = 0
s +1 1 Then diagram will be-
(c) 2 (d)
s + 4s + 2 5s 2 + 6s + 2
GATE-2013
Ans. (a) :
Then transfer function is given as-

Y (s) 1/ s
1
s s +1
T.F. = = = =
X 2 (s )  1   s  s ( s + 1) + s s ( s + 2 )
1+   
 s  s +1 s ( s + 1)
1
Forward path, P1 = 1× s −1 × s −1 × 1 = 108. By performing cascading and/or summing/
s2 differencing operations using transfer function
1 blocks G1(s) and G2(s), one CANNOT realize a
P2 = 1× s −1 ×1×1 =
s transfer function of the form
2 4 G1 (s)
Loop gains, L1 = − , L 2 = − (a) G1(s)G2(s) (b)
s s G 2 (s)

 1 
(c) G1 (s)  + G 2 (s) 
 G1 (s) 
 1  Y G1G 2 /1 + G1H1 G1G 2
(d) G1 (s)  – G 2 (s)  G= = =
 G1 (s)  X 1 + ( G1G 2 /1 + G1H1 )(1) 1 + G1G 2 + G1H1
APGENCO AE- 23.04.2017 110. The block diagram of a system is illustrated in
GATE-2015, Set-II the figure shown, where X(s) is the input Y(s) is
Ans. (b) : As G1 ( s ) and G 2 ( s ) are given the output. The transfer function H(s) =
Y(s)
is
X(s)
In cascade→G1(s)G2(s)
 1 
G1 (s)  + G 2 ( s )  ⇒ Adder and Multiplication
 G1 ( s )  s2 + 1
(a) H(s) =
 1  2s 2 + 1
G1 (s)  − G 2 ( s )  ⇒ Substraction and
 G1 ( s )  (b) H(s) = 3
s2 + 1
Multiplication s + 2s 2 + s + 1
G (s ) s +1
(c) H(s) = 2
So, in the given options 1 is not possible. s + s +1
G2 (s)
s2 + 1
109. The block diagram of a feedback control (d) H(s) = 3 2
s + s + s +1
system is shown in the figure. The overall GATE-2019
closed-loop gain G of the system is Ans. (b) : By using block reduction method-
G1G 2
(a) G =
1 + G1H1
G1G 2
(b) G =
1 + G1G 2 + G1H1
G1G 2
(c) G =
1 + G1G 2 H1
G1G 2
(d) G =
1 + G1G 2 + G1G 2 H1
GATE-2016, Set-III Transfer function is given-
IES-1996
s2 + 1
Ans. (b) : From question diagram after reduction, the
Y (s ) s ( s 2 + s + 1)
overall closed loop gain ‘G’ of the system is- =
X (s ) s2 + 1
1+ ×1
s ( s 2 + s + 1)
Y (s) s2 + 1
=
X ( s ) s ( s + s + 1) + s 2 + 1
2
Y (s) s2 + 1
= 3
X ( s ) s + 2s 2 + s + 1

111. Signal flow graphs can be used to represent: (a) (G1G2) / (1+G1G2) (b) G1G2/(1-G1G2)
(a) Linear systems only G2
(c) G2/(1 + G1G2) (d)
(b) Non-linear system only
(c) Both linear and non-linear systems
(1 − G1G 2 )
(d) Time-invariant as well as time varying TNPSC AE- 2019
systems Ans. (c) :
Ans. (a) : Signal flow graph can be used to represent
linear system only. Signal flow graph (SFG) is a graph
which represents a set of equations. It consists of nodes
and branches such that each branch of signal flow graph
having an arrow which represents the flow of signal.
G(s)
It used for transfer function of the system represent If R(s) = 0 then T.F. =
linear system only. 1 + G(s)H(s)
112. Y(s) G2
=
W(s) 1 + G1G 2
114. When two networks are cascaded, the overall
transfer function E2(s)/E1(s) is given by
Given figure shown a speed control system in

which the output member of the system is
subject to a torque disturbance. In the diagram
Ωr(s), Ω(s), T(s) and D(s) are the Laplace
transforms of the reference speed, output
speed, driving torque and disturbance torque,
respectively. In the absence of a disturbance (a) H1(s) + H2 (s)
torque, the output speed is equal to the
reference speed. Assume that the reference H 2 (s)
(b)
input is zero, the steady-state output velocity H1 (s)
for a unit-step disturbance torque is given by : (c) H1(s) H2(s)
(a) 1/K (b) K
(d) H1(s)*H2(s) (*-convolution)
(c) K/2 (d) K/4
APPSC Poly. Lect. 15.03.2020 TNPSC AE- 2019
Ans. (a) : In the absence of reference input, this Ans. (c) :
reduces to - I1 ( s ) sC1 1
H1 (s) = =
1  R 1sC1I1 ( s ) + I1 ( s )  sC1 R 1sC1 + 1
Ω(s) 1
Then, = Js = I 2 ( s ) sC 2 1
D(s) 1 + K 1 Js + K H 2 (s) = =
Js  R 2sC 2 I2 ( s ) + I 2 ( s )  sC 2 R 2sC 2 + 1
 1  1 In cascade, the overall transfer function
Ω (s) =   D (s)
Unit step
D(s) →
 Js + K  s H(s) = H1(s). H2(s).
 1 1 115. The forward transfer function
Ω (s) =  
 Js + K  s G (s) = 3
20
and the feedback gain
The steady state output velocity for a unit step ( s + 2s 2
+ 4s )
disturbance torque-
H ( s ) = –0.8. Find the closed loop transfer
Ω(s)ss = limsΩ ( s )
s →0 function of the SFG.
 1 1 1 20s 20
lims   = (a) (b)
s→0  Js + K  s K ( s + 2s + 4s + 16 )
3 2
( s + 2s + 4s + 20 )
3 2
113. For the signal flow graph representing a

feedback system subjected to a disturbance 20 20s
(c) (d)
w(s), the transfer function relating y(s) to w(s) ( s + 2s + 4s + 16 )
3 2
( s + 2s + 4s + 20 )
3 2
with R(s) = 0
UPPCL AE-05.11.2019
G (s)
Ans. (c) : T ( s ) =
1 + G (s) H (s)

20 Then E(s) = –s2Y(s)
 1  1 
+ + 4s E ( s ) = −s 2  2
3 2
T (s) = s 2s  2 
20  s + 1  s 
1+ 3 × 0.8
s + 2s 2 + 4s  1 
E (s) = −  2 
20  s +1
T (s ) = Take inverse Laplace transform
s + 2s + 4s + 16
3 2
116. Consider a transfer function e ( t ) = − sin t

2 118. For a linear time invariant system shown in
s - 5s + 100
H(s) = 2
. The transfer function figure, X(s) is the input and Y(s) is the output.
s + 5s + 100
represents a :
(a) High pass filter
(b) Band elimination filter
(c) Low pass filter
(d) All pass filter
In order to nullify the effect of noise N(s), the
s 2 − 5s + 100
Ans. (d) : H ( s ) = gain of the feed-forward path Ge(s) is :
s 2 + 5s + 100 s(s + a) (s + d) c(s + a)
(a) (b)
H(s = 0) =
100
=1 c(s + b) s(s + a) (s + d)
100 s(s + b) (s + d) c(s + a)
(c) (d)
s 2 1 − 5 / s + 100 / s 2  c(s + a) s(s + b) (s + d)
s (s = ∞ ) = 2  
s 1 + 5/ s + 100 / s 2  DRDO-2009
Ans. (c) : From the block diagram -
H (s = ∞ ) = 1
s+a 
Hence system is all pass filter. Y ( s ) = N ( s ) +  X ( s ) − G e ( s ) N ( s ) − Y ( s )   
s+b
117. For the system shown in figure, e(t) is the error
 c 
between input x(t) and output y(t).  
 s (s + d ) 
 s + a  c 
Let x =    
 s + b   s ( s + d ) 
Y(s) + x.Y(s) = N(s) – Ge(s) N(s).x + X(s).x
If x(t) = t u(t) and all initial conditions are zero, Y(s) [1 + x] = N(s) [1 – Ge(s).x] + X(s).x
then e(t) will be : from the question, to nullify the effect of noise N(s)
(a) sin t (b) cos t 1 – Ge(s).x = 0
(c) – cos t (d) – sin t 1
DRDO-2009 Ge(s) =
x
Ans. (d) : From the Block diagram - Put the value of x
e(t) = –x(t) + y(t) (i)
s ( s + b )( s + d )
d2 y Ge (s) =
and –e(t) = 2 ⇒ E ( s ) = −s Y ( s )
2
c (s + a )
dt
Take Laplace of equation (i) and put the value of e(t) Y(s)
d2y 119. The transfer function of the linear time
− 2 = −x ( t ) + y ( t ) X(s)
dt variant system shown in figure is :
–s2Y(s) = –X(s) + Y(s)
–s2Y(s) – Y(s) = –X(s)
Y (s ) 1
=
X (s ) s2 + 1
Given, x(t) = t u(t) G1 (s) (G 2 (s) + 1) G 2 (s) (G1 (s) + 1)
1 (a) (b)
X (s) = 2 1 − G1 (s) G 2 (s) 1 − G1 (s) G 2 (s)
s G (s) (G 2 (s) – 1) G 2 (s) (G1 (s) – 1)
 1  1  (c) 1 (d)
Y (s) =  2  2  1 − G1 (s) G 2 (s) 1 − G1 (s) G 2 (s)
 s + 1  s  DRDO-2009
Ans. (b) : Given block diagram can be simplified as - 121. The signal flow graph of the network in figure
is
Y ( s ) G 2 ( s ) (1 + G1 ( s ) ) (a)
=
X ( s ) 1 − G1 ( s ) G 2 ( s )
120. For the flow diagram shown in figure, the
Y (s)
transfer function is (b)
R (s)
(c)
(d)
3
(a) DRDO-2008
s + 6s + 11
2
Ans. (a) : Apply voltage divider rule-
3
(b) 2 Z(s)
s + 5s + 4 E0 (s ) = Ei (s )
1
3 + Z(s)
(c) 2 Y (s)
s + 6s + 8
−3 E0 (s ) Z(s)
(d) 2 =
s + 6s + 11 Ei ( s )  1 
 + Z (s )
 ( )
BSNL(JTO)-2009 Y s 
Y ( s ) ∞ Pk ∆ k
Ans. (a) : Transfer function, =∑ E0 (s ) Y ( s ) .Z ( s )
R ( s ) k =1 ∆ =
E i ( s ) 1 + Y ( s ) .Z ( s )
1 3
Forward path, P1 = × P1∆1 = Y ( s ) .Z ( s )
s +1 s + 4
1 Forward path P1 = Y ( s ) .Z ( s )
Loop, L1 = × −1
s +1 Loop, L1 = –Y(s)Z(s)
1 3 Hence, signal flow graph is-
L2 = × × −1
( s + 1) ( s + 4 )
∆1 = 1, ∆ 2 = 1, ∆ = 1 − ( L1 + L 2 )
 1 3 
∆ = 1 +  + 
 s + 1 ( s + 1)( s + 4 )  122. In transfer function representation, the order
3 of the system is given by
(a) Highest power of ‘s’ in the numerator
Y (s) ( s + 1)( s + 4 )
= polynomial
R (s)
1+
(s + 4) + 3 (b) Highest power of ‘s’ in the denominator
( + 1)( s + 4 )
s polynomial
(c) Number of poles at the origin
Y (s ) 3 3
= = (d) Number of Zeros on the imaginary axis
R ( s ) ( s + 1)( s + 4 ) + s + 7 s 2 + 4s + s + 4 + s + 7 Mizoram PSC IOLM -2018, Paper II
Y (s) 3 Ans. (b) : In control system, the order of the system is
= decided by the highest power of 's' in denominator or by
R ( s ) s 2 + 6s + 11
the degree of characteristic equation.
123. The type number of the control system with 6
(a)
G (S ) H (S ) =
(s + 2) ( s + 6s + 11s + 16 )
3 2
s ( s + 2s + 3 )
2
6
(b)
(a) One
(c) Three
(b) Two
(d) Four (s 3
+ 6s 2 + 11s + 6 )
Nagaland PSC CTSE (Degree)-2017, Paper-II 8
(c)
Ans. (a) : Type of the system is determined by open
loop system.
( s 3
+ 6s 2
+ 11s + 12 )
 5
s  s  (d)
k 1 +  1 +  .....
z1  z 2  ( s + 6s + 11s + 5)
3 2
So, G ( s ) H(s) = 
 s  s  UPPCL AE-05.11.2019
s n 1 + 1 +  .....
 p 1  p 2 
(b) : Differential equation-
If n = 0 → type − 0system d3 y ( t ) d2 y ( t ) dy ( t )
+ 6 ⋅ + 11 + 6y ( t ) = 6.u ( t )
n = 1 → type − 1 system dt 3
dt 2
dt
124. The impulse response of a single –pole system Taking Laplace transform-
would approach a non-zero constant as t → ∞ s3 Y ( s ) + 6s 2 Y ( s ) + 11s Y ( s ) + 6Y ( s ) = 6U ( s )
if and only if the pole is located in the s-plane
(a) On the negative real axis Y ( s ) s3 + 6s 2 + 11s + 6  = 6 U ( s )
(b) At the origin
(c) On the positive real axis Y (s) 6
= 3
(d) On the imaginary axis U ( s ) s + 6s + 11s + 6
2

Ans. (b) : Impulse response of single pole system 127. What will be the transfer function of the given
k block diagram?
C (s) =
s
At t → ∞ response = lims  C ( s ) 
s →0
k
= lims × = k
s →0 s
At t → ∞ the response is non zero at pole lie on the
origin.
(a) (G1G2+G1G3)/(1–G1G2H+G2+G3)
4 1 (b) (G1G2+G1G3)/(1+G1G2H+G2+G3)
3
125. X(s) = 1- 3 +   find no of finite pole and (c) (G1G2–G1G3)/(1–G1G2H–G2+G3)
1+s s-2 (d) (G1+G3)/ (1+G1G2H+G2+G3)
zero ____.
(a) 1, 2 (b) 2, 2
(c) 2, 4 (d) 0, 2 Ans. (b) : Given- block diagram-
NPCIL-2015
4 1
 3
Ans. (b) : X ( s ) = 1 − 3 +  
1+ s s - 2
4 1
( s + 1)( s − 2 ) − ( s − 2 ) + ( s + 1)
= 3 3
( s + 1)( s − 2 ) Forward path gain-
3 ( s + 1)( s − 2 ) − 4 ( s − 2 ) + ( s + 1) P 1 = G 1G 2 , ∆ 1 = 1
= P 2 = G 1G 3 , ∆ 2 = 1
3 ( s + 1)( s − 2 )
Loop gain → l1 = –G1G2H
Number of pole = 2
l2 = – G2
Number of zero = 2
l3 = – G3
126. The transfer function of the state variable
Mason's gain formula
representation of the system given by the
differential equation, y''' + 6y'' + 11y' + 6y = 6u Transfer function = T.F. = P1∆1 + P2 ∆ 2
is: ∆

G1G 2 ×1 + G1G 3 × 1 131. With negative feedback in a closed loop control
= system, the system sensitivity to parameter
1 − ( −G1G 2 H − G 2 − G 3 )
variations
G1 ( G 2 + G3 ) (a) Increases (b) Decreases
T.F. = (c) Become zero (d) Become infinite
1 + G 2 + G 3 + G1G 2 H
128. Find the transfer function of the state variable Ans. (b) : With the negative feedback in a closed loop
representation of the system given by the control system the sensitivity decreases. Negative
differential equation, y'' + 2y' + 4y = 8u . feedback in a control system reduces the overall gain
4 8 also it reduces the sensitivity of output to input
(a) (b)
( s + 2s + 4 )
2
( s + 2s + 4 )
2 variation, distortion and noise reduction.
132. Which of the following is an example of an
2 6 open loop system?
(c) (d)
( s + 2s + 4 )
2
( s + 2s + 4 )
2
(a) household refrigerator
UPPCL AE-05.11.2019 (b) Respiratory system of an animal
(c) Stabilization of air pressure entering into a
Ans. (b) : y"+ 2y '+ 4y = 8u
mask
Taking Laplace transform- (d) execution of a program by a computer.
s 2 Y ( s ) + 2sY ( s ) + 4Y ( s ) = 8u ( s ) TRB Poly. Lect. -2012
Y ( s ) s 2 + 2s + 4 = 8u ( s ) Ans. (d) : In open loop control system the control
action is independent of output.
Y (s ) 8 Example - Traffic signal, bread foster, sprinkler,
= 2
u ( s ) s + 2s + 4 ordinary washing machine and system having no sensor.
133. As compared to closed loop system, an open
 ( s – a )( s – b ) 
129. If, f ( s ) =   the poles of f ( s ) are: loop is
 ( s – c )( s – d )  (a) More stable as well as more accurate
(a) s = a and s = 0 (b) s = c and s = d (b) Less stable as well as less accurate
(c) s = a and s = b (d) s = 0 and s = ∞ (c) More stable but less accurate
(d) Less stable but more accurate
UPPCL AE-05.11.2019
LMRC AM (S&T)-13.05.2018
Ans. (b) : Poles of the system is defined for-
Ans. (c) : As compared to closed loop system, an open
N (s)
F(s) = Where D(s) = 0 loop is more stable but less accurate.
D (s) 134. The signal flow graph of a feed back control
system is given below. The transfer function
( s − c )( s − d ) = 0 ⇒ s = c and d are the poles of the
C(s)
system. of the system is,
R(s)
130. A certain control system is represented by the
following differential equation. Its transfer
d 2 y dy dx
function would be + + 3y = + 2x
dt 2 dt dt
s+2 s+2
(a) (b) 2
s+3 s +s+3 G G − G3 G G − G3
(a) 1 2 (b) 1 2
s2 + 2 1 − G1H 1 + G1H
(c) 2 (d) None of these
s +s+3 G G + G3 G G + G3
Mizoram PSC Jr. Grade -2018, Paper-II (c) 1 2 (d) 1 2
1 + G1H 1 − G1H
Ans. (b) : Given equation-
TNTRB AE– 2017
d 2 y dy dx
+ + 3y = + 2x Ans. (b) : Forward path P1 = G1G 2 ∆1 = 1
dt 2 dt dt
Take Laplace transform- P2 = −G 3 , ∆2 = 1
2
s Y(s) + sY(s) + 3Y(s) = sX(s) + 2X(s) Individual loop L1 = −G1H
Y (s ) s+2 P∆ + P ∆ G G − G3
= T.F = 1 1 2 2 = 1 2
X (s ) s2 + s + 3 ∆ 1 + G1H

Compare this equation with s 2 + 2ξωn s + ω2n = 0
(iii) Time Response Specification
We get ω2n = 3 ⇒ ωn = 3
1. Systems having a finite non-zero steady state and 2ξωn = 3
error to a parabolic input is called as
(a) Type – 0 System (b) Type – 1 System 2× ξ× 3 = 3
(c) Type – 2 System (d) Type – 3 System ξ = 0.866 Qξ < 1
UPPSC Poly. Tech. Lect-22.03.2022, Paper-I Hence given system is underdamped system.
APPSC Poly. Lect.- 15.03.2020
4. Steady state error for unit ramp input and
RPSC Lect. 10.01.2016 Type-I system is -
TNPSC AE- 2019
1
Ans. (c) (a) 0 (b)
Kv
Type Step input Ramp Parabolic
input input (c) ∞ (d) None of the above
Type-0 A/1+K ∞ ∞ SAIL- 2014
Type-1 0 A/k ∞ Ans. (b) : Steady state error for unit ramp input and
Type-2 0 0 A/k 1
Type-I system is
Kv
K .
2. A unity feedback system has G(s) = .
s(s + 10) Type Step input Ramp Parabolic
an open-loop transfer function If the damping input input
ratio is 0.5, then what is the value of K? Type-0 A/1+K ∞ ∞
(a) 150 (b) 100
(c) 50 (d) 10 Type-1 0 A/k ∞
UPPSC Poly. Tech. Lect-22.03.2022, Paper-I Type-2 0 0 A/k
APGENCO AE-23.04.2017 5. A unity feedback system has
GATE-2015, Set-II
K ( 2s + 1)
IES-2014, 2011, 2005 G(s) =
Ans. (b) : Given that, s(4s + 1)(s + 1)2
K What is the value of K if the steady-state value
G(s) = and ξ = 0.5 of error is to be less than 0.1 when an input
s(s + 10) r(t)=1 +5t is applied?
Closed loop transfer function- (a) K = 5 (b) 6 < K < 10
G(s) (c) 11 < K < 40 (d) K > 50
T(s) = ESE-2022
1 + G(s)
UPPSC Poly. (Lect.) - 10.03.2019
K K
T(s) = = 2 K ( 2s + 1)
s(s + 10) + K s + 10s + K Ans. (d) : Open loop T.F.=
s ( 4s + 1)( s + 1)
2
Characteristic equation-
s 2 + 10s + K = 0 For type-1 system –
Compare this with s + 2ξωn s + ωn = 0
2 2 ess = 0 ( step unit )
ω2n = K ⇒ ωn = K A
So, And ess = ( ramp input )
K
and 2ξωn = 10 (Q ξ = 0.5 ) Q r ( t ) = 1 + 5t
2 × 0.5 × K = 10 5
K = 100 ess = 0 + < 0.1
K
3. If the characteristic equation of a closed-loop 5
system is 2s2 + 6s + 6 = 0, then the system is : K>
0.1
(a) overdamped (b) critically damped K>50
(c) underdamped (d) undamped
6. Calculate the peak time of the given system for
UPPSC Poly. Tech. Lect. 22.03.2022, Paper-I
unit step i/p.
IES-2017
Characteristic equation,
2s2 + 6s + 6 = 0
s2 + 3s +3 = 0
2π 2π For sustained oscillation
(a) sec (b) sec 50
3 3 4K − =0
K + 0.5
3 3 50
(c) sec (d) sec 4K =
2π 2π K + 0.5
UPPCL AE-30.03.2022
2K 2 + K = 25
Ans. (a) : Characteristic equation 1 + GH = 0
2K 2 + K − 25 = 0
1
1+ =0 −1 ± 1 + 200
s ( s + 1) =
2× 2
s2 + s + 1 = 0
−1 + 14.17
ωn = 1 K= = 3.3
4
2ξωn = 1
( K + 0.5 ) s 2 = −50
1
ξ= s 2 = −13.16
2
( jω) = −13.16
2
ω = ω 1 − ξ2
d n
1 3 ω2 = 13.16
ωd = 1× 1 − = ω = 3.62rad / s
4 2
π 2π 9. For the given control system, what is the value
Peak time (tp) = = sec. of K so that there is 10% error in the steady
ωd 3 state:
7. Consider a standard second order system given
ωn2
by 2 . The speed of response is
s + 2ζωns + ωn2
measured in time and frequency domain by :
(a) steady-state error, rise time in the time (a) 172 (b) 272
domain and resonant peak in the frequency (c) 572 (d) 672
domain ESE-2022
(b) settling-time, rise-time in the time domain
and bandwidth in the frequency domain K (s + 5)
Ans. (d) : Open loop T.F. =
(c) rise-time in the time domain and bandwidth in s ( s + 6 )( s + 7 )( s + 8 )
the frequency domain For type-1 system, ramp input has finite steady
(d) settling-time, steady state in the time domain
state error.
and bandwidth in the frequency domain
UPPCL AE-30.03.2022 K v = limsG ( s )
s→ 0
ω K (s + 5)
2
Ans. (b) : C ( s ) = 2 n 5K
= lims =
s + 2ξωn s + ω2n x →0 s ( s + 6 )( s + 7 )( s + 8 ) 6× 7×8
ess = lim  r ( t ) − c ( t )  1 10
t →∞ ess = =
The speed of response is measured, in time and K v 100
frequency domain by settling time, rise time in time 6× 7×8 1
domain and Band width in frequency domain. ess = =
5K 10
8. Consider the characteristics equation of a
K = 672
control system given by s3 + (K+0.5)s2 + 4ks +
50 = 0. Find the value of the frequency if the 10. Consider the following statements regarding
system has sustained oscillations for a given K. time response specifications:
(a) ω = 50 rad/sec (b) ω = 25 rad/sec 1. Delay time is the time required for the
(c) ω = 3.63 rad/sec (d) ω = 4.63 rad/sec response to reach 10% to 90% or 5% to
95% or 0% to 100% of its final value.
UPPCL AE-30.03.2022
2. Peak time is the time required for the
Ans. (c) : R-H tabulation- response to reach the first peak overshoot.
s3 1 4K 3. Settling time is the time required for the
s2 K + 0.5 50 response to reach and maintain beyond a
specified tolerance band, i.e., either 3% or
50
s1 4K − 0 5% of the initial value.
K + 0.5 Which of the above statements are not
s0 50 correct?
(a) 1 and 2 only (b) 1 and 3 only −πξ
(c) 2 and 3 only (d) 1, 2 and 3 −1.609 =
ESE-2022 1 − ξ2
Ans. (b) : Delay time (td)- Delay time is the time on squaring of both side we get
required to reach 50% of its final value by a time π2 ξ2
response signal during its first cycle of oscillation. 2.59 =
1 − ξ2
Settling time- Settling time is the time required for the
response to reach up to 3% of the final value. ξ2
= 0.262
11. The open-loop transfer function of a unity 1 − ξ2
feedback system is given by ξ 2 = 0.262 − 0.262ξ 2
K 1.262ξ2 = 0.262
G(s) =
s (τs + 1)
0.262
By what factor should the amplifier gain K be ξ2 =
multiplied so that the damping ratio is 1.262
increased from 0.25 to 0.75? ξ 2 = .207
(a) 0.1111 (b) 1.1111 ξ = 0.456
(c) 0.3333 (d) 3.3333 we know that standard characteristics equation
ESE-2022
s 2 + 2ξωn s + ωn 2 = 0 ....(ii)
Ans. (a) : Relation between damping factor ( ξ ) and on comparing equation (i) and (ii) we get
amplifier gain (K) 2ξωn = 4 + k
1
ξ∝ 2 × .456 kα = 4 + k
K from option (b) we gate value of k.
2
K 2  ξ1   0.25 
2 So,
=   = K2 =   K1 2 × .456 4α = 4 + 4
K1  ξ 2   0.75 
K2= 0.1111K1 8
α=
12. A unity negative feedback system has an open 2 × 0.456 ×2
k α = 4.385
loop transfer function, G (s ) = . α = 19.232
(s + 4)
13. For a second order system, if damping ratio is
s+α less than 1, then system is-
Consider a Cascade compensator Gc(s) = ,
s (a) Over damped (b) Under damped
then what is the value of 'k' and 'α' to achieve (c) Critically damped (d) Undamped
peak overshoot of 20%? UPPSC Poly. Tech. Lect.-22.03.2022, Paper -I
(a) k = 16, α = 29.23 (b) k = 4, α = 19.23 Ans. (b) : For a second order system, if damping ratio
(c) k = 19.23, α = 4 (d) k = 8, α = 4 is less than 1, then system is under damped.
UPPSC Poly. Tech. Lect.-22.03.2022, Paper -I 14. A unity feedback system has open loop transfer
Ans. (b) : Given that, k
k function of G(s) = . The value of ‘k’
G(s) = s(s + 3)
s+4 that yields a damping ratio of 0.5 for the
s+α closed loop system is-
G C (s) = (a) 3 (b) 5
s
(c) 6 (d) 9
So, characteristics equation is 1+ G(s) GC(s) = 0
k(s + α)
1+ =0 Ans. (d) : Close loop characteristic equation
(s + 4) s 1 + GH = 0
s 2 + 4s + ks + kα 1+
k
=0
=0
(s + 4) s s ( s + 3)
s 2 + (4 + k) s + kα = 0 ....(i) s 2 + 3s + k = 0
given 20% overshoot Comparing the characteristic equation
−πξ s 2 + 2ξωn s + ω2n = 0
2
1−ξ
Hence, 0.2 = e ωn = k and 2ξωn = 3
−πξ
ln0.2 = 2 × 0.5 × k = 3
1 − ξ2 k=9
15. For open loop transfer function of a unit 1
l Ans. (a) : G(s) =
feedback is G(s) = , having peak s(s + 1)
s(s + 2) Velocity error constant K v = lims.G(s)
s→0
overshoot 10%. Find damping ratio.
(a) 0.36 (b) 0.60 1
K v = lims.
(c) 0.72 (d) 0.10 s→0 s(s + 1)
UPPSC Poly. Tech. Lect.-22.03.2022, Paper -I = lim1/(1 + s)
s →0
1
Ans. (b) : G ( s ) = K v = 1
s (s + 2) Steady state error due to unit ramp
Peak overshoot = 10% = 0.1 input ess = 1/Kv
πξ
− ess = 1
1−ξ2
Peak overshoot = e
πξ 18. In control system, when maximum value is
−
0.1 = e r1−ξ2 subtracted from step value and result is divided
by step value, result is called.
πξ
l n 0.1 = − (a) % undershoot (b) % overshoot
1 − ξ2 (c) % undamped (d) % overdamped
−πξ RPSC ACF & FRO 23.02.2021
−2.30 =
1 − ξ2 Ans. (b) : Peak over Shoot (Mp)
It gives the normalised difference between steady state
ξ = 0.5511 ≈ 0.60 output to first peak of the time response
16. For a second order closed loop system shown in  πξ
−


figure, the natural frequency (in rad/sec) and  1−ξ2 
%M p = e  
× 100%
damping constants are respectively
19. For a second order as ξ is increased from zero
the response becomes
(a) Zero
(b) Infinity
(a) 2, 1 (b) 1, 2 (c) Progressively less oscillatory
1 (d) Progressively more oscillatory
(c) 4, (d) 4, 1
2 RPSC ACF & FRO 23.02.2021
UPPSC ITI Principal/Asstt. Director-09.01.2022 Ans. (c) : As ξ increases from 0 to 1 then the frequency
Ans. (a) : of oscillation reduces.
For all positive value of ξ system are stable and pole
away from origin called insignificant pole, and does not
affect the stability of system θ = cos -1ξ
4 4 20. Two identical first order systems have been

T.F. = = cascaded non-interactively. The unit step
s ( s + 4 ) + 4 s + 4s + 4 response of the system will be
Compared with s 2 + 2ξωn s + ω2n (a) Over-damped (b) Under-damped
(c) Undamped (d) Critically damped
ω2n = 4 , ωn = 2
And 2ξωn = 4 TSTRANCO AE-2008
ξ =1 Ans. (d) : Two identical first order system have been
cascaded non-interactively. The unit step response of
17. What is the steady state error for a unity the system will be critically damped.
1 For ξ = 1 closed loop poles are real, equal and negative.
feedback control system having G(s) =
s(s + 1) 21. For the following system find peak time and
due to unit ramp input? settling time, respectively.
(a) 1 (b) 0.5 Y (S ) 4
=
(c) 0.25 (d) 0.5 U ( S ) s 2 + 2s + 4
RPSC ACF & FRO-23.02.2021 (a) 1.5 s, 2 s (b) 1.82 s, 3 s
OPSC Poly. Lect. (Instrumentation)-2018, Paper-II (c) 2.82 s, 4 s (d) 0.82 s, 5 s
IES-2005 UPRVUNL AE -19.07.2021, Shift-II
Y(s) 4 23. The unit impulse response of a system is
Ans. (b) : = ….(i) h(t) = e–t, t ≥ 0
U(s) s 2 + 2s + 4
For the system, the steady-state value of the
It is a second-order system. output for unit step input is equal to
Standard second order system is given as- (a) –1 (b) 0
Y(s) ω2n (c) 1 (d) ∞
= 2 ….(ii) APPSC Poly. LECT. 2020
U(s) s + 2ξωn s + ω2n
GPSC Astt. Prof. 11.04.2017, GATE- 2006
Compare equation (i) & (ii)
Ans. (c) : Given unit impulse response of a system is-
ξωn = 1, ω2n = 4 h ( t ) = e− t , t≥0
1
ξ= ωn = 2 H (s) =
1
2 s +1
nπ 1× π 1
Peak time (tp) = = For unit step input- R ( s ) =
ωd ωn 1 − ξ 2 s
1× π C ( s ) = H ( s ) .R ( s )
= = 1.8125
2 1 − 1/ 4 1 1
= ×
3 3 ( s + 1) s
Settling time (ts) = 3T = = = 3sec
ξωn 1 1
=
22. Consider a system with the transfer function s ( + 1)
s
s+6 Apply partial fraction -
G(s) = 2
. Its damping ratio will be 0.5
Ks + s + 6 1 1
C (s) = −
when the value of K is s s +1
(a) 2/6 (b) 3 Taking inverse Laplace transform we get,
(c) 1/6 (d) 6 c ( t ) = (1 − e − t ) u ( t )
APSC Poly. Lect. 14.03.2020
For steady state value put t = ∞
Nagaland PSC CTSE -2015 Paper- II
Mizoram PSC IOLM-2010 Paper-II c ( t ) 1
= 1 − e −∞ = 1 − = 1 − 0
GATE-2002
t =∞
∞
s+6 c ( )
∞ = 1
Ans. (c) : Given transfer function G ( s ) = 2
Ks + s + 6 24. The steady state error of a stable 'type 0' unity
s+6 feedback system for a unit step function is
=
 s 6 1
K  s2 + +  (a) 0 (b)
 K K 1+ Kp
=
(s + 6) / K (c) ∞
1
(d)
 2 s 6 Kp
s + + 
 K K Nagaland Poly. Lect. 15.03.2020
Damping ratio, ξ = 0.5 Nagaland PSC CTSE- 2015, Paper-II
Ans. (b) : Steady state error for type zero system is
ω2n 1
On comparing with ; given by ess =
s 2 + 2ξωn s + ω2n 1+ kP
6 A = magnitude of step signal
ωn =
K kp = lim G ( s ) H ( s )
s →0
1 25. Overall transfer function of a system is given as
2ξωn =
K 2s + 1
G(s) = 2 . The system is characterized
6 1 s + 2s + 5
2 × 0.5 × = as
K K
6 1 (a) Underdamped system
4 × 0.25 × = 2 (b) Undamped system
K K (c) Critical damped system
1
K= (d) Overdamped system
6 NLC GET -24.11.2020
2s + 1 After using partial fraction
Ans. (a) : G ( s ) =
s 2s + 5 2 1 2
C(s) = −
Characteristic equation- s 1+ s
s 2 + 2s + 5 = 0 Taking inverse laplace
Compare above equation with c(t) = u(t) –2e–tu(t)
s 2 + 2ξωn s + ω2n = 0 c(t) = (1–2e–t)u(t)
ω2n = 5 and 2ξωn = 2 28. If Kp = ∞, Kv = finite, Ka = 0, then the type of
1 T.F is _____.
ωn = 5 so ξ = = 0.44 (a) Type 0 (b) Type 1
5
(c) Type 2 (d) None
So, that ξ = 0.44, system is underdamped
26. The Third peak overshoot and second Nagaland PSC CTSE (Degree)-2017, Paper-II
undershoot of the step response of the second
order underdamped system is given by NPCIL-2015
−
3ξπ 2 ξπ Ans. (b) :
−
1−ξ2 1−ξ2 Type Step input Ramp Parabolic
(a) e and e respectively
4 ξπ 5ξπ
input input
− −
1−ξ 2 1−ξ2 0 1 ess = ∞ ess = ∞
(b) e and e respectively ess =
6 ξπ 4 ξπ 1+ kp
−
1−ξ2 1−ξ2
(c) e and e respectively 1 ess = 0 1 ess = ∞
ess =
5ξπ 4 ξπ kv
− −
1−ξ 2 1−ξ 2
(d) e and e respectively 2 ess = 0 ess= 0 1
ess =
ISRO Scientist Engg. -2020 kv
Ans. (d) : As we know
− nπξ
29. For a Type-2 system, the steady-state errors for
1−ξ2 unit step and unit ramp input are :
Peak overshoot (Mp) = e
for 2nd undershoot n = 4 (a) 0 and ∞ (b) ∞ and 0
−4 πξ (c) 0 and 0 (d) ∞ and ∞
1−ξ2 APPSC Poly. Lect.15.03.2020
so, Mp = e
for 3rd peak overshoot n = 5
−5 πξ UPRVUNL AE-11.06.2014
so, Mp = e 1−ξ2 IES-2019, 2007
GATE-1991
27. The unit step response of a system with the
Ans. (c) : For type - 2 system, two poles are at origin.
1−s
transfer function G(s) = is given by which K
1+s Let G(s) = 2
of the following? (A unit step function is s
represented by u (t)). Steady state error for unit step input
(a) (1 − 2e− t )u(t) (b) (1 − e− t )u(t) K
K P = lim G(s) = lim 2 = ∞
(c) e–t u(t) (d) 2e–t u(t) s →0 s→0 s
ISRO Scientist Engg. -2020 1 1

ess = =
Ans. (a) : Given that 1+ KP 1+ ∞
1− s
G(s) = ess = 0
1+ s
for unit step Steady state error for unit ramp input.
1 K
R(s) = K v = Lim s.G(s) = Lim s. 2 = ∞
s s →0 s →0 s
output response
1 1
C(s) = R(s)×G(s) ess = =
Kv ∞
1 1 − s (1 − s )
= × = ess = 0
s 1 + s s (1 + s )

30. If the characteristic equation of a closed-loop 32. For a second order system. damping ratio (ξ),
system is s2 + 2s+ 2= 0, then the system is is 0< ξ<1, then the roots of the characteristic
(a) overdamped (b) critically damped polynomial are
(c) underdamped (d) undamped (a) real but not equal (b) real and equal
Mizoram PSC IOLM-2018 Paper-II (c) complex conjugates (d) imaginary
Nagaland PSC (Degree) -2018 Paper- II GPSC Astt. Prof.- 11.04.2017
Nagaland PSC (Degree) -2017 Paper- II Nagaland PSC CTSE - 2015
GPSC Asst.Prof.-11.04.2017 IES-2005
NIELIT Scientists- 2017 GATE- 1995
UJVANL AE-2016 Ans. (c) : For underdamped system,
Mizoram PSC IOLM-2010 Paper-II
0 < ξ <1
GATE-2001
Standard second order differential equation-
Ans. (c) : Standard second order characteristic
equation- ω2n
= 2
s 2 + 2ξωn s + ωn2 = 0 s + 2ξωn s + ω2n
And given characteristic equation is- Roots are = −ξωn ± jωn 1 − ξ 2 ( for 0 < ξ < 1)
s + 2s + 2 = 0
2
Hence, roots of characteristic polynomial are complex
On comparison- conjugates.
ω2n = 2 33. For a closed-loop system shown in the figure,
ωn = 2 what is the settling time ± for 2% settling of the
steady-state condition, assuming unit-step
2ξωn = 2 input?
ξ = 1/ 2 = 0.707
ξ < 1 ; Hence the system is underdamped.
31. For a second-order system with the closed-loop
9
transfer function T(s)= 2 the settling (a) 0.33s (b) 1.33s
s + 4s + 9
time for 2-percent band, in seconds is (c) 2.33s (d) 3.33s
(a) 1.5 (b) 2.0 TNTRB AE-2017
(c) 3.0 (d) 4.0 Nagaland PSC CTSE (Degree)-2016, Paper-II
IES-2018, 2016, 2015,2013,2012,2010, 1998,1997,1993
RPSC VP/Suptd. ITI-05.11.2019
Nagaland PSC (Degree) 2018, Paper-II Ans. (b) :
GPSC Asst.Prof.-11.04.2017
Nagaland PSC CTSE 2015, Paper-II
Mizoram PSC IOLM-2010 Paper-II
GATE- 1999
Ans. (b) : Given second order system-
25
9 Let G (s) = , H(s) = 1
T (s) = 2 ……………(i) s (s + 6)
s + 4s + 9
Standard second order system- C(s) G(s) 25
= =
ωn
2 R(s) 1 + G(s) s(s + 6) + 25
T (s) = 2 …………(ii)
s + 2ξωn s + ωn2 C(s)
= 2
25
From comparing equation (i) and (ii) we get R(s) s + 6s + 25
ωn = 9 ωn = 3
2 characteristic equation-
s 2 + 6s + 25 = 0
2ξωn = 4
compare C.E. with s 2 + 2ξωn s + ωn2 = 0
4 2
ξ= = We get ω2n = 25 ⇒ ωn = 5
6 3
Settling time for 2% band is given as- 2ξωn = 6
4 ξ = 6 /(2 × 5) = 0.6
ts =
ξωn Settling time for 2% tolerance.
4 4
ts =
4 ts = = = 4/3
ξωn 0.6 × 5
( 2 / 3) × 3
ts = 2 sec t s = 1.33sec

34. A ramp input applied to an unity feedback Ans. (d) : According to question
system results in 5% steady state error. The
type number and zero frequency gain of the ωd ωn 1 − ξ
2
system are respectively = = 1− ξ2

ωn ωn
(a) 1 and 20 (b) 0 and 20
(c) 0 and 1/20 (d) 1 and 1/20 37. A second order system is said to be critically
Nagaland PSC, CTSE (Degree)-2017, Paper-II damped if the damping factor ξ is
ISRO Scientist Engg. - 2016 (a) ξ > 1 (b) ξ < 1
Mizoram PSC IOLM - 2010 Paper -II (c) ξ = 1 (d) ξ = 0.707
GATE-2005
Ans. (a) : Velocity error constant,
Kv = limsG ( s ) = finite
s→0 Ans. (c) : ξ = 1 → critically damped
1 ξ > 1→ Overdamped
ess = 5% = ( Given ) ξ < 1→Underdamped
20
1 1 ξ = 0→ Undamped
∴ =
K v 20 38. As the poles of a network shift away from the
Kv = 20 axis, the response becomes :
Kv is finite for type 1 system. (a) More oscillating (b) Less oscillating
35. Of the following transfer function second order (c) Constant (d) None of these
linear time-invariant systems, the Nagaland PSC CTSE (Degree)- 2016, Paper-I
underdamped system is represented by Ans. (b) : When poles of any closed system shifted
1 1
(a) H ( s ) = 2 (b) H ( s ) = 2 away from the imaginary axis in negative direction,
s + 4s + 4 s + 5s + 4 then value of ξ (damping ratio) decreases. Hence
1 1 system response becomes less oscillating.
(c) H ( s ) = 2 (d) H ( s ) = 2
s + 4.5s + 4 s + 3s + 4 39. The open loop transfer function of a unity
RPSC Vice Principal ITI-2016 K
feedback system is given by . If the
ISRO Scientist Engg.-2007 s ( s + 1)
IES-1998
value of K is such that the system in critically
Ans. (d) : For under damped system ξ< 1
from option (a):- damped, the closed loop poles will lie at
(a) 0.5 ± j 0.5 (b) ± j 0.5
2ξωn = 4
(c) 0 and –1 (d) –0.5
4 4
ξ= = =1 TNPSC AE - 2018
2× 2 4
K K
From option (b):- Ans. (d) : G(s) = T (s) = 2
2ξωn = 5 s(s + 1) s +s+K
5 5 For critically damped system: ξ = 1
ξ= = = 1.25
2× 2 4 2ξ ωn = 1 ωn = K
from option (c):-
2 × 1× K = 1
2ξωn = 4.5
1 1
4.5 K = ,K =
ξ= = 1.125 2 4
2× 2
From option (d):- 1
2ξωn = 3 So, transfer function is T ( s ) = 4
3 2 1
ξ= s +s+
4 4
ξ = 0.75 = 2
1
=
1
From the option (d), the system is underdamped. 4s + 4s + 1 ( 2s + 1)2
36. The ratio of damped frequency to natural Close loop pole is -
frequency of the given system having damping
s = – 0.5, –0.5
factor ξ is hence poles will lie at –0.5.
1
(a) (b) ξ 40. Consider a unity feedback control system
ξ whose open loop transfer function is
(c) ξ 2 (d) 1− ξ2 K
G (s)=
Nagaland PSC CTSE (Degree) 2018, Paper-II s ( Js + F )
Then for unit ramp input steady state error is 42. The unit-step response of a system starting for
given as rest is given by c ( t ) = 1 − e−2t for t ≥0. The
K transfer function of the system is
(a) ess=K (b) ess =
F 1 2
(a) (b)
K F 1 + 2s 2+s
(c) ess = (d) ess = 1 2s
JF K (c) (d)
Nagaland PSC CTSE (Degree)-2016, Paper-II 2 + s 1 + 2s
TNPSC AE-2008 Nagaland PSC CTSE (Degree)-2017, Paper-II
Ans. (d) : Given that , Ans. (b) : Given,
 K  C(t)= 1–e–2t
G ( s ) =   , H ( s ) =1 Take Laplace transform
 s ( Js + F )  1 1
For unit ramp input- C(s) = −
velocity co-efficient s s+2
Kv = limsG(s)H ( s ) 1
for unit step input R(s) =
s →0 s
K K K then,
K v = lim s × 1 = lim =
s→0 s ( Js + F ) s→0 ( Js + F ) ( J × 0 + F) 1 1
−
K C(s) s s + 2 s + 2 − s 2s
Kv = TF = = = =
F R(s) 1 s(s + 2) s(s + 2)
Steady state error for unit ramp input- s  
1
1 1  
ess = = s
Kv K 2
F TF =
s+2
F
ess = 43. s2 – 0.75s + 0.25 is the characteristic equation of
K a second order system. Its response to unit step
41. A transfer function G(s) has pole-zero plot as function will be,
shown in the figure. Given that the steady state (a) Over damped
function gain is 2, the transfer function G(s) (b) Under damped
will be given by (c) Critically damped
(d) Exponential growth
Ans. (d) : Given,
Characteristic equation, s2 – 0.75s + 0.25
( 0.75 )
2
5(s + 1) 2(s + 1) 0.75 ± − 4 ×1× 0.25
(a) 2 (b) 2 Roots of the equation =
s + 4s + 4 s + 4s + 5 2 ×1
10(s + 1) 10(s + 1) = 0.375 ± j 0.10937
(c) 2 (d)
s + 4s + 5 (s + 2)2 The roots of the equation is positive real part that means
ISRO Scientist Engg. 2009 roots lie in RHS. Then the system is unstable and its
Ans. (c) : According to the figure- response to unit step function will be exponential
growth.
K ( s + 1) K ( s + 1)
G(s) = = 44. For a feedback system shown below, If Kt=0
( s + 2 + j)( s + 2 − j) ( s + 2 )2 − j2 and Ka=5, then steady state error for unit ramp
K ( s + 1) input is 0.2. What will be the new value of Kt
G(s) = and Ka if damping ratio is increased to 0.5
s 2 + 4s + 5 without affecting steady state error:
Given, steady state gain = 2
lim G ( s ) = 2
s →0
K ( 0 + 1)
=2
0+0+5
K = 10
10 ( s + 1) (a) Kt= 1.5, Ka=1.25 (b) Kt=1.5, Ka= 12.5
G (s) = 2 (c) Kt=15, Ka=12.5 (d) Kt=15, Ka=1.25
s + 4s + 5
Ans.(b): By using block reduction technique. Then the impulse response to an impulse
strength of 5 is
KA −5t / τ 5K −5t / τ
(a) y(t) = e (b) y(t) = e
τ τ
Transfer function of above block diagram 5K − t / τ KA − t / τ
(c) y(t) = e (d) y(t) = e
2K a τ τ
TNPSC AE - 2018
C(s) s ( s + 2 ) + 2sK t
= Ans. (c) : Given that
R(s) 1 + 2K a
K Y (s)
s ( s + 2 ) + 2sK t G (s) = =
sτ + 1 X ( s )
C (s) 2K a
= ............(i) X(s) = 5
R(s) s 2 + 2s (1 + K t ) + 2K a KX(s)
compare equation (i) with the 2ndorder system Y(s) =
(sτ + 1)
C(s) ω2n 5K
= 2 Y(s) =
R ( s ) s + 2ξωn s + ω2n sτ + 1
ω2n = 2K a 2ξωn =2(1+Kt) Y(s)=
5K
ωn = 2K a ξ=
1+ Kt (
τ s+ 1
τ )
ωn Taking inverse Laplace-
1+ Kt 5K − t / τ
ξ= y(t) = .e
2K a τ
According to the equation . 46. Consider the control system shown in fig and
ξ = 0.5 statements given below the figure.
1+ Kt 1. The system is of second order
so, 0.5 = 2. Basically the system is having negative
2K a feedback
Ka = 2(1+Kt)2 –––––(ii) 3. The system is of type 1
From the above equation (ii) 4. The dimension of the output is not same as
Ka > Kt input of these statements
only option (b) satisfies this condition
Now, the steady state error 9
s(s+3)
 R(s) 
ess = lims  
s→0  1 + G(s)  s2
9
r(t) = tu(t)
1 (a) 2 and 4 correct (b) 1 and 2 correct
R(s) = 2 (c) 2, 3 and 4 correct (d) 1, 2 and 3 correct
s
TNPSC AE - 2018
 1 
  9 s2
s 2 Ans. (a) : (i) Loop gain G ( s ) H ( s ) = .
So, ess = lims   s ( s + 3) 9
s →0  2K a 
 1 + s(s + 2) + 2sK  s
 t  =
Given , ess = 0.2 s+3
Hence type = 0
1  s ( s + 2 ) + 2sK t 
(ii) Characteristic equation -
0.2 = lim  
s→0 s s ( s + 2 ) + 2sK t + 2K a
  1 + G (s) H (s) = 0
2 + 2K t s
0.2 = i.e. 1 + =0
2K a s+3
Ka = 5(1 + Kt)––––(iii) ⇒ 2s + 3 = 0
After solving equation (ii) & (iii) Hence order = 1
Kt = 1.5, Ka = 12.5 (iii) System is negative feedback
45. The transfer function of a first-order process is (iv) Dimension is not same of output & input.
given by 47. The expression for determining the peak
Y (s) K overshoot of a second order–system
= G(s) =
R (s) τs + 1 (a) M P = e − πξ / 1−ξ2
(b) M P = e πξ / 1−ξ2


− πξ

 50. For good response of a second order control
 
πξ / 1−ξ2 1−ξ2  system-
(c) M P = 1 − e (d) M P = 1 − e 
1. higher tp (peak time) is needed

TNPSC AE - 2018
2. the maximum or peak overshoot must be
Ans. (a) : Peak overshoot of a second order system is less
defined as 3. The steady state error(ess) is less
2
M P = e −πξ / 1−ξ 4. The maximum or peak overshoot must be
Where ξ = damping ratio. higher
48. Given the damping ratio ξ = 0.4 and undamped (a) (1), (2), (4) (b) (1), (2)
natural frequency ωn = 5 rad/sec of a second (c) (1), (4) (d) (1), (2) (3)
order system. The transfer function of the UPPCL AE-16.11.2013
system is Ans. (d) : A good control system should have
C (s) 25 (i) low maximum over shoot
(a) = 2
R ( s ) s + 4s + 25 (ii) less steady state error.
(iii) tp should be high.
C (s) 5
(b) = 2 51. For a stable type-1 system, having unit step
R ( s ) s + 4s + 25 input, what is the value of the steady state
C (s) 25 error?
(c) = 2 (a) 4 (b) 2
R ( s ) s + s + 25 (c) 1 (d) 0
C (s) 25 UPSC JWM-2016
(d) =
R ( s ) s 2 + 25s + 25 Ans. (d) : G(s) =
1
TNPSC AE - 2018 s
Ans. (a) : Given that kP = lim G(s) = ∞
s→0
ωn = 5 rad/sec
ξ = 0.4 1 1
ess = = =0
Standard transfer function for second order system- 1+ kP 1+ ∞
ω2n 52. A first order system has a time constant of 20s.
Transfer Function = 2
s + 2ξωn s + ωn 2 It is subjected to a step input. The settling time
52 of the output is assumed to be the time it
T (s) = 2 reaches 95% of its final steady state value. The
s + 2 × 0.4 × 5s + 25 settling time of the system is
25 (a) 100s (b) 50s
T (s ) = 2
s + 4s + 25 (c) 60s (d) 20s
TNPSC AE-2008
49. Consider a unity gain negative feedback system
with open loop transfer function given by Ans. (c) : For first order system–
c(t) = c0(1 – e–t/τ)
300 ( s + 1)
2
G (s) = 0.95 c0 = c0(1 – e–t/τ)

( s + 2 )( s + 5 )( s + 10 ) 1 – e–t/τ = 0.95
If the input to the closed loop system is unit e–t/τ = 0.05
step function then the steady state error is t
(a) 0.50 (b) 0.25 = 2.99 ≈ 3
τ
(c) 0.00 (d) 1.00
UPPCL AE- 31.12.2018 t = 3 × 20 ⇒ t = 60 sec
53. In a critically damped system, the damping
300 ( s + 1)
2
Ans. (b) : G ( s ) = factor is of the order of :

( s + 2 )( s + 5)( s + 10 ) (a) Zero (b) Less than unity
(c) Unity (d) Greater than unity
1
ess = lim Nagaland PSC CTSE (Degree)-2016, Paper-II
300 ( s + 1)
2
s→0
1+ Ans. (c) : For a critically damped system, the value of

( s + 2 )( s + 5 )( s + 10 ) damping factor is strictly unity, known as marginally
1 1 stable system.
ess = = 54. The steady state error of a type 1 second order
1+
300 1+ 3
system to unit ramp input is
2 × 5 × 10
2ξ
ess = 0.25 (a) 2ξ ωn (b)
ωn
(c) 4ξ /ωn (d) None of these 58. A causal system having the transfer function
Nagaland PSC CTSE (Degree)-2016, Paper-II 1
H (s) = is excited with 10u(t). The time
Ans. (b) : For a 2nd order system (s + 2)
ωn 2
at which the output reaches 99% of its steady
G (s) H (s) = So, steady-state error for ramp
s ( s + 2ξωn ) state value is
input. (a) 2.7 sec (b) 2.5 sec
(c) 2.3 sec (d) 2.1 sec
1 1 2ξ
ess = = = Mizoram PSC IOLM-2010, Paper-II
limsG ( s ) H ( s ) ωn ωn 1
s →0
2ξ Ans. (c) : H(s) =
s+2
55. The peak overshoot Mp is a function of r(t) = 10 u(t), R(s) = 10/s
(a) Natural frequency of oscillation ωn only 10
(b) Damping ratio ξ only C(s) =
s(s + 2)
(c) Damped natural frequency ωd only
apply partial fraction
(d) Both (a) and (b)
1 1 
Nagaland PSC CTSE (Degree)-2016, Paper-II C(s) = 5  −
Ans. (b) : The peak overshoot Mp is a function of  s s + 2 
damping ratio only. Taking inverse laplace transform
56. The effect of error rate damping is c(t) = 5 1 − e −2t  u(t)
(a) To reduce steady state error
Steady state value = 5
(b) Delay the response
(c) To provide larger settling time 5(1– e–2t) = 5 × 0⋅99
(d) None of the above 1– e–2t = 0⋅99
–2t
Nagaland PSC CTSE (Degree)-2016, Paper-II e = 0⋅01
Ans. (a) : The effect of error rate damping is to reduce t = 2 ⋅ 3sec
steady state error.
59. Which of the following system is generally
57. The transfer function H(s) of a stable system is preferred
2 2
H(s) = (s + 5s - 9)/(s + 1) (s - 2s + 10) (a) underdamped (b) overdamped
The impulse response is (c) critically damped (d) oscillatory
-t t t
(a) -e u(t)+(e sin 3t + 2e cos 3t u(t)
RPSC Lect.-2011
(b) -e-tu(t)–(et sin 3t + 2et cos 3t u(t)
-t t t Ans. (a) : Under damped system are the most practical
(c) -e u(t)–(e sin 3t + 2e cos 3t u(t)
and most commonly used. An underdamped system
(d) -e-tu(t)+(et sin 3t + 2et cos 3t u(-t)
ensures the system always reaches the desired end state
with same overshoot.
Ans. (a) : Given that
60. If a system is critically damped and gain is
s 2 + 5s − 9 increased, the system
H(s) =
(
( s + 1) s − 2s + 10
2
) (a) becomes overdamped
(b) becomes underdamped
Apply partial fraction -
(c) becomes oscillatory
A Bs + C
H(s) = + ........(i) (d) remains critically underdamped
s + 1 s 2 − 2s + 10 RPSC Vice Principal ITI-2016
after solving
Ans. (b) : If the value of damping = 1
A = –1, B = 2, C = 1
Put the value of A,B and C in equation (i) 1
ξ∝
1 2s + 1 gain
H(s) = − +
s + 1 s 2 − 2s + 10 If gain is increases then the damping ratio is decreases
1 2 ( s − 1) + 3 and system underdamped.
H(s) = − + 61. A system has characteristic equation as s2 + 2s
s + 1 ( s − 1)2 + ( 3)2
+ 8 = 0. The damping ratio and the natural
1 2(s − 1) 3 frequency of oscillation of the system
H(s) = − + + respectively are
s + 1 ( s − 1) + ( 3 )
2 2
( s − 1) + ( 3)
2 2
(a) 2*(2)0.5, 0.5 (b) 0.5, 2*(2)0.5
Taking inverse laplace transform (c) 0.353, 2*(2) 0.5
(d) 2, 0.353
h(t) = –e–tu(t) + [2etcos3t + etsin3t] u(t) RPSC Vice Principal ITI-2016
Ans. (c) : Characteristics equation s 2 + 2s + 8 = 0 take inverse laplace transform-
ωn = 8 = 2.828 5 5 
y(t) =  − 5e − t + e −2 t  u(t)
2× ξ× 2 2 = 2 2 2 
64. In a unity feedback control system, the open-
1
ξ= = 0.3535 loop transfer function is
2 2 K(s + 2)
62. A temperature-sensing device can be modeled G(s) = 2 2
s (s + 7s + 12)
as a first-order system with a time constant of
6s. It is suddenly subjected to a step input of 25 Then the error constant Kp, Kv and Ka,
°C – 150°C. The indicated temperature in 10 s respectively, are :
after the process has started will be : K K
(a) ∞, ∞ and (b) 0,0 and
(a) 118.2°C (b) 126.4°C 6 6
(c) 134.6°C (d) 142.8°C Κ K
IES-2019 (c) ,0 and 0 (d) , ∞ and ∞
6 6
Time constant (τ) = 6 sec IES-2018
final temp (θf) = 150ºC
Initial temp (θi) = 25ºC
Temperature as a function of time for unit step input. K(s + 2)
G(s) = 2 2
θ (t) = final value + (Initial − final) e−t/τ s (s + 7s + 12)
= θf + (θi − θf ) e − t / τ = 150 + (25 − 150) e − t / 6 • Position error constant,
θ (t) = 150 −125e−t/6 K(s + 2)
K p = Lim G(s) = Lim 2 2
Put t = 10 sec s→0 s →0 s (s + 7s + 12)
θ (10 ) = 150 − 125e −10 / 6

Kp = ∞
θ (10) = 126.4º C
• Velocity error constant
63. For the given transfer function K v = Lim s.G(s)
s →0
Y(s) 1
G(s) = = K(s + 2)
R(s) s 2 + 3s + 2 = Lim s ×
The response y(t) for a step input r(t) = 5u(t)
s →0 s (s 2 + 7s + 12)
2
will be Kv = ∞
Where u(t) is a unit step input.
• Acceleration error constant
5 5 
(a)  − 5e − t + e −2t  u(t) K a = Lim s 2 .G(s)
 2 2  s→0
5 −t 
K(s + 2)
(b)  − 5e  u(t) = Lim s 2 ×
2  s →0 s 2 (s 2 + 7s + 12)
 5 5 −2 t  K(s + 2)
(c)  + e  u(t) = Lim 2
2 2  s →0 (s + 7s + 12)
 −t 5 −2 t  Ka = K / 6
(d)  −5e + e  u(t)
 2  65. Settling time is the time required for the system
IES-2019 response to settle within a certain percentage of:
Ans. (a) : Given that, (a) maximum value
Y(s) 1 (b) final value
G(s) = = (c) input amplitude value
R(s) (s 2 + 3s + 2)
(d) transient error value
and r(t) = 5 u(t)
IES-2018
⇒ R (s) = 5/s.
Ans. (b) : Settling time is the time required for the
1 response of the system to settle within a certain
So Y(s) = 2 × R(s)
( s + 3s + 2 ) percentage of final value.
1 5 5 66. A unity feedback system is shown in the figure.
= × = What is the magnitude of K so that the system
( s 2
+ 3s + 2 ) s s(s + 2) (s + 1) is under-damped?
Apply partial fraction -
5 5 5
Y(s) = + −
2s 2(s + 2) (s + 1)

a2 10K /(1 + 10k)
(a) K = 0 (b) K = =
4 10
1+ .s
a2 a2 (1 + 10K)
(c) K < (d) K >
4 4 10
closed loop time constant TCL =
IES-2018 1 + 10K
Ans. (d) : TOL
Q TCL =
20
10 1
= × 10
1 + 10K 20
So, G(s) =
K K = 1.9
s(s + a) 68. The steady-state error for a Type 0 system for
closed loop control system- unit-step input is 0.2. In a certain instance, this
C(s) G(s) K / s(s + a) error possibility was removed by insertion of a
= = unity gain block. Thereafter, a unit ramp was
R(s) 1 + G(s) 1 + K / s(s + a)
applied. The nature of the block and new
C(s) K steady-state error in this changed configuration
=
R(s) s(s + a) + K will, respectively, be :
Characteristic equation- (a) integrator; 0.25 (b) differentiator; 0.25
s2 + a s+K = 0 (c) integrator; 0.20 (d) differentiator; 0.20
Compare this with s 2 + 2ξωn s + ωn2 = 0 IES-2018
Ans. (a) : Steady state error for unit step input-
2ξωn = a , ω2n = K
1
2 × ξ × K = a , ωn = K ess =
1+ KP
For under damped system- Where KP = Position error constant
0<ξ < 1
1
a ⇒ 0.2 =
0< <1 1+ KP
2 K
KP = 4
a
0< < K Now if we insert a unity gain block by which error was
2
completely remove then block is an integrator.
a2 Now, the new open loop transfer function,
0< <K
4 G (s) G(s)H(s)
G(s) = old =
67. The open-loop transfer function of a system is new s s
10K Now, Velocity error constant
1 + 10s K v = Lim s. G new (s)
s →0
When the system is converted into a closed-
loop with unity feedback, the time constant of G(s)H(s)
= Lim s.
the system is reduced by a factor of 20. The s →0 s
value of K is : Kv = Lim G(s) H(s)
s →0
(a) 1.9 (b) 1.6
(c) 1.3 (d) 1.0 Kv = 4
IES-2018
1
Ans. (a) : Given that, Steady state error (ess) =
Open loop transfer function, Kv
10K 1
G(s) = ess = = 0.25
1 + 10s 4
Then time constant (TOL) = 10 10
closed loop transfer function- 69. A control system has G(s) = and H(s) =
G(s) 10K s (s + 5)
T.F. = = K. What is the value of K for which the steady-
1 + G(s) 1 + 10s + 10K
state error for unit-step input is less than 5%?
10K (a) 0.913 (b) 0.927
=
 10s   (c) 0.953 (d) 1.050
(1 + 10k ) 1 +  IES-2017
 (10K + 1)  GATE-1998
Ans. (d) : 71. The unit step input response of a certain
control system is given by c(t) = 1 + 0.2e–60t
– 1.2 e–10t. The undamped natural frequency ωn
and damping ratio ξ are, respectively :
(a) 24.5 and 1.27 (b) 33.5 and 1.27
(c) 24.5 and 1.43 (d) 33.5 and 1.43
IES-2016
1
Ans. (c) : Unit step input response at R ( s ) =
s
C(t) = (1+0.2 e-60t −1.2 e−10t)u (t)
Taking laplace transform-
 1 0.2 1.2 
C(s) =  + − 
 s (s + 60) ( s + 10 ) 
(s + 60)(s + 10) + 0.2s(s + 10) − 1.2s(s + 60)

C(s) =
s(s + 60)(s + 10)
So, open loop transfer function with unity feedback is
Transfer function
G(s)
G '(s) = C(s) (s + 60)(s + 10) + 0.2s(s + 10) − 1.2s(s + 60)
1 + G(s) {H(s) − 1} = =
R(s) (s + 60)(s + 10)
10 / s(s + 5)
G '(s) =  1
10  i.e.as R ( s ) = 
1+ (K − 1)  s
s(s + 5)
∴ Characteristic equation-
10 (s + 60) (s +10) = 0
G '(s) =
s (s + 5) + 10 (K − 1) s2 +70 s+ 600 = 0
Position error constant (Kp) = lim G '(s) Compare this with s 2 + 2ξωn s + ωn2 = 0
s→0
10 we get, ω2n = 600 ⇒ ωn = 600 = 24.49  24.5

K p = lim
s →0 s(s + 5) + 10(K − 1) and 2ξωn = 70
1 2ξ × 600 = 70
Kp =
(K − 1)
ξ = 1.43
1
ess = < 5% (given) 72.
For a unity feedback control system having an
1+ Kp
25
1 open-loop transfer function G(s) = ,
⇒ < 0.05 s(s + 6)
1 what is the time tp at which the peak of the step
1+
(K − 1) input response occurs?
⇒ (K–1)/K < 0.05 (a) 0.52s (b) 2.75s
⇒ K < 1.052 (c) 0.79s (d) 1.57s
IES-2016
70. The largest error between reference input and
output during the transient period is called : Ans. (c) : Given that,
(a) peak error (b) transient overshoot 25
G(s) =
(c) peak overshoot (d) transient deviation s(s + 6)
IES-2017 Closed loop transfer function-
Ans. (c) : The largest (error) between the output and
G(s)
reference input is called peak overshoot. This will T.F. =
occurs in transient period. Peak overshoot time is 1 + G(s)
denoted by MP 25
T.F. = 2
s + 6s + 25
ω2n
compare this with 2
s + 2ξωn s + ω2n
we get ω2n = 25 ⇒ ωn = 5
and 2ξωn = 6

2ξ × 5 = 6 75. The time required for the step response to
ξ = 0.6 decrease and stay within a specified percentage
of its final value is called :
π π
Peak time (tP) = = (a) Delay time (b) Rise time
ωd ωn 1 − ξ 2 (c) Lag time (d) Settling time
π π IES-2015
tp = = Ans. (d) : Settling time is the time required to settle
5 × 1 − 0.62 5 × 0.8 down a system about its steady state or the time
t P = 0.7854 sec required for the step response to decrease and stay
within a specified percentage of its final value (steady
t P = 0.79s
state value).
73. The closed-loop transfer function of a unity feedback 76. When the unit impulse response of a second
C(s) ωn2 1
control system is, = 2 . The order system is e −0.8t sin 0.6t, the natural
R(s) s + 2ξωn s + ωn2
6
velocity error constant of the system is : frequency and damping ratio of the system are
respectively.
ω ω
(a) n (b) n (a) 1 rad/s and 0.8 (b) 0.64 rad/s and 0.8
2ξ ξ (c) 1 rad/s and 1 (d) 0.64 rads and 1
2ωn 3ωn IES-2015
(c) (d)
ξ 2ξ Ans. (a) : Given that,
IES-2016 1
Impulse response C(t) = e −0.8t sin (0.6t).
Ans. (a) : Given that, 6
closed loop transfer function Compare this with standard impulse response of second
ω2n order system Ke −ξωn t sin(ωd t)
= 2
s + 2ξωn s + ωn2 We get,
So, open loop transfer function ξωn = 0.8 ...........(i)
ω2n ωd =0.6
G(s) =
s 2 + 2ξωn s + ωn2 − ωn2 ωn 1 − ξ 2 = 0.6 .........(ii)
ω2n on dividing equation (i) and (ii)
G(s) =
s(s + 2ξωn ) ξ / 1 − ξ2 = 0.8 / 0.6 = 4 / 3
velocity error constant Kv = lims. G(s)
s →0
⇒ ξ = 0.8
ω2n ω2 from equation (i),
K v = lim = n
s→0 ( s + 2ξωn ) 2ξωn ωn = 1
ωn 77.The effects of feedback on stability and
Kv = sensitivity are:
2ξ
(a) Negative feedback improves stability and
74. The transfer function 1/2s+1 will have: system response is less sensitive to external
(a) dc gain 1 and high frequency gain 1 inputs and parameter variations
(b) dc gain 0 and high frequency gain ∞ (b) Feedback does not affect stability but system
(c) dc gain 1 and high frequency gain 0 response is insensitive to disturbances and
parameter variations
(d) dc gain 0 and high frequency gain 1
(c) Feedback does not affect stability and system
IES-2016
response is sensitive to disturbances and
1 parameter variations
Ans. (c) : Given that, transfer function =
2s + 1 (d) Negative feedback affects stability and
For DC gain s = 0 system response is more sensitive to
1 disturbances and parameter variations
DC gain = =1 IES-2015
2 × 0 +1
High frequency gain (put s → ∞ ) Ans. (a) : The effect of negative feedback in a closed
loop system improves the stability of the system and the
 1  1 1
lim 
s →∞ 2s + 1
 = = =0 system response is less sensitive to external input and
  2 × ∞ + 1 ∞ parameter variations.

K But given that steady state value
78. Given that the transfer function G(s) = 2
. = 0.9 of steady state value.
s (1 + sT)
the type and order of this system are respectively. K
⇒ = 0.9 ⇒ K = 0.9(21 + K)
(a) 5 and 2 (b) 2 and 2 21 + K
(c) 2 and 3 (d) 3 and 3 K = 189
IES-2015
81. Derivative feedback is employed in the control
system shown in the figure, to improve its
K
G(s) = 2 damping. If the required damping factor of the
s (1 + sT) system is 0.5, the value of Kd must be adjusted
Poles of this transfer function s= 0, 0, -1/T to:
The number of poles present at the origin is known as type
of system. Hence type of given transfer function is 2.
The total number of poles present in the transfer
function is known as order of the system. Hence order
of given system is 3.
79. When damping ratio is equal to zero, the
damping frequency of a system is: (a) 4 (b) 19
(a) Equal to natural frequency
(c) 0.25 (d) 6
(b) Zero
IES-2013
(c) More than natural frequency
(d) Less than natural frequency Ans. (b) :
IES-2014
damping ratio (ξ) = 0
We know that,
Damping frequency ωd = ωn 1 − ξ 2
ωd = ωn 1 − 0 (Qξ = 0) 1/ s(4s + 1) 1
= ⇒
ωd = ωn 1+
K ds s(4s + 1) + K d s
s(4s + 1)
Where ωn = Natural frequency.
80. A unity feedback system has
K(s + 12)
G(s) = .
(s + 14) (s + 18)
What is the value of K
to yield 10% error in steady state?
(a) 672 (b) 189 C(s) 100 / {s(4s + 1) + K d s}
=
(c) 100 (d) 21 R(s) 1 + 100 / {s(4s + 1) + K d s}
IES-2014 100
K(s + 12) =
Ans. (b) : G(s) = 4s 2 + (K d + 1)s + 100
(s + 14) (s + 18)
C(s) 25
G(s) =
Closed loop transfer function = R(s) (K + 1)
1 + G(s) s2 + d s + 25
4
G(s) Characteristic equation-
T(s) =
1 + G(s) ( K + 1)
s2 + d s + 25 = 0
K(s + 12) 4
T(s) =
(s + 14) (s + 18) + K(s + 12) Compare this with s 2 + 2ξωn s + ωn2 = 0
Steady state value of T(s) ω2n = 25 ⇒ ωn = 5
= lim T(s) 1+ Kd
s →0
and 2ξωn =
K(s + 12) 4
= lim
s →0 (s + 14)(s + 18) + K(s + 12) 1+ Kd
2×0.5×5= {Q ξ = 0.5}
12K K 4
= = K d = 19
14 ×18 + 12K 21 + K
82. Which has one of the following transfer Ans. (c) : Given that,
functions the greatest overshoot? Peak overshoot (MP) = 30% = 0.3
2
(a) 2
9
(b) 2
16 and MP = e −πξ / 1−ξ = 0.3
s + 2s + 9 s + 2s + 16
−πξ / 1 − ξ 2 = −1.204
25 36
(c) 2 (d) 2 ξ 2 = (1 − ξ2 ) × 0.1468
s + 2s + 25 s + 2s + 36
IES-2013 ξ 2 = 0.128 ⇒ ξ = 0.3577
Ans. (d) : We know that, π
Peak time (tP) =
−πξ ωd
2
Peak overshoot M P = e 1−ξ π π
tp = =
i.e, peak overshoot increase with decrease in damping ωn 1 − ξ 2
10 1 − 0.128
ratio.
t P = 0.3364 sec
1
Mp ∝
ξ 84. The type of system which is used for
determination of static error constants is
9 determined from the number of:
• For G(s) = 2
s + 2s + 9 (a) Zeros at origin for open loop transfer
2
characteristics equation , s + 2s + 9 = 0 function.
compare with standard second order equations (b) Poles at origin for open loop transfer function
(c) Zeros at origin for closed loop transfer
s + 2ξωn s + ωn = 0
2 2
function
We get, ω2n = 9 ⇒ ωn = 3 (d) Poles at origin for closed loop transfer
function.
and , 2ξ1ωn = 2 IES-2012
ξ1 = 1/ 3 Ans. (b) : For determination of static error constant we
use the type of system which can be determine by the
16 number of open loop poles at origin.
• For 2 ,
s + 2s + 16 85. The following quantities give a measure of the
transient characteristics of a control system,
ω2n = 16 ⇒ ωn = 4
when subjected to unit step excitation:
2ξ 2 ωn = 2 ⇒ ξ 2 = 1/ 4 1. Maximum overshoot
2. Maximum undershoot
25 3. Overall gain
• For G(s) = 2 , 4. Delay time
s + 2s + 25
5. Rise time
ωn = 25 ⇒ ωn = 5
2
6. Fall time
2 ξ 3 ωn = 2 (a) 1, 3 and 5 (b) 2, 4 and 5
(c) 2, 4 and 6 (d) 1, 4 and 5
ξ3 = 1/ 5 IES-2012
Ans. (d) : Transient characteristic is the measure of
36
• For G(s) = 2 following quantities when unit step input is applied are-
s + 2s + 36 (i) Maximum overshoot
⇒ ω2n = 36 ⇒ ωn = 6 M = e −πξ / 1−ξ
2
P
2 ξ 4 ωn = 2 (ii) Delay time
ξ 4 = 1/ 6 (1 + 0.7ξ )
td =
ωn
36 (iii) Rise time
Hence transfer function has
s + 2s + 36
2
π−φ π−φ π − cos −1 ξ
greatest overshoot. tr = = =
ωd ωn 1 − ξ 2 ωn 1 − ξ 2
83. If the overshoot of the unit-step response of a
second order system is 30%, then the time at 86. For a second order dynamic system, if the
which peak overshoot occurs (assuming ωn = 10 damping ratio is 1 then the poles are:
(a) imaginary and complex conjugate
rad/sec)
(b) in the right-half of s-plane
(a) 0.36 sec (b) 0.363 sec (c) equal, negative and real
(c) 0.336 sec (d) 0.633 sec (d) negative and real
IES-2012 IES-2016, 2012
Ans. (c) : Given that, damping ratio (ξ) = 1 Ans. (b) : From the given block diagram-
Damping ratio is one that means the poles of closed 2
G(s) = 2 and H(s) = 1/s
loop transfer function is equal, negative (left side of s- (s + 2s + 2)
plane) and real. Open loop transfer function = G(s) H(s)
Poles for 2nd order system
2
s1 ,s 2 = −ξωn ± jωn 1 − ξ 2 =
s(s 2 + 2s + 2)
if ξ = 1 then, Hence type of this system is 1.
s1 ,s 2 = −ωn , − ωn 89. Consider a second order all-pole transfer
Equal, negative and real. function model, if the desired settling time
(5%) is 0.60 sec and the desired damping ratio
87. What is the steady-state value of the unit-step
response of a closed-loop control system shown 0.707, where should the poles be located in s-
in figure? plane?
(a) −5 ± j4 2 (b) −5 ± j5
(c) −4 ± j5 2 (d) −4 ± j7
IES-2011
Settling time (ts) = 0.6 (5% tolerance) and
(a) – 0.5 (b) 0 ξ = 0.707
(c) 2 (d) ∞ 3
IES-2011 Q ts = (5% tolerance)
ξωn
Ans. (b) :
3
= 0.6
0.707 × ωn
ωn = 7.072
Poles of transfer function = −ξωn ± jωn 1 − ξ 2
= −(0.707) (7.072) ± j(7.072) 1 − 0.707 2
C(s) 10 /(s + 1) = −5 ± j5
=
R(s) 10 1
1+ × 90.
Two identical first order systems have been
(s + 1) s cascaded non-interactively, the unit step
C(s) 10s response of system is:
= (a) over damped (b) under damped
R(s) s(s + 1) + 10
(c) undamped (d) critically damped
r(t) = u(t)
IES-2011
1 Ans. (d) : When two identical first order system have
⇒ R(s) =
s been cascaded non interactively, the unit step response
10s 1 of the system is critically damped.
So, C(s) = × Transfer function of the first order system is
{s(s + 1) + 10} s 1
Steady state value = lims C(s) T.F =
s →0 1 + sT
10 10s The overall transfer function of two cascaded first order
= lims × = lim
s →0 {s(s + 1) + 10} s→0 s(s + 1) + 10 systems is
1 1 1
Steady state value = 0. T.F = . =
88. The block diagram of a closed-loop control (1 + sT ) (1 + sT ) (1 + sT )2
system is given in figure. What is the type of 1
this system? =
1 + s 2 T 2 + 2sT
1
=
2 2 2 1 
T s + s + 2 
 T T 
1/ T 2
(a) Zero (b) One = 2
1 1
(c) Two (d) Three s2 + 2   s +  
IES-2011 T T
Characteristics equation- We get ω2n = 16 ⇒ ωn = 4
2
1 1 and 2ξωn = 4
s2 + 2   s +   = 0
T T ξ = 1/ 2 = 0.5
Compare with standard second order characteristic π
equation- For first order overshoot tp =
ωd
s 2 + 2ξωn s + ωn 2 = 0
3π
1 1 For second order overshoot tp =
ξωn = , ωn = ωd
T T
ξ = 1 , critically damped π π
Peak time t p = =
ωd ωn 1 − ξ 2
91. From the point of view of stability and response
speed of a closed loop system, the appropriate π π
range for the value of damping ratio has tp = =
between : 4 1 − 0.5 2
4 3/2
(a) 0 to 0.2 (b) 0.4 to 0.7 π
(c) 0.8 to 1.0 (d) 1.1 to 1.5 tp = s
Nagaland PSC (Degree)-2018, Paper -II 2 3
IES-2010 94. The closed loop transfer function of a control
Ans. (b) : For better stability and speed of response of a system has the following poles and zeros
closed loop system the approximate range of damping Poles Zeros
ratio is 0.4 to 0.7. p1 = – 0.05 z1 = – 6
Damping ratio (ξ) = 0 means system is undamped and ξ p2 = 1.0 z2 = – 8
> 1 means system is overdamped and it become p3 = – 5
sluggish in nature. p4 = – 10
92. The transfer function of a linear-time invariant The closed loop response can be closely
system is given as 1/(s+1). What is the steady- approximated by considering which of the
state value of the unit-impulse response? following?
(a) Zero (b) One (a) p1 and p2 (b) p3and p4
(c) Two (d) Infinite (c) p3 and z1 (d) p4 and z2
IES-2008 IES-2008
Ans. (a) : Ans. (a) : With the use of dominant pole concept.
Y(s) 1 Poles p1 and p2 are -0.05 and 1.0 are dominant poles and
Transfer function =
R(s) (s + 1) p3 and p4 are -5 and -10 are far away poles. thus closed
r (t) = unit impulse input loop response can be closely approximated by p1 and p2.
R(s) = 1
1
So Y(s) = 95.
(1 + s)
−t
⇒ y(t) = e
steady state value = lim e − t = limsY ( s ) = 0
t →∞ s →0
A closed loop system is shown in the above
93. A second order control system has a transfer figure.
16 What is the ratio of output frequencies
function 2 . What is the time for the
s + 4s + 16 ω(forK = 32)
first overshoot? ?
ω (for K = 16)
2π π
(a) s (b) s (a) 1.40 (b) 1.42
3 3 (c) 1.44 (d) 1.46
π π IES-2008
(c) s (d) s
2 3 4 3 K
UPPCL AE-16.11.2012 Ans. (c) : G ( s ) = s ( s + 2 )
IES-2008
Ans. (c) : Given transfer function- K
16 s (s + 2)
T.F = 2 Transfer function =
s + 4s + 16 K
1+
Compare this transfer function with standard second s (s + 2)
ω2n K
Order system 2 = 2 .................. (i)
s + 2ξωn s + ωn2 s + 2s + K

1 98. For the unity feedback system with
Input R ( s ) =
s 10
G(s) = 2 , what is the steady state error
K s (s + 4)
C (s) =
s ( s 2 + 2s + K ) resulting from an input 10t?
Apply partial fraction- (a) 10 (b) 1
1 s+2 (c) Zero (d) 1
= − 2 IES-2007
s s + 2s + K
1 s +1 1 Ans. (c) : Given that,
= − − 10
( ) ( )
2 2
s ( s + 1) + K − 1
2
( s + 1)
2
+ K −1 G(s) = 2
s (s + 4)
1 s +1 1
C (s) = − − Input is ramp input with 10 amplitude.
( ) ( )
2 2
s ( s + 1) + K − 1
2
( s + 1)
2
+ K −1 Velocity error constant K v = lim s.G(s)
s→0
Taking inverse laplace transform 10
K v = lim s. 2
e − t sin ( K −1 t ) s→0 s (s + 4)
C ( t ) = u ( t ) − e − t cos ( K −1 t − ) K −1 Kv = ∞
Output frequency ω = K − 1 Steady state error (ess) =
1
=
1
ω ( for K = 32 ) 31 Kv ∞
= = 1.44
ω ( for K = 16 ) 15 ess = 0
96. How can the steady-state error in a system be 99. For second-order system
reduced?
(a) By decreasing the type of system d2y dy
2 2 +4 + 8y = 8x
(b) By increasing system gain dt dt
(c) By decreasing the static error constant What is the damping ratio?
(d) By increasing the input (a) 1 (b) 0.25
IES-2007 (c) 0.333 (d) 0.5
Ans. (b) : The steady state error of a system can be IES-2013, 2007, 1991
reduced by increasing system gain or by increasing the
type of the system or by increasing the static error Ans. (d) : Second-order system-
constant (position, velocity and acceleration). d2 y dy
2 2
+ 4 + 8y = 8x
1 dt dt
↓ess∝
K↑ Take Laplace transform-
97. For second-order system, ξ is equal to zero in 2s 2 Y(s) + 4sY(s) + 8Y(s) = 8X(s)
ωn2 Y(s) {s 2 + 2s + 4} = 4X(s)
s + 2ξωn s + ωn2
2
Which one of the following is correct? Y(s) 4

=
(a) Closed-loop poles are complex conjugate X(s) (s 2 + 2s + 4)
with negative real part Characteristic equation-
(b) Closed-loop poles are purely imaginary
(c) Closed-loop poles are real, equal and negative s 2 + 2s + 4 = 0
(d) Closed-loop poles are real, unequal and Compare this equation with s 2 + 2ξωn s + ωn2 = 0
negative
We get → ω2n = 4 ⇒ ωn = 2
IES-2007
Ans. (b) : Given second order system is and 2ξωn = 2
2 × ξ × 2 = 2 ⇒ ξ = 0.5
2
ω n
=
s + 2ξωn s + ωn2
2
100. What is the value of K for a unity feedback
If ξ is equal to zero, ξ = 0 , → undamped response Κ
system with G(s) = to have a peak
ωn 2 s(1 + s)
Transfer function = overshoot of 50%?
s 2 + ωn 2
(a) 0.53 (b) 5.3
Roots are, s = ± jωn
(c) 0.6 (d) 0.047
then closed loop poles are purely imaginary IES-2006
Ans. (b) : Given that, Ans. (d) : Step response = 1 − e −5t − 5te −5t
K d
G(s) = So, impulse response = (step response)
s(s + 1) dt
1−ξ2
Peak overshoot (MP) = e −πξ / d
= (1 − e −5t − 5te −5t )
50% = e−πξ / 1−ξ2 dt
= 0 − (−5e −5t ) − 5e−5t + 25t e −5t
−0.693 = −πξ / 1 − ξ 2
I.R. = 25te−5t
ξ 2 = (0.04868) (1 − ξ 2 ) Q Transfer function = L [Impulse response]
⇒ ξ = 0.2154 ______(i) = L [25te−5t]
25
Closed loop transfer function- T.F. =
( s + 5)
2
G(s) K
= =
1 + G(s) K + s(1 + s) 25
T.F. =
K s 2 + 10s + 25
T.F = 2
s +s+K Compare the characteristic equation of T.F. with
Compare this with standard equation- s 2 + 2ξωn s + ωn2 = 0
s 2 + 2ξωn s + ωn2 = 0 We get ω2n = 25 ⇒ ωn = 5
ωn = K and 2ξωn = 1 and 2ξωn = 10
2ξ K = 1 2ξ × 5 = 10 ⇒ ξ = 1
1 103. Match List-I (System G(s)) with List-II (Nature
ξ=
2 K of Response) and select the correct answer
from equation ____(i) using the code given below the Lists :
1 List-I List-II
= 0.2154 400
2 K A. 2 1. Undamped
s +12s + 400
K = 5.38 ≈ 5.3
900
101. Consider the following statements: B. 2 2. Critically damped
s + 90s + 900
For the first order transient systems, the time 225
constant is : C. 2 3. Underdamped
1. a specification of transient response. s + 30s + 225
2. reciprocal of real-axis pole location. 625
D. 2 4. Overdamped
3. an indication of accuracy of response. s + 625
4. an indication of speed of the response. Codes :
Which of the statements given above are A B C D
correct? (a) 3 1 2 4
(a) Only 1 and 2 (b) Only 1, 2 and 4 (b) 2 4 3 1
(c) Only 3 and 4 (d) 1, 2, 3 and 4 (c) 3 4 2 1
IES-2006 (d) 2 1 3 4
Ans. (b) : For the first order transient system, the time IES-2005
constant is the specification of transient response or Ans. (c) :
response reaches to its 63.6% of its steady stage value. 400
(i)
Time constant is the reciprocal of real axis pole location
s + 12s + 400
2
for first system or first order system's time constant is
an indication of speed of response For this transfer function-
102. The unit step response of a second order system ω2n = 400 ⇒ ωn = 20
is = 1 – e–5t – 5t e–5t and 2ξωn = 12
Consider the following statements: 2 × ξ × 20 = 12 ⇒ ξ = 0.3 (underdamped).
1. The undamped natural frequency is 5 rad/s.
900
2. The damping ratio is 1. (ii) 2
3. The impulse response is 25 t e –5t s + 90 s + 900
Which of the statements given above are For this transfer function
correct? ω2n = 900 ⇒ ωn = 30
(a) Only 1 and 2 (b) Only 2 and 3 2ξωn = 90
(c) Only 1 and 3 (d) 1, 2 and 3
IES-2006 2ξ × 30 = 90 ⇒ ξ = 1.5 (overdamped)

225 106. Consider the unity feedback system as shown
(iii) below. The sensitivity of the steady state error
s + 30s + 225
2
For this transfer function- to change in parameter K and parameter a

ω2n = 225 ⇒ ωn = 15 with ramp inputs are respectively
2ξωn = 30
2ξ × 15 = 30 ⇒ ξ = 1 (Critically damped)
625
(iv) (a) 1, – 1 (b) – 1, 1
s 2 + 625
For this transfer function- (c) 1, 0 (d) 0, 1
ω2n = 625 ⇒ ωn = 25 IES-2003
Ans. (b) :
2ξ ωn = 0 ⇒ ξ = 0 (Undamped)
104. Which of the following expresses the time at
which second peak in step response occurs for a
second order system?
π 2π Open loop transfer function-
(a) (b)
ωn 1 − ξ 2
ωn 1 − ξ 2 K
G(s) = and H(s) = 1
3π π s(s + a)
(c) (d) Error transfer function-
ωn 1 − ξ 2
1 − ξ2
E(s) 1 1
IES-2005 = =
Ans. (c) : We know that, R(s) 1 + G(s)H(s) 1 + K ×1
nπ nπ s(s + a)
Peak time (t P ) = = Steady state error ess = lim s.E(s)
ωd ωn 1 − ξ2 s→0
for over peak n = 1, 3, 5.......... s.R(s)

for under peak n = 2, 4, 6 ........ ess = lim
s→01 + K / s(s + a)
3π
∴ For second over peak, peak time t p = For ramp input R (s) = 1/s2
ωn 1 − ξ 2 ∴ ess = a / K
105. What is the unit step response of a unity • Sensitivity due to change in K
feedback control system having forward path
K ∂e K ∂
transfer function G(s) =
80
? SeKss = . ss = . (a / K)
s (s + 18) ess ∂ K a / K ∂K
(a) Overdamped (b) Critically damped SeKss = −1
(c) Underdamped (d) Undamped oscillatory
IES-2004 • Sensitivity due to parameter a -
Ans. (a) : Given that, a ∂ess a ∂ (a / K)
80 Seass = . = . =1
G(s) = ess ∂a a/K ∂a
s(s + 18)
107. Assuming unit ramp input, match List-I
G(s)
Closed loop transfer function = (System Type) with List-II (Steady State Error)
1 + G(s)H ( s ) and select the correct answer using the codes
80 given below the lists :
T.F = [H(s) = 1] List-I List-II
s + 18s + 80
2
Characteristic equation- A. 0 1. K
s2 + 18 s + 80 = 0 B. 1 2. ∞
Compare this with s 2 + 2ξωn s + ωn2 = 0 C. 2 3. 0
We get ω2n = 80 ⇒ ωn = 4 5 D. 3 4. 1/K
Codes:
and 2ξωn = 18
A B C D
2ξ × 4 5 = 18 (a) 2 4 3 3
18 9 (b) 1 2 2 4
ξ= =
>1 (c) 2 1 4 3
8 5 4 5
(d) 1 2 4 3
Hence given system is overdamped system.
IES-2003
Ans. (a) : For unit ramp input, only type 1 system gives 111. Match List-I (Pole-zero plot of linear control
steady state error. system) with List-II (Responses of the system)
Velocity error constant (Kv) = lims.G(s). and select the correct answer:
s →0 List-I List-II
1 c
and steady state error = .
Kv
• For type 0, Kv = 0, ess = ∞ A.
1.
t
• For type 1, Kv = K , ess = 1/K
• For type 2, Kv = ∞ , ess = 0
• For type 3, Kv = ∞, ess = 0 c
108. When the time period of observation is large, B. 2.
the type of the error is: t
(a) Transient error (b) Steady state error
(c) Half-power error (d) Position error constant c
IES-2003
Ans. (b) : When the time period of observation is large C. 3. t
then the type of error is steady state error.
109. The unit impulse response of a system having
transfer function K/(s + α) is shown below. The
value of α is: D. 4.
Codes:
A B C D
(a) 4 3 1 2
(b) 4 3 2 1
(a) t1 (b) 1/t1 (c) 3 4 2 1
(c) t2 (d) 1/t2 (d) 3 4 1 2
IES-2003 IES-2002
Ans. (d) : Given that, Ans. (b) : If the poles of transfer function lies in right
Y(s) K side then system is unstable. If poles are complex
H(s) = = conjugate then response is oscillatory in nature.
R(s) (s + α )
for impulse response R(s) = 1
K
so, Y(s) =
(s + α )
y(t) = K e−at
from the given plot- (oscillatory)
• at t = t1, y (t1) = 0.63K
y(t1) = 0.63 K = K e −αt1
⇒ α = .462 / t1
• At t = t2
y(t2) = 0.37 K = K e −αt 2 (unstable)
α = 1/ t 2
110. A system has a single pole at origin. Its impulse
response will be:
(a) constant (b) ramp
(c) decaying exponential (d) oscillatory
IES-2002 (stable)
Ans. (a) : Let the transfer function- 112. Which of the following is the steady state error
H(s) =K/s for a step input applied to a unity feedback
So, it impulse response R(s) = 1 system wi

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ALL INDIA ENGINEERING SERVICES AND

Analog Electronics ............................................................................... 199-502

Electronics Measurements and Instrumentation.............................. 503-636

Note : Network Theory, Electromagnetic Field Theory, Communication System, Advance

S.L. Exam NAME EXAM DATE/TIME No. of Questions

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82. Which of the following statements is true? n0 =

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• In N-type semiconductor we will add pentavalent

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So, fermi level is very closed to valence band.

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9.1× 10−31 which of these statements are correct?

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D = 0.4 × 0.026 Hence, option C is correct.

Electronic Devices & Circuits 48 YCT

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donor impurities include, Arsenic (As), phosphorus (P), 1.6 ×10−19

impurity, it forms a N-type semiconductor. 1

Electronic Devices & Circuits 51 YCT

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indirect Bandgap semiconductor

(a) continuous signal

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Fermi level in intrinsic semiconductor n= =

= 2 ×1016 cm3 N D = 1.64 × 1020 m −3

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which one of the following represents the 1

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YCT Experts Team Electronics & Communication Eng Anand Mahajan Print

YCT Experts Team Electronics & Communication Eng Anand Mahajan Print