1 2 3 4 5
A A
Compal Confidential
ZIVY2/ZIVY3 M/B Schematics Document
B B
Intel Shark Bay + N15P-GX
(Crescent Bay + N15P-GX)
C
LA-B111P C
2014-02-25
REV:1.0
D D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Cover
Document Number
Sheet Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-B111P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 25, 2014 Sheet 1 of 59
1 2 3 4 5
1 2 3 4 5
Compal Confidential
Shark Bay/Crescent Bay
nVidia Intel
PEG 16X DDR3-SO-DIMM X 2
A
N15P-GX Processor DDR3L 1600MHz 1.35V BANK 0, 1, 2, 3
A
VRAM GDDR5 2G/4G +1.35V, +0.675VS
Page 36~45 Dual Channel Page 11, 12
Haswell H
Broadwell H
LCD conn eDP
Page 22
BGA
37.5mmX32mm
HDMI HDMI, DDC Page 4~10
Page 24
+VCC_CORE, +1.35V_CPU_VDDQ
port 8
DMI x4 Touch Panel
Page 22
5GB/s
port 10
BT (NGFF)
B Page 28 B
USB2.0
PCI-e Intel port 4
USB conn x1
(WLAN)
Lynx-Point Right USB Board Page 34
port 2 port 5 port 3
PCH
port 0,1
NGFF Card Reader LAN
2230 Conn. port 1,2
Realtek RTS5249 Realtek GbE USB conn x2
WLAN/BT Left USB Board Page 30
RTL8111GUL USB3.0
Page 28 Page 34
Page 25
USB Board port 9
USB 2.0(BT) Camera Page 22
port 10
DMIC
Digital Array MIC
FCBGA 695 Balls
HM86
SPI ROM SPI 20mmX20mm
8MB
C Page 16 C
S/PDIF
Page 34
Azalia Audio Codec
Realtek ALC283 Page 26 Combo Jack
Page 34
Page 13 ~ 21
port 4 SATA +1.05VS, +1.5VS, +3VS,
2.5" SATA HDD/SDD GEN3 +3V_PCH, +RTCVCC
Speaker Connector
Page 29
DC/DC Interface CKT. Page 26
Page 35
LPC BUS Subwoofer AMP.
Green CLK Subwoofer
TPA3113D2PWPR Page 27 Page 27
SLG3NB304VTR Page 27
Fan Control Touch Pad CONN. ENE KB9022 C Int. KBD
Page 32 Page 32
Page 34 +3VLP
Thermal Sensor page 31 LID switch
D SMSC 1403-2 D
Page 32 Page 33
ZZZ ZZZ0
PCB-MB(DA) PCB-MB(DAZ)
PCB P/N for Load BOM
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
V1.0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom LA-B111P 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 25, 2014 Sheet 2 of 59
1 2 3 4 5
1
Voltage Rails ( O MEANS ON X MEANS OFF ) BOM Structure Table
USB Port Table BTO Item BOM Structure
B+ +5VALW +3V_PCH +1.35V +5VS
45 LEVEL 45@
5 External
USB 2.0 Port USB 3.0 Port Connector CONN@
+3VALW +3VS USB Port
+12VS_PANEL +1.5VS
KB ZIVY2 (15") KB15@
power
0 XHCI 1 Left USB3.0
+1.05VS
UHCI0 KB ZIVY3 (17") KB17@
plane 1 XHCI 2 Left USB3.0
+VCC_CORE
ZIVY2 (15") 15@
2
+0.675VS
UHCI1 ZIVY3 (17") 17@
3
+12VS
EHCI1 Subwoofer WF@
4 Right USB2.0
UHCI2 DIS SKU DIS@
5
Nvidia GC6 state SW@
6
State
UHCI3 Haswell HW@
7
Broadwell BW@
8 Touch screen
UHCI4 Deep S3 DS3@
9 Camera
NO Deep S3 NODS3@
10 WLAN
S0
EHCI2 UHCI5 Green clk support GCLK@
O O O O O 11
No Green clk support NOGCLK@
12
S3
UHCI6 Unpop CMOS@/NCMOS@
O O O O X 13
Unpop @
DeepS3
EMI Pop EMI@
O O X O X EMI unpop @EMI@
Board ID Table for AD channel
S5 S4/AC
ESD Pop ESD@
O O X X X Vcc 3.3V
ESD unpop @ESD@
Ra / Rc 100K +/- 1%
S5 S4/ Battery only Board ID
SATA re-driver TI@/Parade@
O X X X X Rb / Rd V AD_BID min V AD_BID typ V AD_BID max
0 0 0 V 0 V 0 V
S5 S4/AC & Battery 1 12K +/- 1% 0.347 V 0.354 V 0.360 V
don't exist X X X X X
2 15K +/- 1% 0.423 V 0.430 V 0.438 V
3 20K +/- 1% 0.541 V 0.550 V 0.559 V
4 27K +/- 1% 0.691 V 0.702 V 0.713 V
5 33K +/- 1% 0.807 V 0.819 V 0.831 V
A 6 43K +/- 1% 0.978 V 0.992 V 1.006 V A
EC SM Bus1 address EC SM Bus2 address Symbol Note :
Device Address Device Address
Smart Battery Thermal Sensor EMC1403-2-AIZL-TR 1001_101xb
Charger 0b 0001 0010 (0x12H) PCH SML1 Bus address
: means Digital Ground : means Analog Ground
Install below 43 level BOM structure for ver. 0.1
nVidia N15P-GX 0x9E
PCH SM Bus address PCH SML0 Bus address CPU part
Device Address Device Address
CPU1@ CPU3@ CPU4@ CPU5@ CPU6@ CPU7@
DDR DIMM0 1010 000x A0h
R3 R3 R3
DDR DIMM1 1010 010x A4h U1 U1 R1 U1 U1 U1 U1
Click Pad
I5_4200H 2.8G I7_4750HQ 2G I7_4702HQ 2.2G I7_4700HQ 2.4G I7_4850HQ 3.5G I7_4950HQ 3.6G
SA000071N20 SA00007A900 SA00006TQ20 SA00006TP20 SA00007J710 SA00007A800
4319S138L03 V2G 4319S138L04 V4G 4319S138L05 V4G
SMBUS Control Table
Touch Thermal
SOURCE BATT KB9022 SODIMM Pad sensor VGA
SMB_EC_CK1 KB9022
SMB_EC_DA1
+3VLP_EC V X X X X X
PCH
SMBCLK
SMBDATA +3V_PCH X X V
+3VS
V
+3VS
X X
SML0CLK
SML0DATA
PCH
+3V_PCH
X X X X X X
Security Classification Compal Secret Data Compal Electronics, Inc.
SML1CLK
SML1DATA
PCH
+3V_PCH
X V
+3VS
X X V
+3VS
V
+3VS_DGPU
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-B111P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 25, 2014 Sheet 3 of 59
1
5 4 3 2 1
+VCOMP_OUT
PEG_RCOMP 2 1
24.9_0402_1% R1
D D
Note:
Trace width=12 mils ,Spacing=15mils
Max length= 400 mils.
U1A @
HASWELL_BGA_E
AH6 PEG_RCOMP
PEG_RCOMP E10 PEG_CRX_GTX_N15 PEG_CRX_GTX_N[0..15] (36)
DMI_CRX_PTX_N0 AB2 PEG_RXN0 C10 PEG_CRX_GTX_N14
(14) DMI_CRX_PTX_N0 DMI_RXN0 PEG_RXN1
DMI_CRX_PTX_N1 AB3 B10 PEG_CRX_GTX_N13
(14) DMI_CRX_PTX_N1 DMI_RXN1 PEG_RXN2
DMI_CRX_PTX_N2 AC3 E9 PEG_CRX_GTX_N12
(14) DMI_CRX_PTX_N2 DMI_RXN2 PEG_RXN3
DMI_CRX_PTX_N3 AC1 D9 PEG_CRX_GTX_N11
(14) DMI_CRX_PTX_N3 DMI_RXN3 PEG_RXN4 B9 PEG_CRX_GTX_N10
DMI_CRX_PTX_P0 AB1 PEG_RXN5 L5 PEG_CRX_GTX_N9
(14) DMI_CRX_PTX_P0 DMI_RXP0 PEG_RXN6
DMI_CRX_PTX_P1 AB4 L2 PEG_CRX_GTX_N8
(14) DMI_CRX_PTX_P1 DMI_RXP1 PEG_RXN7
DMI_CRX_PTX_P2 AC4 M4 PEG_CRX_GTX_N7
(14) DMI_CRX_PTX_P2 DMI_RXP2 PEG_RXN8
DMI
DMI_CRX_PTX_P3 AC2 L4 PEG_CRX_GTX_N6
(14) DMI_CRX_PTX_P3 DMI_RXP3 PEG_RXN9 M2 PEG_CRX_GTX_N5
DMI_CTX_PRX_N0 AF2 PEG_RXN10 V5 PEG_CRX_GTX_N4
(14) DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 AF4 DMI_TXN0 PEG_RXN11 V4 PEG_CRX_GTX_N3
(14) DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 AG4 DMI_TXN1 PEG_RXN12 V1 PEG_CRX_GTX_N2
(14) DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 AG2 DMI_TXN2 PEG_RXN13 Y3 PEG_CRX_GTX_N1
(14) DMI_CTX_PRX_N3 DMI_TXN3 PEG_RXN14 Y2 PEG_CRX_GTX_N0
DMI_CTX_PRX_P0 AF1 PEG_RXN15 F10 PEG_CRX_GTX_P15 PEG_CRX_GTX_P[0..15] (36)
(14) DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 AF3 DMI_TXP0 PEG_RXP0 D10 PEG_CRX_GTX_P14
(14) DMI_CTX_PRX_P1 AG3 DMI_TXP1 PEG_RXP1 A10
DMI_CTX_PRX_P2 PEG_CRX_GTX_P13
(14) DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 AG1 DMI_TXP2 PEG_RXP2 F9 PEG_CRX_GTX_P12
(14) DMI_CTX_PRX_P3 DMI_TXP3 PEG_RXP3 C9 PEG_CRX_GTX_P11
C PEG_RXP4 A9 PEG_CRX_GTX_P10 C
PEG_RXP5 M5 PEG_CRX_GTX_P9
PEG_RXP6 L1 PEG_CRX_GTX_P8
PEG_RXP7 M3 PEG_CRX_GTX_P7
FDI_CSYMC F11 PEG_RXP8 L3 PEG_CRX_GTX_P6
(14) FDI_CSYMC FDI_INT F12 FDI_CSYNC PEG_RXP9 M1 PEG_CRX_GTX_P5
(14) FDI_INT DISP_INT PEG_RXP10 Y5
PEG
PEG_CRX_GTX_P4
PEG_RXP11 V3 PEG_CRX_GTX_P3
PEG_RXP12 V2 PEG_CRX_GTX_P2
PEG_RXP13 Y4 PEG_CRX_GTX_P1
PEG_RXP14 Y1 PEG_CRX_GTX_P0
PEG_RXP15 B6 2 1DIS@ C1 PEG_PTX_C_DRX_N[0..15] (36)
PEG_PTX_DRX_N15 0.22U_0402_10V6K PEG_PTX_C_DRX_N15
PEG_TXN0 C5 PEG_PTX_DRX_N14 2 1DIS@ C2 PEG_PTX_C_DRX_N14
FDI PEG_TXN1
0.22U_0402_10V6K DGPU
E6 PEG_PTX_DRX_N13 0.22U_0402_10V6K 2 1DIS@ C3 PEG_PTX_C_DRX_N13
PEG_TXN2 D4 PEG_PTX_DRX_N12 0.22U_0402_10V6K 2 1DIS@ C4 PEG_PTX_C_DRX_N12
PEG_TXN3
PEG_TXN4
G4 PEG_PTX_DRX_N11 0.22U_0402_10V6K 2 1DIS@ C5 PEG_PTX_C_DRX_N11 PEG
E3 PEG_PTX_DRX_N10 0.22U_0402_10V6K 2 1DIS@ C6 PEG_PTX_C_DRX_N10
PEG_TXN5 J5 PEG_PTX_DRX_N9 0.22U_0402_10V6K 2 1DIS@ C7 PEG_PTX_C_DRX_N9
PEG_TXN6 G3 PEG_PTX_DRX_N8 0.22U_0402_10V6K 2 1DIS@ C8 PEG_PTX_C_DRX_N8
PEG_TXN7 J3 PEG_PTX_DRX_N7 0.22U_0402_10V6K 2 1DIS@ C9 PEG_PTX_C_DRX_N7
PEG_TXN8 J2 PEG_PTX_DRX_N6 0.22U_0402_10V6K 2 1DIS@ C10 PEG_PTX_C_DRX_N6
PEG_TXN9 T6 PEG_PTX_DRX_N5 0.22U_0402_10V6K 2 1DIS@ C11 PEG_PTX_C_DRX_N5
PEG_TXN10 R6 PEG_PTX_DRX_N4 0.22U_0402_10V6K 2 1DIS@ C12 PEG_PTX_C_DRX_N4
PEG_TXN11 R2 PEG_PTX_DRX_N3 0.22U_0402_10V6K 2 1DIS@ C13 PEG_PTX_C_DRX_N3
PEG_TXN12 R4 PEG_PTX_DRX_N2 0.22U_0402_10V6K 2 1DIS@ C14 PEG_PTX_C_DRX_N2
PEG_TXN13 T4 PEG_PTX_DRX_N1 0.22U_0402_10V6K 2 1DIS@ C15 PEG_PTX_C_DRX_N1
PEG_TXN14 T1 PEG_PTX_DRX_N0 0.22U_0402_10V6K 2 1DIS@ C16 PEG_PTX_C_DRX_N0
PEG_TXN15 C6 2 1DIS@ C17 PEG_PTX_C_DRX_P[0..15] (36)
PEG_PTX_DRX_P15 0.22U_0402_10V6K PEG_PTX_C_DRX_P15
PEG_TXP0 B5 PEG_PTX_DRX_P14 0.22U_0402_10V6K 2 1DIS@ C18 PEG_PTX_C_DRX_P14
PEG_TXP1 D6 PEG_PTX_DRX_P13 0.22U_0402_10V6K 2 1DIS@ C19 PEG_PTX_C_DRX_P13
PEG_TXP2 E4 PEG_PTX_DRX_P12 0.22U_0402_10V6K 2 1DIS@ C20 PEG_PTX_C_DRX_P12
PEG_TXP3 G5 PEG_PTX_DRX_P11 0.22U_0402_10V6K 2 1DIS@ C21 PEG_PTX_C_DRX_P11
B PEG_TXP4 E2 PEG_PTX_DRX_P10 0.22U_0402_10V6K 2 1DIS@ C22 PEG_PTX_C_DRX_P10 B
PEG_TXP5 J6 PEG_PTX_DRX_P9 0.22U_0402_10V6K 2 1DIS@ C23 PEG_PTX_C_DRX_P9
PEG_TXP6 G2 PEG_PTX_DRX_P8 0.22U_0402_10V6K 2 1DIS@ C24 PEG_PTX_C_DRX_P8
PEG_TXP7 J4 PEG_PTX_DRX_P7 0.22U_0402_10V6K 2 1DIS@ C25 PEG_PTX_C_DRX_P7
PEG_TXP8 J1 PEG_PTX_DRX_P6 0.22U_0402_10V6K 2 1DIS@ C26 PEG_PTX_C_DRX_P6
PEG_TXP9 T5 PEG_PTX_DRX_P5 0.22U_0402_10V6K 2 1DIS@ C27 PEG_PTX_C_DRX_P5
PEG_TXP10 R5 PEG_PTX_DRX_P4 0.22U_0402_10V6K 2 1DIS@ C28 PEG_PTX_C_DRX_P4
PEG_TXP11 R1 PEG_PTX_DRX_P3 0.22U_0402_10V6K 2 1DIS@ C29 PEG_PTX_C_DRX_P3
PEG_TXP12 R3 PEG_PTX_DRX_P2 0.22U_0402_10V6K 2 1DIS@ C30 PEG_PTX_C_DRX_P2
PEG_TXP13 T3 PEG_PTX_DRX_P1 0.22U_0402_10V6K 2 1DIS@ C31 PEG_PTX_C_DRX_P1
PEG_TXP14 T2 PEG_PTX_DRX_P0 0.22U_0402_10V6K 2 1DIS@ C32 PEG_PTX_C_DRX_P0
PEG_TXP15
1 OF 12
HSW-QUAD-CORE-GT2_BGA1364
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/7) DMI,FDI,PEG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 4 of 59
5 4 3 2 1
5 4 3 2 1
+VCCIO_OUT Follow Intel schematic
+1.35V
review-0930
Note:
2
U1B @ HASWELL_BGA_E
R3 PECI/THERMTRIP: MISC R174
62_0402_5% C51 BB51 SM_RCOMP0 470_0402_5%
Trace width=4 mils ,Spacing=18mil PROC_DETECT SM_RCOMP0 BB53
DDR3
SM_RCOMP1
SM_RCOMP1
THERMAL
Zo=50 ohm T1 H_CATERR# G50 BB52 SM_RCOMP2
1
G51 CATERR SM_RCOMP2 BE51 H_DRAMRST# R2 1 2
D (31) H_PECI PECI SM_DRAMRST DDR3_DRAMRST# (11,12) D
1 0.1U_0402_16V7K
H_PROCHOT# R4 1 2 H_PROCHOT#_R E50 N53 XDP_PRDY# 0_0402_5%
(31) H_PROCHOT# PROCHOT PRDY T3 C33
56_0402_5% D53 N52 XDP_PREQ# 1 @ESD@ V0.3
(18,45) H_THRMTRIP# THERMTRIP PREQ N54 T2
XDP_TCLK V1.0 @ESD@
TCK M51 XDP_TMS C187 2
TMS M53 XDP_TRST#
JTAG
TRST 100P_0402_50V8J
H_PM_SYNC D52 N49 XDP_TDI 2
(14) H_PM_SYNC PM_SYNC TDI
PWR
H_CPUPWRGD F50 M49 XDP_TDO
(18) H_CPUPWRGD PWRGOOD TDO
PM_SYS_PWRGD_BUF AP48 F53 XDP_DBRESET# ESD 9/5
CPU_PLTRST# L54 SM_DRAMPWROK DBR
1 (18) CPU_PLTRST# PLTRSTIN Place near SODIMM side,
2
R51 XDP_BPM#0
BPM#0 R50 XDP_BPM#1 T4
R5 C188
CLK_CPU_DPLL# AC6 BPM#1 P49 XDP_BPM#2 T5
100P_0402_50V8J (15) CLK_CPU_DPLL# DPLL_REF_CLKN BPM#2 T6
10K_0402_5% 2 @ESD@ CLK_CPU_DPLL AE6 N50 XDP_BPM#3
(15) CLK_CPU_DPLL DPLL_REF_CLKP BPM#3 T7
CLOCK
CLK_CPU_SSC_DPLL# V6 R49 XDP_BPM#4
(15) CLK_CPU_SSC_DPLL# T8
1
CLK_CPU_SSC_DPLL Y6 SSC_DPLL_REF_CLKN BPM#4 P53 XDP_BPM#5
(15) CLK_CPU_SSC_DPLL SSC_DPLL_REF_CLKP BPM#5 T9
CLK_CPU_DMI# AB6 U51 XDP_BPM#6
(15) CLK_CPU_DMI# BCLKN BPM#6 T10
ESD 9/5 CLK_CPU_DMI AA6 P51 XDP_BPM#7
(15) CLK_CPU_DMI BCLKP BPM#7 T11
remove by SIT phase
2 OF 12
HSW-QUAD-CORE-GT2_BGA1364
C C
HASWELL_BGA_E
U1L @
DC_TEST_B3_A3 A3
A4 DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4 DDR3 COMPENSATION SIGNALS
BF51
DAISY_CHAIN_NCTF_BF51 BF52 DC_TEST_BE52_BF52
A51 DAISY_CHAIN_NCTF_BF52 BF53 DC_TEST_BE53_BF53 SM_RCOMP0 R6 1 2 100_0402_1%
DC_TEST_A52_B52 A52 DAISY_CHAIN_NCTF_A51 DAISY_CHAIN_NCTF_BF53
DC_TEST_A53_B53 A53 DAISY_CHAIN_NCTF_A52 C1 DC_TEST_C1_C2 SM_RCOMP1 R8 1 2 75_0402_1%
DAISY_CHAIN_NCTF_A53 DAISY_CHAIN_NCTF_C1 C2 DC_TEST_C1_C2
DAISY_CHAIN_NCTF_C2 C3 DC_TEST_C3_B2 SM_RCOMP2 R9 1 2 100_0402_1%
DC_TEST_C3_B2 B2 DAISY_CHAIN_NCTF_C3
DC_TEST_B3_A3 B3 DAISY_CHAIN_NCTF_B2 C54 DC_TEST_B54_C54
DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_C54 D1
DC_TEST_A52_B52 B52 DAISY_CHAIN_NCTF_D1 Note:
DC_TEST_A53_B53 B53 DAISY_CHAIN_NCTF_B52 D54 Trace width=12~15 mil, Spcing=20 mils
DC_TEST_B54_C54 B54 DAISY_CHAIN_NCTF_B53 DAISY_CHAIN_NCTF_D54
DAISY_CHAIN_NCTF_B54 Max trace length= 500 mils
BC1
BC54 DAISY_CHAIN_NCTF_BC1
DC_TEST_BE1_BD1 BD1 DAISY_CHAIN_NCTF_BC54
DAISY_CHAIN_NCTF_BD1 PU/PD for JTAG signals
B DC_TEST_BE54_BD54 BD54 B
SM_DRAMPWROK with DDR Power Gating Topology DC_TEST_BE1_BD1 BE1 DAISY_CHAIN_NCTF_BD54
DAISY_CHAIN_NCTF_BE1 RSVD
AN35 +3VS
DC_TEST_BE2_BF2 BE2 AN37
DC_TEST_BE3_BF3 BE3 DAISY_CHAIN_NCTF_BE2 RSVD AF9 XDP_DBRESET# R11 2 1 1K_0402_5%
DC_TEST_BE52_BF52 BE52 DAISY_CHAIN_NCTF_BE3 RSVD AE9
+3V_PCH +3V_PCH DC_TEST_BE53_BF53 BE53 DAISY_CHAIN_NCTF_BE52 RSVD G14 +1.05VS
DC_TEST_BE54_BD54 BE54 DAISY_CHAIN_NCTF_BE53 RSVD G17
DC_TEST_BE2_BF2 BF2 DAISY_CHAIN_NCTF_BE54 RSVD AD45 XDP_TMS R12 2 @ 1 51_0402_5%
DC_TEST_BE3_BF3 BF3 DAISY_CHAIN_NCTF_BF2 RSVD AG45 XDP_TDI R13 2 @ 1 51_0402_5%
+1.35V_CPU_VDDQ BF4 DAISY_CHAIN_NCTF_BF3 RSVD RP1
1 DAISY_CHAIN_NCTF_BF4
C192 @ XDP_TDO 1 8
1
0.1U_0402_16V7K XDP_TCLK 2 7
1
DS3@ DS3@ XDP_TRST# 3 6
R153 R152 2 R7 4 5
100K_0402_5% 100K_0402_5% 1.8K_0402_1%
U6 51_0804_8P4R_5%
2
DS3@
2
1 12 OF 12 TMS/TDI no require pull high on Check list
P
(14,31) SYS_PWROK B 4 PM_SYS_PWRGD_BUF HSW-QUAD-CORE-GT2_BGA1364
2 O
(14) PM_DRAM_PWRGD A
G
1 74AHC1G09GW_TSSOP5
3
DS3@ R10
C191 3.3K_0402_1%
0.01U_0402_16V7K
2
2
R70 1 2 0_0402_5%
NODS3@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/7) PM,XDP,CLK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 5 of 59
5 4 3 2 1
5 4 3 2 1
D HASWELL_BGA_E D
U1C @ @
HASWELL_BGA_E
U1D
(11) DDR_A_D[0..63] DDR_A_D0 AH54 BD31 (12) DDR_B_D[0..63]
DDR_A_D1 AH52 SA_DQ0 RSVD BE25 M_CLK_DDR#0 DDR_B_D0 AC54 AY36
DDR_A_D2 AK51 SA_DQ1 SA_CKN0 BF25 M_CLK_DDR0 M_CLK_DDR#0 (11) DDR_B_D1 AC52 SB_DQ0 RSVD AW27 M_CLK_DDR#2
AK54 SA_DQ2 SA_CK0 BE34 DDR_CKE0_DIMMA M_CLK_DDR0 (11) AE51 SB_DQ1 SB_CKN0 AV27 M_CLK_DDR2 M_CLK_DDR#2 (12)
DDR_A_D3 DDR_B_D2
DDR_A_D4 AH53 SA_DQ3 SA_CKE0 BD25 M_CLK_DDR#1 DDR_CKE0_DIMMA (11) DDR_B_D3 AE54 SB_DQ2 SB_CK0 AU36 DDR_CKE2_DIMMB M_CLK_DDR2 (12)
DDR_A_D5 AH51 SA_DQ4 SA_CKN1 BC25 M_CLK_DDR1 M_CLK_DDR#1 (11) DDR_B_D4 AC53 SB_DQ3 SB_CKE0 AW26 M_CLK_DDR#3 DDR_CKE2_DIMMB (12)
DDR_A_D6 AK52 SA_DQ5 SA_CK1 BF34 DDR_CKE1_DIMMA M_CLK_DDR1 (11) DDR_B_D5 AC51 SB_DQ4 SB_CKN1 AV26 M_CLK_DDR3 M_CLK_DDR#3 (12)
AK53 SA_DQ6 SA_CKE1 BE23 DDR_CKE1_DIMMA (11) AE52 SB_DQ5 SB_CK1 AU35 DDR_CKE3_DIMMB M_CLK_DDR3 (12)
DDR_A_D7 DDR_B_D6
DDR_A_D8 AN54 SA_DQ7 SA_CKN2 BF23 DDR_B_D7 AE53 SB_DQ6 SB_CKE1 BA26 DDR_CKE3_DIMMB (12)
DDR_A_D9 AN52 SA_DQ8 SA_CK2 BC34 DDR_B_D8 AU47 SB_DQ7 SB_CKN2 AY26
DDR_A_D10 AR51 SA_DQ9 SA_CKE2 BD23 DDR_B_D9 AU49 SB_DQ8 SB_CK2 AV35
DDR_A_D11 AR53 SA_DQ10 SA_CKN3 BC23 DDR_B_D10 AV43 SB_DQ9 SB_CKE2 BA27
DDR_A_D12 AN53 SA_DQ11 SA_CK3 BD34 DDR_B_D11 AV45 SB_DQ10 SB_CKN3 AY27
DDR_A_D13 AN51 SA_DQ12 SA_CKE3 DDR_B_D12 AU43 SB_DQ11 SB_CK3 AV36
DDR_A_D14 AR52 SA_DQ13 BE16 DDR_CS0_DIMMA# DDR_B_D13 AU45 SB_DQ12 SB_CKE3
DDR_A_D15 AR54 SA_DQ14 SA_CS#0 BC17 DDR_CS1_DIMMA# DDR_CS0_DIMMA# (11) DDR_B_D14 AV47 SB_DQ13 BA20 DDR_CS2_DIMMB#
DDR_A_D16 AV52 SA_DQ15 SA_CS#1 BE17 DDR_CS1_DIMMA# (11) DDR_B_D15 AV49 SB_DQ14 SB_CS#0 AY19 DDR_CS3_DIMMB# DDR_CS2_DIMMB# (12)
DDR_A_D17 AV53 SA_DQ16 SA_CS#2 BD16 DDR_B_D16 BC49 SB_DQ15 SB_CS#1 AU19 DDR_CS3_DIMMB# (12)
DDR_A_D18 AY52 SA_DQ17 SA_CS#3 BC16 M_ODT0 DDR_B_D17 BE49 SB_DQ16 SB_CS#2 AW20
DDR_A_D19 AY51 SA_DQ18 SA_ODT0 BF16 M_ODT1 M_ODT0 (11) DDR_B_D18 BD47 SB_DQ17 SB_CS#3
DDR_A_D20 AV51 SA_DQ19 SA_ODT1 BF17 M_ODT1 (11) DDR_B_D19 BC47 SB_DQ18 AY20 M_ODT2
DDR_A_D21 AV54 SA_DQ20 SA_ODT2 BD17 DDR_B_D20 BD49 SB_DQ19 SB_ODT0 BA19 M_ODT3 M_ODT2 (12)
DDR_A_D22 AY54 SA_DQ21 SA_ODT3 BC20 DDR_A_BS0 DDR_B_D21 BD50 SB_DQ20 SB_ODT1 AV19 M_ODT3 (12)
DDR_A_D23 AY53 SA_DQ22 SA_BS0 BD21 DDR_A_BS1 DDR_A_BS0 (11) DDR_B_D22 BE47 SB_DQ21 SB_ODT2 AW19
DDR_A_D24 AY47 SA_DQ23 SA_BS1 BD32 DDR_A_BS2 DDR_A_BS1 (11) DDR_B_D23 BF47 SB_DQ22 SB_ODT3 AY23 DDR_B_BS0
DDR_A_D25 AY49 SA_DQ24 SA_BS2 DDR_A_BS2 (11) DDR_B_D24 BE44 SB_DQ23 SB_BS0 BA23 DDR_B_BS1 DDR_B_BS0 (12)
DDR_A_D26 BA47 SA_DQ25 BC21 DDR_B_D25 BD44 SB_DQ24 SB_BS1 BA36 DDR_B_BS2 DDR_B_BS1 (12)
BA45 SA_DQ26 VSS BF20 DDR_A_RAS# BC42 SB_DQ25 SB_BS2 AU30 DDR_B_BS2 (12)
DDR_A_D27 DDR_B_D26
DDR_A_D28 AY45 SA_DQ27 SA_RAS BF21 DDR_A_WE# DDR_A_RAS# (11) DDR_B_D27 BF42 SB_DQ26 VSS AV23 DDR_B_RAS#
DDR_A_D29 AY43 SA_DQ28 SA_WE BE21 DDR_A_CAS# DDR_A_WE# (11) DDR_B_D28 BF44 SB_DQ27 SB_RAS AW23 DDR_B_WE# DDR_B_RAS# (12)
C DDR_A_D30 BA49 SA_DQ29 SA_CAS DDR_A_CAS# (11) DDR_B_D29 BC44 SB_DQ28 SB_WE AV20 DDR_B_CAS# DDR_B_WE# (12) C
DDR_A_D31 BA43 SA_DQ30 BD28 DDR_A_MA0 DDR_A_MA[0..15] (11) DDR_B_D30 BD42 SB_DQ29 SB_CAS DDR_B_CAS# (12)
DDR_A_D32 BF14 SA_DQ31 SA_MA0 BD27 DDR_A_MA1 DDR_B_D31 BE42 SB_DQ30 BA30 DDR_B_MA0 DDR_B_MA[0..15] (12)
DDR_A_D33 BC14 SA_DQ32 SA_MA1 BF28 DDR_A_MA2 DDR_B_D32 BA16 SB_DQ31 SB_MA0 AW30 DDR_B_MA1
DDR_A_D34 BC11 SA_DQ33 SA_MA2 BE28 DDR_A_MA3 DDR_B_D33 AU16 SB_DQ32 SB_MA1 AY30 DDR_B_MA2
DDR_A_D35 BF11 SA_DQ34 SA_MA3 BF32 DDR_A_MA4 DDR_B_D34 BA15 SB_DQ33 SB_MA2 AV30 DDR_B_MA3
DDR_A_D36 BE14 SA_DQ35 SA_MA4 BC27 DDR_A_MA5 DDR_B_D35 AV15 SB_DQ34 SB_MA3 AW32 DDR_B_MA4
DDR_A_D37 BD14 SA_DQ36 SA_MA5 BF27 DDR_A_MA6 DDR_B_D36 AY16 SB_DQ35 SB_MA4 AY32 DDR_B_MA5
DDR_A_D38 BD11 SA_DQ37 SA_MA6 BC28 DDR_A_MA7 DDR_B_D37 AV16 SB_DQ36 SB_MA5 AT30 DDR_B_MA6
DDR_A_D39 BE11 SA_DQ38 SA_MA7 BE27 DDR_A_MA8 DDR_B_D38 AY15 SB_DQ37 SB_MA6 AV32 DDR_B_MA7
DDR_A_D40 BC9 SA_DQ39 SA_MA8 BC32 DDR_A_MA9 DDR_B_D39 AU15 SB_DQ38 SB_MA7 BA32 DDR_B_MA8
DDR_A_D41 BE9 SA_DQ40 SA_MA9 BD20 DDR_A_MA10 DDR_B_D40 AU12 SB_DQ39 SB_MA8 AU32 DDR_B_MA9
DDR_A_D42 BE6 SA_DQ41 SA_MA10 BF31 DDR_A_MA11 DDR_B_D41 AY12 SB_DQ40 SB_MA9 AU23 DDR_B_MA10
DDR_A_D43 BC6 SA_DQ42 SA_MA11 BC31 DDR_A_MA12 DDR_B_D42 BA10 SB_DQ41 SB_MA10 AY35 DDR_B_MA11
DDR_A_D44 BD9 SA_DQ43 SA_MA12 BE20 DDR_A_MA13 DDR_B_D43 AU10 SB_DQ42 SB_MA11 AW35 DDR_B_MA12
DDR_A_D45 BF9 SA_DQ44 SA_MA13 BE32 DDR_A_MA14 DDR_B_D44 AV12 SB_DQ43 SB_MA12 AU20 DDR_B_MA13
DDR_A_D46 BE5 SA_DQ45 SA_MA14 BE31 DDR_A_MA15 DDR_B_D45 BA12 SB_DQ44 SB_MA13 AW36 DDR_B_MA14
DDR_A_D47 BD6 SA_DQ46 SA_MA15 DDR_B_D46 AY10 SB_DQ45 SB_MA14 BA35 DDR_B_MA15
BB4 SA_DQ47 AJ52 DDR_A_DQS#0 DDR_A_DQS#[0..7] (11) AV10 SB_DQ46 SB_MA15
DDR_A_D48 DDR_B_D47
DDR_A_D49 BC2 SA_DQ48 SA_DQSN0 AP53 DDR_A_DQS#1 DDR_B_D48 AU8 SB_DQ47 AD52 DDR_B_DQS#0 DDR_B_DQS#[0..7] (12)
DDR_A_D50 AW3 SA_DQ49 SA_DQSN1 AW52 DDR_A_DQS#2 DDR_B_D49 BA8 SB_DQ48 SB_DQSN0 AU46 DDR_B_DQS#1
DDR_A_D51 AW2 SA_DQ50 SA_DQSN2 AY46 DDR_A_DQS#3 DDR_B_D50 AV6 SB_DQ49 SB_DQSN1 BD48 DDR_B_DQS#2
DDR_A_D52 BB3 SA_DQ51 SA_DQSN3 BD12 DDR_A_DQS#4 DDR_B_D51 BA6 SB_DQ50 SB_DQSN2 BD43 DDR_B_DQS#3
DDR_A_D53 BB2 SA_DQ52 SA_DQSN4 BE7 DDR_A_DQS#5 DDR_B_D52 AV8 SB_DQ51 SB_DQSN3 AW16 DDR_B_DQS#4
DDR_A_D54 AW4 SA_DQ53 SA_DQSN5 BA3 DDR_A_DQS#6 DDR_B_D53 AY8 SB_DQ52 SB_DQSN4 AW10 DDR_B_DQS#5
DDR_A_D55 AW1 SA_DQ54 SA_DQSN6 AT2 DDR_A_DQS#7 DDR_B_D54 AU6 SB_DQ53 SB_DQSN5 AW8 DDR_B_DQS#6
DDR_A_D56 AU3 SA_DQ55 SA_DQSN7 AW39 DDR_B_D55 AY6 SB_DQ54 SB_DQSN6 AL2 DDR_B_DQS#7
AU1 SA_DQ56 RSVD AJ53 DDR_A_DQS0 DDR_A_DQS[0..7] (11) AM2 SB_DQ55 SB_DQSN7 BE38
DDR_A_D57 DDR_B_D56
DDR_A_D58 AR1 SA_DQ57 SA_DQS0 AP52 DDR_A_DQS1 DDR_B_D57 AM3 SB_DQ56 RSVD AD53 DDR_B_DQS0 DDR_B_DQS[0..7] (12)
DDR_A_D59 AR4 SA_DQ58 SA_DQS1 AW53 DDR_A_DQS2 DDR_B_D58 AK1 SB_DQ57 SB_DQS0 AV46 DDR_B_DQS1
DDR_A_D60 AU2 SA_DQ59 SA_DQS2 BA46 DDR_A_DQS3 DDR_B_D59 AK4 SB_DQ58 SB_DQS1 BE48 DDR_B_DQS2
DDR_A_D61 AU4 SA_DQ60 SA_DQS3 BE12 DDR_A_DQS4 DDR_B_D60 AM1 SB_DQ59 SB_DQS2 BE43 DDR_B_DQS3
B DDR_A_D62 AR2 SA_DQ61 SA_DQS4 BD7 DDR_A_DQS5 DDR_B_D61 AM4 SB_DQ60 SB_DQS3 AW15 DDR_B_DQS4 B
DDR_A_D63 AR3 SA_DQ62 SA_DQS5 BA2 DDR_A_DQS6 DDR_B_D62 AK2 SB_DQ61 SB_DQS4 AW12 DDR_B_DQS5
SA_DQ63 SA_DQS6 AT3 DDR_A_DQS7 DDR_B_D63 AK3 SB_DQ62 SB_DQS5 AW6 DDR_B_DQS6
+SM_VREF AM6 SA_DQS7 AW40 SB_DQ63 SB_DQS6 AL3 DDR_B_DQS7
+SM_VREF SM_VREF RSVD SB_DQS7
+SA_DIMM_VREFDQ +SA_DIMM_VREFDQ AR6 BD38
+SB_DIMM_VREFDQ AN6 SA_DIMM_VREFDQ BA40 RSVD
+SB_DIMM_VREFDQ SB_DIMM_VREFDQ RSVD AY40 BF39
BC53 RSVD BA39 RSVD BE39
RSVD RSVD AY39 RSVD BF37
RSVD AV40 RSVD BE37
RSVD AU40 RSVD BD39
RSVD AV39 RSVD BC39
RSVD AU39 RSVD BC37
RSVD RSVD BD37
RSVD
3 OF 12
HSW-QUAD-CORE-GT2_BGA1364 4 OF 12
HSW-QUAD-CORE-GT2_BGA1364
A A
Security Classification Compal Secret Data
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(3/7) DDRIII
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 6 of 59
5 4 3 2 1
5 4 3 2 1
D D
COMPENSATION PU FOR eDP
+VCOMP_OUT
HASWELL_BGA_E
U1J @
EDP_COMP 2 1
24.9_0402_1% R14
TMDS_B_DATA2#_PCH C25 F15 EDP_CPU_AUX#
(24) TMDS_B_DATA2#_PCH D25 DDIB_TXN0 EDP_AUXN F14 EDP_CPU_AUX# (22)
TMDS_B_DATA2_PCH EDP_CPU_AUX Note:
(24) TMDS_B_DATA2_PCH TMDS_B_DATA1#_PCH A25 DDIB_TXP0 EDP_AUXP E14 EDP_HPD# EDP_CPU_AUX (22)
(24) TMDS_B_DATA1#_PCH DDIB_TXN1 EDP_HPD
(24) TMDS_B_DATA1_PCH
TMDS_B_DATA1_PCH B25
DDIB_TXP1
Trace width=20 mils ,Spacing=25mil,
HDMI TMDS_B_DATA0#_PCH C24 C14 EDP_CPU_LANE_N0
(24) TMDS_B_DATA0#_PCH TMDS_B_DATA0_PCH D24 DDIB_TXN2 EDP_TXN0 A12 EDP_CPU_LANE_N1 EDP_CPU_LANE_N0 (22) Max length=100 mils.
(24) TMDS_B_DATA0_PCH TMDS_B_CLK#_PCH A24 DDIB_TXP2 EDP_TXN1 D14 EDP_CPU_LANE_P0 EDP_CPU_LANE_N1 (22)
(24) TMDS_B_CLK#_PCH TMDS_B_CLK_PCH B24 DDIB_TXN3 EDP_TXP0 B12 EDP_CPU_LANE_P1 EDP_CPU_LANE_P0 (22)
(24) TMDS_B_CLK_PCH DDIB_TXP3 EDP_TXP1 EDP_CPU_LANE_P1 (22)
C21 AG6 EDP_COMP
D21 DDIC_TXN0 EDP_RCOMP E12 T14
A21 DDIC_TXP0 EDP_DISP_UTIL
B21 DDIC_TXN1 C12 EDP_CPU_LANE_N2
C C20 DDIC_TXP1
DDIC_TXN2
FDI_TXN0
FDI_TXP0
D12 EDP_CPU_LANE_P2 EDP_CPU_LANE_N2
EDP_CPU_LANE_P2
(22)
(22)
HPD INVERSION FOR EDP C
D20 A14 EDP_CPU_LANE_N3
A20 DDIC_TXP2 FDI_TXN1 B14 EDP_CPU_LANE_P3 EDP_CPU_LANE_N3 (22) +VCCIO_OUT
B20 DDIC_TXN3 FDI_TXP1 EDP_CPU_LANE_P3 (22)
DDIC_TXP3
10K_0402_5%
R15 2
C16
D16 DDID_TXN2
A16 DDID_TXP2
B16 DDID_TXN3
DDID_TXP3
1
EDP_HPD#
1
C17
D17 DDID_TXN0 Q1
OUT
A17 DDID_TXP0
B17 DDID_TXN1
DDID_TXP1 2
IN EDP_HPD (22)
GND
100K_0402_5%
10 OF 12 DTC124EKAT146_SC59-3
R16 1
HSW-QUAD-CORE-GT2_BGA1364 V1.0
@
2
B B
HPD is a active-high signal from device.
The HPD processor input is
active-low signal.
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(4/7) eDP,DP and HDMI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 7 of 59
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor
CFG2
2
R17
D 1K_0402_1% D
1
HASWELL_BGA_E
U1K @ PEG Static Lane Reversal - CFG2 is for the 16x
F1
RSVD_TP E1
RSVD_TP 1: Normal Operation; Lane # definition matches
BE4 A5 CFG2
BD3 RSVD_TP RSVD_TP A6 socket pin map definition
RSVD_TP RSVD_TP
F6 R54 CFG_RCOMP 0:Lane Reversed
G6
G21
RSVD_TP
RSVD_TP
CFG_RCOMP
CFG16
CFG18
Y52
V53
Y51
CFG16 T15
*
G24 RSVD_TP CFG17 V52 CFG4
H_CPU_RSVD F21 RSVD_TP CFG19
TESTLO_F21
1
G19 B50
F51 VSS RSVD AH49
F52 VSS RSVD AM48 R18
F22 VSS RSVD AU27 1K_0402_1%
+VCC_CORE VCC RSVD AU26
2
L52 RSVD BD4
L53 RSVD_TP RSVD BC4
RSVD_TP RSVD AL6
L51 RSVD F8
RSVD_TP RSVD Embedded Display Port Presence Strap
F24
F25 RSVD_TP
C RSVD_TP 1 : Disabled; No Physical Display Port C
H_CPU_TESTLO F20 CFG4
TESTLO_F20 attached to Embedded Display Port
CFG0 AG49 F16
T16 CFG1 AD49 CFG0 RSVD
0 : Enabled; An external Display Port device is
T17
T18
CFG2
CFG3
AC49
AE49
Y50
CFG1
CFG2
CFG3
* connected to the Embedded Display Port
CFG4
CFG5 AB49 CFG4
CFG6 V51 CFG5 G12
CFG7 W51 CFG6 RSVD_TP G10 CFG5
Y49 CFG7 RSVD_TP
Y54 CFG8 H54 CFG6
T19 Y53 CFG9 VSS H53
CFG10 VSS
2
W53
U53 CFG11 H51 @ R22 R23 @
V54 CFG12 VSS H52 1K_0402_1% 1K_0402_1%
R53 CFG13 VSS
R52 CFG14 N51
1
CFG15 RSVD G53
L50 RSVD H50
L49 RSVD RSVD
E5 RSVD
RSVD
11 OF 12 PCIE Port Bifurcation Straps
HSW-QUAD-CORE-GT2_BGA1364
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
B
01: Reserved - (Device 1 function 1 disabled ; function B
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
1 2 H_CPU_TESTLO
R19 49.9_0402_1%
1 2 CFG_RCOMP CFG7
R20 49.9_0402_1%
1 2 H_CPU_RSVD
2
R21 49.9_0402_1%
@ R24
1K_0402_1%
1
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB
CFG7 * de assertion
0: PEG Wait for BIOS for training
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(5/7) RSVD,CFG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 8 of 59
5 4 3 2 1
5 4 3 2 1
+1.35V_CPU_VDDQ Source +1.35V +1.35V_CPU_VDDQ +1.35V +1.35V_CPU_VDDQ
Note: JP@ JP1
C37 @
Intel Shark Bay 2 1 0.1U_0402_16V7K
1 2
Removed the S3 power reduction circuit. JUMP_43X118
JP@ JP2 C36 @
0.1U_0402_16V7K
2 1 1 2
JUMP_43X118
D D
@ +VCC_CORE
HASWELL_BGA_E +VCC_CORE +VCC_CORE
U1E
U1F @ HASWELL_BGA_E
J17 B43
+1.35V_CPU_VDDQ J21 RSVD VCC B45 AB45 H33
J26 RSVD VCC B46 AB46 VCC VCC H34
J31 RSVD VCC B48 AB8 VCC VCC H36
RSVD VCC C27 AC46 VCC VCC H37
AR29 VCC C28 AC47 VCC VCC H38
+VCC_CORE AR31 VDDQ VCC C31 AC8 VCC VCC H39
VCC_SENSE AR33 VDDQ
VDDQ
VCC
VCC
C32 AC9 VCC
VCC
VCC
VCC
H40
AT13 C34 AD46 H42
VDDQ VCC VCC VCC
100_0402_1%
Note: AT19 C36 AD8 H43
1 AT23 VDDQ VCC C38 AE46 VCC VCC H45
0 ohm Resistor should be placed VDDQ VCC VCC VCC
R27 AT27
VDDQ VCC
C39 AE47
VCC VCC
H46
AT32 C42 AE8 H48
cloose to CPU AT36 VDDQ VCC C43 AF8 VCC VCC H8
AV37 VDDQ VCC C45 AG46 VCC VCC H9
2
AW22 VDDQ VCC C46 AG8 VCC VCC J10
@ AW25 VDDQ VCC C48 AH46 VCC VCC J14
VCCSENSE 1 2 VCCSENSE_R AW29 VDDQ VCC D27 AH47 VCC VCC J19
(55) VCCSENSE AW33 VDDQ VCC D28 AH8 VCC VCC J24
R25 0_0402_5%
AY18 VDDQ VCC D31 AJ45 VCC VCC J29
@ BB21 VDDQ VCC D32 AJ46 VCC VCC J33
VSSSENSE 1 2 VSSSENSE_R BB22 VDDQ VCC D34 AK46 VCC VCC J36
(55) VSSSENSE VSSSENSE_R (10) VDDQ VCC VCC VCC
R28 0_0402_5% BB26 D36 AK47 J37
BB27 VDDQ VCC D38 AK8 VCC VCC J38
VDDQ VCC VCC VCC
1
100_0402_1%
BB30 D39 AL45 J39
BB31 VDDQ VCC D42 AL46 VCC VCC J40
VDDQ VCC VCC VCC
R26
BB34 D43 AL8 J42
BB36 VDDQ VCC D45 AL9 VCC VCC J43
BD22 VDDQ VCC D46 AM46 VCC VCC J45
2
BD26 VDDQ VCC D48 AM47 VCC VCC J46
BD30 VDDQ VCC E27 AM8 VCC VCC J48
BD33 VDDQ VCC E28 AM9 VCC VCC J8
BE18 VDDQ VCC E31 AN10 VCC VCC J9
C C
BE22 VDDQ VCC E32 AN12 VCC VCC K38
BE26 VDDQ VCC E34 AN13 VCC VCC K40
BE30 VDDQ VCC E36 AN14 VCC VCC K43
BE33 VDDQ VCC E38 AN15 VCC VCC K44
VDDQ VCC E39 AN16 VCC VCC K45
AN31 VCC E42 AN17 VCC VCC K46
L6 RSVD VCC E43 AN19 VCC VCC K48
+VCC_CORE VCC VCC VCC VCC
M6 E45 AN20 K8
AN22 VCC VCC E46 AN21 VCC VCC K9
AN18 RSVD VCC E48 AN23 VCC VCC L37
RSVD VCC F27 AN24 VCC VCC L38
Broadwell/Haswell VCCSENSE_R C50 VCC F28 AN25 VCC VCC L39
+VCCIO_OUT 0_0805_5% AH9 VCC_SENSE VCC F31 AN26 VCC VCC L40
R29 2 1 +VCCIO_OUT_R D51 RSVD VCC F32 AN27 VCC VCC L42
+VCCIO_OUT VCCIO_OUT VCC VCC VCC
Note: +PCH_VPROC R56 2 1 +PCH_VPROC_R F17 F34 AN29 L43
BW@ 0_0603_5% AK6 FC_F17 VCC F36 AN30 VCC VCC L44
+VCOMP_OUT VCOMP_OUT VCC VCC VCC
1
Place the UP resistor close to CPU V0.3 AN33
RSVD VCC
F38 AN32
VCC VCC
L46
R30 V1.0 W9 F39 AN34 L47
75_0402_1% J12 RSVD VCC F42 AN36 VCC VCC L8
AR49 RSVD VCC F43 AN38 VCC VCC M37
RSVD VCC F45 AN39 VCC VCC M38
2
R31 1 2 43_0402_5% H_CPU_SVIDALRT# J53 VCC F46 AN40 VCC VCC M39
(55) VR_SVID_ALRT# VIDALERT VCC VCC VCC
VR_SVID_CLK J52 F48 AN41 M40
(55) VR_SVID_CLK J50 VIDSCLK VCC G27 AN42 VCC VCC M42
VR_SVID_DAT
(55) VR_SVID_DAT VIDSOUT VCC VCC VCC
G29 AN43 M43
B51 VCC G31 AN44 VCC VCC M44
VSS VCC VCC VCC
1
Note: +1.05VS 2 R33 1 F19 G32 AN45 M45
R32 150_0402_1% E52 PWR_DEBUG VCC G34 AN46 VCC VCC M46
VSS VCC VCC VCC
2
Place the UP resistor close to CPU 130_0402_1% V49
RSVD_TP VCC
G36 AN8
VCC VCC
M8
U49 G38 AN9 M9
R34 AM49 RSVD_TP VCC G39 AP10 VCC VCC N37
2
10K_0402_5% W49 RSVD_TP VCC G42 AP12 VCC VCC N38
@ V50 RSVD_TP VCC G43 AP13 VCC VCC N39
1
+VCCIO_OUT AN49 VSS VCC G45 AP14 VCC VCC N40
AJ49 VSS VCC G46 AP15 VCC VCC N42
AG50 VSS VCC G48
Broadwell/Haswell AP16 VCC VCC N43
AK49 VSS VCC H11 +1.05VS AP17 VCC VCC N44
B +VCCIO_OUT AJ50 VSS VCC H12 AP18 VCC VCC N46 B
AP49 VSS VCC H13 AP19 VCC VCC N47
AB50 VSS VCC H14 AP20 VCC VCC N8
VSS VCC VCC VCC
1
2.2U_0603_10V6K
AP50 H16 R35 AP21 N9
VSS VCC VCC VCC
C38
1 AD50 H17 0_0805_5% AP22 P45
AM50 VSS VCC H18 BW@ AP23 VCC VCC P46
VSS VCC H19 AP24 VCC VCC P8
A36 VCC H20 AP25 VCC VCC R46
+VCC_CORE
2
2 A38 VCC VCC H21 AP26 VCC VCC R47
VCC VCC VCC VCC
10U_0603_6.3V6M
A39 H23 1 1 AP27 R8
VCC VCC VCC VCC
0.1U_0402_16V7K
C39 BW@
C40 @
A42 H24 AP29 R9
A43 VCC VCC H25 AP30 VCC VCC T45
A45 VCC VCC H26 AP31 VCC VCC T46
A46 VCC VCC H27 2 2 AP32 VCC VCC U46
A48 VCC VCC H29 AP33 VCC VCC U47
AA46 VCC VCC
VCCST AP34 VCC VCC U8
AA47 VCC AP35 VCC VCC U9
VDDQ DECOUPLING (Follow INTEL DG) AA8 VCC
VCC FC_D5
D5 FC_D5 AP36 VCC
VCC
VCC
VCC
V45
AA9 D3 FC_D3 2 R36 1 AP37 V46
VCC FC_D3 PCH_PWROK (14,31) VCC VCC
+1.35V_CPU_VDDQ AP38 V8
VCC VCC
1
5 OF 12 2K_0402_1% AP39 W46
Close to CPU Close to CPU Close to CPU HSW-QUAD-CORE-GT2_BGA1364 R37 BW@ AP40 VCC VCC W47
1K_0402_1% AP41 VCC VCC W8
BW@ AP42 VCC VCC Y45
VCC VCC
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
AP43 Y46
2
VCC VCC
220U_D2_4VM_R15
330U_D2_2V_Y
1 1 1 1 1 1 1 1 1 1 1 1 AP44 Y8
VCC VCC
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
AP46 A27
VCC VCC
C52
+ + AP47 A28
@ @ @ AP8 VCC VCC A31
2 2 2 2 2 @ 2 2 2 @ 2 2 @ AP9 VCC VCC A32
2 2 AR35 VCC VCC A34
AR37 VCC VCC B27
V0.1A V0.3A V0.3A V0.1A AR39 VCC VCC B28
AR41 VCC VCC B31
V0.3A AR43 VCC VCC B32
AR45 VCC VCC B34
AR46 VCC VCC B36
H30 VCC VCC B38
A A
H31 VCC VCC B39
VCC VCC
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
H32 B42
VCC 6 OF 12 VCC
1 1 1 1 1 1 1 1 1 1 1
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
HSW-QUAD-CORE-GT2_BGA1364
@ @ @
2 2 @ 2 2 2 2 2 2 @ 2 2 2 @
V0.3A V0.3A
Security Classification Compal Secret Data
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
V0.1A
Close to CPU Close to CPU PROCESSOR(6/7) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 9 of 59
5 4 3 2 1
5 4 3 2 1
HASWELL_BGA_E HASWELL_BGA_E
U1I @ U1H @
HASWELL_BGA_E
U1G @
BC10 G20 AT40 AY50
BC12 VSS VSS G23 A11 AJ48 AT42 VSS VSS AY9
BC15 VSS VSS G25 A15 VSS VSS AJ51 AT43 VSS VSS B11
BC18 VSS VSS G26 A19 VSS VSS AJ54 AT45 VSS VSS B15
BC22 VSS VSS G30 A22 VSS VSS AK48 AT46 VSS VSS B19
BC26 VSS VSS G33 A26 VSS VSS AK5 AT47 VSS VSS B22
BC3 VSS VSS G37 A30 VSS VSS AK50 AT49 VSS VSS B26
BC30 VSS VSS G40 A33 VSS VSS AK7 AT5 VSS VSS B30
D BC33 VSS VSS G44 A37 VSS VSS AK9 AT50 VSS VSS B33 D
BC36 VSS VSS G49 A40 VSS VSS AL1 AT51 VSS VSS B37
BC38 VSS VSS G52 A44 VSS VSS AL4 AT52 VSS VSS B40
BC41 VSS VSS G54 AA1 VSS VSS AL48 AT53 VSS VSS B44
BC43 VSS VSS G7 AA2 VSS VSS AL5 AT54 VSS VSS B49
BC46 VSS VSS G8 AA3 VSS VSS AL7 AT6 VSS VSS B8
BC48 VSS VSS G9 AA4 VSS VSS AM5 AT8 VSS VSS BA13
BC5 VSS VSS H44 AA48 VSS VSS AM51 AT9 VSS VSS BA18
BC50 VSS VSS H49 AA5 VSS VSS AM52 AU13 VSS VSS BA22
BC52 VSS VSS H7 AA7 VSS VSS AM53 AU18 VSS VSS BA25
BC7 VSS VSS J44 AB5 VSS VSS AM54 AU22 VSS VSS BA29
BD10 VSS VSS J49 AB51 VSS VSS AM7 AU25 VSS VSS BA33
BD15 VSS VSS J51 AB52 VSS VSS AN1 AU29 VSS VSS BA37
BD18 VSS VSS J54 AB53 VSS VSS AN2 AU33 VSS VSS BA4
BD36 VSS VSS J7 AB54 VSS VSS AN3 AU37 VSS VSS BA42
BD41 VSS VSS K1 AB7 VSS VSS AN4 AU42 VSS VSS BA5
BD46 VSS VSS K2 AB9 VSS VSS AN48 AU5 VSS VSS BA50
BD5 VSS VSS K3 AC48 VSS VSS AN5 AU9 VSS VSS BA51
BD51 VSS VSS K4 AC5 VSS VSS AN50 AV1 VSS VSS BA52
BE10 VSS VSS K5 AC50 VSS VSS AN7 AV13 VSS VSS BA53
BE15 VSS VSS K6 AC7 VSS VSS AP51 AV18 VSS VSS BA9
BE36 VSS VSS K7 AD48 VSS VSS AP54 AV2 VSS VSS BB10
BE41 VSS VSS L48 AD51 VSS VSS AP7 AV22 VSS VSS BB11
BE46 VSS VSS L7 AD54 VSS VSS AR12 AV25 VSS VSS BB12
BF10 VSS VSS L9 AD7 VSS VSS AR14 AV29 VSS VSS BB14
BF12 VSS VSS M48 AD9 VSS VSS AR16 AV3 VSS VSS BB15
BF15 VSS VSS M50 AE1 VSS VSS AR18 AV33 VSS VSS BB16
BF18 VSS VSS M52 AE2 VSS VSS AR20 AV4 VSS VSS BB17
BF22 VSS VSS M54 AE3 VSS VSS AR24 AV42 VSS VSS BB18
BF26 VSS VSS M7 AE4 VSS VSS AR26 AV5 VSS VSS BB20
BF30 VSS VSS N48 AE48 VSS VSS AR48 AV50 VSS VSS BB23
BF33 VSS VSS N7 AE5 VSS VSS AR5 AV9 VSS VSS BB25
C BF36 VSS VSS P1 AE50 VSS VSS AR50 AW13 VSS VSS BB28 C
BF38 VSS VSS P2 AE7 VSS VSS AR7 AW18 VSS VSS BB32
BF41 VSS VSS P3 AF5 VSS VSS AR8 AW37 VSS VSS BB33
BF43 VSS VSS P4 AF6 VSS VSS AR9 AW42 VSS VSS BB37
BF46 VSS VSS P48 AF7 VSS VSS AT1 AW43 VSS VSS BB38
BF48 VSS VSS P5 AG48 VSS VSS AT10 AW45 VSS VSS BB39
BF7 VSS VSS P50 AG5 VSS VSS AT12 AW46 VSS VSS BB41
C11 VSS VSS P52 AG51 VSS VSS AT15 AW47 VSS VSS BB42
C15 VSS VSS P54 AG52 VSS VSS AT16 AW49 VSS VSS BB43
C19 VSS VSS P6 AG53 VSS VSS AT18 AW5 VSS VSS BB44
C22 VSS VSS P7 AG54 VSS VSS AT20 AW50 VSS VSS BB46
C26 VSS VSS R48 AG7 VSS VSS AT22 AW51 VSS VSS BB47
C30 VSS VSS R7 AG9 VSS VSS AT25 AW54 VSS VSS BB48
C33 VSS VSS T48 AH1 VSS VSS AT26 AW9 VSS VSS BB49
C37 VSS VSS U1 AH2 VSS VSS AT29 AY13 VSS VSS BB5
C4 VSS VSS U2 AH3 VSS VSS AT33 AY22 VSS VSS BB6
C40 VSS VSS U3 AH4 VSS VSS AT35 AY25 VSS VSS BB7
C44 VSS VSS U4 AH48 VSS VSS AT37 AY29 VSS VSS BB9
C49 VSS VSS U48 AH5 VSS VSS AT39 AY33 VSS VSS
C52 VSS VSS U5 AH50 VSS VSS AT4 AY37 VSS
C8 VSS VSS U50 AH7 VSS VSS AY42 VSS
D11 VSS VSS U52 VSS 7 OF 12 VSS 8 OF 12
D15 VSS VSS U54 HSW-QUAD-CORE-GT2_BGA1364 HSW-QUAD-CORE-GT2_BGA1364
D19 VSS VSS U6
D22 VSS VSS U7
D26 VSS VSS V48
D30 VSS VSS V7
D33 VSS VSS V9
D37 VSS VSS W48
D40 VSS VSS W50
D44 VSS VSS W52
D49 VSS VSS W54
B D8 VSS VSS W7 B
E11 VSS VSS Y48
E15 VSS VSS Y7
E16 VSS VSS Y9
E17 VSS VSS
E19 VSS AR22
E20 VSS VSS AB48
E21 VSS VSS P9
E22 VSS VSS G18
E24 VSS VSS
E25 VSS A49
E26 VSS VSS_NCTF A50
E30 VSS VSS_NCTF A8
E33 VSS VSS_NCTF B4
E37 VSS VSS_NCTF BA1
E40 VSS VSS_NCTF BA54
E44 VSS VSS_NCTF BB1
E49 VSS VSS_NCTF BB54
E51 VSS VSS_NCTF BD2
E53 VSS VSS_NCTF BD53
E8 VSS VSS_NCTF BF49
F2 VSS VSS_NCTF BF5
F26 VSS VSS_NCTF BF50
F3 VSS VSS_NCTF BF6
F30 VSS VSS_NCTF C53
F33 VSS VSS_NCTF D2
F37 VSS VSS_NCTF E54
F4 VSS VSS_NCTF F54
F40 VSS VSS_NCTF G1
F44 VSS VSS_NCTF
F49 VSS D50
F5 VSS VSS_SENSE VSSSENSE_R (9)
A G11 VSS A
G13 VSS
G16 VSS
VSS
9 OF 12
HSW-QUAD-CORE-GT2_BGA1364
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(7/7) VSS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 10 of 59
5 4 3 2 1
5 4 3 2 1
+1.35V +1.35V
3A@1.35V
(6) DDR_A_D[0..63]
DDR3 SO-DIMM A (6) DDR_A_DQS[0..7]
JDIMM1 CONN@
+VREF_DQ_DIMMA 1 2 (6) DDR_A_DQS#[0..7]
3 VREF_DQ VSS 4 DDR_A_D4
VSS DQ4 (6) DDR_A_MA[0..15]
2.2U_0603_10V6K
0.1U_0402_16V7K
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5
C64
C65
1 1 DDR_A_D1 7 8
9 DQ1 VSS 10 DDR_A_DQS#0
11 VSS DQS0# 12 DDR_A_DQS0
V0.3A @ 13 DM0 DQS0 14
2 2 DDR_A_D6 15 VSS VSS 16 DDR_A_D3
D DDR_A_D2 17 DQ2 DQ6 18 DDR_A_D7 D
19 DQ3 DQ7 20
DDR_A_D12 21 VSS VSS 22 DDR_A_D8
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS VSS 28
Layout Note:
DDR_A_DQS1 29 DQS1# DM1 30 DDR3_DRAMRST#
Layout Note: Place near JDIMM1
31 DQS1 RESET# 32 DDR3_DRAMRST# (12,5) Place near JDIMM1
DDR_A_D14 33 VSS VSS 34 DDR_A_D11
DDR_A_D10 35 DQ10 DQ14 36 DDR_A_D15
37 DQ11 DQ15 38
DDR_A_D16 39 VSS VSS 40 DDR_A_D17 +0.675VS +1.35V
DDR_A_D20 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS VSS 46
DQS2# DM2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
DDR_A_DQS2 47 48
DQS2 VSS
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
49 50 DDR_A_D22 1 1 1 1 1 1 1 1 1 1 1 1
VSS DQ22
C70
C71
C72
C73
C74
C75
C76
C77
C78
C79
C80
C81
DDR_A_D18 51 52 DDR_A_D23 1 1 1 1
DQ18 DQ23
C66
C67
C68
C69
DDR_A_D19 53 54 @ @
55 DQ19 VSS 56 DDR_A_D30
DDR_A_D26 57 VSS DQ28 58 DDR_A_D25 2 2 2 2 2 2 2 2 2 2 2 2
DDR_A_D24 59 DQ24 DQ29 60 2 @2 2 @2
61 DQ25 VSS 62 DDR_A_DQS#3
63 VSS DQS3# 64 DDR_A_DQS3
65 DM3 DQS3 66
DDR_A_D29 67 VSS VSS 68 DDR_A_D28
DDR_A_D31 69 DQ26 DQ30 70 DDR_A_D27
71 DQ27 DQ31 72
VSS VSS Place near JDIMM1 pin203 pin204
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
(6) DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA (6)
75 76
C 77 VDD VDD 78 DDR_A_MA15 C
DDR_A_BS2 79 NC A15 80 DDR_A_MA14
(6) DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5
VDD
A4
VDD
94 CPU DRIVER
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 97
99
A3
A1
A2
A0
98
100
DDR_A_MA0 VREF PATH IS
VDD VDD +SM_VREF +1.35V *M3+M1:Default Recommendation
(6) M_CLK_DDR0
(6) M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#0
101
103 CK0 CK1
102
104
M_CLK_DDR1
M_CLK_DDR#1 M_CLK_DDR1 (6) DEFAULT M1:VREF_DQ driven by a voltage Divider Network during
105 CK0# CK1# 106 M_CLK_DDR#1 (6)
VDD VDD Note: Processor power-off state.
2
DDR_A_MA10 107 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 (6)
(6) DDR_A_BS0 DDR_A_BS0 109
BA0 RAS#
110 DDR_A_RAS#
DDR_A_RAS# (6)
VREF trace width:20 mils at least R38 M3:VREF_DQ driven by Processor.
111 112 1K_0402_1%
DDR_A_WE# 113 VDD VDD 114 DDR_CS0_DIMMA# Spacing:20mils to other signal/planes
(6) DDR_A_WE# WE# S0# DDR_CS0_DIMMA# (6)
DDR_A_CAS# 115 116 M_ODT0
(6) DDR_A_CAS# M_ODT0 (6)
1
117 CAS# ODT0 118 R39
DDR_A_MA13 119 VDD VDD 120 M_ODT1 1 2 +VREF_CA
DDR_CS1_DIMMA# 121 A13 ODT1 122 M_ODT1 (6) +VREF_CA (12)
(6) DDR_CS1_DIMMA# 2.2_0402_1%
S1# NC
2
0.022U_0402_16V7K
C82
123 124
125 VDD VDD 126 +VREF_CA R40
127 TEST VREF_CA 128 @ 1K_0402_1%
1 2
VSS VSS
0.1U_0402_16V7K
2.2U_0603_10V6K
DDR_A_D33 129 130 DDR_A_D36 V0.3A
DQ32 DQ36
C83
C84
DDR_A_D32 131 132 DDR_A_D37 1 1
1
133 DQ33 DQ37 134 R41
DDR_A_DQS#4 135 VSS VSS 136
DQS4# DM4 24.9_0402_1%
DDR_A_DQS4 137 138 @ @
139 DQS4 VSS 140 DDR_A_D38 2 2 V0.3A
2
B DDR_A_D34 141 VSS DQ38 142 DDR_A_D39 B
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS 146 DDR_A_D44
DDR_A_D45 147 VSS DQ44 148 DDR_A_D40
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDR_A_DQS#5
153 VSS DQS5# 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D42 157 VSS VSS 158 DDR_A_D46
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
161 DQ43 DQ47 162 +SA_DIMM_VREFDQ +1.35V
DDR_A_D48 163 VSS VSS 164 DDR_A_D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168
VSS VSS
2
DDR_A_DQS#6 169 170
DDR_A_DQS6 171 DQS6# DM6 172
Note: R42
173 DQS6 VSS 174 DDR_A_D54 VREF trace width:20 mils at least
VSS DQ54 1K_0402_1%
DDR_A_D50 175 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178 Spacing:20mils to other signal/planes
1
179 DQ51 VSS 180 DDR_A_D60
DDR_A_D56 181 VSS DQ60 182 DDR_A_D61 1 R43 2 +VREF_DQ_DIMMA
DDR_A_D57 183 DQ56 DQ61 184 2.2_0402_1%
DQ57 VSS
2
0.022U_0402_16V7K
C85
185 186 DDR_A_DQS#7
187 VSS DQS7# 188 DDR_A_DQS7 R44
189 DM7 DQS7 190 @ 1K_0402_1%
1 2
DDR_A_D62 191 VSS VSS 192 DDR_A_D63 V0.3A
DDR_A_D58 193 DQ58 DQ62 194 DDR_A_D59
1
195 DQ59 DQ63 196 R45 @
197 VSS VSS 198
SA0 EVENT# 24.9_0402_1%
199 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 (12,16,32)
2.2U_0603_10V6K
0.1U_0402_16V7K
201 202 SMB_CLK_S3
SMB_CLK_S3 (12,16,32)
2
SA1 SCL
C86
C87
1 1 203 204
A VTT VTT +0.675VS A
205 206 0.65A@0.675V
@ 207 GND1 GND2 208
V0.3A 2 2 BOSS1 BOSS2
LCN_DAN06-K4406-0103
SP07000LT00
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 11 of 59
5 4 3 2 1
5 4 3 2 1
3A@1.35V
+1.35V +1.35V (6) DDR_B_D[0..63]
(6) DDR_B_DQS[0..7]
JDIMM2 CONN@
+VREF_DQ_DIMMB 1 2
3 VREF_DQ VSS1 4 DDR_B_D5 (6) DDR_B_DQS#[0..7]
DDR_B_D0 5 VSS2 DQ4 6 DDR_B_D1
DDR_B_D4 7 DQ0 DQ5 8 (6) DDR_B_MA[0..15]
DQ1 VSS3
2.2U_0603_10V6K
0.1U_0402_16V7K
9 10 DDR_B_DQS#0
VSS4 DQS#0
C90
C91
1 1 11 12 DDR_B_DQS0
13 DM0 DQS0 14
DDR_B_D2 15 VSS5 VSS6 16 DDR_B_D6
@ DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
D V0.3A 2 2 19 DQ3 DQ7 20 D
DDR_B_D15 21 VSS7 VSS8 22 DDR_B_D8
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D14
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS9 VSS10 28
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
31 DQS1 RESET# 32 DDR3_DRAMRST# (11,5) Layout Note:
DDR_B_D12 33 VSS11 VSS12 34 DDR_B_D11 Place near JDIMM2
DDR_B_D10 35 DQ10 DQ14 36 DDR_B_D13
37 DQ11 DQ15 38
DDR_B_D21 39 VSS13 VSS14 40 DDR_B_D16
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D20 +0.675VS
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS15 VSS16 46
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D19
VSS18 DQ22
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
DDR_B_D23 51 52 DDR_B_D18
DDR_B_D22 53 DQ18 DQ23 54
DQ19 VSS19 1 1 1 1
C92
C93
C94
C95
55 56 DDR_B_D25
DDR_B_D28 57 VSS20 DQ28 58 DDR_B_D29
DDR_B_D24 59 DQ24 DQ29 60 @
61 DQ25 VSS21 62 DDR_B_DQS#3 2 2 2 @2
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D26 67 VSS23 VSS24 68 DDR_B_D30
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31
71 DQ27 DQ31 72
VSS25 VSS26 Place near JDIMM2 pin203 pin204
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
(6) DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB (6)
75 76
C 77 VDD1 VDD2 78 DDR_B_MA15 C
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
(6) DDR_B_BS2
81 BA2 A14 82
Layout Note:
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11 Place near JDIMM2
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94 +1.35V
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
VDD9 VDD10
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
M_CLK_DDR2 101 102 M_CLK_DDR3
(6) M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 (6)
M_CLK_DDR#2 103 104 M_CLK_DDR#3 1 1 1 1 1 1 1 1 1 1 1 1
(6) M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 (6)
C99
C100
C101
C102
C103
C104
C105
C106
C108
C109
C110
105 106
VDD11 VDD12
C107
DDR_B_MA10 107 108 DDR_B_BS1 @ @
109 A10/AP BA1 110 DDR_B_BS1 (6)
(6) DDR_B_BS0 DDR_B_BS0 DDR_B_RAS#
111 BA0 RAS# 112 DDR_B_RAS# (6) 2 2 2 2 2 2 2 2 2 2 2 2
DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS2_DIMMB#
(6) DDR_B_WE# WE# S0# DDR_CS2_DIMMB# (6)
DDR_B_CAS# 115 116 M_ODT2
(6) DDR_B_CAS# CAS# ODT0 M_ODT2 (6)
117 118
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3
DDR_CS3_DIMMB# 121 A13 ODT1 122 M_ODT3 (6)
(6) DDR_CS3_DIMMB# S1# NC2
123 124
125 VDD17 VDD18 126
127 NCTEST VREF_CA 128 +VREF_CA (11)
VSS27 VSS28
0.1U_0402_16V7K
2.2U_0603_10V6K
DDR_B_D33 129 130 DDR_B_D36
DQ32 DQ36
C97
C98
DDR_B_D37 131 132 DDR_B_D32 1 1
133 DQ33 DQ37 134
DDR_B_DQS#4 135 VSS29 VSS30 136
DDR_B_DQS4 137 DQS#4 DM4 138 @
139 DQS4 VSS31 140 DDR_B_D35 2 2 +SB_DIMM_VREFDQ +1.35V
B DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39 B
DDR_B_D38 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D41
VSS34 DQ44
2
DDR_B_D40 147 148 DDR_B_D45 V0.3A
DDR_B_D44 149 DQ40 DQ45 150
Note: R46
151 DQ41 VSS35 152 DDR_B_DQS#5 VREF trace width:20 mils at least
VSS36 DQS#5 1K_0402_1%
153 154 DDR_B_DQS5
155 DM5 DQS5 156 Spacing:20mils to other signal/planes
1
DDR_B_D46 157 VSS37 VSS38 158 DDR_B_D47
DDR_B_D42 159 DQ42 DQ46 160 DDR_B_D43 1 R47 2 +VREF_DQ_DIMMB
161 DQ43 DQ47 162 2.2_0402_1%
VSS39 VSS40
1
0.022U_0402_16V7K
C96
DDR_B_D52 163 164 DDR_B_D53
DQ48 DQ52
2
DDR_B_D48 165 166 DDR_B_D49
167 DQ49 DQ53 168 R48
1 2
DDR_B_DQS#6 169 VSS41 VSS42 170 @ V0.3A
DQS#6 DM6 1K_0402_1%
DDR_B_DQS6 171 172
173 DQS6 VSS43 174 DDR_B_D50 R49
1
DDR_B_D55 175 VSS44 DQ54 176 DDR_B_D54
DQ50 DQ55 24.9_0402_1%
DDR_B_D51 177 178
+3VS 179 DQ51 VSS45 180 DDR_B_D60 @
2
DDR_B_D56 181 VSS46 DQ60 182 DDR_B_D61
DDR_B_D57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_B_DQS#7
VSS48 DQS#7
2
0_0402_5%
187 188 DDR_B_DQS7
189 DM7 DQS7 190
VSS49 VSS50
R50
DDR_B_D62 191 192 DDR_B_D63
DDR_B_D58 193 DQ58 DQ62 194 DDR_B_D59
195 DQ59 DQ63 196
VSS51 VSS52
1
197 198
199 SA0 EVENT# 200 SMB_DATA_S3
+3VS 201 VDDSPD SDA 202 SMB_DATA_S3 (11,16,32)
SMB_CLK_S3
203 SA1 SCL 204 SMB_CLK_S3 (11,16,32)
VTT1 VTT2 +0.675VS
A 0.65A@0.675V A
2.2U_0603_10V6K
0.1U_0402_16V7K
1 1 205 206
G1 G2
C112
C114
LCN_DAN06-K4806-0103
SP07000M200
V0.3A 2 2
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 12 of 59
5 4 3 2 1
5 4 3 2 1
Note:
PCH_RTCX1/PCHRTCX2
Trace length <1000 mils Green CLK
PCH_RTCX1
D NOGCLK@ D
+RTCVCC 1 2 PCH_RTCX2
R51 10M_0402_5% PCH_RTCX1 R155 1 GCLK@ 2 0_0402_5% CLK_32K_RTC_XIN (27)
R52 1 2 1M_0402_5% SM_INTRUDER#
Y1 NOGCLK@
R53 1 2 330K_0402_5% PCH_INTVRMEN 1 2
32.768KHZ 9PF 20PPM 9H03200033
9P_0402_50V_D
9P_0402_50V_D
NOGCLK@ C115
NOGCLK@ C116
INTVRMEN 1 1
：：
(INTEGRATED SUS 1.05V VR) V0.2
* H Integrated VRM enable
2 2
L Integrated VRM disable
(INTVRMEN should always be pull high.)
V0.2
+3VS
R58 1 @ 2 1K_0402_5% HDA_SPKR
HIGH= Enable ( No Reboot )
* LOW= Disable (Default) Note: +RTCVCC
Need to check with PWR update
U2A LPT_PCH_M_EDS
+RTCVCC CLRP1
SHORT PADS
CLRP1 mask
OPEN SAVE ME RTC REGISTER BC8
+3V_PCH PCH_RTCX1 B5 SATA_RXN_0 BE8
RTCX1 SATA_RXP_0
1
C C118 C
SHORT CLEAR ME RTC REGISTER
R60 2 @ 1 1K_0402_5% ME_FLASH 1U_0402_6.3V6K PCH_RTCX2 B4 AW8
RTCX2 SATA_TXN_0 AY8
RTC
2
2
1 2 PCH_SRTCRST# B9 SATA_TXP_0
* Low = Disabled (Default) SRTCRST#
R54 20K_0402_5% BC10
High = Enabled [Flash Descriptor Security Override] 1 2 PCH_RTCRST# SM_INTRUDER# A8 SATA_RXN_1 BE10
R55 20K_0402_5% INTRUDER# SATA_RXP_1 HM86 NA
1
SHORT PADS
CLRP2
C117 CLRP2 PCH_INTVRMEN G10 AV10
INTVRMEN SATA_TXN_1 AW10
1U_0402_6.3V6K OPEN SAVE CMOS SATA_TXP_1
EMI D9
2
RTCRST# BB9
SHORT CLEAR CMOS SATA_RXN_2 BD9
RP2 HDA_BIT_CLK B25 SATA_RXP_2
8 1 HDA_SYNC HDA_BCLK AY13
(26) HDA_SYNC_AUDIO SATA_TXN_2
7 2 ME_FLASH HDA_SYNC A22 AW13
(26) HDA_SDOUT_AUDIO HDA_SYNC SATA_TXP_2
6 3 HDA_RST#
(26) HDA_RST_AUDIO# 5 4 AL10 BC12
(26) HDA_BITCLK_AUDIO HDA_BIT_CLK HDA_SPKR
(26) HDA_SPKR SPKR SATA_RXN_3 BE12
33_0804_8P4R_5% HDA_RST# C24 SATA_RXP_3 HM86 NA
HDA_RST# AR13
L22 SATA_TXN_3 AT13
AZALIA
HDA_SDIN0
SATA
EMI@ (26) HDA_SDIN0 HDA_SDI0 SATA_TXP_3
K22
HDA_SDI1 BD13 SATA_PRX_DTX_N4
SATA_RXN4/PERN1 SATA_PRX_DTX_N4 (29)
G22 BB13 SATA_PRX_DTX_P4 HDD
HDA_SDI2 SATA_RXP4/PERP1 SATA_PRX_DTX_P4 (29)
V0.2
F22 AV15 SATA_PTX_DRX_N4
HDA_SDI3 SATA_TXN4/PETN1 SATA_PTX_DRX_N4 (29)
AW15 SATA_PTX_DRX_P4 SATA_PTX_DRX_P4 (29)
ME_FLASH A24 SATA_TXP4/PETP1
(31) ME_FLASH HDA_SDO BC14
+3VS R59 1 @ 2 1K_0402_1% PCH_GPIO33 B17 SATA_RXN5/PERN2 BE14
DOCKEN#/GPIO33 SATA_RXP5/PERP2
B RP3 R61 1 2 10K_0402_5% PCH_GPIO13 C22 AP15 B
+3V_PCH HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2
PCH_GPIO35 4 5 AR15
(18) PCH_GPIO35 SATA_TXP5/PETP2
SATA_LED# 3 6
PCH_GPIO21 2 7
BBS_BIT0_R 1 8 AY5 SATA_COMP
SATA_RCOMP
10K_0804_8P4R_5% AP3 SATA_LED#
SATALED# SATA_LED# (33)
2 R62 1 PCH_JTAG_TCK AB3 AT1 PCH_GPIO21
51_0402_5% JTAG_TCK SATA0GP/GPIO21
PCH_JTAG_TMS AD1 AU2 BBS_BIT0_R
T25 JTAG_TMS SATA1GP/GPIO19
PCH_JTAG_TDI AE2 BD4
JTAG
T26 JTAG_TDI SATA_IREF +1.5VS
V0.2
PCH_JTAG_TDO AD3 BA2
T27 JTAG_TDO TP9
SATA Impedance Compensation F8
TP25 TP8
BB2
+1.5VS C26
TP22
SATA_COMP 1 2 PCH_JTAG_RST#AB6
T20 TP20
7.5K_0402_1% R66
Note:
1 OF 11
Trace width:4mils DH82HM86-SR17E-C2_FCBGA695
Place the resistor to PCH <500 mils, to 1.5V <100 mils.Avoid
routing next to clock pins.
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/9) SATA,HDA,SPI, LPC, XDP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 13 of 59
5 4 3 2 1
5 4 3 2 1
LPT_PCH_M_EDS
U2B
DMI_CTX_PRX_N0 AW22 U2E LPT_PCH_M_EDS
(4) DMI_CTX_PRX_N0 DMI_RXN_0
(4) DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 AR20
DMI_RXN_1 AJ35 T45 R40 HDMICLK_NB
FDI_RXN_0 VGA_BLUE DDPB_CTRLCLK HDMICLK_NB (16,24)
DMI_CTX_PRX_N2 AP17
(4) DMI_CTX_PRX_N2 DMI_RXN_2
(4) DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 AV20 AL35 U44 R39 HDMIDAT_NB HDMIDAT_NB (16,24)
DMI_RXN_3 FDI_RXN_1 VGA_GREEN DDPB_CTRLDATA
(4) DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 AY22 AJ36 V45 R35
DMI_CTX_PRX_P1 AP20 DMI_RXP_0 FDI_RXP_0 VGA_RED DDPC_CTRLCLK
(4) DMI_CTX_PRX_P1 DMI_RXP_1 AL36 M43 R36
DMI_CTX_PRX_P2 AR17 FDI_RXP_1 VGA_DDC_CLK DDPC_CTRLDATA
(4) DMI_CTX_PRX_P2 DMI_RXP_2
DMI_CTX_PRX_P3 AW20 AV43 M45 N40
CRT
(4) DMI_CTX_PRX_P3 DMI_RXP_3 TP16 VGA_DDC_DATA DDPD_CTRLCLK
D D
DMI_CRX_PTX_N0 BD21 AY45 N42 N38
(4) DMI_CRX_PTX_N0 BE20 DMI_TXN_0 TP5 VGA_HSYNC DDPD_CTRLDATA
DMI_CRX_PTX_N1
(4) DMI_CRX_PTX_N1 DMI_TXN_1 DMI FDI AV45 N44
DMI_CRX_PTX_N2 BD17 TP15 VGA_VSYNC H45
(4) DMI_CRX_PTX_N2 DMI_TXN_2 DDPB_AUXN
DMI_CRX_PTX_N3 BE18 AW44 U40
DISPLAY
(4) DMI_CRX_PTX_N3 DMI_TXN_3 TP10 DAC_IREF K43
DMI_CRX_PTX_P0 BB21 AL39 U39 DDPC_AUXN
(4) DMI_CRX_PTX_P0 DMI_TXP_0 FDI_CSYNC FDI_CSYMC (4) VGA_IRTN
DMI_CRX_PTX_P1 BC20 J42
(4) DMI_CRX_PTX_P1 DMI_TXP_1 AL40 DDPD_AUXN
FDI_INT FDI_INT (4)
DMI_CRX_PTX_P2 BB17 PCH_PWM N36 H43
(4) DMI_CRX_PTX_P2 DMI_TXP_2 (22) PCH_PWM EDP_BKLTCTL DDPB_AUXP
DMI_CRX_PTX_P3 BC18 AT45
LVDS
(4) DMI_CRX_PTX_P3 DMI_TXP_3 FDI_IREF +1.5VS
ENBKL K36 K45
(31) ENBKL EDP_BKLTEN DDPC_AUXP
+1.5VS BE16 AU42
DMI_IREF TP17 PCH_ENVDD G36 J44
(22) PCH_ENVDD EDP_VDDEN DDPD_AUXP
SUSACK# is only used on platform AW17 AU44
TP12 TP13 K40
that support the Deep Sx state. DDPB_HPD TMDS_B_HPD (24)
AV17 AR44 R148 1 2 7.5K_0402_1% PCI_PIRQA# H20
TP7 FDI_RCOMP PIRQA# K38
R71 1 2 DMI_RCOMP AY17 PCI_PIRQB# L20 DDPC_HPD
+1.5VS DMI_RCOMP
INTEL Recommend PIRQB#
7.5K_0402_1% FDI_IREF and FDI_RCOMP can floating H39
PCI_PIRQC# K17 DDPD_HPD
PIRQC#
SUSWARN#_R 1 DS3@ 2 SUSACK#_R R6 C8 DSWODVREN PCI_PIRQD# M20
R150 0_0402_5% SUSACK# DSWVRMEN PIRQD# G17 PCH_GPIO2
SYS_RST# AM1 L13 PCH_DPWROK 1 NODS3@2 EC_RSMRST# DGPU_HOLD_RST# A12 PIRQE#/GPIO2
(18) SYS_RST# SYS_RESET# DPWROK (36) DGPU_HOLD_RST# GPIO50
2 R72 1 R172 0_0402_5% F17 GPU_EVENT#
AD7 K3 B13 PCI PIRQF#/GPIO3 GPU_EVENT# (36)
100K_0402_1% @ SYS_PWROK PCIE_WAKE# PCIE_WAKE# (18,28)
(31,5) SYS_PWROK SYS_PWROK WAKE# GPIO52 L15 GC6_FB_EN
F10 AN7 PM_CLKRUN# C12 PIRQG#/GPIO4 GC6_FB_EN (36,38)
(31,9) PCH_PWROK PCH_PWROK DGPU_PWR_EN
PWROK System Power CLKRUN# (31,45) DGPU_PWR_EN GPIO54 M15 GPU_ALL_PGOOD
Management PIRQH#/GPIO5 GPU_ALL_PGOOD (45)
2 R73 1 10K_0402_5% AB7 U7 SUS_STAT# T21 BBS_BIT1 C10
APWROK SUS_STAT#/GPIO61 GPIO51 AD10
PM_DRAM_PWRGD H3 Y6 SUSCLK T23 PCH_GPIO53 A10 PME#
(5) PM_DRAM_PWRGD DRAMPWROK SUSCLK/GPIO62 SUSCLK (28) * GPIO53
PLTRST#
Y11 PCH_PLTRST#
EC_RSMRST# J2 Y7 PCH_GPIO55 AL6 1
(31) EC_RSMRST# RSMRST# SLP_S5#/GPIO63 PM_SLP_S5# (31) GPIO55
1 DS3@ 2 SUSWARN#_R J4 C6 C193
(31) SUSWARN# SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# PM_SLP_S4# (31)
C R151 0_0402_5% DH82HM86-SR17E-C2_FCBGA695 5 OF 11 100P_0402_50V8J C
PBTN_OUT# K1 H1 2
(31) PBTN_OUT# PWRBTN# SLP_S3# PM_SLP_S3# (31) @ESD@
AC_PRESENT_R E6 F3 SLP_A# T24 SLP_A# can be left NC when IAMT is
(31) AC_PRESENT_R ACPRESENT/GPIO31 SLP_A#
not support on the platfrom
PCH_GPIO72 K7 F1 SLP_SUS#
BATLOW#/GPIO72 SLP_SUS# SLP_SUS# (31)
RI# N4 AY3 H_PM_SYNC
(18) RI# RI# PMSYNCH H_PM_SYNC (5)
AB10 G5 SLP_LAN# can be left NC if no use
TP21 SLP_LAN#
integrated LAN.
D2
SLP_WLAN#/GPIO29
DH82HM86-SR17E-C2_FCBGA695 4 OF 11
+RTCVCC
ESD 9/5
@ESD@ DSWODVREN R75 2 1 +3VS V0.2
C189 2 1 100P_0402_50V8J SYS_PWROK 330K_0402_5%
R77 1 @ 2 BBS_BIT1 2 R76 1 10K_0402_5%
C190 2 1 100P_0402_50V8J EC_RSMRST# 330K_0402_5%
DGPU_HOLD_RST# R146 2 DIS@ 1 10K_0402_5%
@ESD@
* ：
DSWODVREN - On Die DSW VR Enable
：
H Enable (DEFAULT)
L Disable Boot BIOS Strap (GPIO51)
+3VALW PCH_DPWROK R171 1 DS3@ 2 0_0402_5%
SATA_SLPD DPWROK_EC (31)
R149 1 2 10K_0402_5% PCH_GPIO72 +3VS BBS_BIT1 (BBS_BIT0) Boot BIOS Location
B
RP4
0 0 LPC B
W_DISABLE#1 5 4
(18,28) W_DISABLE#1
APWROK can be connect to (18,31) GATEA20 GATEA20 6 3 0 1 Reserved (NAND)
PWROK if iAMT disable KB_RST# 7 2
(18,31) KB_RST#
(18,28) W_DISABLE#2 W_DISABLE#2 8 1
10K_0804_8P4R_5%
1 0 PCI
V0.3A
SUSACK# and SUSWARN# can be tied together if
1 1 * SPI 1 2
V0.2 R74 33_0402_5%
EC does not want to involve in the handshake GPIO51 needs pull up 10k to ensure proper behavior.
mechanism for the Deep Sleep state entry and exit. +3VS
RP5 +3VS
PCI_PIRQC# 8 1
Follow Intel schematic PCI_PIRQB# 7 2
PCI_PIRQA# 6 3
+3V_PCH review-0930 PCI_PIRQD# 5 4 @
5
U3 MC74VHC1G08DFT2G SC70 5P
R81 @ 8.2K_0804_8P4R_5%
VCC
1 2 AC_PRESENT_R +3VS 1 PCH_PLTRST#
200K_0402_5% 4 IN1
(25,28,31,34,36) PLT_RST# OUT
V0.2 V0.2 2
GND
PCH_GPIO55 R83 1 2 10K_0402_5% IN2
1
CLKRUN#: +3VS R79 1 @ 2 1K_0402_5%
3
External pull up to core well is required.
DGPU_PWR_EN 10K_0402_5% 1 2 R113
2
+3VS PCH_GPIO2 10K_0402_5% 1 2 R117 GPIO55 V0.3 R78
100K_0402_5%
GPU_ALL_PGOOD 10K_0402_5% 1 @ 2 R173 A16 swap overide Strap/Top-Block
1 R80 2 8.2K_0402_5% PM_CLKRUN# Swap Override jumper
GPU_EVENT# 10K_0402_5% 1 @ 2 R84
Low=A16 swap
2 R82 1 10K_0402_5% override/Top-Block
@
Follow Intel schematic PCI_GNT3# Swap Override enabled
High=Default
A
review-0930
* A
+3V_PCH 10K_0402_5% 1 2 R154 EC_RSMRST#
RP15
10K_0402_5% 2 @ 1 R339 SUSCLK
8 1 PCH_GPIO28
7 2 SUSWARN#_R PCH_GPIO28 (18)
6 3
5 4 PCH_GPIO24 Security Classification Compal Secret Data
PCH_GPIO24 (18)
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
10K_0804_8P4R_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/9) PCIE, SMBUS, CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 14 of 59
5 4 3 2 1
5 4 3 2 1
LPT_PCH_M_EDS
U2C
D D
Y43 AB35 CLK_PEG_VGA# +3VS
CLKOUT_PCIE_N_0 CLKOUT_PEG_A CLK_PEG_VGA# (36)
Y45 AB36 CLK_PEG_VGA
dGPU
RP8
CLKOUT_PCIE_P_0 CLKOUT_PEG_A_P CLK_PEG_VGA (36) 4 5 PCH_GPIO49
AB1 AF6 3 6 PCH_GPIO49 (18)
PCH_GPIO73 CLK_REQ_VGA# CLK_REQ_VGA# (36)
PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47 2 7 PCH_GPIO18
AA44 Y39 1 8 CLKREQ_WLAN#
AA42 CLKOUT_PCIE_N_1 CLKOUT_PEG_B
CLKOUT_PCIE_P_1 Y38
PCH_GPIO18 AF1 CLKOUT_PEG_B_P 10K_0804_8P4R_5%
PCIECLKRQ1#/GPIO18 U4 PCH_GPIO56
CLK_PCIE_WLAN1# AB43 PEGB_CLKRQ#/GPIO56 PCH_GPIO56 (17)
(28) CLK_PCIE_WLAN1# CLKOUT_PCIE_N_2 AF39 CLK_CPU_DMI#
CLK_PCIE_WLAN1 AB45 CLKOUT_DMI CLK_CPU_DMI# (5)
(28) CLK_PCIE_WLAN1 CLKOUT_PCIE_P_2 AF40 +3V_PCH
WLAN CLK_CPU_DMI
CLKREQ_WLAN# AF3 CLKOUT_DMI_P CLK_CPU_DMI (5)
(28) CLKREQ_WLAN# PCIECLKRQ2#/GPIO20/SMI# AJ40 CLK_CPU_SSC_DPLL# RP9
CLK_PCIE_LAN# AD43 CLKOUT_DP AJ39 CLK_CPU_SSC_DPLL CLK_CPU_SSC_DPLL# (5) 4 5 PCH_GPIO73
(25) CLK_PCIE_LAN# CLK_PCIE_LAN AD45 CLKOUT_PCIE_N_3 CLKOUT_DP_P CLK_CPU_SSC_DPLL (5) 3 6 CLKREQ_CR#
(25) CLK_PCIE_LAN T3 CLKOUT_PCIE_P_3 AF35 2 7
LAN CLKREQ_LAN# CLK_CPU_DPLL# PCH_GPIO8
(18,25) CLKREQ_LAN# PCIECLKRQ3#/GPIO25 CLKOUT_DPNS AF36 CLK_CPU_DPLL CLK_CPU_DPLL# (5) 1 8 PCH_GPIO46 PCH_GPIO8 (18)
AF43 CLKOUT_DPNS_P CLK_CPU_DPLL (5)
AF45 CLKOUT_PCIE_N_4 AY24 CLK_BUF_DMI# 10K_0804_8P4R_5%
PCH_GPIO26 V3 CLKOUT_PCIE_P_4 CLKIN_DMI AW24 CLK_BUF_DMI
(17) PCH_GPIO26 PCIECLKRQ4#/GPIO26 CLOCK SIGNAL CLKIN_DMI_P 1 2 10K_0402_5% PCH_GPIO45
R132
CLK_PCIE_CR# AE44 AR24 CLK_BUF_BCLK#
(34) CLK_PCIE_CR# CLK_PCIE_CR AE42 CLKOUT_PCIE_N5 CLKIN_GND AT24 CLK_BUF_BCLK
CR (34) CLK_PCIE_CR CLKOUT_PCIE_P_5 CLKIN_GND_P
CLKREQ_CR# AA2
(34) CLKREQ_CR# PCIECLKRQ5#/GPIO44 H33 CLK_BUF_DOT96#
AB40 CLKIN_DOT96N G33 CLK_BUF_DOT96
AB39 CLKOUT_PCIE_N_6 CLKIN_DOT96P
C PCH_GPIO45 AE4 CLKOUT_PCIE_P_6 BE6 CLK_BUF_CKSSCD# C
PCIECLKRQ6#/GPIO45 CLKIN_SATA BC6 CLK_BUF_CKSSCD
AJ44 CLKIN_SATA_P RP10
CLKOUT_PCIE_N_7 F45 CLK_PCH_14M CLK_BUF_BCLK# 4 5
AJ42 REFCLK14IN D17 CLK_PCI_LPBACK CLK_BUF_BCLK 3 6
CLKOUT_PCIE_P_7 CLKIN_33MHZLOOPBACK CLK_BUF_DMI 2 7
PCH_GPIO46 Y3 AM43 XTAL25_IN CLK_BUF_DMI# 1 8
PCIECLKRQ7#/GPIO46 XTAL25_IN AL44 XTAL25_OUT
AH43 XTAL25_OUT
CLKOUT_ITPXDP C40
EMI CLKOUTFLEX0/GPIO64
10K_0804_8P4R_5%
AH45
CLKOUT_ITPXDP_P F38 CLK_BUF_DOT96# R85 2 1 10K_0402_5%
CLK_PCI_LPBACK 22_0402_5% 1 EMI@ 2 R90 CLK_PCI_LPBACK_R D44 CLKOUTFLEX1/GPIO65 CLK_BUF_DOT96 R86 2 1 10K_0402_5%
CLKOUT_33MHZ0 F36
22_0402_5% 1 EMI@ 2 R91 CLK_PCI_EC_R E44 CLKOUTFLEX2/GPIO66
(31) CLK_PCI_EC CLKOUT_33MHZ1 F39 PCH_GPIO67 CLK_BUF_CKSSCD# R176 2 1 10K_0402_5%
B42 CLKOUTFLEX3/GPIO67 PCH_GPIO67 (18)
CLK_BUF_CKSSCD R175 2 1 10K_0402_5%
CLKOUT_33MHZ2 AM45
ICLK_IREF +1.5VS
F41 V0.2
CLKOUT_33MHZ3 AD39
A40 TP19 AD38 CLK_PCH_14M R89 2 1 10K_0402_5%
CLKOUT_33MHZ4 TP18
AN44 PCH_CLK_BIASREF 1 R93 2
DIFFCLK_BIASREF +1.5VS
7.5K_0402_1%
DH82HM86-SR17E-C2_FCBGA695 2 OF 11
CLOCK TERMINATION for FCIM and need close to PCH
B B
Green CLK
XTAL25_IN R156 1 GCLK@ 2 0_0402_5% CLK_25M_PCH_XIN (27)
NOGCLK@
XTAL25_IN C122 1 2 12P_0402_50V8J
Y2
NOGCLK@
2
R94 1 2
XTAL0 GND0
1M_0402_5% 3 4
NOGCLK@ XTAL1 GND1
1
25MHZ_10PF_7V25000014 V0.2
XTAL25_OUT C121 1 2 12P_0402_50V8J
NOGCLK@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/9) DMI,FDI,PM,
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 15 of 59
5 4 3 2 1
5 4 3 2 1
LPT_PCH_M_EDS
U2D
+3VS
N7 PCH_GPI011 +3VS
D A20 SMBALERT#/GPIO11 D
(31) LPC_AD0 LAD_0
SMBus R10 PCH_SMBCLK
SMBCLK
1
(31) LPC_AD1 C20
LAD_1 U11 PCH_SMBDATA R99 R100
A18 SMBDATA
(31) LPC_AD2
LPC
LAD_2 N8 PCH_GPIO60 2.2K_0402_5% 2.2K_0402_5%
C18 SML0ALERT#/GPIO60
(31) LPC_AD3
2
LAD_3
2
U8 PCH_SML0CLK
B21 SML0CLK
(31) LPC_FRAME# LFRAME# R7 6 1
PCH_SML0DATA PCH_SMBCLK SMB_CLK_S3
+3VS D21
LDRQ0#
SML0DATA Q2A
SMB_CLK_S3 (11,12,32) DIMM1
5
H6 PCH_GPI074 2N7002KDWH_SOT363-6
R98 2 1 10K_0402_5% G20
LDRQ1#/GPIO23
SML1ALERT#/PCHHOT#/GPIO74 DIMM2
K6 SML1CLK PCH_SMBDATA 3 4 SMB_DATA_S3
SERIRQ AL11 SML1CLK/GPIO58 SMB_DATA_S3 (11,12,32)Click Pad
(31) SERIRQ SERIRQ N11 SML1DATA Q2B
SML1DATA/GPIO75 2N7002KDWH_SOT363-6
AF11
SPI_CLK_PCH_R AJ11 CL_CLK
SPI_CLK AF10
SPI_SB_CS0# AJ7 C-Link CL_DATA
SPI_CS0# AF7 +3VS
AL7 CL_RST#
SPI_CS1#
AJ10
SPI_CS2#
SPI
BA45
SPI_SI AH1 TP1
SPI_MOSI BC45
TP2
5
Thermal
SPI_SO_R AH3 2N7002KDWH_SOT363-6
SPI_MISO BE43
SPI_IO2 AJ4 TP4 SML1CLK 3 4 EC_SMB_CK2
C SPI_IO2 BE44 EC_SMB_CK2 (31,32,36) C
TP3
2
SPI_IO3 AJ2 MAIN@ Q3B 2N7002KDWH_SOT363-6
SPI_IO3
TD_IREF
AY43 PCH_TD_IREF 1 2 EC
R101 8.2K_0402_1% SML1DATA 6 1 EC_SMB_DA2
EC_SMB_DA2 (31,32,36)
MAIN@ Q3A
DH82HM86-SR17E-C2_FCBGA695 3 OF 11 Keep -Thermal
PCH_SMBCLK R162 1 @ 2 0_0402_5% SMB_CLK_S3
PCH_SMBDATA R160 1 @ 2 0_0402_5% SMB_DATA_S3
SML1CLK R161 1 @ 2 0_0402_5% EC_SMB_CK2
+3V_PCH SML1DATA R159 1 @ 2 0_0402_5% EC_SMB_DA2
+3V_PCH
2
C125
R102
+3V_PCH 1 2
1K_0402_5%
R104 15_0402_5% U4 0.1U_0402_16V7K
Follow Intel schematic
1
SPI_SB_CS0# 1 8
R106 SPI_SO_R 1 2 SPI_SO_L 2 CS# VCC 7 SPI_IO3_2 R105 1 2 15_0402_5% SPI_IO3
1 2 SPI_IO2 1 2 SPI_IO2_2 3 SO HOLD# 6 SPI_CLK_PCH R108 1 2 15_0402_5% SPI_CLK_PCH_R review-0930 +3V_PCH
1K_0402_5% 4 WP# SCLK 5 SPI_SI_R R109 1 2 15_0402_5% SPI_SI
R107 15_0402_5% GND SI
64M W25Q64FVSSIQ SOIC 8P PCH_SMBDATA R170 2 1 1K_0402_5%
B PCH_SMBCLK R168 2 1 1K_0402_5% B
SML1CLK R169 2 1 1K_0402_5%
SA000039A30
SML1DATA R167 2 1 1K_0402_5%
PCH_SML0CLK R163 2 1 1K_0402_5%
PCH_SML0DATA R164 2 1 1K_0402_5%
SPI_CLK_PCH
EC/BIOS Share ROM
1
R103 +3VS
33_0402_5% SPI_CLK_PCH
SPI_CLK_PCH (31)
@EMI@ SPI_SI_R
SPI_SI_R (31) (14,24) HDMICLK_NB
HDMICLK_NB R165 2 1 2.2K_0402_5%
SPI_SO_L
SPI_SO_L (31) (14,24) HDMIDAT_NB
HDMIDAT_NB R166 2 1 2.2K_0402_5%
2
SPI_SB_CS0# SPI_SB_CS0# (31)
C126
22P_0402_50V8J
@EMI@
+3V_PCH
R237;c120 close
to U4 pin 1 2
PCH_GPI011 R95 10K_0402_5%
EMI
PCH_GPI074 R96 1 2 10K_0402_5%
PCH_GPIO60 R97 2 1 1K_0402_5%
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) LVDS,CRT,DP,HDMI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 16 of 59
5 4 3 2 1
5 4 3 2 1
D D
U2I LPT_PCH_M_EDS
USB DEBUG=PORT1 AND PORT9
AW31 B37 USB20_N0
AY31 PERN1/USB3RN3 USB2N0 D37 USB20_P0 USB20_N0 (30)
V0.3 PERP1/USB3RP3 USB2P0 A38 USB20_N1 USB20_P0 (30) Left USB
BE32 USB2N1 C38 USB20_P1 USB20_N1 (30) (USB 3.0)
BC32 PETN1/USB3TN3 USB2P1 A36 USB20_P1 (30) Left USB
PETP1/USB3TP3 USB2N2 C36
PCIE_PRX_DTX_N2 AT31 USB2P2 A34
(28) PCIE_PRX_DTX_N2 PERN2/USB3RN4 USB2N3
PCIE_PRX_DTX_P2 AR31 C34
(28) PCIE_PRX_DTX_P2 PERP2/USB3RP4 USB2P3
WLAN B33 USB20_N4
(28) PCIE_PTX_C_DRX_N2
C131 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N2 BD33
PETN2/USB3TN4
USB2N4
USB2P4
D33 USB20_P4 USB20_N4 (34)
USB20_P4 (34) Right USB/B (USB 2.0) EHCI1
C132 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_P2 BB33 F31
(28) PCIE_PTX_C_DRX_P2 PETP2/USB3TP4 USB2N5 G31
USB2P5 K31
PCIE_PRX_DTX_N3 AW33 USB2N6 L31
(25) PCIE_PRX_DTX_N3 PERN_3 USB2P6
(25) PCIE_PRX_DTX_P3 PCIE_PRX_DTX_P3 AY33 G29
PERP_3 USB2N7 H29
LAN USB2P7
C127 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N3 BE34 A32 USB20_N8
(25) PCIE_PTX_C_DRX_N3 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P3 BC34 PETN_3 USB2N8 C32 USB20_P8 USB20_N8 (22)
C128 Touch panel
(25) PCIE_PTX_C_DRX_P3 PETP_3 USB2P8 A30 USB20_N9 USB20_P8 (22)
AT33 USB2N9 C30 USB20_P9 USB20_N9 (22)
AR33 PERN_4 USB2P9 B29 USB20_N10 USB20_P9 (22) USB Camera
PERP_4 USB2N10 D29 USB20_P10 USB20_N10 (28)
BE36 USB2P10 A28 USB20_P10 (28) BT
BC36 PETN_4 USB2N11 C28
PETP_4 USB2P11
USB2N12
G26 EHCI2
PCIe
PCIE_PRX_DTX_N5 AW36 F26
USB
(34) PCIE_PRX_DTX_N5 PERN_5 USB2P12
PCIE_PRX_DTX_P5 AV36 F24
C (34) PCIE_PRX_DTX_P5 PERP_5 USB2N13 C
Card Reader G24
C129 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N5 BD37 USB2P13
(34) PCIE_PTX_C_DRX_N5 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_P5 BB37 PETN_5
C130
(34) PCIE_PTX_C_DRX_P5 PETP_5 AR26 USB3_RX1_N
USB3RN1 USB3_RX1_N (30)
AY38 AP26 USB3_RX1_P
PERN_6 USB3RP1 USB3_RX1_P (30)
AW38 BE24 USB3_TX1_N Left USB
PERP_6 USB3TN1 BD23 USB3_TX1_N (30)
USB3_TX1_P
BC38 USB3TP1 AW26 USB3_TX1_P (30)
USB3_RX2_N USB3_RX2_N (30)
BE38 PETN_6 USB3RN2 AV26 USB3_RX2_P
PETP_6 USB3RP2 BD25 USB3_TX2_N
USB3_RX2_P (30) Left USB
AT40 USB3TN2 BC24 USB3_TX2_P USB3_TX2_N (30)
AT39 PERN_7 USB3TP2 AW29 USB3_TX2_P (30)
PERP_7 USB3RN5 AV29
BE40 USB3RP5 BE26 HM86 NA
BC40 PETN_7 USB3TN5 BC26
PETP_7 USB3TP5 AR29
AN38 USB3RN6 AP29 HM86 NA
AN39 PERN_8 USB3RP6 BD27
PERP_8 USB3TN6 BE28
BD42 USB3TP6
PETN_8 CAD NOTE:
BD41 K24 USBRBIAS 1 R110 2
PETP_8 USBRBIAS# K26 22.6_0402_1%
Route single-end 50-ohms and max 500-mils length.
USBRBIAS Avoid routing next to clock pins or under stitching capacitors.
BE30 M33 Recommended minimum spacing to other signal traces is 15 mils.
+1.5VS PCIE_IREF TP24 L33
TP23
BC30 P3 USB_OC0#
TP11 OC0#/GPIO59 V1 USB_OC# USB_OC0# (18,30)
OC1#/GPIO40 U2 USB_OC2#
BB29 OC2#/GPIO41 P1 USB_OC# USB_OC2# (34)
TP6 OC3#/GPIO42 M3 USB_OC#
OC4#/GPIO43 T1 USB_OC#
B 1 2 PCH_PCIE_RCOMP BD29 OC5#/GPIO9 N2 USB_OC# B
+1.5VS PCIE_RCOMP OC6#/GPIO10
R111 7.5K_0402_1% M1 USB_OC#
OC7#/GPIO14
DH82HM86-SR17E-C2_FCBGA695 9 OF 11
+3V_PCH
RP14
PCH_GPIO56 4 5
(15) PCH_GPIO56 3 6
USB_OC2#
USB_OC# 2 7
PCH_GPIO26 1 8
(15) PCH_GPIO26
10K_0804_8P4R_5%
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/9) PCI, USB
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 17 of 59
5 4 3 2 1
5 4 3 2 1
+3V_PCH
Weak internal pull-high
RP17
4 5 CLKREQ_LAN#
3 6 USB_OC0# CLKREQ_LAN# (15,25)
2 7 RI# USB_OC0# (17,30)
1 8 RI# (14) LPT_PCH_M_EDS
PCIE_WAKE# U2F
D PCIE_WAKE# (14,28) D
10K_0804_8P4R_5% +3VS R112 1 2 10K_0402_5% PCH_GPIO0 AT8
BMBUSY#/GPIO0
F13
TACH1/GPIO1
A14
TACH2/GPIO6
+3V_PCH G15 CPU/Misc
EC_SCI# Broadwell/Haswell
(31) EC_SCI# TACH3/GPIO7
V0.2 PCH_GPIO8 Y1
(15) PCH_GPIO8 GPIO8 +1.05VS R157
+3V_PCH R114 1 @ 2 10K_0402_5% PCH_GPIO12 K13
R115 2 1 10K_0402_5% PCH_GPIO57 LAN_PHY_PWR_CTRL/GPIO12 AN10
TP14 GATEA20 (14,31)
R116 1 2 1K_0402_5% V0.2 PCH_GPIO15 AB11 BW@
GPIO15
2
AY1
PCH_GPIO16 AN2 PECI R119 BW@
SATA4GP/GPIO16 AT6 KB_RST#
GPIO RCIN# KB_RST# (14,31) 1K_0402_5% 0_0402_5%
DGPU_PWROK C14 SD028000080
(36,45,54) DGPU_PWROK TACH0/GPIO17 AV3
H_CPUPWRGD (5)
1
W_DISABLE#2 BB4 PROCPWRGD HW@
(14,28) W_DISABLE#2 SCLOCK/GPIO22 AV1 1 2
H_THRMTRIP#_R H_THRMTRIP# (45,5)
PCH_GPIO24 Y10 THRMTRIP# R157 390_0402_5%
(14) PCH_GPIO24 GPIO24 AU4 CPU_PLTRST#
PCH_GPIO27 R11 PLTRST_PROC# CPU_PLTRST# (5)
* PCH_GPIO27 (Have internal Pull-High) GPIO27 N10
High: VCCVRM VR Enable PCH_GPIO28 AD11 VSS
(14) PCH_GPIO28 GPIO28 1
Low: VCCVRM VR Disable
W_DISABLE#1 AN6 C186
(14,28) W_DISABLE#1 GPIO34
1000P_0402_50V7K
+3VALW PCH_GPIO35 AP1 2
(13) PCH_GPIO35 GPIO35/NMI# @ESD@
R121 1 2 10K_0402_5% PCH_GPIO27 TS_ON AT3
C (22) TS_ON SATA2GP/GPIO36 ESD 9/5 C
PCH_GPIO37 AK1
SATA3GP/GPIO37
CMOS_ON# AT7
(22) CMOS_ON# SLOAD/GPIO38
PCH_GPIO39 AM3 A2
SDATAOUT0/GPIO39 VSS A41
+3VS +3VS PCH_GPIO48 AN4 VSS A43
SDATAOUT1/GPIO48 VSS A44
PCH_GPIO49 AK3 VSS B1
(15) PCH_GPIO49 SATA5GP/GPIO49 VSS
1
R122 B2
1 2 TS_ON PCH_GPIO57 U12 VSS B44
200K_0402_5% R123 10K_0402_5% GPIO57 VSS B45
@ PCH_GPIO68 C16 VSS BA1
1 @ 2 DGPU_PWROK TACH4/GPIO68 VSS BC1
2
PCH_GPIO37 R158 10K_0402_5% D13 VSS BD1
TACH5/GPIO69 VSS BD2
VSS
1
PCH_GPIO70 G13 BD44
1 15@ 2 PCH_GPIO68 V0.3 TACH6/GPIO70 VSS BD45
R124 R125 10K_0402_5% PCH_GPIO71 H15 VSS BE2
10K_0402_5% 2 17@ 1 TACH7/GPIO71 VSS BE3
R128 10K_0402_5% VSS D1
2
BE41 VSS E1
V0.3 BE5 VSS NCTF VSS E45
C45 VSS VSS A4
PCH_GPIO68 A5 VSS VSS
====================================== VSS
Y50 : High (R125 stuff ,R128 un-stuff)
Y70 : Low (R125 un-stuff ,R128 stuff) DH82HM86-SR17E-C2_FCBGA695 6 OF 11
B B
+3VS
R127 1 2 10K_0402_5% CMOS_ON#
R126 1 2 10K_0402_5% PCH_GPIO67
PCH_GPIO67 (15)
R130 1 2 10K_0402_5% PCH_GPIO71
R131 1 2 10K_0402_5% PCH_GPIO70
+3VS
RP18
4 5 PCH_GPIO16
3 6 PCH_GPIO48
2 7 SYS_RST#
SYS_RST# (14)
1 8 PCH_GPIO39
10K_0804_8P4R_5%
A A
Security Classification Compal Secret Data
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 18 of 59
5 4 3 2 1
5 4 3 2 1
D D
U2G LPT_PCH_M_EDS
+1.05VS P45
VCCADAC1_5 +1.5VS
AA24 P43
AA26 VCC CRT DAC VSS PCH Power Rail Table
10U_0603_6.3V6M VCC
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 AD20 M31
C133 VCC VCCADACBG3_3 +1.05VS
C136
C134
C135
AD22
VCC
10U_0603_6.3V6M
AD24 1 Voltage Rail Voltage S0 Iccmax Current (A)
VCC
C137
AD26 BB44
2 2 2 2 VCC VCCVRM
1U_0402_6.3V6K
AD28 1
VCC FDI
C138
AE18 AN34 VCC 1.05V 1.29 A
AE20 VCC VCCIO +3VS 2 @
AE22 VCC AN35
AE24 VCC VCCIO 2
VCC VCCIO 1.05V 3.629 A
AE26 R30
AG18 VCC HVCMOS VCC3_3_R30 R32
VCC VCC3_3_R32
0.1U_0402_16V7K
AG20 1 VCCADAC1_5 1.5V 0.070 A
AG22 VCC Y12 +PCH_USB_DCPSUS1 +3V_PCH
VCC DCPSUS1
0.1U_0402_16V7K
C139
AG24
Y26 VCC AJ30
VCC VCCSUS3_3 2
VCCADAC3_3 3.3V 0.0133 A
Core
AJ32 1
VCCSUS3_3
+1.05VS +1.5VS
C140
AJ26 +PCH_USB_DCPSUS3 VCCCLK 1.05V 0.306 A
+PCH_VCCDSW U14 USB3 DCPSUS3 AJ28
AA18 DCPSUSBYP DCPSUS3 AK20 2
VCCASW VCCIO +1.05VS
U18 AK26 VCCCLK3_3 3.3V 0.055 A
C U20 VCCASW VCCVRM AK28 +1.5VS C
VCCASW VCCVRM
22U_0805_6.3V6M
C141
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 U22
VCCASW
C142
C143
U24 BE22 VCCVRM 1.5V 0.179 A
V18 VCCASW VCCVRM
PCIe/DMI
V20 VCCASW AK18 +1.5VS
2 2 2 VCCASW VCCIO +1.05VS
V22 VCC3_3 3.3V 0.133 A
V24 VCCASW AN11
Y18 VCCASW VCCVRM
Y20 VCCASW SATA
AK22
VCCASW VCCIO VCCASW 1.05V 0.67 A
Y22 +1.05VS
VCCASW AM18
VCCIO AM20
VCCIO VCCSUSHDA 3.3V 0.01 A
AM22
VCCMPHY VCCIO AP22
VCCIO
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
AR22 1 1 1 1 1 VCCSPI 3.3V 0.022 A
VCCIO
C144
C145
C146
C147
C148
AT22
VCCIO
2 2 2 2 2
VCCSUS3_3 3.3V 0.261 A
DH82HM86-SR17E-C2_FCBGA695 7 OF 11
VCCDSW3_3 3.3V 0.015 A
V_PROC_IO 1.05V 0.004 A
B B
+1.05VS
+PCH_USB_DCPSUS1 1 R136 2
0_0402_5%
@
10U_0603_6.3V6M
1 2 +PCH_VCCDSW 1
C149
R134 5.1_0402_1%
+PCH_VCCDSW_R
2 @
+1.05VS
1U_0402_6.3V6K
1
C150
+PCH_USB_DCPSUS3 2 R137 1
0_0603_5%
@
2 10U_0603_6.3V6M
10U_0603_6.3V6M
1 C151 1
C152
2 @ 2 @
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 19 of 59
5 4 3 2 1
5 4 3 2 1
+3V_PCH
+PCH_VCCDSW3_3
0.1U_0402_16V7K
1 2
LPT_PCH_M_EDS +3VALW
U2H R138 0_0402_5%
1
D +3V_PCH D
C156
0.1U_0402_16V7K
1
R24 R20
VCCSUS3_3 VCCSUS3_3 2
C153
R26 R22
R28 VCCSUS3_3 VCCSUS3_3
+1.05VS VCCSUS3_3 GPIO/LPC 2
0.1U_0402_16V7K
1 U26
VCCSUS3_3 A16 +PCH_VCCDSW3_3
VCCDSW3_3 +3VS
C154
M24 C157
VSS AA14 +PCH_VCCSST 1 2 PCH Power Rail Table
2 +3VS U35 DCPSST
VCCUSBPLL
0.1U_0402_16V7K
1 AE14 0.1U_0402_16V7K
USB
L24 VCC3_3 AF12
VCC3_3 VCC3_3 Voltage Rail Voltage S0 Iccmax Current (A)
C155
AG14
VCC3_3 +3V_PCH
0.1U_0402_16V7K
U30 1
2 VCCIO
0.1U_0402_16V7K
1 +1.05VS V28 VCC 1.05V 1.29 A
VCCIO
C159
V30 U36
VCCIO VCCIO +1.05VS
C158
Y30
VCCIO +3V_PCH 2
2
VCCIO 1.05V 3.629 A
+1.5VS +PCH_USB_DCPSUS2 Y35 Azalia
1U_0402_6.3V6K DCPSUS2
0.1U_0402_16V7K
1 A26 1
C160 AF34 VCCSUSHDA
VCCVRM VCCADAC1_5 1.5V 0.070 A
C161
+RTCVCC
10U_0603_6.3V6M
1U_0402_6.3V6K
1 +PCH_VCC AP45 K8 1
2 VCC VCCSUS3_3 2
C162
C163
VCCADAC3_3 3.3V 0.0133 A
Y32 A6
+PCH_VCCCLK VCCCLK VCCRTC
2 M29 RTC P14 +PCH_DCPRTC C164 2
+PCH_VCCCLK3_3 VCCCLK3_3 DCPRTC VCCCLK 1.05V 0.306 A
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V6K
P16 1 2 1 1 1
DCPRTC
C167
L29
VCCCLK3_3
C165
C166
0.1U_0402_16V7K VCCCLK3_3 3.3V 0.055 A
L26 AJ12 +PCH_VPROC
M26 VCCCLK3_3 V_PROC_IO AJ14 +3V_PCH 2 2 2
CPU
C +1.05VS VCCCLK3_3 V_PROC_IO C
VCCVRM 1.5V 0.179 A
U32
1 R139 2 V32 VCCCLK3_3 AD12
ICC
+PCH_USB_DCPSUS2
0_0402_5% VCCCLK3_3 SPI VCCSPI
VCC3_3 3.3V 0.133 A
1U_0402_6.3V6K
@ AD34 1
+PCH_VCCCLK VCCCLK
1U_0402_6.3V6K
C169
1 P18 +PCH_VCCCFUSE
VCC
C168
AA30 P20 VCCASW 1.05V 0.67 A
AA32 VCCCLK VCC
VCCCLK L17 2
2 VCCASW +1.05VS
@ AD35 VCCSUSHDA 3.3V 0.01 A
VCCCLK R18
AG30 VCCASW
AG32 VCCCLK 01/02 EC/BIOS share ROM VCCSPI 3.3V 0.022 A
VCCCLK AW40
+PCH_VCC VCCVRM +1.5VS
AD36
+1.05VS VCCCLK AK30 +3VS
VCC3_3 VCCSUS3_3 3.3V 0.261 A
L1 AE30 Thermal
1 2 +PCH_VCC AE32 VCCCLK AK32
4.7UH_NRS2012T4R7MGJ_20% VCCCLK VCC3_3
VCCDSW3_3 3.3V 0.015 A
0.1U_0402_16V7K
1
10U_0603_6.3V6M
1U_0402_6.3V6K
1 1
C170
C171
C172
DH82HM86-SR17E-C2_FCBGA695 8 OF 11 V_PROC_IO 1.05V 0.004 A
2
2 2
Place near pin AP45
Broadwell
+PCH_VPROC +1.05VS
B B
+1.05VS +PCH_VCCCLK +PCH_VPROC R140 2 1 0_0603_5%
1 2
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V6K
R141 0_0603_5% 1 1 1
C173
C174
C175
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 2 2 2
C176
C177
C178
C179
C180
2 2 2 2 2
Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36 INTEL Recommend follow 486714 DG
Place near pin AG30,AG32,AE30,AE32 Different with COMPAL
0_0805_5%
+3VS +PCH_VCCCLK3_3 +PCH_VCCCFUSE R142 1 2
+1.05VS
1U_0402_6.3V6K
1 2 1
C181
R143 0_0603_5%
V0.2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
C182
C183
C184
C185
2 2 2 2
A A
Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32
Security Classification Compal Secret Data
2014/02/25 2015/02/25 Title
Issued Date Deciphered Date PCH (8/9) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 20 of 59
5 4 3 2 1
5 4 3 2 1
D D
U2J LPT_PCH_M_EDS
AL34 K39 U2K LPT_PCH_M_EDS
AL38 VSS VSS L2
AL8 VSS VSS L44 AA16 B19
AM14 VSS VSS M17 AA20 VSS VSS B23
AM24 VSS VSS M22 AA22 VSS VSS B27
AM26 VSS VSS N12 AA28 VSS VSS B31
AM28 VSS VSS N35 AA4 VSS VSS B35
AM30 VSS VSS N39 AB12 VSS VSS B39
AM32 VSS VSS N6 AB34 VSS VSS B7
AM16 VSS VSS P22 AB38 VSS VSS BA40
AN36 VSS VSS P24 AB8 VSS VSS BD11
AN40 VSS VSS P26 AC2 VSS VSS BD15
AN42 VSS VSS P28 AC44 VSS VSS BD19
C AN8 VSS VSS P30 AD14 VSS VSS AY36 C
AP13 VSS VSS P32 AD16 VSS VSS AT43
AP24 VSS VSS R12 AD18 VSS VSS BD31
AP31 VSS VSS R14 AD30 VSS VSS BD35
AP43 VSS VSS R16 AD32 VSS VSS BD39
AR2 VSS VSS R2 AD40 VSS VSS BD7
AK16 VSS VSS R34 AD6 VSS VSS D25
AT10 VSS VSS R38 AD8 VSS VSS AV7
AT15 VSS VSS R44 AE16 VSS VSS F15
AT17 VSS VSS R8 AE28 VSS VSS F20
AT20 VSS VSS T43 AF38 VSS VSS F29
AT26 VSS VSS U10 AF8 VSS VSS F33
AT29 VSS VSS U16 AG16 VSS VSS BC16
AT36 VSS VSS U28 AG2 VSS VSS D4
AT38 VSS VSS U34 AG26 VSS VSS G2
D42 VSS VSS U38 AG28 VSS VSS G38
AV13 VSS VSS U42 AG44 VSS VSS G44
AV22 VSS VSS U6 AJ16 VSS VSS G8
AV24 VSS VSS V14 AJ18 VSS VSS H10
AV31 VSS VSS V16 AJ20 VSS VSS H13
AV33 VSS VSS V26 AJ22 VSS VSS H17
BB25 VSS VSS V43 AJ24 VSS VSS H22
AV40 VSS VSS W2 AJ34 VSS VSS H24
AV6 VSS VSS W44 AJ38 VSS VSS H26
AW2 VSS VSS Y14 AJ6 VSS VSS H31
F43 VSS VSS Y16 AJ8 VSS VSS H36
AY10 VSS VSS Y24 AK14 VSS VSS H40
AY15 VSS VSS Y28 AK24 VSS VSS H7
AY20 VSS VSS Y34 AK43 VSS VSS K10
AY26 VSS VSS Y36 AK45 VSS VSS K15
AY29 VSS VSS Y40 AL12 VSS VSS K20
AY7 VSS VSS Y8 AL2 VSS VSS K29
B B11 VSS VSS BC22 VSS VSS K33 B
B15 VSS BB42 VSS VSS BC28
VSS VSS VSS
DH82HM86-SR17E-C2_FCBGA695 DH82HM86-SR17E-C2_FCBGA695
10 OF 11 11 OF 11
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (9/9) VSS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 21 of 59
5 4 3 2 1
A B C D E
+3VS_CMOS
1 CMOS Camera +3VS
R255 NCMOS@ V1.0 JEDP1
1
(20 MIL) 1 2 1
0_0603_5% EDP_CONN_LANE_N1 2 1
EDP_CONN_LANE_P1 3 2
4 3
R204 EDP_CONN_LANE_N3 5 4
(20 MIL) 5
3 1 2 1 6
D
@ 10U EDP_CONN_LANE_P3
V0.3A Q14 0_0603_5%
1 1
eDP EDP_CONN_LANE_N2
7
8
9
6
7
8
eDP Panel
CMOS@ C317 C318 @ EDP_CONN_LANE_P2
G
2
AO3413_SOT23 0.1U_0402_16V7K 10U_0603_6.3V6M 10 9
V1.0
2 2 EDP_CONN_LANE_N0
EDP_CONN_LANE_P0
11
12
13
10
11
12
CAMERA
R220 CMOS@
150K_0402_5% EDP_CONN_AUX 14 13
(18) CMOS_ON# for CMOS shake issue reserve
EDP_CONN_AUX#
USB20_N8
15
16
17
14
15
16
DMIC
1 (17) USB20_N8 17
C319 CMOS@ 250mA Touch PANEL USB20_P8 18
2
0.1U_0402_16V7K
Camera
(17) USB20_P8
USB20_N9_CONN
USB20_P9_CONN
19
20
21
18
19
20
TOUCH SCREEN
200mA 22 21
DMIC_DATA 23 22
(26) DMIC_DATA DMIC_CLK 24 23
DMIC (26) DMIC_CLK 25 24
1 @ 2 TS_RST# 26 25
(18) TS_ON 27 26
V0.3 R207 0_0402_5% EDP_HPD
(7) EDP_HPD 28 27
BKOFF#
(31) BKOFF# 28
R238 1 2 PCH_PWM 29
(14) PCH_PWM +3VS_CMOS 30 29
10K_0402_5% +3VS_CMOS
2 31 30 2
+3VS 31
+3VS_TOUCH 32
+3VS_TOUCH 32
33
+LCDVDD 33
34
35 34
INVPWR_B+ 36 35 41
W=80mils 37 36 G1 42
2
R375
1
1090mA 38 37 G2 43
CPU_B+ 38 G3
0_0805_5% 39 44
LCD POWER CIRCUIT 39 G4
C316
C315
40 45
40 G5
0.1U_0603_25V7K
0.1U_0603_25V7K
W=80mils 2 2
R205 ACES_50398-04041-001
2 1 CONN@
+12VS_PANEL
@
0_0805_5%
V0.2 @ 1 1
+3VS +LCDVDD
W=80mils V1.0
W=80mils U11 2A
5 1 +LCDVDD V0.2A
IN OUT confirm PWR
1 2A 2 V1.0
GND 1 1
C307 C308
0.1U_0402_16V7K 4 3 4.7U_0603_6.3V6K C309
2 EN OC 0.1U_0402_16V7K
2 2
SY6288C20AAC_SOT23-5
V0.2
(14) PCH_ENVDD
EDP_CPU_LANE_N1 C301 1 2 0.1U_0402_16V7K EDP_CONN_LANE_N1
3 (7) EDP_CPU_LANE_N1 1 2 0.1U_0402_16V7K 3
EDP_CPU_LANE_P1 C302 EDP_CONN_LANE_P1
(7) EDP_CPU_LANE_P1
EDP_CPU_LANE_N0 C303 1 2 0.1U_0402_16V7K EDP_CONN_LANE_N0
(7) EDP_CPU_LANE_N0 EDP_CPU_LANE_P0 1 2 0.1U_0402_16V7K EDP_CONN_LANE_P0
C304
(7) EDP_CPU_LANE_P0
EDP_CPU_AUX C305 1 2 0.1U_0402_16V7K EDP_CONN_AUX
(7) EDP_CPU_AUX EDP_CPU_AUX# 1 2 0.1U_0402_16V7K EDP_CONN_AUX#
C306
(7) EDP_CPU_AUX#
EDP_CPU_LANE_N2 C310 1 2 0.1U_0402_16V7K EDP_CONN_LANE_N2
(7) EDP_CPU_LANE_N2 1 2 0.1U_0402_16V7K
EDP_CPU_LANE_P2 C311 EDP_CONN_LANE_P2
(7) EDP_CPU_LANE_P2
Touch Panel (7) EDP_CPU_LANE_N3
EDP_CPU_LANE_N3
EDP_CPU_LANE_P3
C313
C314
1
1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
EDP_CONN_LANE_N3
EDP_CONN_LANE_P3
(7) EDP_CPU_LANE_P3
+3VS +3VS_TOUCH
JP11 JUMP_43X79
1 2 R201 2 EMI@ 1 0_0402_5%
JP@ 1 2
L28 @EMI@
(17) USB20_N9 USB20_N9 3 4 USB20_N9_CONN
(17) USB20_P9 USB20_P9 2 1 USB20_P9_CONN
MCF12102G900-T_4P V0.2
R206 2 1 0_0402_5%
EMI@
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD Conn/Camera, Touch
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-B111P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 25, 2014 Sheet 22 of 59
A B C D E
5 4 3 2 1
HDMI Connector
+HDMI_5V_OUT
+3VS +5VS C320 @1
@ 2 2200P_0402_50V7K
Q9
W=40mils W=40mils C321 1 2 2200P_0402_50V7K
0.1U_0402_16V7K
1 3
GND
VIN VOUT
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_16V7K
2 1
C323
D R208 D
C322
1M_0402_5% Q6 1 1
2.2K_0402_1%
2.2K_0402_1%
@C325
AP2330W-7_SC59
1
1 2
C324
2N7002H_SOT23-3 @
1
2 2
R209
R210
TMDS_B_HPD 3 1
(14) TMDS_B_HPD
2
2
JHDMI1 CONN@
R211 HDMI_DET 19
18 HP_DET
20K_0402_5% +5V
17
HDMIDAT_CONN 16 DDC/CEC_GND
1
HDMICLK_CONN 15 SDA
Co-lay for EMI 14 SCL
13 Reserved
TMDS_B_CLK#_PCH 1 2 HDMI_CLK-_CK R212 1 @EMI@ 2 0_0402_5% HDMI_CLK-_CONN 12 CEC 20
(7) TMDS_B_CLK#_PCH 11 CK- GND 21
C326 0.1U_0402_16V7K
TMDS_B_CLK_PCH 1 2 HDMI_CLK+_CK R213 1 @EMI@ 2 0_0402_5% HDMI_CLK+_CONN 10 CK_shield GND 22
(7) TMDS_B_CLK_PCH CK+ GND
TMDS_B_DATA0#_PCH C327 1 2 0.1U_0402_16V7K HDMI_TX0-_CK R214 1 @EMI@ 2 0_0402_5% HDMI_TX0-_CONN 9 23
(7) TMDS_B_DATA0#_PCH 8 D0- GND
C328 0.1U_0402_16V7K
TMDS_B_DATA0_PCH 1 2 HDMI_TX0+_CK R215 1 @EMI@ 2 0_0402_5% HDMI_TX0+_CONN 7 D0_shield
(7) TMDS_B_DATA0_PCH D0+
TMDS_B_DATA1#_PCH C329 1 2 0.1U_0402_16V7K HDMI_TX1-_CK R216 1 @EMI@ 2 0_0402_5% HDMI_TX1-_CONN 6
(7) TMDS_B_DATA1#_PCH 5 D1-
C330 0.1U_0402_16V7K
TMDS_B_DATA1_PCH 1 2 HDMI_TX1+_CK R217 1 @EMI@ 2 0_0402_5% HDMI_TX1+_CONN 4 D1_shield
(7) TMDS_B_DATA1_PCH D1+
TMDS_B_DATA2#_PCH C331 1 2 0.1U_0402_16V7K HDMI_TX2-_CK R218 1 @EMI@ 2 0_0402_5% HDMI_TX2-_CONN 3
(7) TMDS_B_DATA2#_PCH 2 D2-
C332 0.1U_0402_16V7K
TMDS_B_DATA2_PCH 1 2 HDMI_TX2+_CK R219 1 @EMI@ 2 0_0402_5% HDMI_TX2+_CONN 1 D2_shield
(7) TMDS_B_DATA2_PCH D2+
C333 0.1U_0402_16V7K
C337
C338
C339
C341
C334
C335
C336
C340
C-H_13-13201948CP
2 2 2 2 2 2 2 2
@EMI@
@EMI@
@EMI@
@EMI@
@EMI@
C C
@EMI@
@EMI@
@EMI@
V0.3
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
1 1 1 1 1 1 1 1
D13 @ESD@ EMI
HDMI_TX0-_CONN 9 1 HDMI_TX0-_CONN
HDMI_TX0+_CONN 8 2 HDMI_TX0+_CONN
HDMI_TX2-_CONN 7 4 HDMI_TX2-_CONN
+3VS
HDMI_TX2+_CONN 6 5 HDMI_TX2+_CONN Pull up R for PCH OR VGA SIDE
Co-lay for EMI
L11 EMI@
3 HDMI_CLK+_CK 3 4 HDMI_CLK+_CONN 2N7002KDWH_SOT363-6
3 4 Q15A
2
TVWDF1004AD0_DFN9
HDMI_CLK-_CK 2 1 HDMI_CLK-_CONN
2 1 1 6 HDMICLK_CONN
DLW21HN900HQ2L_4P (14,16) HDMICLK_NB
5
D12 @ESD@ DLW21HN900HQ2L_4P
HDMI_CLK-_CONN 9 1 HDMI_CLK-_CONN HDMI_TX0-_CK 2 1 HDMI_TX0-_CONN 4 3 HDMIDAT_CONN
2 1 (14,16) HDMIDAT_NB
B HDMI_CLK+_CONN 8 2 HDMI_CLK+_CONN Q15B B
HDMI_TX0+_CK 3 4 HDMI_TX0+_CONN 2N7002KDWH_SOT363-6
HDMI_TX1-_CONN 7 4 HDMI_TX1-_CONN 3 4
L12 EMI@
HDMI_TX1+_CONN 6 5 HDMI_TX1+_CONN
L13 EMI@
HDMI_TX1+_CK 3 4 HDMI_TX1+_CONN
3 4
3 HDMI_TX1+_CK R360 1 2 470_0402_5%
HDMI_TX1-_CK 2 1 HDMI_TX1-_CONN HDMI_TX1-_CK R357 1 2 470_0402_5%
TVWDF1004AD0_DFN9 2 1 HDMI_CLK+_CK R361 1 2 470_0402_5%
DLW21HN900HQ2L_4P 1 2
HDMI_CLK-_CK R356 470_0402_5%
DLW21HN900HQ2L_4P
HDMI_TX2-_CK 2 1 HDMI_TX2-_CONN HDMI_TX0-_CK R355 1 2 470_0402_5%
2 1 HDMI_TX0+_CK R359 1 2 470_0402_5%
HDMI_TX2-_CK R354 1 2 470_0402_5%
HDMI_TX2+_CK 3 4 HDMI_TX2+_CONN HDMI_TX2+_CK R358 1 2 470_0402_5%
3 4
L14 EMI@ +3VS
D11 @ESD@
1
4 3 HDMICLK_CONN D
+HDMI_5V_OUT 4 3 2
G
S Q5
3
2N7002H_SOT23-3
5 2
+5VS Vbus GND
A A
HDMI_DET 6 1 HDMIDAT_CONN
6 1 Security Classification Compal Secret Data Compal Electronics, Inc.
YSUSB2.0-5_SOT-23-6-6 Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI LS & Conn.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B LA-B111P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 25, 2014 Sheet 24 of 59
5 4 3 2 1
5 4 3 2 1
+3_LAN Rising time (10%~90%) >1mS and <100mS
+3VALW +3V_LAN
W=60mils JP6 JP@
1 2
370mA
1 2
JUMP_43X39 Layout Notice : Place as close
chip as possible.
D D
+3V_LAN +3V_LAN V0.2 +3V_LAN
W=60mils +LAN_VDD10
L15
+LAN_REGOUT 1 2
W=60mils 2.2UH +-20% HPC252012NF-2R2M
1
C349
1U_0402_6.3V6K
C350
0.1U_0402_16V7K
C351
0.1U_0402_16V7K
C352
0.1U_0402_16V7K
C353
0.1U_0402_16V7K
@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_16V7K
C354
C355
0.1U_0402_16V7K
@
C342
C343
2 1 1 1 1
1
C344 C345 1 1
2
4.7U_0603_6.3V6K 0.1U_0402_16V7K C347
1
4.7U_0603_6.3V6K C348 +3V_LAN
2
1 0.1U_0402_16V7K 2 2 2 2
2 2
close to pin 22
R221 1 2 10K_0402_5% LAN_WAKE#_R
close to U12 : Pin 11, 32 These caps close to U12 : Pin 23 ( Should be place within 200 mils ) These components close to U12 : Pin 3,8,22,30 These caps close to U12 : Pin 11,32
These components close to U12 : Pin 24 1uF reserved on Pin 22 DVDD33
R567 1 2 10K_0402_5% LAN_PWRDN#_R
V0.3
Green CLK U12
C C
XTLI R362 1 GCLK@ 2 0_0402_5% CLK_25M_LAN_XIN (27)
These caps close to U11
MDI0+ 1 17 PCIE_PRX_C_DTX_P3 C357 1 2 0.1U_0402_16V7K PCIE_PRX_DTX_P3
MDIP0 HSOP PCIE_PRX_DTX_P3 (17)
MDI0- 2 18 PCIE_PRX_C_DTX_N3 C358 1 2 0.1U_0402_16V7K PCIE_PRX_DTX_N3
MDIN0 HSON PCIE_PRX_DTX_N3 (17)
+LAN_VDD10 3 19
AVDD10 PERSTB PLT_RST# (14,28,31,34,36)
MDI1+ 4 20 ISOLATEB R222 1 2 1K_0402_5% +3VS
MDI1- 5 MDIP1 ISOLATEB 21 LAN_WAKE#_R R223 1 2 0_0402_5%
MDIN1 LANWAKEB LAN_WAKE# (31)
MDI2+ 6 22 +LAN_VDD10 V0.3
MDI2- 7 MDIP2 DVDD10 23 +3V_LAN
NOGCLK@ EMI@ +LAN_VDD10 8 MDIN2 VDDREG 24 +LAN_REGOUT
R372 AVDD10 REGOUT
MDI3+ 9 25 1
MDIP3 LED2 T36
C356 1 2 12P_0402_50V8J 1 2 XTLI MDI3- 10 26 LAN_PWRDN#_R R566 1 @ 2 0_0402_5% to EC
MDIN3 LED1/GPIO LAN_PWRDN# (31)
100_0402_1% +3V_LAN 11 27 1
AVDD33 LED0 T37
V0.3A NOGCLK@ LAN_CLKREQ# 12 28 XTLO V0.3
(15,18) CLKREQ_LAN# CLKREQB CKXTAL1
13 29 XTLI
(17) PCIE_PTX_C_DRX_P3 HSIP CKXTAL2
14 30 +LAN_VDD10 R225 ISOLATEB
(17) PCIE_PTX_C_DRX_N3 HSIN AVDD10
Y3 NOGCLK@ V0.3A 15 31 LAN_RSET 1 2
(15) CLK_PCIE_LAN REFCLK_P RSET
1
2 1 16 32 +3V_LAN 2.49K_0402_1%
GND0 XTAL0 (15) CLK_PCIE_LAN# REFCLK_N AVDD33 33 R226
4 3 GND 15K_0402_5%
GND1 XTAL1
25MHZ_10PF_7V25000014
2
NOGCLK@
RTL8111GUL-CG_QFN32_4X4
C359 1 2 12P_0402_50V8J XTLO SA00006ML10
V0.3A
JRJ1 CONN@
B B
9
MDO0+ 1 GND
PR1+ 10
MDO0- 2 GND
FOR EMI suggest PR1-
V0.3A MDO1+ 3
D10 ESD@ PR2+
MDI2+ 1 4 MDI3+ MDO2+ 4 CHASSIS1_GND
TS1 I/O1 I/O3 PR3+
+V_DAC 1 24 MDO2- 5
TCT1 MCT1 PR3-
MDI0+ 2 23 MDO0+ 2 5 V0.2 MDO1- 6
TD1+ MX1+ GND VDD PR2-
MDI0- 3 22 MDO0- MDO3+ 7
TD1- MX1- PR4+ 11
+V_DAC 4 21 MDI3- 3 6 MDI2- MDO3- 8 GND
TCT2 MCT2 I/O2 I/O4 PR4- 12
MDI1+ 5 20 MDO1+ R227 EMI@ AZC099-04S.R7G_SOT23-6 GND
TD2 MX2+ 1 2 1 2
MDI1- 6 19 MDO1- 75_0805_5% CHASSIS1_GND Place Close to TS1 SANTA_130460-3
TD2- MX2- C360 10P_0603_50V8-J DC234007K00
+V_DAC 7 18
TCT3 MCT3 2 1 D14 ESD@ V0.3A
MDI2+ 8 17 MDO2+ MDI0- 1 4 MDI1-
TD3+ MX3+ DL1 I/O1 I/O3
MDI2- 9 16 MDO2- BS4200N-C-LV_SMB-F2
TD3- MX3- EMI@
+V_DAC 10 15 2 5
TCT4 MCT4 GND VDD
MDI3+ 11 14 MDO3+
TD4+ MX4+
MDI3- 12 13 MDO3- MDI0+ 3 6 MDI1+
TD4- MX4- I/O2 I/O4
1 AZC099-04S.R7G_SOT23-6
A A
IH-160-A
C300 SP050007E00 Place Close to TS1
0.01U_0402_16V7K
2
V0.2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN-RTL8111GUL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 25 of 59
5 4 3 2 1
A B C D E F G H
600ohms @100MHz 2A
P/N: SM01000EE00
Place near U10 +5VDDA_CODEC +3VS +3VDD_CODEC +3VDD_CODEC +IOVDD_CODEC
R230 +5VS
1 @ 2 +5VS_PVDD Place near Pin26
+5VS R228 R229
0_0603_5% 0_0603_5%
0.1U_0402_16V7K
0.1U_0402_16V7K
4.7U_0603_6.3V6K
0_0805_5% 2 1 1 1 @ 2 1 @ 2 2 @ 1
+IOVDD_CODEC L10 0_0603_5%
C365
C366
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1
V1.0
C364
1 1
0.1U_0402_16V7K
4.7U_0603_6.3V6K
1
+3VDD_CODEC +1.5VS
C361
C362
C363
1 2 2 1 1
R231 @
C367
C368
1 2 @
2
0_0402_5% 2 2
1 2 2
C369
1U_0402_6.3V6K
2
Place near Pin1 Place near Pin9
41
46
26
40
1
9
U10
Place near Pin40
PVDD1
PVDD2
AVDD1
AVDD2
DVDD
DVDD-IO
(31) WF_MUTE# R202 1 2 0_0402_5% WF_MUTE#_R
R203 1 2 100K_0402_5%
22
V0.2 21 LINE1-L(PORT-C-L) 43 SPK_L-
V0.3 LINE1-R(PORT-C-R) SPK-OUT-L- 42 SPK_L+
24 SPK-OUT-L+
23 LINE2-L(PORT-E-L) 45 SPK_R+
LINE2-R(PORT-E-R) SPK-OUT-R+ 44 SPK_R-
EXT_MIC_RING2 17 SPK-OUT-R-
W=40 mils (34) EXT_MIC_RING2
(34) EXT_MIC_SLEEVE
EXT_MIC_SLEEVE 18 MIC2-L(PORT-F-L) /RING2
MIC2-R(PORT-F-R) /SLEEVE 32
JACK_PLUG Delay circutis
HPOUT-L(PORT-I-L) HP_OUTL (34)
31 33
LINE1-VREFO-L HPOUT-R(PORT-I-R) HP_OUTR (34) +3VS +3VS
V0.2 WF_MUTE#_R 30
LINE1-VREFO-R 10 HDA_SYNC_AUDIO
SYNC HDA_SYNC_AUDIO (13)
DMIC_DATA 2 6 HDA_BITCLK_AUDIO
(22) DMIC_DATA GPIO0/DMIC-DATA BCLK HDA_BITCLK_AUDIO (13)
DMIC_CLK 1 2 DMIC_CLK_R 3
(22) DMIC_CLK GPIO1/DMIC-CLK
1
1 L16 EMI@ SBY100505T-301Y-N @ JACK_SENSE#
V0.2 R377 @
R235 1 2 0_0402_5% PDB 47 5 HDA_SDOUT_AUDIO R378
C370
ALC283-CG 100K_0402_5%
22P_0402_50V8J
(31) EC_MUTE# PDB SDATA-OUT HDA_SDOUT_AUDIO (13)
HDA_RST_AUDIO# 11 8 R236 1 2 33_0402_5% 100K_0402_5%
2 (13) HDA_RST_AUDIO# RESETB SDATA-IN HDA_SDIN0 (13)
V0.3 EMI@
2
EMI@ 48 R346 1 2 SBY100505T-301Y-N
SPDIF-OUT/GPIO2 SPDIF-OUT (34)
3
V0.3 PC_BEEP 12 V0.3 @
PCBEEP 16 5
D
Q19A
JACK_SENSE# R237 1 2 39.2K_0402_1% 13 MONO-OUT MONO-OUT (27) Sub-woofer G
S DMN66D0LDW-7_SOT363-6
14 SENSE A MIC2-VREFO
2 MIC2-VREFO (34) 2
4
SENSE B
6
29 @
V0.3 37 MIC2-VREFO C372 2 1 4.7U_0603_6.3V6K PLUG_IN# 1 2 2 G
D
Q19B
CBP (34) PLUG_IN#
C373 2 1 1U_0402_6.3V6K 35 7 LDO3 C374 2 1 4.7U_0603_6.3V6K @ S
CBN LDO3-CAP 39 LDO2 R380 DMN66D0LDW-7_SOT363-6
1
LDO2-CAP 27 LDO1 C375 2 1 4.7U_0603_6.3V6K 10K_0402_5% 1
LDO1-CAP 1
36 R379 1 2 100K_0402_5%
+3VS CPVDD
C376 2 1 4.7U_0603_6.3V6K @ @
28 C377 1 2 1U_0402_6.3V6K C500 C499
20 VREF 10U_0603_6.3V6M 2 2 10U_0603_6.3V6M
CPVREF 15 JDREF R239 1 2 20K_0402_1%
C378 2 1 4.7U_0603_6.3V6K 19 JDREF 34 CPVEE
MIC-CAP CPVEE
2
R240 1 2 0_0402_5% 4 PLUG_IN# R376 1 2 0_0402_5% JACK_SENSE#
49 DVSS 25 C379
V0.3 Thermal PAD AVSS1 38 1U_0402_6.3V6K
AVSS2 1 Reserve for cancel Delay circutis
ALC283-CG_MQFN48_6X6
R240 pop on ALC283, SA000060500
NC on ALC233
+3VLP
+3VS
1
100K_0402_5%
EXT_MIC_SLEEVE
Reserve for ESD request.
R232
EMI
3
2N7002KDWH_SOT363-6
SPK_R+_CONN SPK_L-_CONN R233 @
Q16B
2
3 3
100K_0402_5% 5
SPK_R-_CONN SPK_L+_CONN
6
1 2 HDA_BITCLK_AUDIO
4
3
2N7002KDWH_SOT363-6
Q16A
R248@EMI@ 27_0402_5%
1 HDA_RST_AUDIO# 1 2 2
@EMI@ @ESD@ @ESD@ R234
C387 10K_0402_5% 1
1
1U_0402_6.3V6K
C371
33P_0402_50V8J D15 D16
2 PACDN042Y3R_SOT23-3 PACDN042Y3R_SOT23-3 @
1
GNDA
2
@EMI@
wide 40MIL JSPK1 CONN@
R245 1 2 0_0402_5% EC Beep (31) BEEP#
1 2 SPK_R+ R241 1 2 PBY160808T-330Y-N SPK_R+_CONN 4 6
C384 0.1U_0402_16V7K SPK_R- R242 1 2 PBY160808T-330Y-N SPK_R-_CONN 3 4 G2 5
SPK_L+ R243 1 2 PBY160808T-330Y-N SPK_L+_CONN 2 3 G1
@EMI@ C386 2
R246 1 2 0_0402_5% R249 SPK_L- R244 1 2 PBY160808T-330Y-N SPK_L-_CONN 1
1 2PC_BEEP1 1 2 1 2 PC_BEEP 1
PCH Beep (13) HDA_SPKR
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
@EMI@ C385 0.1U_0402_16V7K 1K_0402_5% EMI@ 1 1 1 1 CVILU_CI4304M2HR0-NH
R247 1 2 0_0402_5% EMI@ SP02000Y500
C380
C381
C382
C383
0.1U_0402_16V7K
1
EMI@
@ EMI@
R200 1
@EMI@
2 0_0402_5% PC Beep R250
10K_0402_5% V0.2 EMI@
2
EMI@
2
EMI@
2
EMI@
2
V0.3A
2
4 4
V0.2
GND GNDA
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio ALC283
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-B111P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 25, 2014 Sheet 26 of 59
A B C D E F G H
Place near Pin25
Sub Woofer +5VS
+12VS_WF
V0.2
R251
2 @ 1
+12VS
10U_0805_25V6K
0.1U_0402_16V7K
1 0_0805_5%
1
C388
WF@ C389
2
1
1
2
WF@
10_0603_5%
R252
WF@
@ 100K_0402_5%
R253
U14 WF@
2
from EC WF@
R254 1 2 1K_0402_5% 1 28 WF_GNDA
(31) EC_MUTE#_WF 2 SD# LPVDD 27
FLAG# LPVDD
C390 WF@
V0.3 3 26
WF_GNDA LINP LBSP
4 25 1 2 0.47U_0603_10V
WF@ LINN LOUTP
WF@ GAIN0 5 24 JSPK2 CONN@
WF@ GAIN1 6 GAIN0 PGND 4
WF@ GAIN1 23 SPKWF+ 3 GND
LOUTN EMI@ GND
C391 1 2 1U_0402_16V6K 7 22 SPKWF+ L29 1 2 SPKWF+_CONN 2
AVDD LBSN FBMA-L11-201209-221LMA30_2P 1 2
8 21 EMI@ 1
WF_GNDA AGND RBSN
C392 1
2 1U_0402_16V6K VCLAMP 20 SPKWF- SPKWF- L40 1 2 SPKWF-_CONN ACES_50271-0020N-001
Close to U14 WF_GNDA 20K_0402_1% R224 2 1 2 WF@ 1 9
VCLAMP
ROUTN FBMA-L11-201209-221LMA30_2P
1U_0402_16V6K C469 21 R297 62K_0402_1% 10 19
PLIMIT PGND C394 WF@
EMI@
EMI@
V0.2 V0.2
1000P 50V X7R 0603
1000P 50V X7R 0603
1
1
17.4K_0402_1% 2 R299 1 C393 1 2 0.1U_0603_16V7K 11 18 1 2 0.47U_0603_10V
WF_GNDA RINN ROUTP
1
R1564 @ R1565 @ 12 17 @EMI@ WF_GNDA
RINP RBSP R349 R348 @EMI@
2 1 2 1 30K_0402_1% 2 R341 1 C395 1 2
(26) MONO-OUT 0_0402_5% 0_0402_5% 0.1U_0603_16V7K 13 16 10_0402_5% 10_0402_5%
C396
C397
2
2
41.2K_0402_1% 2 R342 1 WF@ 14 NC RPVDD 15
WF_GNDA +12VS_WF
1 2
1 2
V1.0 WF@ MONO RPVDD
1 1 @EMI@ C477
680P_0402_50V7K 2 1 C472 29 C478 @EMI@
C450 @ C443 @ GND 330P_0402_50V7K 330P_0402_50V7K
10U_0805_25V6K
0.1U_0402_16V7K
22P_0402_50V8J 22P_0402_50V8J V0.2 WF_GNDA WF_GNDA
C471
WF@ C470
WF@ 1
2
1
2 2
WF@ TPA3113D2PWPR_HTSSOP28 WF_GNDA
WF@ SA00004UH00
WF@
2
WF@ 2
WF_GNDA
WF_GNDA WF_GNDA
WF_GNDA
+5VS
R257 1 @ 2 10K_0402_5% GAIN0
R382 1 2 0_0402_5% V
@EMI@ R258 1 @ 2 10K_0402_5% GAIN1
R381 1 2 0_0402_5%
WF@
@EMI@ R259 1 2 10K_0402_5%
R383 1 2 0_0402_5% WF@
@EMI@ R260 1 2 10K_0402_5%
V1.0
WF_GNDA WF_GNDA
+CHGRTC_R
GCLK@
Green CLK +RTCVCC
390_0402_5% 2 1 R366
1
22U_0603_6.3V6M 2 1 C496 R374
U24 0_0402_5%
GCLK@ @
+3VLP C495
2
GCLK@ 10 14 1 2 2.2U_0402_6.3V6M
C485 VBAT VDD_RTC_OUT GCLK@
1 2 15
0.1U_0402_16V7K +V3.3A
2
+3V_LAN VDD 9 CLK_32K_RTC_XIN_R R373 1 GCLK@ 2 0_0402_5% CLK_32K_RTC_XIN
32kHz CLK_32K_RTC_XIN (13)
11 12 CLK_27M_VGA_XIN_R R364 1 GCLK@ 2 22_0402_5% CLK_27M_VGA_XIN
+3V3_AON VDDIO_27M 27MHz CLK_27M_VGA_XIN (36)
+3V_LAN 8 6 CLK_25M_LAN_XIN_R R365 1 GCLK@ 2 33_0402_5% CLK_25M_LAN_XIN
VDDIO_25M_A 25MHz_A CLK_25M_LAN_XIN (25)
+1.05VS 3 5 CLK_25M_PCH_XIN_R R363 1 GCLK@ 2 0_0402_5% CLK_25M_PCH_XIN
VDDIO_25M_B 25MHz_B CLK_25M_PCH_XIN (15)
C489 1 1 1 25M_GREEN_XIN 1
0.1U_0402_16V7K
0.1U_0402_16V7K
C487 C488 25M_GREEN_XOUT 16 XTAL_IN
1 for EMI
0.1U_0402_16V7K
0.1U_0402_16V7K
XTAL_OUT
GND1
GND2
GND3
GND4
C486
GCLK@
GCLK@
GCLK@
2 2 2
GCLK@
2
SLG3NB304VTR_TQFN16_2X3
4
7
13
17
GCLK@ C498 1 2 10P_0402_25V8J
@EMI@
C491 1 2 10P_0402_25V8J
@EMI@
C492 1 2 10P_0402_25V8J
@EMI@
GCLK@ V0.2A V0.3A C490 1 2 10P_0402_25V8J
@EMI@
C494 1 2 18P_0402_50V8J 25M_GREEN_XIN
Reserve for EMI
Y4 GCLK@
2 1 V0.3A
GND0 XTAL0
4 3
GND1 XTAL1
25MHZ_12PF_7V25000012
C493 1 2 15P_0402_50V8J 25M_GREEN_XOUT
GCLK@
V0.3A
V0.2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sub-Woofer / Green CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 27 of 59
1 2 3 4 5
WLAN
A A
+3VS +3VS_WLAN
JP7
1 2
1 2
JUMP_43X39 1 1
JP@
C398 C399 @
For Power consumption 4.7U_0603_6.3V6K 0.1U_0402_16V7K
Measurement
2 2
V0.3A NGFF for WLAN (TYPE 2230)
+3VS_WLAN
JWLAN1 CONN@
1 2
USB20_P10 3 GND 3.3VAUX 4
(17) USB20_P10 USB20_N10 5 USB_D+ 3.3VAUX 6
Bluetooth (17) USB20_N10
7 USB_D- LED1# 8
B 9 GND PCM_CLK 10 B
11 SIDO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDO_DAT0 PCM_OUT 16
17 SDO_DAT1 LED2# 18
19 SDO_DAT2 GND 20
21 SDO_DAT3 UART_W AKE# 22
SDIO_W AKE# UART_RX For EC to detect
23
SDIO_RESET# debug card insert.
24 R267 1 2
V0.2 25 UART_TX 26 100K_0402_5%
27 GND UART_CTS 28
(17) PCIE_PTX_C_DRX_P2 29 PETP0 UART_RTS 30
(17) PCIE_PTX_C_DRX_N2 PETN0 RESERVED EC_TX (31,34)
31 32
33 GND RESERVED 34 EC_RX (31,34)
(17) PCIE_PRX_DTX_P2 PERP0 RESERVED
35 36
(17) PCIE_PRX_DTX_N2 37 PERN0 COEX3 38
39 GND COEX2 40
(15) CLK_PCIE_WLAN1 REFCLKP0 COEX1
41 42 SUSCLK
(15) CLK_PCIE_WLAN1# REFCLKN0 SUSCLK SUSCLK (14)
43 44
GND PERST0# PLT_RST# (14,25,31,34,36)
45 46
(15) CLKREQ_WLAN# CLKEQ0# W _DISABLE2# W_DISABLE#2 (14,18)
(14,18) PCIE_WAKE# R263 1 @ 2 0_0402_5% 47 48
W_DISABLE#1 (14,18)
49 PEW AKE0# W _DISABLE1# 50
51 GND I2C_DATA 52
53 RSRVD/PETP1 I2C_CLK 54
55 RSRVD/PETN1 ALERT 56
57 GND RESERVED 58
59 RSRVD/PERP1 RESERVED 60
C
61 RSRVD/PERN1 RESERVED 62 C
63 GND RESERVED 64
65 RESERVED 3.3VAUX 66
RESERVED 3.3VAUX +3VS_WLAN
67
GND
69 68
MTG77 MTG76
CONCR_213EAAA32FA
SP070011I00
D D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NGFF (WLAN/BT)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 25, 2014 Sheet 28 of 59
1 2 3 4 5
1 2 3 4 5
SATA HDD CONN.
A A
+3VS JHDD1
SATA_PTX_C_DRX_P4_RC400 2 1 0.01U_0402_16V7K SATA_PTX_DRX_P4_C 1
V1.0 SATA_PTX_C_DRX_N4_RC402 2 1 0.01U_0402_16V7K SATA_PTX_DRX_N4_C 2 1
U15 @ 3 2
7 10 SATA_PRX_C_DTX_N4_RC403 2 1 0.01U_0402_16V7K SATA_PRX_DTX_N4_C 4 3
+3VS EN VDD 4
20 SATA_PRX_C_DTX_P4_RC404 2 1 0.01U_0402_16V7K SATA_PRX_DTX_P4_C 5
SATA_PTX_DRX_P4 0.01U_0402_16V7K 1 2 C405 SATA_PTX_C_DRX_P4 1 VDD 6 5
(13) SATA_PTX_DRX_P4 SATA_PTX_DRX_N4 1 2 C401 SATA_PTX_C_DRX_N4 2 A_INp 6 DEW2 VCC 7 6
0.01U_0402_16V7K
(13) SATA_PTX_DRX_N4 A_INn NC 16 DEW1 VCC 8 7
SATA_PRX_DTX_P4 0.01U_0402_16V7K 1 2 C406 SATA_PRX_C_DTX_P4 5 NC 9 8
(13) SATA_PRX_DTX_P4 SATA_PRX_DTX_N4 1 2 C407 SATA_PRX_C_DTX_N4 4 B_OUTp 9 SATA1_A_PRE0 DE1 REXT 1 2 +5VS_HDD 10 9
0.01U_0402_16V7K +5VS @
(13) SATA_PRX_DTX_N4 B_OUTn A_PRE0 8 10
SATA1_B_PRE0 DE2 DE_B R345 0_0805_5%
SDA EQ2 SATA1_A_PRE1 19 B_PRE0
DE_A EQ1 SATA1_B_PRE1 17 A_PRE1 15 SATA_PTX_C_DRX_P4_R
B_PRE1 A_OUTp 14 SATA_PTX_C_DRX_N4_R
SCK GND SATA1_TEST 18 A_OUTn
3 TEST 11 SATA_PRX_C_DTX_P4_R
13 GND B_INp 12 SATA_PRX_C_DTX_N4_R 11
21 GND B_INn 12 GND
EPAD GND
PS8527CTQFN20GTR2-A1_TQFN20_4X4 ACES_50208-01001-001
CONN@
U15 Parade@ U15 TI@ SP01000JF10
B B
PS8527CTQFN20GTR2-A1_TQFN20_4X4 SN75LVCP601RTJR_TQFN20_4X4
SA00007JU00 SA00003ZX00
V0.2
Add EQ pin for PI3EQX6741STZDEX
+3VS
Place caps.
+3VS
near U15 +5VS_HDD
Pleace near HDD CONN
V0.3 +5VS_HDD
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
TI@ @
1U_0402_6.3V6K
C408
0.1U_0402_16V7K
C411
0.01U_0402_16V7K
C412
SCK GND SATA1_TEST 1 R269 2 0_0402_5% SATA1_TEST 1 R268 2 0_0402_5% 1 1 1 1 1 1
C413
C414
C409
C410
@ @
DE_A EQ1 SATA1_B_PRE11 R270 2 0_0402_5% SATA1_B_PRE11 R271 2 4.7K_0402_5%
@ Parade@ @ @
2
C SDA EQ2 SATA1_A_PRE11 R272 2 0_0402_5% SATA1_A_PRE1 1 R273 2 4.7K_0402_5% 2 2 2 2 2 2 C
@ @
REXT DE1 1
SATA1_A_PRE0 R274 2 0_0402_5% V1.0 SATA1_A_PRE01 R275 2 4.7K_0402_5% V0.3A
@ @
DE_B DE2 SATA1_B_PRE01 R276 2 0_0402_5% SATA1_B_PRE01 R277 2 4.7K_0402_5%
@ @
DEW1 1 R296 2 0_0402_5% VCC DEW1 1 R340 2 4.7K_0402_5%
@ @
DEW2 1 R369 2 0_0402_5% VCC DEW2 1 R384 2 4.7K_0402_5%
TI DE1/DE2 dB EQ1/EQ2 dB
NC -6 NC 0 V0.3
0 0 0 7
1 -3 1 14
Asmidia DE_X dB
0 +1.5
1 +3.0
D D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/SSD
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B LA-B111P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 25, 2014 Sheet 29 of 59
1 2 3 4 5
A B C D E
@EMI@
R278 2 1 0_0402_5%
+USB3_VCCA
L17 EMI@ +USB3_VCCA
3 4 U3RXDN1 +5VALW
2A
(17) USB3_RX1_N 3 4 JUSB1 CONN@
U3TXDP1 9 U16 W=80mils
2 1 U3RXDP1 1 SSTX+ 1
(17) USB3_RX1_P 2 1 U3TXDN1 8 VBUS 5 OUT
DLW21HN900HQ2L_4P CON-USBP0+ 3 SSTX- IN 2
D+ 1 2 GND
R279 2 1 0_0402_5% 7 C417 @ C418 4
@EMI@ CON-USBP0- 2 GND 10 EN 3 USB_OC0#
6 D- GND 11 OCB USB_OC0# (17,18)
U3RXDP1 0.1U_0402_16V7K 2.2U_0603_10V6K
1 R280 2 @EMI@ 1 0_0402_5% 4 SSRX+ GND 12 2 1 1
GND GND 1
U3RXDN1 5 13 SY6288D20AAC_SOT23-5
L18 EMI@ SSRX- GND + C415
2 1 U3TXDN1_R 3 4 U3TXDN1 TAITW_PUBAU2-09FNLS1NN4H0 220U_6.3V_M
(17) USB3_TX1_N 3 4
C419 0.1U_0402_16V7K V0.2 PCB Footprint = C_MP6VLPS220MC4R2
2
DC233008A20
2 1 U3TXDP1_R 2 1 U3TXDP1 USB_ON#
(17) USB3_TX1_P 2 1 (31) USB_ON#
C420 0.1U_0402_16V7K
DLW21HN900HQ2L_4P
R281 2 1 0_0402_5%
EMI @EMI@
Co-lay
D17
U3TXDP1 1 9U3TXDP1
U3TXDN1 2 8U3TXDN1 D18
EMI 3 CON-USBP0-
U3RXDP1 4 7U3RXDP1 1
R282 2 1 0_0402_5%
@EMI@ 2 CON-USBP0+
U3RXDN1 5 6U3RXDN1
DLW21HN900HQ2L_4P YSLC05CH_SOT23-3
USB20_N0 2 1 CON-USBP0-
(17) USB20_N0 2 1 @ESD@
3
USB20_P0 3 4 CON-USBP0+
(17) USB20_P0 3 4 TVWDF1004AD0_DFN9
L19 EMI@ @ESD@
R283 2 1 0_0402_5%
@EMI@
2 2
+USB3_VCCB
@EMI@
R284 2 1 0_0402_5% JUSB2 CONN@
U3TXDP2 9 +USB3_VCCB
L20 EMI@ 1 SSTX+
3 4 U3RXDN2 U3TXDN2 8 VBUS +5VALW 2A
(17) USB3_RX2_N 3 4 CON-USBP1+ 3 SSTX-
D+
U17 W=80mils
7 1
2 1 U3RXDP2 CON-USBP1- 2 GND 10 5 OUT
(17) USB3_RX2_P 2 1 6 D- GND 11 IN 2
U3RXDP2 1 2
DLW21HN900HQ2L_4P 4 SSRX+ GND 12 4 GND
C423 @ C424
R285 2 1 0_0402_5% U3RXDN2 5 GND GND 13 EN 3 USB_OC0#
@EMI@ SSRX- GND 0.1U_0402_16V7K 2.2U_0603_10V6K OCB
TAITW_PUBAU2-09FNLS1NN4H0 2 1
3
1 3
R286 2 1 0_0402_5% SY6288D20AAC_SOT23-5
@EMI@ + C416
DC233008A20
L21 EMI@ 220U_6.3V_M
2 1 U3TXDN2_R 3 4 U3TXDN2 V0.2 PCB Footprint = C_MP6VLPS220MC4R2
(17) USB3_TX2_N 3 4 2
C425 0.1U_0402_16V7K
USB_ON#
2 1 U3TXDP2_R 2 1 U3TXDP2
(17) USB3_TX2_P 2 1
C426 0.1U_0402_16V7K
DLW21HN900HQ2L_4P
R287 2 1 0_0402_5%
EMI @EMI@ D19
Co-lay U3RXDN2 1 9 U3RXDN2
U3RXDP2 2 8 U3RXDP2
U3TXDN2 4 7 U3TXDN2
D20
EMI U3TXDP2 5 6 U3TXDP2 3 CON-USBP1+
@EMI@ 1
R288 2 1 0_0402_5% 2 CON-USBP1-
L22 EMI@ 3
USB20_P1 3 4 CON-USBP1+ YSLC05CH_SOT23-3
(17) USB20_P1 3 4 TVWDF1004AD0_DFN9 @ESD@
@ESD@
USB20_N1 2 1 CON-USBP1-
(17) USB20_N1 2 1
DLW21HN900HQ2L_4P
R289 2 1 0_0402_5%
@EMI@
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0 Port
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-B111P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 25, 2014 Sheet 30 of 59
A B C D E
5 4 3 2 1
+3VLP_EC +EC_VCCA 3.3V
+3VLP For Power consumption Vcc Board ID
JP8 Measurement V0.2 L23 Ra 100K +/- 1% +3VLP_EC
1 2 1 2 +EC_VCCA
1 2 BLM15PD800SN1D Board ID Rb VAD_BID typ V
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1000P_0402_50V7K
1000P_0402_50V7K
0_0402_5%
JUMP_43X39 1 1 1 2 2 1
+3VLP
C427
C428
C429
C430
C431
R290
JP@ @ @ @ R291 @
V0.3 C432
0 0 0 V Ra 100K_0402_1%
JP12 +EC_VCCLPC 0.1U_0402_16V7K 12K +/- 1%
1 2 2 2 2 1 1 2 1 0.354 V
+3VALW
1
1 2
2
15K +/- 1% V0.2 BRDID
JUMP_43X39 ECAGND
2 0.430 V
ECAGND (47)
1
V0.3 @ 20K +/- 1%
3 0.550 V R292 @
1
C433
111
125
D D
Rb 0_0402_5% 0.1U_0402_16V7K
22
33
96
67
U18
9
@
2
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
2
MAIN@ V0.2
R560 2 1 0_0402_5% 1 21
(14,18) GATEA20 2 GATEA20/GPIO00 GPIO0F 23 KBL_W_PWM (32) Analog Board ID definition,
(14,18) KB_RST# 3 KBRST#/GPIO01 BEEP#/GPIO10 26 BEEP# (26) Please see page 3.
(16) SERIRQ 4 SERIRQ GPIO12 27 EC_FAN_PWM1 (34)
LPC_FRAME#
(16) LPC_FRAME# LPC_AD3 5 LPC_FRAME# ACOFF/GPIO13 EC_FAN_PWM2 (34)
(16) LPC_AD3 LPC_AD2 7 LPC_AD3 2 1 100P_0402_50V8J ECAGND
(16) LPC_AD2 LPC_AD2 PWM Output C438
LPC_AD1 8 63 VCIN1_BATT_TEMP BATT_TEMP
(16) LPC_AD1 10 LPC_AD1 BATT_TEMP/GPIO38 64 VCIN1_BATT_TEMP (47)
LPC_AD0 LPC & MISC VCIN1_BATT_DROP
(16) LPC_AD0 LPC_AD0 GPIO39 65 ADP_I VCIN1_BATT_DROP (47)
12 ADP_I/GPIO3A 66 ADP_I (47,48)
(15) CLK_PCI_EC CLK_PCI_EC AD Input
13 CLK_PCI_EC GPIO3B 75 BRDID ADP_ID (46)
(14,25,28,34,36) PLT_RST# EC_RST# V0.2 37 PCIRST#/GPIO05 GPIO42 76
T38 EC_SCI# 20 EC_RST# IMON/GPIO43 2 @ 1 BKOFF# ENBKL (14)
R368
(18) EC_SCI# 38 EC_SCII#/GPIO0E 0_0402_5%
V1.0 PWR cancel GPIO1D 68
DAC_BRIG/GPIO3C 70 V0.2 AOU_EN (34)
(32) KSI[0..7] EN_DFAN1/GPIO3D 71 AOU_ILIM (34) DS3
DA Output IREF/GPIO3E ADP_ID_CLOSE (46)
KSI0 55 72
KSI1 56 KSI0/GPIO30 CHGVADJ/GPIO3F SUSWARN# (14)
+3VLP_EC KSI2 57 KSI1/GPIO31
KSI3 58 KSI2/GPIO32 83 EC_MUTE#
KSI4 59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 USB_ON# EC_MUTE# (26)
KSI5 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 EC_MUTE#_WF V0.2 USB_ON# (30)
1 2 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 EC_MUTE#_WF (27)
@ LAN_WAKE# KSI6 PS2 Interface
KSI7 62 KSI6/GPIO36 EAPD/GPIO4D 87 TP_CLK SYS_PWROK (14,5)
R295 10K_0402_5%
(32) KSO[0..17] KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA TP_CLK (32)
C 1 2 VCIN1_BATT_TEMP KSO1 40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA (32) C
@
R293 47K_0402_5% KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97
KSO4 43 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 98 LAN_PWRDN# (25)
V0.2 KSO5 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 ME_FLASH PWR_LEVEL (36) VGA_AC_DET
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH1 ME_FLASH (13)
KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH1 (47) NTC_V
KSO7 46 SPI Device Interface
1 2 ACIN EC KSO8 47 KSO7/GPIO27
C435 100P_0402_50V8J KSO9 48 KSO8/GPIO28 119 SPI_SO_L
KSO10 49 KSO9/GPIO29 SPIDI/GPIO5B 120 SPI_SI_R SPI_SO_L (16)
2 1 VCOUT1_PROCHOT# KSO11 50 KSO10/GPIO2A SPIDO/GPIO5C 126 SPI_CLK_PCH_EC 1 2 SPI_SI_R (16)
@
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 SPI_CLK_PCH (16)
R300 100K_0402_5% KSO12 51 128 SPI_SB_CS0# R118 15_0402_5%
52 KSO12/GPIO2C SPICS#/GPIO5A SPI_SB_CS0# (16)
KSO13
2 @ 1 EC_MUTE# KSO14 53 KSO13/GPIO2D
R302 10K_0402_5% KSO15 54 KSO14/GPIO2E 73 VGA_ALERT#
KSO16 81 KSO15/GPIO2F ENBKL/GPIO40 74 VGA_ALERT# (36)
82 KSO16/GPIO48 PECI_KB930/GPIO41 89 VGATE (55)
@EMI@ @EMI@ KSO17
2 1 2 1CLK_PCI_EC KSO17/GPIO49 FSTCHG/GPIO50 90 WF_MUTE# (26) V0.2
BATT_CHG_LED#
BATT_CHG_LED#/GPIO52 91 BATT_CHG_LED# (33)
C436 R303 CAPS_LED#
EC_SMB_CK1 77 CAPS_LED#/GPIO53 92 PWR_LED# CAPS_LED# (32)
22P_0402_50V8J 33_0402_5%
(47,48) EC_SMB_CK1 EC_SMB_CK1/GPIO44 GPIO PWR_LED#/GPIO54 PWR_LED# (33)
EC_SMB_DA1 78 93 BATT_LOW_LED#
1 2 (47,48) EC_SMB_DA1 79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95 BATT_LOW_LED# (33)
PLT_RST# EC_SMB_CK2 SM Bus SYSON
(16,32,36) EC_SMB_CK2 EC_SMB_DA2 80 EC_SMB_CK2/GPIO46 SYSON/GPIO56 121 SYSON (35,50)
C497 100P_0402_50V8J
(16,32,36) EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 VR_ON (55)
@ESD@ PM_SLP_S4#
PM_SLP_S4#/GPIO59 PM_SLP_S4# (14)
PM_SLP_S3# 6 100 EC_RSMRST#
(14) PM_SLP_S3# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_RSMRST# (14)
DS3 PM_SLP_S5# AOU_CTL3 V0.2
(14) PM_SLP_S5# 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 AOU_CTL3 (34)
(35) PCH_PWR_EN EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 VCIN1_ADP_PROCHOT (47) Turbo_V
V0.2
LAN_WAKE# 16 103 VCOUT1_PROCHOT#
(25) LAN_WAKE# GPIO0A H_PROCHOT#_EC/GPXIOA06 VCOUT1_PROCHOT# (47) PROCHOT
17 104 VCOUT0_MAIN_PWR_ON
(14) SLP_SUS# GPIO0B VCOUT0_PH/GPXIOA07 VCOUT0_MAIN_PWR_ON (49) MAINPWON
18 GPO 105 R367 2 1 BKOFF#
B (54) PWR_GPS_DOWN# V0.2 19 GPIO0C BKOFF#/GPXIOA08 106 BKOFF# (22) B
GPIO PBTN_OUT# 0_0402_5% DS3
+3VS +3VLP_EC (14) AC_PRESENT_R 25 GPIO0D PBTN_OUT#/GPXIOA09 107 PBTN_OUT# (14)
DPWROK_EC
(48) ACOFF EC_TACH1 28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108 +1.05VS_PGOOD DPWROK_EC (14)
RP25
1 8 EC_SMB_CK1 (34) EC_TACH1 EC_TACH2 V0.2 29 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 +1.05VS_PGOOD (52)
2 7 EC_SMB_DA1 EC (34) EC_TACH2 EC_TX 30 EC_PME#/GPIO15
3 6 EC_SMB_CK2 (28,34) EC_TX EC_RX 31 EC_TX/GPIO16 110 ACIN
4 5 EC_SMB_DA2 (28,34) EC_RX PCH_PWROK 32 EC_RX/GPIO17 AC_IN/GPXIOD01 112 EC_ON ACIN (48)
V0.3 (14,9) PCH_PWROK 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 ON/OFF EC_ON (49)
(33) TP_LOCK_LED# 36 SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 115 LID_SW# ON/OFF (33)
2.2K_0804_8P4R_5%
(32) NUM_LED# NUM_LED#/GPIO1A GPI LID_SW#/GPXIOD04 LID_SW# (33)
116 SUSP#
1 2 TP_CLK SUSP#/GPXIOD05 117 NUVOTON_VTT R370 1 2 10K_0402_5% SUSP# (35,50,51,52,53)
@ +1.05VS
R304 4.7K_0402_5% GPXIOD06 118 PECI_KB9012 R306 1 2 43_0402_1%
PECI_KB9012/GPXIOD07 H_PECI (5)
AGND/AGND
1 2 TP_DATA EC V0.3 122
R305 4.7K_0402_5% (33) NOVO# DGPU_PWR_EN 123 XCLKI/GPIO5D 124 +V18R R307 1 2 0_0402_5%
GND/GND
GND/GND
GND/GND
GND/GND
(14,45) DGPU_PWR_EN XCLKO/GPIO5E V18R +3VLP_EC
GND0
1 2 EC_SCI# V0.2 V0.2 V0.3
R294 10K_0402_5%
1 2 EC_TACH1 KB9022C_LQFP128_14X14
11
24
35
94
113
ECAGND 69
R568 10K_0402_5% V0.3 SA000075S20 20mil
1 2 EC_TACH2 V0.2 -- PWR
R569 10K_0402_5%
L24 R309 1 2 0_0402_5% R308 1 2 0_0402_5% VCOUT1_PROCHOT#
2 1 (55) VR_HOT#
BLM15PD800SN1D V0.3
H_PROCHOT# V0.2
V0.2 (5) H_PROCHOT#
ECAGND
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
EC ENE-KB9022 C Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 31 of 59
5 4 3 2 1
KSI[0..7]
(31) KSI[0..7]
KSO[0..17]
INT_KBD CONN.
(31) KSO[0..17]
SMSC thermal sensor
15"
placed near by VRAM +3VS
17"
1
JKB1 CONN@
KSI1 R1001 1 KB15@ 2 0_0402_5% KB01 1 JKB2 CONN@ +3VS R310
KSI7 R1002 1 KB15@ 2 0_0402_5% KB02 2 1 KSI1 1
2 1 10K_0402_5%
KSI6 R1003 1 KB15@ 2 0_0402_5% KB03 3 KSI7 2 @
KSO9 R1004 1 KB15@ 2 0_0402_5% KB04 4 3 KSI6 3 2 U20
2
KSI4 R1005 1 KB15@ 2 0_0402_5% KB05 5 4 KSO9 4 3 C444 0.1U_0402_16V7K
5 4 2
KSI5 R1006 1 KB15@ 2 0_0402_5% KB06 6 KSI4 5
KSO0 R1007 1 KB15@ 2 0_0402_5% KB07 7 6 KSI5 6 5 1 10 EC_SMB_CK2
7 6 VDD SMCLK EC_SMB_CK2 (16,31,36)
KSI2 R1008 1 KB15@ 2 0_0402_5% KB08 8 KSO0 7
KSI3 R1009 1 KB15@ 2 0_0402_5% KB09 9 8 KSI2 8 7 1 REMOTE1+ 2 9 EC_SMB_DA2
9 8 DP1 SMDATA EC_SMB_DA2 (16,31,36)
KSO5 R1010 1 KB15@ 2 0_0402_5% KB10 10 KSI3 9
KSO1 R1011 1 KB15@ 2 0_0402_5% KB11 11 10 KSO5 10 9 REMOTE1- 3 8
KSI0 R1012 1 KB15@ 2 0_0402_5% KB12 12 11 KSO1 11 10 DN1 ALERT#
KSO2 13 12 KSI0 12 11 REMOTE2+ 4 7
KSO4 14 13 KSO2 13 12 (33) REMOTE2+ DP2 THERM#
KSO7 15 14 KSO4 14 13 REMOTE2- 5 6
16 15 15 14 (33) REMOTE2- DN2 GND
KSO8 KSO7
KSO6 17 16 KSO8 16 15
KSO3 18 17 KSO6 17 16 EMC1403-2-AIZL-TR_MSOP10
KSO12 19 18 KSO3 18 17
KSO13 20 19 KSO12 R1021 1 KB17@ 2 0_0402_5% KB01 19 18
KSO14 21 20 KSO13 R1022 1 KB17@ 2 0_0402_5% KB02 20 19 Address 1001_101xb
KSO11 22 21 KSO14 R1023 1 KB17@ 2 0_0402_5% KB03 21 20
KSO10 23 22 KSO11 R1024 1 KB17@ 2 0_0402_5% KB04 22 21
V0.3 KSO15 24 23 KSO10 R1025 1 KB17@ 2 0_0402_5% KB05 23 22
KSO16 25 24 KSO15 R1026 1 KB17@ 2 0_0402_5% KB06 24 23
620_0402_5% KSO17 26 25 KSO16 R1027 1 KB17@ 2 0_0402_5% KB07 25 24
R311 1 2 +5VS_CAPLED 27 26 KSO17 R1028 1 KB17@ 2 0_0402_5% KB08 26 25
+5VS 27 26
CAPS_LED# 28 +5VS_CAPLED R1029 1 KB17@ 2 0_0402_5% KB09 27
(31) CAPS_LED# 28 27
R344 1 2 +5VS_NUMLED 29 31 CAPS_LED# R1030 1 KB17@ 2 0_0402_5% KB10 28
+5VS
NUM_LED# 30 29 GND 32 +5VS_NUMLED R1031 1 KB17@ 2 0_0402_5% KB11 29 28 31
Close U20 Close to DDR
(31) NUM_LED# 30 GND 29 GND
620_0402_5% NUM_LED# R1032 1 KB17@ 2 0_0402_5% KB12 30 32 REMOTE1+
ACES_88514-3001 30 GND REMOTE1+ MMST3904-7-F_SOT323-3
1
SP010011A00 ACES_88514-3001 1
1
C480 1 1 C479 SP010011A00 C442 C
@ESD@ @ESD@ 2200P_0402_50V7K @ C441 2 Q12
2 REMOTE1- 100P_0402_50V8J B
2 E
3
0.1U_0402_16V7K 2 2 0.1U_0402_16V7K REMOTE1-
V1.0
REMOTE2+
KB Backlight
1
15" C445 @
Close to FAN
2200P_0402_50V7K
V0.2
KB BackLight Control 2 REMOTE2- move to power board
40mil
REMOTE1,2+/-:
Trace width/space:10/10 mil
KB Backlight Trace length:<8"
17"
V0.2 JKBL2 CONN@
+5VALW +5VS
+5VS_KBL 1
+5VS 2 1
3 2
3
10K_0402_5%
10K_0402_5%
4 +3VS
Q11 4
1
AO3413_SOT23 TouchPad
R337
R315
30mil JKBL1 CONN@ 5
6 GND
3 1 1 GND
S
+5VS_KBL
@ V0.2 2 1 E&T_6916-Q04N-03R C446
2
3 2 SP01000TB00
V0.3A R335 4 3 0.1U_0402_16V7K JTP1 CONN@
G
2
1 2 4
5 6 8
100K_0402_5% 6 GND TP_CLK 5 6 G2 7
GND (31) TP_CLK 4 5 G1
1 TP_DATA
(31) TP_DATA 4
1
C434 C449 E&T_6916-Q04N-03R 1 1 0_0402_5% 3
3
1U_0402_16V6K
0.01U_0402_16V7K
V0.3 SP01000TB00 @EMI@ @EMI@ R313 2 @ 1 PCH_SMB_CLK_TP 2
OUT
(11,12,16) SMB_CLK_S3 2 1 PCH_SMB_DATA_TP 1 2
@ C447 C448 @
(11,12,16) SMB_DATA_S3
2
2 100P_0402_50V8J 100P_0402_50V8J R314 0_0402_5% 1
2 2 2 ACES_51524-0060N-001
IN
2
(31) KBL_W_PWM SP010014M10
GND
@ESD@
Q23 V0.3A D22
3
PSOT24C_SOT23-3
DTC124EKAT146_SC59-3
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/TP/Thermal sensor
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B LA-B111P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 25, 2014 Sheet 32 of 59
A B C D E
Connector: 0.3A / pin
PWR Board CONN.
+3VLP
4 +3VALW Power Board 4
V0.2
2
R317
1
100K_0402_5% R318
100K_0402_5% R371
NOVO_BTN# 10K_0402_5%
1
D23 ON/OFFBTN#
2 NOVO#
NOVO# (31)
3
S
NOVO_BTN# 1
2
G
3 ON/OFF PWR_LED# 2 Q24
ON/OFF (31) (31) PWR_LED#
AO3413_SOT23
D
1
DAN202UT106_SC70-3 D24 @ESD@ PWR_LED
PJSOT24C 3P C/A SOT-23 V0.2 1
@
1
R319 C421
ON/OFFBTN# 2 1 0.1U_0402_16V7K JPWR1 CONN@
2
0_0402_5% 6 8
ON/OFFBTN# 5 6 G2 7
NOVO_BTN# 4 5 G1
REMOTE2+ 3 4
(32) REMOTE2+ 3
1
REMOTE2- 2
(32) REMOTE2- 1 2
JPW1 @
1
0_0805_5%
ACES_51524-0060N-001
SP010014M10
2
1 1
C440 C439
3 QAD on/off test purpose 10P_0402_25V8J 3
10P_0402_25V8J
@ESD@ 2 2
@ESD@
Lid switch
LED-B CONN
1 R320 2
+3VALW
100K_0402_5%
2 V0.2 JLED1 2
LID_SW# 8
LID_SW# (31) +3VLP 8
PWR_LED 7 10
BATT_LOW_LED# 6 7 G2 9
(31) BATT_LOW_LED# 5 6 G1
1 2 BATT_CHG_LED#
(31) BATT_CHG_LED# 5
2
SATA_LED# 4
(13) SATA_LED# TP_LOCK_LED# 3 4
C452 C453
VOUT
VCC
(31) TP_LOCK_LED# 2 3
0.1U_0402_16V7K 10P_0402_50V8J +3VS
2 1 V0.3 1 2
1
GND
ACES_51522-00801-001
CONN@
1
V0.3
U21
SA00004PT00
1 1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_BTN/PWR_B/LED_B/LID
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B LA-B111P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 25, 2014 Sheet 33 of 59
A B C D E
5 4 3 2 1
+5VALW
@
C454 1 2 4.7U_0402_6.3V6M
C455 1 2 0.1U_0402_16V7K
@EMI@
1 R562
1 R565
0_0402_5% R563
R338 2 1 0_0402_5%
L25 EMI@
10K_0402_5%
10K_0402_5%
+USB2_VCCC
1
+USB2_VCCC USB20_P4_L 3 4 USB20_P4_CONN
D25
@
D U22 3 EXT_MIC_SLEEVE D
1 12 USB20_N4_L 2 1 USB20_N4_CONN 1
IN OUT
47U_0805_6.3V6M
V0.2 9 10 USB20_P4_L 2 EXT_MIC_RING2
2
STATUS# DP_IN
0.1U_0402_16V7K
C467
13 11 USB20_N4_L 1 V0.2A V0.3
(17) USB_OC2# FAULT# DM_IN MCF12102G900-T_4P
1
1 2 4 2
(31) AOU_ILIM ILIM_SEL DM_OUT USB20_N4 (17) YSLC05CH_SOT23-3
C468
R561 0_0402_5% 5 3 R336 2 1 0_0402_5%
(31) AOU_EN EN DP_OUT USB20_P4 (17) @ESD@
1 2 6 15 R324 1 2 80.6K_0402_1%
2
R564 0_0402_5% 7 CTL1 ILIM_LO 16 R323 1 2 20K_0402_1% 2
CTL2 ILIM_HI @EMI@
(35) SUSP R301 1 @ 2 0_0402_5% 8 14 @
1 2 CTL3 GND 17
(31) AOU_CTL3 T-PAD
R316 0_0402_5%
V0.2 TPS2544RTER_QFN16_3X3
SA000070N00
Alway on USB Mode CTL1~3,ILIM_SEL
S0 0 1 0 1
Enable USB Board CONN.
S3/S4/S5 0 1 1 1
S0 0 1 0 1
Disable S3 0 1 0 0 JSUB1 CONN@
31 32
+USB2_VCCC 31 32
S4/S5 0 1 0 0
29 30
27 29 30 28 USB20_P4_CONN
C 25 27 28 26 USB20_N4_CONN C
V0.2 23 25 26 24
(14,25,28,31,36) PLT_RST# 23 24
EMC 21 22
(15) CLKREQ_CR# PCIE_PTX_C_DRX_P5 19 21 22 20 CLK_PCIE_CR
(17) PCIE_PTX_C_DRX_P5 19 20 CLK_PCIE_CR (15)
SPDIF-OUT PCIE_PTX_C_DRX_N5 17 18 CLK_PCIE_CR#
(17) PCIE_PTX_C_DRX_N5 17 18 CLK_PCIE_CR# (15)
PCIE_PRX_DTX_P5 15 16
(17) PCIE_PRX_DTX_P5 13 15 16 14
PCIE_PRX_DTX_N5
(17) PCIE_PRX_DTX_N5 13 14
1
HP_OUTL 11 12
@EMI@ (26) HP_OUTL 11 12 +3VS
HP_OUTR 9 10
(26) HP_OUTR EXT_MIC_SLEEVE 7 9 10 8
R347 (26) EXT_MIC_SLEEVE +5VS
22_0402_5% EXT_MIC_RING2 5 7 8 6 PLUG_IN#
(26) EXT_MIC_RING2 5 6 PLUG_IN# (26)
40 mils 3 4 SPDIF-OUT
SPDIF-OUT (26)
2
40 mils 1 3 4 2
1 2
1
@EMI@ (26) MIC2-VREFO R321 1 2 2.2K_0402_5% ACES_50255-03001-001
C476 SP02000RN00
22P_0402_50V8J R322 1 2 2.2K_0402_5%
2
B
H1 @ H2 @ H4 @
Fan1 Control Circuit B
HOLEA HOLEA HOLEA V1.0 FD1 FD2 FD3 FD4
FIDUCAL FIDUCAL FIDUCAL FIDUCAL
GPU @ @ @ @ +5VS
R325
1
0_0603_5% JFAN1 CONN@
1
1 @ 2 +5VS_FAN 1
H_4P2 2 1
H_4P2 H_4P2 (31) EC_TACH1 3 2
(31) EC_FAN_PWM1 3
4
5 4
2 G5
H3 @ H5 @ H6 @ H10 @ H12 @ H13 @ 6
HOLEA HOLEA HOLEA V1.0 HOLEA HOLEA HOLEA C456 G6
CPU MB 1
10U_0603_6.3V6M ACES_50273-0040N-001
SP02000TI00
1
10U
H_4P2 H_4P2 H_4P2 H_2P5 H_2P5 H_3P0
H7 @
HOLEA
H15 @
HOLEA
H16 @
HOLEA
H17 @
HOLEA JDUG1 CONN@
+5VS FAN2 Control Circuit
1 R343
0_0603_5% JFAN2 CONN@
WLAN +3VS
(28,31) EC_TX
2
3
1
2
1 @ 2 +5VS_FAN2 1
2 1
(28,31) EC_RX (31) EC_TACH2
1
4 3 3 2
4 (31) EC_FAN_PWM2 3
5 4
H_3P2 H_2P5 H_2P5 H_3P0 6 G5 5 4
G6 2 G5
6
ACES_50273-0040N-001 C474 G6
A H8 @ H9 @ H20 H21 SP02000TI00 ACES_50273-0040N-001 A
10U_0603_6.3V6M
HOLEA HOLEA HOLEA HOLEA H22 1 SP02000TI00
HOLEA
LAN 10U
1
H_3P3
橢橢橢
CHASSIS1_GND
H_3P3
H_1P5N H_1P5N
for LAN screw hole H_4P0X3P0
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB charge/FAN/Screw holes
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B LA-B111P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 25, 2014 Sheet 34 of 59
5 4 3 2 1
A B C D E
+5VALW to +5VS Transfer
+5VALW
+3VALW +3V_PCH
1 +5VS JP10 JP@ 1
+5VSJ JUMP_43X39
1 2 2 1
10U_0603_6.3V6M C457 @ +5VSJ JP@ JP5 2 1
JUMP_43X118
2 1 2 1
0.1U_0402_16V7K C458 U23 2 1 3 1
1 14
200mil
VIN1 VOUT1 1 1
1
AO3413_SOT23
+5VL
DS3@ C483
2 13
4.7U_0603_6.3V6K
DS3@ C484
VIN1 VOUT1
1U_0402_6.3V6K
1
0.01U_0402_16V7K
4.7U_0603_6.3V6K @
@ C482
10U_0603_6.3V6M
C460
C461
(31,50,51,52,53) SUSP# R326 2 1 3VS_EN 3 12 C459 1 2 220P_0402_50V7K 1 1 Q10 R352
2
0_0402_5% ON1 CT1 2 DS3@ 2 470_0603_5%
2
R327 4 11
2
VBIAS GND
10K_0402_5%
@
2
5 10 C462 1 2 470P_0402_50V7K 2 2 +5VALW
ON2 CT2
1
+3VSJ D
+3VALW 6 9 2 PCH_PWR_EN#
VIN2 VOUT2 120mil R353
@
7 8 DS3@ G
VIN2 VOUT2 1 2 PCH_PWR_EN# Q13 @
S
1
3
0.01U_0402_16V7K
15 2N7002K_SOT23-3
GPAD
10U_0603_6.3V6M
0.1U_0402_16V7K
47K_0402_5%
10U_0603_6.3V6M
1 1 TPS22966DPUR_SON14_2X3 V0.2 1@ 1 V0.2
+3VSJ +3VS
C466
1
1
D
C463
C464
C465
SA00006FD00 JP@ JP9 V0.3
APE8990GN3B JUMP_43X118 2 C481 DS3@
2 2@ 2 2 (31) PCH_PWR_EN 0.1U_0402_16V7K
2 1 G Q21
2 1 2
S
3
2N7002K_SOT23-3
DS3@
2 2
+3VALW to +3VS Transfer
Discharge circuit-1
+3VALW +1.35V +0.675VS
+5VALW +1.5VS +1.05VS
1
1
3 3
1
1
R328 R331
R329 R330 22_0402_5% 100_0402_1% V0.2 R332
100K_0402_5% 68_0402_5% 100_0402_1%
2
@ @ @ @ V0.2
2
@ R333
2
2
0.675VS_CHG
100K_0402_5%
1.35V_CHG
1.5VS_CHG
VCCP_CHG
V0.3A V0.3A @ V0.3A
2
V0.3A V0.3A
V0.3A
(34) SUSP
6
3
1
D Q17B
1
SYSON 2 2N7002KDWH_SOT363-6 D Q18A Q18B
(31,50) SYSON
G SYSON# 2 SUSP 5 SUSP# 2 SUSP 2 2N7002KDWH_SOT363-6 SUSP 5 2N7002KDWH_SOT363-6
R334
S Q17A @ G @ @
3
10K_0402_5%
Q7 2N7002KDWH_SOT363-6 Q8 S
1
4
2
2N7002H_SOT23-3 @ 2N7002H_SOT23-3
@
@ @
1
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B LA-B111P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 25, 2014 Sheet 35 of 59
A B C D E
5 4 3 2 1
U30A +3V3_AON
PEG_CRX_GTX_P[0..15] PEG_PTX_C_DRX_P0 AN12 Part 1 of 7 @
(4) PEG_CRX_GTX_P[0..15] AM12 PEX_RX0 P6 1 2
PEG_PTX_C_DRX_N0 GC6_FB_EN TO PCH XTAL_OUTBUFF
AN14 PEX_RX0_N GPIO0 M3 GC6_FB_EN (14,38)
PEG_PTX_C_DRX_P1 R503 10K_0402_5%
PEG_CRX_GTX_N[0..15] PEG_PTX_C_DRX_N1 AM14 PEX_RX1 GPIO1 L6
(4) PEG_CRX_GTX_N[0..15] PEG_PTX_C_DRX_P2 AP14 PEX_RX1_N GPIO2 P5 PWR_LEVEL_R 1 DIS@ 2
PEG_PTX_C_DRX_N2 AP15 PEX_RX2 GPIO3 P7 DIS@ R502 100K_0402_5%
PEG_PTX_C_DRX_P[0..15] PEG_PTX_C_DRX_P3 AN15 PEX_RX2_N GPIO4 L7 3V3_MAIN_EN PWR_LEVEL_R 2 1
(4) PEG_PTX_C_DRX_P[0..15] PEG_PTX_C_DRX_N3 AM15 PEX_RX3 GPIO5 M7 GPU_EVENT#_R 3V3_MAIN_EN (45,54) PWR_LEVEL (31) XTAL_OUTBUFF 1 DIS@ 2
PEX_RX3_N GPIO6
TO PCH
PEG_PTX_C_DRX_P4 AN17 N8 D31 RB751V-40_SOD323-2 R517 10K_0402_5%
PEG_PTX_C_DRX_N[0..15] PEG_PTX_C_DRX_N4 AM17 PEX_RX4 GPIO7 L3 SYS_PEX_RST_MON#
(4) PEG_PTX_C_DRX_N[0..15] PEX_RX4_N GPIO8
TO PCH THRMTRIP#
PEG_PTX_C_DRX_P5 AP17 M2 VGA_ALERT# TO EC
AP18 PEX_RX5 GPIO9 L1 VGA_ALERT# (31)
PEG_PTX_C_DRX_N5 VRAM_VREF_CTL
D PEG_PTX_C_DRX_P6 AN18 PEX_RX5_N GPIO10 M5 NVVDD_PWM_VID VRAM_VREF_CTL (41,43) D
@
PEG_PTX_C_DRX_N6 AM18 PEX_RX6 GPIO11 N3 PWR_LEVEL_R NVVDD_PWM_VID (54) GPU_EVENT#_R 2 1
TO EC
GPIO
PEG_PTX_C_DRX_P7 AN20 PEX_RX6_N GPIO12 M4 NVVDD_PSI PWR_LEVEL_R (47) GPU_EVENT# (14)
AM20 PEX_RX7 GPIO13 N4 NVVDD_PSI (54) +3V3_AON
PEG_PTX_C_DRX_N7 D34 RB751V-40_SOD323-2
PEG_PTX_C_DRX_P8 AP20 PEX_RX7_N GPIO14 P2 1 DIS@ 2
PEG_PTX_C_DRX_N8 AP21 PEX_RX8 GPIO15 R8 R421 0_0402_5% RP36
PEG_PTX_C_DRX_P9 AN21 PEX_RX8_N GPIO16 M6 3V3_MAIN_EN 1 8
PEG_PTX_C_DRX_N9 AM21 PEX_RX9 GPIO17 R1 VGA_ALERT# 2 7
PEG_PTX_C_DRX_P10 AN23 PEX_RX9_N GPIO18 P3 GPU_OVERT# 3 6
AM23 PEX_RX10 GPIO19 P4 (37,45) GPU_OVERT# 4 5
PEG_PTX_C_DRX_N10 XTAL_SSIN
PEG_PTX_C_DRX_P11 AP23 PEX_RX10_N GPIO20 P1 DGPU_RST_HOLD#
PEG_PTX_C_DRX_N11 AP24 PEX_RX11 GPIO21 +1.05VSG 10K_8P4R_5%
PEG_PTX_C_DRX_P12 AN24 PEX_RX11_N DIS@
PEG_PTX_C_DRX_N12 AM24 PEX_RX12 DIS@ L31
PEX_RX12_N
10U_0603_6.3V6M
PEG_PTX_C_DRX_P13 AN26 +PLLVDD 1 2 RP37
PEX_RX13
0.1U_0402_16V7K
PEG_PTX_C_DRX_N13 AM26 BLM15AX300SN1D 1 SMB_CLK_GPU 1 8
PEX_RX13_N
22U_0603_6.3V6M
C603
PEG_PTX_C_DRX_P14 AP26 1 SMB_DATA_GPU 2 7
PEX_RX14
1
DIS@
DIS@
PEG_PTX_C_DRX_N14 AP27 @ VGA_EDID_DATA 3 6
PEX_RX14_N
C607
C602
PEG_PTX_C_DRX_P15 AN27 AK9 VGA_EDID_CLK 4 5
SE095224K00 PEG_PTX_C_DRX_N15 AM27 PEX_RX15 DACA_RED AL10 2
2
S CER CAP 0.22U 10V K X5R 0402 PEX_RX15_N DACA_GREEN AL9 2
DACA_BLUE I2C 2.2K_8P4R_5%
DIS@
DACs
PEG_CRX_GTX_P0 C601 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P0 AK14
PEG_CRX_GTX_N0 C604 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N0 AJ14 PEX_TX0 AM9 RP38
PEG_CRX_GTX_P1 C606 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P1 AH14 PEX_TX0_N DACA_HSYNC AN9 VGA_CRT_CLK 1 8
PEG_CRX_GTX_N1 1 2 PEG_CRX_C_GTX_N1 AG14 PEX_TX1 DACA_VSYNC VGA_CRT_DATA 2 7
C609 DIS@ 0.22U_0402_10V6K
PEX_TX1_N under GPU 22U 0603 C941,C945
PEG_CRX_GTX_P2 C610 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P2 AK15 for layout limitation HDCP_SDA 3 6
PEG_CRX_GTX_N2 C611 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N2 AJ15 PEX_TX2 AG10 close to AD8 HDCP_SCL 4 5
PEG_CRX_GTX_P3 C612 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P3 AL16 PEX_TX2_N DACA_VDD AP9
PCI EXPRESS
PEG_CRX_GTX_N3 C613 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N3 AK16 PEX_TX3 DACA_VREF AP8 2.2K_8P4R_5%
PEG_CRX_GTX_P4 C614 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P4 AK17 PEX_TX3_N DACA_RSET SW@ @
PEG_CRX_GTX_N4 C615 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N4 AJ17 PEX_TX4 GC6_FB_EN 3
C PEG_CRX_GTX_P5 C616 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P5 AH17 PEX_TX4_N 11.35V_PWR_EN RP39 C
PEX_TX5 1.35V_PWR_EN (45)
2
PEG_CRX_GTX_N5 C617 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N5 AG17 2 GC6_FB_EN 1 8
PEG_CRX_GTX_P6 1 2 PEG_CRX_C_GTX_P6 AK18 PEX_TX5_N (18,45,54) DGPU_PWROK GPU_EVENT#_R 2 7
C618 DIS@ 0.22U_0402_10V6K DIS@
PEG_CRX_GTX_N6 C619 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N6 AJ18 PEX_TX6 D30 R488 DGPU_RST_HOLD# 3 6 V0.2
PEG_CRX_GTX_P7 C620 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P7 AL19 PEX_TX6_N DAN202UT106_SC70-3 100K_0402_5% 4 5
PEG_CRX_GTX_N7 C621 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N7 AK19 PEX_TX7 R4 VGA_CRT_CLK
1
PEG_CRX_GTX_P8 C622 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P8 AK20 PEX_TX7_N I2CA_SCL R5 VGA_CRT_DATA 10K_8P4R_5%
PEG_CRX_GTX_N8 C623 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N8 AJ20 PEX_TX8 I2CA_SDA DIS@
PEG_CRX_GTX_P9 C624 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P9 AH20 PEX_TX8_N R7 HDCP_SCL
PEG_CRX_GTX_N9 C625 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N9 AG20 PEX_TX9 I2CB_SCL R6 HDCP_SDA RP35
PEG_CRX_GTX_P10 C626 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P10 AK21 PEX_TX9_N I2CB_SDA NVVDD_PSI 1 8
PEX_TX10
I2C
PEG_CRX_GTX_N10 C627 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N10 AJ21 R2 VGA_EDID_CLK 2 7
PEX_TX10_N I2CC_SCL (37) JTAG_TRST
PEG_CRX_GTX_P11 C628 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P11 AL22 R3 VGA_EDID_DATA 3 6
PEX_TX11 I2CC_SDA (37) TESTMODE
PEG_CRX_GTX_N11 C629 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N11 AK22 VGA_CLKREQ#_R 4 5
PEG_CRX_GTX_P12 C630 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P12 AK23 PEX_TX11_N T4 SMB_CLK_GPU
PEG_CRX_GTX_N12 C631 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N12 AJ23 PEX_TX12 I2CS_SCL T3 SMB_DATA_GPU 10K_8P4R_5%
PEG_CRX_GTX_P13 C632 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P13 AH23 PEX_TX12_N I2CS_SDA DIS@
PEG_CRX_GTX_N13 C633 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N13 AG23 PEX_TX13
PEG_CRX_GTX_P14 1 2 PEG_CRX_C_GTX_P14 AK24 PEX_TX13_N
C634 DIS@ 0.22U_0402_10V6K
PEX_TX14 Green CLK
PEG_CRX_GTX_N14 C635 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N14 AJ24
PEG_CRX_GTX_P15 C636 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P15 AL25 PEX_TX14_N
PEG_CRX_GTX_N15 C637 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N15 AK25 PEX_TX15 GCLK@
PEX_TX15_N XTALIN 1 2
CLK_27M_VGA_XIN (27)
AD8 +PLLVDD R516 0_0402_5%
AJ11 PLLVDD
NC AE8 L30 +1.05VSG
AL13 SP_PLLVDD BLM15PX181SN1D
(15) CLK_PEG_VGA PEX_REFCLK
AK13 AD7 +GPU_PLLVDD 1 2
(15) CLK_PEG_VGA# PEX_REFCLK_N VID_PLLVDD
22U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
AK12
4.7U_0603_6.3V6K
VGA_CLKREQ#_R DIS@ NOGCLK@ V0.2 V1.0
PEX_CLKREQ_N
CLK
1 1 1 Y5 27MHZ_10PF_7V27000050
1
1 @ 2 PEX_TSTCLK_OUT AJ26 H3 XTALIN DIS@ DIS@ DIS@ DIS@ NOGCLK@
PEX_TSTCLK_OUT# AK26 PEX_TSTCLK_OUT XTAL_IN H2 XTAL_OUT XTALIN 1 3 R423 2 1 XTAL_OUT
Default unstuffed R401 200_0402_1%
PEX_TSTCLK_OUT_N XTAL_OUT 1 3
C640
C642
C643
C644
B B
1 1
2
DGPU_PEX_RST# AJ12 J4 XTAL_OUTBUFF 2 2 2 C638 GND GND C639
AP29 PEX_RST_N XTAL_OUTBUFF H1 XTAL_SSIN NOGCLK@ NOGCLK@ 1K_0402_1%
PEX_TERMP XTAL_SSIN 15P_0402_50V8J 2 4 15P_0402_50V8J V0.3
2 2
2
V0.3A
R402 C640 under GPU V1.0 V1.0
DGPU_PWROK
+3V_PCH 2.49K_0402_1% DIS@
close to ball : AE8,AD7
N15P-GX_BGA908
1
1
R501
DIS@ 10K_0402_5%
V0.3 +3V3_AON
2
+3V3_AON
G
Q33
2
VGA_CLKREQ#_R 3 1 CLK_REQ_VGA#
CLK_REQ_VGA# (15)
S
2 DIS@
2N7002K_SOT23-3 When REFCLK current is below 20mA, don't need C646 2 SW@
1 @ 2 above gate control for CLKREQ_GPU#, and keep 0.1U_0402_25V6K C645
R403 0_0402_5% 0.1U_0402_25V6K
REFCLK free running
5
U40 1
5
V0.2 U39 1
VCC
(14) DGPU_HOLD_RST# 1
VCC
IN1 4 SYS_PEX_RST_MON# 1
2 OUT IN1 4 DGPU_PEX_RST#
(14,25,28,31,34) PLT_RST#
GND
IN2 DGPU_RST_HOLD# 2 OUT DGPU_PEX_RST# (45)
GND
Internal Thermal Sensor IN2
MC74VHC1G08DFT2G SC70 5P
3
+3V3_AON DIS@ MC74VHC1G08DFT2G SC70 5P
3
SW@
A A
5
DIS@
SMB_CLK_GPU 4 3
EC_SMB_CK2 (16,31,32)
Q32B 2N7002KDWH_SOT363-6
Security Classification Compal Secret Data Compal Electronics, Inc.
2
DIS@ Issued Date 2014/02/25 2015/02/25 Title
SMB_DATA_GPU 1 6 Deciphered Date
Q32A 2N7002KDWH_SOT363-6
EC_SMB_DA2 (16,31,32)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX (1/5) PEG & DAC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 36 of 59
5 4 3 2 1
5 4 3 2 1
Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
+3VS_DGPU SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
ROM_SCLK
U30D
ROM_SO +3VS_DGPU RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
Part 4 of 7
AM6
IFPA_TXC +3VS_DGPU
AN6
IFPA_TXC_N 3V3AUX_NC
P8 ROM_SI DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
AP3 AC6
D AN3 IFPA_TXD0 NC AJ28 D
IFPA_TXD0_N NC STRAP0 Keep pull-up to 3V3_AON and pull-down to GND foot print and stuff 50K ohm pull-up
AN5 AJ4
IFPA_TXD1 NC
AM5
IFPA_TXD1_N NC
AJ5 trace width: 16mils STRAP1
AL6 AL11
AK6 IFPA_TXD2 NC C15 differential voltage sensing.
AJ6 IFPA_TXD2_N NC D19 differential signal routing. STRAP2 RESERVED
AH6 IFPA_TXD3 NC D20
NC
IFPA_TXD3_N NC D23 STRAP3
NC D26
AJ9 NC H31 +VGA_CORE STRAP4
AH9 IFPB_TXC NC T8
AP6 IFPB_TXC_N NC V32
AP5 IFPB_TXD4 NC
IFPB_TXD4_N
2
AM7 Pull-up to +3VS
AL7 IFPB_TXD5
IFPB_TXD5_N
R404 SKU Device ID bit5 to bit0 Resistor Values _DGPU Pull-down to Gnd
AN8 DIS@ 100_0402_1%
AM8 IFPB_TXD6
IFPB_TXD6_N 5K 1000 0000
AK8 N15P-GX 0x1392
1
AL8 IFPB_TXD7
IFPB_TXD7_N 10K 1001 0001
L4 VCCSENSE_VGA
VDD_SENSE VCCSENSE_VGA (54)
15K 1010 0010
AK1
AJ1 IFPC_L0
IFPC_L0_N 20K 1011 0011
AJ3 L5 VSSSENSE_VGA
AJ2 IFPC_L1 GND_SENSE VSSSENSE_VGA (54)
IFPC_L1_N 25K 1100 0100
AH3
AH4 IFPC_L2
IFPC_L2_N 30K 1101 0101
AG5 2 DIS@ 1
AG4 IFPC_L3
IFPC_L3_N
R405 100_0402_1% 35K 1110 0110
TEST 45K 1111 0111
AM1 AK11
C AM2 IFPD_L0 TESTMODE TESTMODE (36) C
AM3 IFPD_L0_N AM10 JTAG_TCK
IFPD_L1 JTAG_TCK PAD T51 @
AM4 AM11 JTAG_TDI @
IFPD_L1_N JTAG_TDI PAD T52 +3V3_AON +3VS_DGPU
AL3 AP12 JTAG_TDO MULTI LEVEL STRAPS
IFPD_L2 JTAG_TDO PAD T50 @
AL4 AP11 JTAG_TMS
IFPD_L2_N JTAG_TMS PAD T53 @
AK4 AN11
AK5 IFPD_L3 JTAG_TRST_N JTAG_TRST (36)
IFPD_L3_N
1
10K_0402_1%
49.9K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
45.3K_0402_1%
4.99K_0402_1%
LVDS/TMDS
10K_0402_1%
14.7K_0402_1%
@ @ @ @ @ @ @
R406
R407
R408
R409
R410
AD2 DIS@
IFPE_L0
R412
AD3
IFPE_L0_N
R439
R413
AD1
SERIAL
2
AC1 IFPE_L1
AC2 IFPE_L1_N H6 STRAP0 ROM_SI
AC3 IFPE_L2 ROM_CS_N H4 ROM_SCLK STRAP1 STRAP3 ROM_SO
AC4 IFPE_L2_N ROM_SCLK H5 ROM_SI STRAP2 STRAP4 ROM_SCLK
AC5 IFPE_L3 ROM_SI H7 ROM_SO
IFPE_L3_N ROM_SO
1
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
45.3K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
R414
R415
R416
R417
R418
AE3 @ @ @ @ @ @ DIS@ DIS@
AE4 IFPF_L0
AF4 IFPF_L0_N
IFPF_L1
R411
R420
R419
AF5
GENERAL
2
AD4 IFPF_L1_N DIS@
AD5 IFPF_L2 L2 1 2
AG1 IFPF_L2_N BUFRST_N R422 10K_0402_5%
AF1 IFPF_L3 M1 GPU_OVERT#
IFPF_L3_N OVERT GPU_OVERT# (36,45)
J1 MULTI_STRAP_REF0_GND 1 DIS@ 2
MULTI_STRAP_REF0_GND R424 40.2K_0402_1% For X76 (N15P-GX)
AG3
AG2 IFPC_AUX_I2CW_SCL ZZZ3 X76L01@ ZZZ4 X76L03@
B IFPC_AUX_I2CW_SDA_N J2 STRAP0 B
STRAP0 GPU FB Memory DDR5 ROM_SI
J7 STRAP1
AK3 STRAP1 J6 STRAP2
AK2 IFPD_AUX_I2CX_SCL STRAP2 J5 STRAP3
IFPD_AUX_I2CX_SDA_N STRAP3 Samsung 2G K4G20325FD-FC03
J3 STRAP4 X76L02@ PD 5K
STRAP4
10K_0402_1% 15K_0402_1%
AB3 128Mx16
AB4 IFPE_AUX_I2CY_SCL X7654438L01 X7654438L03
IFPE_AUX_I2CY_SDA_N K3
THERMDP Hynix 2G H5GC2H24BFR-T2C
K4 X76L01@ PD 10K
AF3 THERMDN ZZZ5 X76L02@ ZZZ6 X76L04@
AF2 IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N N15P-GX
Hynix 4G H5GC4H24MFR-T2C
X76L03@ PD 15K
256Mx16 5K_0402_1% 20K_0402_1%
N15P-GX_BGA908
Samsung 4G K4G41325FC-HC03 X7654438L02 X7654438L04
X76L04@ PD 20K
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX (2/5) TMDS/LVDS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 37 of 59
5 4 3 2 1
5 4 3 2 1
MDA[15..0] MDC[15..0]
(41) MDA[15..0] (43) MDC[15..0]
MDA[31..16] MDC[31..16]
(41) MDA[31..16] (43) MDC[31..16]
MDA[47..32] MDC[47..32]
(42) MDA[47..32] (44) MDC[47..32]
MDA[63..48] MDC[63..48]
(42) MDA[63..48] (44) MDC[63..48]
U30B U30C
CMDA[31..0] (41,42) CMDC[31..0] (42,43,44)
Part 2 of 7 Part 3 of 7
D MDA0 L28 U30 CMDA0 MDC0 G9 D13 CMDC0 D
MDA1 M29 FBA_D0 FBA_CMD0 T31 CMDA1 MDC1 E9 FBB_D0 FBB_CMD0 E14 CMDC1
MDA2 L29 FBA_D1 FBA_CMD1 U29 CMDA2 MDC2 G8 FBB_D1 FBB_CMD1 F14 CMDC2
MDA3 M28 FBA_D2 FBA_CMD2 R34 CMDA3 MDC3 F9 FBB_D2 FBB_CMD2 A12 CMDC3
MDA4 N31 FBA_D3 FBA_CMD3 R33 CMDA4 MDC4 F11 FBB_D3 FBB_CMD3 B12 CMDC4
MDA5 P29 FBA_D4 FBA_CMD4 U32 CMDA5 MDC5 G11 FBB_D4 FBB_CMD4 C14 CMDC5
MDA6 R29 FBA_D5 FBA_CMD5 U33 CMDA6 MDC6 F12 FBB_D5 FBB_CMD5 B14 CMDC6
MDA7 P28 FBA_D6 FBA_CMD6 U28 CMDA7 MDC7 G12 FBB_D6 FBB_CMD6 G15 CMDC7
MDA8 J28 FBA_D7 FBA_CMD7 V28 CMDA8 MDC8 G6 FBB_D7 FBB_CMD7 F15 CMDC8
MDA9 H29 FBA_D8 FBA_CMD8 V29 CMDA9 MDC9 F5 FBB_D8 FBB_CMD8 E15 CMDC9
MDA10 J29 FBA_D9 FBA_CMD9 V30 CMDA10 MDC10 E6 FBB_D9 FBB_CMD9 D15 CMDC10
MDA11 H28 FBA_D10 FBA_CMD10 U34 CMDA11 MDC11 F6 FBB_D10 FBB_CMD10 A14 CMDC11
MDA12 G29 FBA_D11 FBA_CMD11 U31 CMDA12 MDC12 F4 FBB_D11 FBB_CMD11 D14 CMDC12
MDA13 E31 FBA_D12 FBA_CMD12 V34 CMDA13 MDC13 G4 FBB_D12 FBB_CMD12 A15 CMDC13
MDA14 E32 FBA_D13 FBA_CMD13 V33 CMDA14 MDC14 E2 FBB_D13 FBB_CMD13 B15 CMDC14
MDA15 F30 FBA_D14 FBA_CMD14 Y32 CMDA15 MDC15 F3 FBB_D14 FBB_CMD14 C17 CMDC15
MDA16 C34 FBA_D15 FBA_CMD15 AA31 CMDA16 MDC16 C2 FBB_D15 FBB_CMD15 D18 CMDC16
MDA17 D32 FBA_D16 FBA_CMD16 AA29 CMDA17 MDC17 D4 FBB_D16 FBB_CMD16 E18 CMDC17
MDA18 B33 FBA_D17 FBA_CMD17 AA28 CMDA18 MDC18 D3 FBB_D17 FBB_CMD17 F18 CMDC18
MDA19 C33 FBA_D18 FBA_CMD18 AC34 CMDA19 MDC19 C1 FBB_D18 FBB_CMD18 A20 CMDC19
MDA20 F33 FBA_D19 FBA_CMD19 AC33 CMDA20 MDC20 B3 FBB_D19 FBB_CMD19 B20 CMDC20
MDA21 F32 FBA_D20 FBA_CMD20 AA32 CMDA21 MDC21 C4 FBB_D20 FBB_CMD20 C18 CMDC21
MDA22 H33 FBA_D21 FBA_CMD21 AA33 CMDA22 MDC22 B5 FBB_D21 FBB_CMD21 B18 CMDC22
MDA23 H32 FBA_D22 FBA_CMD22 Y28 CMDA23 MDC23 C5 FBB_D22 FBB_CMD22 G18 CMDC23
MDA24 P34 FBA_D23 FBA_CMD23 Y29 CMDA24 MDC24 A11 FBB_D23 FBB_CMD23 G17 CMDC24
MDA25 P32 FBA_D24 FBA_CMD24 W31 CMDA25 MDC25 C11 FBB_D24 FBB_CMD24 F17 CMDC25
MDA26 P31 FBA_D25 FBA_CMD25 Y30 CMDA26 MDC26 D11 FBB_D25 FBB_CMD25 D16 CMDC26
FBA_D26 FBA_CMD26 FBB_D26 FBB_CMD26
MEMORY INTERFACE B
MDA27 P33 AA34 CMDA27 MDC27 B11 A18 CMDC27
MDA28 L31 FBA_D27 FBA_CMD27 Y31 CMDA28 MDC28 D8 FBB_D27 FBB_CMD27 D17 CMDC28
MDA29 L34 FBA_D28 FBA_CMD28 Y34 CMDA29 MDC29 A8 FBB_D28 FBB_CMD28 A17 CMDC29
MDA30 L32 FBA_D29 FBA_CMD29 Y33 CMDA30 MDC30 C8 FBB_D29 FBB_CMD29 B17 CMDC30
MDA31 L33 FBA_D30 FBA_CMD30 V31 CMDA31 MDC31 B8 FBB_D30 FBB_CMD30 E17 CMDC31
C MDA32 AG28 FBA_D31 FBA_CMD31 R28 MDC32 F24 FBB_D31 FBB_CMD31 G14 C
MDA33 AF29 FBA_D32 FBA_CMD32 AC28 R427 +1.35VSG MDC33 G23 FBB_D32 FBB_CMD32 G20 R428 +1.35VSG
MEMORY INTERFACE
MDA34 AG29 FBA_D33 FBA_CMD33 R32 FBA_DEBUG0 2 @ 1 60.4_0402_1% MDC34 E24 FBB_D33 FBB_CMD33 C12 FBC_DEBUG0 2 @ 1 60.4_0402_1%
MDA35 AF28 FBA_D34 FBA_CMD34 AC32 FBA_DEBUG1 2 @ 1 MDC35 G24 FBB_D34 FBB_CMD34 C20 FBC_DEBUG1 2 @ 1
MDA36 AD30 FBA_D35 FBA_CMD35 R429 60.4_0402_1% MDC36 D21 FBB_D35 FBB_CMD35 R430 60.4_0402_1%
MDA37 AD29 FBA_D36 MDC37 E21 FBB_D36
MDA38 AC29 FBA_D37 MDC38 G21 FBB_D37
MDA39 AD28 FBA_D38 MDC39 F21 FBB_D38
MDA40 AJ29 FBA_D39 MDC40 G27 FBB_D39
MDA41 AK29 FBA_D40 MDC41 D27 FBB_D40
MDA42 AJ30 FBA_D41 MDC42 G26 FBB_D41
MDA43 AK28 FBA_D42 MDC43 E27 FBB_D42
MDA44 AM29 FBA_D43 MDC44 E29 FBB_D43
MDA45 AM31 FBA_D44 R30 MDC45 F29 FBB_D44 D12
FBA_D45 FBA_CLK0 CLKA0 (41) FBB_D45 FBB_CLK0 CLKC0 (43)
MDA46 AN29 R31 MDC46 E30 E12
FBA_D46 FBA_CLK0_N CLKA0# (41) FBB_D46 FBB_CLK0_N CLKC0# (43)
MDA47 AM30 AB31 MDC47 D30 E20
FBA_D47 FBA_CLK1 CLKA1 (42) FBB_D47 FBB_CLK1 CLKC1 (44)
MDA48 AN31 AC31 MDC48 A32 F20
FBA_D48 FBA_CLK1_N CLKA1# (42) FBB_D48 FBB_CLK1_N CLKC1# (44)
MDA49 AN32 MDC49 C31
A
MDA50 AP30 FBA_D49 MDC50 C32 FBB_D49
MDA51 AP32 FBA_D50 MDC51 B32 FBB_D50
MDA52 AM33 FBA_D51 K31 MDC52 D29 FBB_D51 F8
FBA_D52 FBA_WCK01 FBA_WCK01 (41) FBB_D52 FBB_WCK01 FBB_WCK01 (43)
MDA53 AL31 L30 MDC53 A29 E8
FBA_D53 FBA_WCK01_N FBA_WCK01# (41) FBB_D53 FBB_WCK01_N FBB_WCK01# (43)
MDA54 AK33 H34 MDC54 C29 A5
FBA_D54 FBA_WCK23 FBA_WCK23 (41) FBB_D54 FBB_WCK23 FBB_WCK23 (43)
MDA55 AK32 J34 MDC55 B29 A6
FBA_D55 FBA_WCK23_N FBA_WCK23# (41) FBB_D55 FBB_WCK23_N FBB_WCK23# (43)
MDA56 AD34 AG30 MDC56 B21 D24
FBA_D56 FBA_WCK45 FBA_WCK45 (42) FBB_D56 FBB_WCK45 FBB_WCK45 (44)
MDA57 AD32 AG31 MDC57 C23 D25
FBA_D57 FBA_WCK45_N FBA_WCK45# (42) FBB_D57 FBB_WCK45_N FBB_WCK45# (44)
MDA58 AC30 AJ34 MDC58 A21 B27
FBA_D58 FBA_WCK67 FBA_WCK67 (42) FBB_D58 FBB_WCK67 FBB_WCK67 (44)
MDA59 AD33 AK34 MDC59 C21 C27
FBA_D59 FBA_WCK67_N FBA_WCK67# (42) FBB_D59 FBB_WCK67_N FBB_WCK67# (44)
MDA60 AF31 MDC60 B24
MDA61 AG34 FBA_D60 MDC61 C24 FBB_D60
MDA62 AG32 FBA_D61 MDC62 B26 FBB_D61
MDA63 AG33 FBA_D62 J30 MDC63 C26 FBB_D62 D6 +FB_PLLAVDD +1.05VSG
B FBA_D63 NC J31 FBB_D63 NC D7 L32 DIS@ B
(41) DQMA[3..0] P30 NC J32 (43) DQMC[3..0] E11 NC C6 1 2
DQMA0 DQMC0 +FB_PLLAVDD
FBA_DQM0 NC FBB_DQM0 NC
22U_0805_6.3V6M
DQMA1 F31 J33 DQMC1 E3 B6 BLM15AX300SN1D
FBA_DQM1 NC FBB_DQM1 NC
DIS@ C647
DQMA2 F34 AH31 DQMC2 A3 F26 1
DQMA3 M32 FBA_DQM2 NC AJ31 DQMC3 C9 FBB_DQM2 NC E26
(42) DQMA[7..4] FBA_DQM3 NC (44) DQMC[7..4] FBB_DQM3 NC
Or use same as L10 PN: SM01000FE00
DQMA4 AD31 AJ32 DQMC4 F23 A26
DQMA5 AL29 FBA_DQM4 NC AJ33 DQMC5 F27 FBB_DQM4 NC A27
DQMA6 AM32 FBA_DQM5 NC DQMC6 C30 FBB_DQM5 NC 2
DQMA7 AF34 FBA_DQM6 DQMC7 A24 FBB_DQM6
FBA_DQM7 FBB_DQM7
(41) DQSA[3..0] DQSA0 M31 E1 GC6_FB_EN_R (43) DQSC[3..0] DQSC0 D10
DQSA1 G31 FBA_DQS_WP0 FB_CLAMP DQSC1 D5 FBB_DQS_WP0
L15= 30ohm
DQSA2 E33 FBA_DQS_WP1 DQSC2 C3 FBB_DQS_WP1
FBA_DQS_WP2 Under GPU FBB_DQS_WP2
DQSA3 M33 DQSC3 B9
(42) DQSA[7..4]
DQSA4 AE31 FBA_DQS_WP3 K27 close to ball : K27 (44) DQSC[7..4]
DQSC4 E23 FBB_DQS_WP3 H17 +FB_PLLAVDD
DQSA5 AK30 FBA_DQS_WP4 FB_DLL_AVDD C648 DIS@ DQSC5 E28 FBB_DQS_WP4 FBB_PLL_AVDD
DQSA6 AN33 FBA_DQS_WP5 1 2 DQSC6 B30 FBB_DQS_WP5
FBA_DQS_WP6 FBB_DQS_WP6
0.1U_0402_16V7K
DQSA7 AF33 0.1U_0402_16V7K DQSC7 A23
FBA_DQS_WP7 U27 +FB_PLLAVDD FBB_DQS_WP7
FBA_PLL_AVDD 1
C650
M30 D9
H30 FBA_DQS_RN0 1 2 E4 FBB_DQS_RN0 DIS@
E34 FBA_DQS_RN1 C649 0.1U_0402_16V7K B2 FBB_DQS_RN1
M34 FBA_DQS_RN2 H26 DIS@ A9 FBB_DQS_RN2 2
AF30 FBA_DQS_RN3 FB_VREF D22 FBB_DQS_RN3
AK31 FBA_DQS_RN4 D28 FBB_DQS_RN4
FBA_DQS_RN5 Under GPU FBB_DQS_RN5
AM34 A30 Under GPU
AF32 FBA_DQS_RN6 close to ball : U27 B23 FBB_DQS_RN6
FBA_DQS_RN7 FBB_DQS_RN7 close to ball : H17
N15P-GX_BGA908 N15P-GX_BGA908
A GC6_FB_EN_R 1 @ 2 A
GC6_FB_EN (14,36)
R426 0_0402_5%
2
DIS@ R518
Near GPU 10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
1
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX (3/5) TMDS/LVDS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 38 of 59
5 4 3 2 1
5 4 3 2 1
Under GPU Near GPU +1.05VSG
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1U_0402_6.3V6K
4.7U_0603_6.3V6K
DIS@ C652
DIS@ C653
DIS@ C670
DIS@ C671
DIS@ C654
DIS@ C655
D D
1U_0402_6.3V6K
1 1 1 1 1 1
DIS@ C651
U30E 1
+1.35VSG Under GPU Part 5 of 7
2 2 2 2 2 2
9000mA 2
AA27 AG19
FBVDDQ_0 PEX_IOVDD_0
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
AA30 AG21
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
FBVDDQ_1 PEX_IOVDD_1
DIS@ C656
DIS@ C657
DIS@ C658
DIS@ C672
DIS@ C659
DIS@ C660
1 1 1 1 1 1 AB27 AG22
AB33 FBVDDQ_2 PEX_IOVDD_2 AG24
AC27 FBVDDQ_3 PEX_IOVDD_3 AH21
AD27 FBVDDQ_4 PEX_IOVDD_4 AH25
2 2 2 2 2 2 AE27 FBVDDQ_5 PEX_IOVDD_5 Under GPU Near GPU +1.05VSG
AF27 FBVDDQ_6
AG27 FBVDDQ_7 AG13
FBVDDQ_8 PEX_IOVDDQ_0
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
B13 AG15
4.7U_0603_6.3V6K
FBVDDQ_9 PEX_IOVDDQ_1
DIS@ C673
DIS@ C661
DIS@ C662
DIS@ C663
DIS@ C664
DIS@ C674
DIS@ C665
Under GPU B19 AG16 1 1 1 1 1 1 1
E13 FBVDDQ_11 PEX_IOVDDQ_2 AG18
E19 FBVDDQ_12 PEX_IOVDDQ_3 AG25
FBVDDQ_14 PEX_IOVDDQ_4
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
H10 AH15
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
FBVDDQ_15 PEX_IOVDDQ_5 2 2 2 2 2 2 2
DIS@ C666
DIS@ C675
DIS@ C667
DIS@ C676
DIS@ C668
DIS@ C669
1 1 1 1 1 1 H11 AH18
H12 FBVDDQ_16 PEX_IOVDDQ_6 AH26
H13 FBVDDQ_17 PEX_IOVDDQ_7 AH27
H14 FBVDDQ_18 PEX_IOVDDQ_8 AJ27
2 2 2 2 2 2 H18 FBVDDQ_19 PEX_IOVDDQ_9 AK27
H19 FBVDDQ_22 PEX_IOVDDQ_10 AL27
H20 FBVDDQ_23 PEX_IOVDDQ_11 AM28
POWER
H21 FBVDDQ_24 PEX_IOVDDQ_12 AN28
Near GPU H22 FBVDDQ_25 PEX_IOVDDQ_13
V0.3 V0.3 H23 FBVDDQ_26 +3V3_AON
H24 FBVDDQ_27
Near GPU
330U 2V D2 LESR9M EEFSX H1.9
FBVDDQ_28
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
H8 AH12
FBVDDQ_29 PEX_PLL_HVDD
DIS@ C677
DIS@ C678
DIS@ C679
DIS@ C680
DIS@ C795
DIS@ C766
DIS@ C764
1U_0402_6.3V6K
H9
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1 1 1 1 1 1 FBVDDQ_30
C
DIS@ C790
DIS@ C681
DIS@ C682
DIS@ C683
L27 @ 1 2 C
1 FBVDDQ_31 1 1 1
SGA20331E10
M27 C684 0.1U_0402_16V7K
+ N27 FBVDDQ_32 AG12
2 2 2 2 2 2 2 P27 FBVDDQ_33 PEX_SVDD_3V3
R27 FBVDDQ_34 @ 1 2 2 2 2 @
2 T27 FBVDDQ_35 C685 0.1U_0402_16V7K RP40
V0.3 T30 FBVDDQ_36 AG26 IFPEF_PLLVDD 1 8
N14P_GB4-128 T33 FBVDDQ_37 PEX_PLLVDD IFPA_IOVDD 2 7
DG-6246_V04 Y27 FBVDDQ_38 IFPC_IOVDD 3 6
FBVDDQ_43 +1.05VSG IFPC_PLLVDD 4 5
J8 Under GPU Near GPU
3V3_AON K8 2.2K_8P4R_5%
3V3_AON
0.1U_0402_16V7K
1U_0402_6.3V6K
L8
4.7U_0603_6.3V6K
3V3_MAIN
DIS@ C686
DIS@ C687
DIS@ C688
B16 M8 1 1 1 @
E16 FBVDDQ_AON 3V3_MAIN RP41
H15 FBVDDQ_AON IFPD_IOVDD 1 8
H16 FBVDDQ_AON IFPD_PLLVDD 2 7
V27 FBVDDQ_AON AH8 IFPAB_PLLVDD 2 2 2 IFPAB_PLLVDD3 6
W27 FBVDDQ_AON IFPAB_PLLVDD AJ8 IFPB_IOVDD 4 5
W30 FBVDDQ_AON IFPAB_RSET
W33 FBVDDQ_AON AG8 IFPA_IOVDD 10K_8P4R_5%
FBVDDQ_AON IFPA_IOVDD AG9 IFPB_IOVDD
IFPB_IOVDD @
RP42
AF7 IFPC_PLLVDD Under GPU (one per pin) Near GPU +3V3_AON IFPE_IOVDD 1 8
+1.35VSG IFPC_PLLVDD AF8 IFPF_IOVDD 2 7
IFPC_RSET
0.1U_0402_16V7K
3 6
0.1U_0402_16V7K
1U_0402_6.3V6K
2 1 F1 AF6 4 5
4.7U_0603_6.3V6K
@ FB_VDDQ_SENSE IFPC_IOVDD
FB_VDDQ_SENSE IFPC_IOVDD
DIS@ C694
DIS@ C705
DIS@ C695
DIS@ C689
R431 10_0402_5% 1 1 1 1
10K_8P4R_5%
2 DIS@ 1 FB_GND_SENSE F2 AG7 IFPD_PLLVDD
+1.35VSG R432 10_0402_5% FB_GND_SENSE IFPD_PLLVDD AN2
B NC 2 2 2 2 B
2 DIS@ 1 FB_CAL_PD_VDDQ J27 AG6 IFPD_IOVDD
R433 40.2_0402_1% FB_CAL_PD_VDDQ IFPD_IOVDD
2 DIS@ 1 FB_CAL_PU_GND H27 AB8 IFPEF_PLLVDD
R434 40.2_0402_1% FB_CAL_PU_GND IFPEF_PLVDD AD6
IFPEF_RSET +3VS_DGPU
Under GPU (one per pin) Near GPU
2 DIS@ 1 FB_CAL_TERM_GND H25 AC7 IFPE_IOVDD
R435 60.4_0402_1% FB_CAL_TERM_GND IFPE_IOVDD AC8 IFPF_IOVDD
IFPF_IOVDD
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
DIS@ C690
DIS@ C691
DIS@ C692
DIS@ C693
Place near balls 1 1 1 1
N15P-GX_BGA908 2 2 2 2
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX (4/5) POWER
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 39 of 59
5 4 3 2 1
5 4 3 2 1
U30F
Part 6 of 7
A2 D2
AA17 GND_0 GND_100 D31
+VGA_CORE U30G +VGA_CORE AA18 GND_1 GND_101 D33
AA20 GND_2 GND_102 E10
AA22 GND_3 GND_103 E22
Part 7 of 7 V17 AB12 GND_4 GND_104 E25
D AA12 VDD_56 V18 AB14 GND_5 GND_105 E5 D
AA14 VDD_0 VDD_57 V20 AB16 GND_6 GND_106 E7
AA16 VDD_1 VDD_58 V22 AB19 GND_7 GND_107 F28
AA19 VDD_2 VDD_59 W12 AB2 GND_8 GND_108 F7
AA21 VDD_3 VDD_60 W14 AB21 GND_9 GND_109 G10
AA23 VDD_4 VDD_61 W16 A33 GND_10 GND_110 G13
AB13 VDD_5 VDD_62 W19 AB23 GND_11 GND_111 G16
AB15 VDD_6 VDD_63 W21 AB28 GND_12 GND_112 G19
AB17 VDD_7 VDD_64 W23 AB30 GND_13 GND_113 G2
AB18 VDD_8 VDD_65 Y13 AB32 GND_14 GND_114 G22
AB20 VDD_9 VDD_66 Y15 AB5 GND_15 GND_115 G25
AB22 VDD_10 VDD_67 Y17 AB7 GND_16 GND_116 G28
AC12 VDD_11 VDD_68 Y18 AC13 GND_17 GND_117 G3
AC14 VDD_12 VDD_69 Y20 AC15 GND_18 GND_118 G30
AC16 VDD_13 VDD_70 Y22 AC17 GND_19 GND_119 G32
AC19 VDD_14 VDD_71 AC18 GND_20 GND_120 G33
AC21 VDD_15 AA13 GND_21 GND_121 G5
AC23 VDD_16 U1 AC20 GND_22 GND_122 G7
M12 VDD_17 XVDD_1 U2 AC22 GND_23 GND_123 K2
M14 VDD_18 XVDD_2 U3 AE2 GND_24 GND_124 K28
M16 VDD_19 XVDD_3 U4 AE28 GND_25 GND_125 K30
POWER
M19 VDD_20 XVDD_4 U5 AE30 GND_26 GND_126 K32
M21 VDD_21 XVDD_5 U6 AE32 GND_27 GND_127 K33
M23 VDD_22 XVDD_6 U7 AE33 GND_28 GND_128 K5
N13 VDD_23 XVDD_7 U8 AE5 GND_29 GND_129 K7
N15 VDD_24 XVDD_8 AE7 GND_30 GND_130 M13
N17 VDD_25 AH10 GND_31 GND_131 M15
N18 VDD_26 V1 AA15 GND_32 GND_132 M17
N20 VDD_27 XVDD_9 V2 AH13 GND_33 GND_133 M18
N22 VDD_28 XVDD_10 V3 AH16 GND_34 GND_134 M20
P12 VDD_29 XVDD_11 V4 AH19 GND_35 GND_135 M22
P14 VDD_30 XVDD_12 V5 AH2 GND_36 GND_136 N12
C P16 VDD_31 XVDD_13 V6 AH22 GND_37 GND_137 N14 C
P19 VDD_32 XVDD_14 V7 AH24 GND_38 GND_138 N16
P21 VDD_33 XVDD_15 V8 AH28 GND_39 GND_139 N19
P23 VDD_34 XVDD_16 AH29 GND_40 GND_140 N2
R13 VDD_35 AH30 GND_41 GND_141 N21
R15 VDD_36 W2 AH32 GND_42 GND_142 N23
R17 VDD_37 XVDD_17 W3 AH33 GND_43 GND_143 N28
GND
R18 VDD_38 XVDD_18 W4 AH5 GND_44 GND_144 N30
R20 VDD_39 XVDD_19 W5 AH7 GND_45 GND_145 N32
R22 VDD_40 XVDD_20 W7 AJ7 GND_46 GND_146 N33
T12 VDD_41 XVDD_21 W8 AK10 GND_47 GND_147 N5
T14 VDD_42 XVDD_22 AK7 GND_48 GND_148 N7
T16 VDD_43 AL12 GND_49 GND_149 P13
T19 VDD_44 Y1 AL14 GND_50 GND_150 P15
T21 VDD_45 NC Y2 AL15 GND_51 GND_151 P17
T23 VDD_46 NC Y3 AL17 GND_52 GND_152 P18
U13 VDD_47 NC Y4 AL18 GND_53 GND_153 P20
U15 VDD_48 XVDD_23 Y5 AL2 GND_54 GND_154 P22
U17 VDD_49 XVDD_24 Y6 AL20 GND_55 GND_155 R12
U18 VDD_50 XVDD_25 Y7 AL21 GND_56 GND_156 R14
U20 VDD_51 XVDD_26 Y8 AL23 GND_57 GND_157 R16
U22 VDD_52 XVDD_27 AL24 GND_58 GND_158 R19
V13 VDD_53 AL26 GND_59 GND_159 R21
V15 VDD_54 AA1 AL28 GND_60 GND_160 R23
VDD_55 NC AA2 AL30 GND_61 GND_161 T13
NC AA3 AL32 GND_62 GND_162 T15
NC AA4 AL33 GND_63 GND_163 T17
NC AA5 AL5 GND_64 GND_164 T18
NC AA6 AM13 GND_65 GND_165 T2
NC AA7 AM16 GND_66 GND_166 T20
NC AA8 AM19 GND_67 GND_167 T22
NC AM22 GND_68 GND_168 AG11
B AM25 GND_69 GND_169 T28 B
AN1 GND_70 GND_170 T32
AN10 GND_71 GND_171 T5
N15P-GX_BGA908 AN13 GND_72 GND_172 T7
AN16 GND_73 GND_173 U12
AN19 GND_74 GND_174 U14
AN22 GND_75 GND_175 U16
AN25 GND_76 GND_176 U19
AN30 GND_77 GND_177 U21
AN34 GND_78 GND_178 U23
AN4 GND_79 GND_179 V12
AN7 GND_80 GND_180 V14
AP2 GND_81 GND_181 V16
AP33 GND_82 GND_182 V19
B1 GND_83 GND_183 V21
B10 GND_84 GND_184 V23
B22 GND_85 GND_185 W13
B25 GND_86 GND_186 W15
B28 GND_87 GND_187 W17
B31 GND_88 GND_188 W18
B34 GND_89 GND_189 W20
B4 GND_90 GND_190 W22
B7 GND_91 GND_191 W28
C10 GND_92 GND_192 Y12
C13 GND_93 GND_193 Y14
C19 GND_94 GND_194 Y16
C22 GND_95 GND_195 Y19
C25 GND_96 GND_196 Y21
C28 GND_97 GND_197 Y23
C7 GND_98 GND_198 AH11
GND_99 GND_199 C16
GND_OPT W32
A GND_OPT A
N15P-GX_BGA908
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX (5/5) POWER/ GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 40 of 59
5 4 3 2 1
5 4 3 2 1
MIRROR
NORMAL U32
Memory Partition A - Lower 16 bits U31
MF=0 MF=1 MF=1 MF=0
MF=0 MF=1 MF=1 MF=0
A4 MDA24
A4 MDA0 DQSA3 C2 DQ24 DQ0 A2 MDA25
VRAM DDR5 chips DQSA0
DQSA2
C2
C13
R13
EDC0
EDC1
EDC3
EDC2
DQ24
DQ25
DQ26
DQ0
DQ1
DQ2
A2
B4
B2
MDA1
MDA2
MDA3
DQSA1
C13
R13
R2
EDC0
EDC1
EDC2
EDC3
EDC2
EDC1
DQ25
DQ26
DQ27
DQ1
DQ2
DQ3
B4
B2
E4
MDA26
MDA27
MDA28
Mode H
Address 0..31
Mode H
Address 32..63
R2 EDC2 EDC1 DQ27 DQ3 E4 MDA4 EDC3 EDC0 DQ28 DQ4 E2 MDA29 CMD0 CS* CMD16 CS*
128Mx16 GDDR5 *8==>2GB EDC3 EDC0 DQ28
DQ29
DQ4
DQ5
E2
F4
MDA5
MDA6 DQMA3 D2
DQ29
DQ30
DQ5
DQ6
F4
F2
MDA30
MDA31
DQ30 DQ6 DBI0# DBI3# DQ31 DQ7 CMD1 A3_BA3 CMD17 A3_BA3
DQMA0 D2 F2 MDA7 D13 A11
D
256Mx16 GDDR5 *8==>4GB DQMA2
D13
P13
DBI0#
DBI1#
DBI3#
DBI2#
DQ31
DQ16
DQ7
DQ8
A11
A13
DQMA1 P13
P2
DBI1#
DBI2#
DBI2#
DBI1#
DQ16
DQ17
DQ8
DQ9
A13
B11
CMD2 A2_BA0 CMD18 A2_BA0 D
P2 DBI2# DBI1# DQ17 DQ9 B11 DBI3# DBI0# DQ18 DQ10 B13
DBI3# DBI0# DQ18 DQ10 DQ19 DQ11 CMD3 A4_BA2 CMD19 A4_BA2
B13 CLKA0 J12 E11
CLKA0 J12 DQ19 DQ11 E11 CLKA0# J11 CK DQ20 DQ12 E13
CK DQ20 DQ12 CK# DQ21 DQ13 CMD4 A5_BA1 CMD20 A5_BA1
CLKA0# J11 E13 CMDA14 J3 F11
CMDA14 J3 CK# DQ21 DQ13 F11 CKE# DQ22 DQ14 F13
CKE# DQ22 DQ14 DQ23 DQ15 CMD5 WE* CMD21 WE*
F13 CMDA9 J5 U11 MDA8
CMDA9 J5 DQ23 DQ15 U11 MDA16 A12/A13 DQ8 DQ16 U13 MDA9
A12/A13 DQ8 DQ16 DQ9 DQ17 CMD6 A7_A8 CMD22 A7_A8
U13 MDA17 CMDA10 K4 T11 MDA10
CMDA6 K4 DQ9 DQ17 T11 MDA18 CMDA11 K5 A8/A7 A10/A0 DQ10 DQ18 T13 MDA11
A8/A7 A10/A0 DQ10 DQ18 A11/A6 A9/A1 DQ11 DQ19 CMD7 A6_A11 CMD23 A6_A11
CMDA7 K5 T13 MDA19 CMDA1 K10 N11 MDA12
DQMA[7..0] CMDA4 K10 A11/A6 A9/A1 DQ11 DQ19 N11 MDA20 CMDA2 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 MDA13
(38,42) DQMA[7..0] BA1/A5 BA3/A3 DQ12 DQ20 BA2/A4 BA0/A2 DQ13 DQ21 CMD8 ABI* CMD24 ABI*
CMDA3 K11 N13 MDA21 M11 MDA14
CMDA[31..0] BA2/A4 BA0/A2 DQ13 DQ21 M11 MDA22 CMDA4 H10 DQ14 DQ22 M13 MDA15
(38,42) CMDA[31..0] DQ14 DQ22 BA3/A3 BA1/A5 DQ15 DQ23 CMD9 A12_RFU CMD25 A12_RFU
CMDA1 H10 M13 MDA23 CMDA3 H11 U4
DQSA[7..0] CMDA2 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 +1.35VSG CMDA7 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2
(38,42) DQSA[7..0] BA0/A2 BA2/A4 DQ0 DQ24 A9/A1 A11/A6 DQ1 DQ25 CMD10 A0_A10 CMD26 A0_A10
CMDA11 H5 U2 CMDA6 H4 T4
MDA[63..0] CMDA10 H4 A9/A1 A11/A6 DQ1 DQ25 T4 A10/A0 A8/A7 DQ2 DQ26 T2
(38,42) MDA[63..0] A10/A0 A8/A7 DQ2 DQ26 DQ3 DQ27 CMD11 A1_A9 CMD27 A1_A9
2
T2 N4
DQ3 DQ27 N4 A5 DQ4 DQ28 N2
DQ4 DQ28
R438
NC DQ5 DQ29 CMD12 RAS* CMD28 RAS*
A5 N2 1K_0402_1% DIS@ U5 M4
U5 NC DQ5 DQ29 M4 NC DQ6 DQ30 M2
NC DQ6 DQ30 DQ7 DQ31 CMD13 RST* CMD29 RST*
M2
1
DQ7 DQ31 J1
MF
+1.35VSG CMD14 CK1* CMD30 CK1*
R436 DIS@ 1 2 1K_0402_1% MF0 J1 +1.35VSG SEN0 J10
DIS@ 1 2 1K_0402_1% SEN0 J10 MF 1 DIS@ 2 ZQ1 J13 SEN B1
R437
SEN ZQ VDDQ CMD15 CAS* CMD31 CAS*
R440 DIS@ 1 2 121_0402_1% ZQ0 J13 B1 R441 121_0402_1% D1
ZQ VDDQ D1 VDDQ F1
VDDQ VDDQ CMD32 NO USED
F1 CMDA8 J4 M1
CMDA8 J4 VDDQ M1 CMDA15 G3 ABI# VDDQ P1
ABI# VDDQ RAS# CAS# VDDQ CMD33 NO USED
CMDA12 G3 P1 CMDA5 G12 T1
CMDA0 G12 RAS# CAS# VDDQ T1 CMDA12 L3 CS# WE# VDDQ G2
CS# WE# VDDQ CAS# RAS# VDDQ CMD34 Debug0
C +1.35VSG CMDA15 L3 G2 CMDA0 L12 L2 C
CMDA5 L12 CAS# RAS# VDDQ L2 WE# CS# VDDQ B3
WE# CS# VDDQ VDDQ CMD35 Debug1
B3 D3
VDDQ VDDQ
1
D3 F3
R492 VDDQ F3 FBA_WCK23#D5 VDDQ H3
549_0402_1% D5 VDDQ H3 FBA_WCK23 D4 WCK01# WCK23# VDDQ K3
(38) FBA_WCK01# WCK01# WCK23# VDDQ WCK01 WCK23 VDDQ
DIS@ D4 K3 M3
(38) FBA_WCK01 WCK01 WCK23 VDDQ VDDQ
M3 FBA_WCK01# P5 P3
2
P5 VDDQ P3 FBA_WCK01 P4 WCK23# WCK01# VDDQ T3
(38) FBA_WCK23# WCK23# WCK01# VDDQ WCK23 WCK01 VDDQ
P4 T3 E5
FBA_VREFC (42) (38) FBA_WCK23 WCK23 WCK01 VDDQ VDDQ
E5 N5
VDDQ N5 A10 VDDQ E10
VDDQ VREFD VDDQ
1
A10 E10 U10 N10
R498 R494 DIS@ U10 VREFD VDDQ N10 FBA_VREFC J14 VREFD VDDQ B12
1.33K_0402_1% 2 1 FBA_VREFC J14 VREFD VDDQ B12 VREFC VDDQ D12
931_0402_1% VREFC VDDQ VDDQ
DIS@ C761 820P_0402_25V8K D12 F12
DIS@ VDDQ VDDQ
F12 H12
2
VDDQ H12 CMDA13 J2 VDDQ K12
CMDA13 J2 VDDQ K12 RESET# VDDQ M12
RESET# VDDQ VDDQ
6
M12 P12
Q37A VDDQ P12 VDDQ T12
VDDQ T12 VDDQ G13
2 DIS@ VDDQ G13 VDDQ L13
(36,43) VRAM_VREF_CTL VDDQ VDDQ
L13 B14
2N7002KDWH_SOT363-6 VDDQ B14 VDDQ D14
1
VDDQ VDDQ
100K_0402_5%
D14 +1.35VSG F14
VDDQ VDDQ
1
+1.35VSG F14 M14
VDDQ VDDQ
R500
DIS@ M14 G1 P14
G1 VDDQ P14 L1 VDD VDDQ T14
L1 VDD VDDQ T14 G4 VDD VDDQ
G4 VDD VDDQ L4 VDD
2
L4 VDD C5 VDD A1
B C5 VDD A1 R5 VDD VSSQ C1 B
R5 VDD VSSQ C1 C10 VDD VSSQ E1
C10 VDD VSSQ E1 R10 VDD VSSQ N1
R10 VDD VSSQ N1 D11 VDD VSSQ R1 +1.35VSG
D11 VDD VSSQ R1 G11 VDD VSSQ U1
CLKA0 G11 VDD VSSQ U1 L11 VDD VSSQ H2
(38) CLKA0 VDD VSSQ VDD VSSQ
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
L11 H2 P11 K2
VDD VSSQ VDD VSSQ
1
10U_0805_25V6K
10U_0805_25V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
P11 K2 G14 A3
VDD VSSQ VDD VSSQ
DIS@ C696
DIS@ C697
@ C698
DIS@ C699
DIS@ C700
@ C701
DIS@ C702
@ C703
@ C704
DIS@ G14 A3 L14 C3 1 1 1 1 1 1 1
VDD VSSQ VDD VSSQ
1
R487 L14 C3 E3
80.6_0402_1% VDD VSSQ E3 VSSQ N3
VSSQ N3 VSSQ R3
2
2
CLKA0# VSSQ R3 H1 VSSQ U3 2 2 2 2 2 2 2
(38) CLKA0# H1 VSSQ U3 K1 VSS VSSQ C4
K1 VSS VSSQ C4 B5 VSS VSSQ R4
B5 VSS VSSQ R4 G5 VSS VSSQ F5
G5 VSS VSSQ F5 L5 VSS VSSQ M5 V0.2 V0.2 V0.2 V0.2
L5 VSS VSSQ M5 T5 VSS VSSQ F10
T5 VSS VSSQ F10 B10 VSS VSSQ M10
B10 VSS VSSQ M10 D10 VSS VSSQ C11 +1.35VSG
D10 VSS VSSQ C11 G10 VSS VSSQ R11
G10 VSS VSSQ R11 L10 VSS VSSQ A12
L10 VSS VSSQ A12 P10 VSS VSSQ C12
VSS VSSQ VSS VSSQ
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
P10 C12 T10 E12
VSS VSSQ VSS VSSQ
C708
DIS@ C709
DIS@ C710
DIS@ C711
@ C712
DIS@ C713
DIS@ C714
T10 E12 H14 N12 1 1 1 1 1 1 2
H14 VSS VSSQ N12 K14 VSS VSSQ R12
K14 VSS VSSQ R12 VSS170-BALL VSSQ U12
VSS170-BALL VSSQ VSSQ
@
U12 H13
VSSQ H13 SGRAM GDDR5 VSSQ K13 2 2 2 2 2 2 1
SGRAM GDDR5 VSSQ K13 VSSQ A14
VSSQ A14 VSSQ C14 V0.2
VSSQ C14 VSSQ E14
A VSSQ E14 VSSQ N14 V0.2 A
VSSQ N14 VSSQ R14
VSSQ R14 VSSQ U14
VSSQ U14 VSSQ
VSSQ @ K4G41325FC-HC04_FBGA170~D
@ K4G41325FC-HC04_FBGA170~D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX GDDR5 1/4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B111P
Date: Tuesday, February 25, 2014 Sheet 41 of 59
5 4 3 2 1
5 4 3 2 1
NORMAL MIRROR
U33 U34
Memory Partition A - Upper 16 bits MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0
A4 MDA32 A4 MDA56
DQSA4 C2 DQ24 DQ0 A2 MDA33 DQSA7 C2 DQ24 DQ0 A2 MDA57
C13 EDC0 EDC3 DQ25 DQ1 B4 MDA34 C13 EDC0 EDC3 DQ25 DQ1 B4 MDA58
EDC1 EDC2 DQ26 DQ2 EDC1 EDC2 DQ26 DQ2
Mode H Mode H
DQSA6 R13 B2 MDA35 DQSA5 R13 B2 MDA59 Address 0..31 Address 32..63
VRAM DDR5 chips R2 EDC2
EDC3
EDC1
EDC0
DQ27
DQ28
DQ29
DQ3
DQ4
DQ5
E4
E2
F4
MDA36
MDA37
MDA38
R2 EDC2
EDC3
EDC1
EDC0
DQ27
DQ28
DQ29
DQ3
DQ4
DQ5
E4
E2
F4
MDA60
MDA61
MDA62
CMD0 CS* CMD16 CS*
DQMA4 D2 DQ30 DQ6 F2 MDA39 DQMA7 D2 DQ30 DQ6 F2 MDA63 CMD1 A3_BA3 CMD17 A3_BA3
D
128Mx16 GDDR5 *8==>2GB DQMA6
D13
P13
DBI0#
DBI1#
DBI3#
DBI2#
DQ31
DQ16
DQ7
DQ8
A11
A13 DQMA5
D13
P13
DBI0#
DBI1#
DBI3#
DBI2#
DQ31
DQ16
DQ7
DQ8
A11
A13 D
DBI2# DBI1# DQ17 DQ9 DBI2# DBI1# DQ17 DQ9 CMD2 A2_BA0 CMD18 A2_BA0
P2 B11 P2 B11
256Mx16 GDDR5 *8==>4GB CLKA1 J12
DBI3# DBI0# DQ18
DQ19
DQ10
DQ11
B13
E11 CLKA1 J12
DBI3# DBI0# DQ18
DQ19
DQ10
DQ11
B13
E11
CMD3 A4_BA2 CMD19 A4_BA2
CLKA1# J11 CK DQ20 DQ12 E13 CLKA1# J11 CK DQ20 DQ12 E13
CK# DQ21 DQ13 CK# DQ21 DQ13 CMD4 A5_BA1 CMD20 A5_BA1
CMDA30 J3 F11 CMDA30 J3 F11
CKE# DQ22 DQ14 F13 CKE# DQ22 DQ14 F13
DQ23 DQ15 DQ23 DQ15 CMD5 WE* CMD21 WE*
CMDA25 J5 U11 MDA48 CMDA25 J5 U11 MDA40
DQSA[7..0] A12/A13 DQ8 DQ16 U13 MDA49 A12/A13 DQ8 DQ16 U13 MDA41
(38,41) DQSA[7..0] DQ9 DQ17 DQ9 DQ17 CMD6 A7_A8 CMD22 A7_A8
CMDA22 K4 T11 MDA50 CMDA26 K4 T11 MDA42
DQMA[7..0] CMDA23 K5 A8/A7 A10/A0 DQ10 DQ18 T13 MDA51 CMDA27 K5 A8/A7 A10/A0 DQ10 DQ18 T13 MDA43
(38,41) DQMA[7..0] A11/A6 A9/A1 DQ11 DQ19 A11/A6 A9/A1 DQ11 DQ19 CMD7 A6_A11 CMD23 A6_A11
CMDA20 K10 N11 MDA52 CMDA17 K10 N11 MDA44
MDA[63..0] CMDA19 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 MDA53 CMDA18 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 MDA45
(38,41) MDA[63..0] BA2/A4 BA0/A2 DQ13 DQ21 BA2/A4 BA0/A2 DQ13 DQ21 CMD8 ABI* CMD24 ABI*
M11 MDA54 M11 MDA46
CMDA[31..0] CMDA17 H10 DQ14 DQ22 M13 MDA55 CMDA20 H10 DQ14 DQ22 M13 MDA47
(38,41) CMDA[31..0] BA3/A3 BA1/A5 DQ15 DQ23 BA3/A3 BA1/A5 DQ15 DQ23 CMD9 A12_RFU CMD25 A12_RFU
CMDA18 H11 U4 CMDA19 H11 U4
CMDA27 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 +1.35VSG CMDA23 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2
A9/A1 A11/A6 DQ1 DQ25 A9/A1 A11/A6 DQ1 DQ25 CMD10 A0_A10 CMD26 A0_A10
CMDA26 H4 T4 CMDA22 H4 T4
A10/A0 A8/A7 DQ2 DQ26 T2 A10/A0 A8/A7 DQ2 DQ26 T2
DQ3 DQ27 DQ3 DQ27 CMD11 A1_A9 CMD27 A1_A9
2
N4 N4
A5 DQ4 DQ28 N2 A5 DQ4 DQ28 N2
NC DQ5 DQ29
R447
NC DQ5 DQ29 CMD12 RAS* CMD28 RAS*
U5 M4 DIS@ 1K_0402_1% U5 M4
NC DQ6 DQ30 M2 NC DQ6 DQ30 M2
DQ7 DQ31 DQ7 DQ31 CMD13 RST* CMD29 RST*
1
R446 DIS@ 1 2 1K_0402_1% MF1 J1 +1.35VSG J1 +1.35VSG CMD14 CK1* CMD30 CK1*
R449 DIS@ 1 2 1K_0402_1% SEN1 J10 MF SEN1 J10 MF
DIS@ 1 2 121_0402_1% ZQ2 J13 SEN B1 1 R451 2 ZQ3 J13 SEN B1
R450
ZQ VDDQ ZQ VDDQ CMD15 CAS* CMD31 CAS*
D1 121_0402_1% D1
VDDQ F1 VDDQ F1
VDDQ
DIS@
VDDQ CMD32 NO USED
CMDA24 J4 M1 CMDA24 J4 M1
CMDA28 G3 ABI# VDDQ P1 CMDA31 G3 ABI# VDDQ P1
RAS# CAS# VDDQ RAS# CAS# VDDQ CMD33 NO USED
CMDA16 G12 T1 CMDA21 G12 T1
C CMDA31 L3 CS# WE# VDDQ G2 CMDA28 L3 CS# WE# VDDQ G2 C
CAS# RAS# VDDQ CAS# RAS# VDDQ CMD34 Debug0
CMDA21 L12 L2 CMDA16 L12 L2
WE# CS# VDDQ B3 WE# CS# VDDQ B3
VDDQ VDDQ CMD35 Debug1
D3 D3
VDDQ F3 VDDQ F3
D5 VDDQ H3 FBA_WCK67#D5 VDDQ H3
(38) FBA_WCK45# WCK01# WCK23# VDDQ WCK01# WCK23# VDDQ
+1.35VSG D4 K3 FBA_WCK67 D4 K3
(38) FBA_WCK45 WCK01 WCK23 VDDQ WCK01 WCK23 VDDQ
M3 M3
R508 1 2 DIS@ 10K_0402_5% P5 VDDQ P3 FBA_WCK45# P5 VDDQ P3
(38,41,42) CMDA14 (38) FBA_WCK67# WCK23# WCK01# VDDQ WCK23# WCK01# VDDQ
R512 1 2 DIS@ 10K_0402_5% P4 T3 FBA_WCK45 P4 T3
(38,42) CMDA30 (38) FBA_WCK67 WCK23 WCK01 VDDQ WCK23 WCK01 VDDQ
R509 1 2 DIS@ 10K_0402_5% E5 E5
(38,43) CMDC14 VDDQ VDDQ
R513 1 2 DIS@ 10K_0402_5% N5 N5
(38,44) CMDC30 VDDQ VDDQ
A10 E10 A10 E10
U10 VREFD VDDQ N10 DIS@ U10 VREFD VDDQ N10
FBA_VREFC J14 VREFD VDDQ B12 2 1 FBA_VREFC J14 VREFD VDDQ B12
(41) FBA_VREFC VREFC VDDQ VREFC VDDQ
(38,41,42) CMDA13 R510 1 2 DIS@ 10K_0402_5% D12 C765 820P_0402_25V8K D12
R514 1 2 DIS@ 10K_0402_5% VDDQ F12 VDDQ F12
(38,42) CMDA29 VDDQ VDDQ
(38,43) CMDC13 R515 1 2 DIS@ 10K_0402_5% H12 H12
R511 1 2 DIS@ 10K_0402_5% CMDA29 J2 VDDQ K12 CMDA29 J2 VDDQ K12
(38,44) CMDC29 RESET# VDDQ RESET# VDDQ
M12 M12
VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
VDDQ G13 VDDQ G13
VDDQ L13 VDDQ L13
CLKA1 VDDQ B14 VDDQ B14
(38) CLKA1 VDDQ D14 VDDQ D14
VDDQ VDDQ
1
+1.35VSG F14 +1.35VSG F14
DIS@ VDDQ M14 VDDQ M14
R455 G1 VDDQ P14 G1 VDDQ P14
80.6_0402_1% L1 VDD VDDQ T14 L1 VDD VDDQ T14
G4 VDD VDDQ G4 VDD VDDQ
2
CLKA1# L4 VDD L4 VDD
B (38) CLKA1# C5 VDD A1 C5 VDD A1 B
R5 VDD VSSQ C1 R5 VDD VSSQ C1
C10 VDD VSSQ E1 C10 VDD VSSQ E1
R10 VDD VSSQ N1 R10 VDD VSSQ N1
D11 VDD VSSQ R1 D11 VDD VSSQ R1
G11 VDD VSSQ U1 G11 VDD VSSQ U1
L11 VDD VSSQ H2 L11 VDD VSSQ H2 +1.35VSG
P11 VDD VSSQ K2 P11 VDD VSSQ K2
G14 VDD VSSQ A3 G14 VDD VSSQ A3
VDD VSSQ VDD VSSQ
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
L14 C3 L14 C3
VDD VSSQ VDD VSSQ
10U_0805_25V6K
10U_0805_25V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
E3 E3
VSSQ VSSQ
DIS@ C726
@ C727
@ C707
DIS@ C706
DIS@ C724
DIS@ C720
DIS@ C715
DIS@ C728
DIS@ C718
N3 N3 1 1 1 1 1 1 1
VSSQ VSSQ
1
R3 R3
H1 VSSQ U3 H1 VSSQ U3
K1 VSS VSSQ C4 K1 VSS VSSQ C4
2
B5 VSS VSSQ R4 B5 VSS VSSQ R4 2 2 2 2 2 2 2
G5 VSS VSSQ F5 G5 VSS VSSQ F5
L5 VSS VSSQ M5 L5 VSS VSSQ M5
T5 VSS VSSQ F10 T5 VSS VSSQ F10
B10 VSS VSSQ M10 B10 VSS VSSQ M10 V0.2 V0.2
D10 VSS VSSQ C11 D10 VSS VSSQ C11
G10 VSS VSSQ R11 G10 VSS VSSQ R11
L10 VSS VSSQ A12 L10 VSS VSSQ A12 +1.35VSG
P10 VSS VSSQ C12 P10 VSS VSSQ C12
T10 VSS VSSQ E12 T10 VSS VSSQ E12
VSS VSSQ VSS VSSQ
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
H14 N12 H14 N12
K14 VSS VSSQ R12 K14 VSS VSSQ R12
VSS170-BALL VSSQ VSS170-BALL VSSQ
@ C716
DIS@ C725
DIS@ C719
DIS@ C722
@ C717
DIS@ C723
DIS@ C721
U12 U12 1 1 1 1 1 1 2
VSSQ H13 VSSQ H13
SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
VSSQ A14 VSSQ A14
VSSQ C14 VSSQ C14 2 2 2 2 2 2 1
A VSSQ E14 VSSQ E14 A
VSSQ N14 VSSQ N14 V0.2
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14 V0.2
VSSQ VSSQ
@ K4G41325FC-HC04_FBGA170~D
@ K4G41325FC-HC04_FBGA170~D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX GDDR5 2/4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B111P
Date: Tuesday, February 25, 2014 Sheet 42 of 59
5 4 3 2 1
5 4 3 2 1
MIRROR
Memory Partition B - Lower 16 bits U36
NORMAL U35
MF=0 MF=1 MF=1 MF=0
MF=0 MF=1 MF=1 MF=0 A4 MDC24
DQSC3 C2 DQ24 DQ0 A2 MDC25
VRAM DDR5 chips DQSC0 C2
C13 EDC0 EDC3
DQ24
DQ25
DQ0
DQ1
A4
A2
B4
MDC0
MDC1
MDC2
DQSC1
C13
R13
R2
EDC0
EDC1
EDC2
EDC3
EDC2
EDC1
DQ25
DQ26
DQ27
DQ1
DQ2
DQ3
B4
B2
E4
MDC26
MDC27
MDC28
Mode H
Address 0..31
Mode H
Address 32..63
DQSC2 R13 EDC1 EDC2 DQ26 DQ2 B2 MDC3 EDC3 EDC0 DQ28 DQ4 E2 MDC29 CMD0 CS* CMD16 CS*
128Mx16 GDDR5 *8==>2GB R2 EDC2
EDC3
EDC1
EDC0
DQ27
DQ28
DQ3
DQ4
E4
E2
MDC4
MDC5 DQMC3 D2
DQ29
DQ30
DQ5
DQ6
F4
F2
MDC30
MDC31
DQ29 DQ5 DBI0# DBI3# DQ31 DQ7 CMD1 A3_BA3 CMD17 A3_BA3
F4 MDC6 D13 A11
D 256Mx16 GDDR5 *8==>4GB DQMC0 D2
D13 DBI0# DBI3#
DQ30
DQ31
DQ6
DQ7
F2
A11
MDC7 DQMC1 P13
P2
DBI1#
DBI2#
DBI2#
DBI1#
DQ16
DQ17
DQ8
DQ9
A13
B11
CMD2 A2_BA0 CMD18 A2_BA0 D
DQMC2 P13 DBI1# DBI2# DQ16 DQ8 A13 DBI3# DBI0# DQ18 DQ10 B13
DBI2# DBI1# DQ17 DQ9 DQ19 DQ11 CMD3 A4_BA2 CMD19 A4_BA2
DQMC[7..0] P2 B11 CLKC0 J12 E11
(38,44) DQMC[7..0] DBI3# DBI0# DQ18 DQ10 B13 CLKC0# J11 CK DQ20 DQ12 E13
DQ19 DQ11 CK# DQ21 DQ13 CMD4 A5_BA1 CMD20 A5_BA1
CMDC[31..0] CLKC0 J12 E11 CMDC14 J3 F11
(38,42,44) CMDC[31..0] CLKC0# J11 CK DQ20 DQ12 E13 CKE# DQ22 DQ14 F13
CK# DQ21 DQ13 DQ23 DQ15 CMD5 WE* CMD21 WE*
DQSC[7..0] CMDC14 J3 F11 CMDC9 J5 U11 MDC8
(38,44) DQSC[7..0] CKE# DQ22 DQ14 F13 A12/A13 DQ8 DQ16 U13 MDC9
DQ23 DQ15 DQ9 DQ17 CMD6 A7_A8 CMD22 A7_A8
MDC[63..0] CMDC9 J5 U11 MDC16 CMDC10 K4 T11 MDC10
(38,44) MDC[63..0] A12/A13 DQ8 DQ16 U13 MDC17 CMDC11 K5 A8/A7 A10/A0 DQ10 DQ18 T13 MDC11
DQ9 DQ17 A11/A6 A9/A1 DQ11 DQ19 CMD7 A6_A11 CMD23 A6_A11
CMDC6 K4 T11 MDC18 CMDC1 K10 N11 MDC12
CMDC7 K5 A8/A7 A10/A0 DQ10 DQ18 T13 MDC19 CMDC2 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 MDC13
A11/A6 A9/A1 DQ11 DQ19 BA2/A4 BA0/A2 DQ13 DQ21 CMD8 ABI* CMD24 ABI*
CMDC4 K10 N11 MDC20 M11 MDC14
CMDC3 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 MDC21 CMDC4 H10 DQ14 DQ22 M13 MDC15
BA2/A4 BA0/A2 DQ13 DQ21 BA3/A3 BA1/A5 DQ15 DQ23 CMD9 A12_RFU CMD25 A12_RFU
M11 MDC22 CMDC3 H11 U4
CMDC1 H10 DQ14 DQ22 M13 MDC23 +1.35VSG CMDC7 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2
BA3/A3 BA1/A5 DQ15 DQ23 A9/A1 A11/A6 DQ1 DQ25 CMD10 A0_A10 CMD26 A0_A10
CMDC2 H11 U4 CMDC6 H4 T4
CMDC11 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 A10/A0 A8/A7 DQ2 DQ26 T2
A9/A1 A11/A6 DQ1 DQ25 DQ3 DQ27 CMD11 A1_A9 CMD27 A1_A9
2
CMDC10 H4 T4 N4
A10/A0 A8/A7 DQ2 DQ26 T2 A5 DQ4 DQ28 N2
DQ3 DQ27
R458
NC DQ5 DQ29 CMD12 RAS* CMD28 RAS*
N4 1K_0402_1% DIS@ U5 M4
A5 DQ4 DQ28 N2 NC DQ6 DQ30 M2
NC DQ5 DQ29 DQ7 DQ31 CMD13 RST* CMD29 RST*
U5 M4
1
NC DQ6 DQ30 M2 J1
DQ7 DQ31 MF
+1.35VSG CMD14 CK1* CMD30 CK1*
SEN2 J10
DIS@ 1 2 1K_0402_1% MF2 J1 ZQ5 J13 SEN B1
R456
MF
+1.35VSG
ZQ VDDQ CMD15 CAS* CMD31 CAS*
R457 DIS@ 1 2 1K_0402_1% SEN2 J10 D1
SEN VDDQ
2
R462 DIS@ 1 2 121_0402_1% ZQ4 J13 B1 F1 CMD32 NO USED
ZQ VDDQ D1 R460 CMDC8 J4 VDDQ M1
VDDQ F1 CMDC15 G3 ABI# VDDQ P1
VDDQ
DIS@ 121_0402_1% RAS# CAS# VDDQ CMD33 NO USED
CMDC8 J4 M1 CMDC5 G12 T1
C CMDC12 G3 ABI# VDDQ P1 CMDC12 L3 CS# WE# VDDQ G2 C
CMD34 Debug0
1
CMDC0 G12 RAS# CAS# VDDQ T1 CMDC0 L12 CAS# RAS# VDDQ L2
CMDC15 L3 CS# WE# VDDQ G2 WE# CS# VDDQ B3
CAS# RAS# VDDQ VDDQ CMD35 Debug1
CMDC5 L12 L2 D3
+1.35VSG WE# CS# VDDQ B3 VDDQ F3
VDDQ D3 FBB_WCK23#D5 VDDQ H3
VDDQ F3 FBB_WCK23 D4 WCK01# WCK23# VDDQ K3
VDDQ WCK01 WCK23 VDDQ
1
D5 H3 M3
(38) FBB_WCK01# WCK01# WCK23# VDDQ VDDQ
R493 D4 K3 FBB_WCK01# P5 P3
(38) FBB_WCK01 WCK01 WCK23 VDDQ WCK23# WCK01# VDDQ
549_0402_1% M3 FBB_WCK01 P4 T3
DIS@ P5 VDDQ P3 WCK23 WCK01 VDDQ E5
(38) FBB_WCK23# WCK23# WCK01# VDDQ VDDQ
P4 T3 N5
(38) FBB_WCK23
2
WCK23 WCK01 VDDQ E5 A10 VDDQ E10
VDDQ N5 U10 VREFD VDDQ N10
FBB_VREFC (44) VDDQ VREFD VDDQ
A10 E10 FBB_VREFC J14 B12
C762 U10 VREFD VDDQ N10 VREFC VDDQ D12
VREFD VDDQ VDDQ
1
2 1 FBB_VREFC J14 B12 F12
R499 R495 820P_0402_25V8K VREFC VDDQ D12 VDDQ H12
1.33K_0402_1% DIS@ VDDQ F12 CMDC13 J2 VDDQ K12
931_0402_1% VDDQ RESET# VDDQ
DIS@ H12 M12
DIS@ VDDQ VDDQ
CMDC13 J2 K12 P12
2
RESET# VDDQ M12 VDDQ T12
Q37B VDDQ P12 VDDQ G13
VDDQ VDDQ
3
2N7002KDWH_SOT363-6 T12 L13
VDDQ G13 VDDQ B14
VDDQ L13 VDDQ D14
5 DIS@ VDDQ B14 +1.35VSG VDDQ F14
(36,41) VRAM_VREF_CTL VDDQ VDDQ
D14 M14
+1.35VSG VDDQ F14 G1 VDDQ P14 +1.35VSG
4
VDDQ M14 L1 VDD VDDQ T14
G1 VDDQ P14 G4 VDD VDDQ
VDD VDDQ VDD
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
L1 T14 L4
VDD VDDQ VDD
10U_0805_25V6K
10U_0805_25V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
B G4 C5 A1 B
VDD VDD VSSQ
DIS@ C742
DIS@ C743
DIS@ C730
DIS@ C729
DIS@ C740
DIS@ C736
DIS@ C731
@ C744
DIS@ C734
L4 R5 C1 1 1 1 1 1 1 1
VDD VDD VSSQ
1
C5 A1 C10 E1
R5 VDD VSSQ C1 R10 VDD VSSQ N1
C10 VDD VSSQ E1 D11 VDD VSSQ R1
2
R10 VDD VSSQ N1 G11 VDD VSSQ U1 2 2 2 2 2 2 2
D11 VDD VSSQ R1 L11 VDD VSSQ H2
G11 VDD VSSQ U1 P11 VDD VSSQ K2
L11 VDD VSSQ H2 G14 VDD VSSQ A3
CLKC0 P11 VDD VSSQ K2 L14 VDD VSSQ C3 V0.2
(38) CLKC0 G14 VDD VSSQ A3 VDD VSSQ E3
VDD VSSQ VSSQ
1
L14 C3 N3
DIS@ VDD VSSQ E3 VSSQ R3 +1.35VSG
R465 VSSQ N3 H1 VSSQ U3
80.6_0402_1% VSSQ R3 K1 VSS VSSQ C4
VSSQ VSS VSSQ
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
H1 U3 B5 R4
2
CLKC0# K1 VSS VSSQ C4 G5 VSS VSSQ F5
(38) CLKC0# VSS VSSQ VSS VSSQ
@ C732
DIS@ C741
DIS@ C735
@ C738
@ C733
DIS@ C739
DIS@ C737
B5 R4 L5 M5 1 1 1 1 1 1 2
G5 VSS VSSQ F5 T5 VSS VSSQ F10
L5 VSS VSSQ M5 B10 VSS VSSQ M10
T5 VSS VSSQ F10 D10 VSS VSSQ C11
B10 VSS VSSQ M10 G10 VSS VSSQ R11 2 2 2 2 2 2 1
D10 VSS VSSQ C11 L10 VSS VSSQ A12
G10 VSS VSSQ R11 P10 VSS VSSQ C12 V0.2
L10 VSS VSSQ A12 T10 VSS VSSQ E12
P10 VSS VSSQ C12 H14 VSS VSSQ N12 V0.2 V0.2
T10 VSS VSSQ E12 K14 VSS VSSQ R12
H14 VSS VSSQ N12 VSS170-BALL VSSQ U12
K14 VSS VSSQ R12 VSSQ H13
VSS170-BALL VSSQ U12 SGRAM GDDR5 VSSQ K13
VSSQ H13 VSSQ A14
SGRAM GDDR5 VSSQ K13 VSSQ C14
A VSSQ A14 VSSQ E14 A
VSSQ C14 VSSQ N14
VSSQ E14 VSSQ R14
VSSQ N14 VSSQ U14
VSSQ R14 VSSQ
VSSQ U14 @ K4G41325FC-HC04_FBGA170~D
VSSQ
@ K4G41325FC-HC04_FBGA170~D Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX GDDR5 3/4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B111P
Date: Tuesday, February 25, 2014 Sheet 43 of 59
5 4 3 2 1
5 4 3 2 1
MIRROR
Memory Partition B - Upper 16 bits U38
NORMAL U37
MF=0 MF=1 MF=1 MF=0
MF=0 MF=1 MF=1 MF=0 A4 MDC56
DQSC7 C2 DQ24 DQ0 A2 MDC57
A4 MDC32 C13 EDC0 EDC3 DQ25 DQ1 B4 MDC58 Mode H Mode H
VRAM DDR5 chips DQSC4
DQSC6
C2
C13
R13
EDC0
EDC1
EDC3
EDC2
DQ24
DQ25
DQ26
DQ0
DQ1
DQ2
A2
B4
B2
MDC33
MDC34
MDC35
DQSC5 R13
R2
EDC1
EDC2
EDC3
EDC2
EDC1
EDC0
DQ26
DQ27
DQ28
DQ2
DQ3
DQ4
B2
E4
E2
MDC59
MDC60
MDC61
Address
CMD0
0..31
CS*
Address
CMD16
32..63
CS*
R2 EDC2 EDC1 DQ27 DQ3 E4 MDC36 DQ29 DQ5 F4 MDC62
128Mx16 GDDR5 *8==>2GB EDC3 EDC0 DQ28
DQ29
DQ4
DQ5
E2
F4
MDC37
MDC38
DQMC7 D2
D13 DBI0# DBI3#
DQ30
DQ31
DQ6
DQ7
F2
A11
MDC63 CMD1 A3_BA3 CMD17 A3_BA3
D DQMC4 D2 DQ30 DQ6 F2 MDC39 DQMC5 P13 DBI1# DBI2# DQ16 DQ8 A13 D
CMD2 A2_BA0 CMD18 A2_BA0
256Mx16 GDDR5 *8==>4GB DQMC6
D13
P13
DBI0#
DBI1#
DBI3#
DBI2#
DQ31
DQ16
DQ7
DQ8
A11
A13
P2 DBI2#
DBI3#
DBI1#
DBI0#
DQ17
DQ18
DQ9
DQ10
B11
B13
DBI2# DBI1# DQ17 DQ9 DQ19 DQ11 CMD3 A4_BA2 CMD19 A4_BA2
P2 B11 CLKC1 J12 E11
DBI3# DBI0# DQ18 DQ10 B13 CLKC1# J11 CK DQ20 DQ12 E13
DQ19 DQ11 CK# DQ21 DQ13 CMD4 A5_BA1 CMD20 A5_BA1
DQSC[7..0] CLKC1 J12 E11 CMDC30 J3 F11
(38,43) DQSC[7..0] CLKC1# J11 CK DQ20 DQ12 E13 CKE# DQ22 DQ14 F13
CK# DQ21 DQ13 DQ23 DQ15 CMD5 WE* CMD21 WE*
DQMC[7..0] CMDC30 J3 F11 CMDC25 J5 U11 MDC40
(38,43) DQMC[7..0] CKE# DQ22 DQ14 F13 A12/A13 DQ8 DQ16 U13 MDC41
DQ23 DQ15 DQ9 DQ17 CMD6 A7_A8 CMD22 A7_A8
MDC[63..0] CMDC25 J5 U11 MDC48 CMDC26 K4 T11 MDC42
(38,43) MDC[63..0] A12/A13 DQ8 DQ16 U13 MDC49 CMDC27 K5 A8/A7 A10/A0 DQ10 DQ18 T13 MDC43
DQ9 DQ17 A11/A6 A9/A1 DQ11 DQ19 CMD7 A6_A11 CMD23 A6_A11
CMDC[31..0] CMDC22 K4 T11 MDC50 CMDC17 K10 N11 MDC44
(38,42,43) CMDC[31..0] CMDC23 K5 A8/A7 A10/A0 DQ10 DQ18 T13 MDC51 CMDC18 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 MDC45
A11/A6 A9/A1 DQ11 DQ19 BA2/A4 BA0/A2 DQ13 DQ21 CMD8 ABI* CMD24 ABI*
CMDC20 K10 N11 MDC52 M11 MDC46
CMDC19 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 MDC53 CMDC20 H10 DQ14 DQ22 M13 MDC47
BA2/A4 BA0/A2 DQ13 DQ21 BA3/A3 BA1/A5 DQ15 DQ23 CMD9 A12_RFU CMD25 A12_RFU
M11 MDC54 CMDC19 H11 U4
CMDC17 H10 DQ14 DQ22 M13 MDC55 +1.35VSG CMDC23 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2
BA3/A3 BA1/A5 DQ15 DQ23 A9/A1 A11/A6 DQ1 DQ25 CMD10 A0_A10 CMD26 A0_A10
CMDC18 H11 U4 CMDC22 H4 T4
CMDC27 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 A10/A0 A8/A7 DQ2 DQ26 T2
A9/A1 A11/A6 DQ1 DQ25 DQ3 DQ27 CMD11 A1_A9 CMD27 A1_A9
2
CMDC26 H4 T4 N4
A10/A0 A8/A7 DQ2 DQ26 T2 A5 DQ4 DQ28 N2
DQ3 DQ27
R468
NC DQ5 DQ29 CMD12 RAS* CMD28 RAS*
N4 1K_0402_1% DIS@ U5 M4
A5 DQ4 DQ28 N2 NC DQ6 DQ30 M2
NC DQ5 DQ29 DQ7 DQ31 CMD13 RST* CMD29 RST*
U5 M4
1
NC DQ6 DQ30 M2 J1
DQ7 DQ31 MF
+1.35VSG CMD14 CK1* CMD30 CK1*
SEN3 J10
DIS@ 1 2 1K_0402_1% MF3 J1 1 R470 2 ZQ7 J13 SEN B1
R466
MF
+1.35VSG
ZQ VDDQ CMD15 CAS* CMD31 CAS*
R467 DIS@ 1 2 1K_0402_1% SEN3 J10 DIS@ D1
DIS@ 1 2 121_0402_1% ZQ6 J13 SEN B1 VDDQ F1
R472
ZQ VDDQ
121_0402_1%
VDDQ CMD32 NO USED
D1 CMDC24 J4 M1
VDDQ F1 CMDC31 G3 ABI# VDDQ P1
VDDQ RAS# CAS# VDDQ CMD33 NO USED
CMDC24 J4 M1 CMDC21 G12 T1
C CMDC28 G3 ABI# VDDQ P1 CMDC28 L3 CS# WE# VDDQ G2 C
RAS# CAS# VDDQ CAS# RAS# VDDQ CMD34 Debug0
CMDC16 G12 T1 CMDC16 L12 L2
CMDC31 L3 CS# WE# VDDQ G2 WE# CS# VDDQ B3
CAS# RAS# VDDQ VDDQ CMD35 Debug1
CMDC21 L12 L2 D3
WE# CS# VDDQ B3 VDDQ F3
VDDQ D3 FBB_WCK67#D5 VDDQ H3
VDDQ F3 FBB_WCK67 D4 WCK01# WCK23# VDDQ K3
D5 VDDQ H3 WCK01 WCK23 VDDQ M3
(38) FBB_WCK45# WCK01# WCK23# VDDQ VDDQ
D4 K3 FBB_WCK45# P5 P3
(38) FBB_WCK45 WCK01 WCK23 VDDQ WCK23# WCK01# VDDQ
M3 FBB_WCK45 P4 T3
P5 VDDQ P3 WCK23 WCK01 VDDQ E5
(38) FBB_WCK67# WCK23# WCK01# VDDQ VDDQ
P4 T3 N5
(38) FBB_WCK67 WCK23 WCK01 VDDQ VDDQ
E5 A10 E10
VDDQ N5 C763 U10 VREFD VDDQ N10
A10 VDDQ E10 2 1 FBB_VREFC J14 VREFD VDDQ B12
U10 VREFD VDDQ N10 820P_0402_25V8K VREFC VDDQ D12
FBB_VREFC J14 VREFD VDDQ B12 DIS@ VDDQ F12
(43) FBB_VREFC VREFC VDDQ VDDQ
D12 H12
VDDQ F12 CMDC29 J2 VDDQ K12
VDDQ H12 RESET# VDDQ M12
CMDC29 J2 VDDQ K12 VDDQ P12
RESET# VDDQ M12 VDDQ T12
VDDQ P12 VDDQ G13
VDDQ T12 VDDQ L13
CLKC1 VDDQ G13 VDDQ B14
(38) CLKC1 VDDQ L13 VDDQ D14
VDDQ VDDQ
1
B14 +1.35VSG F14
DIS@ VDDQ D14 VDDQ M14
R475 +1.35VSG VDDQ F14 G1 VDDQ P14
80.6_0402_1% VDDQ M14 L1 VDD VDDQ T14
G1 VDDQ P14 G4 VDD VDDQ
2
CLKC1# L1 VDD VDDQ T14 L4 VDD
B (38) CLKC1# G4 VDD VDDQ C5 VDD A1 B
L4 VDD R5 VDD VSSQ C1
C5 VDD A1 C10 VDD VSSQ E1
R5 VDD VSSQ C1 R10 VDD VSSQ N1
C10 VDD VSSQ E1 D11 VDD VSSQ R1 +1.35VSG
R10 VDD VSSQ N1 G11 VDD VSSQ U1
D11 VDD VSSQ R1 L11 VDD VSSQ H2
G11 VDD VSSQ U1 P11 VDD VSSQ K2
VDD VSSQ VDD VSSQ
10U_0805_25V6K
10U_0805_25V6K
C756
C752
C747
C760
C750
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
L11 H2 G14 A3
VDD VSSQ VDD VSSQ
1U_0402_6.3V6K
1U_0402_6.3V6K
P11 K2 L14 C3 1 1 1 1 1 1 1
VDD VSSQ VDD VSSQ
1
C758
C759
DIS@ C746
DIS@ C745
G14 A3 E3
L14 VDD VSSQ C3 VSSQ N3
VDD VSSQ VSSQ
DIS@
DIS@
DIS@
DIS@
DIS@
E3 R3
2
VSSQ VSSQ 2 2 2 2 2 2 2
DIS@
DIS@
N3 H1 U3
VSSQ R3 K1 VSS VSSQ C4
H1 VSSQ U3 B5 VSS VSSQ R4
K1 VSS VSSQ C4 G5 VSS VSSQ F5
B5 VSS VSSQ R4 L5 VSS VSSQ M5
G5 VSS VSSQ F5 T5 VSS VSSQ F10
L5 VSS VSSQ M5 B10 VSS VSSQ M10
T5 VSS VSSQ F10 D10 VSS VSSQ C11 +1.35VSG
B10 VSS VSSQ M10 G10 VSS VSSQ R11
D10 VSS VSSQ C11 L10 VSS VSSQ A12
G10 VSS VSSQ R11 P10 VSS VSSQ C12
VSS VSSQ VSS VSSQ
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
L10 A12 T10 E12
VSS VSSQ VSS VSSQ
DIS@ C751
DIS@ C754
DIS@ C749
DIS@ C755
DIS@ C753
1U_0402_6.3V6K
1U_0402_6.3V6K
P10 C12 H14 N12 1 1 1 1 1 1 2
VSS VSSQ VSS VSSQ
DIS@ C748
DIS@ C757
T10 E12 K14 R12
H14 VSS VSSQ N12 VSS170-BALL VSSQ U12
K14 VSS VSSQ R12 VSSQ H13
VSS170-BALL VSSQ U12 SGRAM GDDR5 VSSQ K13 2 2 2 2 2 2 1
VSSQ H13 VSSQ A14
SGRAM GDDR5 VSSQ K13 VSSQ C14
A VSSQ A14 VSSQ E14 A
VSSQ C14 VSSQ N14
VSSQ E14 VSSQ R14
VSSQ N14 VSSQ U14
VSSQ R14 VSSQ
VSSQ U14 @ K4G41325FC-HC04_FBGA170~D
VSSQ
@ K4G41325FC-HC04_FBGA170~D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX GDDR5 4/4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B111P
Date: Tuesday, February 25, 2014 Sheet 44 of 59
5 4 3 2 1
5 4 3 2 1
+3VS to +3V3_AON Vgs=-4.5V,Id=3A,Rds<97mohm +3VS to +3VS_DGPU
Vgs=-4.5V,Id=3A,Rds<97mohm
+3V3_AON +VGA_CORE
+3VS +3V3_AON +3VS_DGPU +3VS +3VS_DGPU
DIS@ Q36
2
2
+3VS 3 1 3 1
D
R476 R477
220_0402_5% 470_0805_5% Q25 AO3413_SOT23 SW@ AO3413_SOT23
DIS@ DIS@ SW@ R504
220_0402_5%
G
1 1 1 1
6 1
3 1
2
2
D C778 @ C779 C783 D
1
R478 DIS@ @ @ C784
20K_0402_5% 0.1U_0402_16V7K 0.01U_0402_16V7K 0.1U_0402_16V7K 0.01U_0402_16V7K
1
Q31A Q31B DIS@ 2 2 D 2 2
2 DGPU_PWR_EN# 5 2N7002KDWH_SOT363-6 2 3V3_MAIN_EN# R505
1
DIS@ DIS@ R479 G 3V3_MAIN_EN# 1 2
2N7002KDWH_SOT363-6 DGPU_PWR_EN# 1 2 V0.2A S Q35 SW@ 10K_0402_5% V0.2A
1
3
2N7002H_SOT23-3 V0.2A
10K_0402_5% SW@
DIS@
1
D
DGPU_PWR_EN 2 2N7002K_SOT23-3
(14,31) DGPU_PWR_EN Q34
G
S DIS@
3
V0.3
+1.35V to +1.35VSG
+1.35V +1.35VSG +3V3_AON +1.05VS to +1.05VSG
Q27 DIS@ +3V3_AON
2
AON6504_POWERDFN56-8-5 +3V3_AON
1 R524
C 2 2 10K_0402_5% +1.05VS +1.05VSG +3V3_AON C
2
5 3
@
R529 @ R480 R526 R522 R521
1
1 2 470_0402_5% 10K_0402_5% 10K_0402_5% +1.35VSG_PGOOD 10K_0402_5%
B+
2
V0.3 180K_0402_5% Q26 DIS@
DIS@ DIS@ DIS@ DIS@
4
1
R483 DIS@ D 8 1 R530 200K_0402_5% R482 R525 R523
1
1
1
VRAM_1.35VS_GATE 1 2 2 2N7002K_SOT23-3 7 D S 2 1 2 +1.05VS_DGPU_PGOOD
4.7U_0603_6.3V6K
V0.3 @ 470_0805_5% 10K_0402_5% 10K_0402_5%
+12VS Q39 D S B+
C780 180K_0402_5% G 6 3 DIS@
D S DIS@ DIS@
1
1
DIS@ C DIS@ 5 4 D
1 S
1
2 D G 2N7002K_SOT23-3
0.01U_0402_25V7K
R484 Q29A 2 Q41 1 VRAM_1.05VS_GATE 1 R491 2 2
+12VS Q38
C781 DIS@ 820K_0402_5% Q29B B MMST3904-7-F_SOT323-3 AO4354_SO8 1 DIS@ 200K_0402_5% G
1
0.01U_0402_25V7K
DIS@ 2 1.35V_PWR_EN# 5 2N7002KDWH_SOT363-6 DIS@E C S DIS@
3
2 2N7002KDWH_SOT363-6 DIS@ @ C789 2
1 1 C600 R490 Q28A Q42 1
2
2 0.1U_0402_16V7K
0.01U_0402_25V7K
4.7U_0603_6.3V6K
DIS@ DIS@ DIS@ 820K_0402_5% Q28B B MMST3904-7-F_SOT323-3
1
+5VALW C791 C605 2 2 3V3_MAIN_EN# 5 2N7002KDWH_SOT363-6 DIS@ E
3
DIS@ DIS@ 2N7002KDWH_SOT363-6 DIS@ @ C788
2
1 2 2 2 DIS@ 2 0.1U_0402_16V7K
4
100K_0402_5% R485 V0.2A +5VALW
DIS@
3
1 2
DIS@ 100K_0402_5% R486 V0.2A
Q30B DIS@
6
1.35V_PWR_EN 5
(36) 1.35V_PWR_EN
2N7002KDWH_SOT363-6 DIS@
Q30A
4
3V3_MAIN_EN 2
(36,54) 3V3_MAIN_EN
2N7002KDWH_SOT363-6
1
+3V3_AON +3V3_AON
B B
H_THRMTRIP# (18,5)
1
2
DIS@
2
R527 @
3
10K_0402_5% C786 DIS@ R528
2 0.1U_0402_16V7K D33
DIS@ 10K_0402_5%
Q44B 1 2
(18,36,54) DGPU_PWROK DIS@
1
GPU_OVERT 5 RB751V-40_SOD323-2
1
2N7002KDWH_SOT363-6
D32
6
DIS@
4
DIS@ +1.05VS_DGPU_PGOOD 1 2
2N7002KDWH_SOT363-6 RB751V-40_SOD323-2
2 1
(36,37) GPU_OVERT#
Q44A +1.35VSG_PGOOD R519 1 20_0402_5% GPU_ALL_PGOOD
GPU_ALL_PGOOD (14)
@ DIS@
1
C785
2 0.1U_0402_16V7K
1
DIS@ D DIS@
(36) DGPU_PEX_RST# R5201 20_0402_5%
2 @ @
G Q40 3V3_MAIN_EN 2 R532 1 +1.05VS_DGPU_PGOOD 1.35V_PWR_EN2 R533 1 +1.35VSG_PGOOD
V0.2 1 S 2N7002K_SOT23-3 1K_0402_5% 10K_0402_5%
3
1 1
@ C793 C792
C787 @ 0.1U_0402_16V7K @ 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 2
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX DC-DC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Tuesday, February 25, 2014 Sheet 45 of 59
5 4 3 2 1
5 4 3 2 1
EMI@ PL101
JDCIN1 PF101
FBMA-L11-201209-121LMA50T_0805
1 2
VIN
1 APDIN 12A_24VDC_429007.WRML
1 2 1 2 APDIN1 SM01000BY00
2 3 1 2
3 4 SP040006C00 EMI@ PL102
4
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
PC101 EMI@
PC102 EMI@
PC103 EMI@
PC104 EMI@
5 FBMA-L11-201209-121LMA50T_0805
5
ACES_50299-00501-003_5P
1
CONN@
SP02000YD00
2
D
135W adaptor D
1 2
PQ101A
@ PR101 0_0402_1% 2N7002KDW-2N_SOT363-6
680P_0603_50V7K
1 2 6 1
+3VALW ADP_ID (31)
0.1U_0402_16V7K
PR102
750_0402_1% A/D
1
PC105
PC106
2
PR103
2
2N7002KDW-2N_SOT363-6
100K_0402_5%
1 2
VIN
3
1
PQ101B
PR104
5
100K_0402_5% ADP_ID_CLOSE (31)
4
+CHGRTC
C PR105 C
1K_0603_5%
1 2
PD101 +3VLP
S SCH DIO BAS40CW SOT-323
2 +CHGRTC_R
+RTCVCC 1
3 PR106
1K_0603_5% JRTC1 CONN@
1 2 1
2 1
3 2
4 GND
GND
ACES_50271-0020N-001
GC02001DR00
RTC Battery BATT CR2032 3V 210MAH MB 5 W/C
30MM
B B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR DCIN / RTC Battery
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Tuesday, February 25, 2014 Sheet 46 of 59
5 4 3 2 1
5 4 3 2 1
EMI@ PL202
V0.2 SM01000AZ00_2P
VMB2 VMB 1 2
CONN@ PL201
JBATT1 PF201 SM01000AZ00_2P
1 1 2 1 2
1 2 BATT+
EMI@
2 3 EC_SMCA 15A_24V_F1206HB10V024TM
3 4 EC_SMDA SP040006F00 EMI@
4
0.01U_0402_25V7K
5 PC207 PC202
5 6 EMI@ PC208 EMI@
6
1000P_0402_50V7K
7 EMI@
7
1
100_0402_1%
100_0402_1%
D 8 0.01U_0402_25V7K D
GND 9 PC201
GND 1000P_0402_50V7K
2
PR201
PR211
SUYIN_125017GA007G101ZL
2
LTCX005GY00
2S2P / 54W +EC_VCCA
(31,48) ADP_I
16.5K_0402_1%
EC_SMB_CK1 (31,48)
1
VCOUT1_PROCHOT#
10K_0402_1%
PR215
EC_SMB_DA1 (31,48)
2
30K_0402_1%
PR216
1 2
+3VLP
PR217
PR212
2
6.49K_0402_1%
@ (31) VCIN0_PH1
A/D
1
1 2
VCIN1_BATT_TEMP (31)
1
PR214 (31) VCIN1_ADP_PROCHOT
10K_0402_5% PH201
2
100K_0402_1%_TSM0B104F4251RZ
(31) VCOUT1_PROCHOT# PWR_LEVEL_R (36) PR221
2
110K_0402_1%
1
ECAGND (31)
2
PR228 PR230
C +5VS +5VS 0_0402_5% 0_0402_5%
C
1
2
PR219
PC204
1
3
10K_0402_1% PQ202A PQ202B
1
0.01U_0402_25V7K 2N7002KDW-2N_SOT363-6 2N7002KDW-2N_SOT363-6
1
PR220
2
47K_0402_1% 2 5
6
2
4
8
VCIN1_BATT_DROP 3 PQ201A
P
+ 1 2 2N7002KDW-2N_SOT363-6 PC203
2 O 0.01U_0402_25V7K +5VS
2
-
G
+2.48V PU202A
1
AS393MTR-E1 SO 8P OP +2.48V
4
+5VS
47K_0402_1%
PR226
1
1
PQ201B 665K_0402_1%
PR222
PR232 2N7002KDW-2N_SOT363-6 1 2
1N4148WS-7-F_SOD323-2
2
1.5M_0402_5%
14.7K_0402_1% PR227
1
5 PR218 15K_0402_1%
3
PR202
PD204
10K_0402_1%
2
2
8
4
2 5
P
1
+
2
7 5 PQ215B
ENE9022 Battery Voltage drop detection.
2
O
2
PR231 VCIN1_BATT_DROP 6 2N7002KDW-2N_SOT363-6
-
G
10K_0402_1% PR229 Connect to ENE9022 pin64 AD1.
4
10K_0402_1%
4
1
D PU202B
1
B PQ205 2 AS393MTR-E1 SO 8P OP B
1
2N7002KW_SOT323-3 G
S
3
6
2N7002KDW-2N_SOT363-6 B+ near 5V input
PQ215A
2
1
B+
layou near +5VALWP
1
+5VS +2.48V PR12
PR225
3.65K_0603_1% PR223 PR224 56.2K_0402_1%
1 2 1 2 1 2
2
10K_0402_1% 10K_0402_1%
VCIN1_BATT_DROP (31)
2
PC209
470P_0402_50V7K 2
1
1
2
@ PC8 PR13
REF
0.1U_0402_25V6 10K_0402_1%
1
3 PU201
2
Cathode
APL431LBAC-TRL_SOT23-3
A A
SA00001MU00
Anode
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN/OTP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Tuesday, February 25, 2014 Sheet 47 of 59
5 4 3 2 1
5 4 3 2 1
AO4407AL Vds=-30V
Rds_on=12.7~17mohm@Vgs=-6V P3 Power Rating = 1W Need EC write ChargeOption() bit[8]=0
ID = 10A (Ta=70C) P2 B+
VACP~VACN spec < 80.64mV to disable iFault_Hi function.
PQ301 SB00000DL10 PQ302 SB000012200
AO4407AL 1P SO8 AO4447A 1P SOIC8 SD00000K820
8 1 1 8 PR302
VIN 7 2 2 7 0.01_1206_1% EMI@ PL301 CHG_B+
6 3 3 6 1UH +-20% PH041H-1R0MS 3.8A
5 5 1 4 1 2 PQ303 SB000012B00
AO4455 1P SO8
2 3 SH00000YG00 1 8
4
3.8x3.8xH1.8 2 7
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
3 6
DCR: 20~25mohm
PC304
PC305
@EMI@ PC306
@EMI@ PC307
PQ304 5
D D
1 2 Idc / Isat: 3.8A
47K_0402_5%
@EMI@ PC303
1
1
10U_0805_25V6K
200K_0402_1%
0.1U_0603_25V7K
4
1
PR301
DTA144EUA_SC70-3 PC302 DISCHG_G
PC301
PR303
5600P_0402_25V7K
2
PR304
ACDET 200K_0402_1%
2
2
2 1 2
2
ACN VIN
2ACOFF-1
1
1
ACP PR305
1DISCHG_G-1
47K_0402_1%
1SS355_UMD2-2
1
1
V1
PD302
P2-1 PR306
2
2 200K_0402_1%
PQ305 PC308 PC309 PQ306
0.1U_0402_25V6 0.1U_0402_25V6 DTC115EUA_SC70-3
2
DTC115EUA_SC70-3 1 2 1 2
PD303
3
1SS355_UMD2-2
2 1 2
6
charge current: 7.4A PQ309
150K_0402_1%
PR308
PQ307A 2N7002KW _SOT323-3
0.1U_0603_25V7K
discharge current: 9A
1
2 2N7002KDW -2N_SOT363-6 ACPRN# P2 D
1
Hybrid: BATT limit 6.5A
PC311
PC310 2PACIN_2
1 2 G
1
VIN PACIN
2
S
3
0.1U_0402_25V6
124K_0402_1%
249K_0402_1%
1
1
P2-2
PACIN_2 SB00000H800
5
C C
PR309
PR328
10_1206_5%
2N7002KDW-2N_SOT363-6
AON7408L 1N DFN
5
PR310
3
PQ307B
10x10xH4
ACOK
CMPIN
CMPOUT
ACP
ACN
PR311 PR312 (31,47) ADP_I PR313
DCR: 17~20mohm
2
PQ310
47K_0402_1% 20K_0402_1% 21 0_0402_5%
2
PACIN 1 2 5 1 2 6 TP 1 2 4 Idc: 8.5A
ACDET PC314
Isat: 15A
PC313 20 BQ24737VCC 1 2
4
PC312 1 2 7 VCC SD00000K820
1 2 IOUT SH00000Q900 PR314
3
2
1
1U_0603_25V6K
1
PQ311 0.01u_0402_25V7K 100P_0603_50V8 19 PL302 0.01_1206_1%
PHASE
DTC115EUA_SC70-3
(31,47) EC_SMB_DA1
8
SDA
PU301 4.7UH +-20% PCMB104T-4R7MS 8.5A
1 2CHG 1 4
BATT+
BQ24737RGRR_VQFN20_3P5X3P5 LX_CHG
18 DH_CHG SB000010U00
HIDRV
5
1 PR315 2 ACOFF-1 2 9
EMI@ PR319
2 3
SA00004RZ00
AON7752 1N DFN
(31) ACOFF SCL
1
(31,47) EC_SMB_CK1 PR317 PR318
4.7_1206_5%
10K_0402_1% 201K_0402_1% 2.2_0603_5% PC315
1 2 10 17 BST_CHG 1 2 1 2 SRP SRN
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
ILIM BTST
1
16251_SN
196K_0402_1%
+3VLP PD301
3
PQ312
PR320
0.047U_0603_16V7K 4
LODRV
0.01U_0402_25V7K
PC316
2
1
1
16 2 1
PC317
PC318
PC324
GND
SRN
SRP
REGN
BM
680P_0603_50V7K
2
2
RB751V-40_SOD323-2
EMI@ PC320
@
11
1 12
13
14
15
3
2
1
1
1
10_0603_5%
6.8_0603_5%
2
PR321
PC319
PR322
1U_0603_16V7 BQ24737VDD
2
2
2
1
DL_CHG
PC321
B @ PR323 B
10K_0402_5% 1 2
2
0.1U_0402_25V6
1
VILIM=3.366V*(196/(196+200))
1
=20*Ichg*10m PC323
Ichg=Idchg=8.33A 0.1U_0402_25V6 @ PC322
2
+3VALW 0.1U_0402_25V6
2
BQ24737VDD
PR326
10K_0402_1%
1
1 2
ACIN (31)
PR325
MOSFET: 3x3 DFN PR324 10K_0402_1%
47K_0402_1%
H/S Rds(on): 22mohm(Typ), 34mohm(Max) PACIN
1 2
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C
1
L/S Rds(on): 8.2mohm(Typ), 14.5mohm(Max)
Idsm: 12A@Ta=25C, 15A@Ta=70C PR327
ACPRN# 2
12K_0402_1%
2
PQ314
DTC115EUA_SC70-3
3
A A
For disable pre-charge circuit
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger_BQ24737
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Tuesday, February 25, 2014 Sheet 48 of 59
5 4 3 2 1
A B C D E
1 1
PR401
499K_0402_1%
ENLDO_3V5V 1 2
B+
1
150K_0402_1%
PU401 PC403 PR403
B+
PR404
EMI@ PL401 7 1 3V5V_EN 0.01U_0402_25V7K 1K_0402_5%
HCB2012KF-121T50_0805 IN EN1 1 2 1 2
2200P_0402_50V7K
1 2 3V_VIN 8 3 3V_FB
IN EN2 PR405 PC404
2
10U_0805_25V6K
10U_0805_25V6K
@EMI@ PC405
0.1U_0402_25V6
6 1
BST_3V 2 1 2
BS
1
PC407
C407
0_0603_5%
@EMI@ PC401
PC406
0.1U_0603_25V7K
@
@P PL402
2
10 LX_3V 1 2
LX +3VALWP
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
9 4 1.5UH_PCMB053T-1R5MS_6A_20%
GND OUT TDC=6A
PR406
SH00000SC00
1
PC408
PC409
PC410
PC411
680P_0603_50V7K 4.7_1206_5%
2 5
T80 PG LDO +3VLP 5x5xH3
Iocp : 8A
1
SY8208BQNC_QFN10_3X3 FSW : 750KHz
DCR: 20~25mohm
2
@EMI@
SA000061M00 PC412
Idc: 6A
1 3V_SN
4.7U_0603_6.3V6M
2
Isat: 10A
@EMI@ PC413
3.3V LDO 150mA~300mA
2
2 PR407 2
2.2K_0402_5%
1 2
(31) EC_ON
@ PR408
1 2
(31) VCOUT0_MAIN_PWR_ON 0_0402_5%
@ PJ401
+3VALWP 1 2 +3VALW
MAINPWON 1 2
JUMP_43X118
3V5V_EN
1M_0402_1%
4.7U_0402_6.3V6M
1
1
PR410
PC414
2
2
B+ EMI@ PL403
HCB2012KF-121T50_0805
1 2 5V_VIN
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
PU402 PC415 PR412
8 1 3V5V_EN 6800P_0402_25V7K 1K_0402_5%
IN EN1 1 2 1 2
1
1
PC416
PC418
@EMI@ PC419
@EMI@ PC420
3 5V_FB PR413 PC417
3 EN2 0_0603_5% 0.1U_0603_25V7K 3
6 BST_5V 1 2 1 2
2
BS
PL404
9 10 LX_5V 1 2 +5VALWP
GND LX
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
5V_VCC 5 4 1.5UH +-20% PCMC063T-1R5MN 9A
VCC OUT TDC=6A
1
@EMI@ PR414
680P_0603_50V7K 4.7_1206_5%
SH000008800
1
PC422
PC423
PC424
PC425
PC428
PC429
2 7 7x7xH3
PG LDO +5VL Iocp : 9A
1
PC421
4.7U_0603_6.3V6M
SY8208CQNC_QFN10_3X3
DCR: 20~25mohm
FSW : 750KHz
2
Idc: 8A
1 5V_SN
SA000061N00 @ PJ402
2
2
1
PC426
4.7U_0603_6.3V6M
Isat: 12A +5VALWP 1 2 +5VALW
1 2
JUMP_43X118
2
@EMI@ PC427
2
5V LDO 150mA~300mA
PR402
1 2
10_0402_1%
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+3VALW/+5VALW
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Tuesday, February 25, 2014 Sheet 49 of 59
A B C D E
5 4 3 2 1
D D
EMI@ PL503
HCB2012KF-121T50_0805
1 2
EMI@ PL501
HCB2012KF-121T50_0805
B+ 1 2 1.35V_B+ PR501
0_0603_5%
BST_1.35V 1 2 BOOT_1.35V
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
+1.35VP
@EMI@ PC501
@EMI@ PC502
1
1
PC503
PC504
PC511
2 DH_1.35V +0.675VSP
1
SW _1.35V
10U_0805_6.3V6K
10U_0805_6.3V6K
PC505
1
0.1U_0603_25V7K
PC506
PC507
2
5
16
17
18
19
20
C PQ501 PU501 C
2
10x10xH4
VLDOIN
PHASE
UGATE
BOOT
VTT
MDU1516URH 1N DFN56-8
21
SB00000S800
DCR: 3~3.3mohm PAD
Idc: 18A 4 DL_1.35V 15
LGATE VTTGND
1
Isat: 28A
14 2
PL502 PR502 PGND VTTSNS
1
2
3
1UH_PCMB104T-1R0MH_18A_20% 11K_0402_1%
1 2 1 2 CS_1.35V 13 3
+1.35VP SH00000N800 PC508 CS RT8207MZQW _W QFN20_3X3 GND
1
PQ502
1U_0603_10V6K
PC510
5
MDU1511RH 1N DFN56-8 1 2 12 4 +VTTREFP
TDC=17A (+VRAM) ESR 12mohm VDDP VTTREF
@EMI@ PR503 PR504
390U 2.5V M C6 R10M SVPE H5.9
4.7_1206_5% 5.1_0603_5%
Iocp : 25A 1
1 2 VDD_1.35V 11 5
SF000003X00
SB00000SD00
+5VALW +1.35VP
1 2
VDD VDDQ
1
+
PGOOD
FSW : 300KHz 4 1 2 PC509
+5VALW
TON
1
@EMI@ PC513 PR513 0.033U_0402_16V7K
FB
S5
S3
2
2 680P_0402_50V7K PC512 5.1_0603_5%
2
1U_0603_10V6K
10
6
+3VALW
1
2
3
1 2
FB_1.35V
EN_0.675VSP
TON_1.35V
EN_1.35V
PR505 100K_0402_5% PR506
8.45K_0402_1%
PR507 1 2 +1.35VP
887K_0402_1%
B 1.35V_B+ 1 2 B
1
MOSFET: 5x6 DFN Vout=0.75V* (1+Rup/Rdown)
H/S Rds(on): 5mohm(Typ), 8.5mohm(Max) PR508
Idsm: 23A@Ta=25C, 18A@Ta=70C @ PR509 10K_0402_1%
1 2
(31,35) SYSON
2
Mode Level +0.675VSP VTTREF_1.35V 0_0402_5%
L/S Rds(on): 2.8mohm(Typ), 3.8mohm(Max)
S5 L off off
1
Idsm: 33.5A@Ta=25C, 42A@Ta=70C @ PC514
S3 L off on 0.1U_0402_10V7K
S0 H on on
2
Note: S3 - sleep ; S5 - power off PR510
47K_0402_1%
1 2 @ PJ501
(31,35,51,52,53) SUSP# +1.35VP 1 2 +1.35V
1 2
1
JUMP_43X118
PC515 @ PJ502
0.1U_0402_10V7K 1 2
2
1 2
JUMP_43X118
PJ503 @
1 2
+0.675VSP 1 2 +0.675VS
A
JUMP_43X39 A
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RT8207M
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Tuesday, February 25, 2014 Sheet 50 of 59
5 4 3 2 1
A B C D
+3VALW
1
1 1
PC603
1U_0402_6.3V6K
2
PU601 SA000034S00
APL5930KAI-TRG_SO8
6
5 VCNTL 3
9 VIN VOUT 4 +1.5VSP
VIN VOUT
22U_0603_6.3V6M
0.022U_0402_16V7K
1
1
PC602 8
EN
1
PC605
7 2
PC604
4.7U_0603_6.3V6K
GND
T81 POK FB PR605
2
20K_0402_1%
2
FB=0.8V
2
PR601
(31,35,50,52,53) SUSP# 1 2 +1.5VSP_EN FB_1.5VSP_UMA
10K_0402_5%
1
1
PR603
PC601 1M_0402_5% PR606
0.1U_0402_16V7K 22.6K_0402_1% @
PJ602
2
1 2
+1.5VSP 1 2 +1.5VS
JUMP_43X79
2 2
PL1203 +12VSP_Panel
1UH +-20% MMD-04BZ-1R0M-V1 3.75A
2 1 LX_AVDD 2 1
+5VALW
+12VSP_Panel
10U_0805_25V6K
SH00000G200 PD1202
22U_0805_25V
22U_0805_25V
22U_0805_25V
22U_0805_25V
1
3
SX34_SMA2 3
PC1216
1
PC1218
PC1219
PC1222
PC1223
10U_0805_25V6K @ PC1215
100P_0402_25V8K
2
1
+
PC1220
PC1225 PU1203
6
1
2 1 88.7K_0402_1%
2
PR1208 47U 16V M D2 ESR40M TQC H1.9
LX
LX
2
12PAL_VIN 8 2 12PAL_FB
2
Vin FB SGA00006W 00
PC1221 0.01U_0402_16V7K
12PAL_FREQ 9 10 1 2
FREQ SS
1
0_0402_5%
1 2 PR1210
PR1211 1 10K_0402_1%
12PAL_EN 1 2 3 COMP
EN
1
PR1213
100K_0402_1%
0.1U_0402_10V7K
GND
GND
PAD
2
47K_0402_1% 100K_0402_1%
1
PR1209
PC1226
PR1212
@
PJ1202
+12VSP_Panel
11
1 2
+12VS_PANEL
2
1 2
1
PC1224 JUMP_43X79
470P 50V K X7R 0402
2
SA00004JV00
RT9297GQW _W DFN10_3X3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Tuesday, February 25, 2014 Sheet 51 of 59
A B C D
5 4 3 2 1
D D
PR702
2.2K_0402_5%
1 2
SUSP# (31,35,50,51,53)
C C
1
PC702
1M_0402_1% 0.1U_0402_16V7K
2
PR703 PJ701
2
+1.05VSP 1 2 +1.05VS
1 2
JUMP_43X118 @
@EMI@ PR704 @EMI@ PC703
4.7_1206_5% 680P_0603_50V7K
EMI@ PL701 1 2SNB_1.05VSP
1 2
HCB2012KF-121T50_0805 PU701
B+ 1 2 B+_1.05VS 8
IN EN
1 PR705
0_0603_5%
PC704
0.1U_0603_25V7K
10U_0805_25V6K
10U_0805_25V6K
6 1
BST_1.05VS 2 1 2 PL702
PC701
PC705
0.1U_0402_25V6
2200P_0402_50V7K
BS
1
1UH_PCMB063T-1R0MS_12A_20%
PC706
PC707
3VLDO_1.05VS 9
GND LX
10 LX_1.05VS 1
SH00000YE00
2
+1.05VSP
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
7x7xH3
@EMI@
@EMI@
1
100K_0402_1%
DCR: 6.7~7.4mohm
330P_0402_50V7K
1
1
PC709
PC710
PC711
PC712
PC715
PC716
@ 4 TDC=8A
PR707
PR706 FB Idc: 12A
PC708
3
ILMT_1.05VS 7
Rup
0_0402_5%
+3VALW Isat: 15A Iocp 12A
2
ILMT BYP
2
2
4.7U_0603_6.3V6K
ILMT_1.05VS
+3VS 1 2 +1.05VS_PGOOD 2
PG LDO
5 3VLDO_1.05VS
FSW 800KHz
1
PR701
PC714
4.7U_0603_6.3V6K
1
1
10K_0402_5% SY8208DQNC_QFN10_3X3
PC713
SA000061Q00
1
PR708
@
2
0_0402_5% PR709
127K_0402_1%
Rdown
2
2
(31) +1.05VS_PGOOD
B
The current limit is set to 8A, 12A or 16A when this pin B
is pull low, floating or pull high
VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.05VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Tuesday, February 25, 2014 Sheet 52 of 59
5 4 3 2 1
5 4 3 2 1
D D
7x7xH3
DCR: 28~33mohm
PC1211 PR1207
Idc: 5.5A @EMI@ @EMI@
P-MOS 2 1 2 1
Isat: 6.5A
SB00000TJ00 680P_0603_50V7K 4.7_1206_5%
PQ1201 AON7407_DFN8-5
1 PL1201 PD1201 EMI@ PL1202
2 4.7UH_PCMB063T-4R7MS_5.5A_20% HCB2012KF-121T50_0805
C 3 5 1 2 2 1 1 2 C
+5VALW SH00000YC00 +12VSP
10U_0805_25V6K
1
1
LX_12VSP SS1P4-M3-84A_DO-220AA2
100P_0402_25V8K
1500P_0402_50V7K
4
1
1
PC1205
PC1204
PC1214
1
1
PR1204 PC1210 88.7K_0402_1%
2
100K_0402_1% 0.022U_0402_25V7K 10U_0805_25V6K PR1203
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
0.1U_0402_25V6
2
PC1206
@EMI@ PC1213
@EMI@ PC1212
2
2
6
1
2 1 PU1201 @
PC1207
PC1208
PC1209
LX
LX
1
2
VIN_12VSP 8 2FB_12VSP
PR1205 Vin FB
10K_0402_1% PC1202 0.01U_0402_16V7K
FREQ_12VSP 9 10 1
SS_12VSP 2
2
FREQ SS
PQ1202
1
2N7002KW _SOT323-3 1COMP_12VSP
D COMP
1
@ PR1206 EN_12VSP 3 PR1202
1 2 2 EN 10K_0402_1%
(31,35,50,51,52) SUSP#
1
G
GND
GND
PAD
0_0402_5% SA00004JV00
S
3
2
1
@ PC1203 RT9297GQW _W DFN10_3X3 10K_0402_1%
0.1U_0402_10V7K PR1201
11
5
2
2
1
PC1201
B 4700P_0402_25V7K B
2
PJ1201 @
1 2
+12VSP 1 2 +12VS
JUMP_43X39
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+12V-Boost
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A3 VPUAE 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 25, 2014 Sheet 53 of 59
5 4 3 2 1
A B C D
GPU_B+
EMI@ PL905
FBMA-L11-201209-121LMA50T_0805
1 2
EMI@ PL906
FBMA-L11-201209-121LMA50T_0805
1 2
B+ 1
GPU_B+
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
FBMA-L11-201209-121LMA50T_0805 PR901
100U_25V_M
1 2 + 2.2_0603_5%
PC1134
1
EMI@ PL901 1
U2_BOOT1 2
@EMI@ PC902
@EMI@ PC903
PC904
PC905
PC901
2 PQ901
1
2
5
SB00000S800
1
PC906 1
0.22U_0603_25V7K
2
MDU1516URH 1N DFN56-8
U2_UGATE1 1 2 4
For intel N15P-GX
PR902 7x7xH4 Imax: 51A
MOSFET: 5x6 DFN 0_0603_5% Peck current: 76.5A
DCR: 0.98mohm
H/S Rds(on): 5mohm(Typ), 8.5mohm(Max) Idc / Isat: 28A OCP: 91.8A
3
2
1
Idsm: 23A@Ta=25C, 18A@Ta=70C Frequency: 450KHz
PL902
0.22UH 20% PCME064T-R22MS0R985 28A +VGA_CORE
L/S Rds(on): 2.8mohm(Typ), 3.8mohm(Max) U2_PHASE1 1 2
Idsm: 33.5A@Ta=25C, 42A@Ta=70C SH00000OY00
PC907
PC909
5
MDU1511RH 1NDFN56-8
PQ902
1 1
560U 2V M D2 LESR4.5M SX H1.9
330U 2V D2 LESR9M EEFSX H1.9
PR903 @EMI@ +@ +
4.7_1206_5%
SGA20331E10
SB00000SD00
SGA00006J00
U2_LGATE1 4 2 2
2
@ PR904 1K_0402_5% ESR: 9mohm
1
1 2 PC911 @EMI@
14.3K_0402_1%
680P_0603_50V7K
PR905
3
2
1
@ PR906 1K_0402_5%
2
1 2
+3V3_AON Rocset +VGA_CORE
2
1 2
NVVDD_PWM_VID (36)
@ PR907 0_0402_1%
PC910
1
330U 2V D2 LESR9M EEFSX H1.9
+@
1
1
PC912 GPU_B+
Rref1
SGA20331E10
1U_0402_6.3V6K PR908 2
2
2 20K_0402_1% 2
PR909
Rboot Rrefadj 2.2_0603_5%
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
2
U2_BOOT2 1 2 PQ903
5
PR910 PR911 @ PR912 0_0402_1% SB00000S800
@EMI@ PC916
1
1
2K_0402_5% 20K_0402_1% 1 2 NVVDD_PSI (36)
@EMI@ PC917
PC918
PC919
PC914
1 2 1 2 PC913
MDU1516URH 1N DFN56-8
@ PC915 47P_0402_50V8J 0.22U_0603_25V7K
2
1 2 2
18K_0402_1%
1
U2_UGATE2 1 2 4
2700P_0402_50V7K
0.01U_0402_16V7K
PR916 PR915
PR914
@ PC920
GPU_VID
1 1K_0402_5% 0_0603_5%
1
Rref2 1 2
PC921
3V3_MAIN_EN (36,45)
1
2
3
2
1
C PL903 +VGA_CORE
2
2 @ PC938
@PC938 0.22UH 20% PCME064T-R22MS0R985 28A
GPU_REFADJ
U2_BOOT1
1
U2_UGATE1
0.01UF_0402_25V7K U2_PHASE2 1 2
0_0402_5%
2
GPU_PSI
PR917
GPU_EN
SH00000OY00
PC923
1
MDU1511RH 1NDFN56-8
PQ904
330U 2V D2 LESR9M EEFSX H1.9
2
1
GPU_FBRTN PR918 RF@ +
4.7_1206_5%
SGA20331E10
6
PU901 1 2
SB00000SD00
PR919 +5VS U2_LGATE2 4
UGATE1
BOOT1
VID
PSI
EN
REFADJ
1 2
Rton 357K_0402_1%
GPU_B+ 1 2
1 GPU_REFIN 7 24 U2_PHASE1 PC926 RF@
REFIN PHASE1
1
@ PR920 680P_0603_50V7K
3
2
1
2
(37) VSSSENSE_VGA 0_0402_1% @ PC925
@PC925 GPU_VREF 8 23 U2_LGATE1 PR921 +5VS
1 2 0.01UF_0402_25V7K VREF LGATE1
2.2_0603_1%
2 GPU_TON 9 22 U2_PWM3
TON GND/PWM3
1
1 2 GPU_FBRTN 10 21
RGND PVCC PR923
1
11 20 U2_LGATE2
TALERT/ISEN2
@ PR922 2.2_0603_1%
0.1U_0603_25V7K
VSNS LAGTE2
1
100_0402_1% @ PC927 GPU_B+
TSNS/ISEN3
PC928
VCC/ISEN1
3
47P_0402_50V8J GPU_COMP 12 19 U2_PHASE2 3
2
2
SS PHASE2
UGATE2
PGOOD
@ PR924
BOOT2
2
1 2 GPU_FB
GND
0.1U_0603_25V7K
1
PC929
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
(37) VCCSENSE_VGA 0_0402_1% PQ905
5
@ PC930 RT8813AGQW_WQFN24_4X4 SB00000S800
@EMI@ PC931
25
13
14
15
16
17
18
1
1 2 Css 0.01U_0402_16V7K SA00005ZV00
@EMI@ PC932
PC933
PC934
PC935
+VGA_CORE 1 2 PU902 SA00005Z710
GPU_TSNS/ISEN3
8 3 PR928U2_UGATE3 1 2
MDU1516URH 1N DFN56-8
@ PR925
1 GPU_TALERT/ISEN2
2
VCC UGATE
GPU_VCC/ISEN1
100_0402_1% 0_0402_5% PR927 2.2_0603_5% PR926
1 2 1 4 1
U2_BOOT3 2 0_0603_5% 4
GPU_EN
GPU_PGOOD1
EN BOOT
U2_UGATE2
U2_BOOT2
U2_PWM3 1 2 5 2
0_0402_5% PR929 PWM PHASE
1 1
@ PC941 6 7
3
2
1
GND LGATE PC936 PL904 +VGA_CORE
0.22U_0603_25V7K 0.22UH 20% PCME064T-R22MS0R985 28A
TP
2 0.01UF_0402_25V7K 2
U2_PHASE3 1 2
PR930
PR931
PR932
1
RT9610BZQW_WDFN8_2X2
9
SH00000OY00
PC937
1
MDU1511RH 1NDFN56-8
PQ906
330U 2V D2 LESR9M EEFSX H1.9
1
+3V3_AON PR933 RF@ +
10K_0402_1%
10K_0402_1%
10K_0402_1%
2
4.7_1206_5%
SGA20331E10
2
10K_0402_1%
SB00000SD00
1
U2_LGATE3 4
1 2
PR934
V0.1A PC939 RF@
U2_PHASE3
U2_PHASE2
U2_PHASE1
680P_0603_50V7K
2
3
2
1
2
1 2 1 2
+3VLP
PR938 PH901 DGPU_PWROK (18,36,45)
1
8.66K_0402_1% 100K_0402_1%_NCP15WF104F03RC
PC908
7.68K_0402_1%
2
0.1U_0603_25V7K
2
PR935
4 4
PU903
1 8
VCC TMSNS1
1
2 7
GND RHYST1
3 6
(31) PWR_GPS_DOWN# OT1 TMSNS2
4 5
OT2 RHYST2
G718TM1U_SOT23-8
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RT8813
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 25, 2014 Sheet 54 of 59
A B C D
A B C D
1 1
100K_0402_1%_B25/50 4250K
VREF
4700P_0402_16V7K
1
105K_0402_1%
100K_0402_1%
255K_0402_1%
36.5K_0402_1%
1
1
PH1102
1
PC1102
PR1103
@ PR1104
PR1105
PR1106
@ PR1102 EMI@ PL1101
10K_0402_1% FBMA-L11-201209-121LMA50T_0805
1 2
2
EMI@ PL1105
2
2
FBMA-L11-201209-121LMA50T_0805
1 2
B+ CPU_B+
1000P_0402_50V7K
39K_0402_1%
150K_0402_1%
150K_0402_1%
20K_0402_1%
1 1 PR1112
100U_25V_M
100U_25V_M
8.06K_0402_5%
SF000004L00
SF000004L00
1 1 2 2.43K_0402_1%
PR1107
PR1109
PR1110
PR1111
PC1101
PC1135
EMI@ PL1106 + + CSP3-1 1 2
1
PR1108
PC1103 FBMA-L11-201209-121LMA50T_0805
1
3.01K_0402_1%
1
2 2
TPS51361A => 39Kohm, PR1113 2
PR1101
39K_0402_1%
2
TPS51633RSMR => 20Kohm
11.8K_0402_1%
0.15U_0402_10V6K
0.15U_0402_10V6K
EMI Part (47.1) CSP3
1
2
1
PR1114
PC1104
PC1105
10K_0402_1%_B25/50 3370K
2
CPU_B+
B-RAM
OCP-I
F-IMAX RF@ PC1106 PR1116RF@
2
1
10U_0805_25V6K
SLEWA 680P_0402_50V7K 4.7_1206_5% @ CSN3
2
PR1115
10U_0805_25V6K
PH1101
1 2 1 2
1
PC1108
1 2 O-USR
CPU_B+
1
PC1107
16
15
14
13
12
11
10
2
9
10K_0402_1% PU1101
9
SLEWA
B-RAMP
F-IMAX
VBAT
THERM
IMON
OCP-I
O-USR 5 4 1 4
PGND2
VIN VSW +VCC_CORE
2 CSP1 17 8 1 2 6 3 2 3 2
CSP1 VR_ON VR_ON (31) BOOT_R PGND1
PR1117 2.2_0402_1%
CSN1 18 7 SKIP# 1 2 7 2 PL1104 SH00000U300
CSN1 SKIP# PC1109 .1U_0402_16V7K
BOOT VDD +5VS 0.15UH 20% PCME064T-R15MS0R667 36A
1
CSN2 19 6 PWM1 PWM3 8 1 1 2 SKIP# 7x7xH4
CSN2 PWM1 PWM
1
PR1141 SKIP#
CSP2 20 5 PWM2 1.5K_0402_1% PU1104 SA000066Y00 @ PR1118
@PR1118 PC1110 DCR: 0.66mohm
CSP2 PWM2 CSD97374CQ4M_SON8_3P5X4P5 0_0402_5% Idc: 36A
@ 1U_0402_6.3V6K
2
CSP3 21 TPS51631ARSMR_QFN32_4X4 4 PWM3 Isat: 45A
2
CSP3 PWM3
CSN3 22 SA000062510 3
CSN3 PGOOD VGATE (31)
GFB 23 2 PR1120
@ PR1119
@PR1119 GFB VDD 2.43K_0402_1%
VR_HOT#
ALERT#
VFB 24 1 VR_SVID_DAT CSP1-1 1 2
DROOP
0_0402_5%
COMP
VFB VDIO
1
10_0402_1%
3.01K_0402_1%
VREF
1 2
VCLK
GND
PAD
(9) VSSSENSE
V5A
1
PR1122
PR1123
PR1124
1 2 10K_0402_1%
(9) VCCSENSE
25
26
27
28
29
30
31
VR_SVID_ALRT# 32
33
11.8K_0402_1%
0.15U_0402_10V6K
0.15U_0402_10V6K
@ PR1121
@PR1121 EMI Part (47.1) EMI Part (47.1) CSP1
2
10K_0402_1%_B25/50 3370K
0_0402_5% PC1111
1
PR1125
PC1112
@PC1113
1U_0402_6.3V6K
VR_SVID_CLK
@ PC1115 CPU_B+
1
PC1117 @EMI@
PC1116 @EMI@
2.2P_0402_50V8C RF@ PC1114 PR1126RF@
VR_HOT#
2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
PH1103
0.1U_0402_25V6
1 2 PR1127 680P_0402_50V7K 4.7_1206_5% CSN1
+3VS
2
3.4K_0402_1% 1 2 1 2
1
PC1118
PC1119
PR1128 1 2
10K_0402_1%
2
1 2 2
2
VREF
9
PR1129 PC1120
10K_0402_1% 330P_0402_50V7K 5 PGND2 4 1 4
PR1130 +VCC_CORE
1
1 2 1 2 VIN VSW
PC1121 1 2 6 3 2 3
0.33U_0402_10V6K PC1122 2.2_0402_1% BOOT_R PGND1
2
1 2 7 2 PL1102 SH00000U300
.1U_0402_16V7K
BOOT VDD +5VS 0.15UH 20% PCME064T-R15MS0R667 36A
PWM1 8
PWM
1 1 2 SKIP# For intel SB 47W
1
SKIP#
PR1132 PU1102 SA000066Y00 @ PR1131
@PR1131 PC1123 TDC: 33A
10_0402_1% CSD97374CQ4M_SON8_3P5X4P5 0_0402_5%
3 1U_0402_6.3V6K Support Turbo: 95A 3
2
1 2
+5VS OCP setting: 114A
Frequency: 1MHz
1
PR1133
PC1124 2.43K_0402_1% DC_LL: -1.5mV/A
1U_0402_6.3V6K CSP2-1 1 2
2
3.01K_0402_1%
1
PR1134
+VCCIO_OUT
11.8K_0402_1%
0.15U_0402_10V6K
0.15U_0402_10V6K
EMI Part (47.1) CSP2
1
PR1135
PC1125
@PC1126
10K_0402_1%_B25/50 3370K
2
CPU_B+
@EMI@ PC1127 PR1138@EMI@
2
1
10U_0805_25V6K
10U_0805_25V6K
680P_0402_50V7K 4.7_1206_5% CSN2
2
1
1
130_0402_1%
54.9_0402_1%
PH1104
1 2 1 2
1
1
PR1136
PR1137
PC1129
PC1130
PC1128
.1U_0402_16V7K
2
2
2
5 PGND2 4 1 4
(9) VR_SVID_CLK
VIN VSW +VCC_CORE
1 2 6 3 2 3
PR1139 2.2_0402_1% BOOT_R PGND1
(9) VR_SVID_ALRT# 1 2 7 2 PL1103 SH00000U300
(9) VR_SVID_DAT PC1131 .1U_0402_16V7K
BOOT VDD +5VS 0.15UH 20% PCME064T-R15MS0R667 36A
PWM2 8 1 1 2 SKIP#
PWM
1
VR_HOT# SKIP#
(31) VR_HOT# PU1103 SA000066Y00 @ PR1140
@PR1140 PC1132
CSD97374CQ4M_SON8_3P5X4P5 0_0402_5% 1U_0402_6.3V6K
2
1
@ PC1133
@PC1133
47P_0402_50V8J
2
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE-47W
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sheet 55 of 59
A B C D
A
B
C
D
5
5
+VCC_CORE
2 1 2 1 2 1 2 1
1U_0402_6.3V6K 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1327
@
PC1321 PC1311 PC1301
2 1 2 1 2 1 2 1
2
1
+
1U_0402_6.3V6K 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1328 PC1322 PC1312 PC1302
+VCC_CORE
2 1 2 1 2 1 2 1
PC1331
1U_0402_6.3V6K 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1329
@
PC1323 PC1313 PC1303
330U_D2_2VM_R9M
2 1 2 1 2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1330
2
1
+
@
PC1324 PC1314 PC1304
1U_0402_6.3V6K
2 1 2 1 2 1
+VCC_CORE
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
@
PC1326 PC1315 PC1305
@ PC1332
2 1 2 1 2 1
330U_D2_2VM_R9M
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
@
PC1325 PC1316 PC1306
4
4
2
1
+
2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M
PC1317 PC1307
+VCC_CORE
2 1 2 1
@ PC1333
22U_0603_6.3V6M 22U_0603_6.3V6M
PC1318 PC1308
330U_D2_2VM_R9M
2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M
@
PC1319 PC1309
2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M
@
PC1320 PC1310
Issued Date
Security Classification
3
3
2
1
2014/02/25
PC942
22U_0603_6.3V6M 2 1 2 1 2 1
1U_0402_6.3V6K
2
1
PC970 PC961
PC947 PC1020 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M
+VGA_CORE
22U_0603_6.3V6M 2 1 2 1 2 1
+VGA_CORE
1U_0402_6.3V6K
2
1
PC968 PC954
PC948 PC1021 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1
1U_0402_6.3V6K
2
1
PC969 PC959
PC949 PC1022 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1
Compal Secret Data
Deciphered Date
1U_0402_6.3V6K
2
1
PC967 PC946
PC951 PC1023 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1
1U_0402_6.3V6K
2
1
PC966 PC940
PC952 PC1024 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1
Near VGA Core
2
2
1U_0402_6.3V6K
2
1
PC943
PC971 PC1025 4.7U_0603_6.3V6M
Under VGA Core
22U_0603_6.3V6M 2 1 2 1
2 1 1U_0402_6.3V6K PC958
2015/02/25
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PC1026 4.7U_0603_6.3V6M
PC963 2 1 2 1
4.7U_0603_6.3V6M
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
2 1 1U_0402_6.3V6K PC944
PC1027 4.7U_0603_6.3V6M
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PC953 2 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
4.7U_0603_6.3V6M
2 1 PC965
4.7U_0603_6.3V6M
Size
Title
Date:
PC964 2 1
Custom
4.7U_0603_6.3V6M
2 1 PC955
4.7U_0603_6.3V6M
PC960
4.7U_0603_6.3V6M
2 1
Document Number
PC962
4.7U_0603_6.3V6M
Tuesday, February 25, 2014
BE_BDW
1
1
Sheet
GB4B-128 package
Compal Electronics, Inc.
56
of
59
PWR-PROCESSOR_DECOUPLING
Rev
1.0
A
B
C
D
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1
for PWR
Item Reason for change PG# Modify List Date Phase
11/15 SIV
1 for panel Vdrop 51 add boost solution
D D
2 11/15 SIV
for EMI request 48 PR319, PC320 change to mount
3 for RF request 54 PR918, PC926, PR933, PC939 change to mount 11/18 SIV
for RF request 55 PC1114, PR1126, PC1106, PR1116 change to mount 11/18 SIV
4
6 battery can't be remove del PR222, PR227, PC204, PR220, PU202, PC206, PR226, PD201, PC205, PR218, 12/30 SIT
47 PR219, PQ201, PQ205, PR228
7 for acoustic noise 55, 56 add PC1135, 1332 12/30 SIT
PR309 is changed from 392K_0402_1% to 124K_0402_1% (SD034124380)
PR312 is changed from 59K_0402_1% to 20K_0402_1% (SD034200280)
8 Add a resistor 249K_0402_1% (SD034249380) between pin 6 of PU301 and PACIN. 12/30 SIT
SIV rework 48
C
PC312 is changed from 2200pF_0402_25V_X7R to 0.01uF_0402_25V_X7R (SE075103K80) C
PQ302 change to AO4447A
PR217 change to 30K
9 SIV rework 47 PR221 change to 110k 12/30 SIT
10 for HW request 50 PR506 change to SD000000680 8.45K 1% 12/30 SIT
PR707 change to 100K +-1%
11 accuracy modify 52 1/20 SVT
PR709 change to 127K +-1%
B B
15
16
17
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Tuesday, February 25, 2014 Sheet 57 of 59
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1 for HW
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase Verify
1 Add 3D Camera function 0.2 23 Add U25,C502~C511. 10/30 SIV SIV Phase
D D
Add R386~R400,R550~R559.
22 Del Q14,R205,C319
Add U13
Remove LPF for woofer amplifier 0.2 27 Change R224->20K,R297->62K
2 Change R1564,R1565->0 ohm,R341->15K, 10/30 SIV Verified by
Change R342->20.5K,R81->200K. SDV rework.
un-stuff C450,C443
3 AC/DC detect issue 0.2 14 Del D1 Verified by
11/03 SIV
31 Add AC_PRESENT_R to U18 pin 19 SDV rework.
4 Change USB power switch Verified by
0.2 30 Change U16,U17->SY6288D20AAC 11/04 SIV
(follow B/E series) SDV rework.
5 Add resistor for 15”/17” K/B co-lay 0.2 31 Add R1001~R1012,R1021~R1032 11/04 SIV SIV Phase
C C
6 Cancel 3D Camera function 0.3 23 Del U25,C502~C508
12/17 SIT SIT Phase
Del R387~R400,R550~R557.
Del R255,R256,R261,R262,L41,L42,D21.
22 Del R204,R386,R558,R559
Verified by
7 TP lock LED function 0.3 31 TP_LOCK_LED# from U18_pin34 to LED 12/24 SIT
SIV rework.
Verified by
8 KB Backight behavior 0.3 32 Add R337,R335,C434,Q23 12/24 SIT
SIV rework.
Verified by
9 Improve VRAM +1.35V 0.3 39 C790 stuff 330uf 12/25 SIT
SIV rework.
Verified by
10 Hole size change for Thermal bracket. 1.0 34 H1,H2,H3,H4,H5,H6 : change to 4.2 mm. 2/5 SVT
SIT rework.
11 ESD reserve 1.0 32 Reserve C479,C480. 2/5 SVT SVT Phase
B B
12
13
14
15
16
17
18
19
A A
20
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR-HW
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-B111P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 25, 2014 Sheet 58 of 59
5 4 3 2 1
5 4 3 2 1
Timing Diagram for G3 or S4-5/M-off (Suspend Well Off) to S0/M0 [non Deep S4/S5 Platform]
+3VLP
T1=NA
EC_ON
D D
T2>100 ms
ON_OFF
T5=110ms T6=100ms
PBTN_OUT#
EC_RSMRST#
T4=110ms
PM_SLP_S5#
PM_SLP_S4#
SYSON T7=0ms
C C
PM_SLP_S3#
T8=20ms
SUSP#
KB_RST# T9=20ms
EC_SCI
VR_ON
T10=100ms
12/11/20
VGATE
B B
PCH_PWROK T11=20ms
SYS_PWROK T12=40ms
H_CPUPWRGD
PM_DRAM_PWRGD
PLT_RST#
A A
Color Command
Signal Names Timing of these signals is set by PCH or processor
Signal Names Timing of these signals should be met by the platform (EC)
Signal Names Timing of these signals is set by IntelR MVP
Voltage rails or chip-to-chip buses Security Classification Compal Secret Data Compal Electronics, Inc.
Signal Names Issued Date 2014/02/25 Deciphered Date 2015/02/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-B111P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 25, 2014 Sheet 59 of 59
5 4 3 2 1
www.s-manuals.com
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