DLD Hardware Project

(Combination Lock)

Submitted to :- Mam Zunairah

Submitted By:-
Syed Najeeb Ali Kazmi (15-EE-63)
Muhammad Huzaifa (15-EE-55)
Taimor Nawaz (15-EE-31)

Electrical Engineering Department

University of Engineering and Technology, Taxila
List of components:-
 Ten 100K ohm resistors
 One 220 ohm resistor
 One 1.5K ohm resistor
 Vero board, LED
 Two capacitors(1 micro Farad,100 micro Farad)
 Three diodes(1N4007,1N4148)
 One pnp transistor(2N3906)
 12V DC supply

Circuit Diagram:-

WORKING OF CIRCUIT:-
This code lock circuit was build around two Dual D Flip Flops IC’s CD4013. The operation of a
single D type Flip flop unit is very important to understand the working principle of the above
circuit. The operation of a D type Flip flop is that any input appearing at the data input D during
present state will appear at pin Q during the positive edge of clock. This operation principle
forms backbone of the above code locker.

In the above circuit Push button switches 5,9,3,1 are used to feed the clock pulse to each D flip
flop, FF1, FF2 ,FF3, FF4.One side of all the push button switches are connected to +12V DC. The
remaining end of push The remaining end of other push button switches are shorted and
connected to the set pins of filp-flops. The relay coil will be activated only if the code is entered
in correct sequence and if there is any variation, the lock will be resetted.

Here the correct code is 5931.When we press 5 the first flip flop(FF1) will be triggered and the
value at the data in (pin9) will be transferred to the Q output (pin13).Since pin 9 is grounded the
value is “0” and so the pin 13 becomes low. For the subsequent pressing of the remaining code
digits in the correct sequence the “0” will reach the Q output (pin1) of the last flip flop
(FF4).This makes the transistor ON and the relay is energized. The positive end of capacitor C2
is connected to the set pin of the filp-flops. When the transistor is switched ON, the capacitor C2
begins to charge and when the voltage across it becomes sufficient the flip-flops are resetted.
This makes the lock open for a fixed amount of time and then it locks automatically. The time
delay can be adjusted by varying the values of R11 and C2.

Conclusion:-
Here we learned the basic principle of D Flip Flop and saw that lock gets opened only when “0”
is fed to the base of pnp transistor which actually then turns “ON”. When wrong key is pressed
then input D is not transferred to Q pin of 2nd D Flip Flop because clock signal is not fed in this
case. But correct key is pressed then clock is also fed to D Flip Flop and hence on positive edge of
clock input D reaches the Q pin of 2nd Flip Flop. When capacitor is fully charged it feeds high
“1”to set pins 6,8 of both IC’s and 9 pin of 1st IC. Due to which high “1” reaches to base of pnp
transistor which then turns off due to which lock is closed.

Problems Faced:-
As we were using Vero board for the first time so building circuit on Vero board after
successfully implementing it on breadboard was bit of difficult, especially while soldering
components.