EE 3CL4, §6

1 / 82
Tim Davidson

Compensators

Lead
compensation
Design via Root
EE3CL4:
Locus
Lead Compensator
example
Introduction to Linear Control Systems
Cascade
compensation
Section 6: Design of Lead and Lag Controllers using
and
steady-state
Root Locus
errors

Lag
Compensation
Design via Root
Tim Davidson
Locus
Lag compensator
example
McMaster University
Prop. vs Lead
vs Lag

Concluding Winter 2018

Insights
EE 3CL4, §6
2 / 82
Tim Davidson Outline
Compensators

Lead 1 Compensators
compensation
Design via Root
Locus
Lead Compensator
2 Lead compensation
example
Design via Root Locus
Cascade
compensation Lead Compensator example
and
steady-state
errors
3 Cascade compensation and steady-state errors
Lag
Compensation
Design via Root
Locus
4 Lag Compensation
Lag compensator
example Design via Root Locus
Prop. vs Lead Lag compensator example
vs Lag

Concluding
Insights 5 Prop. vs Lead vs Lag

6 Concluding Insights
EE 3CL4, §6
4 / 82
Tim Davidson Compensators
Compensators • Early in the course we provided some useful guidelines
Lead regarding the relationships between the pole positions
compensation
Design via Root of a system and certain aspects of its performance
Locus
Lead Compensator
example
• Using root locus techniques, we have seen how the
Cascade pole positions of a closed loop can be adjusted by
compensation
and varying a parameter
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example • What happens if we are unable to obtain that
Prop. vs Lead performance that we want by doing this?
vs Lag
• Ask ourselves whether this is really the performance
Concluding
Insights that we want
• Ask whether we can change the system,
say by buying different components
• seek to compensate for the undesirable aspects of the
process
EE 3CL4, §6
5 / 82
Tim Davidson Cascade compensation
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors • Usually, the plant is a physical process
Lag
Compensation
• If commands and measurements are made electrically,
Design via Root
Locus
compensator is often an electric circuit
Lag compensator
example • General form of the (linear) compensators we will consider is
Prop. vs Lead
Kc M
Q
vs Lag (s + zi )
Gc (s) = Qn i=1
Concluding j=1 (s + pj )
Insights

• Therefore, the cascade compensator adds open loop poles and

open loop zeros
• These will change the shape of the root locus
EE 3CL4, §6
6 / 82
Tim Davidson Compensator design
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
• Where should we put new poles and zeros to achieve desired
steady-state performance?
errors
• That is the art of compensator design
Lag
Compensation
Design via Root
• We will consider first order compensators of the form
Locus
Lag compensator Kc (s + z) K̃c (1 + s/z)
example
Gc (s) = = , where K̃c = Kc z/p
Prop. vs Lead
(s + p) (1 + s/p)
vs Lag

Concluding • with the pole −p in the left half plane

Insights
• and the zero, −z in the left half plane, too
• For reasons that will soon become clear
• when |z| < |p|: phase lead network
• when |z| > |p|: phase lag network
EE 3CL4, §6
8 / 82
Tim Davidson Lead compensation
Compensators

Lead
compensation
Design via Root
Locus
Kc (s + z)
Lead Compensator
example Gc (s) =
Cascade
(s + p)
compensation
and
with |z| < |p|. That is, zero closer to origin than pole
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
Let p = 1/τp and z = 1/(αlead τp ). Since z < p, αlead > 1.
Define K̃c = Kc z/p = Kc /αlead . Then
Kc (s + z) K̃c (1 + αlead τp s)
Gc (s) = =
(s + p) (1 + τp s)
EE 3CL4, §6
9 / 82
Tim Davidson Lead compensation
Kc (s+z) K̃c (1+αlead τp s)
With |z| < |p|, αlead > 1, Gc (s) = (s+p) = (1+τp s)
Compensators

Lead • Frequency response:

compensation
Design via Root
Locus K̃c (1 + jωαlead τp )
Lead Compensator Gc (jω) =
example (1 + jωτp )
Cascade
compensation
and • Bode diagram (in the figure, K1 = K̃c )
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
• Between ω = z and ω = p, |Gc (jω)| ≈ K̃c ωαlead τp
• What kind of operator has a frequency response with
magnitude proportional to ω? Differentiator
• Note that the phase is positive. Hence “phase lead”
EE 3CL4, §6
10 / 82
Tim Davidson A passive phase lead network
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag
V2 (s)
Concluding
Insights
Homework: Show that V1 (s) has the phase lead
characteristic
EE 3CL4, §6
11 / 82
Tim Davidson Active lead and lag networks
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example Here’s an example of an active network architecture.
Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
12 / 82
Tim Davidson Principles of Lead design via
Compensators Root Locus
Lead
compensation • The compensator adds poles and zeros to the P(s) in
Design via Root
Locus
Lead Compensator
the root locus procedure.
example

Cascade
• Hence we can change the shape of the root locus.
compensation
and
steady-state • If we can capture desirable performance in terms of
errors
positions of closed loop poles
Lag
Compensation • then compensator design problem reduces to:
Design via Root
Locus • changing the shape of the root locus so that these
Lag compensator
example desired closed-loop pole positions appear on the root
Prop. vs Lead locus
vs Lag
• finding the gain that places the closed-loop pole
Concluding
Insights positions at their desired positions

• What tools do we have to do this?

• Phase criterion and magnitude criterion, respectively
EE 3CL4, §6
13 / 82
Tim Davidson Root Locus Principles
Compensators • The point s0 is on the root locus of P(s) if 1 + KP(s0 ) = 0.
KG M
Q
Lead (s+zi )
compensation • In first order compensator design with G(s) = Qn i=1
j=1 (s+pj )
Design via Root QM
Locus Kc (s+z) (s+z) Qi=1 (s+zi )
Lead Compensator and Gc (s) = (s+p) , we have P(s) = (s+p) n and
example j=1 (s+pj )

Cascade K = Kc KG . We will restrict attention to the case of K > 0

compensation
and
steady-state
• Phase cond. s0 is on root locus if ∠P(s0 ) = 180◦ + ` 360◦ :
errors
M n
Lag X X
Compensation (angle from −zi to s0 ) − (angle from −pj to s0 )
Design via Root
Locus i=1 j=1
Lag compensator
example
+ (angle from −z to s0 ) − (angle from −p to s0 )
Prop. vs Lead
vs Lag = 180◦ + ` 360◦
Concluding
Insights • Mag. cond. If s0 satisfies phase condition, the gain that puts
a closed-loop pole at s0 is K = 1/|P(s0 )|:
Qn
j=1 (dist from −pj to s0 ) (dist from −p to s0 )
K = QM ×
(dist from −zi to s0 ) (dist from −z to s0 )
i=1
EE 3CL4, §6
14 / 82
Tim Davidson RL design: Basic procedure
Compensators 1 Translate design specifications into desired positions of
Lead dominant poles
compensation
Design via Root 2 Sketch root locus of uncompensated system to see if desired
Locus
Lead Compensator
example
positions can be achieved
Cascade 3 If not, choose the positions of the pole and zero of the
compensation
and compensator so that the desired positions lie on the root
steady-state
errors
locus (phase criterion), if that is possible
Lag 4 Evaluate the gain required to put the poles there
Compensation
Design via Root
(magnitude criterion)
Locus
Lag compensator
example
5 Evaluate the total system gain so that the steady-state error
Prop. vs Lead
constants can be determined
vs Lag
6 If the steady state error constants are not satisfactory, repeat
Concluding
Insights
This procedure enables relatively straightforward design of
systems with specifications in terms of rise time, settling time, and
overshoot; i.e., the transient response.
For systems with steady-state error specifications, Bode (and
Nyquist) methods may be more straightforward (later)
EE 3CL4, §6
15 / 82
Tim Davidson Lead Comp. example
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade 1
compensation Consider a case with G(s) = s(s+2) and H(s) = 1.
and
steady-state Design a lead compensator to achieve:
errors

Lag
• damping coefficient ζ ≈ 0.45 and
Compensation
Design via Root • velocity error constant Kv = lims→0 sGc (s)G(s) ≥ 20
Locus
Lag compensator
example • swift transient response (small settling time)
Prop. vs Lead
vs Lag
What to do?
Concluding
Insights
• Can we achieve this with proportional control?
• If not we will attempt lead control
EE 3CL4, §6
16 / 82
Tim Davidson Attempt prop. control
Compensators

Lead • Closed loop poles that correspond to ζ = 0.45 lie on

compensation
Design via Root
Locus
rays of angle cos−1 (0.45) ≈ 60◦ to neg. real axis
Lead Compensator
example • Sketch them
Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
17 / 82
Tim Davidson Attempt prop. control, II
1
• Add sketch of root locus of s(s+2)
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights

• Is there an intersection? Yes

• What is the value of K = Kamp KG that puts closed-loop
poles at intersection point?
EE 3CL4, §6
18 / 82
Tim Davidson Attempt prop. control, III
Q
Compensators distances from OL poles
• That gain is K = Q
Lead distances from OL zeros
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights

• K = d1 d2 = 5.
• Since KG = 1, Kamp = 5.
EE 3CL4, §6
19 / 82
Tim Davidson Assessing our prop. design
Compensators
• Kamp = 5.
Lead
• Place actual closed loop poles on the root locus (asterisks)
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding • As expected, they are at the target locations (open squares)

Insights
• What is the corresponding Kv ?
• Kv = lims→0 sGc (s)G(s) = Kamp
2
= 2.5 :(
• Do the closed-loop poles have responses that decay quickly?
No, Ts ≈ 4s
EE 3CL4, §6
20 / 82
Tim Davidson Prop. control, step response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
21 / 82
Tim Davidson Lead compensated design
Compensators • Where should the closed-loop poles be? cos−1 (0.45) ≈ 60◦
Lead • Note that the settling time is not specified; it only needs to be
compensation
Design via Root
small. This provides design flexibility.
Locus
Lead Compensator • However, we need a large Kv which will require large gain.
example
Need desired positions far from open loop poles.
Cascade
compensation • Let’s start with desired roots at −4 ± j8 (purple squares)
and √
steady-state • This pair has Ts = 1s and ωn = 42 + 82 ≈ 8.9
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
22 / 82
Tim Davidson How to choose z, p and Kc
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding • Lead design questions:

Insights
• How do we choose z and p to ensure that there exists a
gain that will put closed loop poles at the squares?
• Once we have done that, how do we find the gain that
puts the closed-loop poles at the squares?
EE 3CL4, §6
23 / 82
Tim Davidson How to choose z, p and Kc
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
• We want squares to be on the root locus
example

Prop. vs Lead
• That is, if s0 denotes the position of one of the squares,
vs Lag we want 1 + Gc (s0 )G(s0 ) = 1 + KP(s0 ) = 0
Concluding
Insights • In other words, we want P(s0 ) = −1/K
• Separating that complex-valued equation into magnitude and
phase components, we want
• ∠P(s0 ) = 180◦ ; phase criterion
• |P(s0 )| = 1/K ; magnitude criterion
EE 3CL4, §6
24 / 82
Tim Davidson How to choose z, p and Kc
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead • To find z and p we use the phase criterion

vs Lag
X X
Concluding (angles from OL zeros) − (angles from OL poles) = 180◦
Insights
=⇒ θz − θ0 − θ2 − θp = 180◦
• Then, to find Kc we use the magnitude criterion
Q
distances from OL poles d0 d2 dp
K = Kc KG = Q =
distances from OL zeros dz
EE 3CL4, §6
25 / 82
Tim Davidson How to choose z and p
Compensators • Phase condition equation: θz − θ0 − θ2 − θp = 180◦
Lead • One linear equation, two unknowns. Many solutions
compensation
Design via Root • Simplifying rule of thumb: Place zero on the real axis “underneath”
Locus
Lead Compensator the desired closed-loop pole positions.
example

Cascade
• Reduces the complexity of the design procedure; now we only have
compensation to design the pole position; often a reasonable choice
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
26 / 82
Tim Davidson How to choose p
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead With rule of thumb in place

vs Lag
• Find θp using
Concluding X X
Insights angles from OL zeros − angles from OL poles = 180◦
∼ 90 − (116 + 104 + θp ) = 180
=⇒ θp ≈ 50
• Hence, pole at −p = −4 − 8/ tan(θp ) ≈ −10.86
EE 3CL4, §6
27 / 82
Tim Davidson Checking our work
Compensators

Lead
compensation Does the root locus for the compensated system go through
Design via Root
Locus the desired positions?
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
28 / 82
Tim Davidson How to choose Kc
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator • What is the gain that puts closed-loop poles in the
example

Prop. vs Lead
boxes? Recall
vs Lag
Q
distances from OL poles d0 d2 dp
Concluding K = Kc KG = Q =
Insights distances from OL zeros dz

• In this example KG = 1
d0 d2 dp 8.94(8.25)(10.54)
• Therefore, Kc = dz ≈ 8 ≈ 97.1
EE 3CL4, §6
29 / 82
Tim Davidson Summarizing initial design
97.1(s+4)
Compensators • Our compensator is Gc (s) = (s+10.86)
Lead 97.1(s+4)
compensation
• The compensated open loop is Gc (s)G(s) = s(s+2)(s+10.86)
Design via Root
Locus • Mark all closed-loop poles on the root locus (asterisks)
Lead Compensator
example Note that conjugate pair hit the target (as designed),
Cascade and that the real pole is not far from the (open/closed loop) zero
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights

• Velocity constant: Kv = lims→0 sGc (s)G(s) ≈ 17.9 :(

EE 3CL4, §6
30 / 82
Tim Davidson What to do now?
Compensators
• We tried hard, but did not achieve the design specs
Lead
compensation
Design via Root • Let’s go back and re-examine our choices
Locus
Lead Compensator
example • Zero position of compensator was chosen via rule of thumb
Cascade
compensation • Can we do better?
and
steady-state
Yes, but two parameter design becomes trickier.
errors
• What were other choices that we made?
Lag
Compensation
Design via Root • We chose desired poles to be of magnitude ωn ≈ 8.9
Locus
Lag compensator
example • We could choose them to be further away;
Prop. vs Lead larger gain to get there (and faster transient response)
vs Lag

Concluding • By how much?

Insights
• Show that when desired poles have ωn = 10 as well as the
required ζ ≈ 0.45, then the choice of z ≈ 4.47, p ≈ 12.5 and
KC ≈ 125 results in Kv ≈ 22.3
EE 3CL4, §6
31 / 82
Tim Davidson Root Locus, new lead comp.
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
32 / 82
Tim Davidson Comparisons to prop. design
Compensators

Lead
compensation
Closed-loop pole and zero positions
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
33 / 82
Tim Davidson Comparisons
Compensators Prop.-contr. Lead contr.
Lead 125(s+4.47)
compensation Controller, GC (s) 5 (s+12.5)
Design via Root
Locus
5 125(s+4.47) 1
Lead Compensator
example OL TF, GC (s)G(s) s(s+2) (s+12.5) s(s+2)
Cascade
Y (s) 5 125(s+4.47)
compensation
and
CL TF, R(s) s(s+2)+5 s(s+2)(s+12.5)+125(s+4.47)
steady-state
errors CL poles −1 ± j2 −4.47 ± j8.94, −5.59
Lag
Compensation CL zeros ∞, ∞ −4.47, ∞, ∞
Design via Root
Locus
5 131(1+0.013s) 1.71
Lag compensator
example CL TF, again s2 +2s+5 s2 +8.94s+100
− s+5.59
Prop. vs Lead
vs Lag

Concluding
Insights
• Complex conjugate poles still dominate
• Closed-loop zero at -4.47 (which is also an open-loop
zero) reduces impact of closed-loop pole at -5.59;
residue of that pole in partial fraction expansion is small
EE 3CL4, §6
34 / 82
Tim Davidson New lead comp., ramp response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
35 / 82
Tim Davidson New lead comp., ramp
Compensators response, detail
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
36 / 82
Tim Davidson New lead comp., step response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
Note faster settling time than prop. controlled loop,
However, the CL zero has increased the overshoot a little
Perhaps we should go back and re-design for ζ ≈ 0.40
in order to better control the overshoot
EE 3CL4, §6
37 / 82
Tim Davidson Outcomes
Compensators • Root locus approach to phase lead design was
Lead reasonably successful in terms of putting dominant
compensation
Design via Root poles in desired positions; e.g., in terms of ζ and ωn
Locus
Lead Compensator
example • We did this by positioning the pole and zero of the lead
Cascade
compensation
compensator so as to change the shape of the root
and
steady-state
locus
errors

Lag
• However, root locus approach does not provide
Compensation
Design via Root
independent control over steady-state error constants
Locus
Lag compensator
(details upcoming)
example

Prop. vs Lead • That said, since lead compensators reduce the DC gain
vs Lag
(they resemble differentiators), they are not normally
Concluding
Insights used to control steady-state error.
• The goal of our lag compensator design will be to
increase the steady-state error constants, without
moving the other poles too far
EE 3CL4, §6
39 / 82
Tim Davidson Cascade compensation
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors
• Throughout this lecture, and all the discussion on cascade
Lag
Compensation compensation, we will consider the case in which H(s) = 1.
Design via Root
Locus
Lag compensator
• We will consider first order compensators of the form
example

Prop. vs Lead Kc (s + z)
vs Lag Gc (s) =
(s + p)
Concluding
Insights
with the pole, −p, and the zero, −z, both in the left half plane
• when |z| < |p|: phase lead network
• when |z| > |p|: phase lag network
EE 3CL4, §6
40 / 82
Tim Davidson Steady-state errors
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator If closed loop stable, steady state error for input R(s):
example

Cascade R(s)
compensation ess = lim e(t) = lim s
and t→∞ s→0 1 + GC (s)G(s)
steady-state Q
errors KG i (s+zi ) KC (s+z)
Let G(s) = Q and consider GC (s) =
Lag j (s+pj ) (s+p)
Compensation
Design via Root • Consider the case in which G(s) is a type-0 system.
Locus
Lag compensator
example
• Steady state error due to a step r (t) = Au(t):
Prop. vs Lead ess = 1+KAposn , where
vs Lag Q
Concluding KC z KG i zi
Insights
Kposn = GC (0)G(0) = Q
p j pj

• Note that for a lead compensator, z/p < 1,

• So lead compensation may degrade steady-state error
performance
EE 3CL4, §6
41 / 82
Tim Davidson Steady-state error
Compensators • Now, consider the case
Q in which G(s) is a type-1
Lead KGQ i (s+zi )
compensation system, G(s) = s j (s+pj )
Design via Root
Locus
Lead Compensator • Steady-state error due to a ramp r (t) = At: ess = A/Kv ,
example

Cascade
where the velocity constant is
compensation
and
Q
steady-state KC z KG i zi
errors Kv = lim sGc (s)G(s) = Q
s→0 p j pj
Lag
Compensation
Design via Root
Locus
Lag compensator
example
• Once again, lead compensation may degrade
Prop. vs Lead steady-state error performance
vs Lag

Concluding
Insights • Is there a way to increase the value of these error
constants while leaving the closed loop poles in
essentially the same place as they were in an
uncompensated system? Perhaps |z| > |p|?
EE 3CL4, §6
43 / 82
Tim Davidson Lag compensation
Compensators

Lead
compensation
Design via Root
Locus
Kc (s + z)
Lead Compensator
example Gc (s) =
(s + p)
Cascade
compensation
and
with |z| > |p|. That is, pole closer to origin than zero
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights Let z = 1/τz and p = 1/(αlag τz ). Since z > p, αlag > 1.
Define K̃c = Kc z/p = Kc αlag . Then
Kc (s + z) K̃c (1 + τz s)
Gc (s) = =
(s + p) (1 + αlag τz s)
EE 3CL4, §6
44 / 82
Tim Davidson Frequency response
Compensators
K̃C (1 + jωτz )
Lead
compensation
Gc (jω) =
Design via Root
(1 + jωαlag τz )
Locus
Lead Compensator
example Magnitude
Cascade
compensation
• Low frequency gain: K̃C
and
steady-state • Corner freq. in denominator at ωp = p = 1/(αlag τz )
errors

Lag
• Corner freq. in numerator at ωz = z = 1/τz
Compensation
Design via Root
• ωp < ωz
Locus
Lag compensator
example • High frequency gain: K̃C /αlag = KC
Prop. vs Lead
vs Lag
Phase
Concluding • φ(ω) = atan(ωτz ) − atan(αlag ωτz )
Insights
• At low frequency: φ(ω) = 0
• At high frequency: φ(ω) = 0
√
• In between: negative, with max. lag at ω = zp
EE 3CL4, §6
45 / 82
Tim Davidson Bode Diagram, with K̃c = 1
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights

Note integrative characteristic

EE 3CL4, §6
46 / 82
Tim Davidson A passive phase lag network
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
47 / 82
Tim Davidson Active lead and lag networks
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example Here’s an example of an active network architecture.
Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
48 / 82
Tim Davidson Lag compensator design
• Lag compensator: Gc (s) = Kc s+z
Compensators
s+p . with |z| > |p|.
Lead
compensation • Recall position error constant for compensated type-0
Design via Root
Locus system and velocity error constant for compensated type-1
Lead Compensator
example system:
Cascade Q Q
compensation KC z KG i zi KC z KG i zi
and Kposn = Q , Kv = Q
steady-state p j pj p j pj
errors

Lag where in the latter case the product in the denominator is

Compensation
Design via Root over the non-zero poles.
Locus
Lag compensator
example

Prop. vs Lead
Design Principles
vs Lag
• We don’t try to reshape the uncompensated root locus.
Concluding
Insights
• We just try to increase the value of the desired error constant
by a factor αlag = z/p without moving the poles (well not
much)
• Reshaping was the goal of lead compensator design
EE 3CL4, §6
49 / 82
Tim Davidson Lag compensator design
Compensators

Lead
compensation Design principles:
Design via Root
Locus • Don’t reshape the root locus
Lead Compensator
example
• Adding the open loop pole and zero from the
Cascade
compensation
compensator should only result in a small change to the
and angle criterion for any point on the uncompensated root
steady-state
errors locus
Lag • Angles from compensator pole and zero to any point on
Compensation
Design via Root
the locus must be similar
Locus
Lag compensator
• Pole and zero must be close together
example

Prop. vs Lead • Increase value of error constant:

vs Lag

Concluding
• Want to have a large value for αlag = z/p.
Insights • How can that happen if z and p are close together?
• Only if z and p are both small, i.e., close to the origin
EE 3CL4, §6
50 / 82
Tim Davidson Lag comp. design via Root
Compensators Locus
Lead
compensation
1 Obtain the root locus of uncompensated system
Design via Root
Locus
2 From transient performance specs, locate suitable
Lead Compensator
example dominant pole positions on that locus
Cascade 3 Obtain the loop gain for these points, Kunc = Kamp KG ;
compensation
and hence the (closed-loop) steady-state error constant
steady-state
errors 4 Calculate the necessary increase. Hence αlag = z/p
Lag
Compensation
5 Place pole and zero close to the origin (with respect to
Design via Root
Locus
desired pole positions), with z = αlag p.
Lag compensator
example Typically, choose z and p so that their angles to desired
Prop. vs Lead poles differ by less than 1◦ .
vs Lag
6 Set KC = Kamp
Concluding
Insights
What if there is nothing suitable at step 2?
• Perhaps do lead compensation first,
• then lag compensation on lead compensated plant.
i.e., design a lead-lag compensator
EE 3CL4, §6
51 / 82
Tim Davidson Example
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors 1
Let’s consider, again, the case with G(s) = s(s+2) .
Lag
Compensation Design a lag compensator to achieve damping coefficient
Design via Root
Locus ζ ≈ 0.45 and velocity error constant Kv ≥ 20
Lag compensator
example

Prop. vs Lead
vs Lag
Note: we will get a different closed loop from our lead
Concluding
design.
Insights

First step, obtain uncompensated root locus, and locate

desired dominant pole locations
EE 3CL4, §6
52 / 82
Tim Davidson Uncompensated root locus
In this example, this step is the same as the first step in our
Compensators

Lead
lead design example
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights

• So, yes, it is possible to achieve a damping coefficient

ζ ≈ 0.45 using proportional control
• What is the gain that puts the closed loop poles there?
EE 3CL4, §6
53 / 82
Tim Davidson Finding the gain for prop. control
Q
Compensators distances from OL poles
• That gain is K = Kamp KG = Q
Lead distances from OL zeros
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights

• K = d1 d2 = 5.
• Since KG = 1, Kamp = 5.
EE 3CL4, §6
54 / 82
Tim Davidson Evaluate the velocity error
Compensators constant, and choose z/p
Lead
compensation
Design via Root
Locus
• Velocity error constant of uncompensated loop:
Lead Compensator
example Kv ,unc = lims→0 sGc (s)G(s) = Kamp KG /2
Cascade
compensation • Since KG = 1 and Kamp = 5, Kv ,unc = 2.5
and
steady-state
errors
• In order to obtain Kv ≥ 20, the factor by which we need
Lag
Compensation to increase Kv ,unc by at least 20/2.5 = 8
Design via Root
Locus
Lag compensator
example
• That implies that in the design of our lag controller, we
Prop. vs Lead should choose pole and zero such that z/p ≥ 8,
vs Lag
• where z is chosen to be close to the origin with respect
Concluding
Insights to dominant closed-loop poles, so that the root locus
doesn’t change too much near those dominant
closed-loop poles
EE 3CL4, §6
55 / 82
Tim Davidson Positioning zero and pole
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights

with z/p ≥ 8
EE 3CL4, §6
56 / 82
Tim Davidson Zooming in
Compensators • Try −z = −0.1, along with −p = −1/80.
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag
• Angles from new open-loop zero and open-loop pole to
Concluding
Insights desired closed-loop pole position are pretty close.
• Therefore, their effects will nearly cancel out in phase
criterion at values of s near box
• As a result, compensated root locus should pass close by
the desired positions
EE 3CL4, §6
57 / 82
Tim Davidson Lag compensated root locus
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights

• Yes, indeed, the lag compensated root locus does pass

close by the desired positions
EE 3CL4, §6
58 / 82
Tim Davidson Lag compensated root locus,
Compensators zoomed in
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
59 / 82
Tim Davidson Choosing Kc
Compensators • Choose Kc to be the same as Kamp from the
Lead uncompensated design
compensation
Design via Root
Locus
• That is, Kc = 5
Lead Compensator
example • Plot actual closed loop poles on the locus (asterisks)
Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
60 / 82
Tim Davidson Zoomed in
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
61 / 82
Tim Davidson Comparisons to prop. design
Compensators

Lead
compensation
Closed-loop pole and zero positions
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
62 / 82
Tim Davidson Comparisons
Compensators Prop.-contr. Lag contr.
Lead 5(s+0.1)
compensation Controller, GC (s) 5 (s+1/80)
Design via Root
Locus
5 5(s+0.1) 1
Lead Compensator
example OL TF, GC (s)G(s) s(s+2) (s+1/80) s(s+2)
Cascade
Y (s) 5 5(s+0.1)
compensation CL TF, R(s) s(s+2)+5 s(s+2)(s+1/80)+5(s+0.1)
and
steady-state
errors CL poles −1 ± j2 −0.955 ± j1.979, −0.104
Lag
Compensation CL zeros ∞, ∞ −0.1, ∞, ∞
Design via Root
Locus
Lag compensator 5 4.999(1+7×10−4 s) −0.004
example CL TF, again s2 +2s+5 s2 +1.909s+4.827
+ s+0.104
Prop. vs Lead
vs Lag

Concluding
Insights
• Complex conjugate poles still dominate
• Closed-loop zero at -0.1 (which is also an open-loop
zero) reduces impact of closed-loop pole at -0.104;
residue of that pole in partial fraction expansion is small
EE 3CL4, §6
63 / 82
Tim Davidson Ramp response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
64 / 82
Tim Davidson Ramp response, detail
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
65 / 82
Tim Davidson Step response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights

Note longer settling time of lag controlled loop,

and slight increase in overshoot, due to extra closed-loop
pole-zero pair that do not quite cancel each other out
EE 3CL4, §6
67 / 82
Tim Davidson Prop-Lead-Lag Design
Compensators Comparisons
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and Recall the design example that we have considered for lead and lag
steady-state
errors
designs:
1
Lag For G(s) = s(s+2)
and with H(s) = 1, design a compensator to achieve:
Compensation
Design via Root
Locus
• damping coefficient ζ ≈ 0.45 and
Lag compensator
example • velocity error constant Kv = lims→0 sGc (s)G(s) ≥ 20
Prop. vs Lead
vs Lag
• swift transient response (small settling time)
Concluding
Insights We have done
• Proportional design (blue), which failed to meet specifications
• Lead design (green)
• Lag design (red)
EE 3CL4, §6
68 / 82
Tim Davidson Prop-Lead-Lag Design
Compensators Comparisons
Lead
compensation Closed-loop pole and zero positions
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Prop-Lead-Lag Design
Compensators Comparisons
Lead 1
compensation For given example: G(s) = s(s+2) , ζ ≈ 0.45, Kv ≥ 20.
Design via Root
Locus
Lead Compensator Prop.-contr. Lead contr. Lag contr.
example

125(s+4.47) 5(s+0.1)
Cascade GC (s) 5 (s+12.5) (s+1/80)
compensation
and
steady-state Y (s) 5 131(1+0.013s) 1.71 4.999(1+7×10−4 s) −0.004
R(s) s2 +2s+5 s2 +8.94s+100
− s+5.59 s2 +1.909s+4.827
+ s+0.104
errors

Lag CL poles −1 ± j2 −4.47 ± j8.94, −5.59 −0.955 ± j1.979, −0.104

Compensation
Design via Root
Locus CL zeros ∞, ∞ −4.47, ∞, ∞ −0.1, ∞, ∞
Lag compensator
example
1/Kv 0.4 0.045 0.05
Prop. vs Lead
vs Lag
• Lag design retains similar CL poles to prop. design,
Concluding
Insights plus a “slow” pole
• CL poles of lead design quite different
• Lead and lag meet Kv specification (1/Kv = ess,ramp )
EE 3CL4, §6
70 / 82
Tim Davidson Ramp response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Ramp response, detail
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Step response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Step response, detail
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
74 / 82
Tim Davidson Anything else to consider?
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
75 / 82
Tim Davidson Anything else to consider?
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state With H(s) = 1,
errors

Lag Gc (s)G(s) G(s)

Compensation Y (s) = R(s) + Td (s)
Design via Root
Locus
1 + Gc (s)G(s) 1 + Gc (s)G(s)
Lag compensator
Gc (s)G(s)
example
− N(s)
Prop. vs Lead 1 + Gc (s)G(s)
vs Lag

Concluding
Insights 1 G(s)
E(s) = R(s) − Td (s)
1 + Gc (s)G(s) 1 + Gc (s)G(s)
Gc (s)G(s)
+ N(s)
1 + Gc (s)G(s)
EE 3CL4, §6
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Tim Davidson Response to step disturbance
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Response to step disturbance,
Compensators detail early
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Response to step disturbance,
Compensators detail late
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights

Homework: Show that ess for a step disturbance is 0.2,

0.0225 and 0.025 for prop., lead, lag, respectively
EE 3CL4, §6
79 / 82
Tim Davidson Error due to Gaussian sensor
Compensators noise
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
80 / 82
Tim Davidson Bode diagram of
Compensators GC (s)G(s)/(1 + GC (s)G(s))
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
82 / 82
Tim Davidson Insights
Compensators • If we would like to improve the transient performance of
Lead
compensation
a closed loop
Design via Root
Locus
• We can try to place the dominant closed-loop poles in
Lead Compensator
example
desired positions
Cascade • One approach to doing that is lead compensator design
compensation • However, that typically requires the use of an amplifier
and
steady-state in the compensator, and hence requires a power supply
errors
• Broadening of bandwidth improves transient
Lag
Compensation performance but exposes loop to noise
Design via Root
Locus
Lag compensator
example
• If we would like to improve the steady-state error
Prop. vs Lead
vs Lag
performance of a closed loop without changing the
Concluding
dominant transient features too much
Insights • We can consider designing a lag compensator to
provide the required gain
• However, that typically produces a “weak” slow pole that
slows the decay to steady state