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Vlsi Design PDF
Vlsi Design PDF
Course File
Course file contents
1. Cover Page
2. Syllabus copy
3. Vision of the Department
4. Mission of the Department
5. PEOs and POs
6. Course objectives and outcomes
7. Brief Notes
8. Perquisites, If any
9. Instructional Learning Outcomes
10.Course mapping with PEOs and POs
11.Class Time Table
12.Individual Time Table
13.Lecture Schedule with Methodology being used
14.Detailed notes
15.Additional topics
16.University previous Question papers
17.Question Bank
18.Assignment topics
19.Unit wise bits
20.Tutorial class sheets
21.Known gaps
22.Discussion Topics
23.References, Journals, websites and E-links
24.Quality Control Sheets
a. Course end survey
b. Teaching Evaluation
25.Student List
26. Group-Wise students list for discussion topics
GEETHANJALI COLLEGE OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF Electrical and Electronics Engineering
(Name of the Subject / Lab Course) :VLSI Design
(JNTU CODE -- A60432) Programme : UG
Text Books
Essentials of VLSI circuits and systems – Kamran Eshraghian, Eshraghian
Text-1.
Dougles and A. Pucknell, PHI,2005 Edition.
Principles of CMOS VLSI Design - Weste and Eshraghian, Pearson Education,
Text-2.
1999.
Web Sites
a. www.cmosedu.com
b. www.wikkipedia.com
c. www.btechadda.com
d. www.wikibooks.org
* For the topics Internal & external Circlips, Gaskets and seals (stationary and rotary)
3. Vision of the Department
To impart quality technical education in Electronics and Communication Engineering
emphasizing analysis, design/synthesis and evaluation of hardware/embedded software
using various Electronic Design Automation (EDA) tools with accent on creativity,
innovation and research thereby producing competent engineers who can meet global
challenges with societal commitment.
Course Objectives:
The students should have ability to:
To understand the importance of CPLDs and FPGAs for implementing the variety logic
functions.
Course outcomes:
CO 1: Demonstrate the Fabrication of IC using cadence tools.
CO2: Calculate compute electrical properties of MOS circuits.
CO3: Design various gates, adders, Multipliers and Memories using stick diagrams,
layouts.
CO4: Apply design rules to get Layout of IC.
CO5: Demonstrate semiconductor IC design such as PLA’s, PAL, FPGA, CPLDs.
CO6: Design various forms of memories.
CO7: Implement Subsystems with CMOS Technology.
CO8: Design a Logic Circuit with MOS Transistors.
CO9: Demonstrate VHDL synthesis, simulation, design captures tools, design
verification tools.
CO10: Demonstrate differential strategies for testing of IC’s and CMOS testing.
7. Brief note on Important Topics
Course Outline:
The course outline is as follows:
7. Projects.
8. Prerequisites , If Any
After the completion of the unit the student should be able to:
Develop the Logic Gates and Other complex gates.
Know about Sheet Resistance RS and its concept to MOS.
Get the concept of driving large Capacitive Loads.
Know the Wiring Capacitances.
Understand the concept of Fan-in and fan-out.
UNIT IV: Data Path Subsystems and Array Subsystems
After the completion of the unit the student should be able to:
Know the knowledge of Shifters, Adders.
Develop the ALUs, Multipliers.
Get the knowledge of Parity generators, Comparators.
Design the various counters.
Get the knowledge about Zero/One Detectors.
Get the knowledge about memory architecture.
Understand the concept of static RAM.
Get the knowledge of DRAM.
Know the knowledge of Serial access memory.
After the completion of the unit the student should be able to:
Get the knowledge about PLA and PAL.
Understand the concept of FPGA and its applications.
Get the knowledge about CPLD and its applications.
Know the knowledge about Standard cells.
Get the knowledge of Programmable Array Logic Design Approach.
Understand the needs of testing in VLSI design.
How to apply test principles.
Know the Chip level Test Techniques.
10. Mapping of Course outcomes to Program Outcomes:
1. An ability to apply knowledge of Mathematics, Science, and Engineering to
solve complex engineering problems of Electronics and Communication
Engineering systems.
2. An ability to model, simulate and design Electronics and Communication
Engineering systems, conduct experiments, as well as analyze and interpret
data and prepare a report with conclusions.
3. An ability to design an Electronics and Communication Engineering system,
component, or process to meet desired needs within the realistic constraints
such as economic, environmental, social, political, ethical, health and safety,
manufacturability and sustainability.
4. An ability to function on multidisciplinary teams involving interpersonal
skills.
5. An ability to identify, formulate and solve engineering problems of
multidisciplinary nature.
6. An understanding of professional and ethical responsibilities involved in the
practice of Electronics and Communication Engineering profession.
7. An ability to communicate effectively with a range of audience on complex
engineering problems of multidisciplinary nature both in oral and written
form.
8. The broad education necessary to understand the impact of engineering
solutions in a global, economic, environmental and societal context.
9. A recognition of the need for, and an ability to engage in life-long learning
and acquire the capability for the same.
10. A knowledge of contemporary issues involved in the practice of Electronics
and Communication Engineering profession
11. An ability to use the techniques, skills and modern engineering tools
necessary for engineering practice.
12. An ability to use modern Electronic Design Automation (EDA) tools,
software and electronic equipment to analyze, synthesize and evaluate
Electronics and Communication Engineering systems for multidisciplinary
tasks.
.
Lecture Shedule
Lecture Shedule
Total periods 6
UNIT 1
INTRODUCTION
Integrated circuits were made possible by experimental discoveries which showed that
semiconductor devices could perform the functions of vacuum tubes and by mid-20th-
century technology advancements in semiconductor device fabrication. The integration of
large numbers of tiny transistors into a small chip was an enormous improvement over
the manual assembly of circuits using electronic components. The integrated circuit's
mass production capability, reliability, and building-block approach to circuit design
ensured the rapid adoption of standardized ICs in place of designs using discrete
transistors.
There are two main advantages of ICs over discrete circuits: cost and performance. Cost
is low because the chips, with all their components, are printed as a unit by
photolithography rather than being constructed one transistor at a time. Furthermore,
much less material is used to construct a packaged IC die than a discrete circuit.
Performance is high since the components switch quickly and consume little power
(compared to their discrete counterparts) because the components are small and
positioned close together. As of 2006, chip areas range from a few square millimeters to
around 350 mm2, with up to 1 million transistors per mm
IC Fabrication Process:
An integrated circuit consists of a single crystal chip of
silicon. Containing both active and passive elements, and their interconnection.
The basic structure of an IC consists of four layers of materials, such that:
1.Substrate
2.Epitaxialgrowth
3.Diffusion
4. Metallization
Substrate:
The p-type silicon bottom layer (6 mils thick) and serves where the
Integrated circuit is to be built known as Substrate.
Epitaxial growth:
Diode Fabrication:
Transistor Fabrication:
CMOS:
Fabrication:
MOSFET Fabrication:
Monolithic IC:
Fabrication process:
IC characteristics / Elimination:
polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.9)
p-type body
MOS structure looks like parallel plate capacitor while operating in inversion
– Gate – oxide – channel
Qchannel = CV
C = Cg = eoxWL/tox = CoxWL
V = Vgc – Vt = (Vgs – Vds/2) – Vt
Charge is carried by e-
Carrier velocity v proportional to lateral E-field between source and drain
v = mE m called mobility
E = Vds/L
Time for carrier to cross channel:
t = L /V
Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross
Qchannel
I ds W
= Cox
t
VL
Cox Vgs Vt ds Vds
W
Loff near drain, When Vds
If Vgd < Vt, channel pinches 2 >Vdsat = Vgs – Vt
Now drain voltage no longer increases current
V V
2
gs t
2
0 Vgs Vt cutoff
I V V ds V V V
V
linear
Characteristics of nMOS transistor:
2.5
Vgs = 5
1.5 Vgs = 4
Ids (mA)
1
Vgs = 3
0.5
Vgs = 2
Vgs = 1
0
0 1 2 3 4 5
Vds
The threshold voltage of a MOSFET is usually defined as the gate voltage where an
inversion layer forms at the interface between the insulating layer (oxide) and the
substrate (body) of the transistor. The purpose of the inversion layer's forming is to allow
the flow of electrons through the gate-source junction.
FIGURE OF MERIT:
Inverting Amplifier :
Push-pull inverter
Large signal analysis
VTC and Inversion voltage.
Compare with the earlier VTC.
Small signal analysis
Gain = Vout/Vin= - (gm1+ gm2)/(gds1 + gds2)
Rout = Vout/Iout|Vin=0 1/(gds1 + gds2)
CMOS Inverter analysis :
Inverter Threshold (midpoint, inversion) Voltage(VI) :
point of intersection of VTC and unity gain line.
Trans conductance:
PASS TRANSISTOR:
In electronics, pass transistor logic (PTL) describes several logic families used in the
design of integrated circuits. It reduces the count of transistors used to make different
logic gates, by eliminating redundant transistors. Transistors are used as switches to pass
logic levels between nodes of a circuit, instead of as switches connected directly to
supply voltages. This reduces the number of active devices, but has the disadvantage that
output levels can be no higher than the input level. Each transistor in series has a lower
voltage at its output than at its input. If several devices are chained in series in a logic
path, a conventionally-constructed gate may be required to restore the signal voltage to
the full value. By contrast, conventional CMOS logic always switches transistors to the
power supply rails, so logic voltage levels in a sequential chain do not decrease.
BICMOS INVERTER:
Vdd
Vin T2
T4
Vout
T1
T3
CL
UNIT 2
VLSI CIRCIUT DESIGN PROCESSES
MOS design is aimed at specification into masks for processing silicon to meet the
specification .MOS circuits are formed on four basic layers –n-diffusion, p-diffusion,
polysilicon and metal, which are isolated from one another by thick or thin(thinox)silicon
dioxide insulating layers. The thin oxide (thinox) mask includes n=diffusion, p-diffusion
and transistor channels.
STICK DIAGRAM:
Stick diagrams are used yo convey the information through the use of a color code .the
below table shows the color code
Metal
poly
ndiff
pdiff
• Allow translation of circuits (usually in stick diagram or symbolic form) into actual
geometry in silicon
• Interface between circuit designer and fabrication engineer
• Compromise
– designer - tighter, smaller
– fabricator - controllable, reproducible
Wiring:
The mask layout designs of CMOS NAND and NOR gates follow the general principles
examined earlier for the CMOS inverter layout. Figure 3.7 shows the sample layouts of a
two- input NOR gate and a
two- input NAND gate,
using single-layer
polysilicon and
single- layer meta.
CMOS Layout Design Rules:
The layout designer must follow these rules in order to guarantee a certain yield for the
finished product, i.e., a certain ratio of acceptable chips out of a fabrication batch. A
design which violates some of the layout design rules may still result in a functional chip,
but the yield is expected to be lower because of random process variations.The design
rules below are given in terms of scaleable lambda-rules. Note that while the concept of
scaleable design rules is very convenient for defining a technology-independent mask
layout and for memorizing the basic constraints, most of the rules do not scale linearly,
especially for sub-micron technologies. This fact is illustrated in the right column, where
a representative rule set is given in real micron dimensions. A simple comparison with
the lambda- based rules shows that there are significant differences. Therefore, lambda-
based design rules are simply not useful for sub-micron CMOS technologies.
Logic gate is an idealized or physical device implementing a Boolean function, that is, it
performs a logical operation on one or more logic inputs and produces a single logic
output. Depending on the context, the term may refer to an ideal logic gate, one that has
for instance zero rise time and unlimited fan-out, or it may refer to a non-ideal physical
device.
Switch logic:
Switch logic is based on the pass transistor or on transmission gates. This approach is
fast for small arrays and takes no static current from the supply rails. Thus, power
dissipation of such arrays is small since current inly fows on switching.
Clocked CMOS logic has been used for very low power CMOS and/or for minimizing
hot electron effect problems in N-FET devices .Clocking transistors allow valid logic
output only when clk is high. Clocking transistors may be at output end of logic trees
(maximum performance) or at power supply end of logic trees (maximum protection
from hot electrons)
Pseudo-noms logic:
Using a PMOS transistor simply as a pull-up device for an n-block is called pseudo-
NMOS logic. Note, that this type of logic is no longer ratio-less, i.e., the transistor
widths must be chosen properly, i.e., The pull-up transistor must be chosen wide enough
to conduct a multiple of the n-block's leakage and narrow enough so that the n-block can
still pull down the output safely.
Domino logic is a CMOS-based evolution of the dynamic logic techniques which were
based on either PMOS or NMOS transistors. It allows a rail-to-rail logic swing. It was
developed to speed up circuits.
In Dynamic Logic, a problem arises when cascading one gate to the next. The precharge
"1" state of the first gate may cause the second gate to discharge prematurely, before the
first gate has reached its correct state. This uses up the "precharge" of the second gate,
which cannot be restored until the next clock cycle, so there is no recovery from this
error.
Sheet Resistance:
Layer Rs (Ohm / Sq
Aluminium 0.03
N Diffusion 10 – 50
Silicide 2–4
Polysilicon 15 - 100
2λ
Capacitance:
Standard unit for a technology node is the gate - channel capacitance of the minimum sized
transistor (2λ x 2λ), given as •Cg .This is a ‘technology specific’ value.
Delay Unit:
• Tf ~ 3CL / βVDD
• Τr ~ 3CL / βVDD
• (Derivations for the above are in Pucknell and Eshraghian Pages 105 - 107)
• So, τ r/ τf = βn/βp
• Given that (due to motilities) βn = 2.5 βp, rise time is slower by a factor of 2.5 when
using minimum dimensions of n and p transistors.
Super Buffers:
The symmetry of the conventional inverter is clearly undesirable, and gives rise to significant
delay problems when an inverter is used to drive more significant capacitive loads. Other
NMOS arrangements such as those based on the native transistor, and known as native super
buffers, may be used.
Unit 4:
DATA PATH SUBSYSTEMS
Large systems are composed of sub-systems, known as Leaf-Cell .The most basic leaf cell is
the common logic gate (inverter, and, ..Etc). Structured Design-High regularity-Leaf cells
replicated many times and interconnected to form the system. Logical and systematic
approach to VLSI design is essential.
SHIFTER:
A Shifter is most widely used for arithmetic operations. usually shifting is equivalent to
multiplication by powers of two. Shifting is required during floating-point arithmetic. The
shit register is simplest shifters that can shift by one position per clock cycle.
BARREL SHIFTER:
Barrel shifter produces n output bits and accepts 2n data bits , n control signals . The Barrel
shifter shifts by transmitting a n-bits slice of the 2n data bits to the output.
Adders
The adder is probably the most studied digital circuit. There are a great many ways to
perform binary addition, each with its own area/delay trade-offs. A great many tricks
have been used to speed up addition: encoding, replication of common factors and
precharging are just some of them. The origins of some of these methods are lost in the
mists of antiquity. Since advanced circuits are used in conjunction with advanced logic,
we need to study some higher-level addition methods before covering circuits for
addition.
Serial adder:
Serial adder may require many clock cycles to add two n-bit numbers, but with a very
short cycle time. Usually, they can work on nibbles or on bytes. The most extreme form
of the serial adder is a bit serial adder. When current data bits are the least significant bits
of the addends then a n LSB signal is high.
The addends appear LSB first and can be of arbitrary length the end of a pair of numbers
is signaled by the LSB bit for the next pair.
CARRY SELECT ADDER:
It comprises two versions of the
addition whose carry –ins are
different, then selects the right
one.
ALU:
An ALU is a Arithmetic Logic Unit that requires Arithmetic operations and Boolean
operations. Basically arithmetic operations are addition and subtraction. one may either
multiplex between an adder and a Boolean unit or merge the Boolean unit into the adder as in
tha classic transistor-transistor logic.
MULTIPLIERS:
The above figure shown is booth recoded multiplier. The multiplier is divided into two parts
namely, Both-array and carry propagate adder (CPA). By ascending the 16-bit inputs, the
booth array feeds the result of the multiplier is divided by the floor plan according hierarchy
using an array block and a CPA block.
This array section of multiplier consists of 8 ranks of adders each 17 -bits wide. The
schematic which can be used to represent the first rank and remaining ranks are different. A
Booth decode cell which observes 3-bits of the multiplier(MIER) and procedures the control
signals used in the array adders, can be used by both the above ranks.
A Booth multiplier for multiplying a first number with a second number to produce product
thtat has an array of array cells arranged in a plurality of rows of adder cells and is provided
with input circuitry that reduces the power consumption of the multipliers. This input
circuitry includes a plurality of Booth recoding logic cells that control signals to mulipilexers
in the adder cells in the array. the below example shows the booth recoded multiplier.
0 0 1 0 1 1
0 1 0 0 1 1
0 0 1 0 1 1
0 0 1 0 1 1
0 0 0 0 0 0
0 0 0 0 0 0
0 0 1 0 1 1
0 0 1 1 0 1 0 0 0 1
ARRAY MULTIPLIERS:
Array multipliers is a structure well suited to VLSI implementation .figure shows the
structure of an array multiplier for unsigned numbers. When multiplying the multiplicand and
multiplier by hand, partial products are formed in rows and accumulate in columns, with
partial products shifted by the appropriate amount. In layout, the a bits generally would be
distributed with horizontal wires since each row exactly one a-bits
PARITY GENERATORS:
Parity generators is a function related to binary
addition .Parity generator detects whether the
number of ones in an input word is even or odd. Parity
generator is most widely used to generate the parity
of 16-bits or 32-bit word.
COMPARATOR:
The magnitude of two binary numbers is compared by a magnitude comparator. Basically a
comparator is build with an adder and an inverter.
A<B or A>B may be generated by logical combinations of these signals. Whenever quality
comparisons requires, XNOR gates and AND gates and all that is required.
DYNAMIC RAM:
Dynamic random-access memory (DRAM) is a type of random-access memory that
stores each bit of data in a separate capacitor within an integrated circuit. The capacitor
can be either charged or discharged; these two states are taken to represent the two values
of a bit, conventionally called 0 and 1. Since capacitors leak charge, the information
eventually fades unless the capacitor charge is refreshed periodically. Because of this
refresh requirement, it is a dynamic memory as opposed to SRAM and other static
memory.
STATIC RAM:
Gate-Arrays:
The gate-array is a popular technique used to design IC chips. Like the PLA, it
contains a fixed mesh of unfinished layout that must be customized to yield the
final circuit. Gate-arrays are more powerful, however, because the contents of
the mesh are less structured so the interconnection options are more flexible.
Typical gate-array is built from blocks that contain unconnected transistor pairs, although
any simple component will do. An array of these blocks combined with I/O pads forms a
complete integrated circuit and offers a wide range of digital electronic options (as shown
in above figure). These blocks are internally customized by connecting the components to
form various logical operators such as AND, OR, NOT, and so on. The blocks are also
externally connected to produce the overall chip.
VLSI Design Styles:
Full Custom
ASIC - Application-Specific Integrated Circuit
PLD, FPGA - Programmable Logic
So C - System-on-a-Chip
Full Custom Design Style:
Pre-manufactured components with programmable interconnect wired by CAD tools
Tradeoffs
High Design Costs (huge effort!)
High NRE Cost
High Performance
Low Unit Cost (good for high volume products!)
Examples
Analog and Mixed-Signal
Microprocessor
ASIC Design Style:
Pre-designed (or pre-manufactured) components that are assembled and wired by CAD tools.
Standard cell (pre-designed cells)
Gate array (pre-manufactured cells - just add wiring)
Structured ASIC (complex function customized by wiring)
Tradeoffs
Low Design Cost
High NRE Cost (lower in Gate Array / Structured ASIC)
Medium Unit Cost
Medium Performance
Examples:
Control chip for cell phone
Graphics chips for desktop computers (e.g. nVidia, ATI)
CPLD:
FPGA:
At the beginning of 1980, there were programmable logic devices, which had fast design,
highly configurable and reprogrammable, but they were support only small functions.An
FPGA have bunch of programmable logic blocks in an array with programmable
switches. FPGA s are approximately 10 times less dense.
FPGA has two levels of programmability, each logic block can be programmed
individually to perform simple logic functions and then, switches can be programmed to
implement desire logic function. The key element in programmable logics are 3-input
Look Up Table (LUT), multiplexer and flip-flop. The 3-input LUT is similar to PAL,
used to implement combinational or Boolean equations. FPGA s contain programmable
logic components called "logic blocks", and a hierarchy of reconfigurable interconnects
that allow the blocks to be "wired together"—somewhat like many (changeable) logic
gates that can be inter-wired in (many) different configurations. Logic blocks can be
configured to perform complex combinational functions, or merely simple logic gates
like AND and XOR. In most FPGA s, the logic blocks also include memory elements,
which may be simple flip-flops or more complete blocks of memory.
PAL -
bc
ac
ab
abc
abc
abc
abc
a b c
s cout
Standard cell:
In semiconductor design, standard cell methodology is a method of designing
application-specific integrated circuits (ASICs) with mostly digital-logic features.
Standard cell methodology is an example of design abstraction, whereby a low-level
very-large-scale integration (VLSI) layout is encapsulated into an abstract logic
representation (such as a NAND gate). Cell-based methodology (the general class to
which standard cells belong) makes it possible for one designer to focus on the high-level
(logical function) aspect of digital design, while another designer focuses on the
implementation (physical) aspect. Along with semiconductor manufacturing advances,
standard cell methodology has helped designers scale ASICs from comparatively simple
single-function ICs (of several thousand gates), to complex multi-million gate system-on-
a-chip (SoC) devices.
2-input NAND or NOR function is sufficient to form any arbitrary boolean function set.
But in modern ASIC design, standard cell methodology is practiced with a sizeable
library (or libraries) of cells. The library usually contains multiple implementations of the
same logic function, differing in area and speed. This variety enhances the efficiency of
automated synthesis, place and route (SPR) tools. Indirectly, it also gives the designer
greater freedom to perform implementation tradeoffs (area vs. speed vs. power
consumption.) A complete group of standard cell descriptions is commonly called a
technology library.
IC Design Steps:
Specifications
High-level Functional
Description Description
HLS
Placed
& Routed Gate-level Logic
Design Design Description
DESIGN STEPS:
Step 1: Prepare an Requirement Specification
Step 4: Functional verification all the IP's/Check whether the RTL is free from Linting
Errors/Analyze whether the RTL is Synthesis friendly.
Step 4a: Perform Cycle-based verification (Functional) to verify the protocol behaviour
of the RTL
Step 4b: Perform Property Checking , to verify the RTL implementation and the
specification understanding is matching.
Step 6: To Perform Synthesis for the IP, the inputs to the tool are (library file(for which
synthesis needs to be targeted for, which has the functional/timing information available
for the standard-cell library and the wire-load models for the wires based on the fan-out
length of the connectivity), RTL files and the Design Constraint files, So that the
Synthesis tool can perform the synthesis of the RTL files and map and optimize to meet
the design-constraints requirements. After performing synthesis, as a part of the synthesis
flow, need to build scan-chain connectivity based on the DFT(Design for Test)
requirement, the synthesis tool (Test-compiler), builds the scan-chain.
Step 7a: Perform the Netlist-level Power Analysis, to know whether the design is meeting
the power targets.
Step 7b: Perform Gate-level Simulation with the Synthesized Netlist to check whether the
design is meeting the functional requirements.
Step 7c: Perform Formal-verification between RTL vs Synthesized Netlist to confirm that
the synthesis Tool has not altered the functionality.
Step 7d: Perform STA (Static Timing Analysis) with the SDF(Standard Delay Format)
file and synthesized netlist file, to check whether the Design is meeting the timing-
requirements.
Step 7e: Perform Scan-Tracin , in the DFT tool, to check whether the scan-chain is built
based on the DFT requirement.
Step 9: The next step is the Floor-planning, which means placing the IP's based on the
connectivity,placing the memories, Create the Pad-ring, placing the
Pads(Signal/power/transfer-cells(to switch voltage domains/Corner pads(proper
accessibility for Package routing), meeting the SSN requirements(Simultaneous
Switching Noise) that when the high-speed bus is switching that it doesn't create any
noise related activities, creating an optimized floor plan, where the design meets the
utilization targets of the chip.
Step 9a : Release the floor-planned information to the package team, to perform the
package feasibility analysis for the pad-ring .
Step 9b: To the placement tool, rows are cut, blockages are created where the tool is
prevented from placing the cells, then the physical placement of the cells is performed
based on the timing/area requirements. The power-grid is built to meet the power-target
of the Chip.
Step 10: The next step is to perform the Routing, at first the Global routing and Detailed
routing, meeting the DRC (Design Rule Check) requirement as per the fabrication
requirement.
Step 11: After performing Routing then the routed Verilog netlist, standard-cells
LEF/DEF file is taken to the Extraction tool (to extract the parasitics(RLC) values of the
chip in the SPEF format(Standard parasitics Exchange Format), and the SPEF file is
generated.
Step 12a: Perform the Routed Netlist-level Power Analysis, to know whether the design
has met the power targets.
Step 12b: Perform Gate-level Simulation with the routed Netlist to check whether the
design is meeting the functional requirement.
Step 12c: Perform Formal-verification between RTL vs. routed Netlist to confirm that the
place & route Tool has not altered the functionality.
Step 12d: Perform STA (Static Timing Analysis) with the SPEF file and routed net list
file, to check whether the Design is meeting the timing-requirements.
Step 12e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain is
built based on the DFT requirement, Perform the Fault-coverage with the DFT tool and
Generate the ATPG test-vectors.
Step 12h: Perform LVS(layout vs. Spice) check, a part of the verification which takes a
routed net list converts to spice (call it SPICE-R) and convert the Synthesized net list(call
it SPICE-S) and compare that the two are matching.
Step 12i : Perform the ERC(Electrical Rule Checking) check, to know that the design is
meeting the ERC requirement.
Step 12j: Perform the ESD Check, so that the proper back-to-back diodes are placed and
proper guarding is there in case if we have both analog and digital portions in our Chip.
We have separate Power and Grounds for both Digital and Analog Portions, to reduce the
Substrate-noise.
Step 12k: Perform separate STA(Static Timing Analysis) , to verify that the Signal-
integrity of our Chip. To perform this to the STA tool, the routed net list and SPEF
file(parasitic including coupling capacitances values), are fed to the tool. This check is
important as the signal-integrity effect can cause cross-talk delay and cross-talk noise
effects, and hinder in the functionality/timing aspects of the design.
Step 12l: Perform IR Drop analysis that the Power-grid is so robust enough to with-stand
the static and dynamic power-drops with in the design and the IR-drop is with-in the
target limits.
Step 13: Once the routed design is verified for the design constraints, then now the next
step is chip-finishing activities (like metal-slotting, placing de-coupling caps).
Step 14: Now the Chip Design is ready to go to the Fabrication unit, release files which
the fab can understand, GDS file.
Step 15: After the GDS file is released , perform the LAPO check so that the database
released to the fab is correct.
Step 16: Perform the Package wire-bonding, which connects the chip to the Package.
CMOS TESTING
Testing is one of the most expensive parts of chips
– Logic verification accounts for > 50% of design effort for many chips
– Debug time after fabrication has enormous opportunity cost
– Shipping defective parts can sink a company
NEED FOR TESTING:
The need of testing is to find out errors in the
application.
The good reasons of testing are
1) Quality Assurance.
2) Verification and validating the product/application
before it goes live in the market.
3) Defect free and user friendly.
4) Meets the requirements.
Logic Verification:
Manufacturing Test:
A speck of dust on a wafer is sufficient to kill chip
Yield of any chip is < 100%
– Must test chips after manufacturing before delivery to customers to only
ship good parts
Manufacturing testers are
very expensive
– Minimize time on tester
– Careful selection of test vectors
Manufacturing test ideally would check every node in the circuit to prove it is not
stuck.
Apply the smallest sequence of test vectors necessary to prove each node is not
stuck.
Good observability and controllability reduces number of test vectors required for
manufacturing test.
– Reduces the cost of testing
– Motivates design-for-test.
If each register could be observed and controlled, test problem reduces to testing
combinational logic between registers.
Better yet, logic blocks could enter test mode where they generate test patterns
and report the results automatically.
Scan:
Convert each flip-flop to a scan register CLK
– Only costs one extra multiplexer
Normal mode: flip-flops behave as usual SCAN
Scan mode: flip-flops behave as shift register
Flop
SI
Contents of flops can be scanned out and new values scanned in. Q
D
scan-in
Flop
Flop
Flop
Flop
Flop
Flop
Logic Logic
inputs Cloud Cloud outputs
Flop
Flop
Flop
Flop
Flop
Flop
scanout
Built-in Self-test:
CLK
Q[0] Q[1] Q[2]
Flop
Flop
Flop
D D D
BILBO:
Built-in Logic Block Observer
– Combine scan with PRSG & signature analysis.
C[0]
C[1]
Q[2] / SO
Flop
Flop
Flop
SI 1
0 Q[0]
Q[1]
Chips with internal scan chains can access the chains through boundary scan for
unified test strategy.
PackageInterconnect
CHIP B CHIP C
CHIP A CHIP D
2. Principles of CMOS VLSI Design – Weste and Eshraghian, Pearson Education, 1999.
2. Introduction to VLSI Circuits and Systems – John .P. Uyemura, John Wiley,
2003.
4. Modern VLSI Design – Wayne Wolf, Pearson Education, 3rd Edition, 1997.
6. Explain about power distribution and clock distribution of routing procedure. [16]
4. Explain about power distribution and clock distribution of routing procedure. [16]
SET-2
IV B.TECH – I SEM EXAMINATIONS, NOVEMBER - 2010
VLSI SYSTEMS DESIGN
(COMMON TO CSE, IT, CSS, ECC)
Time: 3hours Max.Marks:80
Answer any FIVE questions
All questions carry equal marks
---
1. a) Explain the path-delay measurement of combinational logic circuits.
b) Explain the design principles of pipelining. [8+8]
2. Explain about power distribution and clock distribution of routing procedure. [16]
SET-3
IV B.TECH – I SEM EXAMINATIONS, NOVEMBER - 2010
VLSI SYSTEMS DESIGN
(COMMON TO CSE, IT, CSS, ECC)
Time: 3hours Max.Marks:80
Answer any FIVE questions
All questions carry equal marks
---
1. Explain any one routing algorithm with suitable example. [16]
8. Explain about power distribution and clock distribution of routing procedure. [16]
*****
SET-4
17. Question Bank
UNIT 1
1. With neat sketch explain how NPN transistors are fabricated in bipolar process.
2. Write in detail about integrated passive components.
3. Compare CMOS and Bipolar technologies.
4. Explain about following two oxidation methods.
a. High pressure Oxidation
b. Plasma oxidation.
5. Clearly explain various diffusion effects in silicon with emphasis on VLSI
6. application.
7. Explain the following,
a. Thermal oxidation technique
b. Kinetics of thermal oxidation.
8. With neat sketch explain the Ion-lithography process.
9. Explain how diodes and resistor are fabricated in Bipolar process.
10. Explain the NMOS fabrication procedure.
11. Explain CMOS fabrication using n-well process.
12. With neat sketch explain how resistor and capacitor are fabricated in p-well
process.
13. Explain how resistors and diodes are fabricated in CMOS process.
14. Explain in detail the IC fabrication steps. What is the size of silicon wafer used
for manufacturing state-of-the art VLSI ICs.
15. What are the different VLSI technologies available compare their speed/power
performance?
16. Draw the cross sectional view of CMOS p-well process.
17. With neat sketch explain BICMOS fabrication in an n-well process.
18. What is lithography? Explain.
19. Clearly explain about ION-IMPLANTATION step in IC fabrication.
UNIT 2
1. What is stick diagram and explain about different symbols used for components in
Stick diagram
2. Discuss in detail the NMOS design style.
3. Design a stick diagram for NMOS EX-OR gate.
4. Discuss CMOS design style. Compare with NMOS design style.
5. What are the effects of scaling on Vt?
6. Explain about layers in integrated circuits.
7. Why is VLSI design process presented in NMOS only?
8. Design a stick diagram for the CMOS logic shown y = (AB+CD).
9. What are design rules?
10. Explain lambda based design rules, contact cuts and double metal process rules.
UNIT 3
1. Explain the requirement and operation of pass transistor and transmission gates.
2. Explain clocked CMOS logic, domino logic and n-p CMOS logic.
3. Explain constructional features and performance characteristics of pseudo NMOS logic
4. Define the following
a) Sheet resistance concept applied to MOS transistor and inverters.
b) Standard unit of capacitance.
5. Describe the following briefly,
a) Cascaded inverters as drivers
b) Super buffers
c) BICMOS drivers.
6. What do you mean by inverter delay? Explain.
7. What is the problem of driving large capacitive loads? Explain a method to drive such
load.
8. Describe three source of wiring capacitance.
9. Define fan-in and fan-out. Explain their effects on propagation delay.
10. Explain rise time and fall-time and their characteristics
UNIT 4
UNIT 5
1.Draw the typical architecture of PAL and explain the operation of it.
Implement JK flip-flop using PROM.
2Write briefly about channel-less gate arrays with neat sketches.
3Write about channeled gate arrays.
4What are advantages and disadvantages of the reconfiguration?
5Explain any one chip architecture that used the anti fuse and give its advantages.
6Draw and explain the FPGA chip architecture.
7Clearly explain each step of high level design flow of an ASIC.
8What is CPLD? Draw its basic structure and give its applications.
9Implement 2-bit comparator using PROM.
10.Draw the typical standard cell structure showing regular power cell and explain.
11.What are the characteristics of 22v10PAL CMOS device and draw its I/O structure.
12. Explain the methods of programming of PAL CMOS device.
13. Explain the function of 4:1 multiplexer in PAL CMOS device with the help of I/O
pads.
14.With a neat sketch clearly explain the architecture of a PLA.
15. Explain in detail the need for testing and the two groups of testing.
16. What are the reasons of malfunctioning of chip? What are the different levels of
testing?
17. What is meant by short circuit and open circuit faults?
18. Draw the basic structure of parallel scan and explain how it reduces the long scan
chains.
19. What is ATPG? Explain a method of generation of test vector.
20. Explain in detail the concurrent fault simulation
21. Explain the self-test technique ‘Signature Analysis and BILBO’.
22. How IDDQ testing is used to test the bridge faults?
23. What is the design for autonomous test and what is the basic device used in this?
24. Explain the gate level and function level of testing.
25. What type of testing technique are suitable for the following,
a. Memories
b. Random logic
c. Data path.
26. What is boundary scan test? Explain.
27. Draw the state diagram of TAP controller and explain how it provides the
control signals for test data and instruction register.
28. What type of faults can be reduced by improving layout design?
29. A sequential circuit with ‘n’ inputs and ‘m’ storage devices. To test this circuit
how many test vectors are required?
18. ASSIGNMENT TOPICS
UNIT 1:
WEEK 1:
1. Fabrication process.
2. PMOS fabrication.
3. CMOS fabrication.
WEEK 2:
UNIT 2:
WEEK 3:
1. IDS-VDS relation
2. Various pull-ups
3. CMOS inverter analysis.
WEEK 4:
UNIT 3:
WEEK 5:
1. Stick diagram
2. Scaling of MOS circuit
3. NMOS and CMOS contacts.
WEEK 6:
UNIT 4:
WEEK 7:
1. Switch logic
2. Driving large capacitance
3. Sheet resistance
WEEK 8:
UNIT 5:
WEEK 9:
1. Shifters.
2. ALU
3. Counters.
WEEK 10:
1. Adders.
2. Multiplier’s.
3. Comparators.
UNIT-6:
WEEK 11:
1. CPLD.
2. FPGA
3. Programmable array logic
WEEK 12:
1. Standard cell.
2. Programmable array logic.
3. PLA’S
UNIT 7:
WEEK 13:
WEEK 14:
1. VHDL synthesis.
2. Simulation.
3. Layout design.
UNIT 8:
WEEK 15:
1. Chip-level test
2. System –level test
3. CMOS testing.
WEEK 16:
OBJECTIVE (FIRST-MID)
17. The source and drain n-diffusion regions form junctions with the
18. In NMOS inverter, the enhancement mode device is called
19. The deficiency of MOS technology lies in the driving capabilities of MOS
20. For modern NMOS technology gate material is
KEY:
1. a
2. c
3. a
4. c
5. b
6. d
7. d
8. a
9. d
10. Heavily doped n type polysilicon.
11. Mosi2
12. Saturation velocity.
13. Pass transistor or transmission gate.
14. Transition
15. Stick diagram
16. n-diffusion or p-diffusion
17. n-p CMOS logic.
18. p-substrate or p-well
19. Pull-down transistor.
20. Limited load
3. Explain FPGA and their advantages? Also compare CPLD and FPGA?
OBJECTIVE (MID-II)
KEY:
1. B
2. B
3. C
4. D
5. D
6. A
7. D
8. D
9. A
10. A
11. Reset
12. BILBO
13. Probe
14. Layout
15. Memories
16. System level testing
17. Manufacturing test
18. Function
19. Full serial scan or parallel scan
20. Placement and routing.
OBJECTIVE
KEY
1. C
2. C
3. D
4. D
5. D
6. C
7. D
8. C
9. C
10. B
11. Level of Integration
12. THRESHOLD VOLTAGE
13. tsd = L2 / μVDS
14. Diffusion Capacitance
15. Figure of Merit
16. Transmission
17. Nmos, pmos
18. Pass
19. Transmission
20. Intrinsic capacitance, overlap capacitance
20.Tutorial Problems
UNIT 1
INTRODUCTION
Integrated circuits were made possible by experimental discoveries which showed that
semiconductor devices could perform the functions of vacuum tubes and by mid-20th-
century technology advancements in semiconductor device fabrication. The integration of
large numbers of tiny transistors into a small chip was an enormous improvement over
the manual assembly of circuits using electronic components. The integrated circuit's
mass production capability, reliability, and building-block approach to circuit design
ensured the rapid adoption of standardized ICs in place of designs using discrete
transistors.
There are two main advantages of ICs over discrete circuits: cost and performance. Cost
is low because the chips, with all their components, are printed as a unit by
photolithography rather than being constructed one transistor at a time. Furthermore,
much less material is used to construct a packaged IC die than a discrete circuit.
Performance is high since the components switch quickly and consume little power
(compared to their discrete counterparts) because the components are small and
positioned close together. As of 2006, chip areas range from a few square millimeters to
around 350 mm2, with up to 1 million transistors per mm
IC Fabrication Process:
An integrated circuit consists of a single crystal chip of
silicon. Containing both active and passive elements, and their interconnection.
The basic structure of an IC consists of four layers of materials, such that:
1.Substrate
2.Epitaxialgrowth
3.Diffusion
4. Metallization
Substrate:
The p-type silicon bottom layer (6 mils thick) and serves where the
Integrated circuit is to be built known as Substrate.
Epitaxial growth:
Metallization:
Finally a fourth material (aluminum) Layer is added to supply the necessary
interconnection between components. It provided contact among the components Al is
used for metallization.
Diode Fabrication:
Transistor Fabrication:
UNIT 2
BASIC ELECTRICAL PROPERTIES
The MOS transistor evolves from the use of a voltage on the gate to induce a charge in
the channel between source and drain, which may then be caused to move from source to
drain under the influence of an electric field created by voltage Vds applied between
drain and source. Since the charge induced is dependent on the gate to source voltage
then Ids is dependent on both Vgs and Vds.
polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.9)
p-type body
MOS structure looks like parallel plate capacitor while operating in inversion
– Gate – oxide – channel
Qchannel = CV
C = Cg = eoxWL/tox = CoxWL
V = Vgc – Vt = (Vgs – Vds/2) – Vt
Charge is carried by e-
Carrier velocity v proportional to lateral E-field between source and drain
v = mE m called mobility
E = Vds/L
Time for carrier to cross channel:
t = L /V
Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross
W
= Cox
L
If Vgd < Vt, channel pinches off near drain, When Vds > Vdsat = Vgs – Vt
Now drain voltage no longer increases current
I ds
V
Vgs Vt dsat 2 Vdsat
V
2
gs Vt
2
0 Vgs Vt cutoff
I ds Vgs Vt ds Vds Vds Vdsat
V
linear
2
t
2
V gs V Vds Vdsat saturation
2
2.5
Vgs = 5
1.5 Vgs = 4
Ids (mA)
1
Vgs = 3
0.5
Vgs = 2
Vgs = 1
0
0 1 2 3 4 5
Vds
The threshold voltage of a MOSFET is usually defined as the gate voltage where an
inversion layer forms at the interface between the insulating layer (oxide) and the
substrate (body) of the transistor. The purpose of the inversion layer's forming is to allow
the flow of electrons through the gate-source junction.
UNIT 3
VLSI CIRCIUT DESIGN PROCESSES
MOS design is aimed at specification into masks for processing silicon to meet the
specification .MOS circuits are formed on four basic layers –n-diffusion, p-diffusion,
polysilicon and metal, which are isolated from one another by thick or thin(thinox)silicon
dioxide insulating layers. The thin oxide (thinox) mask includes n=diffusion, p-diffusion
and transistor channels.
STICK DIAGRAM:
Stick diagrams are used to convey the information through the use of a color code .the
below table shows the color code
• Allow translation of circuits (usually in stick diagram or symbolic form) into actual
geometry in silicon
• Interface between circuit designer and fabrication engineer
• Compromise
– designer - tighter, smaller
– fabricator - controllable, reproducible
Wiring:
The mask layout designs of CMOS NAND and NOR gates follow the general principles
examined earlier for the CMOS inverter layout. Figure 3.7 shows the sample layouts of a
two- input NOR gate and a two-input NAND gate, using single-layer polysilicon and
single-layer meta.
The layout designer must follow these rules in order to guarantee a certain yield for the
finished product, i.e., a certain ratio of acceptable chips out of a fabrication batch. A
design which violates some of the layout design rules may still result in a functional chip,
but the yield is expected to be lower because of random process variations. The design
rules below are given in terms of scaleable lambda-rules. Note that while the concept of
scaleable design rules is very convenient for defining a technology-independent mask
layout and for memorizing the basic constraints, most of the rules do not scale linearly,
UNIT 4
Clocked CMOS logic has been used for very low power CMOS and/or for minimizing
hot electron effect problems in N-FET devices .Clocking transistors allow valid logic
output only when clk is high. Clocking transistors may be at output end of logic trees
(maximum performance) or at power supply end of logic trees (maximum protection
from hot electrons)
Pseudo-nmos logic:
Using a PMOS transistor simply as a pull-up device for an n-block is called pseudo-
NMOS logic. A.3 Note, that this type of logic is no longer ratio-less, i.e., the transistor
widths must be chosen properly, i.e., The pull-up transistor must be chosen wide enough
to conduct a multiple of the n-block's leakage and narrow enough so that the n-block can
still pull down the output safely.
UNIT 5
SUBSYSTEM DESIGN
Large systems are composed of sub-systems, known as Leaf-Cell .The most basic leaf cell is
the common logic gate (inverter, nand, ..Etc). Structured Design-High regularity-Leaf cells
replicated many times and interconnected to form the system. Logical and systematic
approach to VLSI design is essential.
SHIFTER:
A Shifter is most widely used for arithmetic operations. usually shifting is equivalent to
multiplication by powers of two. Shifting is required during floating-point arithmetic. The
shit register is simplest shifters that can shift by one position per clock cycle.
BARREL SHIFTER:
Barrel shifter produces n output bits and accepts 2n data bits , n control signals . The Barrel
shifter shifts by transmitting a n-bits slice of the 2n data bits to the output.
Adders:
The adder is probably the most studied digital circuit. There are a great many ways to
perform binary addition, each with its own area/delay trade-offs. A great many tricks
have been used to speed up addition: encoding, replication of common factors, and
precharging are just some of them. The origins of some of these methods are lost in the
mists of antiquity. Since advanced circuits are used in conjunction with advanced logic,
we need to study some higher-level addition methods before covering circuits for
addition.
Serial adder:
Serial adder may require many clock cycles to add two n-bit numbers, but with a very
short cycle time. Usually, they can work on nibbles or on bytes. The most extreme form
of the serial adder is a bit serial adder. When current data bits are the least significant bits
of the addends then a n LSB signal is high.
The addends appear LSB first and can be of arbitrary length the end of a pair of numbers
is signaled by the LSB bit for the next pair.
CARRY SELECT ADDER:
It comprises two versions of the addition whose carry –ins are different, then selects the right
one.
ALU:
An ALU is a Arithmetic Logic Unit that requires Arithmetic operations and Boolean
operations. Basically arithmetic operations are addition and subtraction. one may either
multiplex between an adder and a Boolean unit or merge the Boolean unit into the adder as in
the classic transistor-transistor logic.
MULTIPLIERS:
The multiplier is divided into two parts namely, Both-array and carry propagate adder (CPA).
By ascending the 16-bit inputs, the booth array feeds the result of the multiplier is divided by
the floor plan according hierarchy using an array block and a CPA block.
UNIT 6
Gate-Arrays:
The gate-array is a popular technique used to design IC chips. Like the PLA, it
contains a fixed mesh of unfinished layout that must be customized to yield the
final circuit. Gate-arrays are more powerful, however, because the contents of
the mesh is less structured so the interconnection options are more flexible.
Typical gate-array is built from blocks that contain unconnected transistor pairs, although
any simple component will do. An array of these blocks combined with I/O pads forms a
complete integrated circuit and offers a wide range of digital electronic options (as shown
in above figure). These blocks are internally customized by connecting the components to
form various logical operators such as AND, OR, NOT, and so on. The blocks are also
externally connected to produce the overall chip.
VLSI Design Styles:
Full Custom
ASIC - Application-Specific Integrated Circuit
PLD, FPGA - Programmable Logic
So C - System-on-a-Chip
DESIGN STEPS:
Step 4b: Perform Property Checking , to verify the RTL implementation and the
specification understanding is matching.
Step 6: To Perform Synthesis for the IP, the inputs to the tool are (library file(for which
synthesis needs to be targeted for, which has the functional/timing information available
for the standard-cell library and the wire-load models for the wires based on the fanout
length of the connectivity), RTL files and the Design Constraint files, So that the
Synthesis tool can perform the synthesis of the RTL files and map and optimize to meet
the design-constraints requirements. After performing synthesis, as a part of the synthesis
flow, need to build scan-chain connectivity based on the DFT(Design for Test)
requirement, the synthesis tool (Test-compiler), builds the scan-chain.
UNIT 8
CMOS TESTING
Logic Verification:
Manufacturing Test:
A speck of dust on a wafer is sufficient to kill chip
Yield of any chip is < 100%
– Must test chips after manufacturing before delivery to customers to only
ship good parts
Manufacturing testers are
very expensive
– Minimize time on tester
– Careful selection of test vectors
Manufacturing test ideally would check every node in the circuit to prove it is not
stuck.
Apply the smallest sequence of test vectors necessary to prove each node is not
stuck.
Good observability and controllability reduces number of test vectors required for
manufacturing test.
– Reduces the cost of testing
– Motivates design-for-test.
If each register could be observed and controlled, test problem reduces to testing
combinational logic between registers.
Better yet, logic blocks could enter test mode where they generate test patterns
and report the results automatically.
Scan:
CLK
Convert each flip-flop to a scan register SCAN
Flop
SI Q
D
21. Known Gaps, If any
None
WEEK 1:
1. Fabrication process.
2. PMOS fabrication.
3. CMOS fabrication.
WEEK 2:
UNIT 2:
WEEK 3:
4. IDS-VDS relation
5. Various pull-ups
6. CMOS inverter analysis.
WEEK 4:
UNIT 3:
WEEK 5:
4. Stick diagram
5. Scaling of MOS circuit
6. NMOS and CMOS contacts.
WEEK 6:
4. Design rules and layout.
5. Scaling of MOS circuits
6. To design CMOS nand gate.
UNIT 4:
WEEK 7:
4. Switch logic
5. Driving large capacitance
6. Sheet resistance
WEEK 8:
UNIT 5:
WEEK 9:
4. Shifters.
5. ALU
6. Counters.
WEEK 10:
4. Adders.
5. Multiplier’s.
6. Comparators.
UNIT-6:
WEEK 11:
4. CPLD.
5. FPGA
6. Programmable array logic
WEEK 12:
4. Standard cell.
5. Programmable array logic.
6. PLA’S
UNIT 7:
WEEK 13:
WEEK 14:
4. VHDL synthesis.
5. Simulation.
6. Layout design.
UNIT 8:
WEEK 15:
4. Chip-level test
5. System –level test
6. CMOS testing.
WEEK 16:
Text Books
Essentials of VLSI circuits and systems – Kamran Eshraghian, Eshraghian
Text-1.
Dougles and A. Pucknell, PHI,2005 Edition.
Principles of CMOS VLSI Design - Weste and Eshraghian, Pearson Education,
Text-2.
1999.
Suggested / Reference Books
Modern VLSI Design - Wayne Wolf, Pearson Education, 3rd Edition, 1997.
Ref-1.
Web Sites
a. www.cmosedu.com
b. www.wikkipedia.com
c. www.btechadda.com
d. www.wikibooks.org
* For the topics Internal & external Circlips, Gaskets and seals (stationary and rotary)
24. Quality Control Sheets
b. Teaching Evaluation
Hard Copy
25.Students List
END