The Superscalar Architecture

(part 2)
Limitation of superscalar machine
Fundamental limitations to parallelism
• True data dependency
• Procedural dependency
• Resource conflicts
• Output dependency
• Antidependency
Pipelining hazards
• RESOURCE HAZARDS A resource hazard occurs when two (or more)
instructions that are already in the pipeline need the same resource. The
result is that the instructions must be executed in serial rather than parallel
for a portion of the pipeline.
• DATA HAZARDS A data hazard occurs when there is a conflict in the access
of an operand location. In general terms, we can state the hazard in this
form: Two instructions in a program are to be executed in sequence and
both access a particular memory or register operand.
• CONTROL HAZARDS A control hazard, also known as a branch hazard,
occurs when the pipeline makes the wrong decision on a branch prediction
and therefore brings instructions into the pipeline that must subsequently
be discarded.
Three types of data hazards
• Read after write (RAW), or true dependency: An instruction modifies
a register or memory location and a succeeding instruction reads the
data in that memory or register location.A hazard occurs if the read
takes place before the write operation is complete.
• Write after read (RAW), or antidependency: An instruction reads a
register or memory location and a succeeding instruction writes to
the location. A hazard occurs if the write operation completes before
the read operation takes place.
• Write after write (RAW), or output dependency: Two instructions
both write to the same location. A hazard occurs if the write
operations take place in the reverse order of the intended sequence.
Superscalar Instruction Issue and
Completion Policies
Assume a superscalar machine:
• capable of fetching and decoding two instructions at a time
• having three separate functional units (e.g., two integer arithmetic
and one floating-point arithmetic), and
• having two instances of the write-back pipeline stage.
• Instructions:
IN-ORDER ISSUE WITH IN-ORDER COMPLETION
IN-ORDER ISSUE WITH OUT-OF-ORDER COMPLETION
OUT-OF-ORDER ISSUE WITH OUT-OF-ORDER COMPLETION
Exercise
Exercise 1

Exercise 2
Exercise 1

WAW
WAR
RAW
*The instrutions on the answer are example of each
dependencies. There are some more actually.
Exercise 2
 Consider a superscalar computer. The processor can issue
Exercise 3 two instructions per cycle if there is no resource conflict and
no data dependence problem.There are essentially two
pipelines, with four processing stages (fetch, decode,
execute, and store). Each pipeline has its own fetch decode
and store unit.
Four functional units (multiplier, adder, logic unit, and load
unit) are available for use in the execute stage and are
shared by the two pipelines on a dynamic basis.The two
store units can be dynamically used by the two pipelines,
depending on availability at a particular cycle.There is a
lookahead window with its own fetch and decoding logic.
This window is used for instruction lookahead for out-of-order
instruction issue

a) Show the pipeline activity for this program on the processor using in-order issue with in-order completion poli
b) Repeat for in-order issue with out-of-order completion.
c) Repeat for out-of-order issue with out-of-order completion.
a)

b)

c)