Digital Electronics: A Practical Approach With VHDL

Online Instructor’s Resource Manual
to accompany
DIGITAL ELECTRONICS
A Practical Approach with VHDL
Ninth Edition
William Kleitz
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ISBN13:
ISBN10: 0-13-216463-9
A01_KLEI7369_08_IRM_FM.qxd 6/25/11 8:43 AM Page 1
Solutions and Answers to

In-text Problems
Chapter 1 1–7. (a) B916 (b) DC16 (c) 7416 (d) FB16
(e) C616
1–1. (a) 610 (b) 1110 (c) 910 (d) 710
(e) 1210 (f) 7510 (g) 5510 (h) 18110 1–8. (a) 1100 01012 (b) 1111 10102
(i) 16710 (j) 11810 (c) 1101 01102 (d) 1010 1001 01002
(e) 0110 00102
1–2. (a) 1011 10102 (b) 1101 01102
(c) 0001 10112 (d) 1111 10112 1–9. (a) 13410 (b) 24410 (c) 14610
(e) 1001 00102 (d) 17110 (e) 96510
1–3. (a) 318 (b) 358 (c) 1348 (d) 1318 1–10. (a) 7F16 (b) 4416 (c) 6B16 (d) 3D16
(e) 1558 (e) 1D16
1–4. (a) 100 1102 (b) 111 1002 (c) 110 0012 1–11. (a) 9810 (b) 6910 (c) 7410 (d) 3610
(d) 011 0102 (e) 101 1112 (e) 8110
1–5. (a) 2310 (b) 3110 (c) 1210 (d) 5810 1–12. (a) 1000 0111BCD (b) 0001 0100 0010BCD
(e) 4110 (c) 1001 0100BCD (d) 0110 0001BCD
(e) 0100 0100BCD
1–6. (a) 1768 (b) 618 (c) 1278 (d) 1368
(e) 1548
1–13. Decimal Binary Octal BCD Hexadecimal
(a) 35 0010 0011 043 0011 0101 23
(b) 41 0010 1001 051 0100 0001 29
(c) 43 0010 1011 053 0100 0011 2B
(d) 78 0100 1110 116 0111 1000 4E
(e) 58 0011 1010 072 0101 1000 3A
1–14. Decimal Binary Octal BCD Hexadecimal
(a) 68 0100 0100 104 0110 1000 44
(b) 98 0110 0010 142 1001 1000 62
(c) 87 0101 0111 127 1000 0111 57
(d) 52 0011 0100 064 0101 0010 34
(e) 45 0010 1101 055 0100 0101 2D
1
1–15. (a) 010 0101 (b) C

p
(b) 0100100 0110001 0110100
S0 LSB MSB
(c) 1001110 0101101 0110110
(d) 1000011 1010000 1010101
(e) 1010000 1100111 P 20 0 tserial = 4 µs
a 21 0
1–16. (a) 25 (b) 243134 (c) 4E2D36 r tparallel = 0.5 µs (500 ns)
(d) 435055 (e) 5067 a 22 1
1–17. (a) Tank A, temperature high; tank C, l 23 1

l
pressure high 24 1
e
(b) Tank D, temperature and pressure high l 25 1
(c) Tanks B and D, pressure high 26 1
(d) Tanks B and C, temperature high 27 0

(e) Tank C, temperature and pressure high 2–3. (a) 8 * 11>3.7 MHz2 = 2.16 ms
1–18. 0001 0010 0000BCD (b) 1.21 ms occurs during the 5th period
1–19. (a) sku43 (b) 534B55343316 which is LOW.
1–20. (a) 68HC11EMFN, C3 (b) 27C64, A8 2–4. (a) 3 * 11>8 MHz2 = 0.375 ms
(c) 2N3904, F4 (d) DB9, E1 (b) 6 * 11>4.17 MHz2 = 1.44 ms
1–21. 16-MAR 1995 Revision A 2–5.
1–22. (a) 2 (b) 2 (c) 4 (d) 1 Cp
E1–1. (a) 0000 0101 (b) Eleven (c) 0E (d) 27
Vout1 4V
E1–2. (a) 40 0V
(b) 55 4V
Vout2
(c) Tank B pressure and temperature are 0V
HIGH. 8V
(d) All pressures are HIGH. Vout3 4V
2–6. D1 = REV D8 = REV

Chapter 2 D2 = FOR D9 = REV
2–1. (a) tp = 1>2 MHz = 0.5 ms D3 = FOR D10 = REV
(b) tp = 1>500 kHz = 2 ms D4 = REV D11 = REV
(c) tp = 1>4.27 MHz = 0.234 ms D5 = FOR D12 = REV
(d) tp = 1>17 MHz = 58.8 ns D6 = REV D13 = REV
(e) f = 1>2 ms = 500 kHz D7 = FOR
(f) f = 1>100 ms = 10 kHz 2–7. V1 = 0 V V5 = 4.3 V
(g) f = 1>0.75 ms = 1.33 kHz V2 = 4.3 V V6 = 5.0 V
(h) f = 1>1.5 ms = 0.667 MHz V3 = 4.3 V V7 = 0 V
2–2. (a) V4 = 0.7 V
Cp 2–8. That diode will conduct, lowering V6 to
S0 MSB
0.7 V (“AND”).
LSB
2–9. That diode will conduct, raising V7 to 4.3 V
P 20
1 (“OR”).
a tserial = 4 µs
21 1
r 2–10. Vout1 L 0 V, Vout2 L 5 V
a tparallel = 0.5 µs (500 ns)
22 0 2–11.
l
0 5V
l 23
Cp
e 24 0 0V
l 3.85 V
25 Vout
1 0V
26
1
2–12. Input signal to BASE (B); output signal from
27 0
COLLECTOR (C).
2 SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS

2–13. The transistor is cutoff; Chapter 3

Vout = 5 V * 1M Æ>1330 Æ + 1 MÆ2
Vout = 4.998 V 3–1. (a) A B C X
2–14. Vout is lowered with a smaller load resistor; 0 0 0 0
Vout = 5 V * 470 Æ>1330 Æ + 470 Æ2 0 0 1 0
Vout = 2.94 V 0 1 0 0
2–15. Because, when the transistor is turned on 0 1 1 0
(saturated), the collector current will be 1 0 0 0
excessive (IC = 5 V>RC). 1 0 1 0
1 1 0 0
2–16. IC = 5 V>100 Æ = 50 mA 1 1 1 1
2–17. The totem-pole output replaces RC with a (b) A B C D X
transistor that acts like a variable resistor.
The transistor prevents excessive collector 0 0 0 0 0
current when it is cut off and provides a 0 0 0 1 0
high-level output when turned on. 0 0 1 0 0
2–18. 0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
2–19. (a) 8.0 MHz 1 0 0 0 0
(b) 125 ns 1 0 0 1 0
1 0 1 0 0
2–20. (a) 9.8304 MHz
1 0 1 1 0
(b) 101.73 ns 1 1 0 0 0
2–21. P3 parallel, P2 serial 1 1 0 1 0
2–22. reverse 1 1 1 0 0
1 1 1 1 1
2–23. A HIGH on pin 2 will turn Q1 on, making 8
RESET_B approximately zero. 3–2. 2 = 256
E2–1. (a) Let 3–3. (a) The output is HIGH whenever all
inputs are HIGH; otherwise, the output
(b) 24
is LOW.
E2–2. (a) Sit (b) The output is HIGH whenever any input
(b) 3 is HIGH; otherwise, the output is LOW.
E2–3. (a) Cp = 5V>0V, Vout3 = 0V>5V 3–4. W = 0, X = 1, Y = 0, Z = 0
inverse of each other 3–5. X = ABC
(b) Cp = 5V>0V, Vout3 = 0V>8V X = ABCD
(c) Cp and Vout3 are in phase. X = A + B + C
E2–4. (a) Cp = 5V>0V, Vout3 = 10V>6V, 3–6. W = 1, X = 0, Y = 1, Z = 1
in phase
(b) Cp = 5V>0V, Vout3 = 10V>8V
(c) it would be inverted. 3–7.
E2–5. (a) V1 = 4.3V, V2 = 0V, V3 = 4.3V, A
V4 = 0.7V
B
(b) V1 = 0V, V2 = 4.3V, V3 = 0V,
V4 = 5.0V (Both diodes are reverse biased.)
X
E2–6. (a) Cp = 5V>0V, Vout = 0V>5V, inverse
of each other
(b) Cp = 5V>0V, Vout = 0V>8V A
SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS 3

3–8. 3–12.
3–13.
Clock 1 2 3 4 5 6 7 8
Enable
3–14. Four
3–15.
3–9. Clock VCC 14 + Power
1
OSC
– supply
A
Enable
B signal
C
Receive
device
X
7 GND 8
7432
A
3–16. Four
B
3–17. Two
C
3–18. HIGH, LOW, and FLOAT
X 3–19. To provide pulses to a digital circuit for
troubleshooting purposes.
3–10. 3–20. LOW, to enable the output to change with
pulser (if gate is good).
3–21. HIGH, to enable the output to change with
pulser (if gate is good).
3–22. Pin 3 should be flashing; the AND gate is bad.
3–23. Pin 2 should be ON; the Enable switch is
bad, or bad Enable connection.
3–24. Pin 3 should be flashing and pin 7 should
be OFF. There is a bad ground connection
to pin 7.
3–25. X = A, X = 0
3–11. 3–26. X = A, Z = A, X = 1, Z = 0
A 3–27.
B
A
X
X
Z
A
B

3–28. X = AB, Y = CD 3–35.

A B X C D Y A
0 0 1 0 0 1
B
0 1 1 0 1 1
1 0 1 1 0 1 C
1 1 0 1 1 0
3–29. W = 1 X
X = 1
Y = 1
Z = 0 D
3–30.
E
F
Y
3–36.
3–31. W = 1
X = 0
Y = 0
Z = 0
3–32.
3–37.
1 7
U
V #8
#1
W HIGH
X LOW
3–33. It disables the other two inputs when it is 4 6
DOWN for the NAND and UP for the NOR. Y
3–34. X = A + B + C Y = D + E + F #6 #7 #8
Z
A B C X D E F Y
3–38. (a) AC (b) CD (c) ACD (d) CP A B
0 0 0 1 0 0 0 1 (e) AC (f) CP AB
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0 3–39. U = CP AB W = BC
0 1 1 0 0 1 1 0 V = CD X = CP CD
1 0 0 0 1 0 0 0 3–40.
1 0 1 0 1 0 1 0
1 1 0 0 1 1 0 0
1 1 1 0 1 1 1 0

3–41. E3–5. (a) Vcc

(b) Logic pulser
(c) Logic probe
(d) Ground
(e) Vcc
E3–6. (a) None
(b) Gate 3
(c) Gates 1 and 4
E3–7. (a) X = 0, Y = 0
(b) X = 1, Y = 1
(c) A B X A B Y
3–42. LOW; to see inverted output pulses (otherwise, 0 0 1 0 0 1
output would always be LOW). 0 1 1 0 1 0
3–43. HIGH; to see inverted output pulses 1 0 1 1 0 0
(otherwise, output would always be HIGH). 1 1 0 1 1 0
3–44. Pins 4 and 10 should be HIGH. The inverters E3–8. (a) NOR
connected to those pins are bad. (b) NAND
3–45. There is no problem. E3–9. (a) Yes
(b) X = AB
3–46. The inverter is not working. (c) 6mS
3–47. With all inputs HIGH, pin 8 should be LOW. E3–10. (a) T1 = 6mS, T2 = 10mS,
Next try making each of the 8 inputs LOW, one T2 - T1 = 4mS
at a time, while checking for a HIGH at pin 8. (b) Two
3–48. Pins 8 and 12 should be LOW. The NORs (c) 1mS
connected to those pins are bad. E3–11. (a) NAND
3–49. AND - 74HC08; U3:A = location C2, (b) NOR
U3:B location D2 OR 74HC32; E3–12. (a) OR
location B7 (b) NAND
3–50. (a) flashing (b) HIGH E3–13. (a) X = C¿, D¿, Cp
3–51. pin 20 LOW (GND), pin 40 HIGH (5) (b) Y = BD¿
3–52. Because they are all part of one IC package. E3–14. (a) U1b, U1c, are bad
3–53. Place probe “A” on the input of the inverter (b) U2c, U2d are bad
(WATCHDOG_CLK). Using the same E3–15. (a) U1b, U1c, U1d are bad
settings for probe “B” as “A,” place probe (b) U2a, U2c are bad
“B” on the output of U4:A. “B” should be E3–16. (a) U1a, U1c are bad
the complement of “A.” (b) U2c, U2d are bad
3–54. all HIGH E3–17. (a) U1b, U1c are bad
3–55. OE_B (b) U2a, U2d are bad
E3–1. (a) X = 1, Y = 1
(b) X = 0, Y = 0 Chapter 4
(c) A B X A B Y
4–1. The 7400-series uses hard-wired logic. The
0 0 0 0 0 0 designer must use a different IC for each
0 1 0 0 1 1 logic function. Programmable logic contains
1 0 0 1 0 1 thousands of logic gates that can be custom-
1 1 1 1 1 1 configured by the designer to perform any
E3–2. (a) AND logic desired.
(b) OR 4–2. Schematic capture using a CAD system or
E3–3. (a) Up a Hardware Description Language like
(b) Down VHDL.
E3–4. Up 1¿1¿2 4–3. Hardware Description Language

4–4. (1) Define the problem, (2) develop the 4–20. (a) Library declares which VHDL library
equations, (3) enter the design, (4) simulate to use.
the I/O conditions, (5) program the PLD, (b) Entity defines the input/output ports.
(6) test the PLD with actual I/O.
(c) Architecture defines the logic expressions.
4–5. (a) 3, (b) 5
4–21. ENTITY and3 IS
4–6. A small indented circle PORT(
4–7. They receive programming information from A, B, C: IN bit;
a PC and program the on-board FPGA that
X :OUT bit);
can then be tested with actual I/O signals.
END and3;
4–8. (a) 3
4–22. ARCHITECTURE arc OF and3 IS
(b) 2
BEGIN
(c) 3
X6 =1A AND B AND C2;
4–9. The PLA provides programmable OR gates
END arc;
for combining the product terms.
4–23.
4–10.
(a) A
X
B
C
(b)
A
B Y
(c)
B
4–11. So that it won’t lose its programmed logic
design when power is removed. C Z
4–12. (a) 2500 usable gates, 128 macrocells
A
(b) 2400 usable gates, 108 macrocells
4–13. The look-up table method Chapter 5
4–14. Inputs Output 5–1. W = 1A + B21C + D2
A B X X = AB + BC
0 0 1 Y = 1AB + B2C
0 1 0 Z = 1AB + B + 1B + C22D
1 0 1
1 1 0 5–2. (a) R = CPF
4–15. They must be re-programmed. (b) G = CP1M + F2
4–16. Schematic entry using a CAD system and (c) B = F1H + C + P2
VHDL entry using a text editor. 5–3.
4–17. It translates the information from the design (a) A
entry stage into a binary file that is later B
M
used to program the CPLD. C
4–18. It defines the IC pin as an input or output D
and connects it to the internal CPLD (b) A
circuitry. B
4–19. Text C
N
D

(c) 5–4.
A
P
B
C
(d) A
B
Q
C
D
(e) A
B
R
C
D
5–5. (a) Commutative law (b) Associative law
(f) A
(c) Distributive law
5–6. M = O S = 0
B N = 1 T = A
C P = AB U = 1
S
Q = C + D V = A
D
R = A W = A
A B C D M N Q R S 5–7.
0 0 0 0 0 0 0 0 0 W = 1A + B2BC A NC
B
0 0 0 1 1 0 0 1 1 W = BC C
W
X = 1A + B21B + C2
0 0 1 0 1 0 0 0 0 A
0 0 1 1 1 1 0 1 1 C
X = B + AC X
0 1 0 0 0 0 0 0 0 B
Y = A + 1A + B2BC
0 1 0 1 1 1 0 1 1 A
0 1 1 0 1 0 0 1 1 B Y
Y = A + BC
0 1 1 1 1 1 1 1 1 C
1 0 0 0 0 0 0 0 0 Z = AB + B + BC A NC
1 0 0 1 1 1 0 1 1 Z = B B Z
1 0 1 0 1 0 0 0 1 C NC
1 0 1 1 1 1 0 1 1
1 1 0 0 1 0 0 0 1 5–8.
1 1 0 1 1 1 0 1 1 X = 1A + B21B + C2 + B + C
1 1 1 0 1 0 0 1 1 X = B + C
1 1 1 1 1 1 1 1 1 Y = 1A + B21B + C2A
A B C P Y = A1B + C2
0 0 0 0
0 0 1 0 Z = AB + AB1B + C2
0 1 0 0 Z = AB
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

5–9. A B C D X Z C D W
A 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 0
C V 0 0 1 0 0 0 1 0 0
0 0 1 1 1 1 1 1 1
D A 0 1 0 0 0 0
D
0 1 0 1 0 0
V
C 0 1 1 0 1 0
V = C(A+D) 0 1 1 1 1 1
1 0 0 0 0 0
B
1 0 0 1 1 0
1 0 1 0 0 0
C 1 0 1 1 1 1
D
W 1 1 0 0 1 0
B NC 1 1 0 1 1 0
C
D W 1 1 1 0 1 1
1 1 1 1 1 1
W = CD
A 5–11. X = 1A + B21D + C2
B
5–12. Y = B1AC + D2
C X
D
A
C
X
B
D
X = (A+C)(B+D)
A
A
C
B
Y
Y
B 5–13. Break the long bar and change the AND to
C
Y = (A+C)B an OR, or the OR to an AND.
A 5–14. (a) NAND (b) NOR
A
B 5–15. Y and Z are both ORs.
B
C C Z
D
Z 5–16. A + B = A B = AB
D
E
5–17.
NC
E B
Z = ABC + CD A
A W W = A+B
B
5–10. C NC
C
A C D V A B C Y A
B
0 0 0 0 0 0 0 0 B
X X = B+C
0 0 1 0 0 0 1 0 C
C A NC
0 1 0 0 0 1 0 0
0 1 1 1 0 1 1 1 A NC
1 0 0 0 1 0 0 0 A B NC
Y
1 0 1 0 1 0 1 0 B
C C Y=C
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1
A
A
B Z B Z = ABC
C
C

5–18. (a) X = AB + (B + C) 5–21.

X = 0 A
B
(b) Y = A + BBC
C
Y = 1 D
5–19.
5–22.
A
B
C
D W 5–23.
A
A B
B W
C C
D D
W = A+B+C+D
5–24.
A
B
X=1
C X
A
B
C
5–25.
D (23) A
Y ABCD>11
(22) B
Y = DA+DB+DC+AB+AC+BC (21) C NC
(20) D NC
A
5–26.
B
D
C
Y
5–27.
A B C W X A B C D Y Z
0 0 0 0 1 0 0 0 0 1 1
0 0 1 1 1 0 0 0 1 1 1
A
0 1 0 1 1 0 0 1 0 1 1
C Z
0 1 1 1 0 0 0 1 1 0 1
D
1 0 0 1 0 0 1 0 0 0 0
C
A Z 1 0 1 1 1 0 1 0 1 1 0
D 1 1 0 0 1 0 1 1 0 1 1
Z = C+AD 1 1 1 0 0 0 1 1 1 1 1
1A + B2 + BC + BCD
1 0 0 0 0 1
5–20. (a) X = 1 0 0 1 1 1
X = ABC + BD + CD 1 0 1 0 0 1
(b) Y = AB + ABC – 1B + C2 1 0 1 1 0 0
Y = 1 1 1 0 0 0 0
1 1 0 1 1 0
1 1 1 0 0 1
1 1 1 1 1 0

5–28. (b)
A
X
B
CANCEL
C
(c)
A
B X
5–29. 5–34.
(a)
(b)
(c)
(d)
5–30.
5–31.
(a) X=A
A
(b) X=A
A
5–32.
5–33.
(a)
5–35. u. SOP x. SOP
A v. POS y. POS
B X w. POS z. POS, SOP
C

5–36. 5–44. The output (pin 8) would be stuck high.

5–45. WATCHDOG - EN – Qa
5–46. WATCHDOG–EN – Qa + Qb
5–47. (a) pin 6 = P1.0 + A15 (b) AND
(c) quad 2 input AND
(d) RD is LOW or WR is LOW
5–48. Pin 20 of U10 goes LOW if RESET and A15
are both LOW.
E5–1. (a) B = KD + HD
(b) B = D1K + H2
E5–2. (a) Seven
5–37. X = A + BC (b) X = AB + CD
Y = B + AC E5–3. (a) 5
Z = AC + AB + A B C (b) X = BC + A
5–38. W = B C + B D + A B E5–4. (a) X = 1A + B21B + C2 + 1B + C2
X = C D + B D + ABCD (b) Six
Y = AB + AD + BCD (c) X = B + C
Z = C + BD + A D E5–5. (a) 2
5–39. (a) X = CD + AC + B (b) X = BC
(b) Y = 1 (c)
5–40. B
X
C
E5–6. (a) Ten

(b) X = ABD + CD
(c)
E5–7. X = AB¿C¿ + A¿BC¿ + AB¿C

E5–8. X = A¿BC¿ + AB¿C + A¿BC + ABC
5–41.
E5–9. (a) 2
(b) X = B¿C¿
E5–10. (a) X = 11A + B2¿1B + C22¿
A
(b) 7
(c) X = A + C¿ + B
B X
E5–11. (a) 6
(TO LOWER- (b) X = B¿ + C¿
LEFT (c)
C SEGMENT)
B
X
D 74LS54 AOI C
E5–12. (a) 11
X = ACD + BCD where A = MSB
(b) X = A¿B¿ + A¿D¿ + B¿D¿ + BC
5–42. Pin 6 should be ON; bad gate.
5–43. The IC checks out OK. The problem is that
pin 9 should be connected to pin 10 (not 9 to
GND).

(c)
E5–13. (a) AND Chapter 6

(b) OR
6–1. (a) Exclusive-OR produces a HIGH output
E5–14. for one or the other input HIGH, but not both.
(b) Exclusive-NOR produces a HIGH output
for both inputs HIGH or both inputs LOW.
6–2. (a) An OR outputs a HIGH for both inputs
HIGH.
(b) An AND outputs a LOW for both inputs
LOW.
E5–15.
6–3.
A
E5–16. B
X ex-OR
Y ex-NOR
E5–17. (a) U1b is bad (b) U1a is bad 6–4. W = AB – A + B = AB + A B (ex-NOR)

E5–18. (a) U1a is bad (b) U1b is bad X = AB + A + B = AB + A B (ex-NOR)
E5–19. (a) U2b is bad (b) U3a is bad Y = AB – AB = AB + AB (ex-OR)
E5–20. (a) U2b is bad (b) U1b is bad
Z = AB + A + B = AB (neither)
E5–21. (a) U1a is bad (b) U2a is bad
6–5.
E5–22. (a) U3a is bad (b) U2a is bad “AND”
E5–23. (a) 3
(b) Gate 2 A
(c)
ex-O R
A
X B
B
E5–24. (a) X = (A¿B¿)¿

(b) X = A + B
(c) No
(d) Yes, Gate 1

6–6. 6–12. Odd

6–13.
5-Bit
TRANSMISSION
CABLE
D0 D0 R
S E
E C
N E
D I
I D3 D3 V
N I
6–7. X = (AB + A B) + AB = AB G N
G
Y = AB + AB – AB = 1
6–8. X = ABBC + AB BC
X = ABC + ABC I0 I0
7 Σ
Y = AB + C AB + AB + C AB 4 E
2 ΣE ‘1’ = ERROR
Y = C + AB 8 ‘0’ = OK
0
6–9. A7 = 1010 0111 0 I8
I8
4C = 0100 1100 0
79 = 0111 1001 0 6–14.
F3 = 1111 0011 1
00 = 0000 0000 1
FF = 1111 1111 1
6–10.
6–15. Yes; LOW

6–16.
6–11.
24 23 22 21 20 23 22 21 20 24
VCC
EVEN
GND
7486
EVEN

6–17. 7–5. +15 0000 1111 -1 1111 1111

X0 +14 0000 1110 -2 1111 1110
A8 +13 0000 1101 -3 1111 1101
A12
+12 0000 1100 -4 1111 1100
X1
A9
+11 0000 1011 -5 1111 1011
A13 X4 +10 0000 1010 -6 1111 1010
X2 P3. 4 +9 0000 1001 -7 1111 1001
A10 +8 0000 1000 -8 1111 1000
A14
+7 0000 0111 -9 1111 0111
X3 +6 0000 0110 -10 1111 0110
A11
A15 +5 0000 0101 -11 1111 0101
+4 0000 0100 -12 1111 0100
E6–1. (a) X = 0, Y = 1
+3 0000 0011 -13 1111 0011
(b) X = 0, Y = 1
+2 0000 0010 -14 1111 0010
(c) A B X A B Y
+1 0000 0001 -15 1111 0001
0 0 0 0 0 1 0 0000 0000
0 1 1 0 1 0
1 0 1 1 0 0 7–6. (a) 7 = 0000 0111
1 1 0 1 1 1 (b) -7 = 1111 1001
(c) 14 = 0000 1110
E6–2. (a) ex-OR (b) ex-NOR (d) 36 = 0010 0100
E6–3. (a) Yes, because it is an Ex-OR. (e) -36 = 1101 1100
(b) Second gate from top. (f) 66 = 0100 0010
E6–4. X = 1A¿B + AB¿2C (g) -48 = 1101 0000
E6–5. X = 1A¿B + AB¿2BC = A¿BC (h) 112 = 0111 0000
(i) -112 = 1001 0000
E6–6. X = A¿B¿ + A¿C¿ + ABC (j) -125 = 1000 0011
E6–7. Because they both have an odd number of 7–7. (a) 0001 0110 = +22
ones (b) 0000 1111 = +15
E6–8. (a) Matching hex digits (c) 0101 1100 = +92
(b) NOR (d) 1000 0110 = -122
(e) 1110 1110 = -18
Chapter 7 (f) 1000 0001 = -127
7–1. (a) 1001 (b) 1111 (c) 1 1100 (g) 0111 1111 = +127
(d) 100 0010 (e) 1100 1000 (h) 1111 1111 = -1
(f) 10010 0010 (g) 10100 1111 7–8. 28 - 1 - 1 to -28 - 1 = 127 to -128
(h) 10110 0000 216 - 1 - 1 to -216 - 1 = 32,767 to -32,768
7–2. (a) 0000 1011 (b) 0000 1011 7–9. (a) 0000 1100
(c) 0011 0000 (d) 0010 0011 (b) 0000 0110
(e) 0011 1110 (f) 0001 1001 (c) 0011 0010
(g) 00110001 (h) 0000 0111 (d) 0000 1110
7–3. (a) 1 0101 (b) 10 1010 (c) 11 1100 (e) 0000 1010
(d) 1 0001 0001 (e) 1 1110 1100 0011 (f) 0011 1011
(f) 111 0111 0001 (g) 1 1001 0011 (g) 1111 0100
(h) 111 1110 1000 0001 (h) 1010 1100
7–4. (a) 11 (b) 101 (c) 100 (d) 101
(e) 11001 (f) 10101 (g) 1101
(h) 10011

7–10. 7–20. From Figure 7–5(c),

Hex Binary Dec Hex Binary Dec Cout = ABC + ABC + ABC + ABC.
0C 0000 1100 12 18 0001 1000 24 Cout = AB + AC + BC, which matches
0D 0000 1101 13 19 0001 1001 25 Figure 7–9.
0E 0000 1110 14 1A 0001 1010 26
0F 0000 1111 15 1B 0001 1011 27
10 0001 0000 16 1C 0001 1100 28
11 0001 0001 17 1D 0001 1101 29
12 0001 0010 18 1E 0001 1110 30
13 0001 0011 19 1F 0001 1111 31
14 0001 0100 20 20 0010 0000 32
15 0001 0101 21 21 0010 0001 33 7–21.
16 0001 0110 22 22 0010 0010 34 A3 B3 A 2 B2 A1 B1 A0 B0
17 0001 0111 23
A B Ci A B Ci A B Ci A B Ci
7–11. (a) E (b) D (c) 21 (d) CA (e) 10C
FA FA FA FA
(f) 162 (g) AB45 (h) A000
Co Σ Co Σ Co Σ Co Σ
7–12. (a) 6 (b) 6 (c) 15 (d) 8F (e) 23
(f) 8A (g) 2FFE (h) 40E8 Σ4 Σ3 Σ2 Σ1 Σ0
7–13. 10010 = 64H 7–22. There is no carry-in to the LSB of the low-
2C8DH + 64H - 1 = 2CF0H order adder, so Cin must be grounded to
7–14. 0BD78H - 07A4BH + 1 = 0432EH ensure it is zero. The carry-out of the low-
03000H - 02F80H + 1 = 00081H order adder must be connected to the carry-
0432EH + 00081H = 043AFH in of the high-order adder to pass any carry
from the 23 addition over to the 24 addition.
7–15. b, c, e
7–23.
7–16. (a) 0001 0001 (b) 0010 1000
(c) 0001 0001 0101 (d) 1000 0101 NC NC A 5 B 5 A 4 B4 A 3 B 3 A 2 B 2 A 1 B1 A 0 B 0
(e) 0001 0000 0001 (f) 0101 1000
(g) 0001 0001 0000 (h) 0001 0000 0011 A 4 B4 A3 B 3 A 2 B 2 A 1 B1 A4 B4 A3 B3 A2 B2 A1 B1
7–17. For the LSB addition of two binary NC Cout 7483 Cin Cout 7483 Cin
numbers. Σ4 Σ3 Σ2 Σ1 Σ4 Σ3 Σ2 Σ1
7–18.
NC Σ6 Σ5 Σ4 Σ3 Σ2 Σ1 Σ0
7–24. When using more than one adder, IC to add

long binary strings, the fast-lookahead-carry
speeds up the addition by providing the
carry-in to the higher-order ICs almost
simultaneously with the binary inputs to be
7–19. © 0 = 1A + B2AB = AB + AB. . . . OK added.
C0 = 1A + B21AB21A + B2 =
AB + A B . . . NO

7–25. 7–32.
A 7 B 7 A 6 B 6 A 5 B 5 A 4 B4 A3 B3 A2 B2 A1 B1 A0 B0
A 4 B 4 A 3 B 3 A 2 B 2 A 1 B1 A4 B4 A3 B3 A2 B2 A1 B1
Cout 4008 Cin Cout 4008 Cin
Σ4 Σ3 Σ2 Σ1 Σ4 Σ3 Σ2 Σ1
Σ7 Σ6 Σ5 Σ4 Σ3 Σ2 Σ1 Σ0
A15 B15 A14 B14 A13 B13 A12 B12 A11 B11 A10 B10 A9 B9 A8 B8
A4 B 4 A3 B 3 A 2 B 2 A 1 B1 A4 B4 A3 B3 A2 B2 A1 B1
Cout Cout
E7–1. (a) 3 inputs, 2 outputs
4008 Cin 4008 Cin
(b) Full adder truth table
Σ4 Σ3 Σ2 Σ1 Σ4 Σ3 Σ2 Σ1
(c) The number of HIGH inputs is odd. The
Σ 16 Σ 15 Σ14 Σ13 Σ12 Σ11 Σ10 Σ9 Σ8 number of HIGH inputs is 2 or more.
E7–2. (a) Ground it
7–26. Reverse the switch (up to add, down to
(b) 0111 + 0110 = 1101
subtract). Also, put an inverter on input line
to Cin of the LSB. E7–3. (a) 0011 1011
(b) 0111 0000
7–27. The Ex-OR gate third from right is bad.
Also, the full-adder fourth from right is bad. E7–4. (a) 0 0111 110111 = ON2
(b) 1 0001 1001 11 = ON2
7–28. The B inputs should be B3 = 0, B2 = 0,
B1 = 1, B0 = 0. Also, the function-select E7–5. (a) 1 0011 11 = ON2
inputs should be S3 = 1, S2 = 0, S1 = 0, (b) 1 011111 = ON2
S0 = 1.
7–29. S3 - S0 = 0100. Chapter 8
(a) 1110 (b) 0001 8–1. (a) See top numbers.
7–30. (b) See lower numbers.
A7B7 A6B6 A5B5 A4B4 A3B3 A2B2 A1B1 A0B0
1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1
1 0 1 0 0 1 1 1 1 0 0 0 0 1 1 1
01 0 1 0 1 00 01 0 0 01 0 0
7–31.
1 0 OUT = 1 if A = B

8–2. (a) See top numbers.

(b) See lower numbers.
A3 0 A3 A7 1 A3
1 0 0 1
A2 1 A2 A6 0 A2
A1 0 A1 A5 1 A1
1 0 1 1
A0 1 A0 A4 1 A0
Low-order High-order
inputs B3 0 B3 A B 1 0 A> B 0 0
0 IA B IA > B equal
8–3. (a) 8–5.

3
A7 •• A0 00 7C C2 82 46 2 22 21 20 0 1 2 3 4 5 6 7 8 9
B7 •• B0 20 4E D2 AA 46
0 0 0 0 0 1 1 1 1 1 1 1 1 1
Outputs:
0 0 0 1 1 0 1 1 1 1 1 1 1 1
0 0 1 0 1 1 0 1 1 1 1 1 1 1
AB
0 1 1 0 1 1 1 1 1 1 0 1 1 1
AB That input is a “don’t care” and will have
8–3. (b) no effect on the output for that particular
A7 •• A0 A4 77 2D FF 1D
table entry.
8–7. Active LOW outputs are 0 when selected.
B7 •• B0 A5 A7 2D 00 2A Active-HIGH outputs are 1 when selected.
Outputs:
AB
t0 - t1 None (E3 disabled)
AB
t5 - t6 2
8–4. A decoder has a coded multibit number such t6 - t7 1
as octal or hex at its input. It has several t7 - t8 0
outputs, only one of which is active, t8 - t9 7
corresponding to the translation of the code t9 - t10 6
at its input. t10 - t11 5

8–10. Time Low output 8–16.

interval pulse at:
t0 - t1 0
t1 - t2 1
t4 - t5 4
t5 - t6 5
t6 - t7 None (E1, E3 disabled)
t7 - t8 None (E1, E3 disabled)
t8 - t9 0
t9 - t10 1
8–11. All HIGH

8–12.
8–17.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
I 0 I1 I2 I3 I4 I5 I6 I7 EI I 0 I1 I2 I3 I4 I5 I6 I7 EI
74148 74148
EO A0 A1 A2 GS EO A0 A1 A2 GS
1 1 1 1 1 1 0 0
1 0 0 0 1 1 1 1
NC NC
8–13. (a) A3 A2 A1 A0 = 1100
(b) A3 A2 A1 A0 = 1011
(c) A3 A2 A1 A0 = 1111
8–14. (a) E0 A0 A1 A2 GS = 11000
(b) E0 A0 A1 A2 GS = 10000 1 1 0 0
1 0 0 1
(c) E0 A0 A1 A2 GS = 11111
0 1 2 3
2 2 2 2
8–15.
t0 t1 t2 t3 t4 t5 t6 8–18. See #17 (lower numbers).
8–19. (a) 3210 = 0011 0010BCD = 1000002
EI (b) 4610 = 0100 0110BCD = 1011102
(c) 5510 = 0101 0101BCD = 1101112
I3
(d) 6810 = 0110 1000BCD = 10001002
I4 8–20.
A0
A1
A2
EO
GS

8–21. See #20 (lower numbers).

8–22. (a) 1100 = 10002 (b) 0101 = 01102
(c) 1110 = 10112 (d) 0111 = 01012
8–23. (a) 10102 = 1111 (b) 11112 = 1000
(c) 00112 = 0010 (d) 00012 = 0001
8–24. (a) Y = 1, Y = 0
(b) S0 = 0, S1 = 1, S2 = 1
8–25.
A To S0’s
B To S1’s
Data
C To S2’s
Select D
To E0 (Low-order
E
multiplexer)
To E1
To E2
To E3
Y0
Y1
Y2 Data out
Y3 8–29. (a) The 74150 is not working. The data
8–26. select is set for input D7, which is 0.
Therefore, Y should be 1 but it is not.
(b) The 74151 is OK. The data select is set
for input I0, which is 1. Y should equal 1
and Y = 0, which they do.
(c) The 74139 has two bad decoders.
Decoder A is enabled and should output
1011 but does not. Decoder B is disabled
and should output 1111 but does not.
(d) The 74154 is OK. The chip is disabled,
so all outputs should be HIGH, which they
are.
8–30. (a) 3000H 0011 ()* 0000 0000 0000
8–27. (a) E1 A0 A1 A2 A3 = 01110
Bank 3
(b) E1 A0 A1 A2 A3 = 01011 (b) 6000H 0110 ()* 0000 0000 0000
8–28. Bank 6
(c) 507CH 0101 ()* 0000 0111 1100
Bank 5
(d) 8001H = 1000 0000 0000 0001
:
A15 disables the ¿138

‹ No banks accessed
8–31. (a) RD = 1, WR = 0, IO>M = 0
Bank = 5, Location = 3H
‹ Write to memory
bank 5, location 3H.
(b) RD = 0, WR = 1, IO>M = 0
Bank = 6, Location = C7H
‹ Read from memory
bank 6, location C7H.

8–32. (a) Assuming NC = 0, Port 1 will read 8–41.

()* 2 06H
0000 0110
active-LOW 110
()* 01H
(b) 0000 0001
active-LOW 610
()* 00H
(c) 0000 0000
active-LOW 710
()* 00H
(d) 0000 0000
active-LOW 710
()* 07H
(e) 0000 0111
active-LOW 010
8–33. (a) Assuming NC = 0, Port 1
must output 0000 0101()* 2 05H E8–1. (a) A0 to A3 = B0 to B3
:
Read DT5 (b) NOR

()* 2 07H
(b) 0000 0111 E8–2.
(a) 1A = B2 = 1 1A 7 B2 = 0 1A 6 B2 = 0
:
Read DT7
()* 2 82H
(b) 1A = B2 = 0 1A 7 B2 = 1 1A 6 B2 = 0
(c) 0000 0010
:
(c) 1A = B2 = 0 1A 7 B2 = 0 1A 6 B2 = 1
Write DT2
(d) Impossible. The ¿238 demux can have
only one active output. E8–3.
8–34. 3.5 V (Y6 input) 0 A3
1 A2
8–35. 0 = 0, 1 = 1, 2 = 1, 3 = 1 0 A1
1 A0
8–36. U8
A=B Buzzer
8–37. The D input of U1:B D3 B3
D2 B2
8–38. AS = 0, AD13 = 1, AD14 = 1, D1 B1
AD15 = 1 D0 B0
8–39. LCD_SL KEY_SL 0 AB
AD4 0 0
AD5 0 0 E8–4. (a) Up
AD11 1 1 (b) all HIGH (ON) except 5
AD12 1 1 (c) all HIGH (ON)
AD13 0 0 E8–5. (a) All HIGH
AD14 0 0 (b) All outputs HIGH when G1 = LOW
AD15 0 0 (c) The 8 (1000) is used to make the top
AS 0 0 Logic Analyzer trace HIGH.
8–40. ICS5 ICS18 (d) Put an 8 in the MS hex digit whenever a
2 0 1 7 is in the LS digit.
5 0 0
6 1 0
9 0 x (don’t care)
12 0 1

E8–6. E8–9. (a) 00

(b) 11
E8–10. (a) The 4Hz signal does not come through.
(b) The 4Hz AND gate is bad.
E8–11. (a) Switch S1 has no effect on flashing speed.
(b) VCC at S1 is open.
E8–12. (a) 1, 1, 0
(b) Yes, it gets inverted twice.
E8–13. (a) LED2 is bad
(b) SW C is bad
(c) SW G is bad
(d) 74LS138 is bad
E8–14. (a) SW 7 is bad
(b) LED 2^3 is bad
(c) 74147 is bad
(d) 74147 is bad
E8–15. (a) SW A is bad
(b) SW G is bad
(c) V0 is bad
(d) 74151 is bad
E8–7. Chapter 9
2^0
9–1. D1 and D2 provide some protection against
0 negative input voltages.
1 A
2
5 V - 0.7
3 B 2^1 9–2. IE = = 1.075 mA
4
4K
5 74147 9–3. From Figure 9–2(a) there is L 0.2 V
C
6 dropped across the 1.6 k, 0.7 V across
7 2^2
8 D VBE3, and 0.7 V across D3, leaving L3.4 V
9 at the output terminal.
2^3
9–4. (a) A LOW, B LOW, Q3 ON,
E8–8. Q4 OFF
(b) A HIGH, B HIGH, Q3 OFF,
Q4 ON
9–5. Negative sign signifies current leaving the
input or output of the gate.
9–6. Sink current is higher.
9–7a. [STD]
(a) Va = VOH = 3.4 V1TYP2
Ia = 3 * IIH = 120 mA
(b) Va = 5 V - IIH * 10K = 4.6 V
VOL
@VIN = LOW, Ia = = 20 mA (typ)
10K
@VIN = HIGH, Ia = VOH>10K
= 340 mA (typ)
(c) Va = VOL = 0.2 V 1typ2
Ia = 2 * IIL = 3.2 mA
(d) Va = VOH = 3.4 V 1typ2
Ia = IIH + 3.4 V>10K = 380 mA

9–7b. [LS] 9–14. (a) The Commercial 74LS00 (8 mA)

(a) Va = VOH = 3.4 V 1typ2 (b) The Military S5400 (4.5 to 5.5 V)
Ia = 3 * IIH = 60 mA 9–15. The open-collector FLOAT level is made a
(b) Va = 5V - IIH * 10K = 4.8 V HIGH level by using a pull-up resistor.
= 35 mA 1typ2
VOL
@VIN = LOW, Ia = 9–16. X = A – B – BC = A B
10K Y = 1AB + AB2 – B + C = AB C
@VIN = HIGH, Ia = VOH>10K
= 340 mA 1typ2
9–17. The 7400 series is faster than the 4000B
(c) Va = VOL = 0.35 V or 0.25 V 1typ2
series but dissipates more power.
9–18. (a) TTL uses bipolar transistors.
Ia = 2 * IIL = 0.8 mA
(d) Va = VOH = 3.4 V 1typ2
(b) CMOS uses field-effect transistors.
9–19. Because MOS ICs are prone to electrostatic
Ia = IIH + 3.4V>10K = 360 mA
burnout.
9–8. (a) tp = 100 ms + 120 ms = 220 ms 9–20. Because the ECL transistors are never
1 allowed to saturate.
f = = 4.55 kHz 9–21. Where speed is most important, ECL is
tp
faster but uses more power.
(b) tr = 2 ms, tf = 3 ms
9–22. The 4000B is slow but uses little power,
(c) tPLH = 8 ms, tPHL = 6 ms
while the ECL is fast but uses a lot of power.
9–9. 9–23. The 74HC family
Vin 9–24. (a)
15ns 20ns
Vout1
Vout2
15ns 22ns
9–10.
(b)
HIGH = 1.4 V HIGH = 0.7 V noise
r
LOW = 0.9 V LOW = 0.4 V margins
(c) 74HCMOS-to-74ALSTTL will work,
but 74ALSTTL-to-74HCMOS will not work
because ALS may output 2.7 V when HC
expects at least 3.5 V (HIGH).
9–25. Interfacing (c) and (e) will require a pull-up
resistor to “pull up” the TTL HIGH-level
9–11. 7400: PD = 5 V * 18 mA + 22 mA2>2 =
output to meet the minimum HIGH-level
input specifications of the CMOS gates.
75 mW1max2 74LS00: PD = 5 V *
11.6 mA + 4.4 mA2>2 = 15 mW1max2 9–26. No trouble with current ratings.
9–12. 7400: VOL = 0.2 V1typ2 9–27. (a) 10 (b) 400
74LS00: VOL = 0.35 V1typ2 9–28.
9–13. (a) 7400: HIGH state (min levels) ⫽ 0.4 V
LOW state (max levels) ⫽ 0.4 V
74LS00: HIGH state (min levels) ⫽ 0.7 V
LOW state (max levels) ⫽ 0.3 V
(b) The 74LS00 has a wider margin for the
HIGH state. The 7400 has a wider
margin for the LOW state.

9–29. 10–3.
G
S
R
9–30.
Q
10–4.
E9–1. (a) HIGH
(b) ON, OFF
(c) OFF, ON
E9–2. (a) tplh = 11nS, tphl = 10nS
(b) tplh = 51nS, tphl = 50nS
E9–3. (a) 12nS, 12nS
(b) 6.3nS, 11nS 10–5.
E9–4. (a) Voh = 4.025V, Vol = 23mV D
Q
(b) Voh = 0V, Vol = 23mV
(c) 10K pull-up resistor G
C9–1. (a) 4 to 24 mA (b) 2 to 8 mA Q
C9–2. (a) 1.15 V, 1.25 V (b) 2.375 V, 2.625 V
(c) 0.066 A, 1.3 mA (d) 25 k-ohms 10–6. Two; a good NOR and a quad AND
C9–3. (a) 1.7 V, 0.7 V, 2.0 V, 0.4 V 10–7.
(b) 1.17 V, 0.630 V, 1.35 V, 0.45 V GD
+5 V +5 V
Chapter 10 1 VCC 14 1 VCC 14
10–1. Q
1 VCC 14 +5 V
S R Q
7 GND 8 7 GND 8
Q 10–8.
GND Q
10–2.
10–9.
G

10–10. 10–21.
1 VCC 14 +5 V
CP
10–11.
E
Q 7 GND 8 CP′
10–12. It is called “transparent” because the Q

10–22.
output follows the level of the D input as
long as E is HIGH. When E goes LOW, Q
latches, or holds on to, the level of D before
the HIGH-to-LOW edge of E.
10–13. HIGH, LOW
10–14. (a) SD, RD
(b) CP, D
10–15.
Cp
10–23. The toggle mode
SD
10–24. SD and RD, active-LOW
RD
10–25. The 7476 accepts J and K data during the
entire positive level of CP, whereas the
D 74LS76 only looks at J and K at the negative
Q
edge of CP.
10–26.
10–16.
10–17. The 7474 is edge-triggered; the 7475 is

pulse-triggered. The 7474 has asynchronous
inputs at SD and RD.
10–18. The synchronous input at D is only read at
the positive edge of CP. The active-LOW
asynchronous inputs at SD and RD override
any operations at CP and D.
10–19. The triangle indicates that it is an edge-
triggered device as opposed to being pulse-
triggered.
10–20. HIGH

10–27. long as the positive timing pulses are very

narrow 1610 ms2, the display will not
Trigger
flicker. The ¿273 is the preferred device,
SD however, because it is edge triggered.
RD 10–34. The display is changing so fast that it
appears that all segments are on. This is
J because, as the number to be displayed
randomly changes from 4 to 6 to 1 to 7,
K etc., all the segments will be turned on
momentarily. With all segments flashing, it
Q1
will look like the number 8.
Q2 10–35. (a) HIGH (b) no (c) Qa must go HIGH
while WATCHDOG_EN is HIGH (Qa will
10–28. go HIGH after Qb of U1:B goes HIGH).
10–36. or
10–37. WATCHDOG_SEL is pulsed.
10–38. (a) CPU_RESET is pulsed LOW.
(b) CPU_RESET must be HIGH and
WATCHDOG_SEL must be pulsed HIGH.
(c) CPU_RESET must be HIGH and the
output of U14:B must go HIGH.
10–29.
CP
E10–1. (a) 1, 0
(b) 0, 1
(c) 0, 0
SD
E10–2. An inverter is made by tying the two NAND
Data
inputs together.
Q E10–3. (a) Top inverter
(b) Vcc
10–30. (c) none
(d) R switch
E10–4. (a) D = 0, pulse C HIGH
(b) D = 1, pulse C HIGH
(c) Q stuck HIGH but would be
“undetermined”
10–31. (d) Set: Pulse S LOW then HIGH Reset:
CP Pulse R LOW then HIGH
E10–5.
CP
SD
Q
D
10–32. Sd′
Rd′
10–33. The ¿373 is a transparent latch. If the

timing pulses are connected to E, the BCD
will pass through to Q while E is HIGH and
latch on to the data when E goes LOW. As

E10–6. 11–4. ta = 16 ns td = 25 ns
tb = 28 ns te = 16 ns
tc = 16 ns tf = 28 ns
11–5. Proper circuit operation depends on
tp of the 7432 being Ú10 ns. The
worst-case tp is specified as 15 ns but the
actual tp may be less. If it’s actually less than
10 ns, the circuit won’t operate properly.
E10–7. (a) J = 0, K = 1, pulse Cp¿ 11–6.
LOW then HIGH
(b) J = 1, K = 0, pulse Cp¿
LOW then HIGH
(c) Q toggles each time Cp¿ goes LOW.
(d) Q stuck HIGH
(e) Set: Pulse S LOW then HIGH; Reset:
Pulse R LOW then HIGH
E10–8. 11–7.
RD
35 ns
CLOCK
J, K
25 ns
CpD
E10–9. 11–8.
Cp′
Sd′
Rd′
Q
Chapter 11
11–1.
RD
Cp
Q
11–9.
11–2.
3.6 V
Vout
0.2 V
11–3. ta = 20 ns td = 30 ns 0.7 V 1.9 V
Vin
tb = 30 ns te = 20 ns
tc = 20 ns tf = 30 ns

11–10. 11–16.
11–17. LIGHT:
1K
VA = 5 V * = 0.0495 V
11–11. 100K + 1K
2.4 V
DARK:
1.7 V 1M
Vin 0.9 V VA = 5 V * = 4.55 V
0.4 V
100K + 1M
0 11–18. For the dark condition, VA should be HIGH.
3.4 V
IIH for the 7414 is 40 mA. This input current
Vout causes the 100-kÆ resistor to drop 4.0 V.
This only leaves 1.0 V at point A, which is
0.2 V below the VT + value of 1.7 V for the 7414.
Therefore, the output of the second inverter
tHI = 1.8 volts change will never go HIGH.
tLOW = 2.2 volts change
DC = 45% 11–19. The 7474 can sink 16 mA. Connect the posi-
tive lead of the buzzer to +5 V and the nega-
11–12.
tive lead to Q. When Q is HIGH, the buzzer
is energized via the LOW Q output.
1K
11–20. VOUT1ON2 = 25 V * = 1.09 V
1K + 22K
1M
VOUT1OFF2 = 25 V * = 24.5 V
1M + 22K
24 V
11–21. Icoil = = 240 mA
100 Æ + 0.2 Æ
11–13. It is caused by switch bounce. If the switch 11–22. (a) The data on D of U14:B must be stable
bounces an even number of times, the LED one setup time prior to the LOW to HIGH
will be off. A debounce circuit would correct transition of CLK. Therefore the propaga-
the problem. tion delay of U15:A must exceed the setup
11–14. IIL for the CP of a 7476 is -3.2 mA, which time of U14:B.
would cause the voltage across a 10-kÆ (b) In this situation there will be no timing
resistor to be 32 V! The voltage across a problems because D of U14:B is stable prior
100-Æ resistor would be 0.32 V, which is to the LOW to HIGH edge of CLK.
OK as a LOW. The 10 kÆ would work with
a 74HCT76 because its IIL is only -1 mA.
11–15. Check the output of the 7805 for +5 V dc.
Check the fuse. If the fuse is OK, you
should check for approximately 12.6 V ac at
the transformer secondary, 20 V dc at the
+> - output of the diode bridge and the
input to the 7805.

A01_KLEI7369_08_IRM_FM.qxd 7/9/11 1:30 PM Page 29
11–23. 11–26.
E11–1. Vt+ = 1.6 V, Vt- = 1.3 V

+5V
0V
1.3V 1.6V
E11–2. (a) Vt+ = 1.6 V, Vt- = 1.2 V,
Voh = 5 V, Vol = 0 V
(b) Yes
E11–3. (a) Vt+ = 1.3 V, Vt- = 0.83 V,

11–24.
Voh = 5 V, Vol = 0 V
(b) Yes
+5V
0V
0.83 V 1.3 V
Chapter 12
12–1. Sequential circuits follow a predetermined
sequence of digital states triggered by a
timing pulse or clock. Combination logic
circuits operate almost instantaneously
based on the levels placed at their inputs.
12–2.
0 1 2 3 4 5 6
Cp
RD
11–25. The switches of U12 and the pull-up Q

resistors are used to place either a HIGH or Q
LOW on the MODA and MODB lines. To
place a HIGH on one of these lines the
corresponding switch must be open. A X
closed switch pulls the line to ground.

12–3. 12–9.
Cp 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9
Cp
RD 20
A 21
22
D
12–10.
Q
12–4. J = AQ + A Q, K = A Q 12–11. (a) 3 (b) 15 (c) 127 (d) 1

12–12. (a) 21 (b) 14 (c) 18 (d) 161 1
(e) 32
12–13. (a) 2 (b) 4 (c) 4 (d) 5
12–14. The time period (tp) of the input clock is
less and less at higher frequencies. If it
becomes less than the total propagation
delay of all flip-flops, the input will be
switching before the last flip-flop has a
chance to switch states.
12–15.
Cp
12–5. 20
Cp 0 1 2 3 4 5 6 7 8 9
21
RD
22
A
12–16. Down counter, mod-8
J 12–17.
1 20 1 21 1 22
K
1 J SD Q 1 J SD Q 1 J SD Q
Q Cp0
Q 1 K RD 1 K RD 1 K RD
12–6. (a) 8 (b) 19 (c) 6 (d) 11 (e) 14 (f) 5

12–7. (a) 3 (b) 3 (c) 1 (d) 5 (e) 6 (f) 4
12–8. (a) 5 MHz (b) 2.5 MHz (c) 1.25 MHz
(d) 0.625 MHz (e) 0.3125 MHz
(f) 0.15625 MHz

12–18. 12–22.
12–19.
1 20 1 21 1 22 1 23
Cp0
12–23.
+5 V
MOD - 11 to RD
UP
10 kΩ
+5 V 21
100 Ω 22
12–24. The 7400 is probably burnt out because you

12–20.
depressed the push button while the 7400
was outputting a HIGH. Without the 7400
the counter is a mod-8.
12–25. Yes, it will work. The inputs to the AND
are normally 1–1 until the push button is
pressed, or the NAND output goes LOW. If
either AND input goes LOW, its output goes
LOW, resetting the counter. This is an im-
provement over Figure 12–19, because the
10 kÆ draws less current than the 100-Æ re-
sistor when the push button is depressed.
12–26. The 7490 is a divide-by-10 counter, the 7492
is a divide-by-12 counter, and the 7493 is a
divide-by-16 counter. The 7490 has master
SET and master RESET inputs. The 7492
12–21. and 7493 have master RESET inputs.
1 1
12–27.
Output
(÷24)
Cp1 Q0 Q1 Q2 Q3 Cp1 Q0 Q1 Q2 Q3
Cp0 23 7490 7492 NC
Input Cp0 ÷2 Cp0 ÷12
20 21 22
1 1 12–28.
MOD - 5
DOWN
+5 V
100 Ω

12–29. 12–36. All F-Fs are driven from the same clock in
synchronous counters. This eliminates the
60pps 7492 10 pps 7490 1 pps 7492 10 ppm 7490 1 ppm
Input ÷6 ÷10 (60 ÷6 ÷10 problem of accumulated propagation delay
ppm) (60 pph) that occurs with ripple counters.
12–37.
7492 10 pph 7490 1 pph 7492 2 ppd 7490 1ppd
÷6 ÷10 (24 ÷12 ÷2 Output
CP 0 1 2 3 4 5 6 7 8 9
ppd)
12–30. 20
21
22
12–38. DC = 20%
12–39.
CPU
0 1 2 3 4
CPD
0 1 2 3 4
12–31.
PL
NC 20 21 22 TCU
TCD
100 Hz Cp1 Q0 Q1 Q2 Q3
Q0
7493 +5 V
NC Cp0 MR1 MR2 330 Ω Q1
Q2
1 = 100 Hz Q3
10 ms 5 6 7 8 9 0 5 4 3 2 1 0 9
12–32. 12–40.
12–33. Connect a RESET push button across the

0.001-mF capacitor. When momentarily 12–41.
pressed, it will RESET the circuit to its
initial condition. 1 1 0 1
12–34. R = 15.0 V - 1.7 V2>15 mA = 220 Æ

PL an 1110 when
PL D 0 D 1 D2 D3
TCU goes LOW
12–35. With all the current going through the same CpU CpU TCU
74193
resistor, as more segments are turned ON, NC CpD TCD NC
the voltage that reaches the segments is re-
MR Q0 Q1 Q2 Q3 Take ÷ 4 output
duced, making them dimmer. The displayed from Q2 or TCU
is much dimmer than the .
Output

12–41. (continued) 12–45.

74LS 193 74151 ( C L K O U T ) TO
15 3 4 5 P I N S 6 & 10
CpU 0 1 2 3 4 5 6 7 1
P0
P1
Q0
QB 2 3
I0
I1
Z
OF M1
10 P2 QC 6 2 I2 Z 6 N/C
9 P3 QD 7 1 I3
15 I4
TCU E (CLK IN) 5 CU TCU 12 N/ C 14 I5
4 CD TCD 13 13 I6
11 N/ C
+5 PL 12 I7
14 MR
F REQUENCY 11 A
Q0 S ELECT
10
9
B
C
7 E
Q1
E12–1. (a) 2^0
(b) 0123456789ABCDEF
Q2
E12–2. It only counts even numbers. Bad seven seg-
Q3 ment display
13 14 15 11 12 13 14 15 11 12 13
E12–3. Doesn’t count past 7. Bad MS flip-flop
12–42. E12–4. (a) Negative
(b) 2^0
(c) Mod-16
E12–5. (a) Mod-10
(b) Connect NAND inputs to 2^3 and 2^2
(c) 2^2
E12–6. (a) Mod-16
(b) Connect 2^3 2^2 to RO1 RO2
(c) Connect 2^3 2^2 to an AND then to
RO1 and connect 2^0 to RO2.
E12–7. (a) Build a circuit similar to Figure 12–35.
(b) Use a third 7490 as div-by-10 with
12–43. (a) HIGH order U10, LOW order U9
10 pps driving its Cp0¿ (The output of
(b) no (c) by a LOW at the output of U3:B
that 7490 is 1pps.) Make the input to
12–44. your 00 to 99 counter switch between
those two clock speeds.
(c) Place an AND gate before the first Cp¿
input. Disable it with a NAND gate that
outputs a LOW when 23 is reached.
E12–8. Build a circuit similar to Figure 12–31.
E12–9.
MR
PL
Cpu
Cpd
Qa
Qb
Qc
Qd
Tcd'
Tcu'
2 1 0 9 8 7 8 9 0 1 2

Chapter 13 13–16.
13–1. Right, negative
13–2. 0010, 0000
13–3. 1110, 1111
13–4. 1001, 0110
13–5. Apply a LOW pulse to RD to RESET all Q
outputs to zero. Next, apply a LOW pulse to
the active-LOW D3, D1, D0 inputs.
13–6. D3, D2, D1, D0 are the data input lines, and
Q0 is the data output line (LSB first). 13–17. Put a switch in series with the phototransis-
13–7. J3, K3 are the data input lines. Q3, Q2, Q1, Q0 tor’s collector. With the switch open, the in-
are the data output lines. (D3, D2, D1, D0 are put to inverter 1 will be HIGH, simulating
held HIGH.) nighttime conditions, causing the yellow
13–8. Connect Q0 to K3 and Q0 to J3. Connect D3, light to flash, day or night.
D2, D1, D0 HIGH, and apply a LOW pulse to 13–18.
RD before applying the clock input.
13–9. Three
13–10. Five
13–11. The Q0 flip-flop and the Q3 flip-flop
13–12.
Cp 0 1 2 3 4 5 6
Q2
13–13.
Cp 0 1 2 3 4 5 6
Q2
13–14. 13–19.
Cp 0 1 2 3 4 5 6 7 8 9
MR
S0
S1
Q0
Q1
13–15.
Q2
Q0 Q0 Q2
X X Z
Q1 Q2 Q3 Q3
S S P S MS S H P S S
Mode L L L L RR R O L R R
L
D

13–20. 13–22.
13–21.
Cp 0 1 2 3 4 5 6 7 8 9
S0
13–23.
S1 Parallel input data
PL
0 1 1 0 1 0 0 1
DSR
PL D 0 D1 D2 D3 D4 D5 D 6 D 7
DSL DS
Clock Cp NC
CP 74165
Oscillator
CE CE
Q7 Q7
Q0
Q1 Serial
output data
Q2
Q3 Cp 0 1 2 3 4 5 6 7 8 9
S S S S P H S S S S
Mode L L L L L O R R R R
L PL
D
CE
Q7
MSB LSB
13–24. The parallel-load and clock inputs are PE,

CP on the 74195 and PE, CP on the 74395A.
The 74195 provides J-K type functions on
its first flip-flop via the J-K inputs. The out-
puts of the 74395A are three-stated, made
active by a LOW on OE.
13–25. The 74164 is a serial-in, parallel-out,
whereas the 74165 is a serial or parallel-in,
serial-out shift register. The 74165 provides a
clock-enable input, CE. The serial input to
the 74164 is the logical AND of two data
inputs (Dsa–Dsb).

13–26. Data are parallel loaded asynchronously 13–31. A buffer is a transparent device that con-
with the 74165 by applying a LOW to PL. nects two digital circuits; a latch is a storage
Data are parallel loaded synchronously with device that can hold data. A buffer allows
the 74166 at the positive edge of CP while data to flow in only one direction; a trans-
PE is held LOW. ceiver is bidirectional.
13–27. 13–32. Several devices must be connected to the
Serial in same bus, but only one device can be active
LSB 1st at a time or else there will be a bus conflict.
DSR D0 D1 D2 D3 DSL DSR D0 D1 D2 D3 DSL
13–33. (a) U4, U12
S0 S0 S0 S0 (b) U5, U30, U31, U32, U36, U37, U38
S1 S1 NC
74194 S1 S1 NC
74194 (c) U3, U6
CP CP CP CP
MR Q0 Q1 Q2 Q3 MR Q0 Q1 Q2 Q3 (d) U11, U33
13–34. The 74HC245 is an octal transceiver. To
1 1
transfer data from D0–D7 to COMMD0–
Serial out OE COMMD7, the /COMM line (pin 19) must
MSB 1st
be LOW, AND the /RD line (pin 1) must be
CP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HIGH. To send data in the other direction
S0
SHIFT RIGHT SHIFT LEFT change /RD to a LOW.
S1
13–35. To load IA0–IA7 of U30, valid data must be
SERIAL
IN
0 0 1 0 1 1 0 1 DONT CARE placed on BD0–BD7 by U33, then a LOW
OE to HIGH pulse must be applied to the CLK
SERIAL
OUT
FLOAT 1 0 1 1 0 1 0 0
input of U30. When pin 3 of U13:A is LOW,
a HIGH will appear at LE of U33. This al-
13–28. At 15° per step, the number of steps per rev- lows the valid data at D0–D7 to pass through
olution is 360°>15° = 24. to BD0–BD7. Next, pin 3 of U13:A goes
13–29. HIGH, making LE LOW, which causes the
data outputs of U33 to remain latched. The
Cp 1 2 3 4 5 6 HIGH at pin 3 of U13:A also enables the
S0 decoder U23. Just before pin 3 went HIGH
S1 A0-A1-A2 are set to 1-0-1 to provide an
active output at /IOADDR. This is the clock
input for U30, which passes the valid data at
Q0 BD0–BD7 of U30 out to IA0–IA7. To load
ID0–ID7 of U32 the same process is fol-
Q1 lowed except A0-A1-A2 are made 0-1-1
before pin 3 of U13:A is made HIGH.
Q2 E13–1. (a) 3
(b) R, S, C, S, C, S, C, S
Q3
E13–2. (a) 3
(b) Q^1
360°>revolution
13–30. = 24 steps>rev. E13–3. (a) 2 ms
15°>step (b)
24 steps 600 rev 14,400 steps
* = Q^0
rev min min
14,400 steps 1 min 240 steps
* = Q^1
min 60 sec sec
240 steps 1 clock pulse 240 pulses Q^2
* =
sec step sec
240 pulses Q^3
= 240 Hz
sec E13–4. (a) Cross-connect the recirculating lines
from the Qs of the last FF.
(b) 8 ms

E13–5. M 0100 1101, Reset 74164. Then 14–8. (a) Frequency increases
Set S 1, press C; Set S 0, press C; (b) The voltage levels, VOH and VOL, remain
Set S 1, press C; Set S 1, press C; the same.
Set S 0, press C; Set S 0, press C; 14–9.
Set S 1, press C; Set S 0, press C.
E13–6. Parallel load 1S0 S1 = 112 ABCD = 1101.
3.3 V
VC
2.0 V
Apply a pulse to Cp (Clk).
Shift right 1S0 S1 = 102. Apply four pulses 0V
to Cp (Clk). 6V
Vout
Chapter 14
0V
14–1. (a) Monostable (b) Bistable (c) Astable
14–2. (a) ¢v = 5 V11 - e-50 ms>1100 kÆ * 470 pF22
to solve for tHI:
¢v = 3.3v - 2.0v = 1.3v
¢v = 3.27 V
(b) ¢v = 5 V11 - e-100 ms>1100 kÆ * 470 pF22
E = 6.0 - 2.0 = 4.0v
¢v = 4.40 V 1
P 1 - 4.0 Q
tHI = 68K.0047m Ln
(c) ¢v = 5 V11 - e-150 ms>1100 kÆ * 470 pF22 1.3
¢v = 4.79 V
(d) tHI = 126 ms
to solve for tLO:
¢v = 3.3v - 2.0v = 1.3 V
E = 3.3v - 0v = 3.3v
1
P 1 - 3.3 Q
tLO = 68K * .0047m Ln
1.3
tLO = 160 ms
126 ms
DC = = 44.1%
1 126 ms + 160 ms
P1 - Q
14–3. t = 100 kÆ * 470 pF Ln
4V f = 1>1126 ms + 160 ms2 = 3.5 kHz
5V 14–10.
t = 75.6 ms
1
P1 - Q
14–4. t = 100 kÆ * 470 pF Ln
4 - 2
5 - 2
t = 51.6 ms
1
P1 - Q
14–5. t = 100 kÆ * 470 pF Ln
4 - 2 74HC00: VIH = 3.5v, VIL = 1.0v,
4 - 0 VOH = 5v, VOL = 0 V
t = 32.6 ms ¢v = 3.5 V - 0 = 3.5v E = 5 - 0 = 5v
14–6. Because in problem 4 the capacitor had to 1
P1 - E Q
tw = RC Ln
travel two-thirds of the total distance it was ¢v
trying to, whereas in problem 5 it had to
travel only one-half of the total. 1
P1 - 5 Q
14–7. Because a Schmitt device has two distinct 50 ms = RC Ln
3.5
switching thresholds, VT+ and VT-; a regular
Inverter does not. The capacitor voltage
RC = 41.5 ms, Pick C = 0.0047mF
charges and discharges between those two
R = 41.5 ms>0.0047mf = 8.84 kÆ
levels.

14–11. 14–14. Rx = 10 kÆ, Cx = 80 pF

Vin 3 μs 7 μs 14–15.
Vout 5 μs 5 μs 0 0.5 1.0 1.5 2.0 time
(μs)
VCC A1
B
Rx 7.21 kΩ
Cx = 0.001 μF
Q1
Vout Q2
T
tw1 = 5.78k * 50 pf ln 2 = 0.20ms
Vin tw2 = 0.20ms1from Fig. 14–172
74121
14–16. tLO = .693 RBC
tw = RxCx ln 2 = .693 – 4.7 k – 1000p
5 ms = RxCx1.6932 = 3.26 ms
RxCx = 7.21 ms, Pick C = 0.001 mF tHI = .6931RA + RB2C
Rx = 7.21 ms>0.001 mF = 7.21 kÆ = .693 16.8k + 4.7k2 1000p
14–12. The first 74121 will generate a 30 ms delay = 7.97ms
pulse to trigger the second 74121 which will
generate the 10 ms output pulse.
14–17. @0 Æ
tHI = 7.97 ms f problem #15

tLO = 3.26 ms from
1
f = = 89.0 kHz
tLO + tHI
tHI
DC = = 71.0%
tHI + tLO
14–13. Choose an output pulse width that’s longer @10 kÆ
than 150 ms, let’s say 170 ms. That way, if a
tLO = .693 – 14.7k – 1000p = 10.2ms
tHI = .693 – 16.8k + 14.7k2 – 1000p
pulse is missing after 170 ms (the o.s. is not
re-triggered), the output will go LOW.
VCC = 14.9ms
1
Rx 12.9 kΩ
f = = 39.8 kHz
tLO + tHI
Cx = 0.047 μF
tHI
DC = = 59.4%
tHI + tLO
Output
NPRO tHI
T 14–18. DC =
1 tHI + tLO
1 .6931RA + RB2C
.6931RA + RB2C + .693 RBC
74123 DC =
.693 C1RA + RB2

tw = 0.28 RxCx a 1 + b,
0.7
.693 C[1RA + RB2 + RB]
DC =
Rx
RA + RB
Pick Cx = 0.047 mF DC =
RA + 2RB
Rx = 12.9 kÆ

1
F =
tHI + tLO
1
.6931RA + RB2C + .693RBC
F =
1
.693 – C[1RA + RB2 + RB]
F = (b) tw = RxCx ln 2 Pick Cx = .001 mF
5 ms = Rx1.001 m21.6932
1.44 Rx = 7.21 kÆ
1RA + 2RB2C
F =
1
14–19. tTOTAL =
f
1
=
50 kHz
= 20 ms
tHI = DC * tTOTAL
= .60 – 20 ms
= 12 ms
(c) tw = 0.28 RxCx a1 + b
tLO = tTOTAL - tHI 0.7
= 20 ms - 12 ms Rx
= 8 ms Pick Cx = 0.0022 mF
5 ms = 0.28 Rx10.0022 m2a1 - b
0.7
tLO = .693 – RB–C
Rx
8 ms = .693 – RB–.0022 mf Rx = 8.12 kÆ
RB = 5.25 kÆ
tHI = .693 – 1RA + RB2–C
12 ms = .693 # (RA + 5.25 kÆ) # .0022 mf
RA = 2.62 kÆ
VCC
RA 2618 Ω
7 8 4
RB 5236 Ω 2 555
6 3 Vout
1 5
C .0022 μF
(d) tHI = .693 RAC, tLO = .693RBC
.01 μF Pick C = .001 mF
5 ms = .693 RA1.001 mF2
14–20. (a) From Example 14-5: RA = 7.22 kÆ, RB = 7.22 KÆ
1
P Q
tHI = RC Ln = RC1.3922
1.08
1 -
3.33
1
tLO = RC ln = RC1.4992
1.08
1 -
2.75
1
tTOTAL = = 10 ms
100 KHz
= RC1.392 + .4992
RC = 11.2 ms; Pick C = .001 mF,
R = 11.2 KÆ

14–21. 14–23.
5V
100 μs
Vtrig
5 μs
0V
3.33 V
Vcap
0
E14–1. (a) Tcalc = 693 mS, Tmeas = 700 mS
(b) DC Vtrig = 20%, DC Vout = 70%
3.5 V (c) Rext = 722 ohms
Vout E14–2. Tw = .693 * 470 ohms * 2.2 mf
= 717 ms
0.1 V
0
tw
tw = 1.10 RAC
tw = 1.10 – 47 K – 1000 pF
tw = 51.7 ms
14–22. Measured: TLO = 300 ms 1Vtrig2
TLO = 720 ms 1Vout2
E14–3. Ttrigger: Ttot = 1>10 kHz = 100 mS,
Thi = 70 mS
Tout: 50% * 100 mS = 50 mS,
50 mS = .693 Rext * Cext,
Pick Cext = .01 mf, Rext = 7220 ohms.
Use those components in a circuit similar to
sec 14-5b.
E14–4. (a) Thi = 6.84 mS, Tlo = 4.65 mS
(b) Rts
(c) Rts
(d) Inc
E14–5.
V out (calc.) V out (meas.)
th 11.64 μs 11.8 μs
If designing for 50% DC:
@ RA = RB = 925 ohms, FREQ 1 MHZ
tl 9.42 μs 9.6 μs
@ RA = RB = 9250 ohms, FREQ
100 KHZ
4V
Vc
2V
4.5 V
V out
0.1 V

A01_KLEI7369_08_IRM_FM.qxd 7/9/11 1:30 PM Page 41
E14–6. Ttot ⫽ 20 ␮S, Thi ⫽ 12 ␮S, Tlo ⫽ 8 ␮S, 15–8. The output voltages (Vout) would all
pick C ⫽ 68 pf and use Tlo ⫽ .693 ⫻ Rb ⫻ double. (Vout) would be limited, however,
C, Thi ⫽ .693 ⫻ (Ra ⫹ Rb) ⫻ C. This by the size of the supply powering the
yields: Ra ⫽ 8.46k-ohms, Rb ⫽ 17.0k- op-amp.
ohms, and C ⫽ 680 pf. Use those values in 15–9. All values of Vout would become positive.
the circuit given in file “sec 14-8b.”
15–10. -2.0 V
Chapter 15 15–11.
D3 D2 D1 D0 Vout D3 D2 D1 D0 Vout
15–1. Converts physical quantities into electrical
quantities. 0 0 0 0 0.00 1 0 0 0 -2.00
15–2. 16, 64, 256, 4096 0 0 0 1 -0.25 1 0 0 1 -2.25
15–3. Very high input impedance, very high volt- 0 0 1 0 -0.50 1 0 1 0 -2.50
age gain, and very low output impedance. 0 0 1 1 -0.75 1 0 1 1 -2.75
15–4. (a) Vout = - a * RF b
Vi 0 1 0 0 -1.00 1 1 0 0 -3.00
Ri 0 1 0 1 -1.25 1 1 0 1 -3.25
5v
= - * 5 kÆ = -2.5 V 0 1 1 0 -1.50 1 1 1 0 -3.50
10 kÆ
0 1 1 1 -1.75 1 1 1 1 -3.75
(b) Vout = - a * 5 kÆ b = -3.75 V
5v
6.67 k 15–12. R/2R method
(c) The lower 20 kÆ has virtual ground at 15–13. To convert the analog output current (Iout)
its top and ground at its bottom there- of the MC1408 to a voltage
fore no current flows through it. 15–14. 8-bit resolution
Vout = - a * 5 kÆ b = -1.25 V
5v 15–15. (a) 0100 00002
20 kÆ
15–5. The (⫺) input is at 0-V potential. : A2
Iout = IREF * a b
A2
15–6. 1210 = 11002
4
ID3 = 5 V>12.5 kÆ = 0.4 mA
1
ID2 = 5 V>25 kÆ = 0.2 mA = 2 mA * = 0.5 mA
ID1 = 0 mA 4
ID0 = 0 mA Vout = IOUT * RF
Vout = -(0.4 mA + 0.2 mA) * 20 kÆ = 0.5 mA * 5 kÆ
= -12 V = 2.5 V
15–7. (a) 20 kÆ, 40 kÆ, 80 kÆ (b) 0 0 1 1 0 1 1 02
:
:
:
:
(b) D3 D2 D1 D0 Vout
A3 A4 A6 A7
0 0 0 0 0.00
Iout = 2 mA * a b
1 1 1 1
0 0 0 1 -1.25 8
+
16
+
64
+
128
0 0 1 0 -2.50
0 0 1 1 -3.75 = 2 mA * .2109 = 0.422 mA
0 1 0 0 -5.00 Vout = 0.422 mA * 5 k = 2.11 V
0 1 0 1 -6.25 (c) 3210 = 0010 00002
0 1 1 0
:
-7.50
A3
0 1 1 1 -8.75
1 0 0 0 -10.00 1
Iout = 2 mA * = 0.25 mA
1 0 0 1 -11.25 8
1 0 1 0 -12.50 Vout = 0.25 mA * 5 kÆ = 1.25 V
1 0 1 1 -13.75
(d) 3010 = 0001 11102
1 1 0 0 -15.00
1 1 0 1 -16.25 3010
Iout = 2 mA * = 0.234 mA
1 1 1 0 -17.50 25610
1 1 1 1 -18.75 Vout = 0.234 mA * 5 kÆ = 1.17 V

15–16. Vout = 15–22. If the counter has to count all the way up to
VREF * a + p Nb
A1 A2 A3 AN 255 (1111 1111), then
+ +
2 4 8 2 1
@0000 0000, Vout = 0V ttot = 255 * = 2.55 ms
100 kHz
@0000 0001, Vout = 10 * a 8 b
1
1
2 15–23. ttot = 8 * = 0.16 ms
50 kHz
= 0.039 V
15–24. Connect DR back to STRT.
@0000 0010, Vout = 10 * a 7 b
1
2 15–25. 7.28
= 0.078 V -5.00 D7
@0000 0011, Vout = 10 * a 7 + 8 b
1 1 2.28
2 2 -1.25 D5
= 0.117 V
1.030
(etc.)
D4 1011 1010
y
-0.625
.4050 = 5 + 1.25
D3 + .625
-.3125
+ .312 5
.092500 + 0.78125
-.078125 D1 = 7.265625 V
.014375
DAC OUT - ACTUAL VIN
%ERROR =
ACTUAL VIN
7.265625 - 7.28
%ERROR = = -0.197%
7.28
15–17. By making VREF = 7.5 V. The range of 15–26. The buffer has a float condition that allows
Iout would then be 0 to 1.5 mA. The range other devices to take turns writing to the
of Vout would be 0 to 7.47 V same data bus without causing a bus con-
1 1 1 1 flict. This enables its use in microprocessor-
15–18. Vout = 5 Va + + + + based systems.
2 4 8 16
15–27. CS (chip select) and RD (READ); active-
b
1 1 1 1
+ + + LOW
32 64 128 256
15–28. When the analog input voltage to be con-
Vout = 4.98 V verted is the difference of two voltages
15–19. 15–29. (a) The three-state output latches (D0 to
D7) would be in the float condition.
000 (b) The outputs would float and WR (start
001 conversion) would be disabled.
3-Bit 010
digital (c) It issues a LOW at power-up to start
011 the first conversion.
output
(ACTIVE 100 (d) 1.0 V
-LOW) 101
AIN
110 15–30. (Eq 15–7) Dout = * 256
111 VREF
0 1 2 3 4 5 6 7 8
Analog input 3.6 V
(a) Dout = * 256 = 18010
voltage (in volts) 5.12 V
15–20. The main advantage is its high speed. Its 18010 = 1011 01002
disadvantage is circuit complexity with Active-LOW ON LEDs =
higher-resolution converters.
D0, D1, D3, D6
15–21. (a) 0 V (b) They are equal.

1.86 V 15–36.
(b) Dout = * 256 = 9310
5.12 V
9310 = 0101 11012
Active-LOW ON LEDs = D1, D5, D7
15–31. The temperature transducer is selected by
setting up the appropriate code on the ABC
multiplexer select inputs. The voltage level 15–37.
passes to the LF 198, which takes a sample VCC
20
at some precise time and holds the level on 7
ADC0801–1
18
Vin (–) 1sbDB0 P1.0
VccREF
the hold capacitor. The LH0084 adjusts the ANALOG IN 6 Vin (+)
DB1
DB2
17
16
15
P1.1
P1.2
DB3 P1.3
voltage to an appropriate level to pass into 8 A–GND
DB4
DB5
14
13
12
P1.4
P1.5
DB6 P1.6
the ADC. The microprocessor issues 9 Vref/2
msbDB7 11
5
P1.7
N/C INTR
CS1, WR1, then waits for INTR to go LOW. 10K 19 CLK–R CS 1
RD 2
It then issues CS1, RD1 to transfer the con- 4 CLK–IN WR 3
+
verted data to the data bus, then CS2, WR2, 150 pf
to transfer the data to RAM.

Rf P2.0
15–32. Vout = -(-250 mV) * VCC

Ri
20
ADC0801–2
7 Vin (–) 1sbDB0 18
VccREF
Rf ANALOG IN
6 Vin (+)
DB1
DB2
17
16
VCC
5V = 250 mV * DB3
DB4
15
14 R3
20 kÆ 8 A–GND DB5
DB6
13
12 10x
msbDB7 11
9
Rf = 400 kÆ N/C
10K
Vref/2
INTR 5 2 1
19 CLK–R CS 1 C1
15–33. 10,000Æ + 5% = 10,500 4 CLK–IN
RD
WR
2
3
7417
OC BUFFER
.001
+
150 pf
10.000Æ - 5% = 9,500
Rf
Vout = -(-250 mV) * E15–1. (a) D0 = -1V, D1 = -2V, D2 =
Ri
-4 V, D3 = -8V
200 kÆ (b) True
Vout = 250 mV *
10 kÆ + 10.5 kÆ (c) D3, D2, (D2 and D1), (D3 and D1
Vout = 2.439 V and D0)
(d) 16
200 kÆ
Vout = 250 mV * (e) 6.25k-ohms
10 kÆ + 9.5 kÆ
E15–2. (a)
Vout = 2.564 V
‹ Range = 2.439 V to 2.564 V
15–34. 0011 11002
15–35. VAB = Vout>Amplifier Gain
VAB = 4.0 V>1000 = 4 mV
Eq 15-6:
VAB = VIN c d
R3 R2
R3 + 1Rg + ¢Rg2
-
R1 + R2
120
120 + 1120 + ¢Rg2
4 mV = -10Vc -
d
120
120 + 120
¢Rg = 0.192Æ
Force = 0.192Æ>0.020Æ per kg
Force = 9.60 kg

16–5.
WRITE E1 0 ADDR 000

E2 1 ADDR 001
1 E3 2 ADDR 010
To CP
3 ADDR 011
of each
A 4 ADDR 100 74LS374
D
D A0 A0 5 ADDR 101
R A1 A1 6 ADDR 110
E15–3. (a) Output E
S A2 A2 7 ADDR 111
Vin Hex Dec S
0.0 00 0
0.5 19 25 16–6. Static RAMs use flip-flops as their basic
1.0 33 51 storage elements and dynamic RAMs store
1.5 4C 76 a charge on an internal capacitor. Dynamic
2.0 66 102 RAMs require refresh circuitry, but are
2.5 7F 127 more dense and less expensive per bit.
3.0 99 153 16–7. CS = LOW, WE = LOW
3.5 B2 178 16–8. High impedance (float)
4.0 CC 204 16–9. 10, 12, 13
4.5 E5 229
5.0 FF 256 16–10. (a) 2048 (b) 2048 (c) 8192 (d) 1024
(e) 4096 (f) 16,384
(b) Yes
16–11. (a) 8192 (b) 16,384
E15–4. (a), (b) (c) 65,536 (d) 16,384
80 E7 06 16–12.
9B D4 00 ; Valley
B6 BD 01
CE A3 07
E2 88 ; Mid 14
F1 6C 25
FB 51 3B
FF ; Peak 38 54
FD 22 6F
F5 12
Chapter 16
16–1. Bipolar, faster; MOS, more dense.
16–2. The address is a binary string that repre-
sents the location where the 8-bit data
string is stored.
16–3. Data are being written into memory from
the data bus. Bus contention occurs only
when two or more devices are writing to
the data bus at the same time.
16–4. The A3 line into the 74LS154 (Fig. 16–4) is 16–13. CS is not held LOW long enough. The
stuck LOW. Put a logic probe on the A3 access time (tacs) for the 2147H is given in
input. If it stays LOW when selecting Figure 16–6(a) as 35 ns minimum. To
addresses 1000 to 1111, then it is shorted correct, increase the LOW CS pulse to
to ground. 35 ns or more.

16–14. 62256 = 32k * 8 16–24. A bad connection to OE or CE. Use a logic

1M probe to see if there is a LOW at OE and
= 32 ICs
32k that CE is receiving LOW pulses.
16–15. The high- and low-order address lines are 16–25. Address line A15 is stuck LOW.
multiplexed to minimize the IC pin count. 16–26. LOW-to-HIGH. The HIGH-to-LOW level
16–16. The row address strobe 1RAS2 signifies enables the ¿138 and selects the appropri-
that a row address is present on the address ate EPROM, but because of propagation
lines; then CAS is used to signify that the delays, the data out of the EPROM are not
column address is present. valid for several hundred nanoseconds.
16–17. (a) Waiting until the LOW-to-HIGH edge
ensures that the data out will be valid.
Read cycle:
RAS 100 ns 16–27. The circuit design will be similar except
the 2716 address inputs are A0 to A10.
CAS The new 74LS138 connections will be as
follows:
ADDRESSES ROW COLUMN
120 nsmax RD EN1 0 To EPROM1(0000 - 07FF)

180 nsmax A15 EN2 To EPROM2(0800 - 0FFF)
Dout Valid data out A14 EN3 To EPROM3(1000 - 17FF)
To EPROM4(1800 - 1FFF)
Write cycle:
RAS 100 ns
A11 A0
A12 A1
CAS
A13 A2 7
ADDRs ROW COLUMN 16–28. The 74154 1-of-16 decoder

40 nsmin 30 nsmin
16–29.
Din Valid data in
A3 A 2 A 1 A 0 Q3 Q 2 Q 1 Q 0
(b) 100 ns + 120 ns = 220 ns max 0 0 0 0 X 0 0 0
(c) 100 ns - 40 ns = 60 ns max A0 Q0 0 0 0 1 X 0 0 1
0 0 1 0 X 0 1 0
16–18. The charge on the internal capacitors must A1 Q1 0 0 1 1 X 0 1 1
be refreshed every 2 ms or sooner to pre- A2 Q2 0 1 0 0 X 1 0 0
0 1 0 1 X 1 0 1
vent loss of data. A3 Q3 NC 0 1 1 0 X 1 1 0
0 1 1 1 X 1 1 1
16–19. Address line multiplexing and memory 1 0 0 0 X 1 1 1
refresh cycling 1 0 0 1 X 1 1 0
1 0 1 0 X 1 0 1
16–20. (a) Nonvolatile (b) Volatile 1 0 1 1 X 1 0 0
(c) Volatile (d) Nonvolatile 1 1 0 0 X 0 1 1
1 1 0 1 X 0 1 0
16–21. 2864 1 1 1 0 X 0 0 1
1 1 1 1 X 0 0 0
16–22. (a) Address 020H in the second EPROM
(b) Address ABCH in the first EPROM 16–30. Location 7AH contains 0110 0101 (65).
(c) No EPROM 16–31. (c), (d), (e), (f)
(d) Address FFFH in the fourth EPROM
16–32. (a) By the polarity (N-S) or (S-N) of magne-
16–23. tized particles.
(b) By the reflection or nonreflection of a
RD EN1 0 8000 - 8FFF laser beam off a specific bit area on the
0 EN2 9000 - 9FFF CD or DVD.
A15 EN3 A000 - AFFF
16–33. (a) Hard disk
B000 - BFFF
(b) DVD
A12 A0 16–34. A 1 on a CD-RW can be returned to its
A13 A1 0-level by reapplying heat at a lower level
A14 A2 7
to return the silver alloy back to its crys-
talline (reflective) state.

16–35. 32k * 8 17–6.

16–36. 128k * 8, 64k accessible
16–37. (a) 8k * 8
(b) SMN_SEL, MON_SEL
(c) A000H–BFFFH
(d) E000H–FFFFH
E16–1. (a) The D flip-flop only captures data at
the instant C is pressed.
(b) Outputs are all stuck LOW.
E16–2. (a) O2 (b) O4
(c) O0 (d) none
17–7. The input port has three-stated outputs so
Chapter 17 that it can be disabled when it is not being
17–1. A microprocessor-based system would be read.
used whenever calculations are to be made, 17–8. CE, RD
decisions based on inputs are to be made, a 17–9. 216 (65,536)
memory of events is needed, or a modifi-
able system is needed. 17–10. LDA, load accumulator; 4000H, address
where the data to be loaded are
17–2. Data bus, 8 lines; address bus, 16 lines
17–11. It stores the contents of the accumulator
17–3. The address bus is used to select a particu- out to address 6000H.
lar location or device within the system.
17–12. B, C, D, E, H, L
17–4.
17–13. Instruction decoder and register: register
and circuitry inside the microprocessor that
receives the machine language code and
produces the internal control signals
required to execute the instruction.
17–14. Because it contains the 16-bit address of
the next instruction to be executed.
17–15. (1) Pulse: read memory location 2000
(LDA) (2) and (3) Pulse: read address
bytes at 2001, 2002 (4000H) (4) Pulse:
read data at address 4000H
17–16. The WR line is used to clock the data on
the data bus to the output port D flip-flop.
17–17. A high-level language (FORTRAN, BASIC,
17–5. etc.) has the advantage of being easier to
write and understand. Its disadvantage is
74LS244 that the programs are not memory efficient.
I0 O0 17–18. Memory-mapped I/O:
I1 O1 (a) LDA addr
I2 O2 (b) STA addr I/O-mapped I/O:
From I3 O3 To (c) IN Port
Input Data
Switches
I4 O4
Bus
(d) OUT Port
I5 O5 17–19. (a) LOW (b) LOW
I6 O6 CE from
address decoder (c) HIGH (d) HIGH
I7 O7
RD from 17–20. (a) IN FCH; OUT F8H
OEa OEb μp control bus (b) IN 3FH; OUT 3EH
17–21. U6a and U6b are drawn as inverted-input
NAND gates to make the logical flow of
the schematic easier to understand.

17–22. The LEDs are active LOW (low on Chapter 18

Qn : LED is ON).
18–1. Because it has RAM, ROM, I/O Ports, and
17–23. (a) IN instruction, RD is pulsed LOW. a Timer/Counter on it.
(b) OUT instruction, WR is pulsed LOW.
18–2. 8031 has no program memory, 8051 has
17–24. (1) A8 to A15 = FFH 4K ROM, 8751 has 4K EPROM.
(2) IO>M = HIGH
18–3. Extra 4K ROM, 128 bytes RAM, 16 bit
(3) RD = LOW Timer/Counter, 1 interrupt.
17–25. (1) A8 to A15 = FEH 18–4. High order address lines A8–A15.
(2) IO>M = HIGH
18–5. High
(3) WR is pulsed LOW/HIGH
18–6. 64K(each)
17–26. The accumulator
18–7. 80H - FFH
17–27. MVI A, 4FH
18–8. P0, 80H; P1, 90H; P2, A0H; P3, BOH
17–28. JZ LOOP is a conditional branch that will
cause the processor to jump to the address 18–9. By reading the two bank-select bits
of the label LOOP if the zero flag is set. (D0H.3, D0H.4) in the PSW.
17–29. 2010 3E INIT: MVI A, O4H 18–10. Because the 8155 uses the ALE signal to
2011 04 internally demultiplex the address/data
2012 3D * 1: DCR A lines. The 2732 needs the A/D lines demul-
2013 CA JZ INIT tiplexed externally.
2014 10 18–11. (a) A = 40H
2015 20 (b) A = 88H
2016 C3 JMP *1 (c) A = 88H
2017 12 (d) A = 40H
2018 20 18–12. (a) A = 22H
17–30. (a) U2, U6, U7, U16, M1 (b) A = 33H
(b) U2, U6, U7, U16, U5, U9, U3:C, M1 (c) A = 40H
17–31. LCD_SL KEY_SL (d) A = 33H
AD3 0 1 18–13. (a) MOV P3, #0C7H
AD4 0 0 (b) MOV R7, P1
AD5 0 0 (c) MOV A,#55H
AD11 1 1 (d) MOVA,@R0
AD12 1 1 (e) MOV P0,R1
AD13 0 0 18–14. READ: MOV A, P0
AD14 0 0 CJNE A,#0A7H,READ
AD15 0 0 MOV P1,#0FFH
18–15. START: MOV A,#20H
17–32. (a) A2, 8031
LOOP: MOV P1,A
(b) U11, ALE
INC A
(c) U3, PSEN
CJNE A, #91H,LOOP
E17–1. (a) LOW JMP START
(b) Press C
18–16. (a) A = 36H
(c) Put 7C on the switches, Make OE¿ = 0
(b) A = 77H
(Data appears on the data bus), Press C
(c) A = 76H
(data appears at output port if OE¿ (G) is
LOW.)

18–17. (a) A = 75H 18–21.

(b) A = F5H X8
(c) A = EBH A8
A 12
18–18. MOV R7,#10H
X1
18–19. MOV A,P0 A9
A 13
ADD A,#05H X4
MOV P1,A X2 P3 . 4
A 10
18–20. RO LOOP 256 * 2 ms = 512 ms A 14
R1 LOOP 256 * 1512 ms + 2 ms2 X3
DELAY = 131,584 ms A 11
A 15
X4
18–22. (a) A2, 8031

(b) U11, ALE
(c) U3, PSEN

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Solutions and Answers to

1–15. (a) 010 0101 (b) C

1–17. (a) Tank A, temperature high; tank C, l 23 1

(c) Tanks B and D, pressure high 26 1

(d) Tanks B and C, temperature high 27 0

2–6. D1 = REV D8 = REV

2 SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS

2–13. The transistor is cutoff; Chapter 3

SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS 3

4 SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS

3–28. X = AB, Y = CD 3–35.

SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS 5

3–41. E3–5. (a) Vcc

6 SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS

SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS 7

8 SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS

SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS 9

5–18. (a) X = AB + (B + C) 5–21.

10 SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS

SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS 11

5–36. 5–44. The output (pin 8) would be stuck high.

E5–6. (a) Ten

E5–7. X = AB¿C¿ + A¿BC¿ + AB¿C

12 SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS

E5–13. (a) AND Chapter 6

E5–17. (a) U1b is bad (b) U1a is bad 6–4. W = AB – A + B = AB + A B (ex-NOR)

E5–24. (a) X = (A¿B¿)¿

SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS 13

6–6. 6–12. Odd

6–15. Yes; LOW

14 SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS

6–17. 7–5. +15 0000 1111 -1 1111 1111

SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS 15

7–10. 7–20. From Figure 7–5(c),

7–24. When using more than one adder, IC to add

16 SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS

SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS 17

8–2. (a) See top numbers.

8–3. (a) 8–5.

18 SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS

8–10. Time Low output 8–16.

8–11. All HIGH

SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS 19

8–21. See #20 (lower numbers).

A15 disables the ¿138

20 SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS

8–32. (a) Assuming NC = 0, Port 1 will read 8–41.

Read DT5 (b) NOR

SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS 21

E8–6. E8–9. (a) 00

22 SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS

9–7b. [LS] 9–14. (a) The Commercial 74LS00 (8 mA)

SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS 23

24 SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS

10–12. It is called “transparent” because the Q

10–17. The 7474 is edge-triggered; the 7475 is

SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS 25

10–27. long as the positive timing pulses are very

10–33. The ¿373 is a transparent latch. If the

26 SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS

SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS 27

28 SOLUTIONS AND ANSWERS TO IN-TEXT PROBLEMS