Asynchronous Transmission

• asynchronous: transmitter and receiver do

Asynchronous Serial
Communications & UARTS
55:036
Embedded Systems and Systems
not share a common clock or explicitly
coordinate the exchange of data
– Transmitter can wait arbitrarily long between
transmissions
– Receiver must figure out how to properly extract
data from the received waveform
• when a new character starts
• the individual bits of the character

Software – Used, for example, when transmitter such as a

keyboard may not always have data ready to send

Possible Signaling Schemes Transmission Timing Issues

• Encoding scheme leaves several questions unanswered:
– How long will each bit last?
– How will the transmitter and receiver agree on timing?
• Standards specify operation of communication systems
• Devices from different vendors that adhere to the standard
can interoperate
• Example organizations:
– International Telecommunications Union (ITU)
+
– Electronic Industries Association (EIA)
– Institute for Electrical and Electronics Engineers (IEEE)
0 1 0 1 0 0 1 – International Standards Organization (ISO)
• RS232/422 is the prevailing standard for
asynchronous serial communications

1
 RS-232 RS-232 Signaling
• Standard for serial transfer of characters
across copper wire
• Produced by EIA
• Full name is RS-232-C
• RS-232 defines serial, asynchronous
communication
– Serial - bits are encoded and transmitted one at a
time (as opposed to parallel transmission)
– Asynchronous - characters can be sent at any
time and bits are not individually synchronized
• There is also a differential (twisted pair)
version of RS-232 intended to operate over
longer distances (RS-422)

RS-232 Signaling RS-232 Signaling

Logical 0 (space) Logical 0 (space)
between +3 v and +15 v. (nominally +12 V) between +3 v and +15 v. (nominally +12 V)

Logical 1 (Mark)
between -3 v and -15 v. (nominally -12 V)

2
 RS-232 Signaling RS-232 Signaling

Idle line is in Character transmission

“mark” state begins with a start-bit

RS-232 Signaling RS-232 Signaling

Followed by data bits Followed by (optional)
(7 or 8), LSB first parity bit

3
 A Logical View of the Previous
RS-232 Signaling
Followed by
Diagram
one or more stop
bits. Line will
stay in mark state Stop bit(s)
until start of next
character LSB MSB
transmission

1 0 0 0 0 0 1

Start Bit Seven data bits Even parity

Converting between RS-232 and Converting between RS-232 and

TTL Logic levels TTL Logic levels

Note: The
QwikFlash
Board uses
a simple two
line (plus GND)
RS-232
connection—
i.e. no RTS/CTS
flow control

4
 RS-232 Bit-level Synchronization RS-232 Bit-level Synchronization
Low-speed: Low-speed:

Note: Rx sampling
High speed; clock runs at 16x
baud rate

When Rx detects leading edge of start bit, it counts 8 ticks of

sampling clock to locate middle of start bit. Then strobes
remaining bit values as 16-tick intervals

Doing RS-232 on a Microcontroller Using the PIC UART

• Two ways:
– In software—”bit-banging”
– via a Universal Asynchronous
Receiver/Transmitter (UART)
• Once the UART is configured, it does all
the work
– To transmit a byte, simply write it to the
UART’s TXREG
– To receive a byte, simply read it from the
UART’s RXREG

5
 Using the PIC UART Using the PIC UART
• Once the UART is configured, it does all • Once the UART is configured, it does all
the work the work
– To transmit a byte, simply write it to the – To transmit a byte, simply write it to the
UART’s TXREG UART’s TXREG
– To receive a byte, simply read it from the – To receive a byte, simply read it from the
UART’s RXREG UART’s RXREG

The transmitter interrupt flag (TXIF) is cleared The receiver interrupt Flag (RXIF) is set when an incoming
by a write to TXREG and set when transmission data byte is available in the RXREG. Automatically
of the byte is complete cleared when the data is read from the RXREG

Using the PIC UART Using the PIC UART, continued

• Once the UART is configured, it does all • The UART can be configured to generate
the work interrupts from:
– To transmit a byte, simply write it to the – The RXIF bit (Rx data ready)
UART’s TXREG • The ISR should read RXREG to receive the new
– To receive a byte, simply read it from the incoming byte
UART’s RXREG – The TXIF bit (Tx ready)
• The ISR should send the next outgoing byte to the
TXREG or disable further TXIF interrupts if no
more bytes to send
The UART has a small (2 byte) internal RX queue (FIFO) in case the
PIC runs behind in reading incoming bytes from the RXREG

6
 The UART Clock Generator The UART Clock Generator

Eight bit counter, clocked at fosc

The UART Clock Generator The UART Clock Generator

Determined by BRGH

Baud Rate:
fosc/(SPBRG+1)16
Eight bit counter, clocked at fosc Eight bit counter, clocked at fosc or
fosc/(SPBRG+1) fosc/(SPBRG+1)
fosc/(SPBRG+1)64

7
 Setting the Baud Rate Achievable Baud rates (BRGH=1)

BRGH=1 BRGH=0
(High rate) (Low Rate)
Baud Rate =

Achievable Baud Rates (BRGH=0) Additional UART Configuration

Details
• Consult:
– PIC Data Sheet
– Chapter 18 in the text