Low-Voltage SOI CMOS DTMOS/MTCMOS Circuit Technique for Design

Optimization of Low-Power SOC Applications

W. C. H. Lin and J. B. Kuo

Dept of Electrical Engineering, BL-528
National Taiwan University
Taipei, Taiwan 106
Email: jbkuo@cc.ee.ntu.edu.tw

Abstract- This paper reports a 0.5V SOI II. DTMOS/MTCMOS Circuit Technique
CMOS dynamic-threshold MOS (DTMOS)/
dual-threshold (MTCMOS) circuit technique
for design optimization of low-power SOC
applications. Via the DTMOS/non-DTMOS
technique for implementing the SOI version
of the gate-level dual-threshold static
power optimization methodology
(GDSPOM), a 16-bit multiplier circuit has
been designed, showing a performance
with 30% less power consumption as
compared to the one designed purely in
DTMOS, at a power supply voltage of 0.5V.
Fig. 1 Cross section of the 90nm SOI CMOS
technology.
I. INTRODUCTION

Nanometer SOI CMOS technology has

becoming another mainstream technology for
implementing low-power VLSI systems for
SOC applications using a low power supply
voltage [1]. Dynamic threshold CMOS
(DTMOS) circuit technique has been reported
for enhancing the speed performance of SOI
digital circuits using a low power supply
voltage [2]. CMOS dual-threshold (MTCMOS)
technique has been renowned for their
capabilities in optimization of VLSI systems
balanced between low power and high speed
[3]. The gate-level dual-threshold static power
optimization methodology (GDSPOM) for VLSI
systems has been reported [4]. In this paper,
via the DTMOS/MTCMOS technique for
implementing the SOI version of GDSPOM, a
16-bit multiplier circuit has been designed,
shows a 30% reduction in power consumption
at the power supply voltage of 0.5V. In the
following sections, the principle of the SOI
DTMOS/MTCMOS circuit technique is
described first, followed by the SOI GDSPOM
procedure, performance of the test multiplier
circuit, discussion and conclusion.
Fig. 2 N-channel and p-channel SOI devices
using DTMOS/MTCMOS technique.
For a 90nm SOI technology with multi-
threshold (MTCMOS) capability as shown in
Fig. 1, high-threshold (HVT) and low-threshold
(LVT) devices are available. HVT devices have
low leakage current but the on current is small.
LVT devices have a large on current, however,
their leakage current when the device is off,
may not be acceptable for low-power
applications. Based on a 90nm SOI CMOS
technology with dual-threshold devices,
NMOS/PMOS device could be designed with
an auxiliary device with its gate controlled by
the gate of the main transistor and the source
connected to the body such that the dynamic

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 Fig. 4 0.5V NAND logic gate circuit with its
Fig. 3 Drain current characteristics of the n/p- layout using the SOI DTMOS/MTCMOS
channel SOI devices using the technique in a 90nm SOI CMOS
DTMOS/MTCMOS technique and technology.
without (non-DTMOS) biased at
∣VDS∣=0.5V.

threshold (DTMOS) capability at a low power

supply voltage as shown in Fig. 2 could be
facilitated- SOI DTMOS technique. As shown
in Fig. 3, adopting the dual threshold
(MTCMOS) technique with a small aspect ratio
for the auxiliary LVT device (0.12μm/90nm)
and a large aspect ratio for the main HVT
device (1μm/90nm), the SOI DTMOS device
could be further enhanced to combine the best
of HVT and LVT devices- it has a low leakage
current in the subthreshold region due to the
dominance of the main HVT device since the
leakage current of the auxiliary LVT device
with a small aspect ratio could be neglected. In
the strong inversion region, its drain current is Fig. 5 Current and voltage waveforms during
enhanced owing to the addition of the auxiliary the pull-up transient of the 0.5V NAND
LVT device for lowering the magnitude of the logic circuit using the SOI
threshold voltage dynamically. It is a new SOI DTMOS/MTCMOS technique and
DTMOS device enhanced with the built-in without (non-DTMOS), with an output
dual-threshold (MTCMOS) technique- capacitive load of 20fF.
DTMOS/MTCMOS.
as compared to the non-DTMOS one while the
Fig. 4 shows the 0.5V NAND logic gate power consumption is similar.
circuit with its layout using the SOI
DTMOS/MTCMOS technique in a 90nm SOI Fig. 6 shows the propagation delay time
CMOS technology. Fig. 5 shows the current versus load capacitance during the pull-up and
and the voltage waveforms during the pull-up pull-down transients of the 0.5V NAND logic
transient of the 0.5V NAND logic circuit using gate circuit using the SOI DTMOS/MTCMOS
the SOI DTMOS/MTCMOS technique and technique and without (non-DTMOS). As
without (non-DTMOS), with an output shown in the figure, the propagation delay time
capacitive load of 20fF. As shown in the figure, of the SOI DTMOS/MTCMOS one is much
the propagation delay time of the circuit using better than the non-DTMOS one. At 20fF, the
the DTMOS/MTCMOS technique is improved delay time is shorter by over 35%.

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Fig. 6 Propagation delay time versus load
capacitance during the pull-up/down
transients of the 0.5V NAND logic gate
circuit using the SOI DTMOS/
MTCMOS technique and without (non-
DTMOS).
III. SOI GDSPOM PROCEDURE
Fig. 7 Flow chart of the SOI version of the
GDSPOM procedure.
Fig. 7 shows the flow chart of the SOI
version of the GDSPOM procedure used for
optimization of a VLSI circuit using the SOI
DTMOS/MTCMOS technique. As shown in the
figure, an RTL design is synthesized into gate-
level netlist of logic cells using SOI non-
DTMOS logic cells. Then, static timing analysis
(STA) is performed to report a list of logic cells
that are required to swap from non-DTMOS to
DTMOS/MTCMOS for meeting the timing
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requirements. Cell-swapping script is executed
to create the netlist of DTMOS/non-DTMOS
logic cells and to calculate the signal
propagation delays and the final static power
consumption. This completes the procedure of
the SOI version of GDSPOM.
IV. PERFORMANCE & DISCUSSION
Fig. 8 Number of timing violated paths in the
0.5V 16-bit multiplier using non-
DTMOS SOI logic gate cells.
Fig. 9 Schematic view of the 0.5V 16-bit
multiplier design optimized by the SOI
version of the GDSPOM procedure
with DTMOS/non-DTMOS logic cells.
To assess the performance of this SOI
DTMOS/MTCMOS circuit technique used for
the SOI version of the GDSPOM procedure for
low-power SOC applications, three 16-bit
multipliers with Wallace tree reduction
architecture based on the 90nm SOI
technology have been designed. Three

Fig. 10 Timing path from IN110 to P28 in the 16-
bit DTMOS/ MTCMOS multiplier
optimized by the SOI GDSPOM
procedure.
Fig.11Power consumption of the 16-bit
multipliers using all-non-DTMOS, all-
DTMOS, and DTMOS/non-DTMOS
optimized by the SOI GDSPOM
procedure.
designs are generated from the same RTL
source code except that one uses all non-
DTMOS logic cells. Another one has all
DTMOS/MTCMOS logic cells and the third one
contains both DTMOS/MTCMOS and non-
DTMOS logic cells optimized by the SOI
GDSPOM procedure. DTMOS/MTCMOS logic
cell library has been developed for use here.
Under a clock cycle of 2.5ns, Fig. 8 shows the
number of timing violated paths in the 0.5V 16-
bit multiplier using non-DTMOS SOI logic gate
cells. Over 4600 paths violate the timing
constraint. In this study, the SOI GDSPOM
procedure reassigned 2574 cells out of 5371 in
the multiplier circuit to swap from non-DTMOS
to DTMOS/MTMOS. Fig. 9 shows the
schematic view of the 0.5V 16-bit multiplier
design optimized by the SOI version of the
GDSPOM procedure to generate the DTMOS
(red) and non-DTMOS (blue) logic cells.
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Yellow lines indicate the originally timing
violated paths.
Fig. 10 shows the signal path from the input
IN110 to the output P28 of the multiplier circuit
using the DTMOS/non-DTMOS approach.
After performing the SOI GDSPOM procedure,
41 cells have been swapped from non-DTMOS
to DTMOS. The data arrival time of this path is
2.28ns, which meets the operating frequency
requirement. Fig. 11 shows the power
consumption of the 16-bit multipliers using all-
non-DTMOS, all-DTMOS, and DTMOS/non-
DTMOS optimized by the SOI GDSPOM
procedure. Among three multipliers using all-
non-DTMOS, all-DTMOS, and DTMOS/non-
DTMOS cells, the all-non-DTMOS one has the
smallest power consumption of 48 μ W, not
meeting the speed requirement, while the all-
DTMOS one has the largest-171μW. Using
the DTMOS/non-DTMOS cells optimized by
the SOI GDSPOM procedure, the power
consumption is 119μW, which is 30% less as
compared to the all-DTMOS one. As shown in
the figure, the slower DTMOS/non-DTMOS
multiplier needs fewer DTMOS cells, hence
consumes less static power.
CONCLUSION
In this paper, a 0.5V SOI DTMOS/
MTCMOS circuit technique for design
optimization of low-power SOC applications
has been described. Via the DTMOS/non-
DTMOS technique for implementing the SOI
version of the GDSPOM procedure, a 16-bit
multiplier circuit has been designed, showing a
performance with 30% less power
consumption as compared to the one designed
purely in DTMOS, at VDD= 0.5V.
ACKNOWLEDGMENTS
This project is supported under a research
grant from National Science Council.
REFERENCES
[1] J.Kuo, “Low-voltage CMOS VLSI circuits,”
Wiley, New York, 1999.
[2] E.Shen, J.Kuo,”0.8V CMOS CAM Cell Ckt
Using BP-DTMOS Tech,” ISCAS Proc. IV,
p.583, 2002.
[3] S.Shigematsu, et al,”A 1V High-Speed
MTCMOS Ckt for Power-Down Application
Ckts” IEEE JSSC, pp.861, 1997.
[4] B.Chung and J.Kuo, “GDSPOM using path-
based STA technique for SOC application,”
Integration, VLSI Journal, p. 9, 2008.