III-V Integrated Circuit

Fabrication Technology
Shiban Tiku
Dhrubes Biswas
III-V Integrated Circuit
Fabrication Technology
III-V Integrated Circuit
Fabrication Technology
Shiban Tiku
Dhrubes Biswas
Published by
Pan Stanford Publishing Pte. Ltd.
Penthouse Level, Suntec Tower 3
8 Temasek Boulevard
Singapore 038988

Email: editorial@panstanford.com
Web: www.panstanford.com

British Library Cataloguing-in-Publication Data

A catalogue record for this book is available from the British Library.

III–V Integrated Circuit Fabrication Technology

Copyright © 2016 by Pan Stanford Publishing Pte. Ltd.
All rights reserved. This book, or parts thereof, may not be reproduced in any form
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ISBN  978-981-4669-30-6 (Hardcover)
ISBN  978-981-4669-31-3 (eBook)

Printed in the USA

 Contents

Preface xxiii
Acknowledgments xxvii

1.
Semiconductor Basics 1
1.1 Introduction 1
1.1.1 GaAs Device Applications 2
1.2 GaAs Crystal Structure 3
1.3 Bonding in III–V Semiconductors 8
1.3.1 Bonding in a Doped Crystal 9
1.4 Energy Band Structure 9
1.4.1 Band Structure and Mobility 13
1.4.2 Free Carrier Concentration and
Fermi Level 14
1.4.3 Energy Levels in Doped Semiconductors 17
1.4.4 Impurities in GaAs 20
1.4.4.1 Specific impurities 22
1.5 Crystal Defects 23
1.5.1 Point Defects 24
1.5.2 Dislocations 25
1.5.3 Other Defects 27
1.6 Other Properties 27

2. GaAs Devices 31
2.1 p–n and Metal–Semiconductor Junctions 31
2.1.1 p–n Junction Physics 31
2.1.1.1 I–V characteristics 33
2.1.1.2 Space charge and junction
capacitance 36
2.1.2 Metal–Semiconductor Junctions 38
2.1.2.1 Junction physics 39
2.1.2.2 Junction characteristics 43
2.2 MESFETs 45
2.2.1 Basic MESFETs 45
2.2.2 Low-Noise FETs 50
2.2.3 FETs for Digital Logic Circuits 51
vi Contents

2.3
HEMTs and PHEMTs 52
2.3.1 Device Operation 54
2.4 Bipolar Junction Transistors 54
2.4.1 Phenomenological Description of
the BJT 55
2.4.2 Current–Voltage Characteristics
of a BJT 60
2.5 HBT Principles of Operation 61
2.5.1 Basic Transport Equations 62
2.5.2 Current Gain and Injection Efficiency 63
2.5.3 Figures of Merit for HBTs 65
2.6 PIN Diodes 66
2.7 IMPATT 68
2.7.1 Read-Type IMPATT 69
2.8 Gunn Diodes 69
2.9 MOSFET 70
2.9.1 Metal–Insulator–Semiconductor
Devices 71
2.9.2 I–V Characteristics 73
2.10 Remarks on Applications 76

3. Phase Diagrams and Crystal Growth of Compound

Semiconductors 79
3.1 Phase Diagrams 79
3.1.1 Introduction 79
3.1.2 Phase Diagram Types 80
3.1.2.1 Isomorphous phase diagram 81
3.1.2.2 Eutectic diagrams 81
3.1.2.3 Peritectic diagrams 82
3.1.3 Congruent Transformation 83
3.2 Crystal Growth 84
3.2.1 Starting Materials and Compounding
Method 85
3.2.2 Single-Crystal Growth 86
3.2.2.1 Bridgman/gradient freeze
technique 87
3.2.2.2 Liquid-encapsulated
Czochralski method 88
3.2.2.3 Vertical boat and vertical
gradient freeze methods 89
 Contents vii

3.2.2.4 Vapor pressure–controlled

Czochralski method 91
3.2.3 InP Crystal Growth 91
3.3 Doping and Resistivity Control 92
3.3.1 n- and p-Type Crystals 94

4. Epitaxy 97
4.1 Liquid-Phase Epitaxy 98
4.2 Vapor-Phase Epitaxy 99
4.2.1 System Configuration 99
4.2.2 VPE Chemistries for GaAs 101
4.2.2.1 Substrate orientation 101
4.2.2.2 Halide process Ga–AsCl3–H2 101
4.2.2.3 Hydride process
Ga–AsH3–HCl–H2 103
4.2.3 MOCVD 103
4.2.3.1 Process control and
mechanisms 105
4.2.3.2 MOCVD sources 110
4.2.3.3 Doping 110
4.2.3.4 HBT growth 114
4.2.3.5 Volume production 115
4.2.3.6 Specific materials 117
4.2.3.7 Selective epitaxy 119
4.2.3.8 In situ monitoring of
epigrowth 119
4.3 Molecular Beam Epitaxy 120
4.3.1 System Description 120
4.3.2 MBE Sources 122
4.3.2.1 RHEED intensity oscillation 123
4.3.3 Specific Materials 124
4.3.3.1 AlGaAs 124
4.3.3.2 InGaAs 124
4.3.3.3 InGaAlAs 124
4.3.3.4 GaN and related alloys 124
4.3.4 Doping 125
4.3.5 HBT Growth 126
4.3.5.1 AlGaAs HBT 126
4.3.5.2 InGaP HBT 127
viii Contents

4.3.5.3 InP HBT 127

4.3.5.4 GaN HBT 128
4.3.6 PHEMTs 128
4.4 Atomic Layer Epitaxy 129
4.4.1 GaAs on Silicon Substrates 130
4.5 Epilayer Characterization 132
4.6 Concluding Remarks 132

5. Photolithography 137
5.1 Introduction 137
5.2 Mask Making 138
5.3 Basics of Printing/Imaging 139
5.3.1 Typical Etch Photoresist Process 143
5.3.2 Lift-Off Photoresist Process 143
5.4 Photoresist 145
5.4.1 Resolution and Contrast 147
5.4.2 Sensitivity 148
5.4.3 Optical Photoresist Reaction Mechanism 149
5.4.4 Image Reversal of a Positive Photoresist 149
5.4.5 Negative Resists 150
5.4.6 Resolution Improvement 152
5.5 Physics of Photolithograpy 152
5.5.1 Diffraction 152
5.6 Step and Repeat Projection Aligner 156
5.7 Pattern Registration 156
5.8 Resist Processing 157
5.8.1 Prebake Dehydration 157
5.8.2 Adhesion Promoter 157
5.8.3 Resist Coating 158
5.8.4 Soft Bake 158
5.8.5 Exposure 159
5.8.6 Standing Waves and Other
Interference Effects 160
5.8.7 Developing 162
5.8.8 De-scum 163
5.8.9 Postbake 163
5.8.10 Stripping 163
5.9 Electron Beam Lithography 164
5.10 X-Ray Lithography 165
5.11 Process Monitoring 166
 Contents ix

5.11.1 Optical Systems 167

5.11.2 SEM 167
5.11.3 Advanced Photolithography
Techniques 168

6.
Wet Etching, Cleaning, and Passivation 169
6.1 Introduction 169
6.1.1 Wet Etch Advantages 170
6.1.2 Wet Etch Disadvantages 170
6.2 GaAs Etching Basics 171
6.2.1 Mechanism 173
6.3 GaAs Etch Chemical Systems 175
6.3.1 Hydrogen Peroxide–Based Etches
6.3.1.1 H2SO4:H2O2:H2O system 176
6.3.1.2 H3PO4:H2O2:H2O system 176
6.3.1.3 Citric acid system (C3H4(OH)
(COOH)3 H2O:H2O2:H2O) 177
6.3.1.4 Ammonia peroxide system
(NH4OH:H2O2:H2O) 177
6.3.1.5 HCl-based systems 178
6.3.2 Special Etches 178
6.3.2.1 Polishing etches 178
6.3.2.2 Crystallographic etches 179
6.3.3 Wet Etches 179
6.3.3.1 InP 179
6.3.3.2 InGaP 179
6.3.3.3 InGaAs 180
6.3.4 Wet Etching of GaN/AlN 181
6.3.5 Etching of Other Materials 181
6.4 Wet Etching in Production 181
6.4.1 Wet Etch Application Examples 182
6.4.1.1 Ion damage avoidance 182
6.4.1.2 Wet etching of multilayer
III–V compounds 184
6.5 Cleaning 185
6.5.1 Plasma Cleaning 187
6.6 Surface Passivation 187
6.6.1 Wet-Chemical Passivation 187
6.6.2 Chalcogenide Passivation 188
6.6.3 Dielectric Passivation 188
x Contents

7. Plasma Processing and Dry Etching 191

7.1 Plasma Processing 191
7.1.1 Plasma Basics 191
7.1.2 Glow Discharge Plasma 192
7.1.3 Voltage Distribution 195
7.1.4 Interaction of Ions with a
Surface/Sputter Yield 199
7.2 Dry Etching 202
7.2.1 Problems with Wet Etching 202
7.2.2 Advantages of Dry Etching 202
7.3 Plasma Etch Systems 204
7.3.1 Reaction Basics 204
7.3.2 Rate Equation 206
7.3.3 Process Parameters 207
7.3.4 Plasma Etch System Types 208
7.3.4.1 Barrel reactor 208
7.3.4.2 Parallel-plate planar reactor 209
7.3.4.3 Downstream reactor 211
7.3.4.4 High-density plasma reactor 211
7.3.4.5 ECR 212
7.3.4.6 ICP 212
7.3.4.7 Ion milling 213
7.4 Etch Processes 214
7.4.1 Etch Rate and Selectivity 215
7.4.1.1 Loading 215
7.4.1.2 Selectivity 216
7.4.1.3 Uniformity 216
7.4.1.4 Microuniformity 217
7.4.2 CD and Etch Profile 217
7.5 Plasma Etching of Materials Used in III–V IC
Processing 218
7.5.1 Selective Etches 219
7.5.2 Silicon Nitride and Oxide Etching 221
7.5.3 Metal Etching 222
7.5.3.1 Refractory metals 224
7.5.3.2 Aluminum 224
7.5.3.3 Gold/copper 224
7.5.3.4 Organic films 225
7.6 High-Aspect-Ratio Etching 225
7.6.1 Through-Wafer Via Etching 225
 Contents xi

7.6.1.1 Etch chemistry for profile

control 226
7.6.2 Wet Etching 226
7.6.3 Aspect-Ratio-Dependent Etching 228
7.7 Plasma Damage 230
7.7.1 Particle and Veil Generation 232
7.8 Etch Process Monitoring 232
7.8.1 Film Monitoring 233
7.8.2 Gas-Phase Monitoring 233
7.8.3 Optical Emission 233

8. Deposition Processes 237

8.1 Physical Vapor Deposition: Introduction 237
8.2 Vacuum Basics 238
8.2.1 Flow Regimes 240
8.3 Pumping Systems for Semiconductor
Processing 241
8.3.1 Cryogenic Pumps 241
8.3.2 Turbomolecular Pumps 242
8.4 Pressure Measurement 243
8.5 Evaporation 244
8.5.1 Evaporation Sources 245
8.5.1.1 Electron beam sources 246
8.5.2 Deposition Rate 247
8.5.2.1 Vapor pressure 247
8.5.2.2 Evaporation rate 248
8.5.2.3 Film thickness variation 249
8.5.3 Deposition Rate Monitors 251
8.5.4 Alloy Deposition 252
8.5.5 Film Growth Mechanism 252
8.6 Sputter Deposition 255
8.6.1 Advantages of Sputter Deposition 255
8.6.2 Deposition System Types 256
8.6.2.1 Planar diode 256
8.6.2.2 Triode 256
8.6.2.3 Magnetron sputtering 257
8.6.3 RF Sputtering 258
8.6.4 Reactive Sputtering 259
8.6.5 Bias Sputtering 259
8.6.5.1 System selection 260
xii Contents

8.6.6 Mechanism and Rates 261

8.7 Plasma-Enhanced Chemical Vapor Deposition 264
8.7.1 Film Requirements 264
8.7.2 CVD Systems 265
8.7.2.1 CVD reactor types 265
8.7.3 Plasma-Enhanced CVD 267
8.7.4 Production Multistation System 267
8.7.4.1 High-density plasma systems 270
8.8 Atomic Layer Deposition 270
8.8.1 ALD Principles 270
8.8.2 ALD Reactors 272

9. Ion Implantation and Device Isolation 275

9.1 Introduction 275
9.1.1 Advantages 276
9.1.2 Disadvantages 276
9.2 Ion Implantation: Theory 276
9.2.1 Theory of Ion Stopping 277
9.2.2 Channeling 283
9.2.3 Transverse Effects 283
9.2.4 Implant Damage 284
9.3 Ion Implantation Systems 286
9.3.1 Implantation System Parts 287
9.3.1.1 Ion source 287
9.3.1.2 Ion extraction and analyzing
device 288
9.3.1.3 Accelerator tube 289
9.3.1.4 Beam scanning system 289
9.3.1.5 System end station 289
9.3.2 Ion Implanter Types 290
9.4 System/Process Issues 291
9.4.1 Masking Considerations 291
9.4.2 Doubly Ionized Species 292
9.5 Common Ion Implant Species for GaAs 292
9.5.1 n-Type Dopants 292
9.5.2 p-Type Dopants 295
9.5.3 Implants for Isolation 295
9.6 Ion Implant Characterization 296
9.6.1 Sheet Resistivity Monitoring 296
9.6.2 Optical Dosimetry 296
 Contents xiii

9.6.3 C–V Method 296

9.7 Implant Activation 297
9.7.1 Annealing 297
9.7.2 Encapsulation for Annealing 299
9.7.3 Rapid Thermal Annealing 299
9.7.3.1 History of development 301
9.7.3.2 System description 301
9.7.3.3 Temperature control 302
9.7.4 Process Description 303
9.8 Activation of Dopants 303
9.8.1 n-Type Dopants 303
9.8.2 p-Type Dopant Activation 305
9.9 Device Isolation 306
9.9.1 Introduction 306
9.9.2 Isolation by Etching 307
9.9.3 Ion Implant Isolation 307
9.9.4 Mechanism 310
9.9.5 Isolation-Related Reliability Issues
for HBT 310

10. Diffusion in III–V Compound Semiconductors 315

10.1 Introduction 315
10.1.1 Rate Equations 316
10.2 Diffusion Basics 317
10.2.1 Basic Mechanisms 317
10.2.1.1 Interstitial mechanism 317
10.2.1.2 Substitutional mechanism 318
10.2.1.3 Kick-out mechanism 319
10.2.1.4 Interstitial-substitutional
mechanism 319
10.2.2 Impurity Diffusion Rates in GaAs 320
10.3 Diffusion Equations for III–V Semiconductor
Processing 321
10.3.1 Constant Diffusion Coefficient 322
10.3.1.1 Thin-film solution 322
10.3.1.2 Diffusion from a constant
source 323
10.3.1.3 Diffusion from a limited
source 324
xiv Contents

10.3.1.4 Concentration-dependent
diffusion coefficient 325
10.3.2 Interstitial-Substitutional Diffusion 325
10.4 Measurement of Diffused Layers 325
10.5 Diffusion in GaAs 326
10.5.1 Diffusion by Periodic Table Groups 326
10.5.2 Zn Diffusion in GaAs 327
10.5.3 Sulfur Diffusion in GaAs 329
10.6 Diffusion Systems 329
10.7 Rapid Thermal Diffusion 333

11. Ohmic Contacts 335

11.1 Introduction 335
11.2 History 336
11.3 Theory of Metal–Semiconductor Ohmic
Contacts 337
11.3.1 Contact Resistance 339
11.4 Contact Resistance Measurement by TLM 340
11.5 Ohmic Contact Technology for n-Type Contacts 345
11.5.1 Epigrown Contacts 345
11.5.1.1 Contacts with heavy donor
doping 345
11.5.1.2 Contacts with lower barrier
height 346
11.5.2 Alloyed Ohmic Contacts 346
11.5.2.1 Gold:germanium contacts 346
11.5.2.2 Silicon:tin contacts 347
15.2.2.3 Indium-based contacts 347
11.5.3 Ohmic Contact Deposition 348
11.5.4 Alloy Process and Alloying Systems 348
11.5.4.1 Alloying systems 349
11.5.5 Mechanism of Contact Formation 351
11.5.6 Refractory Contacts 351
11.6 Ohmic Contacts to p-Type GaAs 353
11.7 Ohmic Contacts to InP Devices 355
11.8 Ohmic Contacts to GaN 355
11.8.1 Mechanism 356
11.9 Ohmic Contact Corrosion 357
 Contents xv

12. Schottky Diodes and FET Processing 361

12.1 Schottky Diodes 361
12.1.1 Depletion Width 362
12.1.2 Schottky Diode Metallization 363
12.1.3 Reverse Breakdown 364
12.2 FET Gate Fabrication 365
12.2.1 Gate Metallization and Fabrication 365
12.2.2 Gate Recess Process 365
12.2.3 Gate Formation 366
12.2.3.1 T-gate 367
12.3 Digital FETs 369
12.3.1 Gate Fabrication 369
12.3.2 Self-Aligned n+-Technique 369
12.3.3 Substitutional Gate Processes 371
12.3.4 Mixed-Signal Process 371
12.4 Heterojunction and Insulated Gate FETs 372
12.4.1 HMESFET 373
12.4.2 SAG FET Technology: Remarks 374
12.5 Pregate Surface Preparation and Passivation 376
12.6 Current Developments 377

13. HEMT Process 379

13.1 Introduction 379
13.2 Device Fabrication 380
13.2.1 InGaP HEMT 384
13.2.2 Low-Noise Process 386
13.2.3 Power Amplifier Process 387
13.2.4 Switch Process 388
13.3 InP HEMT 390
13.4 Processing Issues 393
13.4.1 Gate Walk 393
13.4.2 Gate Sinking 394
13.4.3 Breakdown Voltage Improvement 396

14. HBT Processing 399

14.1 Introduction 399
14.2 Review of HBT Process Evolution 400
14.3 Basic HBT Fabrication Process 403
14.4 Self-Alignment 406
14.4.1 Base–Emitter Self-Alignment 407
xvi Contents

14.4.2 Other Self-Alignment Schemes 409

14.5 Collector-Up HBT 410
14.6 Common HBT Epimaterials 411
I4.6.1 InGaP/GaAs HBTs 411
14.6.2 InP HBTs 412
14.7 HBT Contacts 413
14.8 HBT Geometry 416
14.8.1 Base Width 416
14.8.2 Layout Comparison 417
14.9 HBT Fabrication Issues 418
14.9.1 Junction Considerations 420
14.10 HBT Epilayer Design 422
14.10.1 Emitter Layer Design 422
14.10.2 Collector Layer 423
14.10.2.1 Subcollector layer 424
14.10.3 Base Layer Design 424
14.11 Other HBT Structure Improvements 424
14.11.1 Graded-Base HBTs 426
14.11.2 Double-Heterojunction Bipolar
Transistor 426

15. BiFET and BiHEMT Processing 429

15.1 BiFET Process 430
15.1.1 Stacked Devices 430
15.1.2 Merged Devices 430
15.1.3 Guidelines for Extra Layers 433
15.1.4 Epitaxial Layer Screening 433
15.1.5 Fabrication Process 433
15.1.6 BiFET Gate Process 435
15.2 BiHEMT Process 439
15.2.1 BiHEMT Process and Yield
Improvement 444

16. MOSFET Processing 447

16.1 Introduction 447
16.2 Oxidation 448
16.2.1 Wet Oxidation 449
16.2.2 Liquid-Phase Oxidation 451
16.3 Dielectric Passivation 453
16.4 Atomic Layer Deposition 453
 Contents xvii

16.5 p-Type Devices 457

16.6 Concluding Remarks 458

17. Passive Components 461

17.1 Resistors 461
17.1.1 Semiconductor/GaAs Resistors 461
17.1.2 Thin-Film Resistors 464
17.1.3 Common TFR Materials 465
17.2 Capacitors 468
17.2.1 MIM Capacitors 469
17.2.2 Silicon Nitride for MIM 472
17.2.2.1 Stacked capacitors 476
17.3 Inductors 477

18. Interconnect Technology 483

18.1 Introduction 483
18.2 Interconnect Requirements 484
18.2.1 Electrical Requirements 484
18.2.2 Adhesion and Barrier Requirements 485
18.2.3 Diffusion and Electromigration
Effects 486
18.2.4 Interlevel Dielectric Layer
Requirements 487
18.3 Production Interconnect Processes 487
18.3.1 Baseline Gold Interconnect Process 487
18.3.2 Plated Metal Interconnect Process 490
18.3.3 Air Bridge Process 491
18.3.4 Digital GaAs Interconnect Process 493
18.4 Future of Interconnect Technology 494
18.4.1 Copper Interconnects 494

19. Backend Processing and Through-Wafer Vias 497

Section I: Through-Wafer Via Process 497
19.1 Introduction 497
19.2 Wafer Bonding 498
19.3 Wafer Thinning 500
19.4 TWV Photolithography 501
19.5 TWV Etch 502
19.6 Backside Metallization 504
19.6.1 Backside Plating 504
xviii Contents

19.7 Backside Street Etching 507

19.8 Wafer Demounting/Debonding 507
19.9 Wafer Dicing 508
19.9.1 Scribe and Break 508
19.9.2 Laser Dicing 509
Section II: Wafer-Bumping Process 510
19.10 Introduction 510
19.10.1 Advantages of the Wafer-Level
Bump Process 512
19.11 Requirements of Components of the Solder
Ball or Pillar Process 512
19.11.1 Underbump Metallurgy 512
19.11.2 Solder Ball and Pillar 514
19.12 Fabrication Process 514
19.12.1 Solder Ball Process 514
19.12.2 Copper Pillar Process 516

20. Electroplating 521

20.1 Electroplating History 521
20.2 Electroplating Fundamentals 521
20.3 Electroplating Bath Types 522
20.4 Electroplating Deposition Process 525
20.4.1 Pulse Plating 525
20.5 Metal Deposition Mechanisms 526
20.5.1 Polarization 526
20.5.2 Diffusion and Mass Transport 526
20.5.3 Microthrowing Power 527
20.5.4 Brightening 529
20.6 Process Monitoring 529
20.6.1 Hull Cell 529
20.7 Electroless Plating 530
20.8 Copper Electroplating 531
20.8.1 Large-Volume Production 532

21. Measurements and Characterization 535

21.1 Introduction 535
21.2 Sheet Resistance 535
21.2.1 Four-Point Probe Method 536
21.2.2 Van der Pauw Method 538
21.3 Contactless Resistivity Measurement 539
 Contents xix

21.4
Carrier Mobility 540
21.4.1 Hall Mobility 540
21.4.2 Drift Mobility 542
21.5 Doping Profile by C–V Method 543
21.6 Schottky Diode Parameter Measurement 544
21.6.1 Current–Voltage Method 546
21.6.2 Activation Energy Method 547
21.6.3 Capacitance–Voltage Method for
Schottky Diode Barrier Height
Measurement 547
21.7 FET Characteristics 549
21.7.1 FET Transconductance 549
21.7.2 FET Source Resistance Measurement 549
21.8 HBT Parameter Extraction 551
21.8.1 Output I–V characteristics 551
21.8.2 Gummel Plot 551
21.8.3 Emitter Resistance 551
21.8.4 VCE Offset 553
21.8.5 Ron 553
21.9 RF Characterization 553
21.9.1 Introduction 553
21.9.2 S-Parameter Measurements 554
21.9.3 RF Figures of Merit 557
21.9.3.1 VSWR 559
21.9.3.2 Load pull test 560
21.9.3.3 PAE 560
21.9.3.4 Linearity 560
21.9.3.5 Noise figure 561
21.9.4 Smith Chart 563
21.10 Film Thickness and Refractive Index 563
21.10.1 Ellipsometry 564
21.10.2 Interferometry 566
21.11 Film Stress Measurement 566

22. Reliability 571

22.1 Introduction 571
22.2 Basic Reliability Testing 572
22.3 Test Procedure 574
22.3.1 Step Stress Test 575
22.3.1.1 Temperature measurement 577
xx Contents

22.3.1.2 Simulation of operation 577

22.4 FET/HEMT Failure Modes and Mechanisms 578
22.4.1 Gate Sinking 579
22.4.2 Ion-Induced Failure Mechanisms 580
22.4.3 Effect of Hydrogen 580
22.4.4 Mobile Ion Contamination 581
22.4.5 Hot Electron Trapping 581
22.4.6 Surface State Effects 582
22.5 HBT Degradation and Reliability 582
22.5.1 HBT Reliability Issues Related to
Base Doping 584
22.5.2 Hydrogen and Ion Implant Isolation 587
22.6 Ohmic Contact Degradation 588
22.7 Other III–V IC Failure Mechanisms 588
22.7.1 Electromigration 588
22.7.2 Moisture Ingression and Corrosion 589
22.7.3 Stress-Induced Burnout 589
22.8 GaN Device Reliability 590

23. GaN Devices 593

Section I: GaN Electronic Devices 593
23.1 Introduction 593
23.2 Bulk Crystal Growth 594
23.2.1 Hydride Vapor-Phase Epitaxy 596
23.2.1.1 MOCVD templates 598
23.2.2 High-Pressure Solution Growth 599
23.2.3 Ammonothermal Growth 599
23.3 Epitaxial Growth 600
23.3.1 MBE 601
23.3.2 OMVPE 603
23.3.2.1 Doping 604
23.3.3 HVPE 605
23.4 Device Physics and Device Types 605
23.5 Process Technology 610
23.5.1 Etching and Surface Passivation
of GaN 610
23.5.2 Ohmic Contacts 610
23.5.3 Schottky Contacts 612
23.5.4 Implant Isolation 613
 Contents xxi

23.6 Device Fabrication 614

23.6.1 AlN/GaN HEMT 614
23.6.2 Device Performance Optimization 614
23.6.2.1 Surface passivation 617
23.6.3 Normally Off GaN Devices 617
23.6.4 MMIC Fabrication 617
23.7 Reliability 620
23.7.1 General Reliability Concerns 620
23.7.1.1 Gate sinking 620
23.7.1.2 Ohmic contacts 621
23.7.2 Current Collapse 621
23.8 III–N HBT Devices 624
23.8.1 GaN HBT Device Challenges 625
23.8.2 Current State-of-the-Art Performance 627
23.9 Other Devices 628
Section II: GaN Optical Devices 628
23.10 Introduction to LEDs 628
23.11 Junction Luminescence 629
23.11.1 Device Behavior: Electrical 632
23.11.2 Optical Characteristics 634
23.12 LED Processing 635
23.12.1 Visible LEDs 635
23.12.2 UV LEDs 637
23.12.3 Epitaxial Growth 638
23.13 Current Challenges 640
23.13.1 Current Performance 640
23.14 Introduction to III–N Lasers 641
23.14.1 Basic Principles 641
23.15 Diode Laser Fabrication 643
23.15.1 Fabry–Perot Semiconductor
Diode Laser 643
23.15.2 VCSEL 645

24. RF MEMS 651

24.1 Introduction 651
24.1.1 Differences with Silicon 652
24.2 Basics of MEMS 652
24.3 Ohmic Contact Switches 652
24.4 Capacitive Switches 653
xxii Contents

24.4.1 Electrostatic or Capacitive Excitation 653

24.4.2 Actuation Voltage 655
24.4.3 Piezoelectric Excitation 657
24.5 Process Technology 658
24.5.1 OMMIC Process 658
24.5.2 University of Illinois Process 660
24.6 Examples of Applications 661
24.6.1 Waveguide Switch 661
24.6.2 Fabry–Perot Filter 661
24.6.3 MEMS on MMIC 662
24.6.4 Hybrid Circuits 663

Appendix 667

Acronyms 673

Index 677
 Contents xxiii

Preface

In this Internet age, practicing engineers still need a book that they
can keep on their desk. This book is aimed for them and also graduate
students and engineers new to the field of III–V semiconductor
integrated circuit (IC) processing. This book specifically addresses
the needs of students who know semiconductor theory but lack
detailed processing knowledge. The content is chosen on the
basis of the needs of students as seen by a teacher and the needs
of practicing engineers dealing with processing issues as seen by
an experienced process engineer. GaAs processing has reached
a mature stage, a long way from a few decades ago, when it was
more of an art than a science. New semiconductor compounds are
emerging that will dominate future materials and device research;
however, the processing techniques used for GaAs will still remain
relevant. This book covers all aspects of the current state of the
art of III–V processing, with emphasis on heterojunction bipolar
transistors (HBTs), the volume leader technology, having grown
due to the explosive growth of wireless technology. The book’s
primary purpose is to discuss processing; only necessary equations
are derived and device behavior is discussed for the purpose of
understanding device figures of merit and electrical parameters that
engineers need to understand and control. All aspects of processing
of active and passive devices, from crystal growth to backside
processing, including lithography, etching, and film deposition, are
covered. New material systems based on GaN are playing a larger
role on the development side; although the etching chemistries,
deposition materials, and temperature regimes are different, similar
principles apply. The most promising structures of these material
systems and devices are covered in the book.
The book covers semiconductor material basics, physics of
devices used in semiconductor IC processing, and all the processing
technologies used in III–V semiconductor fabrication. In the
discussion, differences with silicon IC processes are emphasized.
Crystal growth and particularly epitaxy are discussed in depth
because of the special role played by them and device structures
xxiv Preface

made possible by them. Photolithography, ion implantation, wet

and plasma etching, and deposition of films are covered in detail.
Thermal processes and diffusion are discussed to the level needed for
III–V processing. Schottky and ohmic contact physics and processing
are discussed from a practical point of view for controlling these
in high-volume production. All the device technologies currently
in use in the III–V semiconductor marketplace are discussed in
depth, including recently introduced bipolar field-effect transistor
(BiFET) and bipolar high-electron-mobility transistor (BiHEMT)
technologies. Device types that are emerging and expected to be
important in the near future, like metal–oxide–semiconductor
field-effect transistors (MOSFETs), are also introduced. Passive
devices and interconnects are covered, being integral to monolithic
microwave integrated circuit (MMIC) fabrication. Also, backside
processing, which is absolutely necessary for high efficiency,
is described in detail and wafer-scale bumping is introduced,
being critical to future higher-frequency needs. Characterization
of films and semiconductor layers, as well as device parameter
measurement, is covered in detail. Reliability issues relevant to III–V
semiconductors are discussed. Finally, emerging GaN devices and
microelectromechanical systems (MEMS) are briefly described.
Most published books on the market emphasize III–V device
physics. No new processing book has been published in a decade.
Published books are old and cover mostly FET processing. Ralph
Williams’s book, Modern GaAs Processing, is over 20 years old and
does not cover processing technologies in detail. S. K. Ghandhi’s
book, VLSI Fabrication Principles: Silicon and Gallium Arsenide,
covers processing techniques in detail but IC processing very briefly.
This book is also old, published in the 1980s. Fazal Ali’s book, HEMTs
and HBTs: Devices, Fabrication and Circuits, covers fabrication
very broadly and was also published in 1991, over 20 years ago.
Baca and Ashby’s book, Fabrication of GaAs Devices, has a narrow
focus, specializing in cleaning and passivation; basic IC processing
techniques are not covered. It was published in 2005, a decade old
now.
This (present) book covers all aspects of processing, from
crystal growth to backside processing. It covers the current volume
production device types, HBTs, HEMTs, etc. The book is not restricted
to GaAs; other emerging III–V materials are covered, too.
 Preface xxv

Epigrowth, device structure, and processing discussions

are connected together through different chapters. Processing
techniques relevant to III–V IC fabrication are described as they are
used in III–V processing facilities in high-volume production. Process
flows are illustrated by step-by-step block diagrams. Scanning
electron microscopy (SEM) pictures of actual devices are included,
where needed. This is one book to find any topic relevant to III–V
processing. Practical process problems and ways to handle these are
described.
The current understanding of III–V processing has come a long
way from the era when GaAs processing was based on practical
knowledge and company trade secrets. This book attempts to connect
practice on the fabrication floor to current scientific understanding.
Shiban Tiku
Dhrubes Biswas
 Acknowledgments

The earlier books on GaAs and III–V semiconductor materials pro-

cessing were written in an era when GaAs was considered the “tech-
nology of the future.” This present work, although inspired by those,
is aimed at fulfilling the needs of this era in which the technology is
well established and perhaps becoming the “technology of the past,”
while paving the way for future technologies. Many minds and hands
have contributed to this work. I am indebted to all my teachers over
the years, who left an indelible mark on my life. I also thank the peo-
ple of India for the almost free education I received.
This book would not have been possible without support
from Skyworks Solutions’ management, Ravi Ramanathan, Nercy
Ebrahimi, and Andy Hunt, and IP council Donald Bollella, who
weighed the benefits of contributing to the III–V industry worldwide
over the risk of disclosing trade secrets. A lot of data came from my
fellow engineers at Skyworks and the CS MANTECH community
in general. Early feedback from Martin Brophy (Avago) and Peter
Asbeck (UCSD) encouraged me. In particular, help from the following
Skyworks colleagues is acknowledged: Heather Knoedler, Jens
Riege, Dave Crawford, Ravi Ramanathan, Mike Sun, Jiro Yota, Pete
Zampardi, Lance Rushing, Cristian Cismaru, Sam Mony, Lam Luu,
and Manjeet Singh. Constant support from my wife, Sushma, and
son, Vikram, helped me during difficult times. I am also thankful to
Archana Ziradkar of Pan Stanford Publishing for systematic editorial
help and to Barron Miller for drafting of many of the figures.
Shiban Tiku