Processing and Layout

David Johns and Ken Martin

University of Toronto
(johns@eecg.toronto.edu)
(martin@eecg.toronto.edu)

University of Toronto slide 1 of 34

© D.A. Johns, K. Martin, 1997
 Silicon Wafer
• Create 8” diameter cylinder (1m long) of single-crystaline
silicon with light doping (usually p-)
• Ingot cut into wafers about 1mm thick
Photolithography
• Portions of silicon wafer are masked out so processing can
be applied to remaining areas
• First create glass mask with dark areas using e-beam
(cost of mask set often >$50k)
• Thermally grow SiO2 on wafer, apply negative
photoresist, align glass mask and expose to UV light
• Photoresist hardens (after baking) where exposed to light,
remaining region removed (including SiO2)
• Negative since SiO2 removed where mask is light

University of Toronto slide 2 of 34

© D.A. Johns, K. Martin, 1997
 Photolithography
Ultraviolet light

Opaque
region Translucent
region
Glass
mask

p– substrate
Hardened photoresist, PR1 SiO2

University of Toronto slide 3 of 34

© D.A. Johns, K. Martin, 1997
 Diffusion
Gas containing phosphorus

2PH3 + 4O2

n well SiO2

p– substrate

• Introduce dopants where well will be located

• Phosphorus gas used in furnace (1000 ° C)

University of Toronto slide 4 of 34

© D.A. Johns, K. Martin, 1997
 Ion Implantation
Vertical and horizontal
deflection plates

Ion
beam
Separating Focusing Acceleration Target
slit lens plates

Focusing
lens
Ion source

• More control as can set concentration and thickness

• Acceleration sets depth, current and time set dosage
• However, lattice damage and narrow doping profile
— requires annealing

University of Toronto slide 5 of 34

© D.A. Johns, K. Martin, 1997
 Annealing
Ion dopant
concentration

Before annealing

After annealing

Depth into
silicon wafer

• Heat to 1000 °C then cool slowly

University of Toronto slide 6 of 34

© D.A. Johns, K. Martin, 1997
 Field-implants
Si3N4
PR3
Boron ions
PR2
PR2

n well

Field-implants
SiO2
p– substrate

• Ensures silicon under field-oxide will not invert (will

remain p-) although conductors above

University of Toronto slide 7 of 34

© D.A. Johns, K. Martin, 1997
 Field-oxide
Si3N4 SiO2 Field-oxide

n well

p+ field-implants
p– substrate

• Thick SiO2 where no transistors

• Wet process (H2O) — fast but more defects
• Dry process (O2) — slower but denser and higher quality
(high temp so called thermal oxide)

University of Toronto slide 8 of 34

© D.A. Johns, K. Martin, 1997
 Thin gate-oxide and threshold-adjust
Thin gate SiO2
Field-oxide

n well
Gate threshold-
voltage-adjust
p+ field-implants implant
p– substrate

• Thin oxide grown using dry process (0.01 µm )

• If n-well more heavily doped then single boron implant
will adjust
Vtn from -0.1V to 0.8V and
Vtp from -1.6V to -0.8V

University of Toronto slide 9 of 34

© D.A. Johns, K. Martin, 1997
 Polysilicon Gates
PR4
Polysilicon
SiO2 gate

n well

p+
p– substrate

• Apply gate but only heat to 650 °C — polysilicon (rather

than single crystal)
• 10 to 30 Ω ⁄ and thickness of 0.25 µm

University of Toronto slide 10 of 34

© D.A. Johns, K. Martin, 1997
 P+ Junctions
PR4 Polysilicon Polysilicon PR4
PR5 PR5

p+ p+ p+
n well
+ p+ p+
p p+
Substrate connection
p– substrate

• Gates and drains formed for p-channel

• Use ion implantation
• Self-aligned as gate determines edges
• Substrate connection also shown

University of Toronto slide 11 of 34

© D.A. Johns, K. Martin, 1997
 N+ Junctions
PR6 PR6
Polysilicon gates

n+ p+ p+ n+ p+ n+ n+
n
p+ p+ p+
Well tie Substrate tie
p-channel n-channel
junctions –
p substrate junctions

• p+ regions protected and n+ implanted

• Requires annealing after since ion implantation used
• Would melt gate if it were metal

University of Toronto slide 12 of 34

© D.A. Johns, K. Martin, 1997
 Final Cross Section
Overglass Metal 1 Polysilicon gate Via
Metal 2 CVD SiO2

n+ p+ p+ n+ p+ n+ n+
n
p+ p+ p+
p+ field-implant
Well tie Substrate tie Field-oxide

p-channel transistor p– substrate n-channel transistor

University of Toronto slide 13 of 34

© D.A. Johns, K. Martin, 1997
 Bipolar Cross Section
p+ poly n+ poly

Base Al Emitter Base

Collector

n+ poly

n+ n–

p+ n+ p+

p– substrate n+ SiO2
p+ p

University of Toronto slide 14 of 34

© D.A. Johns, K. Martin, 1997
 Transistor Layout

L
Active region
Polysilicon mask
Field-oxide region

5λ
λ Active-region mask Contact mask

4λ W 2λ

2λ
λ
2λ
Effective gate region
2λ
L

University of Toronto slide 15 of 34

© D.A. Johns, K. Martin, 1997
 Mask misalignment
Gate poly

Source junction Drain junction

Noncatastrophic
misalignment

Source-to-gate Source-to-drain
short circuit short circuit

University of Toronto slide 16 of 34

© D.A. Johns, K. Martin, 1997
 Series Transistor Layout
J3
J1 J2
Q1 Q2
λ 2λ 2λ J3 2λ

3λ

Less capacitance at node J1

Q
Q1 10λ
Q
Q2 J2
1 2
J3 since less area AND
not beside field implants
3λ

2λ
2λ 2λ

University of Toronto slide 17 of 34

© D.A. Johns, K. Martin, 1997
 CMOS Inverter
p+ junction
n+ well tie

λ
n well

Q2 VDD VDD

Q2 p-channel
transistor

Vin Vout
3λ
Poly
interconnect

Q1 Gnd λ 5λ
Active region

Metal interconnect

Vout

n-channel
Vin Q1 transistor

Gnd

n+ junctions
p+ substrate tie

University of Toronto slide 18 of 34

© D.A. Johns, K. Martin, 1997
 Single Large Transistor (4 in parallel)
Node 1 Metal interconnect

Active region

J1 J2 J3 J4 J5

Q1 Q2 Q3 Q4

Gates
Node 2 VG

University of Toronto slide 19 of 34

© D.A. Johns, K. Martin, 1997
 Schematic of Large Transistor
Node 1

J1 J2 J4 J5
J3
Q1 Q2 Q3 Q4

Node 2 VG
Node 1

Q 1 J2 Q 2 J2 Q3 J4 Q 4 J4
VG
J1 J3 J3 J5

Node 2

University of Toronto slide 20 of 34

© D.A. Johns, K. Martin, 1997
 Actual sizes different from Masks
SiO2 protection SiO2 protection Polysilicon gate

Well
Overetching

Lateral diffusion under SiO2 mask

Polysilicon gate Transistor channel

p+ field implants Channel width narrowing

University of Toronto slide 21 of 34

© D.A. Johns, K. Martin, 1997
 Common Centroid Layout for Diff Pair
DM1 SM1,M2

GM2
M1

M2

M2

M1

M1

M2

M2

M1

M1

M2
GM1

DM2

University of Toronto slide 22 of 34

© D.A. Johns, K. Martin, 1997
 Capacitor Errors due to Overetching
x1

x 1 – 2∆e

y 1 – 2∆e y1

∆e

True capacitor size

∆e
Ideal capacitor size

• Use unit sized capacitors as much as possible

• If not unit sized, keep the same perimeter-to-area ratio to
minimize errors

University of Toronto slide 23 of 34

© D.A. Johns, K. Martin, 1997
 Capacitor Layout
10 µm 10 µm

10 µm 10 µm
19.6 µm

6.72 µm

4 units 2.314 units

• Want to maintain ratio of 4 to 2.314
• Rectangular capacitor of size 1.314 units used
— has same perimeter-to-area ratio as square
— also has same number of corners

University of Toronto slide 24 of 34

© D.A. Johns, K. Martin, 1997
 Capacitor Layout Equation
• Assume K is non-unit sized and between 1 and 2
— otherwise use another unit sized capacitor
C2 A2 x2 y2
K ≡ ------ = ------ = ---------
- (1)
C1 A1 x1
2

• Can show that

y2 = x1 ( K ± K 2 – K ) (2)

(+/- simply changes orientation of rectangle and sqrt is

positive since K>1)
• Also
2
Kx 1
x 2 = --------- (3)
y2

University of Toronto slide 25 of 34

© D.A. Johns, K. Martin, 1997
 Example Capacitor Layout

Well contacts

Polysilicon bottom plate

C1 C2

Polysilicon top plates

C2 C1 Polysilicon edge matching

Well region

University of Toronto slide 26 of 34

© D.A. Johns, K. Martin, 1997
 Typical Resistor Layout
0.14

10

2.11

University of Toronto slide 27 of 34

© D.A. Johns, K. Martin, 1997
 More Accurate Resistor Layout

Dummy Dummy
resistor resistor

R1 R2 R1 R2

University of Toronto slide 28 of 34

© D.A. Johns, K. Martin, 1997
 Separate Analog and Digital Power Supplies
I/O pad

Analog power-supply net Digital power-supply net

• Connect analog and digital supplies together as close to

supply as possible

University of Toronto slide 29 of 34

© D.A. Johns, K. Martin, 1997
 Guard Ring to Sheild Analog
VDD

Analog Digital
region n+ region
p+ n well p+

Depletion region
p–substrate acts as bypass
capacitor

• Depth of well causes higher impedance since doping

usually higher near surface of p- substrate (perhaps 10
times higher resistance!)

University of Toronto slide 30 of 34

© D.A. Johns, K. Martin, 1997
 Sheilding Signals
Analog interconnect
Ground line used for shielding
Digital interconnect

n+ n+ n+
n well

p– substrate

• Shields keep noise from being capacitively coupled into or

out of substrate

University of Toronto slide 31 of 34

© D.A. Johns, K. Martin, 1997
 Example Analog Floorplan
V DD
Opamp 1 Opamp 2 Opamp 3 Opamps
Contact to substrate
V SS
Gnd

n well under capacitor region Capacitors

Region for n-channel switches

Switches
n well under p-channel switch region n well shield and
bypass capacitor
V DD

Gnd
φ1

φ1

φ2
Clock lines

φ2

University of Toronto slide 32 of 34

© D.A. Johns, K. Martin, 1997
 Latch-Up
Vin VDD VDD

p+ n+ Q1 n+ p+ Q2 p+ n+

n well Rn

Rp p– substrate

• Occurs when large substrate or well currents

• Creates an SCR that might turn on and not off until harm
done (or power turned off)

University of Toronto slide 33 of 34

© D.A. Johns, K. Martin, 1997
 Latch-Up
VDD = 5 V VDD = 0.9 V

Rn Rn
Q2 Q2

0V 5V

Vinv Q1 Q1
Rp Rp

• Capacitive coupling due to junction depletion caps of

MOS drains
• Have many substrate contacts and guard rings

University of Toronto slide 34 of 34

© D.A. Johns, K. Martin, 1997