Design Considerations for Fast-Settling Two-Stage

Miller-Compensated Operational Amplifiers

F. A. Amoroso, A. Pugliese, and G. Cappuccino, Senior Member, IEEE
Department of Electronics, Computer Science and Systems
University of Calabria
Via P. Bucci, 42C, 87036-Rende (CS), Italy
{f.amoroso, a.pugliese, cappuccino}@deis.unical.it

Abstract- The settling behavior of two-stage Miller-

compensated operational amplifiers (op-amps) is investigated in
this paper. The analysis aims to evaluate the real effectiveness of
conventional design approaches for the settling performances
optimization when op-amps are used in common SC circuits. It is
shown that the existing strategies are effective only for
sufficiently large values of the load capacitance to be driven by
the SC circuit. In typical situations in which this condition is not
satisfied, the conventional design rules to fix the element of the
op-amp compensation network may be inadequate to achieve
fast-settling two-stage amplifiers. Design examples in a
commercial 0.35-μm CMOS technology demonstrate that a
careful strategy for the sizing of the amplifier compensation
network elements can result in a significant reduction of the op-
amp settling time with respect to designs in which the
conventional criterion is used.
I. INTRODUCTION
Two-stage topologies are widely used in modern low-
voltage CMOS technologies to reach a suitable trade-off
between the dc gain and the output swing of operational
amplifiers (op-amps). To guarantee the closed-loop stability of
two-stage op-amps, frequency compensation strategies based
on the Miller technique are usually employed [1]-[8]. In the
basic Miller compensation approach, a capacitance is
connected across the two amplifier stages. The resulting open-
loop op-amp frequency response presents two left half-plane
(LHP) poles and one right-half plane (RHP) zero, which arises
from the feedforward signal path through the compensation
capacitance. Unfortunately, this RHP zero tends to degrade the
amplifier open-loop phase margin. For this reason, different
improved solutions were developed to compensate two-stage
op-amps [9]-[12]. The most well-established and widely used
technique to avoid the RHP zero is the nulling-resistor Miller
compensation, in which a resistor is connected in series to the
Miller capacitance [2]-[6], [8]-[12]. The schematic of a typical
fully-differential two- stage Miller-compensated amplifier is
depicted in Fig. 1. The first and the second amplifier stages are
implemented by MOSFETs M1-M5 and M6-M9, respectively.
The compensation network is constituted of the capacitance
CC and the nulling-resistor RC. The resulting open-loop
amplifier transfer function is
Figure 1. Fully-differential two-stage Miller-compensated op-amp.
characterized by three poles and one zero [9]-[11]. The
values of CC and RC are generally chosen to cancel the zero
or, more conveniently, to move it to the left half-plane and
cancel the first open-loop non-dominant pole aiming to
enhance the op-amp gain-bandwidth (GBW) product [9]-[12].
As recently demonstrated in [12], the simple NRMC with
pole/zero cancellation can be a competitive solution in terms
of the trade-off between the GBW product and the total
amplifier transconductance with respect to other more
complicated schemes in which voltage or current
buffers/amplifiers are employed.
The compensation network sizing has a crucial impact on
the op-amp dynamic characteristics and, as a consequence, on
the overall performances of the system in which the amplifier
is used. Therefore, the definition of a proper criterion to
optimize the sizing of CC and RC on the basis of the specific
application requirements is mandatory in order to achieve
high-performance system designs. In switched-capacitor (SC)
applications in which the amplifier speed is the main concern,
this criterion should guarantee the settling time minimization
for the desired accuracy level in the op-amp output response
[11]. To this aim, design strategies oriented to the GBW
maximization [10], [12] are not suitable. In fact, owing to the
high-order settling behavior of the op-amp in Fig. 1, the GBW
product maximization does not lead necessarily to settling
time minimization [13]. In [11], a design strategy was
proposed to size the amplifier compensation network aiming
to achieve the optimal open-loop op-amp phase margin which

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allows minimizing the settling time for a given response amplifier stage, respectively. Aiming to enhance the amplifier
accuracy level. The expression of the optimal phase margin bandwidth, CC and RC are generally chosen to perform the
was derived in [11] for unity-gain closed-loop op-amp cancellation between the zero and the first open-loop non-
configurations, by assuming for the amplifier a two-pole open- dominant pole [9]-[12] by imposing:
loop transfer function resulting from the pole/zero
cancellation. Starting from a two-pole amplifier description z1OL = p2OL . (2)
and by considering a generic feedback model, the expression
of the optimal phase margin was then modified in [14], [15] to
On the basis of (1) and (2), the following design rules were
take into account non-unitary feedback factors of typical SC
presented in [11] to size CC and RC in order to minimize the
circuits. Unfortunately, as will be demonstrated in the
op-amp settling time:
following, the design rules arising from the analyses carried
out in [11], [14], [15], may not guarantee an actual pole/zero
⎧ 1 1 1 C 2 C1
cancellation for op-amps used in real SC applications, ⎪ RC = tan (φ (ψ ) )g g C [( g m 2 + r + r )CC + r + r ]
especially in the presence of small capacitive loads which ⎪ MC m1 m 2 1 1 2 1 2

characterize common SC circuits, such as integrators used in ⎪ 2

− b + b + 4ac
⎪CC = ,(3)
sigma-delta modulators and multiplying digital-to-analog ⎪ 2a
converters (MDACs) used in pipeline analog-to-digital ⎨ 2
⎪a = ( g m 2 + 1 / r1 + 1 / r2 )
converters [4], [7]. As a consequence, the classical settling ⎪ tan (φ MC (ψ ) )g m1 g m 2 C1
optimization strategy based on a two-pole circuit model tends ⎪
to be ineffective. To identify the validity range of the classical ⎪b = ( g m 2 + 1 / r1 + 1 / r2 )(C 2 / r1 + C1 / r2 ) − g m 2 + 1 / r1 + 1 / r2
⎪ tan (φ MC (ψ ) )g m1 g m 2C1 gm2
design approach, the settling behavior of two-stage Miller- ⎩
compensated op-amps used in SC circuits is investigated in
this paper. In Section II, the conventional strategy for the where φMC (ψ) is the optimal op-amp phase margin which
settling performances optimization is revised and applied to allows minimizing the settling time of a two-pole system for
define sizing rules for the compensation network sizing. The the desired response accuracy level ψ. The expression of φMC
impact of the external amplifier capacitive feedback network (ψ) was derived in [11] referring to two-pole amplifiers in
on the SC circuit settling performances is evaluated in Section unity-gain closed-loop configurations, and was then
III by means of design examples in a commercial 0.35-μm generalized in [14], [15] to take into account a generic non-
CMOS technology. Further amplifier designs are then unitary feedback factor f as follows:
presented in Section IV to show how a careful analysis of the
op-amp settling behavior can lead the designer to fix 1 + (π / lnψ ) 2 .
φMC (ψ ) = 90° − tan −1[ ] (4)
conveniently the compensation network elements. Finally, 4f
some conclusions are reported in Section V.

III. ANALYSIS OF THE ACTUAL SETTLING BEHAVIOR OF SC

II. CLASSICAL SETTLING OPTIMIZATION STRATEGY
The classical design strategy is aimed at the settling
optimization for a two-pole closed-loop system, which comes
from assuming a two-pole transfer function for the amplifier in
open-loop configuration [11], [14], [15]. Actually, the transfer
function of the op-amp in Fig. 1 is characterized by three poles
p1OL, p2OL and p3OL, and one zero z1OL, which can be calculated
as follows [11]:
CIRCUITS USING TWO-STAGE MILLER-COMPENSATED OP-AMPS
In typical SC applications, the amplifier is used in the
feedback configuration shown in Fig. 2. For example, it well
describes SC integrators during the integration phase as well
as MDACs during the amplifying phase, when the resistances

⎧ 1
⎪ p1OL = − ( g r r + r + r )C + C r + C r
⎪ m2 1 2 1 2 C 1 1 2 2

⎪ ( g m 2 r1r2 + r1 + r2 )CC + C1r1 + C 2 r2

⎪ p2 OL = − r1r2 (C1CC + C 2CC + C1C 2 )
⎪ , (1)
⎨
⎪p = − 1 1 1 1
( + + )
⎪ 3OL RC C1 C 2 CC
⎪
⎪z = g m2
⎪⎩ 1OL CC (1 − g m 2 RC ) Figure 2. Closed-loop amplifier configuration in typical SC circuit operations.
of transistor used as switches are properly fixed to have a
where gmi, ri and Ci are the transconductance, the output negligible impact on the op-amp settling time [14], [15]. In the
resistance and the lumped output capacitance of the i-th schematic, CS and CF constitute the external feedback

6
capacitive network, and CIN and CL model the input op-amp for the compensation network do not lead to a real
capacitance and the total lumped capacitive load to be driven closed-loop pole/zero cancellation, and an unpredicted
by the circuit, respectively. For the circuit in the pole/zero doublet occurs. This results in strongly
CF C F (C S + C IN ) underdamped settling behavior such as the ones depicted in
figure, f = and C 2 = C L + [14], Fig. 3, which report the HSPICE simulation results related to
C F + C S + C IN C F + C S + C IN
the op-amp step response for CL= 4 pF and CL=2 pF. Thus, the
[15]. The circuit in Fig. 2 using the op-amp in Fig. 1 was conventional design approach may be ineffective to achieve
designed in a commercial 0.35-μm CMOS technology. CS= 1 fast-settling SC circuits in typical situations in which CL is
pF and CF= 4 pF were fixed, and four different load comparable with CS and CF.
capacitances were considered, i.e. CL= 100 pF, CL= 20 pF,
CL= 4 pF and CL= 2 pF. The dimensions and the bias currents
of the amplifier transistors (and as a consequence the power IV. PROPOSED DESIGN
dissipation) were maintained unchanged for all the designs
Starting from the analysis presented in the previous
carried out. gm1=88.2 μA/V, gm2=363.8 μA/V, r1= 3.07 MΩ, r2= section, the elements of the op-amp frequency compensation
74.5 kΩ, C1=0.07 pF, CIN=0.03 pF, and a dc gain equal to 77 network were carefully fixed by means of circuit simulations
dB and a power dissipation of 1.64 mW @ 3.3 V result from in order to actually optimize the amplifier settling behavior for
HSPICE simulations for the designed op-amps. The the 1% accuracy level. Table II compares the CC and RC values
compensation network was sized according to the obtained from the classical design rules (1)-(4) with the
conventional strategy aiming to optimize the amplifier settling
behavior for the 1% accuracy level (ψ=0.01) [11].
Table I summarizes the closed-loop poles and zeros of the
circuit resulting from HSPICE simulations, as well as the
value of z1OL obtained from (1), when CC and RC are fixed on
the basis of the classical rules (3)-(4) (φMC (ψ)=65.2° for
ψ=0.01). Other than the expected LHP zero, the actual circuit
frequency response presents two further zeros (one LHP zero
and one RHP zero) which tend to approach the poles when CL
decreases. In particular, the effect of the approach of the RHP
zero is the increasing of the initial undershoot in the amplifier
time response. However, the most important result shown in
Table I is related to the LHP zero which should ensure the
pole/zero cancellation in the amplifier frequency response, i.e.
z1. In fact, according to the conventional design approach for
the NRMC op-amp, this zero should be equal to z1OL (1) and
should cancel p1. Unfortunately, for the cases under
examination, z1 is actually very close to p1 and well estimated
by z1OL only for the very large load capacitance of 100 pF.
Instead, z1 deviates significantly from p1 and z1OL

TABLE I: HSPICE simulation results for the closed-loop poles and zeros of the
circuit compensated according to the conventional rules
CEXT Simulated poles Simulated zeros z1OL (1)
(pF) (rad/s) (rad/s) (rad/s)
p1=-3.75·106 z1=-3.74·106
100 p2,3=(-5.01±3.06 i)·107 z2=2.84·108 -3.75·106
z3=-3.87·108
p1=-1.82·107 z1=-1.75·107
-1.81·107
20 p2,3=-1.07·108±6.92·107 i z2=2.42·108
z3=-4.58·108
p1=-7.62·107 z1=-6.11·107
-7.69·107
4 p2,3=(-2.16±1.46 i)·108 z2=2.01·108
z3=-6.41·108
z1=-8.79·107 Figure 3. Positive/negative step responses of the circuit when the proposed
p1=-1.31·108 -1.32·108
2 z2=1.93·108 and the classical approaches are used: a) CL= 4 pF; b) CL= 2 pF.
p2,3=(-2.77±1.89 i)·10
z3=-7.75·108
when CL decreases. This is especially evident for CL= 4 pF
and CL=2 pF, which are more realistic values to be assumed
for the circuit load capacitance in typical SC applications
[4], [8], [16],[17]. As a consequence, the sizing rules (3)-(4)

7
 TABLE II: Compensation network elements and main performances of the designed amplifiers (φMC = 65.2°)
CL CC and RC tS +/ tS-(1%) (ns)
(pF) Conventional Proposed Conventional Proposed
CC=0.33 pF CC= 0.56 pF
2 37.5 / 37.6 13.0 / 13.1
RC=25.7 kΩ RC=24.0 kΩ
CC=0.43 pF CC=0.63 pF
4 51.5 / 51.6 17.3 / 17.4
RC=33.0 kΩ RC=31.5 kΩ
CC=0.86 pF CC=0.98 pF
20 87.0 / 86.7 33.0 / 33.1
RC=66.9 kΩ RC=71.0 kΩ
CC=1.85 pF CC=1.97 pF
100 82.1 / 82.4 73.7 / 72.8
RC=147.0 kΩ RC=162 kΩ
proposed ones. The table also reports the
positive/negativesettling times (tS+/ tS-), the GBW product and
the open-loop phase margin (φM) values of the amplifiers
compensated according to the proposed and the classical
strategies. It clearly appears that the proposed compensation
network elements allow an impressive improvement of the
circuit speed performances for a given power dissipation
when the load capacitance decreases. In particular, for CL=4
pF and CL=2 pF, the settling time is reduced by about 65 %
using the proposed values of CC and RC. Interestingly, it is also
evident that the value of the op-amp phase margin which
actually guarantees the settling optimization significantly
deviates from the one predicted by the classical analysis for
small load capacitances. The improvement obtained by using
the proposed compensation network elements is further
evidenced by the op-amp step responses depicted in Fig. 3
(obtained for CL= 4 pF and CL=2 pF). It appears that the
proposed approach guarantees a considerably enhanced
settling behavior with respect to the strongly underdamped
amplifier dynamics resulting from the classical design
strategy.
Above examples clearly demonstrate the importance of the
presented analysis in order to design high-speed two-stage
Miller-compensated op-amps for SC applications.
V. CONCLUSIONS
The settling behavior of two-stage Miller-compensated op-
amps used in SC circuits has been analyzed. By means of
design examples in a commercial 0.35-μm CMOS technology
it has been shown that classical strategies for the settling
optimization of two-stage Miller-compensated op-amps may
be actually effective only for sufficiently large values of the
load capacitance to be driven by the SC circuit. In typical real
situations in which this condition is not satisfied, the
conventional design rules to fix the element of the op-amp
compensation network may be inadequate to achieve fast-
settling two-stage amplifiers. It has been demonstrated that a
careful strategy for the sizing of the amplifier compensation
network elements can result in a significant reduction of the
op-amp settling time with respect to designs in which the
conventional criterion is used.
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