Modeling of CIGRE Benchmark HVDC System Using
PSS/E Compared with PSCAD
Do-Hoon Kwon, Student Member, IEEE, Hyeon-Jin Moon, Student Member, IEEE, Rae-Gyun Kim, Student Member,
IEEE, Chan-Gi Kim, Senior Member, IEEE, and Seung-Ill Moon, Senior Member, IEEE
1Abstract— This paper presents a model of the first CIGRE
benchmark HVDC system in PSS/E. The model was composed of
three parts which: equation converting, DC line, and the control
mode selection. The equation conversion uses different equations
to calculate the dc voltage and dc power according to normal and
abnormal conditions. The DC line calculates the dc current at both
dc transmission lines using the dc voltage derived by the equation
conversion. The ABB and AREVA control selections are
investigated to determine the control mode selection model.
Simulation studies have been carried out in PSCAD as well as
PSS/E to confirm the performance. The simulation results of
PSS/E are similar to those of PSCAD. PSS/E cannot analyze the
valve state or firing level such as the harmonic instability or the
firing control of the converter.
Index Terms— HVDC transmission, CIGRE HVDC benchmark
model, modeling, PSS/E
I. INTRODUCTION
I N recent years, the High Voltage Direct Current (HVDC)
Technology has grown to become the most attractive
transmission technology in the power transmission system.
Since the first commercial HVDC transmission system was
installed in Sweden in 1954, its applications have largely
increased. 70,000MW transmission capacity is transmitted
around the world through 95 HVDC projects [1]. Many HVDC
simulation model systems like digital simulators have been
developed to assess the power system or to control the HVDC
system, etc. However, a similar circuit topology with control is
required in order to compare the performance of any HVDC
system models based on digital simulators. Therefore, the
CIGRE Benchmark Model, was proposed in 1985 [2]. It is a
common reference system that has tested the HVDC system
model for the past three decades. A comparison of four digital
models has been carried out in 1991 [3]. The assumptions and
reasons for selecting the HVDC benchmark model have been
This work was supported in part by the Korea Electric Power Research
Institute (KEPRI) grant funded by the Korea Electric Power Corporation
(KEPCO), with project of Development of optimal application technology of
HVDC No.1, No 2 system in Jeju network.
D. H. Kwon, H. J. Moon, and R. G. Kim are with the School of Electrical
Engineering and Computer Science, Seoul National University, Seoul 151-742,
Korea (e-mail: dhkwon@powerlab.snu.ac.kr, hjmoon@powerlab.snu.ac.kr).
C. G. Kim is with the Korea Electric Power Research Institute (KEPRI),
Daejeon 305-760, Korea (e-mail: ckkim@kepri.re.kr).
S. I. Moon is with the School of Electrical Engineering and Computer
Science, Seoul National University, Seoul 151-742, Korea (e-mail:
moonsi@plaza.snu.ac.kr).
978-1-4673-7172-8/15/$31.00 ©2015 IEEE
discussed in [4] by the CIGRE Working Group. The capabilities
and limitations of the EMTP and NETOMAC programs for
HVDC system simulation were investigated in [5], where the
fundamental differences between the two programs and the new
advanced stability feature of provided by NETOMAC have
been discussed. In addition, custom power devices, such as
DSTATCOM and DVR, have been simulated using
PSCAD/EMTDC and MATLAB/SIMULINK. This allows for
the analysis of advantages and disadvantages during the
transient situation described in [6]. The elaborate control model
and control technique for the 4-terminal Pacific Intertie HVDC
transmission scheme using EMTP have been presented in [7].
More recently, a comparative study of the CIGRE HVDC
benchmark system model and simulation using
PSCAD/EMTDC, PSB/SIMULINK, and PSCAD/SIMULINK
interface have been reported in [8]. Furthermore, the CIGRE
HVDC benchmark system has been modeled using
MATLAB/SIMULINK in [9].
Meanwhile, PSS/E is a powerful time-domain simulator that
simulates the power systems and controls. The transmission
planning and operation engineers are provided with a broad
range of methodologies for use in the design and operation of
reliable networks. There are also sample HVDC models, such as
CDC4T, CDC6T, and CDC7T in PSS/E, but these models have
too many parameters to simulate properly and makes it difficult
for these sample models to apply to various power systems.
Based on previous observations, this paper describes a
CIGRE benchmark HVDC system model in PSS/E with defined
parameters according to HVDC operation and control.
Simulation result comparisons in PSCAD are also presented to
confirm the model performance.
Section II of this paper briefly identifies the CIGRE HVDC
benchmark system while Section III provides the simulation and
modeling environments in PSS/E. it also introduces the control
level differences between PSCAD and PSS/E. Section IV
presents the methods for selecting the AREVA and ABB control
mode. Section V shows the detailed model of the CIGRE
HVDC benchmark system that is comprised of three parts in
PSS/E: the converting equation, the dc line, and the control. The
three-phase ground fault simulation results at both sides are
given in Section VI and, followed by conclusions in Section
VII.
 2

II. CIGRE BENCHMARK SYSTEM IN PSCAD
Fig. 1 shows the CIGRE benchmark HVDC system which is a
mono-polar 500-kV, 1000-MW HVDC link with 12-pulse
converters on the rectifier side in PSCAD. The inverter side is
similar to the rectifier side and both are connected to the weak
ac system, which has a short circuit ratio of 2.5 at a 50Hz rated
frequency. There are the low and high filters that compensate for
a portion of, or all of, the reactive power absorbed by the
converter, to limit the current distortion caused by the converter
harmonics to an acceptable level. The capacitive reactive
compensation are also provided at both sides to supply the
reactive power. The full three-phase model of the CIGRE
benchmark HVDC system is available as an example file in
PSCAD Version 4.2.0. The CIGRE benchmark HVDC system
data [3], [4] is given in Table I. The detailed power circuits of
the converter and power circuit models like converter, converter
transformer, supplying voltage source, and dc line are reported
in [8].
The control system model has the following three controllers
in PSCAD Version 4.0.2:
 Extinction Angle (γ) Controller
 DC Current Controller
 Voltage Dependent Current Limiter (VDCOL)
The rectifier side controls only the constant DC current while
the inverter side can control the extinction angle (γ) or the DC
current with Voltage Dependent Current Limiter (VDCOL). The
detailed information on control at both sides is provided in [8].
Every controller uses the PI controller to produce the required
order. The γ controller selects the minimum value of γ of each
thyristor valve in the converter at the inverter side during the
one cycle in PSCAD, as shown in Fig. 2. If γ is selected for
another value, such as the average value of all thyristor valves in
the converter, then commutation failure can occur due to the γ,
which is larger than the average value. The minimum γ is
considered the firing control region, because the PSCAD
simulation time step is shorter than 10ms, as shown in Fig. 4.
III. SIMULATION AND MODELING ENVIRONMENT IN PSS/E
PSS/E is a package of programs that study the power system
transmission network and generation performance in both
steady-state and dynamic conditions. The process of solving the
algebraic equations for given loads and generator power outputs
is referred to as the Power Flow Calculation and requires an
iterative procedure. Dynamic simulation is the process of
integrating the differential equations to produce transient
variation plots of quantities like rotor angle or power flow [10].
The HVDC system can be modeled at various simulation time
steps depending on the simulation tools used from PSS/E,
PSCAD, and RTDS. PSS/E can be used to simulate system
phenomenon at a fundamental frequency or below, i.e.
phenomena like low-frequency resonances or oscillation
damping. Fig. 3 indicates the various kinds of control that can
occur in a power system.
Because the PSS/E simulation time step is longer than the
time to analyze the interactions between HVDC and ac systems
at 1kHz or higher, such as harmonic instability, the modeling
scopes of HVDC in PSS/E are at constant current loop level,
VDCOL, and over as shown in Fig. 4. It is assumed that a firing
angle such that the minimum γ of thyristor valves at the inverter
side is ideal in PSS/E while the minimum γ of thyristor valves is
considered in PSCAD as shown in Fig. 2.
Turbine and boiler control
Generator control
System stabilizing control
Protective relay system
HVDC, SVC
10-4 10-3 10-2 10-1 1 101 102 103 104
Time period (s)
Fig. 3. Power system control and time period

DC Line 0 10ms 500ms 0.1s

AC System 345kV : 422.84kV
603MVA
6-Pulse
Rectifier
Time
LF Filter
345kV : 422.84kV
603MVA
Valve and Firing Pole Master
6-Pulse
Rectifier
HF Filter

Firing Control Constant Current Loop Constant Frequency Control

Reactive power
Harmonic Instability VDCOL Modulation Signal
Fig. 1. Simplified diagram of the CIGRE benchmark HVDC system at the
rectifier side Fig. 4. The relationship between simulation time and HVDC control level and
interaction

γerror IV. CONTROL MODE SELECTION METHOD

+
γmeasured Min in - Ki The HVDC rectifier and inverter can change their control
Σ Kp + αorder_γ
1 Cycle
+
s modes into current and voltage control according to the ac
system. Various renowned HVDC companies like ABB,
γmin_set point
SIEMENS, and ALSTORM have their own methods for
Fig. 2. Simplified γ control system model of CIGRE benchmark HVDC system
selecting the control modes to model the HVDC system. Some
at the inverter side in PSCAD
 3

methods for control mode selections are described in following
subcircuits.
A. ABB Control Mode Selection Method
The ABB HVDC system model control mode selection can
be achieved by changing the maximum or minimum limit of the
PI controller in the dc current controller. Fig. 5 shows the simple
diagram for the control mode selection at the rectifier and
inverter sides. Every voltage and current controller at both sides
is composed of the PI controller. There are two control modes:
dc voltage and current control at the rectifier converter. The dc
voltage controller output goes to the dc current controller and
the minimum dc current controller is shown in Fig. 5(a). The
minimum dc current controller limit is selected to be the larger
αmin, which is pre-determined, or the dc voltage controller
output.
If the rectifier controls the dc current in normal operations,
the dc voltage controller will decrease αorder_vol which is the
minimum limit of the dc current controller since Vdc_order is
larger than Vdc_measured. Because the difference between Idc_order
and Idc_measured is small in the steady state, the dc current
controller output is near the measured α, which is normally
within 15 and 20 degrees. This means that the rectifier control
mode is the dc current control since αorder is the output from the
dc current controller.
DC Voltage
Controller
αmax_voltage
Vdc_order Ki αorder_vol
Vdc_measured Kp +
s Idc_measured
αmin_voltage Maximum
Select
αmin
(a)
When the rectifier controls the dc voltage due to the ac
voltage drop at the rectifier side, the dc current controller will
decrease αorder to the minimum and increase the dc current since
Id_measured is near Id_order at the inverter end, which is smaller than
Id_order at the rectifier end. This means that the rectifier control
mode is the dc voltage control, as αorder is the output from the dc
voltage controller.
The normal αmin is 5 degrees to ensure adequate voltage
across the valve before firing, αmax_voltage and αmax_current are
normally between 90 and 140 degrees in the inverter region to
assist the system under certain fault conditions.
In the detailed ABB HVDC model, the minimum limit of the
dc voltage controller is the maximum value among αmin, and,
αmin_RAML from the Rectifier Alpha Min Limiter, αmin_OVL which
considered the over voltage limit, and αmin_refVARC calculated by
the voltage and angle reference calculator [11].
Fig. 5(b) shows the simple diagram for control mode
selection at the inverter end, which is composed of the dc
voltage controller, the dc current controller, and the alphamax
inverter controller. The output from the dc voltage controller
goes into the dc current controller as the maximum limit of the
dc current controller. This is the smaller αmax value, which is
pre-determined as the output from the dc voltage controller.
In normal operations, the dc current controller increases αorder
to the maximum limit to increase the inverter dc voltage since
Id_measured is larger than the Id_order of the inverter. This means that
the inverter control mode is the dc voltage control since αorder is
DC Current the output from the dc voltage controller.
Controller The maximum limit of the dc voltage controller is determined
by the alphamax inverter controller which is nothing but
αmax_current
constant beta control to have a positive slope in the current
margin region increase the stability of the current controller. If
Idc_order Ki
there is no positive slope, sudden changes in the current cause
Kp +
s
αorder power oscillations in the system during mode shifting. The
constant beta for positive slopes and αmax are given in (1) and (2).
The normal αmin at the inverter is 110 degrees for the inverter
and does not operate as the rectifier.
αmin_current
 I o Vd 
=β arccos  cos γ − 2 ⋅ X c ⋅ ⋅  (1)
 I dN Vdio 

α max= π − β (2)
DC Voltage DC Current
αmax
Controller Controller
B. AREVA Control Mode Selection Method
γref
Alphamax αmax_voltage Minimum αmax_current The AREVA HVDC system model selects the control mode
Inverter
Select
controller composed of the PD controllers and integrator by using the
minimum and maximum selection at both converter sides, as
Vdc_order Idc_order shown in Fig. 6. A basic mode selection principle in AREVA is
Ki Ki
Vdc_measured Kp +
s αorder_vol Idc_measured Kp +
s
αorder to select the control mode with the smallest difference between
the set-point and measured value.
There are two control modes: dc voltage and current control
αmin_voltage αmin_current at the rectifier converter. The dc voltage controller is comprised
(b) of Vdc control and αmin control, as shown in Fig. 6(a). If the
Fig. 5. Simple diagram for ABB HVDC system model control mode selection at (a) rectifier controls the dc current in normal operations, the
rectifier and, (b) inverter difference between Idc_order and Idc_measured is so small that output
 4

αorder_current from the PD controller is near measured α while Vdc
control and αmin control decrease αorder_voltage and αorder_αmin since
each set-point value is larger than each measured value.
Therefore, the dc current control mode is selected among the
control modes, because the larger value of the two outputs,
αorder_voltage or αorder_αmin, is smaller than αorder_current.
When the rectifier controls the dc voltage due to the ac
voltage drop, αorder_current is decreased by the dc current
controller and rectifier dc voltage increased to increase dc
current to Idc_order. The αmin controller make αorder_αmin into αmin
and αorder_voltage is near αmeasured due to the small difference
between Vdc_set point and Vdc_measured. Therefore, αorder is selected
from the dc voltage controller, which is Vdc control or αmin
control.
After the control mode is chosen by maximum selection, the
αorder passes through the integrator and the PD controller
function becomes the PI controller. This means that the AREVA
HVDC system model can have the same results as the ABB
HVDC system model using the PD controller, the maximum
selector, and the integrator. The normal αmin_set point is 5 degrees
so that there is a certain voltage across the valve before firing
and Vdc_set point is larger than 1.0 pu at the rectifier.
The control mode selection of the inverter side is similar to
that of the rectifier side except for the minimum selection as
shown in Fig. 6(b). If the inverter controls the dc voltage in
normal operations, αorder_current is increased by the dc current
controller to increase the dc voltage of the inverter side since
Idc_order is smaller than Idc_measured. αorder_γ and αorder_voltage are
small since γmeasured is near γset point and the difference between
Vdc_set point and Vdc_measured is very small. Therefore, the dc voltage
controller, Vdc control or αmin control, is selected by minimum
selection.
When the inverter controls the dc current due to the ac
voltage drop in the rectifier side, the difference between Idc_order
and Idc_measured is so small that αorder_current is near zero while
αorder_voltage and αorder_γ increase since Vdc_set point is larger than
Vdc_measured and γset point is smaller than γmeasured. This means that
αorder_current is selected by minimum selection rather than by
αorder_voltage or αorder_γ. Additionally γset point can be increased to
have a positive slope in the current margin region.
In the detailed AREVA HVDC model, the Vac control for
preventing overvoltage of ac system, αmax and γrec control for
operating the inverter mode of the rectifier during the dc fault
are also implemented.

DC Current Controller

αorder_current
V. CIGRE HVDC SYSTEM MODEL IN PSS/E
Idc_order - Σ Kp + sKd
+ The CIGRE HVDC system model in PSS/E is comprised of
Idc_measured 179° three parts: the converting equation, the dc line, and the control.
The control is implemented using the PI controllers and the
Maximum 2πf00
DC Voltage Controller Select s
αorder minimum and maximum selection. This is similar to the AREVA
αorder_voltage
HVDC system model and VDCOL at the inverter side.
Vdc_set point - 1°
+
Σ Kp + sKd
The converting equation calculates the dc voltage and dc real
Maximum power in addition to ac active and reactive power and certain
Vdc_measured Select
additional quantities like converter transformer secondary
αmin_set point +
Σ Kp + sKd
αorder_αmin voltage. These values are derived using ac and dc converting
- equations in transient conditions as well as steady state
αmeasured conditions after the control the calculates the firing angle of
(a)
both converters at each time step.
The converting equation initializes the present dc quantities
from the load flow. During the dynamic run, the firing angle
DC Current Controller
updated by the control part enables the converting equation to
- αorder_current calculate the dc voltages at both sides of the link. The dc line
Idc_order Σ Kp + sKd
+ part updates the dc current at each time step using the firing
Idc_measured 179°
angle and dc voltage at both converter ends. These dc voltage
Minimum 2πf00
and current updates can calculate the dc and ac active power at
αorder
DC Voltage Controller Select s both converter sides. The reactive power of the ac system at the
αorder_voltage converter is found by calculating the power factor angle in terms
Vdc_set point +
Σ Kp + sKd 1°
- of firing angle and overlap angle.
Maximum When the firing angle is derived by the control, Vdcc, μc,
Vdc_measured Select
power factor angle, Pdcc, and Pacc can be expressed as (3)-(7).
γset point - αorder_γ
Σ Kp + sKd
+
3 2 3X I 
γmeasured Vdcc = Nc  Eacc cos α c − cc dc − 2 Rcc I dc  (3)
 π π 
(b)  2 I dc X cc 
µ= arccos

cos α − −
 c α (4)
Eacc 
c c
Fig. 6. Simple diagram for the control mode selection of the AREVA HVDC system 
model at the (a) rectifier and, (b) inverter
 5

2µc + sin ( 2α c ) − sin ( 2 ( µc + α c ) ) +

tan (φc ) = (5) 1 Vdl1 1
cos ( 2α c ) − cos ( 2 ( µc + α c ) ) 1+sT1 Σ G1 Idr
1+sT1
-
- G1
1 + Vdx Vdm
P=
dcc Vdcc ⋅ I dc (6) G1
1+sT1
+
Σ
-
1/sT Vdm

G2
+
2 1 Vdl2 1
3N c Eacc E − 06
( cos ( 2α c ) − cos 2 ( µc + α c ) ) 1.0SBASE 1 Σ G2 Idi
Pacc = (7) G2
1+sT2
1+sT2
-
1+sT2
4π X cc

G1=1/R1; G2=1/R2; T1=L1/R1; T2=L2/R2; T=C

Finally, Qacc can be calculated using (5) and (7). Iac is given by
(b)
Fig. 7. (a) Simple dc line part model (b) dc current derivation diagram
2
3N c Eacc 1.0 E − 06
Q=
acc
4π X cc
(
2µc + sin ( 2α c ) − sin ( 2 ( µc + α c ) )
SBASE
) (8)
Vdl=
1 Vdr − Vdm
(17)
 P + jQacc 
I ac =  acc  (9) Vdl=
 Vac  2 Vdm − Vdi (18)

The dc line part initializes dc current at both sides of the line.

The overlap angle, μc, is normally around 20 degrees.
However, the normal mode limit is reached when it reaches 60
degrees. If μc exceeds 60 degrees, the HVDC model discerns a
transient abnormality, and the dc voltage and current
calculations should be amended as follows:
3 6
Vdcc = Nc  Eacc cos (α c − 30 ) − cc dc − 2 Rcc I dc 
 π
They are set to the same value calculated in the load flow, the
capacitor current, ic, which is zero, and the midpoint voltage,
Vdm, which is halfway between the rectifier and inverter voltages.
There is no capacitor at the midpoint if the dc line is cable.
The model is written in standard Fortran 77 and complied
using the Intel® FORTRAN Complier.
9X I 
(10)
π 

=

γ c arccos  cos (α c − 30 ) −
6 I dc X cc  VI. CASE STUDIES AND RESULTS
 − 30 (11)
 Eacc 
2µc + sin ( 2 (α c − 30 ) ) − sin ( 2 ( γ c + α c ) ) A. Test System and Simulation Conditions
tan (φc ) = (12)
cos ( 2 (α c − 30 ) ) − cos ( 2 ( γ c + 30 ) ) The test system for the PSS/E CIGRE HVDC system model is
3N c E 2
1.0 E − 06 a four bus system, which has two buses for the ac system at the
Pacc =
4π X cc
acc
(
cos ( 2 (α c − 30 ) ) − cos 2 ( γ c + 30 )
SBASE
) (13)
rectifier and inverter sides and two buses for the HVDC rectifier
2
3N c Eacc 1.0 E − 06 and inverter. The ac base voltage of the two buses at the rectifier
Qacc
=
4π X cc
(
2µc + sin ( 2 (α c − 30 ) ) − sin ( 2 ( γ c + 30 ) )
SBASE
) (14)
side is 345kV. A generator connected to the ac system bus
supplies 1,000MW of power to the rectifier bus as shown in Fig.
8. The 500kV HVDC transmission system supplies 1,000MW
The transformer open circuit secondary voltage magnitude, Eacc,
to the inverter side; this is similar to the rectifier side, but has a
and the transformer valve winding secondary voltage under load
980MW load with 230kV ac base voltage. The rectifier and
conditions, Vacs, can be calculated by
inverter bus have a 600MVar shunt capacitor to supply reactive
power. Filters are assumed to be ideal due to the PSS/E
TRc ⋅ EBASE simulation time step.
=Eacc Vac ⋅1.0 E + 03
TAPc (15)
The GIGRE HVDC system has been simulated in both
Vacs=
Vac ( R + jX cc ) ⋅ SBASE
− I ac ⋅ TAPc ⋅ cc PSCAD and PSS/E to confirm the model’s performance. The
TAPc N c ⋅ TRc2 ⋅ EBASE 2 (16)
HVDC system was simulated for 5s to analyze the steady-state
and transient results. The simulation was run without any faults
for the steady-state analysis, then a three-phase ground fault at
The dc line section calculates the dc current at both sides of a
the rectifier or inverter side occurred for 0.1s at 1s for the
dc transmission line using dc voltage derived by the converting
transient analysis. The CIGRE HVDC system model should be
equation at each time step. The line is modeled as shown in Fig.
loaded before the dynamic simulations in PSS/E, as shown in
7. Vdl1 and Vdl2 are the voltage drops given as (17) and (18) in
Fig. 9.
Fig. 7(b).

Vdr Vdi AC System Rectifier

Idr Vdm Idi

R1 L1 L2 R2
Rectifier C ic Inverter

Reactive power
Fig. 8. Simplified diagram of test system at the rectifier side in PSS/E
(a)
 6

Dynamic Simulation
Second Action 1.6
1 Fault
1.1 Clear Fault
5 Run

p.u
1
Fig. 9. Loading HVDC model and operation for dynamic simulation in PSS/E

B. Simulation Results 0.4

Figs. 10 and 11 indicate the dc voltage and current at the 1 1.2 1.4 2
rectifier side when a three-phase ground fault occurs at the Time (s)
inverter side. The rectifier dc voltage had an ac component for (a)
five cycles after the fault due to commutation failure at the
inverter in PSCAD, as shown in Fig. 10(a). Meanwhile, the dc
1.6
voltage dropped to -1pu and a little ac component was shown
after the fault in PSS/E. The dc voltage was returned to 1pu

p.u
linearly due to the VDCOL after fault clearing in PSS/E, as 1
shown in Fig. 10(b).
The dc current at the rectifier side increased to 1.6pu rapidly
due to the voltage difference between the rectifier side and the 0.4
middle of the dc line. This increased rapidly as the inverter dc
1 1.2 1.4 2
voltage dropped to zero due to the three-phase ground fault at
Time (s)
the inverter side in PSCAD, as shown in Fig. 11(a). the dc
current decreased rapidly once more after the fault clearing due (b)
Fig. 11. Rectifier DC current when 3-phase ground fault occurs at the inverter side in
to the voltage difference between the rectifier side and middle of (a) PSCAD and, (b) PSS/E
the dc line, which decreased as the inverter dc voltage increased
dramatically, as shown in Fig. 10(a). Fig. 11(b) indicates that
similar results appeared in PSS/E. 1
Fig. 12(a) and (b) show that the simulation results of the dc
p.u

voltage at the inverter in both PSCAD and PSS/E are similar.

The voltage dropped to zero when a 3-phase ground fault 0
occurred at the inverter side in both simulations, but decreased
to -0.7pu right after the fault in PSCAD due to the dc line
capacitance, as shown in Fig. 7(a). The dc voltage increases to -1
1 1.2 1.4 2
1pu linearly due to the VDCOL after fault clearing in PSS/E. Time (s)
(a)
1
1
p.u

0
p.u

-1
-1.5 0
1 1.2 1.4 2
Time (s) 1 1.2 1.4 2
(a) Time (s)
(b)
1 Fig. 12. Inverter DC voltage when 3-phase ground fault occurs at the inverter side in
(a) PSCAD and, (b) PSS/E
p.u

0
The dc current at the inverter side increased to 2.5pu, which is
-1 higher than the peak value of dc current at the rectifier side, and
-1.5
rapidly goes to the right after the fault in PSCAD, as shown in
1 1.2 1.4 2 Fig. 13(a). This is due to the voltage difference in the middle of
Time (s)
the dc line. The inverter side is also bigger than the rectifier and
(b) the middle of the dc line. Similar results appeared in PSS/E, but
Fig. 10. Rectifier DC voltage when 3-phase ground fault occurs at the inverter side
there was a little AC component during the fault, as shown in
in (a) PSCAD and, (b) PSS/E
 7

Fig. 13(b). It occurred in PSCAD due to commutation failure at VII. CONCLUSIONS

the inverter side. VDCOL’s effect can be identified in PSS/E.
Fig. 14 shows the dc current at the rectifier side when a
3-phase ground fault occurs at the rectifier side. The simulation
results for both simulations are similar, but there was no AC
component at the fault, as shown in Fig. 14(b). This means that
PSS/E cannot analyze of the valve state or firing level with the
harmonic instability or firing control.
2.5
p.u
In this paper, the GIGRE benchmark HVDC system has been
modeled in PSS/E and compared to the example file in PSCAD
by analyzing the three-phase ground fault results at both sides.
The methods for selecting the AREVA and ABB control modes
as well as the converting equations and dc line model have been
demonstrated by the CIGRE benchmark HVDC system in
PSS/E. The simulation results of PSS/E were similar to those of
PSCAD, which shows that PSS/E is not able to analyze the
valve state or firing level with the converter’s harmonic
instability or firing control.

TABLE I
1 CIGRE HVDC BENCHMARK SYSTEM DATA
Parameter Rectifier Inverter
0 AC Base Voltage 345 kV 230 kV
Base MVA 100 MVA 100 MVA
1 1.2 1.4 2 Transf. tap (HV side) 1.01 pu 0.989 pu
Time (s) Voltage Source 1.088∠22.18° 0.935∠-23.14°
(a) Nominal DC Voltage 500 kV 500 kV
Nominal DC Current 2 kA 2 kA
Transf. Xl 0.18 pu 0.18 pu
Source Impedance R = 3.737Ω R = 0.7406 Ω
2.5 L= 0 H L = 0.0365 H
System Frequency 50 Hz 50 Hz
Minimum Angle α = 15° γ = 15°
p.u

0 REFERENCES
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p.u

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[6] W. Freitas and A. Morelato, “Comparative study between power system
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(b)
Fig. 14. Rectifier DC voltage when 3-phase ground fault occurs at the rectifier side
in (a) PSCAD and, (b) PSS/E
 8

Do-Hoon Kwon (S’15) received his B.S. and M.S. degree in Electrical
Engineering from Seoul National University in 2010 and 2012, respectively.
He is currently a Ph.D. candidate in Electrical Engineering at Seoul Nation
University. His research fields of interest include HVDC, EMS and Smart
distribution system.

Hyeon-Jin Moon (S’15) received his B.S. degree in electrical engineering

from Hanyang University in 2012. He is currently a Ph.D. candidate in
Electrical Engineering at Seoul Nation University. His research fields of
interest include ESS, EMS and Smart distribution system.

Rae-Gyun Kim (S’14) received his B.S. degree in electrical engineering from
Seoul National University in 2014. He is currently a M.S. candidate in
Electrical Engineering at Seoul Nation University. His research fields of
interest include HVDC, ESS and Fault Current Detection.

Chan-Ki Kim (M’02-SM’14) received his M.Sc. and Ph.D. degrees in

Electrical Engineering from Chung-Ang University, Korea in 1993 and 1996,
respectively.
Since 1996, he has been with KEPRI, the R&D center of KEPCO (Korea
Electric Power Corporation). His research interests are HVDC, Power
Electronics and Generator Control. In the field of HVDC and Power Electronics,
he has helped to develop the HVDC simulator, HVDC commissioning
technology and HVDC control algorithms. Related to these developments, until
now he has published over 150 technical papers in widely read journals,
including KIEE and IEEE, and submitted 40 patents and programs and has
published three books(HVDC Transmission - Power Conversion Application in
Power System –Published by Wiley & IEEE Press, 2009 ).
He received the Technical Award from the Ministry of Science and
Technology of the Korean Government and Excellent Paper Awards from KIEE
in 2002 and 2004, respectively. He is a senior member of the Institute of
Electrical and Electronics Engineers (IEEE).

Seung-Ill Moon (M’93-SM’14) received the B.S. degree in electrical

engineering from Seoul National University, Seoul, Korea, in 1985, and the
M.S. and Ph.D. degrees in electrical engineering from Ohio State University,
Columbus, in 1989 and 1993, respectively.
He was an Assistant Professor of the Department of Electrical Engineering at
Chonbuk National University. And currently he is a Professor of the School of
Electrical Engineering and Computer Science at Seoul National University. He
is a Member of Presidential Committee on Green Growth in Korea, Advisor for
Ministry of Industry, Trade and Energy in Korea, Member of KEPCO President
Nomination Committee, Executive Director of Korea Smart Grid Institute,
President of Electric Service Forum, Visiting Commentator of KBS (Korean
Broadcasting System), Chairman of Green Industry and Technology
Committee of Korea, and Chairman of Electric Power Policy Committee of
Korea. His special fields of interest include Smart Grid, Distributed Generation,
Flexible AC Transmission System, Renewable Energy, and Battery Energy
Storage Systems.
Mr. Moon’s awards and honors include the Service Merit Medal (Korean
Government), Young-Moon Park Best Scholar Award and Outstanding Scholar
Award (Korean Institute of Electrical Engineers).