Design source

module tlc(R,G,Y,clk,rst);

input clk,rst;

reg[3:0]count;

output reg R,G,Y;

reg [2:0]ps,ns;

parameter s0=3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100,s5=3'b101;

always @(posedge clk )

begin

if(rst)

begin

ns<=3'b000;

count<=4'b0000;end

else

ps<=ns;

end

always @ (posedge clk )

begin

case(ps)

3'b000: begin

count<=count+1;

begin

if(count==15)begin

ns<=3'b001;

count<=0;

R<=1;

G<=1;

Y<=0; end

else
 begin

ns<=3'b000;

R<=0;

Y<=0;

G<=0;

end

end

end

3'b001:

begin

count<=count+1;

if(count==3'b011) begin

ns<=3'b010;

count<=0;

R<=1;

Y<=1;

G<=0; end

else begin

ns<=3'b001;

R<=0;

Y<=0;

G<=0;

end

end

3'b010:

begin

count<=count+1;

if(count==3) begin

ns<=3'b011;

count<=0;

R<=1;
 Y<=0;

G<=0;

end

else begin

ns<= 3'b010;

R<=0;

Y<=0;

G<=0;

end

end

3'b011: begin

count<=count+1;

if(count==15) begin

ns<=3'b100;

count<=0;

R<=1;

Y<=0;

G<=1;

end

else begin

ns<=3'b011;

R<=0;

Y<=0;

G<=0;

end

end

3'b100: begin

count=count+1;

if(count==3) begin

ns<=3'b101;

count<=0;
 R<=1;

Y<=1;

G<=0;

end

else begin

ns<=3'b100;

R<=0;

Y<=0;

G<=0;

end

end

3'b101: begin

count<=count+1;

if(count==3) begin

ns<=3'b000;

count<=0;

R<=1;

Y<=0;

G<=0;

end

else begin

ns<=3'b101;

R<=0;

Y<=0;

G<=0;

end

end

endcase

end

endmodule

test bench
`timescale 1ns/1ns

module tlc_tb;

reg clk=1,rst=1;

reg[3:0]count=0;

wire R,G,Y;

tlc a1(R,G,Y,clk,rst);

always #5 clk=~clk;

initial

begin

#10 rst=0;

#1000 $finish;

end

endmodule