Floorplan

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Agenda:
● Basic Terminologies before Floorplan
● Input Files for Floorplan
● Introduction
● Floorplan Steps
● Target Utilization Display
● Density calculation
● Power Planning

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Basic Terminologies before Floorplan:
● Aspect Ratio: It is the ratio between height
and width of the core or a block. Routing
resources, congestion, placement of stan-
dard cells, timing, clock-tree, placement
of IO pads and packaging depends on the
aspect ratio of the core or a block.

Aspect ratio = height of the core /

width of the core

CORE 3
Basic Terminologies before Floorplan:
● Core Utilization: It defines the total area
occupied by the standard cells and macros
in the block or top-level design. Typically,
70-80% utilization is taken into account
for blocks as timing optimization involves
placement of buffers or inverters which
requires area.

Core utilization = (standard cell area +

macro cells area) / total core area

Ques: Why don’t we maintain 100% of core utilization? 4

Basic Terminologies before Floorplan:
● Cell Orientation: Every instance in a design such as a block, a macro, an IO pad or a
standard cell have orientation associated with them. Orientation is defined as the
rotation and/or mirroring of that instance about x or y axis to make connections
meaningful and easier. Different types of cell orientations-

○ R0 - No rotation.
○ MX - Mirror through x-axis.
○ MY - Mirror through y-axis.
○ R90 - Rotate 90 degrees counter-clockwise.
○ R180 - Rotate 180 degrees counter-clockwise.
○ R270 - Rotate 270 degrees counter-clockwise.
○ MX90 - Mirror through x-axis and rotate 90 degrees counter-clockwise.
○ MY90 - Mirror through y-axis and rotate 90 degrees counter-clockwise.
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Basic Terminologies before Floorplan:
● Core Boundary: It is the area or region within which standard cells and
macros are placed in the design. From top-level of a design, core boundary
will be rectangular or square shaped. From block-level of a design, core
boundary may have rectangular or rectilinear shape.

● Halo: It is the area around the boundary of a block or a macro or a standard

cell within which no other block or standard cell or macro is placed. If the
blocks or standard cells or macros are moved, halos for those instances
move along with it. It is also called as the keepout region. Halos of two
adjacent instances can be overlapped.

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Basic Terminologies before Floorplan:
● Instance: A single occurance or a single object of a standard cell type or a
macro or a block defined with a unique instance name. Ex: a 2-input AND
gate could be instantiated as CELL_AND_1 and a usb 2.0 macro could be
instantiated as USB_2_0_1.

● Manufacturing Grid: The smallest resolution of the technology node is called

as the Manufacturing Grid. Any geometry (or shape) created in the design
must be snapped (or aligned) with this grid to avoid DRC errors.

● Net: A logical connection between two or more pins of different instances.

Some of the different types of net in a design are single fanout net,
multi-fanout net, power net, ground net, signal net, clock net etc.
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Basic Terminologies before Floorplan:
● Macro: A Macro is an Intellectual Property (IP) in a design that is owned by a
company. These are reusable logic blocks used in a design without the
necessity of building them from scratch. Two types of macro are Soft Macro
and Hard Macro.
○ Soft Macro is not specific to any technology node. Due to this, soft
macros are unpredictable in terms of timing, area and power. But soft
macros are more flexible in terms of reconfigurability and can be
modified at the RTL level.
○ Hard Macro is what we call as a Block in PD. It is designed specific to a
technology node to meet timing, area and power.

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Basic Terminologies before Floorplan:
● Physical Cells: These cells do not have any logical functionality in the
design. Some of the standard physical cells are tap cells, tie cells, endcap
cells, decap cells, filler cells, spare cells.

● Pin: A pin is an IO terminal that is present in blocks or hard-macros or

standard-cells of a design. Ex: For a 2-input AND gate, CELL_AND_1/a,
CELL_AND_1/b are the input pins and CELL_AND_1/z is the output pin.

● Port: A port is an IO (Input/Output) terminal that is present in blocks or

hard-macros of a design. From top-level, ports are pins in hard-macros or
blocks. But from block-level, pins talking to top-level are celled as ports.
Direction of ports can be input, output or in-out.
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Basic Terminologies before Floorplan:
● Placement Blockage: It is the area defined by the designer for the PnR tool
to avoid placing or overlapping standard cells in that particular area. If a
block or standard cell or macro or IO pad is moved, placement blockages
does not move along with it.
○ Hard placement blockage means that the tool must not place or overlap any
standard cell (including buffers and inverters) in the mentioned blockage area.
○ Non-buffer blockage means that the tool can place or overlap any buffer or
inverter in the mentioned blockage area except other standard cells in the
design.
○ Partial blockage means that the designer can adjust the percentage of blockage
inside the blockage area and the tool should honor it. By default, 100%
placement is blocked inside the blockage area.

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Basic Terminologies before Floorplan:
● Placement Grid: Placement grid is a multiple of the manufacturing grid in which
all the standard cells are placed. Based on the placement grid, rows are formed
and standard cells are placed.

● Power Domain: It is the collection of instances or blocks that share the same
supply voltage in a design. Each power domain has a separate library associated
with it.

● Routing Blockage: It is the area defined by the designer for the PnR tool to block
routing resources in single or multiple metal layers at a particular area. Routing
blockages can be created and removed at any point in the design based on the
requirements. It is possible to create routing blockages over a block or an
instance using it’s cell type or instance name without the area numbers.
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Basic Terminologies before Floorplan:
● Row: Standard cell row is the area defined for placing standard cells in the
design. Every standard cell in the design sits on the standard cell row. The
row height is based on the standard cell height used in the design. Different
types of rows are possible in a design based on sites or heights of standard
cells used.

● Track: Track is a virtual line (guideline) for the PnR tool in which routing of
metal wires happen in the design. For each metal layer in the design, tracks
are defined for preferred and non-preferred direction with specific pitch
and offset. The PnR tool routes the metal wires by assuming the track at
the center of metal piece.
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Basic Terminologies before Floorplan:
● Voltage Island: It is a dedicated area in the design which has its own row,
site, cells and power structure defined for better power consumption.
Level-shifters are used to convert from one voltage level to another.

● Wire: A physically realized connection of a net which is routed by the router

by having the center of metal piece in the track (on-track) using same or
different metal layers and vias.

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Input files of Floorplan:
● Gate level netlist
● Logical (Timing) & Physical views of standard cells & all other IPs used in
the design
● Timing constraints (SDC)
● Power Intent (UPF / CPF)
● FP DEF & Scan DEF
● Technology file
● RC Co-efficient files

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Introduction:
After given input files this is the first step of physical layout
implementation.

With ever larger designs, it is important to plan a design at an early

stage. This early plan helps constrain later design decisions in terms of
area, wire usage, ports, and port locations.

The early stage plan, a.k.a. a floorplan, is fleshed out with increasing
details with the design flow.

Floorplanning a chip or block is an important task of physical design in

which the location, size, and shape of soft modules, and the placement
of hard macros are decided.
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Introduction:
Depending on the design style or purpose, floorplanning can also

● Include row creation

● I/O pad or pin placement
● Bump assignment (flip chip)
● Bus planning
● Power planning and more.

Typically we use the various floorplanning commands to interactively create a

floorplan. This data then becomes part of the physical data output for the design
using the ROWS, TRACKS, GCELLGRID, and DIE AREA statements. We can manually
enter this data into DEF to create the floorplan.

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Floorplan Steps :
Step 1: Define the outline

The outline of the floorplan can be rectangular or rectilinear. For defining a

rectangular outline we only need height and the width but for rectilinear we
need more co-ordinates. The rectilinear shape can be Plus shape,
L-shape,T-shape or U-shape.

Rectangular shape 17
Plus shape T-shape
Floorplan Steps (Step 2) :
Step 2: Define the Core Area

Where we can place the standard cells in a manner is

called the core area.
Row

All standard cells of the design must be placed inside Row

Height
the core area.

The outside area of the core can be used to place the

I/O pads , I/O pins and core power stripes and rings.
Although there is no restriction for placing macros and
pads inside the core but generally we don’t do it.
Core to IO
boundary
Cells are placed in rows inside the core like a bookshelf
in a library. All cells rows have the same height.

Core area
IO boundary 18
Floorplan Steps (Step 3):
Step 3: Placements of IO pads and
Pins

After defining the core area we can

now place the pins and pads.

For block level layout we can define

and fix the location of the pin by design
physical constraint or randomly.

But for chip level we have to place IO

pads with pad filler cells and corner
cells.
Placement of the Pins (block level)
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Floorplan Steps (Step 3) :

Placement of IO pads (Chip level ) 20

 FloorPlan Steps (Step 4):

Step 4: Placement of hard

macros

The objects to the left of the

core area are the top-level
modules, which can be moved
and reshaped.

The objects to the right of the

chip area are the blocks
( Hard Macros ), which can be
moved but not reshaped.
Floorplan View of a chip level design

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Floorplan Steps (Step 4) :
So we place those blocks or hard macros to complete the floorplan stage.Because
a good macro placement have following qualities :

➔ Provide better utilization of cell placement

➔ Provide a compact layout
➔ Allow us to make robust power planning for macros
➔ Reduce Routing congestion (Make the design more routable)
➔ Make timing closure easy.

Note: Hard macros are basically any kind of instance which is not a standard cell.
Example : Memory ,Ram , Rom & OTP

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Target Utilization Display (Step 4):
The Module constraints, display a target utilization (TU=%) value to represent their physical design size.
This is an estimation of module utilization for the given size of the module where only standard cell and
hard macro areas are considered. Floorplan constraints such as placement blockages are not
considered. This value is calculated by the standard cells area plus the hard macros area, divided by
the module area. The initial TU values are calculated during design import.

The TU percentage helps judge the physical size of a module guide to customize the shape of the
module in the floorplan.

For example, modules P1 and P2 have a TU values of 77.2%. If the modules are reshaped with the same
area, they retain their TU values.

P1
P1

P2
P2 23
Target Utilization Display (Step 4):

For Better results sometimes we place them

in the core area so they are preplaced close
Block
to one another, as shown in the figure. Block

The most important factor is highest priority

P1
of constraints (connectivity between itself
P2
and other modules).

Other floorplan constraints, such as

neighboring preplaced module guides,
preplaced blocks, placement blockages, and
routing blockages, are also considered, but
at a lower priority than connectivity.
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Density calculation (Step 4):

We can determine the core utilization of the core and module sizes by total area
or density or standard cell density.

Core utilization = (std cell area+macro area+halo) / core size

In determining the size of the core area and module guides, standard cells and
hard macros are treated the same.

In PnR tools we can specify the floorplan by using the Core Utilization or Cell
Utilization options.

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Floorplan Steps:
Step 5: Power Planning = (Power + Ground ) routing

power grid network is created to distribute power to each part of the design
equally. Power router create power routings which is considered as pre routes.
And this pre routes will not modified by the detailed router when the signal nets
are routed.
Few things can be considered while we do power planning :
➔ All cells and macros need to be covered during power planning
➔ Minimize routing congestion
➔ Meet electro migration requirements
➔ Acceptable power drop.

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Power Planning (block level) (Step 5):

2. Vertical
stripes

3.Power Rails

1. Core power Rings

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Power Planning block level
Power Planning (Chip level) (Step 5):

In chip level then can be several

voltage domain and different
macros. macro

For that ,we do several power macro

planning so that power can be
distributed homogeneously.
macro

Core rings are added around the core area

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Power Planning (Chip level)(Step 5) :

stripes are added around the stripes over switch cell pins
for each different layer Power rails added 29
Power Planning (Chip level)(Step 5) :

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Pad pins are connected to rings
End of Floorplanning

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