Lovely Professional University, Punjab

Course Code Course Title Course Planner Lectures Tutorials Practicals Credits
CSE211 COMPUTER ORGANIZATION AND DESIGN 23368::Umer Iqbal Wani 3 1 0 4
Course Weightage ATT: 5 CA: 25 MTT: 20 ETT: 50
Exam Category: 55: Mid Term Exam: All Subjective – End Term Exam: All
Subjective
Course Orientation COMPETITIVE EXAMINATION (Higher Education), KNOWLEDGE ENHANCEMENT

Course Outcomes :Through this course students should be able to

CO1 :: review the structure and functioning of a digital computer and understand its overall system architecture.
CO2 :: describe and understand the generic principles that underlie the building of a digital computer, digital logic and memory hierarchy
CO3 :: analyze the working of memory unit and study the examples of mapping techniques for different cache memory systems
CO4 :: understand functioning of the basic building blocks of a computer
CO5 :: visualize the underlying architecture and connection of various hardware components of a computer
CO6 :: develop innovative architectural designs of computers based on the common and fundamental concepts

TextBooks ( T )
Sr No Title Author Publisher Name
T-1 COMPUTER SYSTEM MORRIS MANO PRENTICE HALL
ARCHITECTURE
Reference Books ( R )
Sr No Title Author Publisher Name
R-1 COMPUTER ARCHITECTURE A HENNESSY,J.L,DAVID PEARSON
QUANTITATIVE APPROACH A PATTERSON, AND
GOLDBERG
R-2 COMPUTER ORGANIZATION WILLIAM STALLINGS PRENTICE HALL
AND ARCHITECTURE-
DESIGNING FOR PERFORMANCE

LTP week distribution: (LTP Weeks)

Weeks before MTE 7
Weeks After MTE 7
Spill Over (Lecture) 7
An instruction plan is only a tentative plan. The teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Detailed Plan For Lectures
Week Lecture Broad Topic(Sub Topic) Chapters/Sections of Other Readings, Lecture Description Learning Outcomes Pedagogical Tool Live Examples
Number Number Text/reference Relevant Websites, Demonstration/
books Audio Visual Aids, Case Study /
software and Virtual Images /
Labs animation / ppt
etc. Planned
Week 1 Lecture 1 Basics Of Digital T-1 Introduction to the Students will Demonstration Digital
Electronics(Logic gates) R-2 course understand about with PPT electronics is
Introduction of course contents and based entirely
digital computer, basic of digital on the
Logic gates and flip electronics fundamental
flops principles of
Boolean logic.
Consider the
following
devices: i . A
soda machine
which accepts
coins and
dispenses cans
of soda ii. a
microwave oven
with
programmable
power levels and
timers iii. a
hand-held
calculator

An instruction plan is only a tentative plan. The teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 1 Lecture 1 Basics Of Digital T-1 Introduction to the Students will Demonstration Digital
Electronics(Introduction to R-2 course understand about with PPT electronics is
combinational circuit) Introduction of course contents and based entirely
digital computer, basic of digital on the
Logic gates and flip electronics fundamental
flops principles of
Boolean logic.
Consider the
following
devices: i . A
soda machine
which accepts
coins and
dispenses cans
of soda ii. a
microwave oven
with
programmable
power levels and
timers iii. a
hand-held
calculator
Basics Of Digital T-1 Introduction to the Students will Demonstration Digital
Electronics(introduction to course understand about with PPT electronics is
sequential circuits) Introduction of course contents and based entirely
digital computer, basic of digital on the
Logic gates and flip electronics fundamental
flops principles of
Boolean logic.
Consider the
following
devices: i . A
soda machine
which accepts
coins and
dispenses cans
of soda ii. a
microwave oven
with
programmable
power levels and
timers iii. a
hand-held
calculator
Lecture 2 Basics Of Digital T-1 Introduction to Students will Demonstration
Electronics(Multiplexers and R-2 multiplexers, Decoders, understand how with diagrams
De multiplexers) Flip flops Muxs, Decoders, Flip
flops function

An instruction plan is only a tentative plan. The teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 1 Lecture 2 Basics Of Digital T-1 Introduction to Students will Demonstration
Electronics(Decoder and multiplexers, Decoders, understand how with diagrams
Encoder) Flip flops Muxs, Decoders, Flip
flops function
Basics Of Digital T-1 Introduction to Students will Demonstration
Electronics(Flip flops) R-2 multiplexers, Decoders, understand how with diagrams
Flip flops Muxs, Decoders, Flip
flops function
Lecture 3 Register Transfer and Micro T-1 Discussion on Bus and i. Students will Demonstration
Operations(Register Memory Transfers, Bus understand transfer with images
Transfer Language and selection and three state between Processor
Register Transfer) bus buffers registers through
buses ii. Understand
transfer between
Processor register
and memory through
buses
Week 2 Lecture 4 Register Transfer and Micro T-1 Operations are Student will learn Peer Learning
Operations(register transfer) performed on the binary about the 16 Logical
data stored in the micro-operations and
register practice its
applications

An instruction plan is only a tentative plan. The teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 2 Lecture 5 Register Transfer and Micro T-1 Discussion on Shift .Students will Demonstration The most
Operations(Logic Micro R-2 registers ( left and right understand about data with PPT common uses of
Operations) shift registers etc.) storage in shift a shift register is
registers. ii. to convert
Understand the between serial
movement of data in and parallel
shift registers. interfaces. This
is useful as
many circuits
work on groups
of bits in
parallel, but
serial interfaces
are simpler to
construct. ii.
Shift registers
can be used as
simple delay
circuits. iii.
Bidirectional
shift registers
could be
connected in
parallel for a
hardware
implementation
of a stack.

Lecture 6 Register Transfer and Micro T-1 Introduction of micro- i. Students will Discussion with Internal
Operations(arithmetic operations and internal understand about Images hardware
microoperations) hardware organization processing task of organization of a
of a digital computer. digital hardware digital computer
modules. ii.
Understand the
Micro-operations of
system.
Week 3 Lecture 7 Register Transfer and Micro T-1 Discussion on Students will learn Peer Learning
Operations(Shift Micro Arithmetic and logical about the working of
Operations) shift unit ALSU
Lecture 8 Computer Organization T-1 Introduction to basic i. Students will Discussions with
(instruction codes) computer organization understand about images and PPT
and show how its internal
operation can be registers,control
specified with register structure and
transfer statement. instruction . ii.
Understanding of
Common bus system

An instruction plan is only a tentative plan. The teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 3 Lecture 9 Computer Organization T-1 Introduction to basic i. Students will Discussions with
(computer registers) computer organization understand about images and PPT
and show how its internal
operation can be registers,control
specified with register structure and
transfer statement. instruction . ii.
Understanding of
Common bus system
Week 4 Lecture 10 Computer Organization T-1 Discussion on basic Students will Discussion with Control Unit of
(common bus system) computer instruction understand the images a computer
format and timing for elements of modern system
register instructions sets and
explain their impact
on processor desig
Lecture 11 Computer Organization T-1 Explain the basics of . Understand the discussions with
(instruction cycle) instruction execution on characteristics of an image
a computer. instruction set and
how it maps to
underlying hardware.
ii. Identify and
analyze the design
and function of the
basic instruction
execution elements of
a modern processo
Lecture 12 Computer Organization T-1 Discussion on memory Students will identify Discussion
(memory reference reference instructions and analyze the thorough
instructions) and interrupt cycle design and function knowledge and
of the basic understanding of
instruction execution key concepts
elements of a modern
processor
Computer Organization T-1 Discussion on memory Students will identify Discussion
(input-output and interrupt) reference instructions and analyze the thorough
and interrupt cycle design and function knowledge and
of the basic understanding of
instruction execution key concepts
elements of a modern
processor
Week 5 Lecture 13 Test 1
Lecture 14 Central Processing Unit T-1 Introduction to various i) Understand the Discussion with
(General Register data processing organization and examples
Organization) operations performed in architecture of CPU.
CPU and storage device ii) To understand
that store information stack based processor
organization. ii.
Instruction set of a
stack organized
processor

An instruction plan is only a tentative plan. The teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 5 Lecture 15 Central Processing Unit T-1 Describing about
(Data Transfer and different modes of
Manipulation) transfer and categories
of computer instruction
including program
control instructions
Central Processing Unit T-1 Describing about
(Program control) different modes of
transfer and categories
of computer instruction
including program
control instructions
Week 6 Lecture 16 Central Processing Unit T-1 Describing about
(Addressing Modes) different modes of
transfer and categories
of computer instruction
Students will learn Peer Learning
about computer
instruction and data
transfer instruction
Students will learn Peer Learning
about computer
instruction and data
transfer instruction
Students will learn Students will learn
about computer about computer
instruction and data instruction and
transfer instruction data transfer
instruction

Lecture 17 Central Processing Unit T-1 CISC and RISC variable Students will peer learning
(Complex instruction set length instructions in understand the CISC
computer) multiple cycles and RISC
Architecture
Lecture 18 Central Processing Unit T-1 CISC and RISC variable Students will peer learning
(Reduced instruction set length instructions in understand the CISC
computer) multiple cycles and RISC
Architecture
Week 7 Lecture 19 Central Processing Unit T-1 CISC and RISC variable Students will peer learning
(Reduced instruction set length instructions in understand the CISC
computer) multiple cycles and RISC
Architecture

SPILL OVER
Week 7 Lecture 20 Spill Over
Lecture 21 Spill Over

MID-TERM
Week 8 Lecture 22 Input-Output Organization T-1 Introduction to input Students will Discussion with
(Input Output Interface) output subsystem of a understand the mode images
computer of communication
between the central
system and out side
environment

An instruction plan is only a tentative plan. The teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 8 Lecture 22 Input-Output Organization T-1 Introduction to input Students will Discussion with
(Data transfer schemes) output subsystem of a understand the mode images
computer of communication
between the central
system and out side
environment

Lecture 23 Input-Output Organization T-1 Discussion on types of . Students will Discussion with A sound card
(Direct memory access data transfer schemes understand the Image may need to
transfer) and Discussion on DMA concept of Direct access data
used when multiple memory access to stored in the
bytes are to be memory for data computer's
transferred between transfers ii. Learn RAM, but since
memory and IO devices how DMA used when it can process
multiple bytes are to the data itself, it
be transferred may use DMA
between memory and to bypass the
IO devices iii. Learn CPU. Video
DMA Data transfer cards that
mechanism between support DMA
I/O devices and can also access
system memory with the system
the least processor memory and
intervention using process graphics
DMAC without needing
the CPU. Ultra
DMA hard
drives use DMA
to transfer data
faster than
previous hard
drives that
required the data
to first be run
through the CPU

An instruction plan is only a tentative plan. The teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 8 Lecture 23 Input-Output Organization T-1 Discussion on types of
(Input/Output processor.) data transfer schemes
and Discussion on DMA
used when multiple
bytes are to be
transferred between
memory and IO devices
Lecture 24 Input-Output Organization T-1 Discussion on types of
(Input/Output processor.) data transfer schemes
and Discussion on DMA
used when multiple
bytes are to be
transferred between
memory and IO devices
Week 9 Lecture 25 Input-Output Organization T-1 Introduction to input
(Priority interrupt) output subsystem of a
compute
Input-Output Organization T-1 Introduction to input
(modes of data transfer) output subsystem of a
compute
An instruction plan is only a tentative plan. The teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
. Students will Discussion with
understand the Image
concept of Direct
memory access to
memory for data
transfers ii. Learn
how DMA used when
multiple bytes are to
be transferred
between memory and
IO devices iii. Learn
DMA Data transfer
mechanism between
I/O devices and
system memory with
the least processor
intervention using
DMAC
. Students will Discussion with
understand the Image
concept of Direct
memory access to
memory for data
transfers ii. Learn
how DMA used when
multiple bytes are to
be transferred
between memory and
IO devices iii. Learn
DMA Data transfer
mechanism between
I/O devices and
system memory with
the least processor
intervention using
DMAC
Students will Discussion with
understand the mode images
of communication
between the central
system and out side
environment
Students will Discussion with
understand the mode images
of communication
between the central
system and out side
environment
Week 9 Lecture 26 Memory hierarchy(main T-1 Describing about RAM Students will learn Peer discusion Content
memory) and ROM chips , about content addressable
Auxiliary memory is addressable memory memory is often
also discussed. used in
Associative memory- computer
Describing about networking
Argument register devices. For
Match Logic etc example, when a
network switch
receives a data
frame from one
of its ports, it
updates an
internal table
with the frame's
source MAC
address and the
port it was
received on. It
then looks up
the destination
MAC address in
the table to
determine what
port the frame
needs to be
forwarded to,
and sends it out
on that port. The
MAC address
table is usually
implemented
with a binary
CAM so the
destination port
can be found
very quickly,
reducing the
switch's latency

An instruction plan is only a tentative plan. The teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 9 Lecture 26 Memory hierarchy(auxiliary T-1 Describing about RAM Students will learn Peer discusion Content
memory) and ROM chips , about content addressable
Auxiliary memory is addressable memory memory is often
also discussed. used in
Associative memory- computer
Describing about networking
Argument register devices. For
Match Logic etc example, when a
network switch
receives a data
frame from one
of its ports, it
updates an
internal table
with the frame's
source MAC
address and the
port it was
received on. It
then looks up
the destination
MAC address in
the table to
determine what
port the frame
needs to be
forwarded to,
and sends it out
on that port. The
MAC address
table is usually
implemented
with a binary
CAM so the
destination port
can be found
very quickly,
reducing the
switch's latency

An instruction plan is only a tentative plan. The teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 9 Lecture 26 Memory hierarchy T-1 Describing about RAM Students will learn Peer discusion Content
(associative memory) and ROM chips , about content addressable
Auxiliary memory is addressable memory memory is often
also discussed. used in
Associative memory- computer
Describing about networking
Argument register devices. For
Match Logic etc example, when a
network switch
receives a data
frame from one
of its ports, it
updates an
internal table
with the frame's
source MAC
address and the
port it was
received on. It
then looks up
the destination
MAC address in
the table to
determine what
port the frame
needs to be
forwarded to,
and sends it out
on that port. The
MAC address
table is usually
implemented
with a binary
CAM so the
destination port
can be found
very quickly,
reducing the
switch's latency
Lecture 27 Test 2
Week 10 Lecture 28 Memory hierarchy(cache T-1 Discussion on types of Students will learn Peer Learning
memory) mapping techniques in about basic concepts
cache memory of cache memory

Lecture 29 Memory hierarchy(virtual T-1 Discussion on page table Students will Discussion with
memory) ,memory mapping table understand about how images
to manage memory
space and address
space

An instruction plan is only a tentative plan. The teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Week 10 Lecture 30 Introduction to Parallel T-1 Detailed discussion on Introduction to Peer Learning
Processing(Pipelining) instruction pipelining in pipelining and its
computer. types
Week 11 Lecture 31 Introduction to Parallel T-1 Detailed discussion on Introduction to Peer Learning
Processing(Pipelining) instruction pipelining in pipelining and its
computer. types
Lecture 32 Introduction to Parallel T-1 Introduction to parallel Amdahl's law , Discussion with
Processing(Characteristics R-1 processing and chracteristics of examples
of multiprocessors) multiprocessors multiprocessors
Introduction to Parallel T-1 Introduction to parallel Amdahl's law , Discussion with
Processing(parallel R-1 processing and chracteristics of examples
processing) multiprocessors multiprocessors
Lecture 33 Introduction to Parallel T-1 Various multiprocessor Students will learn Discussions with
Processing(Interconnection R-1 interconnection about Time-shared, images and
Structures) structures Multiport memory, diagrams
crossbar switch,
hypercube
interconnection
Week 12 Lecture 34 Test 3
Lecture 35 Multiprocessors T-1 Different categories of Students will learn Discussion with
(Categorization of R-1 multiprocessors, about multiprocessor images
multiprocessors introduction to GPU calssification, and
(SISD,MIMD,SIMD.SPMD) GPU
, Introduction to GPU)
Lecture 36 Multiprocessors T-1 Different categories of Students will learn Discussion with
(Categorization of R-1 multiprocessors, about multiprocessor images
multiprocessors introduction to GPU calssification, and
(SISD,MIMD,SIMD.SPMD) GPU
, Introduction to GPU)
Week 13 Lecture 37 Latest technology and trends T-1 Latest processor Student will learn Demonstration and
in computer architecture R-1 architecture study is about latest processor discussions
(multi-cores processor.) done architectures
Latest technology and trends T-1 Latest processor Student will learn Demonstration and
in computer architecture R-1 architecture study is about latest processor discussions
(microarchitecture) done architectures
Lecture 38 Latest technology and trends T-1 Discussion on new Students will learn Peer Learning
in computer architecture R-1 nonvolatile memory about new processor
(latest processor for technology and and new memory
smartphone or tablet and discussion on various technology with there
desktop) processors architectures
Lecture 39 Latest technology and trends T-1 Discussion on new Students will learn Peer Learning
in computer architecture R-1 nonvolatile memory about new processor
(latest processor for technology and and new memory
smartphone or tablet and discussion on various technology with there
desktop) processors architectures

An instruction plan is only a tentative plan. The teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
 Week 14 Lecture 40 Latest technology and trends T-1 Latest processor Student will learn Demonstration and
in computer architecture R-1 architecture study is about latest processor discussion
(next generation processors done architectures
architecture)

SPILL OVER
Week 14 Lecture 41 Spill Over
Lecture 42 Spill Over
Week 15 Lecture 43 Spill Over
Lecture 44 Spill Over
Lecture 45 Spill Over

Scheme for CA:

CA Category of this Course Code is:A0203 (2 best out of 3)

Component Weightage (%) Mapped CO(s)

Test 1 50 CO1, CO2
Test 2 50 CO2, CO4, CO5
Test 3 50 CO3, CO5, CO6

Details of Academic Task(s)

Academic Task Objective Detail of Academic Task Nature of Academic Academic Task Marks Allottment /
Task Mode submission
(group/individuals) Week
Test 1 To check the subject Will be covering syllabus from Week 1 to Week 5. All Individual Offline 30 4/5
understanding and questions should be of 5 marks each or in multiples of 5
learning ability of
the students
Test 2 To check the subject Will be covering syllabus from Week 6 to Week 8. All Individual Offline 30 8/9
understanding and questions should be of 5 marks each or in multiples of 5
learning ability of
the students
Test 3 To check the subject Will be covering syllabus from Week 9 to Week 11. All Individual Offline 30 11 / 12
understanding and questions should be of 5 marks each or in multiples of 5
learning ability of
the students

An instruction plan is only a tentative plan. The teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.
Plan for Tutorial: (Please do not use these time slots for syllabus coverage)

Tutorial No. Lecture Topic Type of pedagogical tool(s) planned

(case analysis,problem solving test,role play,business game etc)

Tutorial1 Problem Solving on Logic Gates Problem Solving

Tutorial2 Problems based on Bus and Memory transfer and Arithmetic and shift Problem Solving
Micro operations
Tutorial3 Problem Solving on Register transfer and Register transfer language and Problem Solving
Instruction Codes
Tutorial4 Problem Solving on Control Timing Signals and Instruction Cycle Problem Solving
Tutorial5 Problem Solving on Memory Reference Instructions and Input Output Problem Solving
interrupt
Tutorial6 Problem Solving on program and Micro Program Control, Problem Solving
Tutorial7 Problem Solving on Data Transfer, Manipulation and Addressing Modes Problem Solving
After Mid-Term
Tutorial8 Problem Solving on Data Transfer Schemes, Program Control and Problem Solving
Interrupts
Tutorial9 Problem Solving on Direct Memory Access and Memory Hierarchy Problem Solving
Tutorial10 Problem Solving on Cache Memory, Associative Memory and Virtual Problem Solving
Memory
Tutorial11 Problem Solving on Pipelining Problem Solving
Tutorial12 Problem Solving on Amdahl's law Problem Solving
Tutorial13 Problem solving on interconnection structures Problem Solving
Tutorial14 Problem Solving on GPU Problem Solving

An instruction plan is only a tentative plan. The teacher may make some changes in his/her teaching plan. The students are advised to use syllabus for preparation of all examinations. The students are expected to keep themselves
updated on the contemporary issues related to the course. Upto 20% of the questions in any examination/Academic tasks can be asked from such issues even if not explicitly mentioned in the instruction plan.