The 5th Power Electronics, Drive Systems and Technologies Conference (PEDSTC 2014), Feb 5-6, 2014, Tehran,
Iran firPEDSYc-J'
A New Cascaded Multilevel Inverter Structure
with Less Number of Switches
Elyas Zamiri, Sajjad Hamkari, Majid Moradzadeh, Ebrahim Babaei, Member IEEE
Faculty of Electrical and Computer Engineering, University of Tabriz
Tabriz, Iran
elyaszamiry@yahoo. com, sajjad. hamkari@yahoo. com, moradzadeh. majid@yahoo. com, e-babaei@tabrizu. ac. ir
Abstract-Because of many features of multilevel inverters, its
applications in industries are not negligible. This paper proposes
a new topology for multilevel inverters that has been obtained
from series blocks of sub multilevel inverter. One of the issues in
this kind of inverters is quantity of switches. The proposed
inverter consists of fewer number of power electronic switches
which leads to lower switching loss, weight, and cost
comparison with conventional inverters. Another advantage of
this structure is its modular capability. In this paper, three
algorithms are considered to determine the size of DC voltage
source and eventually accuracy of proposed inverter has been
approved by PSCAD/EMTDC software.
Keywords- Cascaded inverter; Multilevel inverter; Optimal
structure; DCIAC converter
I. [NTRODUCTION
Multilevel inverters are composed of a number of power
electronic switches and DC voltage sources that produce a
stepped voltage waveform in its output [1]. Generally,
multilevel inverters are divided into three categories [2-3] as
follows: neutral-point clamped inverter (NPC) [4], flying
capacitor inverter (FC) [5], and cascaded H-bridge inverter
(CHB) [6]. These inverters can surrender higher power with
lower dv/dt and di/dt in output waveform which is to reduce
EM[ noise and Size of the output filter. Therefore, using these
inverters is very common nowadays [7]. [n recent years,
several architectures have been proposed for cascade
multilevel inverters [8-12]. This kind of inverters can produce
more voltage levels and also provide higher quality of power
in its output. As a result, this kind of inverter is considered
more than other kinds of inverters [13]. Cascade inverters are
made of series separate single phase inverters with separate dc
voltage sources. On the other hand, this inverter consists of a
number of basic blocks (sub mu[tileve[ inverter) that each of
these blocks has similar control system [14]. One of the major
advantages of this type of inverters is the ability of its
modulation. So, if an error occurs in one of the blocks, it can
replace or fix by using a control system [[ 5], but there are
some disadvantages such as high number of dc voltage sources
and power electronic switches [16]. Increasing the number of
power electronic switches leads to increase the number of
driver circuits too. Both of these issues caused to increase in
complexity, size, and cost of the circuit. Thus, reducing the
number of power electronic switches is very vital and should
978-1-4799-3479-9/14/$31.00 ©2014 IEEE
be considered [17]. [n this paper, a new structure has been
proposed for cascaded inverters. The proposed structure has
fewer number of power electronic switches in comparison
with other conventional ones which is based on a basic
structure using three power electronic switches and two dc
voltage sources. Generalized multilevel inverter is presented
in
as series connection of these blocks. The main advantage of
the proposed inverter is the fewer number of power electronic
switches and also no need for a complicated control system. In
this paper, three algorithms are used to determine the size of
the dc voltage sources. Value of each voltage sources is
assumed the same in the first algorithm. The second algorithm
is designed to have the maximum number of voltage levels,
and the third algorithm is proposed for using of SPWM
modulation. The rest of the paper is organized as follows:
In Section II, t he circuit topology that consists of series
connection basic structure is introduced. In Section III, three
different algorit hms have been proposed to determine the size
of the dc voltage sources. [n Section [V the comparison is
done between the proposed structure and other conventional
structure based on the criteria as follows: Number of
switches, number of on-state switches for each level and total
blocking voltage switches. Simulation results are presented in
Section V and finally conclusion is presented in Section VI.
II. PROPOSED STRUCTURE
A. basic proposed structure
Figure 1 shows the basic model of our proposed structure.
As can be seen, this structure consists of two dc voltage
sources and three power electronic switches. [t can produce
positive, zero, or negative voltage levels in its output. In this
structure, Sa and S" are one directional switches, but Sc is
bidirectional switch. Obviously, the switches Sa ' Sb and
Sc should not be ON in the same time with each other.
Otherwise, it will cause short circuit of the dc voltage sources.
For example, when the switch Sa is in ON state, the switches
Sh and Sc should be in OFF state. Different values of the
output voltage ( va ) for different switching states is shown in
Table 1 . As can be seen from this Table, each of the output
voltage levels has just generated by turning on a switch that
leads to reduce switching losses. Another criterion for
comparing multilevel inverters is their maximum blocked
199
voltage by switches. Maximum blocked voltage for each (7)
switch is shown in Table 2.

+ +

�,. l
•
+ �)'ock = Vz,'ocka �)'ock,h Vz,'ock,c
=2Vdc + 2Vdc + Vdc (8)
=5 Vdc
c ,

I •
It should be noted that according to the structures been used
Figure 1. Basic model of the proposed structure for three-level inverter
for power electronic switches (one directional or bidirectional),
the number of power diodes is always equal to the number of
IGBTs.

TABLE I. DIFFERENT SWITCHING STATES FOR BASIC STRUCTURE B. proposed structure

In order to achieve higher levels in output voltage, series
Switch states connection of the proposed basic structure can be used
State Vo according to Figure 2. In the structure shown in Figure 2, the
Sa S" Sc
units first, second, . . . , nth are dc voltage sources with sizes
1 0 1 0 Vdc Vdc,] , Vdc,2' · · ·' Vdc,n' respectively. As can be seen, the number
of dc sources used in the proposed structure is more than other
2 0 0 I 0
conventional structures which can be considered as one of the
3 I 0 0 -Vdc disadvantages of the proposed structure. Different values of the
output voltage (vo ) for different switching states is shown in
Table 3.
TABLE II. MAxIMUM BLOCKING VOLTAGE (MBV) BY SWITCHES FOR
PROPOSED BASIC STRUCTURE

Sa Sb Sc

f
Switches •

So, \ S� l
MVB 2Vdc 2Vdc Vdc +

den �
In the proposed structure, number of switches (N ", ; ,ch ) ,

T I
s"

T
number of IGBTs (NIGBl,), number of drivers ( N dr;ver ) ' number V, V.,.

of output voltage levels ( N/eve! ) , number of dc voltage sources

(N "",rcJ, variety of dc voltage sources ( NmrieIY ) , maximum
output voltage (v:"max) ' and total blocking voltage by switches •

•
(Vz,/ock ) are obtained from following equations, respectively: •

t
So
l � J
NSWilch =3 (1 ) Vn

de,2 de,2
s
s
NIGBl =4 (2) V V

N dril'er =3 (3)

N'eve/ =3 (4) S� Se
N,lOlirce =2 (5)
v"
TL- _l l ___ ___
....
.

Nvar;ety =1 (6) Figure 2. Generalized Proposed Structure

200
 TABLE II!. DIFFERENT SWITCHING STATES FOR GENERALIZED STRUCTURE

Switch states

Sa,] Sa,2 ... Sa,n Sh,] Sh,2 ... Sh,n SC,] Sc,2 ... Sc,n Vo

0 0 ... 0 1 1 ... 1 0 0 ... 0 Vdc,] + Vdc,2 + ... + Vdc,n

... ... ... ... ... ... ... ... ... ... ... ...
1 0 ... 0 0 1 ... 0 0 0 ... 1 -Vdc,] + Vdc,2
... 1 1 ... ... Vdc,] + Vdc,2
0 0 ... 0 0 1 ... 0 1 0 ... I Vdc,2
0 0 0 0 1 0 ... 0 0 1 ... 1 Vdc,]
0 0 ... 0 0 0 ... 0 1 I ... I 0

1 0 ... 0 0 0 ... 0 0 1 ... 1 -Vdc,]

0 1 ... 0 0 0 ... 0 1 0 ... 1 -Vdc,2
I I ... 0 0 0 ... 0 0 0 ... I -Vdc,] -Vdc,2
0 I ... 0 1 0 ... 0 0 0 ... I Vdc,] -Vdc,2
... ... ... ... ... ... ... ... ... ... ... ... :

1 1 ... 1 0 0 ... 0 0 0 ... 0 -Vdc,] -Vdc,2 -... -Vdc,n

(12)
III. THE ALGORITHMS FOR DETERMINING DC VOLTAGE
SOURCE AMPLITUDE

Number of output voltage levels (N'el'ei) in multilevel N'evei =2n -1 (13)

inverter Fig. 2, depends on the dc voltage sources amplitude
determination algorithms. Therefore without having the so
called algorithm, obtaining the comprehensive equation for N,ullrce =2n (14)
N'evei is unachievable.

First algorithm
Nvw7ety =I
A. (15)
If amplitude of each dc voltage sources in the proposed
structure was identical and each of them equals to Vdc , number
of output voltage levels obtains from (9). n
Vo,max = I
j =]
VdC,j =5n Vdc (16)

Vde,}, =Vdc for j =1,2,3,.. ·,n (9)

According to this algorithm number of switches, IGBTs, Vblock =Vblock,a + Vblock,b + Vblock,c
driver circuits, output voltage levels, dc voltage sources, n
(17)
variety of dc voltage sources, also maximum output voltage
amplitude and total switches blocking voltages are calculated I
= ( �)Iock,a,j + �)Iock,h,j + �)Iock,c,j)
j=]
by following equations.

B. Secon d algorithm
N,lwifCh = 3n (10)
In order to have maximum output voltage level, second
algorithm is applied. Since each stage of proposed structure is
able to make both of positive and negative levels, then for
NJGHT =4n (11) obtaining the maximum output voltage level, amplitude of dc
voltage sources in each stage is calculated from (18).

201
 1
Vde,; =y- Vde for j=1,2,3,"',n (1 8) (modulation frequency), that cause reducing of switching
losses in proposed structure.

r-
for j=1
According to this algorithm number of switches, IGBTs, Vde! = 2Vde,H for j=2 (27)
driver circuits, output voltage levels, dc voltage sources, 3Vdc,I_1 for j=3,4,"',n
variety of dc voltage sources, also total switches blocking
voltages and maximum output voltage amplitude are calculated
by following equations.

N"lVilCh = 3n (1 9) According to this algorithm number of switches, IGBTs,

driver circuits, output voltage levels, dc voltage sources,
variety of dc voltage sources, also maximum output voltage
amplitude and total switches blocking voltages are calculated
NIGBl, =4n (20)
by following equations.

Ndriver = 3n (21 ) NSWilCh = 3n (28)

N'e)'e' = 3/1 (22) NIGBl =4n (29)

Nwu rce =2n (23) Ndri)'er = 3n (30)

n1
Nvariety =n (24) Nlevel =2(3 - ) + 1 (31 )

Nsull rce =2n (32)

V bluck =V bluck + V bloek ,b + V bloek ,e
,0

n
I
= (VbIOCk,a,j + V block,b,j + V block,c,j)
j �I Nvar;ct:v =n (33)
= (V de,1 +V "<2 + ... +V de,n) +
2 (25)

5(3/1 - l)
= V dc
2
I
/I

V;"max = Vde,j
n j�1
n2
"
Vo,max = � Vde,) =Vdc + 2Vde + 6Vdc + ... + 2(3 - )Vde (34)
i�1 n
=(3 -l)Vdc
(26)

V block =V hlock,a + V block ,b + V hlock ,c

n
C. Third algorithm I
= (V bloek,a,j + V bloek,b,j + V bloek,c,j)
j �I
In order to apply modulation on the proposed structure,
third algorithm is used for determining the dc voltage sources =2(Vde ,1 +v dc,2 + .. · + V de n) +
'
(35)
amplitude. If amplitude of dc voltage sources calculated from
2(V dc,1 + V dc,2 +", + Vdc,n) + (Vdc,1 + V d<2 +", + V dc,n)
(27), only first stage switches are switching in high frequency
I
=5(3/1- )V de

202
 TABLE IV. COMPARISON BETWEEN THE PROPOSED STRUCTURE AND CHB INVERTER

Symmetric Proposed Trinary Proposed

Symmetric CHB Trinary CHB
inverter inverter
Number of switch and 3(Nlevel - 1) 31og;znd
2(Nleve/ - I) 41og;I"'1
driver 2
N1e1oel - 1
Number of ON switch N1evel - 1 21og;bd log;h�d
2
5(N1evel - 1) 5(Nlevel - 1)
�)l ock 2(Nleve/ - 1)Vdc 2(N1e,.el - 1)Vde Vde
2 2

IV. COMPARISON WITH SIMILAR STRUCTURE +

The main aim of presenting proposed multilevel inverter is

reduction in number of power electronic switches. Each of the �S,
S1'.2
165Vl
switches in the proposed structure is composed of an IGBT
with a reverse diode. Each of these IGBTs requires a driver
circuit [ IS]. Thus, reduction in the number of switches cause
reduction of the size, weight and cost of the proposed inverter.
Also one of the important parameters in multilevel inverter is
the number of switches that is in conducting status to produce

:�
the voltage levels, which are directly related with Conduction
losses. Another important factor in multilevel inverters is total S
d
1

T I
S
switch blocking voltage. According to Number of switches, d
55V 55
drivers, ON switches to produce different voltage and total
switch blocking voltage, in TableA Comparison between the T
proposed structure and cascade half bridge (CRB) inverter is •
shown. Meanwhile, the number of output voltage levels is
Figure 3. Proposed structure based on second algorithm (nine levels)
assumed equal to N1evel . It is noted that the number switches of
proposed structure is less than CRB inverter. As a result, the
number of reverse diodes and driver circuits are also
proportionally less. Also the number of ON switches to
produce each level in proposed structure is half of CRB TABLE V. SIMULATED LOAD INFORMAnON
structure in same condition. For this reason the switch
conduction losses is half. But as you can see in Table4, the Power factor
State Load (R-L)
total blocking voltage is increased. (cos¢»)

a OQ - 0. 1H 0
b 10Q - 0.05H 0.5 3 7
c 50Q - 0. IH 0.847

d 50Q - OH 1
V. SIMULATION RESULTS

In this section, for evaluating of proposed structure

operation, output voltage and current waveforms are obtained
Output voltage and current waveforms for different loads is
from simulation in PSCAD/EMTDC software. In
shown in Fig. 4. According to Fig. 4 output voltage levels are
determination of dc voltage sources amplitude, second
nine. In the figures 4.a,b,c because of inductivity of the load, it
proposed algorithm which is presented in section III is used.
operates not only like the low pass filter, that makes output
According to the table 5 the system is simulated with RL load.
current waveform near to completely sinusoidal waveform,
Nine level structure Fig. 3, of proposed inverter is used for
producing the output sinusoidal waveform with 220 rms but also makes phase displacement between output voltage
voltage and 50Hz frequency. Table 6 shows the switching and current waveforms. In FigA,d because of resistive load,
status of simulated structure. output voltage and current waveforms are the same, with only
different in the amplitudes.

203
TABLE VI. DIFFERENT SWITCHING STATUS FOR NINE LEVEL STRUCTURE VL CONCLUSION

V /oad[pU] Switching status In this paper, a new structure is proposed for cascaded
multilevel inverter. In the proposed structure minimum number
55 V = I pu Sa,] Sh,] SC,] Sa,2 Sh,2 Sc,2
of power electronic switches is used, that not only reduces size,
4 0 1 0 0 1 0 weight and cost of the circuit but also reduces the switching
losses. Modularity of the proposed system made debugging
3 0 0 I 0 1 0 easy and reduces complexity of the system. In the proposed
structure, three different algorithms are used to determine the
2 I 0 0 0 1 0
dc voltage sources amplitude. The accuracy of the proposed
1 0 1 0 0 0 1 structure has been approved by the PSCADIEMTDC software.

0 0 0 1 0 0 1
-1 1 0 0 0 0 1
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204