Professional Documents
Culture Documents
Homework #2
Upload your homework solution to ecampus as a single pdf file. Your homework solution should include
a listing of any C code or Verilog code, along with any output obtained when the code is run. DO NOT
include pictures of your code in your homework solution file, instead, copy the text of your C or Verilog
code into your homework solution file. DO NOT upload a zip file. You will have only ONE attempt to
upload your homework solution.
In addition, your source code (any C code or Verilog code or testbenches) should be sent via email to
449and749graders@gmail.com. Your email title should state your NAME, SECTION NUMBER and
HOMEWORK NUMBER. Name your files in a way that identifies the homework number and the question
(e.g. hw1-Q1b.v). For all the code that you write, please provide comments for full credit.
1. [15 points.] Consider a digital circuit as shown in Figure 1 with three inputs A, B, C and two
outputs X, Y. At time t = 20, the inputs make a transition as : A = 1->0, B = 0->1, C =
1->0.
Perform event driven timing simulation of the circuit and plot the waveforms of X, Y, P and Q as a
function of time. The delays of individual gates are mentioned in the figure.
1
2 Homework #2
Figure 1: Circuit 1
int abc(int x)
{
int i= 0;
while (x)
{
i++;
x >>= 1;
}
return (i);
}
Find the values returned by abc(562) and abc(401). What is the purpose of this function in the
context of digital logic?
3. [15 points.]
Consider the makefile given below. The files: colleges.c, dept.c, faculty.c, research grp.c, stu-
dent info.h, net id info.h and address.h are all within the same directory as makefile.
university: colleges.o dept.o faculty.o research grp.o
gcc -o university colleges.o dept.o faculty.o research grp.o
clean:
rm -rf *.o student info.h
(a) Assume that there are no binary files in the directory to begin with, what new files would be
generated after the make command is executed? Also write the order of files’ creation.
(b) Suppose I run touch student info.h and then execute make again in the above directory.
What new files would be generated in this case and in what order?
(c) Suppose I run make clean. What would be the problem when I run make again? What file
would I need to copy to my working directory to handle this problem?
(a) The equivalent gate count for a piece of Verilog code is 500 and the equivalent gate count for
another piece of Verilog code is 40,000. If both pieces of Verilog code are separately synthesized
into an FPGA, is there a difference in the size of the two bitstreams? Give reason for your answer.
(b) For the following Verilog code snippets, starting from time t = 0 draw the waveforms of a
and b with respect to time. Assume that at time t = 0 a rising event occurs on clk. When
we enter the always block, assume that a and b are in an X state. Explain the reason for the
difference between the waveform of the two code snippets.
Code A:
a = #2 0;
b = #1 1;
b = #1 0;
end
Code B:
(a) N0 = 14, B0 = 5, B1 = 7
(b) N0 = 300, B0 = 5, B1 = 3
(c) N0 = 11122, B0 = 6, B1 = 7
Consider the name of the function as: int numConversion(int N0, int B0, int B1)