Multiple Clock Domains

A DSP Builder model can operate using multiple Simulink sampling periods. You can
specify the clock domain in some DSP Builder block sources, such as the Counter
block. You can also specify the clock domain in DSP Builder rate change blocks such
as Tsamp.
When using multiple sampling periods, DSP Builder must associate each sampling
period to a physical clock domain that can be available from an FPGA PLL or a clock
input pin. Therefore, the top-level DSP Builder model must contain DSP Builder rate
change blocks such as PLL or Clock_Derived.
You can use a PLL block to synthesize additional clock signals from a reference
clock
signal. These internal clock signals are multiples of the system clock frequency.
f Refer to �Using the PLL Block� on page 3�14 for more information.

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