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Abstract - This paper details the code development, implementation and testing of basic behaviour and characterization of the
biological neuron model in FPGA environment. In this work, the real behavior and function of biological human neuron was
studied and implemented as an artificial neuron in VHDL environment. To develop the biological neuron model, Perceptron
algorithm was employed. The artificial biological neuron contains sub blocks such as timer, alpha, addition & comparison and
inhibit blocks. Initially, the sub blocks were developed individually and combined together according to the biological neuron model
design. Simulation codes for the artificial neuron model were developed using VHDL language. Finally, the developed artificial
neuron model was implemented on ANVYL SPARTAN-6 XC6SLX45 CSG484 package FPGA kit and the outputs were exhibited as
simulation output in the PC monitor as well as in the LED indicators of the Anvyl Board. This work helps to learn the strategies of
developing codes for neuronal behaviour study using FPGA and VHDL language, which will be extended to advanced applications
like computational neuroscience and artificial intelligence.
Fig. 10 Output for Timer block Fig 12.Output for Addition/Comparision block
From the Fig. 10, it was observed that till the count of 0.4,
O. Inhibit block
the the first input was processed. After the completion of
this process, the counter was automatically reseted, which
When the inhibit block received the input signal, it
indicated that the current process was finished and the
reset the counter, activated the enable signal and started
timer was waiting for the next input. After receiving the
the count again. In Fig. 13, as the input was received, the
next input, the counter was started again and the process
count was reset and started counting again from the
was continued up to the count of 0.7.
begining. After the completion of the this process, the
enable signal was deactivated.
M. Alpha block
The input for this block is the output from the previous
block i.e., from the timer block. Here, the input is
processed by the function f(x)=x*e–x, where x is the input.
The input is multiplied with the corresponding weight and
the result is shown in the Fig. 11.
Fig 13. Output for inhibit designs or modules and each module is redefined with
greater details or divided in more sub-systems with the
H. The complete artificial neuron model intention to implement in FPGA hardware.
FPGAs have limited usable area and design tool chains,
The complete artificial neuron model was developed which create difficulty in implementation of large neural
and implemented in the Anvyl board and the simulation networks. Therefore, designs should be optimized in size
output of the neuron model is given in the Fig.14. Here, to implement in an FPGA with limited number of
two different inputs were given to the neuron from the resources [11].
two dendrites. But, the input with higher value was An FPGA design neuron model includes the pre- and
processed and its weight was added, whereas the lower post-synaptic connections and an integrator which
input was rejected. For digital neuron modeling the computes the spikes. Further, it models the activity level
weight was given as „1‟. Therefore, the inhibit value was of the neuron based on the firing rate that depends on the
the addition of input (in1) with the higher value, which integrated value. In the basic model, the integrated value
rejected the other neuron‟s input and its weight. For was updated for each incoming spike by an increment or a
example, If the weight of the input in1 is 0011 and the decrement operation on the membrane potential (MP),
weight of the input in2 is 0001 (i.e., the input in1 is which was modeled by a counter and depends on the
greater than in2), then the input in1 was processed and the polarity of the received spike. If the spike is positive, MP
weight 0011 was added, which was given as an inhibit is found to be incremented, whereas it is decremented
result. This condition was stored in the neuron and an when the spike is negative. Also, the present MP is found
output was sent out. This is represented by a high signal, to be translated into output stream of spikes continuously.
i.e. „1‟ in the output wave form. The neuron fires only In this work, the Anvyl FPGA development platform
when the addition of inputs exceeds the threshold level. If was employed, which is a complete, ready-to-use digital
the inputs of in1 = 0000, in2 = 0000 and in1 = 0001, in2 = circuit development platform based on a speed grade-3
0001, then these input combinations didn‟t cross the Xilinx SPARTAN-6 XC6SLX45 CSG484 package FPGA
threshold level and the inhibit value of these two inputs kit as shown in Fig. 15. The Anvyl is compatible with all
was found to be zero. For all the other inputs the Xilinx CAD tools, including ChipScope, EDK, and the
respective outputs are shown in the Fig. 14. free ISE WebPack™, so designs can be easily carried out
economically.
The proposed neuronal model was implemented in VHDL In the Anvyl board, the slide switches sw0 to sw3 are
(Very High Speed Integrated Circuit Hardware used as input 1 (in1). Slide switches sw4 to sw7 are used
Description Language) language. The model was as input 2 (in2). LEDs (LD0-LD3) are used for displaying
developed in the VHDL language using top-down the inhibit output. LED (LD14) is used to output the
approach, i.e., divide the complex design into simple threshold signal. LED (LD13) is used to display the
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