Defining Timing Constraints using SDC

Webinar Q&A Logs – Both Sessions – September 2019

Resources:

Tcl training from Doulos

A 2-day class teaching the essentials of the language and its application in the field of PLD and ASIC design. It is
packed full of examples and exercises all directly based on design related problems, and covers the need-to-know
essentials for design engineers and EDA support specialists.

https://www.doulos.com/content/training/tcl_essential.php

Q&A Log for Session 1 Q&A log for Session 2 »

Audience Question:
Q: Can't a delay be mentioned in Verilog format. Why does a new language need to be
learnt?
A: Delays in Verilog are ignored by synthesis. Once the circuit is laid out, the delays through
the various paths depend on the gate delays and the net delays. SDC doesn't specify the
ACTUAL delay it specifies the CONSTRAINTS on the delay - the set-up time (the max delay)
and the hold time (the min delay).

Audience Question:
Q: What is SDF full form?
A: Standard Delay Format, it is IEEE standard (1497-2001)

Audience Question:
Q: Is embedding SDC commands in the Verilog source (perhaps as comments) possible?
(the feature would be great for specifying some exceptions in IPs)
A: I've never heard of such a thing. If there were some EDA tools that allowed this, the
trouble is that you would have RTL that became tool-specific, which is not usually nice.

Audience Question:
Q: Do different tools have different Syntax for SDC or is it common across the spectrum?
A: SDC is based on TCL so the basic syntax is the same across tools. What is likely to differ
are the names of the commands and each vendor is free to give things different names.

Audience Question:
Q: How deep should I have to be involved in design to be responsible for this task (writing
the constraints)?
A: You should be writing constraints in SDC directly or some tool-specific version or via a
GUI for every design. At the very least, the synthesiser needs to know the clock period. A
simple design would only require simple constraints; a complex design would probably
require complex constraints. On a one-person FPGA design, the designer should be writing
simple constraints. On a complex IC project, there would be one or more people who are
responsible for writing constraints (and for other aspects of physical design such as
synthesis, timing-analysis and layout).

Page 1 of 17
Defining Timing Constraints using SDC
Webinar Q&A Logs – Both Sessions – September 2019

Audience Question:
Q: What are pins in SDC?
A: Pins are the internal connection points between internal blocks. Ports are the physical
connections to the outside world - this is unfortunately the opposite to what you might
expect

Audience Question:
Q: Does a cell only have input pins? There were no output pins for cells in your figure.
A: Any cell would also have output pins. That should have been shown, too.

Audience Question:
Q: I am interested in the 2-day Tcl course.
A: I've added a link to the Q&A (https://www.doulos.com/content/training/tcl_essential.php) - we
will also include it in the webinar follow-up messaging. By all means contact our team via
the webinar survey after the presentation to find out more. Thanks for your interest :)

Audience Question:
Q: Is Doulos planning to propose a "Comprehensive SDC/STA" training soon? (same content
as Comprehensive VHDL/SV, theory + Labs)
A: We currently offer an SDC/STA course as part of our Xilinx training offering. Please see
the website for more details.

Audience Question:
Q: What are collections?
A: They are a simply a group of nodes - perhaps all inputs or just a parallel data bus.

Audience Question:
Q: Why should we use collections? Are absolute objects bad?
A: For just one object, there is no problem using its name, but if you are trying to work with
a large group of objects, collections save you having to type the same information multiple
times.

Audience Question:
Q: If a design has multiple functional modes and design can transition from one mode to
another by writing some control registers, how can SDC be defined for each mode?
A: If a design has multiple functional modes, that would not necessarily affect the timing. If
it did, then it is possible to (eg) set points in the design to fixed logic values to force the
DUT into various modes. However, the beauty of Static Timing Analysis is that (unlike a
gate-level simulation) it checks every path in your design. Any special case that you need to
add lessens that advantage. (Though on a real design it is almost always necessary to
define special cases such as false paths etc).

Audience Question:
Q: At what stage do we decide the constraints of the design?
A: You should be thinking of your constraints at the same time as you are writing the VHDL
/ Verilog. Many of those constraints will be defined by outside influences - such as system
clock frequencies or external timing requirements.

Page 2 of 17
Defining Timing Constraints using SDC
Webinar Q&A Logs – Both Sessions – September 2019

Audience Question:
Q: If unconstrained paths are in the design what we should do?
A: You would need to find out why those paths are unconstrained. If they are genuinely
false (eg a clock-domain crossing from one clock to an asynchronous clock) then they
should be unconstrained. If not, then you would need to add a constraint to constrain them
or you would need to debug your existing constraints.

Audience Question:
Q: Since, a PLL is an analog IP, can we write a generated clock wrt the base clock? Is that
technically correct?
A: When using a PLL on an FPGA, the tools will automatically create constraints that relate
to the generated clocks to the input base clock.

Audience Question:
Q: Why is [get_registers clkdiv] at the end of the create_generated_clock command?
A: This defines the source of the generated clock. In the side it is defined as a flip-flop.
Another example: create_generated_clock -divide_by 2 -source [get_ports Clock1] -n
Clock3 [get_pins clock_div2/Clocko]

Audience Question:
Q: Can you give an example where the base clock would be different to the virtual clock?
A: The slide (7) gives one such example. The virtual clock is not perfectly synchronous to
the base clock because there are flip-flop delays. There could also be some other kind of
mixing of two clocks inside the block. We are just using this as an example.

Audience Question:
Q: Why we will not define virtual clock in SDC?
A: A virtual clock allows you to define the timing of points (eg outputs of the design) whose
timing is not defined with respect to any of the clocks internal to the DUT. An output (eg)
will be sampled by some other clock on some other component on the board. The idea of a
virtual clock is useful for specifying the timing in this kind of situation.

Audience Question:
Q: In what case do we set input/output delay from virtual clock?
A: If it's USEFUL for you to do so. If you can define the timing of an input or output with
respect to a real clock, then it would be more useful to do so.

Audience Question:
Q: When will we use virtual clocks but not the base clock?
A: You should have at least one clock in your design otherwise it will be asynchronous and
that is difficult to design in an FPGA.

Audience Question:
Q: How we can get to know clock port names?
A: You will know those names already as you assign them in the top-level VHDL / Verilog.
Otherwise you can use a TCL command to select them as a group.

Audience Question:
Q: On create_clock -period option, what if we had a sub-nanosecond clock period?
A: A decimal point is allowed, eg -period 0.9

Page 3 of 17
Defining Timing Constraints using SDC
Webinar Q&A Logs – Both Sessions – September 2019

Audience Question:
Q: Didn't manage to find the command "report_uncosntrainted_paths" in dc_shell. Is it a
purely primetime command?
A: It is certainly present in Xilinx tools, it may not be available in all other vendors.

Audience Question:
Q: What is the difference between logical, physical exclusive and asynchronous
A: You use -asynchronous when there are paths between two clock groups but the two
clocks are completely asynchronous (eg normal clock domain crossing).

You use -logically_exclusive when you have two completely separate clocks and there
are no paths between them at all. Why bother then? Because there may be other effects
between them (eg crosstalk).

You use -physically_exclusive when you have two clocks that are mutually exclusive, eg
two clocks that pass into a multiplexor so only one can be ever “active” at one time.

Audience Question:
Q: What's the use of defining a virtual clock in a design while it's not even being used in the
design?
A: If the signal is not being used, the synthesis tools might remove the clock completely. If
you require the signal at an output, it could still have timing requirements when it goes to
your external device - which is why you would need to constrain it.

Audience Question:
Q: When going from synthesis to place & routing, names of the clocks or nets often change
or are replaced. How do we ensure the correct SDC values are implemented in place &
routing?
A: I think this is tool-dependent (and is way beyond the scope of this webinar).

Audience Question:
Q: What is the maximum uncertainty value we can set?
A: This is tool-dependent (and I’m afraid is way beyond the scope of this webinar).

Audience Question:
Q: How do you know pin is connected to a particular clock?
A: You will have specified this elsewhere in your SDC file through a pin assignment
command.

Audience Question:
Q: In the set_multicycle_path, the delay is defined as 2 clock cycles, which clock is this
relative to? clk1 or clk2?
A: It relates to clk2.
(Note: clk1 was incorrectly stated in the live Q&A session – apologies!).

Page 4 of 17
Defining Timing Constraints using SDC
Webinar Q&A Logs – Both Sessions – September 2019

Audience Question:
Q: When I assign my pll clock into sdc file
(mango_demo_0|pll_0|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ) the tool
Quartus ignores it msg is invalid node. But when I do the timing analysis I am using the
same node for timing report how to fix in the constraints file.
A: To be honest, this sounds like a tool specific issue. Having said that, I have experienced
problems trying to use the same constraints for both synthesis and STA. Names get
changed by synthesis, nodes disappear and new ones are created. In my experience, I have
used different constraints for synthesis and STA.

Audience Question:
Q: What is the difference between base clock,design_clk,virtual clk??? Is there any
difference between driverclk and base clk.
A: A clock is a clock with a specific source, eg a clock input to the IC. A generated clock is a
DERIVED clock, eg the output of a clock divider. A virtual clock is a USEFUL construct to use
when specifying the timing of points that cannot be defined with respect to an ordinary
clock.

Audience Question:
Q: If we are getting unconstrained points at the output ports, what we should do?
A: Add constraints! The tools will tell you what is unconstrained and you should add extra
constraints as necessary.

Audience Question:
Q: As you mentioned, if we don’t mention any switch of setup or hold in multi_cycle_path is
it valid for just Setup or both setup & Hold?
A: If you don’t mention setup in the set_multicycle_path command (or even if you do) then
the hold check might be wrong. So, you probably want to follow your main
set_multicycle_path command with another which fixes the fact that the hold constraint is
wrong, eg :

set_multicycle_path 3 -from <somewhere> -to <somewhere else>

set_multicycle_path 2 <somewhere> -to <somewhere else> -hold

Audience Question:
Q: How do we decide the value of set_input_delay and set_output_delay?
A: This will come from what you need to have on your external connections. You will have
certain setup & hold requirements to other devices in your project and this will lead to the
input and output delays.

Audience Question:
Q: How do we know how much uncertainty there is in a clock?
A: That will be a product of the circuit generating the clock. eg a PLL will have a certain
jitter, which will dominate the clock uncertainty. The documentation of the clock generation
circuitry ought to specify this sort of thing.

Audience Question:
Q: What is the virtual clock and why do we need it?
A: A virtual clock is a USEFUL construct to use when specifying the timing of points that
cannot be defined with respect to an ordinary clock.

Page 5 of 17
Defining Timing Constraints using SDC
Webinar Q&A Logs – Both Sessions – September 2019

Audience Question:
Q: Can you tell us how much value we should consider for input and output delays?
A: That will depend entirely on what your external devices need so we cannot give you a
general figure.

Audience Question:
Q: If a design contains a CDC bridge, is that handled in a similar manner as the generated
clock example?
A: No. One way of handling CDC is to specify a false path from one domain to the other.
You then need some other way of checking the CDC, eg design review, simulation or a
dedicated CDC checking tool.

Q: Are there any dedicated CDC checking tools available in the market?
A: Yes. We don’t recommend specific tools here at Doulos, but a Google search for “clock
domain crossing analysis” will give you lots of information.

Audience Question:
Q: Is clock uncertainty propagated automatically from base clock to generated clock or do I
need to re-define it on the generated clock?
A: I think it should be but have struggled to build a testcase to prove it.

Audience Question:
Q: In your CDC example, you defined false path on clk1 and clk2. How can constraint the
delay between reg1 and reg2 when I'm using the false path. In case I want those two
registers to be close to each other.
A: You could perhaps use the set_max_delay command from the Q output of reg1 to the D
input of reg2?

Audience Question:
Q: Here regA and regB are triggered by which clock? clk2 or clk2 / 2 ?
A: clk2

Audience Question:
Q: The I/Os are usually much slower than the DUT clock, is this considered?
A: Yes. This is the purpose of the things like virtual clocks, multicycle paths and so on. In
my experience, constraining IO timing is not straightforward.

Audience Question:
Q: What's the use of defining a virtual clock in a design while it's not even being used in the
design?
A: A virtual clock is a USEFUL construct to use when specifying the timing of points that
cannot be defined with respect to an ordinary clock.

Audience Question:
Q: Should all IO ports in a design have input/output delays set? For example - an SPI
interface to an external ADC, using a generated clock from the FPGA... how would this be
constrained? (i.e. no common oscillator clock/virtual clock)
A: It is often a good idea - the external ADC will have its own setup & hold requirements
and constraints will ensure that you meet that timing.

Page 6 of 17
Defining Timing Constraints using SDC
Webinar Q&A Logs – Both Sessions – September 2019

Audience Question:
Q: Don’t we need to define a clock for multicycle?
A: The clock itself would have been defined somewhere else. You are just setting the
multicycle path here.

Audience Question:
Q: The main issue with SDC is that it is NOT a IEEE standard, like VHDL or SV. This means
each FPGA supplier can be partially compliant to it, he may add options to "standard"
command which are not supported => Could Doulos push in this direction, in order to
propose a dedicated training based on a IEEE standard for SDC ?
A: I don't know whether there is any industry initiative to standardise the setting of timing
constraints, so I am not sure who we might push. We do our best to write technology-
independent RTL, but physical design (synthesis, STA, layout) is always going to be much
more technology-dependent.

Q: The set_clock_group command have options -physical_exclusive, and when we use this
option, after synthesis, then report all clock groups, then the clock inside the
physical_exlcusive group will be show inside two groups, does that matter?
A: I set up some clocks and clock groups on a sample design:

create_clock -p 10 [get_ports Clock0]

create_clock -p 10 [get_ports Clock1]
create_clock -p 10 [get_ports Clock2]

set_clock_groups -async -group [get_clocks {Clock0 Clock1 Clock3}] -group [get_clocks Clock2]
set_clock_groups -physically_exclusive -group [get_clocks Clock0] -group [get_clocks Clock1]

And then did report_clocks -group and go (in Synopsys DC):

Clock Groups :

Total logically exclusive groups: 0

Total physically exclusive groups: 1

NAME : Clock0_2
False timing paths.
-groups { Clock0 }
-groups { Clock1 }

Total asynchronous groups: 1

NAME : Clock0_1
False timing paths.
-groups { Clock0 Clock1 Clock3 }
-groups { Clock2 }

Which is what I’d expect, I think. I’m not sure whether this answers your question, but it is
well beyond the scope of this webinar.

Audience Question:
Q: Why define an output delay using virtual clock if it is not really in use inside my
design?
A: A virtual clock is a USEFUL construct to use when specifying the timing of points that
cannot be defined with respect to an ordinary clock.

Page 7 of 17
Defining Timing Constraints using SDC
Webinar Q&A Logs – Both Sessions – September 2019

Audience Question:
Q: Is the clock dividing flipflop implicitly inferred by the tool?
A: No. You would write it in RTL. (Or perhaps instantiate some technology-specific IP).

Audience Question:
Q: Is there is any dependency of SDC on hold time violation. For example, if my design is
having hold time violation can we resolve the violation by changing my SDC?
A: You could change the SDC, but you would have set those values for a reason. It may be
possible that the device is not fast enough for your needs. It would not be a good design if
you change the SDC just to meet timing, when you have a particular need for those values.

Audience Question:
Q: How can we get to know multicycle paths?
A: You're the designer. You should know where the multicycle paths are. This is a
fundamental decision which ought to be taken early in the design.
Q: --> but how to get fast knowledge about the exceptions if you're not part of the design
team.
A: That would come from looking at the design source files. If you do not have access to the
VHDL or Verilog source (perhaps it is 3rd party IP), the constraints should be specified by
the original designer.

Audience Question:
Q: For a generated clock, is it always an output pin of a clock divider ?
A: No. the create_generated_clock command can be used for any derived clock or for
renaming other clocks.

Audience Question:
Q: Can you give me setup expression in terms of jitter, uncertainty, capture delay, launch
delay?
A: SLACK = PERIOD + CAPTURE_DELAY - TOTAL_UNCERTAINTY - (LAUNCH_DELAY +
C2Q_DELAY + Q2D_PROP_DELAY + SETUP_TIME)

Audience Question:
Q: When I use the command set_false_path -from [get_clocks A] -to [get_clocks B], is
there any way I can leave some specific paths out of this command? I mean, leaving some
specific paths that cross clock A to B without the set_false_path constraint being applied?
A: You would need to specify some kind of mask - using a TCL grep for example. Any
filtering commands in TCL would be available to you here.

Audience Question:
Q: Is there a way to get all the registers that do NOT meet certain condition? For example,
all registers NOT named regA?
A: In TCL you can do pattern matching using wildcards (* and ?) or with a full Regular
Expression so can select practically any group of nodes you like. The best tip is to not try to
make one complex expression to do everything: TCL allows you to nest commands so select
a group of nodes, then remove those that you don't want. For more information, please see
the regexp page on the TCL website.

Page 8 of 17
Defining Timing Constraints using SDC
Webinar Q&A Logs – Both Sessions – September 2019

Audience Question:
Q: If we don't know the external device contact, how we will mention input and output
delay?
A: In this case, you would be the person specifying the timing to the outside world. There
are no "generic" values you can use.

Audience Question:
Q: Difference between set_false_path and async_clocks during clock constraining?
A: I think async_clocks must be a deprecated, proprietary command.

Audience Question:
Q: How would setup and hold multicycle path define look like?
A: If you don’t mention setup in the set_multicycle_path command (or even if you do) then
the hold check might be wrong. So, you probably want to follow your main
set_multicycle_path command with another which fixes the fact that the hold constraint is
wrong, eg:

set_multicycle_path 3 -from <somewhere> -to <somewhere else>

set_multicycle_path 2 <somewhere> -to <somewhere else> -hold

Audience Question:
Q: The 2 in slide 10 relates to which clock? clk1 or clk2?
A: It relates to clk2. (Sorry, in haste I said clk1 originally)

Audience Question:
Q: Is it a good idea to tweak SDC to see better results in Place & Route tools?
A: The constraints should only be set for what you need. Certainly in Xilinx FPGAs, over
constraining the design will not help and could lead to long synthesis run times for no
benefit.

Audience Question:
Q: It is possible to define a multicycle exception using the sync enable signal as a source? I
mean, a type of exception "from all registers using sync enable to all registers using the
same sync enable". This way we don't need to select all specific from and to registers. Is
this possible at all?
A: Yes. SDC is based on TCL. TCL is good at that sort of thing. You'd have to write some
TCL to do the processing.

Audience Question:
Q: Is SDC included free with Vivado?
A: It is a Xilinx version which they call XDC, but it is very similar (and based on TCL). Many
commands are the same, but with a Xilinx flavour to them.

Audience Question:
Q: Are there any Tcl commands not supported by SDC?
A: That would depend on the tool manufacturer. It is usual for the complete TCL processor
to be present and everything to be built on top of that, but you should check the tool
documentation.

Page 9 of 17
Defining Timing Constraints using SDC
Webinar Q&A Logs – Both Sessions – September 2019

Audience Question:
Q: How to check max_delay in postlayout netlist, how to deal with clock latency impact for
max_delay?
A: Your STA ought to include the clock latency (by using the actual delays through the
actual clock distribution network), which in my experience can vary a lot between min and
max delay. I'm not sure what you are asking exactly?

Audience Question:
Q: How to check the clock domain crossing?
A: You would probably set a false path in SDC from the one domain to the other. Then you
would probably check the CDC some other way, eg design review, simulation or a dedicated
CDC checking tool.

Audience Question:
Q: Can you give command defining uncertainty for multicycle path with an example?
A: Uncertainty is a property of a clock. Uncertainty affects setup violations (basically, if the
capture clock is early with respect to the launch clock, then the clock period has been
reduced a little making a setup violation more likely). It does not matter whether the path is
multicycle or not.

Audience Question:
Q: How to get access to that Tcl webinar?
A: We'll provide you with a link to this webinar by email. We don't currently have a specific
Tcl webinar - but we will keep you posted about updates to our webinars and training. There
are also useful resources on the Doulos website: www.doulos.com/knowhow/tcltk/

Audience Question:
Q: We have one design in which we are generating clock from FPGA and delivering it to
external device. That external device is using that clock for driving its pins. And hence, we
are using clock generated using create_generated_clock command in set_input_Delay
command instead of virtual command. It seems right. Isn't it?
A: It may well be. It's difficult to say without seeing your design (and in the short time I
have to answer each question). A virtual clock can be USEFUL. If it's not useful or some
other way is more useful, then that's the way to go.

Audience Question:
Q: Is the increasing number of asynchronous design implementation cause increased
number of false path?
A: Fully asynchronous designs are very difficult to synthesize in FPGAs and require a lot of
constraints on combinatorial paths, rather than the clock-based ones we have examined in
this webinar.

Audience Question:
Q: Why the synthesis tools will be checking for hold at (n-1) edge of the setup?
A: Because setup times involve the delay from one clock edge to the next. Hold times
involve the same clock edge.

Page 10 of 17
Defining Timing Constraints using SDC
Webinar Q&A Logs – Both Sessions – September 2019

Audience Question:
Q: How do I tell the tool that some input port is asynchronous?
A: You would usually put a synchronizer flip-flop on the input and derive your timing from
there. It is not possible to define purely asynchronous inputs.

Audience Question:
Q: What about delays on PCB to external devices ? Should one take them into account?
A: In theory, yes, but that will only usually be an issue with very high-speed designs. You
can add the delays into your general setup / hold requirements for the I/O pin.
A: Yes, probably. You probably would define the timing at the DUT pins with respect to
some clock (real or virtual) and the loading of the PCB would be taken into account when
determining the IO driver timing. It would then be a system design issue to make sure that
the interface between the DUT and the other board-level component was OK.

Audience Question:
Q: On what basis you will specify min and max delay?
A: min_delay and max_delay are useful for a combinational path through your design. The
values of these delays depend on your board-level or system design. Combinational paths
are nasty - try to avoid them if you can.

Audience Question:
Q: In a PLL, the output clock(s) are related to the input reference clocks but not necessarily
synchronous, as there are various amounts of delay depending on the divider ratios. It has
also internal feedback path. Should I still define the output clocks as generated_clocks? And
what other constraints should be defined?
A: If you are using an FPGA, it is usual that the PLL block will come with its own (tool-
generated) constraints so you won't need to write them yourself.

Audience Question:
Q: For FPGA with IOB registers I always try to make use of these to fix the interface
timings. In this case is there ever any need to specify IO timing constraints?
A: An IOB register will help with IO timing, certainly. But the delay from the Q output of the
IOB register is not 0. There will be a delay driving the actual PCB track from the IO cell. You
might need to worry about that. (But that might be a board- or system-level issue).

Audience Question:
Q: If we don’t know external devices how will you specify min & max delay?
A: If you have no way of knowing what your device will be connected to, you become
responsible for specifying the setup & hold timing from your device for other people to
comply with.

Audience Question:
Q: Can you tell what is the use of divide by 1 clock?
A: It is useful in the case of a clock that is driven by some circuit that adds delay but
doesn't change the frequency or inverts the clock. It can also be used for renaming a clock.

Page 11 of 17
Defining Timing Constraints using SDC
Webinar Q&A Logs – Both Sessions – September 2019

Audience Question:
Q: I didn't get about false path and multicycle delay
A: A false path is a path whose timing you don’t care about. Examples: the path from an
asynchronous input or other clock domain to the first flip-flop in the synchroniser; a path
that is only used in test mode.
A multicycle path is a path whose delay is allowed to be more than one clock cycle, perhaps
because the flip-flops are clocked by a divided clock or because they are not enabled every
clock cycle.

Audience Question:
Q: Is constraining for timing same as assertions for functionality? and how do they embed
in the design and what is format of that file?
A: Functionality is simply making sure your design works correctly (assuming no timing
delays anywhere). In this webinar we have only been considering using external design
constraints files for meeting timing requirements - assertions for functionality are outside its
scope I'm afraid.

Session 2 Q&A log follows on the next page

Page 12 of 17
Defining Timing Constraints using SDC
Webinar Q&A Logs – Both Sessions – September 2019

Session 2 Q&A log Q&A log for Session 1 »

Audience Question:
Q: Do the other EDA vendors (e.g. Cadence) also use SDC commands?
A: Yes. Other vendors use SDC commands.
A: But they might change some of the command names - Xilinx use their own variant called
XDC for example which is very similar to SDC.

Audience Question:
Q: What is the difference between testing bench and SDC?
A: A test bench is for checking functionality, while SDC sets the actual timing requirements
of the design. Functional test assumes perfect logic cells with no delays.

Audience Question:
Q: is gate level simulation is equivalent to STA?
A: No, generally STA is better. Gate-level simulation can check timing but can only check
the actual paths exercised by the input stimulus. STA, however, checks all paths in a design
(both rising and falling / min and max delays / setup, hold, min pulse width, reset
recovery...). Gate-level simulation can aid STA, perhaps for checking external interface
timing or asynchronous structures.

Audience Question:
Q: Why doesn't SDC let different exceptions for I/O interface depending on the temperature
model. Such as for a particular temperature model the data delay is 1/4 clock period but for
a different temperature model the delay is 1 clock period. Hence the clock relationship
changes for each temperature model. So, for static analysis we would fail timing for some
temperature models while that just means the clock relationship differs between the
models. But there is no way to define exceptions that satisfy multiple clock relationships.
A: That sort of thing wasn't put into the SDC "language". What you might want to do in that
circumstance is create different constraints files for the extremes of temperature and check
each of them against your design.

Audience Question:
Q: If all the processes are synchronised by the clock, do we still need to check the
timing?
A: Yes - the constraints will check that the delays in combinatorial logic between the flip-
flops are not too long or too short (hold violations) and the constraints will also check other
timing issues such as minimum pulse widths or reset recovery.

Audience Question:
Q: But the tool uses SDC to satisfy a design qualifies timing, which file would the fitter
use
A: Both parts use the SDC file. It is needed for making sure that the logic between flip-flops
is not too large, but it is also needed at the place and route stage to ensure that physical
path delays do not compromise the timing.

Page 13 of 17
Defining Timing Constraints using SDC
Webinar Q&A Logs – Both Sessions – September 2019

Audience Question:
Q: Are the collection all_inputs and all_outputs related to top-level ports (and not internal
pin inputs/outputs)?
A: all_inputs and all_outputs relate to the top-level IO, not the internal pins.

Audience Question:
Q: Do you have any strategies for ensuring tools like Xilinx Vivado don't 'undo' any TCL
constructs in my .xdc file? I have found cases where Vivado has replaced my TCL variable
name for a particular internal clock (or whatever) with the actual clock name. So much for
readability!
A: Vivado has a habit of renaming signal names in a hierarchical fashion as you get deep
into the design. Often the easiest way is to use a wildcard "*name*" so that you don't have
to work out the internal signal.

Audience Question:
Q: Can you define a phase for base or virtual clocks?
A: Yes, you define a clock offset as well as its period.

Audience Question:
Q: How do you constrain output signal timing from a state machine design (running at 80
MHz) that is a SPI interface, and puts out a SPI_DATA signal and a "SPI_CLK" clock signal
(generated in state machine) that is 6 MHz. The device outside the FPGA has setup and
hold requirements dependent on the 6 MHz clock it receives from the FPGA.
A: You can use the set_output_delay command - it is covered later in the webinar

Audience Question:
Q: What happens if we don't have [get_registers clkdiv] for generated clock? Is it illegal?
A: It would not be legal unless you name the clock(s) explicitly.

Audience Question:
Q: What does the "-p" option specify for create_clock?
A: Clock period (ns).

Audience Question:
Q: How do you constrain output signal timing from a state machine design (running at 80
MHz) that is a SPI interface, and puts out a SPI_DATA signal and a "SPI_CLK" clock signal
(generated in state machine) that is 6 MHz. The device outside the FPGA has setup and
hold requirements dependent on the 6 MHz clock it receives from the FPGA.
A: What you're really concerned about is that the difference in delay between SPI_DATA and
SPI_CLK isn't too great, rather than the absolute delay. This is often the case with IO
timing. You could define a SPI_CLK as a clock and then define the timing of SPI_DATA
relative to that or you could report the delays manually and do some calculation in TCL.

Audience Question:
Q: How do you constrain output signal timing from a state machine design (running at 80
MHz) that is a SPI interface, and puts out a SPI_DATA signal and a "SPI_CLK" clock signal
(generated in state machine) that is 6 MHz. The device outside the FPGA has setup and
hold requirements dependent on the 6 MHz clock it receives from the FPGA.
A: I mean using the 6MHz clock.

Page 14 of 17
Defining Timing Constraints using SDC
Webinar Q&A Logs – Both Sessions – September 2019

Audience Question:
Q: Is the input/output delay defined with respect to rising or falling edge of the respective
clock(s)?
A: Either - you can specify the edge in the TCL command.

Audience Question:
Q: What is the timing constraint between reg2 and regA?
A: It's just a regular path - nothing special.

Audience Question:
Q: If nothing is defined, does it mean rising edge by default? (for input or output delay)
A: Yes, rising edge is the default.

Audience Question:
Q: The path between reg2 and regA is dealing the metastability resolving, right? any
constraint to make sure it has enough time to resolve the metastability?
A: You can never fully mitigate for metastability. The more flip-flops you have, the less
chance there is of a metastable state passing into the design.

Audience Question:
Q: Greetings! -- You explained the use of set_clock_uncertainty for specifying jitter. Why
not use the set_clock_jitter SDC command to specify jitter? -- Thanks
A: set_clock_uncertainty can be used to add addition uncertainty if you have also specified
jitter separately. Or, as in the example on the slide, you can specify all sources of
uncertainty using set_clock_uncertainty.

Audience Question:
Q: Is it same for the situation where the clock crossing happens at the border of a hierarchy
design?
A: Yes, the tool will analyse the design in the same way.

Audience Question:
Q: How is the timing for virtual clock calculated for output delay paths? Is it always ideal
clock or is it possible to have propagated clock?
A: A virtual clock can only be an ideal clock.

Audience Question:
Q: Are the clocks used for reg2out path differently calculated between ICC2 and PT?
A: That is a vendor specific question for Synopsys and is beyond the scope of this webinar.
(I have used PT, but not ICC2).

Audience Question:
Q: We would still need set_multicycle_path command for the hold case right?
A: Both cases are covered in a similar way - a setup delay is effectively a negative time
before a clock edge, while the hold is the time after the event.

Audience Question:
Q: Or group should be a clock?
A: set_clock_groups should only apply to clock signals.

Page 15 of 17
Defining Timing Constraints using SDC
Webinar Q&A Logs – Both Sessions – September 2019

Audience Question:
Q: What is the role of "clock" divider and the arrowed signals going to the regA and regB
flops? The whole figure is confusing.
A: The arrowed signals from regA to regB show a path going through a block of
combinational logic that could have a delay of more than one clock period through it. But,
because both regA and regB are clocked at half the speed of clk2, the design should still
work OK. However, we have to tell the timing analysis that this is the case and we do that
using the set_multicycle_path command.

Audience Question:
Q: check_timing command reports about all constrained paths in design. does check_timing
command checks and reports everything or it doesn't cover certain paths?
A: It covers all constrained paths. It cannot report timing on unconstrained paths.

Audience Question:
Q: Earlier in the presentation, you showed a report_unconstrained_paths command. Is it
SDC? If not where is it coming from?
A: It is a Tcl command. It is available in Xilinx Vivado, but may also be in other tool chains.

Audience Question:
Q: What exactly should be checked in hold check of a mcp?
A: I'm sorry - I don't understand your question. The hold check on an MCP is the same as
any other (physically) - we are checking that the path is not too short (relative to any clock
skew). However, as Johannes said, you need to take care with holds when using the
set_multicycle_path command. (Basically, you have to specify the hold manually in a
separate set_multicycle_path command using the -hold option.)

Audience Question:
Q: Hi, is there a book, manual or reference on all the SDC commands?
A: The documentation for your particular toolchain should have an SDC reference. For Xilinx
it will be called XDC, but would still be similar. For the basic command structure, any TCL
book will give you the background you need (or come on a Doulos training course!)

Audience Question:
Q: In a single clock system, is a clock definition command sufficient to constrain the timing
for the whole system?
A: It will define all the clock dependencies, yes. You may need to also add constraints for
the input and output delays on the datapath.

Audience Question:
Q: Is "-datapath only" for path delay a part of SDC?
A: -datapath_only is proprietary.

Audience Question:
Q: On slide-8, set_clock_uncertainty says jitter is 0.5ns. Is this RMS-jitter?
A: No, the maximum extent (peak) jitter.

Page 16 of 17
Defining Timing Constraints using SDC
Webinar Q&A Logs – Both Sessions – September 2019

Audience Question:
Q: On slide-8, set_clock_uncertainty says jitter is 0.5ns. Is this RMS-jitter?
A: No - it's the maximum jitter. (Which is, I guess, a fantasy, but STA doesn't do the kind of
statistical calculation that would be required were it RMS.)

Audience Question:
Q: Perhaps confirm that jitter number is peak-to-peak, rather than peak?
A: It's peak to peak. If you think about it the worst case is (for setup) that the launch clock
is as late as it ever could be and the capture clock is as early as it ever could be.

Audience Question:
Q: Perhaps confirm that jitter number is peak-to-peak, rather than peak?
A: Effectively the maximum deviation it could be. So for +5ns, -2ns you would specify a
jitter of 5ns.

Audience Question:
Q: On the generated clock is defined at the top-level file, do you need to define it again
within every VHDL instance that uses the clock?
A: Within your project, the properties of the constraint propagate all the way through - so if
it is set once it should be fine right to the output.

Audience Question:
Q: I wonder if it is the SDC you are talking about, I did set the base clock, but I did not set
other clock or set_false_path.
A: You won't see clocks and false paths in SDF.

Audience Question:
Q: Yes, I only see rising and falling time
A: In the SDF? I'd expect to see delays (min/max / rising/falling).

Page 17 of 17