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FPGA implementations of HEVC Inverse DCT using high-level synthesis

Conference Paper · September 2015

DOI: 10.1109/DASIP.2015.7367262

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 FPGA Implementations of HEVC Inverse DCT
Using High-Level Synthesis
Ercan Kalali, Ilker Hamzaoglu
Faculty of Engineering and Natural Sciences, Sabanci University
34956 Tuzla, Istanbul, Turkey
{ercankalali, hamzaoglu}@sabanciuniv.edu
Abstract— High Efficiency Video Coding (HEVC), the
recently developed international video compression standard, has
50% better video compression efficiency than H.264 video
compression standard at the expense of significantly increased
computational complexity. HEVC Inverse Discrete Cosine
Transform (IDCT) algorithm accounts for 11% of the
computational complexity of an HEVC video encoder. Recently,
commercial and academic high-level synthesis (HLS) tools are
started to be successfully used for FPGA implementations of
digital signal processing algorithms. Therefore, in this paper, the
first FPGA implementations of HEVC 2D IDCT algorithm using
HLS tools in the literature are proposed. The proposed HEVC
IDCT hardware are implemented on Xilinx FPGAs using three
HLS tools; Xilinx Vivado HLS, LegUp, MATLAB Simulink HDL
Coder. Using HLS tools significantly reduced the FPGA
development time, and the resulting FPGA implementations
achieved real-time performance. Therefore, HLS tools can be
used for FPGA implementation of HEVC video encoder.
Keywords—HEVC, IDCT, FPGA Implementation, HLS.
I. INTRODUCTION
ITU and ISO joint collaborative team on video coding
(JCT-VC) recently developed a new international video
compression standard called High Efficiency Video Coding
(HEVC) [1]-[2]. HEVC has 50% better video compression
efficiency than H.264 video compression standard.
HEVC standard uses Discrete Cosine Transform (DCT) and
Inverse Discrete Cosine Transform (IDCT) same as H.264
standard. However, H.264 standard uses only 4x4 and 8x8
Transform Unit (TU) sizes for DCT/IDCT. HEVC standard
uses 4x4, 8x8, 16x16, and 32x32 TU sizes for DCT/IDCT.
Larger TU sizes achieve better energy compaction. However,
they increase the computational complexity exponentially.
DCT and IDCT are heavily used in an HEVC encoder [3]-
[5]. IDCT has high computational complexity. It accounts for
11% of the computational complexity of an HEVC video
encoder. DCT and IDCT account for 25% of the
computational complexity of an all intra HEVC video
encoder.
Recently, commercial and academic high-level synthesis
(HLS) tools are started to be successfully used for FPGA
implementations of digital signal processing algorithms. The
high level synthesis tools accept their inputs in different
formats [6]. For example, Xilinx Vivado HLS and LegUp
tools take C or C++ codes as input, and generate Verilog or
VHDL codes. MATLAB Simulink HDL Coder takes
MATLAB Simulink models as input, and generates Verilog or
VHDL codes.
Since HEVC 2D IDCT performs matrix multiplication
operations, it is suitable for HLS implementation. Therefore,
in this paper, the first FPGA implementations of HEVC 2D
IDCT algorithm using HLS tools in the literature are
proposed. The proposed HEVC 2D IDCT hardware are
implemented on Xilinx FPGAs using three HLS tools; Xilinx
Vivado HLS, LegUp, MATLAB Simulink HDL Coder.
The inputs given to these HLS tools, C codes for Xilinx
Vivado HLS and LegUp and MATLAB Simulink model for
MATLAB Simulink HDL Coder, are developed based on the
HEVC 2D IDCT software implementation in the HEVC
reference software encoder (HM) version 15 [7]. Two HEVC
2D IDCT HLS implementations are done. In one of them, in
the C codes and MATLAB Simulink model multiplications
with constants are implemented using multiplication
operation. In the other one, they are implemented using
addition and shift operations.
Some of the optimization options of these HLS tools are
used in order to increase performances of the FPGA
implementations such as pipelining and loop unrolling.
Verilog RTL codes generated by these three HLS tools for the
two HEVC 2D IDCT HLS implementations are verified to
work in a Xilinx Virtex 6 FPGA.
Using HLS tools significantly reduced the FPGA
development time. The implementation results show that the
proposed HEVC 2D IDCT FPGA implementations using HLS
achieved real-time performance with acceptable hardware
area. Therefore, HLS tools can be used for FPGA
implementation of HEVC video encoder.
A few HLS implementations for H.264 video compression
standard are proposed in the literature [8]-[11]. There are a
few HLS implementations based on MPEG reconfigurable
video coding [12]-[13]. There are several HLS
implementations for image and video processing algorithms
such as sorting in the median filter [14]-[17]. Several
handwritten Verilog RTL implementations for HEVC video
compression standard are also proposed in the literature [18]-
[23].

Fig. 1. HLS Implementation of HEVC 2D IDCT
The HEVC 2D IDCT HLS implementation proposed in this
paper is the first HLS implementation for HEVC video
compression standard. It is also the first HLS implementation
for the transform operations in video compression standards.
In addition, HEVC IDCT algorithm is one of the most
computationally complex algorithms compared to other HLS
implementations for both image processing and video
compression.
The rest of the paper is organized as follows. HEVC 2D
IDCT algorithm is explained in Section II. In Section III, the
proposed HLS implementations are explained, and the
implementation results are given. Finally, Section IV presents
the conclusions.
II. HEVC 2D IDCT ALGORITHM
HEVC standard uses Inverse Discrete Cosine Transform
(IDCT) same as H.264 standard. However, H.264 standard
uses only 4x4 and 8x8 Transform Unit (TU) sizes for
DCT/IDCT. HEVC standard uses 4x4, 8x8, 16x16, and 32x32
TU sizes for DCT/IDCT.
HEVC standard performs 2D transform by first performing
1D column transform and then performing 1D row transform.
The coefficients in the DCT/IDCT matrices are derived from
the DCT basis functions. However, integer DCT coefficients
are used for simplicity.
First, an integer IDCT matrix for 32x32 TU size is
generated. The other TU sizes (4x4, 8x8, 16x16) use the sub-
sampled versions of the 32x32 TU size. An IDCT matrix for
4x4 TU size is shown in (1).
Because of the multiplications with large coefficients,
truncation and clipping operations are added to HEVC IDCT
after the horizontal 1D transform and the vertical 1D
transform. The truncation operations are shown in (2) and (3).
͸Ͷ ͸Ͷ ͸Ͷ ͸Ͷ
ͺ͵ ͵͸ െ͵͸ െͺ͵
‫ܶܥܦܫ‬ସ௫ସ ൌ൦ ൪ (1)
͸Ͷ െ͸Ͷ െ͸Ͷ ͸Ͷ
͵͸ െͺ͵ ͺ͵ െ͵͸
ܶ‫݊݋݅ݐܽܿ݊ݑݎ‬ଵ஽ ൌ ሺ‫ܶܥܦܫ‬ሺ‫ݔ‬ǡ ‫ݕ‬ሻ ൅ ͸Ͷሻ ‫ ب‬͹(2)
ܶ‫݊݋݅ݐܽܿ݊ݑݎ‬ଶ஽ ൌ ሺ‫ܶܥܦܫ‬ሺ‫ݔ‬ǡ ‫ݕ‬ሻ ൅ ʹͲͶͺሻ ‫(ʹͳ ب‬3)
III. HEVC 2D IDCT HLS IMPLEMENTATIONS
The proposed HLS implementation of HEVC 2D IDCT for
all TU sizes is shown in Fig. 1. IDCT inputs are selected
depending on size of the IDCT operation (4x4, 8x8, 16x16 or
32x32). First, 1D column IDCT is performed, and the resulting
coefficients are clipped. Then, 1D row IDCT is performed
using the transpose of the resulting matrix as input, and the
resulting coefficients are clipped.
Two HEVC 2D IDCT HLS implementations are done.
These HLS implementations are synthesized to Verilog RTL
using three different HLS tools. The inputs given to these HLS
tools, C codes for Xilinx Vivado HLS and LegUp and
MATLAB Simulink model for MATLAB Simulink HDL
Coder, are developed based on the HEVC 2D IDCT software
implementation in the HEVC reference software encoder (HM)
version 15 [7]. In one HLS implementation, in the C codes and
MATLAB Simulink model multiplications with constants are
implemented using multiplication operation. In the other one,
they are implemented using addition and shift operations.
Verilog RTL codes generated by these three HLS tools for
the two HEVC 2D IDCT HLS implementations are verified
with RTL simulations. RTL simulation results matched the
results of HEVC 2D IDCT implementation in HEVC reference
software encoder (HM) version 15 [7]. The Verilog RTL codes
are synthesized and mapped to a Xilinx XC6VLX550T FF1760
FPGA with speed grade 2 using Xilinx ISE 13.4. The FPGA
implementations are verified with post place and route
simulations.
A. Xilinx Vivado HLS
Xilinx Vivado HLS tool can generate Verilog RTL codes
from C/C++ and System C codes. It can optimize the area,
speed and power consumption of the hardware implementation.
It provides bit-accurate and cycle-accurate implementations. It
has several optimization options such as pipelining, loop
unrolling, and loop merging. It allows adding specific RAM
blocks, FIFOs, or ROMs to HLS implementation with
directives. It also allows adding specific DSP blocks such as
multiplier, divider or square unit. In addition, it has an option
to select I/O ports as bus, memory, FIFO or acknowledge type.
It also allows adding high speed AXI-4 busses for data transfer.
 void COL_partialButterflyInverse8( (multiplications with constants are implemented using
int15 resid[DCT_8], int7 coeff[31], int7 coef8[16], multiplication operation) and AS (multiplications with
int16 *Y1, int16 *Y2, int16 *Y3, int16 *Y4,
int16 *Y5, int16 *Y6, int16 *Y7, int16 *Y8)
constants are implemented using addition and shift operations),
{ for each TU size and for all TU sizes are given in Table II.
char j,l,k = 0;
int26 E[4], O[4], EE[2], EO[2]; C. MATLAB Simulink HDL Coder

for(l=0; l<4; l++) #pragma HLS unroll factor=2

MATLAB Simulink is a widely used modeling tool for
{O[l] = coef8[l*4]*resid[1] + coef8[l*4+1]*resid[3] + many applications such as signal processing and
coef8[l*4+2]*resid[5] + coef8[l*4+3]*resid[7]; communication. MATLAB Simulink HDL Coder tool can
}; generate Verilog RTL codes from MATLAB Simulink models.
It has several optimization options such as pipelining, clock
EO[0] = coeff[1]*resid[2] + coeff[2]*resid[6];
EO[1] = coeff[2]*resid[2] - coeff[1]*resid[6]; gating, resource sharing, RAM mapping, and delay balancing.
EE[0] = coeff[0]*resid[0] + coeff[0]*resid[4];
EE[1] = coeff[0]*resid[0] - coeff[0]*resid[4]; TABLE I. XILINX VIVADO HLS IMPLEMENTATION RESULTS

#pragma HLS pipeline Freq. Full

TU Imp. LUTs DFFs Slices BRAMs I/O
E[0] = EE[0] + EO[0]; (MHz) HD fps
E[1] = EE[0] - EO[0];
E[2] = EE[1] + EO[1]; M 1081 560 356 1 134 222 142
4x4
E[3] = EE[1] - EO[1]; AS 663 373 212 1 134 294 189
M 3486 2515 1193 3 262 222 72
*Y1 = Clip3(-32768, 32767, (E[0] + O[0] + 64) >> 7); 8x8
AS 2834 2010 919 1 262 313 101
*Y2 = Clip3(-32768, 32767, (E[1] + O[1] + 64) >> 7); M 7159 5495 2554 13 518 208 80
*Y3 = Clip3(-32768, 32767, (E[2] - O[2] + 64) >> 7); 16x16
AS 5000 4090 1602 1 518 333 128
*Y4 = Clip3(-32768, 32767, (E[3] - O[3] + 64) >> 7);
*Y5 = Clip3(-32768, 32767, (E[3] + O[3] + 64) >> 7); M 13046 10366 4556 25 1030 208 54
32x32
*Y6 = Clip3(-32768, 32767, (E[2] + O[2] + 64) >> 7); AS 40764 28772 12605 13 1030 208 54
*Y7 = Clip3(-32768, 32767, (E[1] - O[1] + 64) >> 7); M 24542 18416 8193 39 1045 200 52
*Y8 = Clip3(-32768, 32767, (E[0] - O[0] + 64) >> 7); All
AS 50566 34955 14944 13 1045 208 54
}
Fig. 2. Xilinx Vivado C Code TABLE II. LEGUP IMPLEMENTATION RESULTS

A part of the C codes developed and given as input to Freq. Full

Xilinx Vivado HLS tool is shown in Fig. 2. Since HEVC 2D TU Imp. LUTs DFFs Slices BRAMs I/O
(MHz) HD fps
IDCT performs matrix multiplication operations, many for M 4546 1232 1484 2 781 149 36
loops are used in the C codes. Therefore, loop unrolling 4x4
AS 1431 623 554 1 781 162 39
directive is used in the C codes to increase performance. M 8669 2701 2772 7 781 147 35
Pipelining directive is also used in the C codes to increase 8x8
AS 4804 2474 1613 1 781 213 51
performance. M 14557 4896 4829 27 781 130 31
16x16
AS 17199 8876 5582 21 781 150 36
The FPGA implementation results for the Verilog RTL
M 26854 9420 8654 27 781 128 31
codes generated by Xilinx Vivado HLS tool for the two C 32x32
AS 51254 26427 15580 21 781 147 35
codes, M (multiplications with constants are implemented
using multiplication operation) and AS (multiplications with M 53605 17714 16950 56 829 130 31
All
AS 74072 38369 23481 41 781 143 35
constants are implemented using addition and shift operations),
for each TU size and for all TU sizes are given in Table I.
TABLE III. MATLAB SIMULINK HDL CODER IMPLEMENTATION
B. LegUp RESULTS

LegUp is an open-source HLS tool. It can generate Verilog Freq. Full

TU Imp. LUTs DFFs Slices BRAMs I/O
RTL codes from C codes. It provides few optimization options (MHz) HD fps
such as pipelining and loop unrolling. However, data M 661 160 200 0 130 149 96
dependencies because of loop unrolling cannot be detected by 4x4
AS 377 134 133 0 116 166 107
LegUp. It does not provide bit-accurate implementations. This M 2620 262 750 0 258 110 61
8x8
increases area and decreases performance of FPGA AS 1167 174 375 0 242 136 75
implementation. It generates RTL codes especially for Altera M 9649 484 2671 0 514 104 54
16x16
FPGA synthesis tools. However, the generated RTL codes can AS 3924 362 1210 0 488 120 62
also be synthesized using Xilinx ISE tool with some M 34499 1005 9684 0 1026 100 50
32x32
modifications. AS 12861 668 3878 0 983 110 55
M 46471 1393 13727 0 1032 100 50
The FPGA implementation results for the Verilog RTL All
13669 1140 3932 0 1000 110 55
AS
codes generated by LegUp HLS tool for the two C codes, M
It has many available models and it allows adding handwritten
MATLAB codes. These speed up the design process. However,
implementing large designs is the main drawback of Simulink.
Because large designs require complex graphical models, and
this slows down the design process.
A part of the MATLAB Simulink model developed and
given as input to MATLAB Simulink HDL Coder tool is
shown in Fig. 3. Pipelining and clock gating optimizations are
used in the model. The FPGA implementation results for the
Verilog RTL codes generated by MATLAB Simulink HDL
Coder tool for the two MATLAB Simulink models, M
(multiplications with constants are implemented using
multiplication operation) and AS (multiplications with
constants are implemented using addition and shift operations),
for each TU size and for all TU sizes are given in Table III.
D. Hardware Comparison
The implementation results of the three HLS tools (Xilinx
Vivado HLS, LegUp, MATLAB Simulink HDL Coder) are
compared with the implementation result of the handwritten
Verilog RTL implementation of the HEVC 2D IDCT
hardware in [23] except the proposed energy reduction
technique. The handwritten Verilog RTL codes are also
synthesized and mapped to a Xilinx XC6VLX550T FF1760
FPGA with speed grade 2 using Xilinx ISE 13.4. The
comparison results are given in Table IV.
Fig. 3. MATLAB Simulink Model
The HEVC 2D IDCT hardware in [23] is shown in Fig. 4.
In this hardware, IDCT inputs are selected depending on size
of the IDCT operation (4x4, 8x8, 16x16 or 32x32). The
hardware uses an efficient butterfly structure for column and
row transforms. After 1D column IDCT, the resulting
coefficients are stored in a transpose memory, and they are
used as input for 1D row IDCT. The multiplication operations
are performed in the datapaths using only adders and shifters.
In order to reduce number and size of the adders in the
hardware, Hcub MCM algorithm [24] is used for calculating
4, 8, 16 and 32 point IDCT. Hcub algorithm determines
necessary shift and addition operations in a multiplier block.
There are 4 multiplier blocks in 8x8 datapath, 8 multiplier
blocks in 16x16 datapath and 16 multiplier blocks in 32x32
datapath.
These results show that the proposed HEVC 2D IDCT
FPGA implementations using HLS achieved real-time
performance with acceptable hardware area. In addition, HLS
implementations have comparable area and clock frequency
results with handwritten Verilog RTL implementation.
However, handwritten Verilog RTL implementation processes
more frames per second (fps) than the HLS implementations.
This is because the handwritten Verilog RTL implementation
includes several optimizations such as a complex pipeline and
resource sharing between different TU sizes. In addition, HLS
implementations spend some redundant clock cycles
especially for hand-shaking protocols.
Fig. 4. HEVC 2D IDCT Hardware [23]

TABLE IV. HARDWARE COMPARISON

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