Design and Verification of 32-bit pipelined RISC-V

Instruction Set Architecture

Athira V R
Electronics and Communication
Department
Anna University Regional Campus
Madurai
nairaathira843@gmail.com

Abstract— RISC-V is an open source instruction set stages namely – Instruction Fetching, Instruction Decoding,
architecture (ISA) based on the principles of Reduced Executing, Memory Access, Writing Back. Each stage is
Instruction Set Computation (RISC).In this paper; a 32-bit designed in such a way that a new instruction should start at
pipelined RISC-V Instruction set architecture has been every cock cycle and each stage must finish its execution
designed. The design is implemented in such a way that at within one clock cycle. Finally, a reusable verification
every clock cycle a new instruction is started and each stage platform is built using System Verilog to perform functional
finishes its execution within one clock cycle. The hazards in verification and to collect coverage.
pipeline like structural, data and control hazards are removed.
Furthermore, the Universal Verification Methodology (UVM)
is used to build the verification platform to verify the RTL II. RISC-V ISA DESIGN
code, then by using functional coverage it is verified that all the
DUT features have been verified and have measured the A. Instruction formats
quality of verification. The synthesized RTL code is reliable The RISC V instruction are classified into seven formats.
and fully verified. They are
Keywords—RISC-V, Verilog, System Verilog, UVM, U-type : It is used for instructions that use a 20-bit
Functional Coverage, EDA tools. immediate operand and an rd destination register.
J-type : The J-type instruction format is used to encode
I. INTRODUCTION the jal instruction with an immediate value that determines
Up till 1980s most realization of ISA i.e., CPU got more the jump target address. It is similar to the U-type, but the
and more complicated because of using CISC (Complex bits in the immediate operand are arranged in a different
Instruction Set Computing). As CISC instructions took order.
several clock cycle to execute a single instruction,
R-type : The R-type instructions are used for operations
implementation of pipeling is complex, this results in slower that set a destination register rd to the result of an arithmetic,
speed and slow memory access. In early 1980s the IBM logical or shift operation applied to source registers rs1 and
researcher John Cocke and his team created the first rs2.
prototype computer employing a reduced instruction set
computer (RISC) architecture. Then Prof. Krste Asanović I type : The I-type instruction format is used to encode
and graduate students Yunsup Lee and Andrew Waterman instructions with a signed 12-bit immediate operand with a
started the RISC-V instruction set in May 2010 as part of the range of [−2048..2047], an rd register, and an rs1 register.
Parallel Computing Laboratory (Par Lab) at UC Berkeley, of
which Prof. David Patterson was Director[2]. RISC-V is a S-type : The S-type instruction format is used to encode
new instruction set architecture (ISA) designed to support instructions with a signed 12-bit immediate operand with a
computer architecture research and education[1].The main range of [−2048..2047], an rs1 register, and an rs2 register.
idea of RISC V is on each clock cycle an instruction gets B-type : The B-type instruction format is used for branch
executed and the memory is fixed size which allows to instructions that require an even immediate value that is used
decode the instruction easy. The RISC V is defined as a set to determine the branch target address as an offset from the
of modules – BASE and EXTENSION module. This allows current instruction’s address.
any implanter to select which features to incorporate into a
CPU design. For any RISC V implementation, one of BASE
module and zero or more of EXTENSION module is
provided. RV32I refers to the 32-bit base integer instruction Funct3 Instruction Opcode
set. Standard RISC-V extensions are defined as M for 000 beq 1100011
multiplication and division, F for floating-point instructions, 001 bne 1100011
D for double-point precision instructions, and A for atomic
instructions. In addition, RV32G is a general-purpose 32-bit 100 blt 1100011
instruction set that includes all instructions from the M, F, D, 101 Bge 1100011
and A extensions. There also exist the 64-bit and 128-bit 110 Bltu 1100011
variants of these instruction sets. This paper is focused on
111 Bgeu 1100011
RV32I base module.
000 lb 0000011
In this paper, the 32-bit RISC V ISA processor is
designed with Verilog Language, mainly in five pipelined 010 lw 0000011
 000 sb 0100011 Clock 1 2 3 4 5 6
010 sw 0100011 Iteration
000 addi 0010011 i IF ID EXE MEM WB
100 xori 0010011 i+1 IF ID EXE MEMWB
110 ori 0010011 i+2 IF ID EXE MEM
111 andi 0010011 i+3 IF ID EXE
000 add 0110011 Fig. 2 Five stage pipelined cycle.

000 sub 0110011 IF Instruction Fetch

001 sll 0110011 ID Instruction Decode
010 slt 0110011 EXE Execute
100 xor 0110011 MEM Memory
110 or 0110011 WB Write Back
111 and 0110011 Fig. 3 Stages of pipeline.

Fig. 1 .Instruction formats with funct3 and opcode. C. Hazards

B. Pipeline stage
The pipelined implementation of RISC V is divided into
5 sub cycle/steps :- Instruction Fetch(IF), Instruction
Decode(ID), Execution(EXE), Memory Access(MEM),
Write Back(WB). These steps are explained as follows:
Instruction Fetch (IF) : During this stage, an instruction
is fetched from the memory. The program counter or PC
register holds the address of the instruction that is to be
fetched from the instruction memory. After the instruction is
fetched, the PC increments the value of PC to PC + 4 .But
for Branch/Jump instruction the new value of PC will be the
target address. So PC is not updated in this stage for
Branch/Jump instruction, new value is stored in NPC.
Instruction Decode (ID) : In this stage, two functions
are performed. The instruction fetched from the instruction
memory is decoded by using opcode. The indexes is given to
the register memory as address and the register is fetched.
Both the instruction decoding and register prefetching is
done parallely. Similarly, the immediate data is sign
extended. Simultaneously, for Branch/Jump instruction the
target address is calculated during register fetching.
Execute (EXE): The computation process occurs during
this stage. This stage consists of two 2*1 MUX, an ALU and
a comparator. For Branch/Jump instruction, the MUX_1
produces NPC as output and feds to the ALU, otherwise it
gives, register A as output and feds to the ALU. For
immediate instruction, the MUX_2 selects imm (immediate
value) as the output and feds to the ALU, Otherwise it
produces register B as output. The MUX output is fed to the
ALU, the ALU computes and produces ALUOut.
Memory Access (MEM): If any data memory is needed
to access, then it is done in this stage. The LOAD, STORE
and Branch instruction use this stage. The Branch updates
the PC depending on the outcome of branch condition.
Write Back (WB): During this stage, the result is written
back to the register file. The result may either come from the
ALU or the memory system (via. a LOAD).
In the pipeline, some situations that prevent the next
instruction -in the instruction stream- from executing during
its designated clock cycles. This is known as a hazard [5].
The hazards are classified into three categories.
Structural Hazard: If two instructions already in
pipeline are at two different stages, but they are trying to use
same hardware resource. If there is single copy of hardware
resource, they cannot access simultaneously, one has to wait.
In this paper, two memories are used – Instruction memory
and Data memory.
Data Hazard: This hazard occurs due to instruction
dependency. Data hazards can be removed either by
forwarding data and/or by inserting stall cycle.
Control Hazard: Control hazard arise due to branch
instruction. The branch is taken at Execute (EXE) stage, so
already entered instruction at Instruction Fetch (IF),
Instruction Decode (ID) are discarded. In this paper,
TAKEN_BRANCH register is set after the decision to take a
branch is known. It is required to disable instructions that
have already entered the pipeline from making any state
change.
III. VERIFICATION PLATFORM
In this paper, UVM methodology is used to verify the
synthesized RTL code. The test stimulus is generated by the
uvm_seq_item (transaction class). The uvm_sequencer
executes the uvm_seq_item and does the arbitrating process
between them and routing sequence items between the driver
and sequence. The uvm_driver is responsible for converting
the the uvm_seq_item into “pin wiggles” on the signal-level
interface to send and receive data to/from the DUT.The pin-
level behaviour on the DUT interface is monitored by
uvm_monitor.It also converts the signal into sequence items
and providing those sequence item to analysis component in
the agent, scoreboard and functional coverage. The analysis
component from the uvm_monitor is get from the
uvm_scoreboard (Scoreboard class) and it determines
whether the DUT is functioning properly or not, it evaluates
whether or not the actual results observed from the DUT
matches the predicted result. This gives the most flexible
way of reuse by allowing for substitution for predictor and
evaluator model. Functional verification ensures that the
implementation conforms to the specification from a
functional perspective. Because of the rapid growth of both
design size and complexity, functional verification has
become one of the key bottlenecks in the design process. The
uvm_agent has a configuration object that allows the test
writer to control aspects of the agent as the testbench is
assembled and executed.The uvm_agent and other
components are encapsulated in uvm_env (Environment
class). After the uvm_environment is defined, uvm_test is
initiated, configured. Then the uvm_test is started from an
initial block in the top-level HVL module by calling
uvm_test().
Fig.4. A testbench implemented using UVM Architecture for block level
verification.
IV. TOOLS
Software has become a major component of system
functionality, creating and designing new requirements for
block-to-system verification reuse and the need for system
verification and debug. Through this paper, the following
EDA tools are used.
Xilinx ISE Design Suite : This tool is used to synthesize
and implement the design. It is used in RTL design phase.
This tool uses both Verilog , VHDL and combination of both
Hardware Description Language. In this paper, Verilog
Hardware Description Language is used.
Questa Sim : Questa Sim spans all levels of design and
verification abstraction and supports multiple verification
methodologies and languages to increase testbench
productivity, automation and reusability. In this paper,
System Verilog language with UVM methodology is used.
This tool helps to view functional coverage better.
V. CONCLUSION
The RISC V gives and open resource environment to
allow the designer to tweak at a greater extend. In this
paper, 32-bit pipelined RISC V ISA is designed with
Verilog Hardware Description Language (HDL) and
synthesized. Harnessing the System Verilog with
verification methodology UVM, the correctness of the
design is verified and functional coverage is obtained.
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