CENTER OF EXCELLENCE

ADVANCED PROGRAM IN ELECTRONIC AND

COMMUNICATION ENGINEERING

LAB 2
Combinational Circuit Design

1. Project Objective:
The objectives of this lab are the following:
 To continue to introduce and use the various laboratory and design tools.
 To continue to learn about data sheets and real world properties of logic devices.
 To practice simplifying existing designs.
 To begin to learn to execute a logic design based upon a specified set of
requirements.
 To continue to work with the Altera DE1 board and Quartus environment and tools.
2. Project Scope:
To meet project requirements, you will need to:
a. Get used with Instruments and Tools for Digital System Design and Analysis.
b. Know how to configure the Function Generator
c. Well work with data sheets and real world parts and understand some new concepts
d. Build, develop project and analyze the stimulation results.
3. Reference Material
 The data sheets for the SN 74LS04.
 Referenced sections from Appendices B and C in the Brown and Vranesic text, 2nd
Edition.
 The DE 1 Board tutorials.
 The Verilog tutorials.
4. Lab Description
4.1 Cautions and Warnings
Never connect the power supply to your lab partner or your TA. This makes
him or her very crabby.
Always make certain that your ICs have the writing side up before pressing them
into the holes of your breadboard with your thumb.
 Never disconnect the power supply wires from your circuit and leave them lying
on your bench. The current will drain out of the power supply and the supply will
no longer be usable…. Unless, of course, you can manage to clean up the current
and somehow put it back in.
If you leave the current laying on your bench, it will no longer be current, but,
passed. The same thing will happen if you happen to swallow a berry from a current
bush. Thought, since the current bush is an annual plant, can it be used to solve the
energy crisis?
4.2 Background
Instruments and Tools for Digital System Design and Analysis
Let’s continue with our introduction to the various
laboratory tools and this time take a look at the function
generator. This tool provides a variety of different signals +v
ground
or waveforms that we can use as inputs to our systems. -v

Among other properties of a generated signal, the function

Figure 1
generator gives us the ability to control its amplitude,
offset (with respect to ground), frequency (period), and
pulse width. There are several characteristics that we will find to be common
amongst most function generators:
 Their output is bipolar by default – the signal excursion is above and below
ground as we see in figure 1.
 The instrument is designed to operate into a 50  load.

We must take these into account before we connect the generator to our circuit.
Let’s see what that means.

4.3 Procedure
4.3.1 Laboratory Part 1 – Working with the Function Generator
Configuring the Function Generator
In this first lab project, we will learn to work with an oscilloscope. It’s one of our
main tools for looking at the characteristics of signals in a circuit. We’ll find that it
gives us a lot more information than a DVM.
1. For all of the measurements in Part 1 of the Lab, DO NOT work on the
DE1 board….work on a separate breadboard.
2. Using the calibrated output (typically just below the lower right hand corner
of the display) on the scope, make sure that your probe is good.
3. Next, connect the output of a function generator to an oscilloscope.
 4. Using the controls on the scope (we say scope because it’s much more
coolerer than saying oscilloscope), set its input to ground and adjust the trace
to the center of the screen.
5. Set the scope’s input to DC and configure the vertical gain to 2.0 volts / cm.
6. Configure the function generator in to the 50  mode and select a square
wave output with an offset of 0 VDC and an amplitude of 5 VPP using the
front panel controls and display.
7. Measure and record the values shown on the oscilloscope. Are these values
consistent with the settings on the function generator?
8. Modify the function generator configuration to that
Vout
shown in figure 2. Select R1 to be approximately 50 Function
. Generator
R1

9. Repeat steps 2 - 7.
Are the values now consistent with the displayed Figure 2
settings on the function generator? Can you explain
the difference?
10. Configure the function generator into the HIGH Z mode and remove the
resistor, R1. Are the values now consistent with the displayed settings on the
function generator? Can you explain why?

4.3.2 Laboratory Part 2 – Working with Data Sheets and Real World Parts Again
For all of the measurements in Part 2 of the Lab, DO NOT work on the DE1
board….work on a separate breadboard.

Timing Measurements
In our first lab, we began to explore some of the real world aspects of the logic
parts that we’re working with. In those projects, we introduced the concept of
the propagation delay of a signal through a part. We also examined, in some
detail, the ability of our parts to source and to sink current.
Let’s now examine propagation delay in greater detail as well as look at two
additional time related parameters, rise time and fall time. Once again, we’ll
compare the measurements we make with those that we find in the vendor’s data
sheets.
In a digital device, the times for an input signal to propagate through the device
and cause the output signal to change from a high to a low or vice versa are given
in the vendor’s data sheet as PHL and PLH respectively. Generally, these times
are not equal.
A second important pair of parameters characterizing the real world behaviour
of a digital device are used to specify the time required for its output to change
from one state to another…from a low to a high and vice versa. These two times
are designated the rise time and fall times of the device and are specified by the
vendor as rise and fall respectively. We may also see these written as simply R
and F. As with propagation delay, these two signals are generally not equal.

1. As a first step, using the data sheet for an SN 74LS04, find the vendor
specified values for these two propagation
delays. Observe that a typical and a maximum
Function
value are given. What do these mean? Generator

2. Next, configure the function generator to Figure 3

produce a 5 V, 100 K Hz, square wave. Using
the oscilloscope, make certain that you have the
offset and amplitude set correctly.
3. Connect the function generator to the SN 74LS04 as shown in figure 3.
4. Using two scope probes, connect one to the gate’s
input and the other to its output. Measure and Input

record the values for PHL and PLH. These t pLH t pHL

measurements are made at the 50% points of the

Output
corresponding signals as we see in figure 4.
Figure 4

Compare the values you have

measured with those from the data 90% 90%
sheet. trise tfall

10% 10%
5. Using the oscilloscope, now measure
and record the rise and fall times of
Figure 5
the output of the SN 74LS04. These
measurements are made at the 10%
and 90% points in the signal as we see in figure 5.
Record the values you have measured. Do the values seem reasonable?
 Logic Reduction
In our first lab, we worked with the selectable multiple logic function circuit in
figure 6 below. Let’s revisit that circuit and explore simplifying the design.
1. As a first step, draw a Karnaugh map (Qua???? I know, I know, we’ll get
there) for the circuit in figure 6.

SEL1 SEL1 SEL2 RESULT

0 0 Result = A and B
0 1 Result = A or B
SEL2 1 0 Result = A xor B
1 1 Result = 0
A
B
Table 1.
RESULT
Truth Table for Result
function

Figure 6

2. From the Karnaugh map you just drew, can you see any way to swap only
two of the selection lines such that the logic for this circuit can be minimized?
Why can we do this?
The reduced design must not use any XOR gates. Show the revised selection
assignment table and draw a circuit diagram for this reduced circuit.
Create a new Verilog source file for your revised design run a simulation.
Use the average of the two propagation delays, PHL and PLH, that you
measured for the SN 74LS04 as the delay for each gate in your simulation.
3. What are the longest and shortest propagation delay paths, from input to
output, through your original implementation from Lab 1?
4. What are the longest and shortest propagation delay paths, from input to
output, through your revised circuit?
4.3.3 Laboratory Part 3 – Executing a Design from a Set of Requirements
Your company, MyEverything, following its incredibly successful introduction of
the products myPod, the online music shoppe, myTunes, and the fabulous state of
the art communications system, myPhone, has now embarked on its next great
venture: myPhoto. Weighing in at 20 megapixels and support for more than 4 trillion
colors (more than even the latest Parisian fashion shoppes), the beyond the state of
the art photographic system will far surpass anything that is currently on the market.
The product is in the early stages of its product development cycle.
In your position as a senior system designer, you have been given the task of
assembling a team, then designing and developing the prototype of the myPhoto
system.
The specification for the behaviour of the system is as follows:
Specification
Inputs
1. SYSON: the photographic system is turned on.
2. TAKE: capture the currently selected image.
3. SELFLASH: enable the advanced built-in light system.
4. NOFLASH: sensor that detects that the use of artificial lighting is prohibited.
5. ~INFOCUS: sensor that detects if the image is in focus.
6. ~LOWLIGHT: sensor that detects a low ambient light condition.

The inputs SYSON, TAKE, SELFLASH, and NOFLASH, are active high.
The inputs, ~INFOCUS and ~LOWLIGHT are active low.
Outputs
Four outputs, ~CAPTURE, ~OUTOFFOCUS, ~FLASH, and
~THERMONUCLEAR DEVICE
All outputs are low true – asserted low.
Operation
The operation of the myPhoto system is as follows:
Capture - the CAPTURE output is to be asserted under the
following conditions:
 The system is on, it is in focus, the ambient light is sufficient, flash has
not been selected, and the user chooses to take a picture.
 The system is on, it is in focus, the ambient light is low, flash has been
selected, the use of flash is permitted, and the user chooses to take a
picture.
Out of Focus - the OUTOFFOCUS output is to be asserted under
the following conditions:
The system is on, the in focus sensor indicates that the potential
image is out of focus, and the user chooses to take a picture.
 Flash - the FLASH output is to be asserted under the
following conditions:
 The user has elected to capture an image, flash has been
selected, flash is permitted, the system is in focus and ON.
 The user has elected to capture an image, the ambient light sensor
indicates a low light condition, flash is permitted, the system is in focus
and ON.
Thermonuclear Device - the system is to activate the
THERMONUCLEAR DEVICE output thereby effectively
stopping the use of any extraordinary ambient light enhancement
devices under the following conditions:
 The user has elected to capture an image, flash has been
selected, flash is not permitted, and the system is ON.
Design
With your partner…..
1. Draw a block diagram for your system. Clearly identify all inputs
and outputs.
Please see the document blockDiagramBasics for some general
guidelines for doing a block diagram.
2. Complete a paper design of the collection system as an SSI
implementation.
3. Model, simulate, and test your design using the Icarus Verilog Tools.
 Test all appropriate inputs. Verify your design by using the output
truth table and timing.
 Use the SN 74LS04 gate delay you measured in part 2 of this lab for
all gates within your module.
Build
To implement the system, we are going to use the Altera Cyclone II FPGA on
the DE 1 Board.
As we stated in Lab 1, the Quartus tools support both Verilog code and graphical
entry. For this design, we will use the graphical tools to first create the design
then enter the module into our project.
We will also continue to work with the Verilog code that we have developed and
tested up to this point.
 All of that said, read through this section completely before starting your
implementation…

Important First Steps

 First scan through the DE1_user_manual:
This is a very good overview of the capabilities of the board and a handy
reference.
 Start with and follow Tutorial 1in Appendix B of our class text to see how to
get a new project started (also see Recommended Design Approach below).
Specifically, first read section B3; then, from Appendix C, read sections C1.1
and C1.2.
 The same information is presented in a slightly different form in the Altera
tutorial in the DE1 tutorials in the document:
tut_quartus_intro_schematic.pdf.
Bear in mind that the devices in the Altera tutorial (s) are different from ours,
they may reference the DE2 board, and there may be some information that
we are not using at the moment.
Go through this document to get a step-by-step guided tour of developing a
schematic entry project in the Quartus environment.
 After you have gone over the tutorials and other background material, you’re
ready to go.

Recommended Design Approach

Working with the two tutorials, we recommend the following general design
approach.
1. Create a new project.
Under the Quartus environment select File →New Project Wizard.
2. Create a logic diagram of your design
Under the Quartus environment select File →New Block Diagram /
Schematic.
Add the file to your project.
Create the diagram.
3. Synthesize your project.
Synthesize your project by selecting
Processing →Start Compilation.
 4. Assign pins on the FPGA to your I/O signals
Follow the Altera Verilog tutorial to assign pins to all of your input and
output signals. The pins associated with each of the signals are given in
the DE1_user_manual.
For now, we’ll take the longer approach. Later, we’ll use a much faster
method.
5. Compile your program once again now that you have assigned the pins
We compile twice because Quartus needs to first figure out the inputs and
outputs to our system. Once those are known, we can assign pins to each
then recompile with full information.
6. Download your project to the Altera chip
Download your project by selecting Tools →Programmer.
7. Your design should be running and working perfectly in its new home.
Debug and Test
Verify that your design meets all the requirements in the original specification.
Extra Credit
For extra credit, propose and implement additional features or capabilities for
the myPhoto image capture system. Extra credit points will be based upon
originality, creativity, and imagination.
To receive extra credit, all of the basic features must be working properly.
To be considered for extra credit, each added feature must be fully functional.
4.3.4 Questions
1. If you had implemented your myPhoto image capture system using SSI parts,
how many chips would you have used?
2. Discuss the advantages and disadvantages of implementing the design in SSI vs.
array logic parts.
Consider the following:
 The amount of work (e.g. wiring, etc) that goes into making each circuit.
 The number of extra components needed for the circuit.
 The amount that is to be produced.
 Other items that may be considered when determining "cost".
 Debugging
When you are done, turn in your answers to all the questions as part of your final
report, your source code listings, and output of the Verilog simulation.
Be certain to clean up your bench when you are finished.
4.3.5 Laboratory Final Report
There is one report per team. The final report is to be typed and formatted according
to the guidelines specified for reports. Your report is due at the start of the demo of
your project.
The report must contain an itemized list for each team member identifying what he
or she contributed to the project. The list must be signed by the team member attesting
to the fact each of the items listed represents his or her own original work.
5. Assessment Plan

Performance Performance Criteria Weighting Mark

Areas
1. Teamwork 10%
1.1 Clear roles for all team members 40%
1.2 Clear tasks and deliverables assigned to each 60%
member

2. Design and 50%

Implement
2.1 Develop a Verilog entry project in the 20%
Quartus environment
2.2 Figure out the input and outputs of system 20%
2.3 Verify the design meets all the requirements 30%
in the original specification
2.4 Demonstrate the project 30%

3. Written report 40%

3.1 Well-organized report structure as required 20%
3.2 Clear answers of all lab questions 40%
3.3 Detailed explanations 40%