Combinational Logic:

ARITHMETIC CIRCUITS

Digital Systems Design

OBJECTIVES

• Describe combinational logic circuits

• Design multiplexers and demultiplexers
• Design decoders and encoders
• Design code converters
• Design Arithmetic circuits
• Design comparison circuits
• Write VHDL codes for basic combinational circuits
Arithmetic Architectures
The architecture depends of:
• Sampling rate:

Radar
Audio
Voice Vs. Sonar
Video
Communications
Image Processing

• Resources in the device

Arithmetic Architectures Types

Serial: 1-bit per

clock cycle

Parallel: 1-datum
per clock cycle

Pipeline: several
parallel operations
per clock cycle
ADDITION
• Addition is the most commonly performed arithmetic operation in digital systems
• An adder is a digital circuit that adds two N-bit numbers and generates an N-bit
number.
• Direct implementation of an N-bit adder would be very complex and not scalable
• A simpler approach would be to build an N-bit adder from smaller module
circuits, which can be duplicated and expanded as the size of the adder increases.

x
n

y Adder s
n
n

en
Half-Adder

• A 1-bit half-adder adds two 1-bit operands, and produces a 2-bit

result
• 1-bit half-adder cannot be used as a circuit module to build a larger
adder.

x s
Half
Adder
y cout
Half-Adder
Full-Adder

• A 1-bit half-adder adds three 1-bit operands, and produces a 2-bit

result

x s
Full
y
Adder
cin cout
Full-Adder
Full-Adder
s cout
cin cin
xy 0 1 xy 0 1
00 0 1 00 0 0
01 1 0 01 0 1
11 0 1 11 1 1
10 1 0 10 0 1

s = ̅ ·  · 
+ ̅ ·  · 
+ x ·  · 
+  ·  · 
cout = x ·  +  · 
+ x · 

s = ⨁⨁

Full-Adder
s = ⨁⨁

cout = x ·  +  · 
+ x · 

Full-Adder: Functional simulation

VHDL CODE GENERATED CIRCUIT

FUNCTIONAL SIMULATION
Full-Adder: Timing simulation
VHDL CODE
GENERATED CIRCUIT

TIMING SIMULATION
Adder – Serial Architecture*

xn-1 x0 sn-1 s0
x s Shift
Shift Register
Registers y Full
yn-1 y0 Adder cout
cin

Memory
Element

* Adder Serial architecture is a sequential circuit. Thus, it will be covered further in the course
Adder – Parallel Architecture: Ripple-Carry

Note: The carry-in to the least significant bit (c0) is normally cleared to 0
Ripple-Carry Adder
Adder – Parallel Architecture: Carry Look-Ahead

• To speed up the performance

of a ripple-carry adder, the
ripple effect of the carry must
be eliminated.
• Carry look-ahead adders are
much faster because they
compute the carry-in in a
parallel fashion.
Adder – Parallel Architecture: Carry Look-Ahead

Lets go back to a Full Adder Description…

Adder – Parallel Architecture: Carry Look-Ahead

Focus on the highlighted minterms…

Adder – Parallel Architecture: Carry Look-Ahead

Lets go back to a Full Adder Description…

(⨁) · 

·
Adder – Parallel Architecture: Carry Look-Ahead

 =  ·  + (⨁) · 

c3 c2 c1 c0 cc-1
-1

Lets generalize  =  ·  + ( ⨁ ) · 


Adder – Parallel Architecture: Carry Look-Ahead

 =  ·  + ( ⨁ ) · 


 

Generated Term Propagated Term

 =  +  · 

Adder – Parallel Architecture: Carry Look-Ahead

=0 →  =  ·  + ( ⨁ ) · 
 →  =  +  · 


=1 →  =  ·  + ( ⨁ ) · 

→  =  +  · 

=2 → % = % · % + (% ⨁% ) · 

 → % = % + % · 


=3 → ' = ' · ' + (' ⨁' ) · 

% → ' = ' + ' · 
%
Adder – Parallel Architecture: Carry Look-Ahead

=0 →  =  ·  + ( ⨁ ) · 
 →  =  +  · 


=1 →  =  ·  + ( ⨁ ) · 

→  =  +  · 

=2 → % = % · % + (% ⨁% ) · 

 → % = % + % · 


=3 → ' = ' · ' + (' ⨁' ) · 

% → ' = ' + ' · 
%
Adder – Parallel Architecture: Carry Look-Ahead

= 0 →  =  +  · 


= 1 →  =  +  · 

 =  +  ·  +  · 


 =  +  ·  +  ·  · 

= 2 → % = % + % · 

% = % + % ·  +  ·  +  ·  · 

% = % + % ·  + % ·  ·  + % ·  ·  · 


= 3 → ' = ' + ' · % + ' · % ·  + ' · % ·  ·  + ' · % ·  ·  · 


Adder – Parallel Architecture: Carry Look-Ahead

= 0 →  =  +  · 
  = ·  =  ⨁

= 1 →  =  +  · 
 =  ·   =  ⨁
% = % · % % = % ⨁%
 =  +  ·  +  · 

' = ' · ' ' = ' ⨁'
 =  +  ·  +  ·  · 

= 2 → % = % + % · 

% = % + % ·  +  ·  +  ·  · 

% = % + % ·  + % ·  ·  + % ·  ·  · 


= 3 → ' = ' + ' · % + ' · % ·  + ' · % ·  ·  + ' · % ·  ·  · 


Adder – Parallel Architecture: Carry Look-Ahead

= 0 →  =  +  · 

= 1 →  =  +  ·  +  ·  · 

= 2 → % = % + % ·  + % ·  ·  + % ·  ·  · 

= 3 → ' = ' + ' · % + ' · % ·  + ' · % ·  ·  + ' · % ·  ·  · 


 = ·  =  ⨁
 =  ·   =  ⨁ All terms depend on the current
inputs and the initial carry,
% = % · % % = % ⨁% therefore, no propagation delays
are observed
' = ' · ' ' = ' ⨁'
Adder – Parallel Architecture: Carry Look-Ahead

= 0 →  =  +  · 

= 1 →  =  +  ·  +  ·  · 

= 2 → % = % + % ·  + % ·  ·  + % ·  ·  · 

= 3 → ' = ' + ' · % + ' · % ·  + ' · % ·  ·  + ' · % ·  ·  · 


 = ·  =  ⨁
 =  ·   =  ⨁ All terms depend on the current
inputs and the initial carry,
% = % · % % = % ⨁% therefore, no propagation delays
are observed
' = ' · ' ' = ' ⨁'
Adder – Parallel Architecture: Carry Look-Ahead

= 0 →  =  +  · 

) =  ⨁


= 1 →  =  +  ·  +  ·  · 

) =  ⨁

 = ·  =  ⨁
 =  ·   =  ⨁
Adder – Parallel Architecture: Carry Look-Ahead

= 0 →  =  +  · 

) =  ⨁


= 1 →  =  +  ·  +  ·  · 

) =  ⨁

 = ·  =  ⨁
 =  ·   =  ⨁
Adder – Parallel Architecture: Carry Look-Ahead

= 0 →  =  +  · 

) =  ⨁


= 1 →  =  +  ·  +  ·  · 

) =  ⨁

 = ·  =  ⨁
 =  ·   =  ⨁
Subtraction

• The subtraction operation is performed as an addition operation

using the two’scomplement.
• Overflow never occurs.
• If the carry from the MSB is set (1), the result is the correct answer
and the carry is ignored.
• If the carry from the MSB is reset (0), the result is the two’s
complement of the answer.
Subtraction

x x s

y
Two´s y Adder
Complement cout
‘0’ cin

Two´s Complement

y x s
“00…01” y Adder
‘0’ cin cout
Subtraction
Adder-Substractor

x y x y x y x y
cout cin cout cin cout cin cout cin

s s s s
Multiplication

• The product of A (n bits) times B (m bits) is P (m+n bits)

• Types:
• Array (parallel) multiplier
• Series-parallel multiplier
• Series-Series multiplier
• Pipelined multiplier
• Reduced hardware multiplier
Parallel Multiplier - unsigned

ANDs

adders
Parallel Multiplier - unsigned
Parallel Multiplier - unsigned
Parallel Multiplier - unsigned
Parallel Multiplier - unsigned
4-bit Serial/Parallel Multiplier (CSAS)*

bn-1 b0

pn-1 p0
Shift
Register

*CSAS: Carry Save Add Shift

Work in class
• Design a combinational circuit to implement a unsigned
parallel multiplier.
• Write the VHDL code for the designed circuit
• Simulate in ModelSim your design
• Verify results for signed binary numbers