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00 - Note Lenovo - 448b7 - Compal - LA-8951PR01 Schematic PDF
00 - Note Lenovo - 448b7 - Compal - LA-8951PR01 Schematic PDF
Compal Confidential
Model Name : VIUS3/S4
File Name : LA-8951PR01
1 1
BOM P/N:43
Compal Confidential
/
/x
su
2 2
p.
om
Intel Ivy Bridge ULV Processor + Panther Point PCH
AMD Seymour XT
yc
m
//
3 2011-12-28 3
p:
REV:0.1
tt
h
4 4
Compal confidential
File Name :VIUS3/VIUS4
Chief River
AMD Seymour XT Intel DDR3-SO-DIMM X1
1 23mm *23mm PCI-E X16 IVY Bridge SV/ULV BANK 0, 1
1
/
100MHz 100MHz
Std HDMI HDMI 1.4a 2.7GT/s 5GT/s
/x
Connector 6*SATA
(port0,1 Support SATA3)
su
2 2
PX 5.0
LVDS Intel 4*USB3.0
Connector
Panther Point
p.
14*USB2.0
om
Mini card Slot 1 PCI-E(WLAN)
HM77/HM70
WLAN/WiMAX
USB PORT 2.0 x2 (Right)
FCBGA 989 Balls
IO Board
PCI Express (Full) 25mm*25mm
yc
mSATA(SSD) HD Audio
Mini card Slot 2 Card Reader RTS 5178 (2in1)
IO Board
SSD Gen 2
m
SPI ROM LPC BUS CMOS Camera
BIOS
// BlueTooth CONN
3 3
4MB*1
2MB*1 EC WLAN/WiMAX
p:
ENE KB9012
WWAN
LAN(10/100/Giga)
tt
WLAN/WiMAX
Realtek 2Channel Speaker
h
8105E-VD (10/100)
8111F-VL (Giga)
Int.KBD
Audio Codec Single Digital MIC
Touch Pad RealTek
RJ45 CONN ALC259-VC2
Audio Combo Jack
Sub-borad (APPLE type)
Thermal Sensor HeadPhone Output
4 Microphone Input 4
POWER BOARD EMC1403
IO Board
LED BOARD
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title
IO Board THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 02, 2012 Sheet 2 of 55
A B C D E
A B C D E
SIGNAL
Voltage Rails STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
/
G-series
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT
S0
5 Y-series
O O O O 4 56K +/- 5% 1.036 V 1.185 V 1.264 V EVT
6
/x
Y-series
5 100K +/- 5% 1.453 V 1.650 V 1.759 V DVT
7 Y-series
6 200K +/- 5% 1.935 V 2.200 V 2.341 V PVT
S3 Y-series
O O O X 7 NC 2.500 V 3.300 V 3.300 V MP
su
2 2
S5 S4/AC
O O X X USB Port Table BOM Structure Table
3 External BTO Item BOM Structure
p.
S5 S4/ Battery only USB 3.0 USB 2.0 Port
O X X X USB Port INTEL UMA only UMA@
S5 S4/AC & Battery
xHCI1 0 GPU:Seymour XT PX@ PX5@
X X X X UHCI0
om
don't exist xHCI2 1 USB 3.0 Port (Left Side) HDMI HDMI@
Address xHCI3 2 Mini Card(WLAN) HDD1 (HM77 SATA 3.0) HDD1@
EC SM Bus1 address EC SM Bus2 address UHCI1
xHCI4 3 HDD2 (HM70 SATA 2.0) HDD2@
EHCI1
4 X (USB PORT disabled on HM70 ) Interna-Intel-USB3.0 IU3@
Device Device Address UHCI2
yc
Smart Battery 0001 011X b Thermal Sensor F75303M 1001_101xb
5 X (USB PORT disabled on HM70 ) Interna-Intel-USB2.0 IU2@
6 X (USB PORT disabled on HM70 ) Blue Tooth BT@
UHCI3
7 X (USB PORT disabled on HM70 ) 10/100 LAN 8105E@
PCH SM Bus address
m
8 USB/B (Right Side USB-BD) GIGA LAN 8111F@
UHCI4
9 USB/B (Right Side USB-BD) Connector ME@
Device Address
10 USB Port (Right Side CR-BD) 45 LEVEL 45@
DDR DIMM0 1001 000Xb
// EHCI2 UHCI5
11 Camera (LVDS) Unpop @
DDR DIMM2 1001 010Xb
3 3
12 X (USB PORT disabled on HM70 )
UHCI6
13 X (USB PORT disabled on HM70 )
AMD-GPU SM Bus address
p:
PCH
SMBDATA +3VALW +3VS +3VS HM70 Disable P5,P6,P7,P8
SML0CLK
SML0DATA
PCH
+3VALW
X X X X X X X
Compal Electronics, Inc.
V X V X X V X
Compal Secret Data
SML1CLK
Security Classification
PCH Issued Date 2011/06/15 2012/07/11 Title
SML1DATA +3VS +3VS +3VS
Deciphered Date
+3VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7981P
Date: Friday, February 03, 2012 Sheet 3 of 55
A B C D E
5 4 3 2 1
/
BIF_VDDC (current consumption = 55mA@1.0V, in Same as OFF ON 70mA
PCIE_VDDC(1.0V) BACO mode) VDDC Same as
PCIE_VDDC
/x
BIF_VDDC=VGA_CORE When GPU enable
BIF_VDDC=1.0V When BACO
VDDR1(1.5VGS) VDDR1 1.5V OFF OFF 2.8A
VDDC/VDDCI 1.12V OFF OFF 12.9A
su
C C
VDDC/VDDCI(1.12V)
p.
VDD_CT(1.8V)
PXS_RST# PE_EN BACO Switch
iGPU dGPU
om
PERSTb BIF_VDDC
PXS_PWREN
REFCLK PX_mode
yc
+3.3VALW MOS
+3.3VGS
Straps Reset 1
m
+1.5V SI4800
+1.5VGS
Straps Valid +1.0V +1.0VGS
Regulator
2 3
//
B
Global ASIC Reset B
+B Regulator
+VGA_CORE
+1.8V +1.8VGS
T4+16clock
SI4800
5 4
p:
PWRGOOD
tt
h
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7981P
Date: Thursday, February 02, 2012 Sheet 4 of 55
5 4 3 2 1
A B C D E
1
R249 max length = 500 mils
24.9_0402_1%
- typical impedance = 14.5 mohms
UCPU1A
W=12mil L=500mil S=15mil
2
1 G3 PEG_COMP 1
PEG_ICOMPI G1
[15] DMI_CRX_PTX_N0 M2
DMI_RX#[0]
PEG_ICOMPO
PEG_RCOMPO
G4 Layout placement: Place close to U8 (GPU)
[15] DMI_CRX_PTX_N1 P6
P1 DMI_RX#[1]
[15] DMI_CRX_PTX_N2 DMI_RX#[2]
[15] DMI_CRX_PTX_N3 P10 H22 PEG_GTX_C_HRX_N0 C259 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N0
DMI_RX#[3] PEG_RX#[0] J21 PEG_GTX_C_HRX_N1 C276 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N1
N3 PEG_RX#[1] B22 PEG_GTX_C_HRX_N2 C257 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N2
[15] DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2]
[15] DMI_CRX_PTX_P1 P7 D21 PEG_GTX_C_HRX_N3 C274 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N3
DMI_RX[1] PEG_RX#[3] PEG_GTX_HRX_N[0..15] [22]
DMI
[15] DMI_CRX_PTX_P2 P3 A19 PEG_GTX_C_HRX_N4 C254 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N4
DMI_RX[2] PEG_RX#[4] PEG_GTX_HRX_P[0..15] [22]
[15] DMI_CRX_PTX_P3 P11 D17 PEG_GTX_C_HRX_N5 C272 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N5
DMI_RX[3] PEG_RX#[5] B14 PEG_GTX_C_HRX_N6 C252 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N6
PEG_RX#[6] PEG_HTX_C_GRX_N[0..15] [22]
K1 D13 PEG_GTX_C_HRX_N7 C270 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N7
[15] DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] PEG_HTX_C_GRX_P[0..15] [22]
M8 A11 PEG_GTX_C_HRX_N8 C250 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N8
[15] DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
N4 B10 PEG_GTX_C_HRX_N9 C268 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N9
[15] DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
R2 G8 PEG_GTX_C_HRX_N10 C248 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N10
[15] DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] A8 PEG_GTX_C_HRX_N11 C267 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N11
K3 PEG_RX#[11] B6 PEG_GTX_C_HRX_N12 C246 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N12
[15] DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12]
M7 H8 PEG_GTX_C_HRX_N13 C264 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N13
[15] DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
P4 E5 PEG_GTX_C_HRX_N14 C244 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N14
/
[15] DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
T3 K7 PEG_GTX_C_HRX_N15 C262 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N15
[15] DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
/x
K22 PEG_GTX_C_HRX_P0 C258 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P0
PEG_RX[0] K19 PEG_GTX_C_HRX_P1 C277 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P1
PEG_RX[1] C21 PEG_GTX_C_HRX_P2 C256 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P2
U7 PEG_RX[2] D19 PEG_GTX_C_HRX_P3 C275 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P3
[15] FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3]
W11 C19 PEG_GTX_C_HRX_P4 C255 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P4
[15] FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
W1 D16 PEG_GTX_C_HRX_P5 C273 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P5
[15] FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]
su
AA6 C13 PEG_GTX_C_HRX_P6 C253 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P6
[15] FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]
2 W6 D12 PEG_GTX_C_HRX_P7 C271 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P7 2
[15] FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
V4 C11 PEG_GTX_C_HRX_P8 C251 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P8
Intel(R) FDI
C8 PEG_GTX_C_HRX_P11 C266 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P11
p.
PEG_RX[11] C5 PEG_GTX_C_HRX_P12 C247 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P12
U6 PEG_RX[12] H6 PEG_GTX_C_HRX_P13 C265 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P13
[15] FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
W10 F6 PEG_GTX_C_HRX_P14 C245 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P14
[15] FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
W3 K6 PEG_GTX_C_HRX_P15 C263 1 2 PX@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P15
[15] FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
om
AA7
[15] FDI_CTX_PRX_P3 FDI0_TX[3]
W7 G22 PEG_HTX_GRX_N0 C562 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N0
[15] FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
T4 C23 PEG_HTX_GRX_N1 C582 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N1
[15] FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
AA3 D23 PEG_HTX_GRX_N2 C564 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N2
[15] FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
AC8 F21 PEG_HTX_GRX_N3 C584 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N3
[15] FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] H19 PEG_HTX_GRX_N4 C566 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N4
+1.05VS_VTT AA11 PEG_TX#[4] C17 PEG_HTX_GRX_N5 C587 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N5
[15] FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
eDP_COMPIO and ICOMPO signals AC12 K15 PEG_HTX_GRX_N6 C568 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N6
yc
[15] FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] F17 PEG_HTX_GRX_N7 C589 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N7
should be shorted near balls and U11 PEG_TX#[7] F14 PEG_HTX_GRX_N8 C570 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N8
[15] FDI_INT FDI_INT PEG_TX#[8]
routed with typical impedance PEG_TX#[9]
A15 PEG_HTX_GRX_N9 C591 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N9
1
m
can't be left floating FDI1_LSYNC PEG_TX#[11] M10 PEG_HTX_GRX_N12 C574 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N12
24.9_0402_1% PEG_TX#[12]
,even if disable eDP function... F10 PEG_HTX_GRX_N13 C594 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N13
PEG_TX#[13] D9 PEG_HTX_GRX_N14 C576 1 2 PX@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N14
W=12mil L=500mil S=15mil
2
IVY-BRIDGE_BGA1023
@
Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)
4 4
+1.05VS_VTT
非 外外外
PCH->CPU PH VCPLL and connect to PCH DF_TVS BCLK H2 CLK_CPU_DMI [14]
UNCOREPWRGOOD: CORE OK BCLK# CLK_CPU_DMI# [14]
MISC
CLOCKS
F49
都 後後 做
SM_DRAMPWROK:DRAM power ok [17] H_SNB_IVB# PROC_SELECT# AG3 CLK_CPU_DPLL
RESET#: ok CPU reset DPLL_REF_CLK AG1 CLK_CPU_DPLL#
偵偵CPU有有有有
C57 DPLL_REF_CLK#
PROC_DETECT#
SM_RCOMP0,SM_RCOMP1
Follow DG 1.5& Tacoma_Fall2 1.0 W=20mil L=500mil S=13mil
reserve XBOX 三三三三 T33 PAD @ H_CATERR# C49
CATERR# SM_RCOMP2
W=15mil L=500mil S=13mil
THERMAL
@
C614 2 1 0.1U_0402_16V4Z H_CPUPWRGD_R
follow Checklist 1.5 H_PECI A48 AT30 SM_DRAMRST#
[18,37] H_PECI PECI SM_DRAMRST# SM_DRAMRST# [7]
R292 2 1 10K_0402_5% +1.05VS_VTT R534 2 1 62_0402_5% R533 1
56_0402_5% BF44 SM_RCOMP0 R272 2 1 140_0402_1% @ C82
SM_RCOMP[0]
DDR3
MISC
[37,42] H_PROCHOT# H_PROCHOT# 1 2 H_PROCHOT#_R C45 BE43 SM_RCOMP1 R273 2 1 25.5_0402_1%
PROCHOT# SM_RCOMP[1] BG43 SM_RCOMP2 R267 2 1 200_0402_1% 100P_0402_50V8J
SM_RCOMP[2] 2
/
DDR3 Compensation Signals
D45
[18] H_THERMTRIP# THERMTRIP#
/x
N53
PRDY# N55
PREQ# ESD
TCK
L56
L55
XDP_TCK
XDP_TMS
C Reserve
TMS
PWR MANAGEMENT
J58 XDP_TRST#
su
TRST#
非CORE外外外OK
PM_SYNC TDI L59 XDP_TDO
TDO
UNCOREPWRGOOD:
PU/PD for JTAG signals +1.05VS_VTT
[18] H_CPUPWRGD
1 2 H_CPUPWRGD_R B46
R305 0_0402_5% UNCOREPWRGOOD K58 XDP_DBRESET#
p.
DBR#
R237 XDP_TMS R20 2 1 51_0402_5%
1 2 VDDPWRGOOD_R BE45 G58 XDP_TDI R39 2 1 51_0402_5%
130_0402_1% SM_DRAMPWROK BPM#[0] E55 XDP_TDO R37 2 1 51_0402_5%
BPM#[1] E59 @
SM_DRAMPWROK:DRAM power ok BPM#[2]
om
G55 XDP_TCK R40 2 1 51_0402_5%
BPM#[3] G59 +3VS XDP_TRST# R28 2 1 51_0402_5%
BUF_CPU_RST# D44 BPM#[4] H60
RESET# BPM#[5] J59 XDP_DBRESET# R312 2 1 1K_0402_5%
BPM#[6] J61
BPM#[7]
Tacoma_Fall2 1.0 PH 1K +3VS
Check list 1.5 PH 1K +3VS
Debug port DG1.1-1.3 50~5K ohm
yc
IVY-BRIDGE_BGA1023
@
m
+3VALW
Buffered reset to CPU
+3VS +1.5V_CPU_VDDQ
//
1
3 C228 +3VS 3
1
0.1U_0402_16V4Z
R31
10K_0402_5% R238
2
1 2 200_0402_5%
U22 +1.05VS_VTT
p:
1
@ C617
R35
2
5
10K_0402_5% 0.1U_0402_16V4Z
1
1 2 1
P
[15] SYS_PWROK
2
B 4PM_SYS_PWRGD_BUF R546
2 O 75_0402_5%
[15] PM_DRAM_PWRGD A
G
tt
1
5
74AHC1G09GW_TSSOP5 R544 U45
3
2
43_0402_5% 1
P
@ R38 BUF_CPU_RST# 1 2 BUFO_CPU_RST# 4 NC
39_0402_5% Y 2PCH_PLTRST#
A PCH_PLTRST# [17]
G
h
SN74LVC1G07DCKR_SC70-5
1 2
C43
3
0.1U_0402_16V4Z
D @
2
4 4
UCPU1C UCPU1D
[12] DDR_A_D[0..63]
DDR_A_D0 AG6 AL4
DDR_A_D1 AJ6 SA_DQ[0] AU36 AL1 SB_DQ[0] BA34
DDR_A_D2 AP11 SA_DQ[1] SA_CK[0] AV36 SA_CLK_DDR0 [12] AN3 SB_DQ[1] SB_CK[0] AY34
DDR_A_D3 AL6 SA_DQ[2] SA_CK#[0] AY26 SA_CLK_DDR#0 [12] AR4 SB_DQ[2] SB_CK#[0] AR22
AJ10 SA_DQ[3] SA_CKE[0] DDRA_CKE0_DIMMA [12] AK4 SB_DQ[3] SB_CKE[0]
DDR_A_D4
1 DDR_A_D5 AJ8 SA_DQ[4] AK3 SB_DQ[4] 1
DDR_A_D6 AL8 SA_DQ[5] AN4 SB_DQ[5]
DDR_A_D7 AL7 SA_DQ[6] AR1 SB_DQ[6]
DDR_A_D8 AR11 SA_DQ[7] AU4 SB_DQ[7]
DDR_A_D9 AP6 SA_DQ[8] AT40 AT2 SB_DQ[8] BA36
AU6 SA_DQ[9] SA_CK[1] AU40 SA_CLK_DDR1 [12] AV4 SB_DQ[9] SB_CK[1] BB36
DDR_A_D10
DDR_A_D11 AV9 SA_DQ[10] SA_CK#[1] BB26 SA_CLK_DDR#1 [12] BA4 SB_DQ[10] SB_CK#[1] BF27
DDR_A_D12 AR6 SA_DQ[11] SA_CKE[1] DDRA_CKE1_DIMMA [12] AU3 SB_DQ[11] SB_CKE[1]
DDR_A_D13 AP8 SA_DQ[12] AR3 SB_DQ[12]
DDR_A_D14 AT13 SA_DQ[13] AY2 SB_DQ[13]
DDR_A_D15 AU13 SA_DQ[14] BA3 SB_DQ[14]
DDR_A_D16 BC7 SA_DQ[15] BE9 SB_DQ[15]
DDR_A_D17 BB7 SA_DQ[16] BB40 BD9 SB_DQ[16] BE41
DDR_A_D18 BA13 SA_DQ[17] SA_CS#[0] BC41 DDRA_CS0_DIMMA# [12] BD13 SB_DQ[17] SB_CS#[0] BE47
DDR_A_D19 BB11 SA_DQ[18] SA_CS#[1] DDRA_CS1_DIMMA# [12] BF12 SB_DQ[18] SB_CS#[1]
DDR_A_D20 BA7 SA_DQ[19] BF8 SB_DQ[19]
DDR_A_D21 BA9 SA_DQ[20] BD10 SB_DQ[20]
DDR_A_D22 BB9 SA_DQ[21] BD14 SB_DQ[21]
DDR_A_D23 AY13 SA_DQ[22] BE13 SB_DQ[22]
DDR_A_D24 AV14 SA_DQ[23] AY40 BF16 SB_DQ[23] AT43
DDR_A_D25 AR14 SA_DQ[24] SA_ODT[0] BA41 SA_ODT0 [12] BE17 SB_DQ[24] SB_ODT[0] BG47
SA_DQ[25] SA_ODT[1] SA_ODT1 [12] SB_DQ[25] SB_ODT[1]
/
DDR_A_D26 AY17 BE18
DDR_A_D27 AR19 SA_DQ[26] BE21 SB_DQ[26]
DDR_A_D28 BA14 SA_DQ[27] BE14 SB_DQ[27]
DDR_A_D29 AU14 SA_DQ[28] BG14 SB_DQ[28]
/x
DDR_A_D30 BB14 SA_DQ[29] BG18 SB_DQ[29]
DDR_A_D31 BB17 SA_DQ[30] AL11 DDR_A_DQS#0 DDR_A_DQS#[0..7] [12] BF19 SB_DQ[30] AL3
DDR_A_D32 BA45 SA_DQ[31] SA_DQS#[0] AR8 DDR_A_DQS#1 BD50 SB_DQ[31] SB_DQS#[0] AV3
DDR_A_D33 AR43 SA_DQ[32] SA_DQS#[1] AV11 DDR_A_DQS#2 BF48 SB_DQ[32] SB_DQS#[1] BG11
DDR_A_D34 AW48 SA_DQ[33] SA_DQS#[2] AT17 DDR_A_DQS#3 BD53 SB_DQ[33] SB_DQS#[2] BD17
DDR_A_D35 BC48 SA_DQ[34] SA_DQS#[3] AV45 DDR_A_DQS#4 BF52 SB_DQ[34] SB_DQS#[3] BG51
su
DDR_A_D36 BC45 SA_DQ[35] SA_DQS#[4] AY51 DDR_A_DQS#5 BD49 SB_DQ[35] SB_DQS#[4] BA59
2 DDR_A_D37 AR45 SA_DQ[36] SA_DQS#[5] AT55 DDR_A_DQS#6 BE49 SB_DQ[36] SB_DQS#[5] AT60 2
p.
DDR_A_D42 BB51 BC59
DDR_A_D43 AY53 SA_DQ[42] AY60 SB_DQ[42]
DDR_A_D44 BB49 SA_DQ[43] BE54 SB_DQ[43]
DDR_A_D45 AU49 SA_DQ[44] AJ11 DDR_A_DQS0 DDR_A_DQS[0..7] [12] BG54 SB_DQ[44]
DDR_A_D46 BA53 SA_DQ[45] SA_DQS[0] AR10 DDR_A_DQS1 BA58 SB_DQ[45] AM2
SA_DQ[46] SA_DQS[1] SB_DQ[46] SB_DQS[0]
om
DDR_A_D47 BB55 AY11 DDR_A_DQS2 AW59 AV1
DDR_A_D48 BA55 SA_DQ[47] SA_DQS[2] AU17 DDR_A_DQS3 AW58 SB_DQ[47] SB_DQS[1] BE11
DDR_A_D49 AV56 SA_DQ[48] SA_DQS[3] AW45 DDR_A_DQS4 AU58 SB_DQ[48] SB_DQS[2] BD18
DDR_A_D50 AP50 SA_DQ[49] SA_DQS[4] AV51 DDR_A_DQS5 AN61 SB_DQ[49] SB_DQS[3] BE51
DDR_A_D51 AP53 SA_DQ[50] SA_DQS[5] AT56 DDR_A_DQS6 AN59 SB_DQ[50] SB_DQS[4] BA61
DDR_A_D52 AV54 SA_DQ[51] SA_DQS[6] AK54 DDR_A_DQS7 AU59 SB_DQ[51] SB_DQS[5] AR59
DDR_A_D53 AT54 SA_DQ[52] SA_DQS[7] AU61 SB_DQ[52] SB_DQS[6] AK61
DDR_A_D54 AP56 SA_DQ[53] AN58 SB_DQ[53] SB_DQS[7]
AP52 SA_DQ[54] AR58 SB_DQ[54]
yc
DDR_A_D55
DDR_A_D56 AN57 SA_DQ[55] AK58 SB_DQ[55]
DDR_A_D57 AN53 SA_DQ[56] AL58 SB_DQ[56]
DDR_A_D58 AG56 SA_DQ[57] AG58 SB_DQ[57]
DDR_A_D59 AG53 SA_DQ[58] AG59 SB_DQ[58]
DDR_A_D60 AN55 SA_DQ[59] AM60 SB_DQ[59]
SA_DQ[60] DDR_A_MA[0..15] [12] SB_DQ[60]
m
DDR_A_D61 AN52 BG35 DDR_A_MA0 AL59 BF32
DDR_A_D62 AG55 SA_DQ[61] SA_MA[0] BB34 DDR_A_MA1 AF61 SB_DQ[61] SB_MA[0] BE33
DDR_A_D63 AK56 SA_DQ[62] SA_MA[1] BE35 DDR_A_MA2 AH60 SB_DQ[62] SB_MA[1] BD33
SA_DQ[63] SA_MA[2] BD35 DDR_A_MA3 SB_DQ[63] SB_MA[2] AU30
SA_MA[3] AT34 DDR_A_MA4 SB_MA[3] BD30
SA_MA[4] SB_MA[4]
SA_MA[5]
SA_MA[6]
AU34
BB32
//
DDR_A_MA5
DDR_A_MA6 SB_MA[5]
SB_MA[6]
AV30
BG30
BD37 AT32 DDR_A_MA7 BG39 BD29
3 [12] DDR_A_BS0 BF36 SA_BS[0] SA_MA[7] AY32 BD42 SB_BS[0] SB_MA[7] BE30 3
DDR_A_MA8
[12] DDR_A_BS1 BA28 SA_BS[1] SA_MA[8] AV32 DDR_A_MA9 AT22 SB_BS[1] SB_MA[8] BE28
[12] DDR_A_BS2 SA_BS[2] SA_MA[9] BE37 DDR_A_MA10 SB_BS[2] SB_MA[9] BD43
SA_MA[10] BA30 DDR_A_MA11 SB_MA[10] AT28
p:
IVY-BRIDGE_BGA1023 IVY-BRIDGE_BGA1023
h
@ @
R216
0_0402_5% R212
1 2 1K_0402_5%
CPU 通通DIMM做reset @
2
3 1 1 2
S
BSS138_NL_SOT23-3
R217 S0
G
2
4.99K_0402_1%
DRAMRST_CNTRL_PCH hgih ,MOS ON
SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH
1
S3
[14] DRAMRST_CNTRL_PCH
1 2 DRAMRST_CNTRL DRAMRST_CNTRL_PCH Low ,MOS OFF
R62 0_0402_5% SM_DRAMRST# lo,DDR3 DRAMRST# HIGH
[10] DRAMRST_CNTRL Dimm not reset
1 2
[37] DRAMRST_CNTRL_EC
R64 0_0402_5%
S4,5 Security Classification Compal Secret Data Compal Electronics, Inc.
1
DS3@ C190 DRAMRST_CNTRL_PCH Low ,MOS OFF 2011/06/24 2012/07/12 Title
For DS3 0.047U_0402_16V7K SM_DRAMRST# lo,DDR3 DRAMRST# low
Issued Date Deciphered Date PROCESSOR(3/7) DDRIII
2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Dimm reset AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 7 of 55
A B C D E
A B C D E
1
R296
T32 PAD @ CFG0 B50 N59 1K_0402_1%
C51 CFG[0] BCLK_ITP N58
2
CFG2 B54 CFG[1] BCLK_ITP#
D53 CFG[2]
+CPU_CORE CFG4 A51 CFG[3] N42
1 1
CFG5 C53 CFG[4] RSVD30 L42
CFG6 C55 CFG[5] RSVD31 L45
PEG Static Lane Reversal - CFG2 is for the 16x
CFG[6] RSVD32
2
啟啟
CFG[14] RSVD38
2
F51
R91 D52 CFG[15] CFG4 UMA,Optimus eDP
關關
100_0402_1% L53 CFG[16] AT49
CFG[17] RSVD39 DISO eDP
1
@ K24
RSVD40
1
RESERVED
VCC_VAL_SENSE H43 @ R293
VSS_VAL_SENSE VSS_VAL_SENSE K43 VCC_VAL_SENSE AH2 1K_0402_1%
VSS_VAL_SENSE RSVD41 AG13
2
RSVD42
2
AM14
/
R306 VAXG_VAL_SENSE H45 RSVD43 AM15
VSSAXG_VAL_SENSE K45 VAXG_VAL_SENSE RSVD44
VSSAXG_VAL_SENSE
/x
49.9_0402_1%
N50 eDP enable
1
su
K48 0:Enable
2 RSVD7 A4 2
DC_TEST_A4 C4
BA19 DC_TEST_C4 D3 CFG6
AV19 RSVD8 DC_TEST_D3 D1 CFG5
+VGFX_CORE AT21 RSVD9 DC_TEST_D1 A58
p.
BB21 RSVD10 DC_TEST_A58 A59
RSVD11 DC_TEST_A59
1
BB19 C59
AY21 RSVD12 DC_TEST_C59 A61 R543 R541
RSVD13 DC_TEST_A61
2
om
R310 AY22 D61 These pins are for solder joint @ @
AU19 RSVD15 DC_TEST_D61 BD61
2
49.9_0402_1% AU21 RSVD16 DC_TEST_BD61 BE61 reliability and non-critical to
BD21 RSVD17 DC_TEST_BE61 BE59
function. For BGA only.
1
BG22 BG4
yc
R95 BE22 RSVD22 DC_TEST_BG4 BG3
100_0402_1% BG26 RSVD23 DC_TEST_BG3 BE3
BE26 RSVD24 DC_TEST_BE3 BG1
PCIE Port Bifurcation Straps
@ RSVD25 DC_TEST_BG1
BF23 BE1
1
m
VSSAXG_VAL_SENSE RSVD27 DC_TEST_BD1
CFG[6:5] 10: 2x8 PCI Express
2
3 3
CFG7
1
p:
R297
@ 1K_0402_1%
2
tt
h
4 4
C26
VCC[9] VCCIO[13]
AL14
PD0.8
PD0.8 C27
VCC[10] VCCIO[14]
AL15
C32
VCC[11] VCCIO[15]
AL16
CAP at Power side
CAP at Power side C34
C37 VCC[12] VCCIO[16]
AL20
AL22
C39 VCC[13] VCCIO[17] AL26
C42 VCC[14] VCCIO[18] AL45
D27 VCC[15] VCCIO[19] AL48
D32 VCC[16] VCCIO[20] AM16
D34 VCC[17] VCCIO[21] AM17
D37 VCC[18] VCCIO[22] AM21
D39 VCC[19] VCCIO[23] AM43
CORE SUPPLY
F25
F26 VCC[28]
/
F28 VCC[29]
F32 VCC[30]
F34 VCC[31]
/x
F37 VCC[32] AA14
F38 VCC[33] VCCIO[30] AA15
VCC[34] VCCIO[31] For PEG
F42 AB17
G42 VCC[35] VCCIO[32] AB20
H25 VCC[36] VCCIO[33] AC13
H26 VCC[37] VCCIO[34] AD16
H28 VCC[38] VCCIO[35] AD18
su
H29 VCC[39] VCCIO[36] AD21
2 H32 VCC[40] VCCIO[37] AE14 2
H34 VCC[41] VCCIO[38] AE15
H35 VCC[42] VCCIO[39] AF16
H37 VCC[43] VCCIO[40] AF18
H38 VCC[44] VCCIO[41] AF20
p.
H40 VCC[45] VCCIO[42] AG15
J25 VCC[46] VCCIO[43] AG16
J26 VCC[47] VCCIO[44] AG17 +3VS
J28 VCC[48] VCCIO[45] AG20
J29 VCC[49] VCCIO[46] AG21
VCC[50] VCCIO[47]
om
1
J32 AJ14
J34 VCC[51] VCCIO[48] AJ15 R521
J35 VCC[52] VCCIO[49] 10K_0402_5%
J37 VCC[53]
J38 VCC[54]
2
J40 VCC[55] +1.05VS_VTT
J42 VCC[56]
K26 VCC[57] W16 VCCIO_SEL
K27 VCC[58] VCCIO50 W17 VCCIO_SEL after Ivy bridge ES2 Voltage support
yc
VCC[59] VCCIO51
1
K29
K32 VCC[60] R522
K34 VCC[61] 10K_0402_5% 1/NC : (Default) +1.05VS_VTT
K35
K37
VCC[62]
VCC[63]
@ BC22 * 0: +1.0VS_VTT
2
K39 VCC[64]
m
K42 VCC[66] BC22 VCCIO_SEL
L25 VCC[67] VCCIO_SEL
L28 VCC[68]
L33 VCC[69]
L36 VCC[70] +1.05VS_VTT
// L40
N26
VCC[71]
VCC[72]
+1.05VS_VTT +1.05VS_VTT
QUIET
RAILS
1
3 N34 VCC[74] VCCPQE[1] AN22 3
N38 VCC[75] VCCPQE[2] R531 R529
Place the PU
VCC[76] 1 2 130_0402_5% 75_0402_5% resistors close to CPU
C553
p:
1U_0402_6.3V6K
2
A44 H_CPU_SVIDALRT# R528 1 2 43_0402_1%
VR_SVID_ALRT# [50]
tt
SVID
C44 H_CPU_SVIDDAT R530 1 2 0_0402_5%
VIDSOUT VR_SVID_DAT [50]
+CPU_CORE
h
Place the PU
1
resistors close to VR 1 R79 2 R281
100_0402_1%
100_0402_1%
@
2
F43 VCCSENSE_R R282 1 2 0_0402_5%
SENSE LINES VCC_SENSE VCCSENSE [50]
G43 VSSSENSE_R R289 1 2 0_0402_5%
VSS_SENSE VSSSENSE [50]
1
R513 1 2 10_0402_5% +1.05VS_VTT
R288
AN16 VCCIO_SENSE 100_0402_1%
VCCIO_SENSE VCCIO_SENSE [47]
AN17 VSSIO_SENSE_L
VSS_SENSE_VCCIO VSSIO_SENSE_L [47]
2
1
R512 Should change to connect form
10_0402_5%
power cirucit & layout differential
IVY-BRIDGE_BGA1023
4 with VCCIO_SENSE. 4
2
@
Check list 1.5
+1.5V +1.5V_CPU_VDDQ
@ J1
1 2
PAD-OPEN 4x4m
M3 Support
1
R86 1 @ 2 0_0402_5%
1 2 R80 @ C116
[40,45,46] SUSP 0_0402_5% R65 U11 AO4430L_SO8 220_0402_5% 0.1U_0402_10V6K +VREF_DQ_DIMMA
2
8 1
7 2
2
6 3 3
D
SA_DIMM_VREFDQ 1
+3VALW +VSB 5
1
BSS138_NL_SOT23-3
D Q2204
G
4
2
1
2 RUN_ON_CPU1.5VS3#
1
R85 Q7 G DRAMRST_CNTRL_PCH
R78 82K_0402_5% 2N7002K_SOT23-3 S DRAMRST_CNTRL [7]
1 100K_0402_5% @ 1
3
R175
2
15K_0402_1%
2
RUN_ON_CPU1.5VS3 1 2
RUN_ON_CPU1.5VS3#
1
1
1
1
@ D R77 C115
R81 2 1 0_0402_5% 2 D 330K_0402_5% 0.047U_0603_25V7K
2
[37,40] CPU1.5V_S3_GATE 2
G @
2
Q6 S G Q8
1 @ 2 2N7002K_SOT23-3 S 2N7002K_SOT23-3
3
[37,40,45,46,47,49] SUSP#
0_0402_5% R82 @
3
+1.5V_CPU_VDDQ
+1.5V
RUN_ON_CPU1.5VS3# [6]
+V_SM_VREF_CNT should
POWER
1
R117 2 @ 1 0_0402_5%
UCPU1G have 20 mil trace width R113 @ R76
1K_0402_1% 1K_0402_1%
+VGFX_CORE
DC 29A
2
AY43 3
D
+V_SM_VREF_CNT 1 +V_SM_VREF
AA46 SM_VREF Q11
VREF
VAXG[1]
1
AB47 AO3414_SOT23-3
VAXG[2]
1
AB50 BE7 SA_DIMM_VREFDQ C117 @ @ R116
G
2
VAXG[3] SA_DIMM_VREFDQ
/
AB51 BG7 SB_DIMM_VREFDQ 0.1U_0402_16V4Z 1K_0402_1%
AB52 VAXG[4] SB_DIMM_VREFDQ R124
INTEL Recommend VAXG
2
AB53 VAXG[5] 1K_0402_1% RUN_ON_CPU1.5VS3
2
VAXG[6]
1
AB55
2*470uF,6*22uF(0805) and 6*10uF(0603) VAXG[7]
/x
AB56
2
AB58 VAXG[8] R519 @ R518 @
VAXG[9]
11*1U(0402) AB59
AC61 VAXG[10]
1K_0402_1% 1K_0402_1%
SA_DIMM_VREFDQ
2
AD47 VAXG[11]
PD0.8 AD48 VAXG[12]
VAXG[13]
5A SB_DIMM_VREFDQ
AD50
AD51 VAXG[14] AJ28
Check list1.5 P18 M1 default M3 no stuff
- 1.5V RAILS
VAXG[15] VDDQ[1]
su
AD52 AJ33
AD53 VAXG[16] VDDQ[2] AJ36
2 AD55 VAXG[17] VDDQ[3] AJ40 +1.5V_CPU_VDDQ 2
AD56 VAXG[18] VDDQ[4] AL30
Place TOP IN BGA INTEL Recommend VDDQ
AD58 VAXG[19] VDDQ[5] AL34
AD59 VAXG[20]
VAXG[21]
VDDQ[6]
VDDQ[7]
AL38 C321 C329 C351 C348 C328 C312 C318 C320 C349 C316 1*330uF,8*10uF(0603) ,10*1uF(0402)
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
AE46 AL42 1
VAXG[22] VDDQ[8]
N45
VAXG[23] VDDQ[9]
AM33
PD0.8
1
p.
P47 AM36 + C286
P48 VAXG[24] VDDQ[10] AM40 330U_D2_2V_Y
P50 VAXG[25] VDDQ[11] AN30
2
P51 VAXG[26] VDDQ[12] AN34 2
P52 VAXG[27] VDDQ[13] AN38
P53 VAXG[28] VDDQ[14] AR26 @ @ @ @ @ @ @ @ @ @
DDR3
P55 VAXG[29] VDDQ[15] AR28
om
GRAPHICS
P56 VAXG[30] VDDQ[16] AR30
P61 VAXG[31] VDDQ[17] AR32
Place BOT OUT BGA
T48 VAXG[32] VDDQ[18] AR34
T58 VAXG[33] VDDQ[19] AR36
T59 VAXG[34] VDDQ[20] AR40 C340 C337 C338 C296 C295 C299 C339 C298
VAXG[35] VDDQ[21]
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
T61 AV41 SGA20331E10 S POLY C 330U
VAXG[36] VDDQ[22]
1
U46 AW26
V47 VAXG[37] VDDQ[23] BA40 2V Y D2 LESR9M EEFSX H1.9
V48 VAXG[38] VDDQ[24] BB28
2
V50 VAXG[39] VDDQ[25] BG33
yc
V51 VAXG[40] VDDQ[26]
V52 VAXG[41]
V53 VAXG[42]
V55 VAXG[43]
V56 VAXG[44]
V58 VAXG[45]
V59 VAXG[46]
VAXG[47]
m
W50
W51 VAXG[48]
W52 VAXG[49]
CR CheckList Rev1.5 W53 VAXG[50]
W55 VAXG[51]
W56 VAXG[52]
W61 VAXG[53]
3
1*330uF,2*1uF(0402) R308
1 R87 2 3
PD0.8 100_0402_5%
100_0402_1%
+1.5V_CPU_VDDQ
2
QUIET RAILS
1
C150 2 1 0.1U_0402_10V7K
1
C317
R309 1U_0402_6.3V6K
2
C151 2 1 0.1U_0402_10V7K
1.2A
tt
100_0402_5%
1.8V RAIL
2
C633
10U_0603_6.3V6M
C153
1U_0402_6.3V6K
C281
1U_0402_6.3V6K
C280
1 1
1
BC43
VDDQ_SENSE BA43
2
VSS_SENSE_VDDQ
SENSE LINES
2 2
6A L17
L21 VCCSA[1]
N16 VCCSA[2]
N20 VCCSA[3]
N22 VCCSA[4]
SA RAIL
P17 VCCSA[5]
+VCCSA P20 VCCSA[6] U10
VCCSA ULV
Place TOP IN BGA R16 VCCSA[7] VCCSA_SENSE +VCCSA_SENSE [48]
+VCCSA R18 VCCSA[8] CPU EDS1.3 P.93 VID0 VID1 Vout HR CR
VCCSA[9] VCCSA_VID0 Must PD
1
R21 0 0 0.9V V V
C309 C302 C300 C301 C308 U15 VCCSA[10]
VCCSA VID
1 VCCSA[11]
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2 W20 VCCSA[15]
2V Y D2 LESR9M EEFSX H1.9 VCCSA[16] 1 1 0.75V X V
@
B phase Cost down proposal H_VCCSA_VID0
@ @ @ @ @
4
H_VCCSA_VID1 H_VCCSA_VID0 [48] 4
IVY-BRIDGE_BGA1023
H_VCCSA_VID1 [48]
Place BOT OUT BGA @
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1*330uF,5*10uF(0603) ,5*1uF(0402)
1
PD0.8
2
UCPU1H
UCPU1I
A13 AM38
A17 VSS[1] VSS[91] AM4
A21 VSS[2] VSS[92] AM42 BG17 M4
A25 VSS[3] VSS[93] AM45 BG21 VSS[181] VSS[250] M58
A28 VSS[4] VSS[94] AM48 BG24 VSS[182] VSS[251] M6
A33 VSS[5] VSS[95] AM58 BG28 VSS[183] VSS[252] N1
A37 VSS[6] VSS[96] AN1 BG37 VSS[184] VSS[253] N17
1 1
A40 VSS[7] VSS[97] AN21 BG41 VSS[185] VSS[254] N21
A45 VSS[8] VSS[98] AN25 BG45 VSS[186] VSS[255] N25
A49 VSS[9] VSS[99] AN28 BG49 VSS[187] VSS[256] N28
A53 VSS[10] VSS[100] AN33 BG53 VSS[188] VSS[257] N33
A9 VSS[11] VSS[101] AN36 BG9 VSS[189] VSS[258] N36
AA1 VSS[12] VSS[102] AN40 C29 VSS[190] VSS[259] N40
AA13 VSS[13] VSS[103] AN43 C35 VSS[191] VSS[260] N43
AA50 VSS[14] VSS[104] AN47 C40 VSS[192] VSS[261] N47
AA51 VSS[15] VSS[105] AN50 D10 VSS[193] VSS[262] N48
AA52 VSS[16] VSS[106] AN54 D14 VSS[194] VSS[263] N51
AA53 VSS[17] VSS[107] AP10 D18 VSS[195] VSS[264] N52
AA55 VSS[18] VSS[108] AP51 D22 VSS[196] VSS[265] N56
AA56 VSS[19] VSS[109] AP55 D26 VSS[197] VSS[266] N61
AA8 VSS[20] VSS[110] AP7 D29 VSS[198] VSS[267] P14
AB16 VSS[21] VSS[111] AR13 D35 VSS[199] VSS[268] P16
AB18 VSS[22] VSS[112] AR17 D4 VSS[200] VSS[269] P18
AB21 VSS[23] VSS[113] AR21 D40 VSS[201] VSS[270] P21
VSS[24] VSS[114] VSS[202] VSS[271]
/
AB48 AR41 D43 P58
AB61
AC10
VSS[25]
VSS[26]
VSS[115]
VSS[116]
AR48
AR61
D46
D50
VSS[203]
VSS[204] VSS VSS[272]
VSS[273]
P59
P9
/x
AC14 VSS[27] VSS[117] AR7 D54 VSS[205] VSS[274] R17
AC46 VSS[28] VSS[118] AT14 D58 VSS[206] VSS[275] R20
AC6 VSS[29] VSS[119] AT19 D6 VSS[207] VSS[276] R4
AD17 VSS[30] VSS[120] AT36 E25 VSS[208] VSS[277] R46
AD20 VSS[31] VSS[121] AT4 E29 VSS[209] VSS[278] T1
VSS[32] VSS[122] VSS[210] VSS[279]
su
AD4 AT45 E3 T47
2 AD61
AE13
VSS[33]
VSS[34]
VSS[35]
VSS VSS[123]
VSS[124]
VSS[125]
AT52
AT58
E35
E40
VSS[211]
VSS[212]
VSS[213]
VSS[280]
VSS[281]
VSS[282]
T50
T51
2
p.
AF21 VSS[38] VSS[128] AU32 F29 VSS[216] VSS[285] T56
AF47 VSS[39] VSS[129] AU51 F35 VSS[217] VSS[286] U13
AF48 VSS[40] VSS[130] AU7 F40 VSS[218] VSS[287] U8
AF50 VSS[41] VSS[131] AV17 F55 VSS[219] VSS[288] V20
om
AF51 VSS[42] VSS[132] AV21 G51 VSS[220] VSS[289] V61
AF52 VSS[43] VSS[133] AV22 G6 VSS[221] VSS[290] W13
AF53 VSS[44] VSS[134] AV34 G61 VSS[222] VSS[291] W15
AF55 VSS[45] VSS[135] AV40 H10 VSS[223] VSS[292] W18
AF56 VSS[46] VSS[136] AV48 H14 VSS[224] VSS[293] W21
AF58 VSS[47] VSS[137] AV55 H17 VSS[225] VSS[294] W46
AF59 VSS[48] VSS[138] AW13 H21 VSS[226] VSS[295] W8
yc
AG10 VSS[49] VSS[139] AW43 H4 VSS[227] VSS[296] Y4
AG14 VSS[50] VSS[140] AW61 H53 VSS[228] VSS[297] Y47
AG18 VSS[51] VSS[141] AW7 H58 VSS[229] VSS[298] Y58
AG47 VSS[52] VSS[142] AY14 J1 VSS[230] VSS[299] Y59
AG52 VSS[53] VSS[143] AY19 J49 VSS[231] VSS[300] G48
m
AG61 VSS[54] VSS[144] AY30 J55 VSS[232] VSS[301]
AG7 VSS[55] VSS[145] AY36 K11 VSS[233]
AH4 VSS[56] VSS[146] AY4 K21 VSS[234]
AH58 VSS[57] VSS[147] AY41 K51 VSS[235]
AJ13 VSS[58]
VSS[59]
VSS[148]
VSS[149]
AY45 K8 VSS[236]
VSS[237]
// VSS_NCTF_1
A5
AJ16 AY49 L16 A57
3 VSS[60] VSS[150] VSS[238] VSS_NCTF_2 3
AJ20 AY55 L20 BC61
AJ22 VSS[61] VSS[151] AY58 L22 VSS[239] VSS_NCTF_3 BD3
AJ26 VSS[62] VSS[152] AY9 L26 VSS[240] VSS_NCTF_4 BD59
VSS[63] VSS[153] VSS[241] VSS_NCTF_5
p:
+1.5V
+VREF_DQ_DIMMA +1.5V +1.5V
JDIMM1
1
+VREF_DQ_DIMMA 1 2
R223 3 VREF_DQ VSS 4 DDR_A_D4
1K_0402_1% DDR_A_D0 5 VSS DQ4 6 DDR_A_D5
DDR_A_D1 7 DQ0 DQ5 8
9 DQ1 VSS 10 DDR_A_DQS#0
2
DDR_A0_DM0 11 VSS DQS0# 12 DDR_A_DQS0
13 DM0 DQS0 14
1
VSS VSS
0.1U_0402_16V4Z
C221
1 DDR_A_D2 15 16 DDR_A_D6
DQ2 DQ6
1
2.2U_0402_6.3V6M
C222
All VREF traces should DDR_A_D3 17 18 DDR_A_D7
R226 19 DQ3 DQ7 20
have 10 mil trace width 1K_0402_1% DDR_A_D8 21 VSS VSS 22 DDR_A_D12
1 1
2
2 DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
2
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS VSS 28 DDR_A0_DM1
DDR_A_DQS1 29 DQS1# DM1 30 DIMM_DRAMRST#
DQS1 RESET# DIMM_DRAMRST# [7]
31 32
DDR_A_DQS#[0..7] [7] VSS VSS
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15
DDR_A_DQS[0..7] [7] DQ11 DQ15
37 38
DDR_A_D16 39 VSS VSS 40 DDR_A_D20
DDR_A_D[0..63] [7] DQ16 DQ20
DDR_A_D17 41 42 DDR_A_D21
43 DQ17 DQ21 44
DDR_A_MA[0..15] [7] VSS VSS
DDR_A_DQS#2 45 46 DDR_A0_DM2
DDR_A_DQS2 47 DQS2# DM2 48
49 DQS2 VSS 50 DDR_A_D22
DDR_A_D18 51 VSS DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54
Layout Note: 55 DQ19 VSS 56 DDR_A_D28
Place near JDIMM1 DDR_A_D24 57 VSS DQ28 58 DDR_A_D29
+1.5V DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS 62 DDR_A_DQS#3
DDR_A0_DM3 63 VSS DQS3# 64 DDR_A_DQS3
65 DM3 DQS3 66
/
VSS VSS
1U_0402_6.3V6K
C294
1U_0402_6.3V6K
C326
1U_0402_6.3V6K
C291
1U_0402_6.3V6K
C310
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
1 1 1 1 DQ27 DQ31
71 72
/x
VSS VSS
2 2 2 2 DDRA_CKE0_DIMMA 73 74 DDRA_CKE1_DIMMA
[7] DDRA_CKE0_DIMMA CKE0 CKE1 DDRA_CKE1_DIMMA [7]
75 76
77 VDD VDD 78 DDR_A_MA15
DDR_A_BS2 79 NC A15 80 DDR_A_MA14
[7] DDR_A_BS2 BA2 A14
81 82
su
DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11
2 DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7 2
+1.5V 87 A9 A7 88
DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
p.
VDD VDD
10U_0603_6.3V6M
C287
10U_0603_6.3V6M
C284
10U_0603_6.3V6M
C314
10U_0603_6.3V6M
C289
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
1 1 1 1 A1 A0
99 100
SA_CLK_DDR0 101 VDD VDD 102 SA_CLK_DDR1
[7] SA_CLK_DDR0 CK0 CK1 SA_CLK_DDR1 [7]
[7] SA_CLK_DDR#0 SA_CLK_DDR#0 103 104 SA_CLK_DDR#1 SA_CLK_DDR#1 [7]
CK0# CK1#
om
2 2 2 2 105 106 +1.5V
DDR_A_MA10 107 VDD VDD 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 [7]
[7] DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS# DDR_A_RAS# [7]
111 BA0 RAS# 112
VDD VDD
1
[7] DDR_A_WE# DDR_A_WE# 113 114 DDRA_CS0_DIMMA# DDRA_CS0_DIMMA# [7]
DDR_A_CAS# 115 WE# S0# 116 SA_ODT0 R265
[7] DDR_A_CAS# CAS# ODT0 SA_ODT0 [7]
117 118 1K_0402_1%
DDR_A_MA13 119 VDD VDD 120 SA_ODT1
+1.5V A13 ODT1 SA_ODT1 [7]
DDRA_CS1_DIMMA# 121 122
yc
[7] DDRA_CS1_DIMMA#
2
123 S1# NC 124
125 VDD VDD 126 +VREF_CA
127 TEST VREF_CA 128
VSS VSS
10U_0603_6.3V6M
C303
10U_0603_6.3V6M
C293
10U_0603_6.3V6M
C343
1
DQ32 DQ36
220U_B2_2.5VM_R35
C311
0.1U_0402_16V4Z
C353
1 1 1 DDR_A_D33 131 132 DDR_A_D37
+ 133 DQ33 DQ37 134 R269
m
VSS VSS 1
1
2.2U_0402_6.3V6M
C354
@ DDR_A_DQS#4 135 136 DDR_A0_DM4 1K_0402_1%
@ DDR_A_DQS4 137 DQS4# DM4 138
2 2 2 2 139 DQS4 VSS 140 DDR_A_D38
2
DDR_A_D34 141 VSS DQ38 142 DDR_A_D39 2
DDR_A_D35 143 DQ34 DQ39 144
DDR_A_D40
145
147
DQ35
VSS
// VSS
DQ44
146
148
DDR_A_D44
DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
3 151 DQ41 VSS 152 DDR_A_DQS#5 3
DDR_A0_DM5 153 VSS DQS5# 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D42 157 VSS VSS 158 DDR_A_D46
p:
1U_0402_6.3V6K
C412
1U_0402_6.3V6K
C413
1U_0402_6.3V6K
C414
167 168
tt
DDR_A_D51
179 DQ51 VSS 180 DDR_A_D60
DDR_A_D56 181 VSS DQ60 182 DDR_A_D61
DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_A_DQS#7
DDR_A0_DM7 187 VSS DQS7# 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D58 191 VSS VSS 192 DDR_A_D62
Layout Note: DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
Place near JDIMM1.203,204 195 DQ59 DQ63 196
197 VSS VSS 198
199 SA0 EVENT# 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 [14,31,38]
201 202 SMB_CLK_S3
SA1 SCL SMB_CLK_S3 [14,31,38]
DDR_A0_DM0 +0.75VS 203 204 +0.75VS
DDR_A0_DM1 VTT VTT
2.2U_0402_6.3V6M
C409
0.1U_0402_16V4Z
C408
10K_0402_5%
R331
ME@
DIMM_1 Standard H:4.0mm
<Address: SA1:SA0=00>
1
1
R501
+RTCBATT C439 @ 0_0603_5%
1U_0402_6.3V6K U13A
2
PCH_RTCX1 A20 C38 LPC_AD0
1 2 RTCX1 FWH0 / LAD0 A38 LPC_AD0 [31,37]
PCH_RTCRST# LPC_AD1
LPC
FWH1 / LAD1 LPC_AD1 [31,37]
R356 20K_0402_5% PCH_RTCX2 C20 B37 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD2 [31,37] +3VS
1 2 PCH_SRTCRST# C37 LPC_AD3
FWH3 / LAD3 LPC_AD3 [31,37]
R357 20K_0402_5% PCH_RTCRST# D20
RTCRST#
1
D36 LPC_FRAME# SERIRQ R118 2 1 10K_0402_5%
FWH4 / LFRAME# LPC_FRAME# [31,37]
1
RTC
1U_0402_6.3V6K SM_INTRUDER# K22 LDRQ0# K36
Prevent back drive issue.
2
2
G
Q3 HDA_BITCLK_PCH N34 AM1
HDA_BCLK SATA0RXP SATA_PRX_DTX_C_P0 [31]
SATA 6G
BSS138_NL_SOT23-3 AP7 SATA_PTX_DRX_C_N0 2 1 C1185 0.01U_0402_16V7K SSD
+RTCBATT 3 1 L34 SATA0TXN AP5 2 1 C1208 0.01U_0402_16V7K SATA_PTX_DRX_N0 [31]
HDA_SYNC_PCH_R HDA_SYNC_PCH SATA_PTX_DRX_C_P0
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 [31]
D
R358 1 2 1M_0402_5% SM_INTRUDER# HDA_SPKR T10 AM10 SATA_DTX_C_R_PRX_N1 R148 HDD1@ 2 1 0_0402_5% SATA_DTX_C_PRX_N1 [35]
[36] HDA_SPKR SPKR SATA1RXN
R48 AM8 SATA_DTX_C_R_PRX_P1 R149 HDD1@ 2 1 0_0402_5% HDD0 w/ HM77
SATA1RXP SATA_DTX_C_PRX_P1 [35]
R355 1 2 330K_0402_5% PCH_INTVRMEN 1 2 HDA_RST_PCH# K34 AP11 SATA_PTX_DRX_N1 R150 HDD1@ 2 1 HDD1@ 2
0_0402_5% SATA_PTX_R_DRX_N1_CO 1 C1209 0.01U_0402_16V7K
HDA_RST# SATA1TXN AP10 2 1 SATA_PTX_R_DRX_N1 [35]
Disable w/ HM70
@ 0_0402_5% SATA_PTX_DRX_P1 R151 HDD1@ HDD1@ 2
0_0402_5% SATA_PTX_R_DRX_P1_CO 1 C1223 0.01U_0402_16V7K
INTVRMEN SATA_PTX_R_DRX_P1 [35]
1
H R29 HDA_SDIN0 E34 AD7 SATA_DTX_C_R_PRX_N2 R154 HDD2@ 2 1 0_0402_5% SATA_DTX_C_PRX_N1
* [36] HDA_SDIN0
2
C34 SATA2TXP
(INTVRMEN should always be pull high.)
/
IHDA
HDA_SDIN2 AB8
A34 SATA3RXN AB10
+3VS HDA_SDIN3 SATA3RXP AF3
SATA3TXN Disable w/ HM70
/x
AF1
R109 1 @ 2 1K_0402_5% HDA_SPKR HDA_SDOUT_PCH A36 SATA3TXP
SATA
HDA_SDO Y7
HIGH= Enable ( No Reboot)Disable TCO timer system reboot feature SATA4RXN Y5
R162 1 @ 2 1K_0402_1% PCH_GPIO33 C36 SATA4RXP AD3
* LOW= Disable (Default internal PD) HDA_DOCK_EN# / GPIO33 SATA4TXN AD1
R341 2 1 10K_0402_5% PCH_GPIO13 N32 SATA4TXP
su
+3V_PCH +3V_PCH HDA_DOCK_RST# / GPIO13
R46 Y3
2
1K_0402_5% R100 SATA5RXN Y1 2
@ SATA5RXP
2 @ 1 HDA_SDOUT_PCH 51_0402_5% AB3
R73 2 1 PCH_JTAG_TCK J3 SATA5TXN AB1
0_0402_5% JTAG_TCK SATA5TXP
2 1 PCH_JTAG_TMS H7 Y11 +1.05VS_VTT
L=500mil S=15mil
JTAG
[37] ME_FLASH
p.
JTAG_TMS SATAICOMPO
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
HDA_SDO JTAG_TDI SATAICOMPI R121 37.4_0402_1%
ME debug mode,this signal has a weak internal PD PCH_JTAG_TDO H1
JTAG_TDO AB12 +1.05VS_VTT
* Low = Disabled (Default) SATA3RCOMPO L=500mil S=15mil
om
High = Enabled [Flash Descriptor Security Overide] +3VS
AB13 SATA3_COMP 1 2 GPIO19 has internal Pull up
SATA3COMPI R126 49.9_0402_1%
+3V_PCH GPIO21 Debug Port DG 1.2 PH 4.7K +3VS
SPI_CLK_PCH_R T3 AH1 RBIAS_SATA3 1 2
R47 2 1 1K_0402_5% HDA_SYNC_PCH SPI_CLK SATA3RBIAS R440 750_0402_1%
This signal has a weak internal pull-down SPI_SB_CS0# Y14
SPI_CS0#
SPI_SB_CS1# T1 BBS_BIT0_R R466 2 1 10K_0402_5%
yc SPI
SPI_CS1# P3 PCH_SATALED#
On Die PLL VR Select is supplied by SATALED# PCH_SATALED# R429 2 1 10K_0402_5%
SPI_SI V4 V14 PCH_GPIO21
*1.5V when sampled high SPI_MOSI SATA0GP / GPIO21 No use PH 10K +3VS PCH_GPIO21 R136 2 1 10K_0402_5%
1.8V when sampled low SPI_SO_R U3 P1 BBS_BIT0_R
SPI_MISO SATA1GP / GPIO19
m
Needs to be pulled High for Huron River platfrom
PANTHER_FCBGA989 Boot BIOS Strap
<BOM Structure>
R75
33_0402_5%
1 2 HDA_BITCLK_PCH
Boot BIOS GPIO51 GPIO19
33_0402_5%
1 2 HDA_RST_PCH#
- 1 0
[36] HDA_RST_AUDIO#
p:
R72
33_0402_5% * SPI 1 1
1 2 HDA_SDOUT_PCH +3VS +3VS
[36] HDA_SDOUT_AUDIO
R172
R266 1 2 SPI_WP#1
tt
0_0402_5% U46
+3V_PCH +3V_PCH +3V_PCH 3.3K_0402_5% SPI_SB_CS1# 2 1 CS1# 1 8 0_0402_5%
SPI_SO_R 1 2 SPI_SO1 2 CS# VCC 7 SPI_HOLD#1 R199
R221 1 2SPI_HOLD#1 SPI_WP#1 3 SO HOLD# 6 SPI_CLK1 1 2 SPI_CLK_PCH_R
WP# SCLK Reserve for EMI
1
C191
1 2
PCH_RTCX1 R173
0_0402_5% U44 0.1U_0402_16V4Z
1 2 PCH_RTCX2 SPI_SB_CS0#2 1 CS# 1 8 0_0402_5%
R406 10M_0402_5% SPI_SO_R 1 2 SPI_SO_L 2 CS# VCC 7 SPI_HOLD# R168
SPI_WP# 3 SO HOLD# 6 SPI_CLK_PCH 1 2 SPI_CLK_PCH_R
4 33_0402_5% 4 WP# SCLK 5 SPI_SI_R 1 2 SPI_SI 4
Y2
1 2 R169 GND SI R170
32M W25Q32BVSSIG SOIC 8P 33_0402_5%
32.768KHZ_12.5PF_9H03200019
18P_0402_50V8J
1 1
C451
C452 18P_0402_50V8J
Security Classification Compal Secret Data Compal Electronics, Inc.
2011/06/24 2012/07/12 Title
2 2 Issued Date Deciphered Date PCH (1/9) SATA,HDA,SPI, LPC, XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 13 of 55
A B C D E
A B C D E
U13B +3V_PCH
PCIE_DTX_C_PRX_N1 BG34
No use PH 10K +3VALW PCH_GPIO11 1 2
[32] PCIE_DTX_C_PRX_N1 R33 10K_0402_5%
PCIE_DTX_C_PRX_P1 BJ34 PERN1 E12 PCH_GPIO11
[32] PCIE_DTX_C_PRX_P1 PERP1 SMBALERT# / GPIO11 EC LID SW OUT
PCIE LAN C480 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N1 AV32
[32] PCIE_PTX_C_DRX_N1 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P1 AU32 PETN1 H14 PCH_SMBCLK PCH_SMBCLK 1 2
C478 DDR,WLAN,XDPSMBUS R405 2.2K_0402_5%
[32] PCIE_PTX_C_DRX_P1 PETP1 SMBCLK
PH 2.2K +3VALW
PCIE_PRX_DTX_N2 BE34 C9 PCH_SMBDATA PCH_SMBDATA R370 1 2 2.2K_0402_5%
[31] PCIE_PRX_DTX_N2 PERN2 SMBDATA
PCIE_PRX_DTX_P2 BF34
[31] PCIE_PRX_DTX_P2 PERP2
WLAN C482 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N2 BB32
[31] PCIE_PTX_C_DRX_N2 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P2 AY32 PETN2 DRAMRST_CNTRL_PCH 1 2
C481 R391 1K_0402_5%
SMBUS
[31] PCIE_PTX_C_DRX_P2 PETP2 A12 DRAMRST_CNTRL_PCH
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH [7]
BG36 PCH_HOT# R392 1 2 10K_0402_5%
BJ36 PERN3 C8 PCH_SML0CLK
1 +3VS AV34 PERP3 SML0CLK S3 reduse No use PH 10K +3VALW 1
AU34 PETN3 G12 PCH_SML0DATA PCH_SML1CLK R403 1 2 2.2K_0402_5%
R424 2 1 10K_0402_5% WLAN_CLKREQ#_R PETP3 SML0DATA
BF36 PCH_SML1DATA R369 1 2 2.2K_0402_5%
R110 2 1 10K_0402_5% PCH_GPIO20 BE36 PERN4
AY34 PERP4 C13 PCH_HOT# UMA@
+3V_PCH BB34 PETN4 SML1ALERT# / PCHHOT# / GPIO74 PCH_HOT# [37] No use PH 10K +3VALW PEG_CLKREQ#_R 1 2
R25 10K_0402_5%
PETP4 E14 PCH_SML1CLK EC-PCH SMBUS
PCI-E*
R414 2 1 10K_0402_5% PCH_GPIO25 BG37 SML1CLK / GPIO58
BH37 PERN5 M16 PCH_SML1DATA
2 1 10K_0402_5% LAN_CLKREQ#_R AY36 PERP5 SML1DATA / GPIO75 PH 2.2K +3VALW +3VS
R389 HM70 not support For DDR
BB36 PETN5
R53 2 1 10K_0402_5% PCH_GPIO26 PCIE port 4-7 PETP5 R404
BJ38 2.2K_0402_5%
PERN6
2
R50 2 1 10K_0402_5% PCH_GPIO44 BG38 1 2
+3VS
Controller
AU36 PERP6 M7
R32 2 1 10K_0402_5% PCH_GPIO45 AV36 PETN6 CL_CLK1 PCH_SMBDATA 6 1 SMB_DATA_S3
PETP6 SMB_DATA_S3 [12,31,38]
Link
R51 2 1 10K_0402_5% PCH_GPIO46 BG40 T11 Q34A
BJ40 PERN7 CL_DATA1 DMN66D0LDW-7_SOT363-6 R371
R54 2 1 10K_0402_5% PCH_GPIO56 AY40 PERP7 @ 2.2K_0402_5%
/
PETN7
5
BB40 P10 2 R9 1 1 2
PETP7 CL_RST1# PEG_CLKREQ# [23] +3VS
0_0402_5%
BE38 PCH_SMBCLK 3 4 SMB_CLK_S3
SMB_CLK_S3 [12,31,38]
/x
BC38 PERN8
AW 38 PERP8 Q34B
AY38 PETN8 No use PH 10K +3VALW
DMN66D0LDW-7_SOT363-6
PETP8 PX@
M10 PEG_CLKREQ#_R R56 1 210K_0402_5% +3VS
1 2 0_0402_5% CLK_PCIE_LAN#_R Y40 PEG_A_CLKRQ# / GPIO47 Pull up at EC side.
R153
[32] CLK_PCIE_LAN# CLKOUT_PCIE0N For VGA,EC,Thermal sensor
su
PCIE LAN R163 1 2 0_0402_5% CLK_PCIE_LAN_R Y39 R58 PX@0_0402_5%
[32] CLK_PCIE_LAN CLKOUT_PCIE0P AB37 2 1 CLK_PCIE_VGA#
2 CLK_PCIE_VGA#_R CLK_PCIE_VGA# [22] 2
CLOCKS
CLKOUT_PEG_A_N
2
No use PH 10K +3VALW R164 1 2 0_0402_5% LAN_CLKREQ#_R J2 AB38 CLK_PCIE_VGA_R 2 1 CLK_PCIE_VGA
[32] LAN_CLKREQ# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA [22]
R59 PX@0_0402_5%
PCH_SML1DATA 6 1 EC_SMB_DA2 EC_SMB_DA2 [23,34,37]
R165 1 2 0_0402_5% CLK_PCIE_WLAN1#_R AB49 AV22 CLK_CPU_DMI#
[31] CLK_PCIE_WLAN1# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# [6]
p.
R166 1 2 0_0402_5% CLK_PCIE_WLAN1_R AB47 AU22 CLK_CPU_DMI Q33A
[31] CLK_PCIE_WLAN1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI [6]
WLAN DMN66D0LDW-7_SOT363-6
5
R167 1 2 0_0402_5% WLAN_CLKREQ#_R M1
[31] WLAN_CLKREQ# PCIECLKRQ1# / GPIO18
No use PH 10K +3VS AM12
CLKOUT_DP_N / CLKOUT_BCLK1_N AM13 PCH_SML1CLK 3 4 EC_SMB_CK2
CLKOUT_DP_P / CLKOUT_BCLK1_P EC_SMB_CK2 [23,34,37]
om
AA48
AA47 CLKOUT_PCIE2N Q33B
CLKOUT_PCIE2P BF18 CLK_BUF_CPU_DMI# R152 1 2 10K_0402_5% DMN66D0LDW-7_SOT363-6
PCH_GPIO20 V10 CLKIN_DMI_N BE18 CLK_BUF_CPU_DMI R147 1 2 10K_0402_5%
No use PH 10K +3VS PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
yc
No use PH 10K +3VALW PCH_GPIO25 A8
PCIECLKRQ3# / GPIO25 G24 CLK_BUF_DREF_96M# R99 1 2 10K_0402_5%
CLKIN_DOT_96N E24 CLK_BUF_DREF_96M R93 1 2 10K_0402_5%
CLKIN_DOT_96P Pull down 10K ohm
2
Y43
Y45 CLKOUT_PCIE4N for using internal Clock R551 R545
CLKOUT_PCIE4P
m
AK7 CLK_BUF_PCIE_SATA# R139 1 2 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
PCH_GPIO26 L12 CLKIN_SATA_N / CKSSCD_N AK5 CLK_BUF_PCIE_SATA R138 1 2 10K_0402_5%
No use PH 10K +3VALW PCIECLKRQ4# / GPIO26 CLKIN_SATA_P / CKSSCD_P
1
PCH_SML0CLK
V45 K45 CLK_BUF_ICH_14M R101 1 2 10K_0402_5%
CLKOUT_PCIE5N REFCLK14IN
V46
//
CLKOUT_PCIE5P
PCH_SML0DATA
V42 CLKOUT_PCIE6N
CLKOUT_PCIE6P +3VS
No use PH 10K +3VALW PCH_GPIO45 T13
PCIECLKRQ6# / GPIO45
h
1
V38 K43
V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 R421 XTAL25_IN
FLEX CLOCKS
2
PCIE_CLK_8N AK14 CLKOUTFLEX2 / GPIO66 DGPU_PRSNT#
PCIE_CLK_8P AK13 CLKOUT_BCLK0_N / CLKOUT_PCIE8N K49 DGPU_PRSNT# 3 4
CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX3 / GPIO67 OSC NC
2
R420 2 1
PANTHER_FCBGA989 PX@ 10K_0402_5% NC OSC
1 Y3 1
<BOM Structure> 25MHZ_10PF_7V25000014
1
C457 C468
10P_0402_50V8J 10P_0402_50V8J
2 2
GPIO67
DGPU_PRSNT#
4 4
DIS,Optimus 0
UMA 1
U13C
:
[5] DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 BJ20 DSWODVREN - On Die DSW VR Enable
+3V_PCH DMI3RXP BG14 FDI_CTX_PRX_P0
FDI_RXP0 FDI_CTX_PRX_P0 [5]
* H Enable internal DSW +1.05VS
:
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 FDI_CTX_PRX_P1 [5]
1 [5] DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 1
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 FDI_CTX_PRX_P2 [5] L Disable
[5] DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2
R34 2 1 10K_0402_5% SUSWARN#_R DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 [5] Must always PH at +RTCVCC
[5] DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 FDI_CTX_PRX_P4 [5]
DMI
FDI
[5] DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4
R49 2 1 10K_0402_5% PCH_GPIO72 BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 [5]
DMI_CRX_PTX_P0 AY24 FDI_RXP5 BJ10 FDI_CTX_PRX_P6
[5] DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 [5] +3V_PCH
R390 2 1 10K_0402_5% RI# DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 [5]
[5] DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7
DMI_CRX_PTX_P2 AY18
[5] DMI_CRX_PTX_P2 DMI2TXP
DMI_CRX_PTX_P3 AU18 PCH_PCIE_WAKE# R374 1 2 10K_0402_5%
[5] DMI_CRX_PTX_P3 DMI3TXP
R393 2 1 300_0402_5% PM_DRAM_PWRGD AW16 FDI_INT
FDI_INT FDI_INT [5]
Follow G +1.05VS_VTT BJ24 AV12 FDI_FSYNC0 PCH_GPIO29 R36 1 @ 2 10K_0402_5%
R394 2 1 10K_0402_5% PCH_RSMRST#
L=500mil S=15mil DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 [5]
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1 +3VS
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 [5]
R156 49.9_0402_1% @
1 2 DMI2RBIAS BH21 AV14 FDI_LSYNC0 CLKRUN# R423 1 2 8.2K_0402_5%
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 [5]
R155 750_0402_1%
+3VS BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 [5]
R397 @ 4mil width and place
/
2 1 200_0402_5% PM_DRAM_PWRGD PCH_DPWROK 2 R135 10_0402_5%
within 500mil of the PCH For DS3 DS3@
DPWROK_EC [37]
A18 DSWODVREN
For DS3
/x
DSWVRMEN
not support Deep S4,S5 not support Deep S4,S5 DPWROK mux with RSMRST#
su
PCH_PCIE_WAKE# PCH_PCIE_WAKE# [31,32]
R415 10K_0402_5% SYS_RESET# WAKE#
2 2
1
p.
with PWROK (check list1.5 P.47) PCH_PWROK 1 2 PCH_PWROK_R L22 G8 SUS_STAT# T1@ PAD R375
R107 0_0402_5% PWROK SUS_STAT# / GPIO61
10K_0402_5%
R303 1 @ 2 0_0402_5% APWROK L10 N14 SUSCLK 0111 Add R375 to GND
[37] PCH_APWROK SUSCLK [37]
2
APWROK SUSCLK / GPIO62
om
PCH_PWROK_R 2 1 APWROK
R191 0_0402_5%
PM_DRAM_PWRGD B13 D10 PM_SLP_S5#
[6] PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# [37]
AEPWROK can be connect to
PWROK if iAMT disable
[37] EC_RSMRST# 1 2 PCH_RSMRST# C21 H4 PM_SLP_S4#
RSMRST# SLP_S4# PM_SLP_S4# [37]
R125 0_0402_5% Can be left NC
yc
R1489 0_0402_5%
For Deep S3
For DS3 2 1 SUSWARN#_R K16 F4 PM_SLP_S3# when IAMT is not
+3VALW [37] SUSWARN# SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# PM_SLP_S3# [37]
DS3@
support on the
DS3@ [37] PBTN_OUT# 1 2 PBTN_OUT#_R E20 G10 SLP_A# T4@ PAD platfrom
PWRBTN# SLP_A#
m
R195 2 1 200K_0402_5% AC_PRESENT_R R129 0_0402_5%
D3
[23,37,43] ACIN 1 2 AC_PRESENT_R H20 G16 SLP_SUS# not support
ACPRESENT / GPIO31 SLP_SUS# SLP_SUS# [37,40]
RB751V-40_SOD323-2
// For DS3 Deep S4,S5 can NC
No use PH 10K +3VALW PCH_GPIO72 E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC [6] PCH EDS1.5 P.75
3 3
Ring Indicator CRB1.0 PH 10K +3VALW RI# A10 K14 PCH_GPIO29 If Intel LAN no use, can let be NC.
RI# SLP_LAN# / GPIO29
p:
PANTHER_FCBGA989
<BOM Structure>
tt
U36
PCH_PWROK 2
P
MC74VHC1G08DFT2G_SC70-5 1
3
4 4
U13D
PCH_ENBKL J47 AP43 +3VS
[29] PCH_ENBKL L_BKLTEN SDVO_TVCLKINN
M45 AP45
[29] PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
P45 AM42
[29] PCH_PWM L_BKLTCTL SDVO_STALLN
1
AM40
T40 SDVO_STALLP R144 R131
[29] EDID_CLK L_DDC_CLK
K47 AP39 2.2K_0402_5% 2.2K_0402_5%
[29] EDID_DATA L_DDC_DATA SDVO_INTN AP40 HDMI@ HDMI@
CTRL_CLK T45 SDVO_INTP
L=500mil S=20mil
2
+3VS Change to eDP only CTRL_DATA P39 L_CTRL_CLK
1 1
2.37K_0402_1% L_CTRL_DATA
R108 1 2 2.2K_0402_5% CTRL_CLK R132 2 1 LVDS_IBG AF37 P38 HDMICLK_NB
LVD_IBG SDVO_CTRLCLK HDMICLK_NB [30]
AF36 M39 HDMIDAT_NB
LVD_VBG SDVO_CTRLDATA HDMIDAT_NB [30]
R105 1 2 2.2K_0402_5% CTRL_DATA DIS only can NC W=10mil S=30mil LVD_VREF AE48
AE47 LVD_VREFH AT49
UMA LVDS DDC LVD_VREFL DDPB_AUXN AT47
R428 1 2 2.2K_0402_5% EDID_CLK DDPB_AUXP AT40 TMDS_B_HPD#
DDPB_HPD TMDS_B_HPD# [30]
LVDS_ACLK# AK39
LVDS
[29] LVDS_ACLK# LVDSA_CLK#
R425 1 2 2.2K_0402_5% EDID_DATA LVDS_ACLK AK40 AV42 TMDS_B_DATA2#_PCH HDMI@ C406 1 2 0.1U_0402_10V6K
[29] LVDS_ACLK LVDSA_CLK DDPB_0N HDMI_TX2-_CK [30]
AV40 TMDS_B_DATA2_PCH HDMI@ C352 1 2 0.1U_0402_10V6K HDMI D2
DDPB_0P HDMI_TX2+_CK [30]
Check list1.5 P.60 disable Graphics LVDS_A0# AN48 AV45 TMDS_B_DATA1#_PCH HDMI@ C539 1 2 0.1U_0402_10V6K
[29] LVDS_A0# LVDSA_DATA#0 DDPB_1N HDMI_TX1-_CK [30]
AM47 AV46 TMDS_B_DATA1_PCH 1 2
/
DATA/Clock/Control an NC LVDSA_DATA3 DDPC_CTRLCLK P42
DDPC_CTRLDATA
VCC_TX_LVDS,VCCA_LVDS PD to GND Place close to connector side
/x
AF40
AF39 LVDSB_CLK# AP47
2 LVDSB_CLK DDPC_AUXN AP49 2
CRT disable: UM77 not support AH45 DDPC_AUXP AT38
DATA/Clock/Control an NC LVDS/CRT AH47 LVDSB_DATA#0 DDPC_HPD
AF49 LVDSB_DATA#1 AY47
VCCADAC connect to +3VS
su
AF45 LVDSB_DATA#2 DDPC_0N AY49
DAC_IREF connect 1K_0402_5% LVDSB_DATA#3 DDPC_0P AY43
AH43 DDPC_1N AY45
AH49 LVDSB_DATA0 DDPC_1P BA47
AF47 LVDSB_DATA1 DDPC_2N BA48
AF43 LVDSB_DATA2 DDPC_2P BB47
p.
LVDSB_DATA3 DDPC_3N BB49
DDPC_3P
N48 M43
om
P49 CRT_BLUE DDPD_CTRLCLK M36
T49 CRT_GREEN DDPD_CTRLDATA
CRT_RED
AT45
CRT
T39 DDPD_AUXN AT43
M40 CRT_DDC_CLK DDPD_AUXP BH41
CRT_DDC_DATA DDPD_HPD
yc
BB43
M47 DDPD_0N BB45
M49 CRT_HSYNC DDPD_0P BF44
CRT_VSYNC DDPD_1N BE44
3 3
DDPD_1P BF42
DDPD_2N
m
CRT_IREF T43 BE42
T42 DAC_IREF DDPD_2P BJ42
CRT_IRTN DDPD_3N BG42
DDPD_3P
1
R114 PANTHER_FCBGA989
//
1K_0402_5%
<BOM Structure>
CRT disable
2
use 1K_0402_5%
p:
tt
h
4 4
U13E
+3VS AY7
NV_CE#0 AV7
R90 BG26 NV_CE#1 AU3
8 1 PCI_PIRQC# BJ26 TP1 NV_CE#2 BG4
7 2 PCI_PIRQB# BH25 TP2 NV_CE#3
6 3 PCI_PIRQA# BJ16 TP3 AT10
5 4 PCI_PIRQD# BG16 TP4 NV_DQS0 BC8
AH38 TP5 NV_DQS1
8.2K_1206_8P4R_5% AH37 TP6 AU2
1 AK43 TP7 NV_DQ0 / NV_IO0 AT4 1
R409 AK45 TP8 NV_DQ1 / NV_IO1 AT3
8 1 PCH_GPIO2 C18 TP9 NV_DQ2 / NV_IO2 AT1
7 2 PCH_GPIO3 N30 TP10 NV_DQ3 / NV_IO3 AY3
6 3 PCH_GPIO4 H3 TP11 NV_DQ4 / NV_IO4 AT5
5 4 PXS_PWREN_R AH12 TP12 NV_DQ5 / NV_IO5 AV3
NVRAM
AM4 TP13 NV_DQ6 / NV_IO6 AV1
8.2K_1206_8P4R_5% AM5 TP14 NV_DQ7 / NV_IO7 BB1
Y13 TP15 NV_DQ8 / NV_IO8 BA3
R408 1 2 8.2K_0402_5% PCH_GPIO51 K24 TP16 NV_DQ9 / NV_IO9 BB5
L24 TP17 NV_DQ10 / NV_IO10 BB3
R418 1 2 8.2K_0402_5% PCH_WL_OFF# AB46 TP18 NV_DQ11 / NV_IO11 BB7
AB45 TP19 NV_DQ12 / NV_IO12 BE8
RSVD
R432 1 2 8.2K_0402_5% PCH_GPIO53 TP20 NV_DQ13 / NV_IO13 BD4
NV_DQ14 / NV_IO14 BF6
R433 1 2 8.2K_0402_5% PCH_GPIO52 NV_DQ15 / NV_IO15
B21 AV5
R401 1 2 8.2K_0402_5% PCH_GPIO5 M20 TP21 NV_ALE AY1 DF_TVS
AY16 TP22 NV_CLE
BG46 TP23 AV10
DMI,FDI Termination Voltage
+3VS TP24 NV_RCOMP
AT8
Set to Vcc when HIGH HR CPU NC
1 2 NV_RB# DF_TVS
R66 8.2K_0402_5% BE28 AY5
Set to Vss when LOW CR CPU PD
USB3_RX2_N BC30 TP25 NV_RE#_WRB0 BA2
/
[39] USB3_RX2_N TP26 NV_RE#_WRB1
1 2 DGPU_HOLD_RST#_R BE32 CR Check list P.89 PH 2.2K series 1K
R41 @ 8.2K_0402_5% BJ32 TP27 AT12
BC28 TP28 NV_WE#_CK0 BF3
TP29 NV_WE#_CK1
/x
[39] USB3_RX2_P USB3_RX2_P BE30
BF32 TP30 +1.8VS
BG32 TP31 C24
AV26 TP32 USBP0N A24
USB3.0 TP33 USBP0P
1
2 USB3_TX2_N BB26 C25 USB20_N1 2
[39] USB3_TX2_N TP34 USBP1N USB20_N1 [39]
AU28 B25 USB20_P1 USB3 (Left side) R145
TP35 USBP1P USB20_P1 [39]
Boot BIOS Strap AY30 C26 USB20_N2 2.2K_0402_5%
TP36 USBP2N USB20_N2 [31]
su
AU26 A26 USB20_P2 Mini Card (WLAN)
TP37 USBP2P USB20_P2 [31]
USB3_TX2_P AY26 K28
GPIO19 GPIO51 Boot BIOS [39] USB3_TX2_P
2
AV28 TP38 USBP3N H28 DF_TVS 2 1
TP39 USBP3P H_SNB_IVB# [6]
Bit11 Bit10 Destination AW30
TP40 USBP4N
E28
D28
EHCI 1 R146 1K_0402_5%
GNT1#/ USBP4P C28
GPIO51 0 1 Reserved USBP5N A28
CLOSE TO THE BRANCHING POINT
p.
USBP5P C29
1 0 PCI USBP6N B29
HM70 not support USB port 4,5,6,7,12,13
USBP6P
Internal 1 1 SPI PCI_PIRQA# K40 N28
PH
* PCI Interrupt Requests PCI_PIRQB# K38 PIRQA# USBP7N M28
PCI
PCI_PIRQC# H38 PIRQB# USBP7P L30 USB20_N8
0 0 LPC PIRQC# USBP8N USB20_N8 [38]
om
PCI_PIRQD# G38 K30 USB20_P8 USB2 (Right side)
PIRQD# USBP8P USB20_P8 [38]
G30 USB20_N9
USBP9N USB20_N9 [38] +3V_PCH
CR Check list 1.5 only use for GPIO DGPU_HOLD_RST# R55 2 1 0_0402_5% PX5@ DGPU_HOLD_RST#_R C46 E30 USB20_P9 USB2 (Right side)
USB
REQ1# / GPIO50 USBP9P USB20_P9 [38]
PCH_GPIO52 C44 C30 USB20_N10
REQ2# / GPIO52 USBP10N USB20_N10 [38]
No use PH +3VS [24,49] PXS_PWREN
R57 2 1 0_0402_5% PX5@ PXS_PWREN_R E40
REQ3# / GPIO54 USBP10P
A30 USB20_P10
USB20_P10 [38] Card Reader USB_OC0# 2 1
Only GPIO L32 USB20_N11 EHCI 2 R24 10K_0402_5%
USBP11N USB20_N11 [29]
PCH_GPIO51 D47 K32 USB20_P11
無無 如如
function CR Check list 1.5 only use for GPIO PCH_GPIO53 E42 GNT1# / GPIO51 USBP11P G32
USB20_P11 [29] CMOS Camera (LVDS) USB_OC7# 2 1
PH(Internal PH), GPIO PH +3VS PCH_WL_OFF# F46 GNT2# / GPIO53 USBP12N E32 0110 modify WLAN USB port to USB8 R367 10K_0402_5%
[31] PCH_WL_OFF# GNT3# / GPIO55 USBP12P
yc
C32 Port9 is for debug. USB_OC5# 2 1
USBP13N A32 R378 10K_0402_5%
PCH_GPIO2 G42 USBP13P
PCH_GPIO3 G40 PIRQE# / GPIO2 USB_OC6# 2 1
C42 PIRQF# / GPIO3 C33 1 2
GPIO55 PCH_GPIO4
PIRQG# / GPIO4 USBRBIAS#
USBRBIAS R377 10K_0402_5%
PCH_GPIO5 D44 R399 22.6_0402_1%
PCH_WL_OFF# R215 1 @ 2 1K_0402_5% PIRQH# / GPIO5
m
B33 L=500mil S=15mil
3 PCI_PME# K10 USBRBIAS +3V_PCH 3
[37] PCI_PME# PME# R349
A16 swap overide Strap/Top-Block PCH_PLTRST# C6 A14 USB_OC0# USB_OC1# 4 5
[6] PCH_PLTRST# PLTRST# OC0# / GPIO59 K20
USB_OC0# [39] Card reader 3 6
Swap Override jumper USB_OC1# USB_OC4#
PANTHER_FCBGA989
@
R10
0_0402_5%
tt
2 1
+3VS
h
5
U25 @
PCH_PLTRST# 2
P
B 4
Y PLT_RST# [31,32,37]
1
A
G
R11
3
100K_0402_5%
MC74VHC1G08DFT2G_SC70-5
2
4 4
+3VS
5
U29 PX@ R6
2 0_0402_5%
P
B 4 2 1
Y GPU_RST# [22]
DGPU_HOLD_RST# 1
A
G
1
On-Die PLL Voltage Regulator PCH_GPIO70 Function
1
R67 @ R69
::
This signal has a weak internal pull up 10K_0402_5% 10K_0402_5%@ R68
H On-Die PLL voltage regulator enable 0 13/14" 10K_0402_5%
* L On-Die PLL Voltage Regulator disable 1 NA @
2
PCH_GPIO69 PCH_GPIO70
2
PCH_GPIO71 PCH_GPIO71
2
+3V_PCH
2
R42 @ R44
Fan Tachometer Inputs 10K_0402_5% 200K_0402_5% 0 USB3.0 by PCH R43
1
1 200K_0402_5% 1
R411 TACH1~7 only on server 1 USB3.0 by NEC
1
10K_0402_5% can insted to GPIO
1
2
PCH_GPIO28 U13F
2
2
No use PH 10K +3VALW EC_SMI# C10 R106
[37] EC_SMI# GPIO8
10K_0402_5%
Deep S4,S5 wake event signal No use PH +3VALW PCH_GPIO12 C4
LAN_PHY_PWR_CTRL / GPIO12
1
RTC alarm,Power BTN,GPIO27 No use PH +3VALW[37] EC_LID_OUT#
EC_LID_OUT# @1
@ 2 PCH_GPIO15 G2 P4
GATEA20 [37]
R60 0_0402_5% GPIO15 A20GATE
PCH_GPIO27 (Have internal Pull-High)
/
AU16 PCH_PECI_R 1 @ 2
PECI CPU-EC
CPU/MISC
Deep S4,S5 wake event signal mSATA_DET# U2 PECI H_PECI [37,6]
No use PH +3VS [31] mSATA_DET# 0_0402_5% R158
SATA4GP / GPIO16 P5 EC_KBRST#
+3VALW RCIN# KBRST# [37] CTRL+ALT+DEL
No use PH +3VS
/x
For DS3
GPIO
R45 1 2 0_0402_5% VGA_PWRGD_R D40 AY11 non CPU power ok
[22,49] VGA_PWRGD TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD [6]
DS3@
R208 2 1 10K_0402_5% No use PH 10K +3VS Blue Booth BT_DISABLE T5 AY10 PCH_THRMTRIP#_R 1 2 H_THERMTRIP# 130c shut down
[31] BT_DISABLE SCLOCK / GPIO22 THRMTRIP# H_THERMTRIP# [6]
R159 390_0402_5%
No use PH +3VALW DDR3 PCH_GPIO24 E8 T14
R83 1 @ 2 10K_0402_5% PCH_GPIO27 GPIO24 / MEM_LED INIT3_3V#
INIT3_3V Checklist1.5 P.69
su
No use PD 10K to GND EC_LID_OUT# 1 2 PCH_GPIO27 E16
2 R61 0_0402_5% GPIO27 +3VS 2
PCH_GPIO28 P8
This signal has weak internal
No use PH 10K +3VALW GPIO28 AH8 PU, can't pull low,leave NC
PCH_BT_ON# K1 NC_1
No use PH 10K +3VS BT ON/OFF [31] PCH_BT_ON# STP_PCI# / GPIO34 AK11 EC_KBRST# 1 2 10K_0402_5%
R103
NC_2
p.
No use can NC R243 1 2 10K_0402_5% PCH_GPIO35 K4
+3V_PCH GPIO35 AH10 PCH_GPIO68 R400 1 2 10K_0402_5%
PCH_GPIO36 V8 NC_3 TS_VSS1~4
1 2 1K_0402_5% EC_SMI#
Can't PH SATA2GP / GPIO36 AK10 PD to GND
R261 @
PCH_GPIO37 M5 NC_4
Can't PH SATA3GP / GPIO37
om
P37
OPTIMUS_EN# N2 NC_5
No use PH 10K +3VS Optimus(L)/ non optimus(H) SLOAD / GPIO38
SATA2GP/GPIO36 & SATA3GP/GPIO37 PCH_GPIO39 M3
Sampled at Rising edge of PWROK. No use PH 10K +3VS SDATAOUT0 / GPIO39
No use PH 10K +3VS PCH_GPIO48 V13 BG2
Weak internal pull-down. SDATAOUT1 / GPIO48 VSS_NCTF_15
(weak internal pull-down is disabled SATA5GP&TEMP_ALERT# CRB PH 10K +3VS PCH_GPIO49 V3
SATA5GP / GPIO49 VSS_NCTF_16
BG48 9/15 Layout
yc
after PLTRST# de-asserts) PCH_GPIO57 D6 BH3 request remove
No use PH +3VALW GPIO57 VSS_NCTF_17
NOTE: This signal should NOT be Test point
BH47
pulled high when strap is sampled VSS_NCTF_18 They will route
+3VS A4 BJ4
VSS_NCTF_1 VSS_NCTF_19 by itself
m
UMA@ 9/15 Layout A44 BJ44
R427 1 2 10K_0402_5% OPTIMUS_EN# VSS_NCTF_2 VSS_NCTF_20
+3VS request remove A45 BJ45
PX@ VSS_NCTF_3 VSS_NCTF_21
Test point
NCTF
R112 1 2 10K_0402_5% PCH_GPIO0 R426 1 2 10K_0402_5%
//
They will route
A46
VSS_NCTF_4 VSS_NCTF_22
BJ46
VSS_NCTF_7 VSS_NCTF_25
R71 1 2 10K_0402_5% VGA_PWRGD_R
* Muxless 0 B47 C48
VSS_NCTF_8 VSS_NCTF_26
R419 1 2 10K_0402_5% PCH_GPIO39 nonMuxless 1 BD1 D1
VSS_NCTF_9 VSS_NCTF_27
tt
PANTHER_FCBGA989
1
4
GPIO36/GPIO37 is Strap functionality 4
R63 @ 0_0402_5%
1 2 PCH_GPIO24 that requires internal pull down to be sampled at rising PWROK.
[46] DDR3L_EN#
When uses as SATA2GP/SATA3GP for mechanical presence detect
-use a external pull up 150K-200K ohm to Vcc3_3
When used as GP input
GPIO24 Unmultiplexed -ensure GPI is not driven high during strap sampling window
NOTE: GPIO24 configuration When Unused as GPIO or SATA*GP
register bits are not cleared by
Security Classification Compal Secret Data Compal Electronics, Inc.
-use 8.2K-10K pull-down 2011/06/24 2012/07/12 Title
CF9h reset event. check list page 47 Issued Date Deciphered Date PCH (6/9) GPIO, CPU, MISC
CRB1.0 PH10K to +3VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 18 of 55
A B C D E
A B C D E
10U_0603_6.3V6M
C106
1U_0402_6.3V6K
C64
1U_0402_6.3V6K
C67
1U_0402_6.3V6K
C75
CRT
1 1 1 1 AD21 C53 C54 C40
AD23 VCCCORE[3] U47 10U_0603_6.3V6M
AF21 VCCCORE[4] VSSADAC 0.01U_0402_16V7K 0.1U_0402_16V7K
VCC CORE
AF23 VCCCORE[5] 2 2 2
1 2 2 2 2 AG21 VCCCORE[6] +3VS 1
AG23 VCCCORE[7]
AG24 VCCCORE[8] AK36 +VCCA_LVDS 1 2
AG26 VCCCORE[9] VCCALVDS R442
Place Near AA23 AG27 VCCCORE[10] 1mA AK37 0_0603_5%
AG29 VCCCORE[11] VSSALVDS
AJ23 VCCCORE[12]
LVDS
AJ26 VCCCORE[13] AM37
AJ27 VCCCORE[14] VCCTX_LVDS[1]
AJ29 VCCCORE[15] AM38 L27 +1.8VS
AJ31 VCCCORE[16] VCCTX_LVDS[2] 0.1UH_MLF1608DR10KT_10%_1608
VCCCORE[17] AP36
Place Near AM37 +VCCTX_LVDS 2 1
+1.05VS_VTT 60mA VCCTX_LVDS[3] 1 1
1
AP37
AN19 VCCTX_LVDS[4] C91 C92 C108
VCCIO[28] 0.1uH inductor, 200mA
0.01U_0402_16V7K 22U_0603_6.3V6K
2
2 2
PAD T31 @ +VCCAPLLEXP BJ22 +3VS
VCCAPLLEXP 266mA 0.01U_0402_16V7K
On-Die PLL Voltage Regulator V33
HVCMOS
:
AN16 VCC3_3[6]
VCCIO[15] Place Near V33
/
H On-Die PLL voltage regulator AN17
1
enable VCCIO[16] V34
I/O Buffer Voltage
C61
VCC3_3[7]
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
/x
AN21 2925mA 2
0.1U_0402_16V7K
,VCCAPLLSATA VCCIO[17]
PCH Power Rail Table
AN26 +1.5VS
VCCIO[18]
S0 Iccmax
AN27 AT16 Voltage Rail Voltage
VCCIO[19] VCCVRM[3] Current(A)
Internal PLL and VRM(+1.5VS)
su
+1.05VS_VTT AP21 +1.05VS_VTT
2 VCCIO[20] 2
AP23 AT20
V_PROC_IO 1.05 0.001 Processor I/F
VCCIO[21] VCCDMI[1]
1 DMI buffer logic
DMI
10U_0603_6.3V6M
C80
1U_0402_6.3V6K
C87
1U_0402_6.3V6K
C88
1U_0402_6.3V6K
C90
1U_0402_6.3V6K
C86
p.
AP26 AB36
VCCIO[23] VCCIO[1] 2 place
2 2 2 2 2 AT24
V5REF_Sus 5 0.001 Suspend Well Reference Voltag
VCCIO[24] near AT20 Core Well I/O Buffer
Vcc3_3 3.3 0.266 I/O Buffer Voltage
om
AN33
Place Near AN16,AN21,AN33
VCCIO[25] 190mA Display DAC Analog Power. This power is
AN34 AG16 VccADAC 3.3 0.001
+3VS VCCIO[26] VCCPNAND[1] +1.8VS
VccDFTERM should PH +1.8VS or +3VS supplied by the core well.
NAND / SPI
yc
0.1U_0402_16V7K 0.1U_0402_16V7K VccADPLLB 1.05 0.08 Display PLL B power
VCCPNAND[3]
Place Near 2 AP16 2 place
BH29 VCCVRM[2] AJ17
VCCPNAND[4] near AG16 VccCore 1.05 1.3 Internal Logic Voltage
PAD @ +1.05VS_VCCAPLL_FDI BG6
VCCFDIPLL
m
T17 VccDMI 1.05 0.042 DMI Buffer Voltage
+1.05VS_VTT +3VS
AP17
VCCIO[27]
FDI
V1 For SPI control logi VccIO 1.05 2.925 Core Well I/O buffers
VCCSPI
20mA
1
C98
AU20
VCCDMI[2]
// 1
VccASW 1.05 1.01
1.05 V Supply for Intel R Management
1U_0402_6.3V6K C60 Engine and Integrated LAN
3 PANTHER_FCBGA989 1U_0402_6.3V6K 3
2 Near 2
VccSPI 3.3 0.02 3.3 V Supply for SPI Controller Logic
AU20 <BOM Structure>
p:
Trace 20mil VccDSW 3.3 0.003 3.3v supply for Deep S4/S5 well
On-Die PLL Voltage Regulator
:
H On-Die PLL voltage regulator VccpNAND 1.8 0.19 1.8V power supply for DF_TVS
tt
enable
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 VccRTC 3.3 6 uA Battery Voltage
,VCCAPLLSATA
h
+3VS +1.05VS_VTT
+1.05V analog R430 @
VCC3_3 = 266mA detal waiting for newest spec
internal clock PLL 0_0603_5% VCCDMI = 42mA detal waiting for newest spec
2 1 +VCCACLK
L23
Can NC
10UH_LB2012T100MR_20%
1 2 +3VS_VCC_CLKF33
1 1 +VCCDSW3_3 U13J POWER +1.05VS_VTT
1U_0402_6.3V6K
C55
1
C71 C47 AD49 N26
10U_0603_6.3V6M 0.1U_0402_16V7K VCCACLK VCCIO[29]
2 2 Not support Deep S4,S5 P26
1
connect to +3VALW 2 T16 VCCIO[30] C51
1
Near T16 VCCDSW3_3 P28 1U_0402_6.3V6K 1
VCCIO[31] 2
Near T38 +PCH_VCCDSW V12 3mA T27
PAD T14 @
DCPSUSBYP VCCIO[32]
T29
Near N26
suppied by internal +3VS_VCC_CLKF33 T38 VCCIO[33] +3V_PCH
1.05V VR must NC VCC3_3[5]
GPIO28 T23
PAD T30 @ +VCCAPLL_CPY_PCH BH23 VCCSUS3_3[7]
On-Die PLL Voltage Regulator 119mA
:
VCCAPLLDMI2 T24
VCCSUS3_3[8] 1 1
+3VALW AL29 C46 C45
H On-Die PLL voltage regulator +1.05VS_VTT VCCIO[14] V23 0.1U_0402_16V7K 0.1U_0402_16V7K
USB
enable R407 VCCSUS3_3[9]
Near T23 Near T24
0_0603_5% PAD T15 @ +VCCSUS1 AL24 V24 2 2 +3V_PCH +5V_PCH
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 2 1 +VCCDSW3_3 DCPSUS[3] VCCSUS3_3[10]
,VCCAPLLSATA P24
VCCSUS3_3[6]
1
+1.05VS_VTT
AA19 D23 R348
VCCASW[1] T26 RB751V-40_SOD323-2 100_0402_5%
+1.05VS_VTT AA21 1010mA VCCIO[34]
Near M26
+1.05VS_VTT VCCASW[2]
2
AA24 M26 +PCH_V5REF_SUS
L25 @ VCCASW[3] 1mA V5REF_SUS 1 2
+3VS +5VS
22U_0603_6.3V6K
C113
22U_0603_6.3V6K
C110
10UH_LB2012T100MR_20% AA26 C37
1
1 2 +1.05VS_VCCA_A_DPL AN23 +VCCA_USBSUS @ T16 0.1U_0402_16V7K
DCPSUS[4]
/
AA27 PAD
VCCASW[5]
1
220U_B2_2.5VM_R35
C118
1U_0402_6.3V6K
C103
2
AA29 VCCSUS3_3[1] D29 R130
1 VCCASW[6] 1.05V VR Must NC
1
+ @ 100_0402_5%
Near BD47
/x
R301 AA31 RB751V-40_SOD323-2
VCCASW[7]
0_0603_5%
2
2 2 AC26 P34 +PCH_V5REF_RUN
2
1 1 1
VCCASW[8] 1mA V5REF +3V_PCH 2
2
1
1U_0402_6.3V6K
C56
1U_0402_6.3V6K
C73
1U_0402_6.3V6K
C66
AC27
VCCASW[9] N20 C42
PCI/GPIO/LPC
1 2 +1.05VS_VCCA_B_DPL AC29 VCCSUS3_3[2] 1U_0402_6.3V6K
1
su
2
L26 2 2 2 VCCASW[10] N22 C38
VCCSUS3_3[3]
1U_0402_6.3V6K
C104
p.
2 W21 AA16
VCCASW[14] VCC3_3[1]
1 1 1
W23 W16 C471 C62 C49
VCCASW[15] VCC3_3[8] 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
W24 T34
VCCASW[16] VCC3_3[4] 2 Place near 2 Place near 2 Place near
om
W26 AJ2 AA16,W16 T34
VCCASW[17]
W29
VCCASW[18]
W31 AJ2 +1.05VS_VTT
VCCASW[19] VCC3_3[2]
W33
VCCASW[20] AF13
Near M6 VCCIO[5] Near AH13,AH14,AF13
yc
1
2 1 +VCCRTCEXT N16
C39 0.1U_0402_16V7K DCPRTC AH13 C76
VCCIO[12] 1U_0402_6.3V6K
Y49 AH14 2
+1.5VS VCCVRM[4] VCCIO[13]
GPIO28
m
3 AF14 3
+1.05VS_VCCA_A_DPL BD47 VCCIO[6]
80mA On-Die PLL Voltage Regulator
SATA
:
VCCADPLLA AK1 +VCCSATAPLL @ T29 PAD
+1.05VS_VTT
Place BF47 VCCAPLLSATA +1.5VS
+1.05VS_VCCA_B_DPL H On-Die PLL voltage regulator
near AG33 VCCADPLLB 80mA
AF11 enable
+1.05VS_VTT
// AF17
AF33 VCCIO[7]
VCCVRM[1]
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
1 C77 1 C79 AF34 VCCIO[8] AC16 +1.05VS_VTT ,VCCAPLLSATA
1U_0402_6.3V6K 1U_0402_6.3V6K AG34 VCCIO[9] 55mA VCCIO[2]
+1.05VS_VTT VCCIO[11] AC17
VCCIO[3] Near AC16
Place Place 1 C72
2 2 1U_0402_6.3V6K AG33 AD17
near AF17 near AG33
p:
VCCIO[10] VCCIO[4] 1
1 C74 95mA C68
Place 1U_0402_6.3V6K 1U_0402_6.3V6K
2 2 1 +VCCSST V16
near AF33, Near V16 C57 0.1U_0402_16V7K DCPSST +1.05VS_VTT 2
2
AF34,AG34 +1.05VM_VCCSUS T17 T21
tt
1.05V VR Must NC
+1.05VS_VTT V21
VCCASW[23]
1mA
CPU
h
BJ8
V_PROC_IO T19
VCCASW[21]
1 1 1
+RTCBATT +3V_PCH
4.7U_0603_6.3V6K
C114
0.1U_0402_16V7K
C109
0.1U_0402_16V7K
C111
A22 P32
10mAVCCSUSHDA
HDA
2 2 2 VCCRTC
isolation between SSC (AG33)
1U_0402_6.3V6K
C445
0.1U_0402_16V7K
C450
0.1U_0402_16V7K
C453
1 1 1 1
and DIFFCLKN(AF33,AF34,AG34) PANTHER_FCBGA989 C41
4 0.1U_0402_16V4Z 4
18mil width(DIFFCLKN)
<BOM Structure>
10mil (SSC) Place 2 2 2 2
U13I
AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
B11 VSS[162] VSS[262] K46
1 U13H B15 VSS[163] VSS[263] K7 1
H5 B19 VSS[164] VSS[264] L18
VSS[0] B23 VSS[165] VSS[265] L2
AA17 AK38 B27 VSS[166] VSS[266] L20
AA2 VSS[1] VSS[80] AK4 B31 VSS[167] VSS[267] L26
AA3 VSS[2] VSS[81] AK42 B35 VSS[168] VSS[268] L28
AA33 VSS[3] VSS[82] AK46 B39 VSS[169] VSS[269] L36
AA34 VSS[4] VSS[83] AK8 B7 VSS[170] VSS[270] L48
AB11 VSS[5] VSS[84] AL16 F45 VSS[171] VSS[271] M12
AB14 VSS[6] VSS[85] AL17 BB12 VSS[172] VSS[272] P16
AB39 VSS[7] VSS[86] AL19 BB16 VSS[173] VSS[273] M18
AB4 VSS[8] VSS[87] AL2 BB20 VSS[174] VSS[274] M22
AB43 VSS[9] VSS[88] AL21 BB22 VSS[175] VSS[275] M24
AB5 VSS[10] VSS[89] AL23 BB24 VSS[176] VSS[276] M30
AB7 VSS[11] VSS[90] AL26 BB28 VSS[177] VSS[277] M32
AC19 VSS[12] VSS[91] AL27 BB30 VSS[178] VSS[278] M34
AC2 VSS[13] VSS[92] AL31 BB38 VSS[179] VSS[279] M38
AC21 VSS[14] VSS[93] AL33 BB4 VSS[180] VSS[280] M4
AC24 VSS[15] VSS[94] AL34 BB46 VSS[181] VSS[281] M42
AC33 VSS[16] VSS[95] AL48 BC14 VSS[182] VSS[282] M46
AC34 VSS[17] VSS[96] AM11 BC18 VSS[183] VSS[283] M8
VSS[18] VSS[97] VSS[184] VSS[284]
/
AC48 AM14 BC2 N18
AD10 VSS[19] VSS[98] AM36 BC22 VSS[185] VSS[285] P30
AD11 VSS[20] VSS[99] AM39 BC26 VSS[186] VSS[286] N47
AD12 VSS[21] VSS[100] AM43 BC32 VSS[187] VSS[287] P11
/x
AD13 VSS[22] VSS[101] AM45 BC34 VSS[188] VSS[288] P18
AD19 VSS[23] VSS[102] AM46 BC36 VSS[189] VSS[289] T33
AD24 VSS[24] VSS[103] AM7 BC40 VSS[190] VSS[290] P40
AD26 VSS[25] VSS[104] AN2 BC42 VSS[191] VSS[291] P43
AD27 VSS[26] VSS[105] AN29 BC48 VSS[192] VSS[292] P47
AD33 VSS[27] VSS[106] AN3 BD46 VSS[193] VSS[293] P7
su
AD34 VSS[28] VSS[107] AN31 BD5 VSS[194] VSS[294] R2
2 AD36 VSS[29] VSS[108] AP12 BE22 VSS[195] VSS[295] R48 2
AD37 VSS[30] VSS[109] AP19 BE26 VSS[196] VSS[296] T12
AD38 VSS[31] VSS[110] AP28 BE40 VSS[197] VSS[297] T31
AD39 VSS[32] VSS[111] AP30 BF10 VSS[198] VSS[298] T37
AD4 VSS[33] VSS[112] AP32 BF12 VSS[199] VSS[299] T4
VSS[34] VSS[113] VSS[200] VSS[300]
p.
AD40 AP38 BF16 W34
AD42 VSS[35] VSS[114] AP4 BF20 VSS[201] VSS[301] T46
AD43 VSS[36] VSS[115] AP42 BF22 VSS[202] VSS[302] T47
AD45 VSS[37] VSS[116] AP46 BF24 VSS[203] VSS[303] T8
AD46 VSS[38] VSS[117] AP8 BF26 VSS[204] VSS[304] V11
VSS[39] VSS[118] VSS[205] VSS[305]
om
AD8 AR2 BF28 V17
AE2 VSS[40] VSS[119] AR48 BD3 VSS[206] VSS[306] V26
AE3 VSS[41] VSS[120] AT11 BF30 VSS[207] VSS[307] V27
AF10 VSS[42] VSS[121] AT13 BF38 VSS[208] VSS[308] V29
AF12 VSS[43] VSS[122] AT18 BF40 VSS[209] VSS[309] V31
AD14 VSS[44] VSS[123] AT22 BF8 VSS[210] VSS[310] V36
AD16 VSS[45] VSS[124] AT26 BG17 VSS[211] VSS[311] V39
AF16 VSS[46] VSS[125] AT28 BG21 VSS[212] VSS[312] V43
AF19 VSS[47] VSS[126] AT30 BG33 VSS[213] VSS[313] V7
yc
AF24 VSS[48] VSS[127] AT32 BG44 VSS[214] VSS[314] W17
AF26 VSS[49] VSS[128] AT34 BG8 VSS[215] VSS[315] W19
AF27 VSS[50] VSS[129] AT39 BH11 VSS[216] VSS[316] W2
AF29 VSS[51] VSS[130] AT42 BH15 VSS[217] VSS[317] W27
AF31 VSS[52] VSS[131] AT46 BH17 VSS[218] VSS[318] W48
VSS[53] VSS[132] VSS[219] VSS[319]
m
AF38 AT7 BH19 Y12
AF4 VSS[54] VSS[133] AU24 H10 VSS[220] VSS[320] Y38
AF42 VSS[55] VSS[134] AU30 BH27 VSS[221] VSS[321] Y4
AF46 VSS[56] VSS[135] AV16 BH31 VSS[222] VSS[322] Y42
AF5 VSS[57] VSS[136] AV20 BH33 VSS[223] VSS[323] Y46
VSS[58] VSS[137] VSS[224] VSS[324]
AF7
AF8 VSS[59]
VSS[60]
VSS[138]
VSS[139]
AV24
AV30
//
BH35
BH39 VSS[225]
VSS[226]
VSS[325]
VSS[328]
Y8
BG29
AG19 AV38 BH43 N24
3 AG2 VSS[61] VSS[140] AV4 BH7 VSS[227] VSS[329] AJ3 3
AG31 VSS[62] VSS[141] AV43 D3 VSS[228] VSS[330] AD47
AG48 VSS[63] VSS[142] AV8 D12 VSS[229] VSS[331] B43
AH11 VSS[64] VSS[143] AW14 D16 VSS[230] VSS[333] BE10
p:
PANTHER_FCBGA989
<BOM Structure>
/
PCIE_RX5N PCIE_TX5N AL15
TXCLK_LP_DPE3P AK14
PEG_HTX_C_GRX_P9 Y30 AB27 PEG_GTX_HRX_P9 TXCLK_LN_DPE3N
/x
PEG_HTX_C_GRX_N9 W31 PCIE_RX6P PCIE_TX6P AB26 PEG_GTX_HRX_N9 AH16
PCIE_RX6N PCIE_TX6N TXOUT_L0P_DPE2P AJ15
C TXOUT_L0N_DPE2N C
su
PCIE_RX7N PCIE_TX7N TXOUT_L1N_DPE1N
AH18
PEG_HTX_C_GRX_P7 V30 W24 PEG_GTX_HRX_P7 TXOUT_L2P_DPE0P AJ17
PEG_HTX_C_GRX_N7 U31 PCIE_RX8P PCIE_TX8P W23 PEG_GTX_HRX_N7 TXOUT_L2N_DPE0N
PCIE_RX8N PCIE_TX8N AL19
p.
TXOUT_L3P AK18
PEG_HTX_C_GRX_P6 U29 V27 PEG_GTX_HRX_P6 TXOUT_L3N
PEG_HTX_C_GRX_N6 T28 PCIE_RX9P PCIE_TX9P U26 PEG_GTX_HRX_N6
PCIE_RX9N PCIE_TX9N
om
PEG_HTX_C_GRX_P5 T30 U24 PEG_GTX_HRX_P5 216-0774207-A11ROB_FCBGA631
PEG_HTX_C_GRX_N5 R31 PCIE_RX10P PCIE_TX10P U23 PEG_GTX_HRX_N5
PCIE_RX10N PCIE_TX10N
PX@
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_N4
R29
P28 PCIE_RX11P PCIE_TX11P
T26
T27
PEG_GTX_HRX_P4
PEG_GTX_HRX_N4 LVDS
yc
PCIE_RX11N PCIE_TX11N
m
PEG_HTX_C_GRX_P2 N29 P27 PEG_GTX_HRX_P2
PEG_HTX_C_GRX_N2 M28 PCIE_RX13P PCIE_TX13P P26 PEG_GTX_HRX_N2
PCIE_RX13N PCIE_TX13N
//
PEG_HTX_C_GRX_P1 M30 P24 PEG_GTX_HRX_P1
PEG_HTX_C_GRX_N1 L31 PCIE_RX14P PCIE_TX14P P23 PEG_GTX_HRX_N1
PCIE_RX14N PCIE_TX14N
p:
CLOCK
CLK_PCIE_VGA AK30
[14] CLK_PCIE_VGA AK32 PCIE_REFCLKP
CLK_PCIE_VGA#
[14] CLK_PCIE_VGA# PCIE_REFCLKN
h
R222 0_0402_5%
2 @ 1 CALIBRATION PX@
[18,49] VGA_PWRGD
Y22 1.27K_0402_1% 1 2 R298
PCIE_CALRP
2 R299PX@1 N10 AA22 2K_0402_1% 1 PX@ 2 R300 +1.0VGS
A 10K_0402_5% PWRGOOD PCIE_CALRN A
GPU_RST# AL27
[17] GPU_RST# PERSTB
Security Classification Compal Secret Data Compal Electronics, Inc.
216-0774207-A11ROB_FCBGA631 2010/07/12 2012/07/11 Title
Issued Date Deciphered Date
SeymourXT-S3 PCIE/LVDS
PCIE LANE
PX@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
Document Number Rev
0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 02, 2012 Sheet 22 of 55
5 4 3 2 1
5 4 3 2 1
U8B
AF2
TXCAP_DPA3P AF4
Y11 TXCAM_DPA3N
AE9 DVCLK AG3
L9 DVCNTL_0 TX0P_DPA2P AG5
N9 DVCNTL_1 DVO DPA TX0M_DPA2N
DVCNTL_2 AH3
AE8 TX1P_DPA1P AH1
AD9 DVDATA_12 TX1M_DPA1N
AC10 DVDATA_11 AK3
+1.8VGS +DPC_VDD18 AD7 DVDATA_10 TX2P_DPA0P AK1
L8 AC8 DVDATA_9 TX2M_DPA0N
2 1 +DPC_VDD18 AC7 DVDATA_8 AK5
BLM15BD121SN1D_0402 AB9 DVDATA_7 TXCBP_DPB3P AM3
10U_0603_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_10V6K
D
PX@ AB8 DVDATA_6 TXCBM_DPB3N D
C304
C305
C306
1 1 1 DVDATA_5
AB7 AK6
AB4 DVDATA_4 TX3P_DPB2P AM5
@ @ @ VRAM_ID2 AB2 DVDATA_3 DPB TX3M_DPB2N
2 2 2 [27] VRAM_ID2 DVDATA_2
VRAM_ID1 Y8 AJ7
[27] VRAM_ID1 DVDATA_1 TX4P_DPB1P
VRAM_ID0 Y7 AH6
[27] VRAM_ID0 DVDATA_0 TX4M_DPB1N
AK8
TX5P_DPB0P AL7
TX5M_DPB0N
+DPC_VDD18 W6 DPC
+DPC_VDD18 DPC_PVDD
V6
+1.0VGS +DPC_VDD10 DPC_PVSS V4
L9 +DPC_VDD18 AC6 TXCCP_DPC3P U5
+DPC_VDD18 DPC_VDD18#1 TXCCM_DPC3N
2 1 +DPC_VDD10 AC5
BLM15BD121SN1D_0402 DPC_VDD18#2 W3
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
C346
C347
/
Y6 DPC_VSSR#3 J8 1 R307 2
AA1 DPC_VSSR#4 DPC_CALR 150_0402_1%
DPC_VSSR#5
PX@
/x
I2C
R1
R3 SCL
SDA
su
AM26 T55
GENERAL PURPOSE I/O R AK26
C C
GPU_GPIO0 U6 RB
GPU_GPIO1 U10 GPIO_0 AL25 T56
GPU_GPIO2 T10 GPIO_1 G AJ25
VGA_SMB_DA2_R U8 GPIO_2 GB
CH751H-40PT_SOD323-2
D4
@ VGA_SMB_CK2_R U7 GPIO_3_SMBDATA AH24 T57
0117 AMD request to stuff R320
GPIO_4_SMBCLK B
p.
1 2 GPU_GPIO5 T9 AG25 +AVDD +1.8VGS
[15,37,43] ACIN GPIO_5_AC_BATT BB
T8 DAC1 L10 +3VGS
T7 GPIO_6 AH26 VGA_HSYNC +AVDD 1 2
GPU_GPIO8 P10 GPIO_7_BLON HSYNC AJ27 VGA_VSYNC BLM15BD121SN1D_0402 GPU_GPIO0 R339 2 @ 1 10K_0402_5%
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
GPU_GPIO9 P4 GPIO_8_ROMSO VSYNC GPU_GPIO1 R338 2 PX@ 1 10K_0402_5%
C397
C400
C401
GPIO_9_ROMSI 1 1 1
P2 PX@ GPU_GPIO2 R325 2 PX@ 1 10K_0402_5%
PX@
om
GPU_GPIO11 N6 GPIO_10_ROMSCK AD22 1 R318 2 GPU_GPIO5 R320 2 PX@ 1 10K_0402_5%
GPU_GPIO12 N5 GPIO_11 RSET 499_0402_1% PX@ PX@ PX@
GPU_GPIO13 N3 GPIO_12 AG24 +AVDD +AVDD 2 2 2 GPU_GPIO8 R313 2 @ 1 10K_0402_5%
Y9 GPIO_13 AVDD AE22 GPU_GPIO9 R314 2 @ 1 10K_0402_5%
GPU_VID0 N1 GPIO_14_HPD2 AVSSQ
[49] GPU_VID0 GPIO_15_PWRCNTL_0
T63 M4 AE23 +VDD1DI +VDD1DI GPU_GPIO11 R315 2 PX@ 1 10K_0402_5%
R6 GPIO_16_SSIN VDD1DI AD23 GPU_GPIO12 R316 2 @ 1 10K_0402_5%
PX@ W10 GPIO_17_THERMAL_INT VSS1DI GPU_GPIO13 R317 2 @ 1 10K_0402_5%
R319 1 2
10K_0402_5% M2 GPIO_18_HPD3 +VDD1DI +1.8VGS
GPU_VID1 P8 GPIO_19_CTF AM12 L11 VGA_HSYNC R548 1 @ 2 10K_0402_5%
yc
[49] GPU_VID1 GPIO_20_PWRCNTL_1 R2
T70 P7 AK12 +VDD1DI 1 2 VGA_VSYNC R549 1 @ 2 10K_0402_5%
N8 GPIO_21_BB_EN R2B BLM15BD121SN1D_0402
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
PEG_CLKREQ# N7 GPIO_22_ROMCSB AL11 PX@
C313
C396
C315
[14] PEG_CLKREQ# GPIO_23_CLKREQB G2 1 1 1
+3VGS AJ11
GPIO24_TRSTB L6 G2B
PX@ 1 R321 2
10K_0402_5% GPIO24_TRSTB GPIO25_TDI L5 JTAG_TRSTB AK10 PX@ PX@ PX@
1 2 GPIO25_TDI GPIO26_TCK L3 JTAG_TDI B2 AL9 2 2 2
m
PX@ R322 10K_0402_5%
PX@ 1 R323 2
10K_0402_5% GPIO27_TMS GPIO27_TMS L1 JTAG_TCK B2B
PX@ 1 R324 2
10K_0402_5% GPIO26_TCK T64 GPIO28_TDO K4 JTAG_TMS
1R326 2 TEST_EN K7 JTAG_TDO AH12
PX@ 5.11K_0402_1% AF24 TESTEN C AM10
T65 TESTEN_LEGACY Y AJ9
COMP
AB13
W8 GENERICA
DAC2
// AL13 T53
+1.8VGS +DPLL_PVDD W9 GENERICB H2SYNC AJ13 T54
B
L14 W7 GENERICC V2SYNC +3VGS B
2 1 +DPLL_PVDD AD10 GENERICD
BLM15BD121SN1D_0402 GENERICE_HPD4 AD19
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
C324
C325
1 1 1
p:
1
4.7K_0402_5%
PX@ PX@ PX@ AE20 R327 R328
2 2 2 @ A2VDD 10K_0402_5% 10K_0402_5%
AE17
A2VDDQ
2
tt
2
+1.8VGS AE19
PX@ A2VSSQ VGA_SMB_CK2_R 1 6
EC_SMB_CK2 [14,34,37]
2 R329 1499_0402_1% +VREFG_GPU AC16 PX@ PX@
VREFG
5
+1.0VGS +DPLL_VDDC AG13 1 R330 2 Q64A
L49 2 R332 1249_0402_1% R2SET 715_0402_1% 2N7002DW-T/R7_SOT363-6
h
0.1U_0402_10V6K
1U_0402_6.3V4Z
C331
C332
1 1 1 DDC1CLK
PX@ PLL/CLOCK AE5 2N7002DW-T/R7_SOT363-6
+DPLL_PVDD AF14 DDC1DATA
+DPLL_PVDD DPLL_PVDD
PX@ PX@ PX@ AE14 AD2
2 2 2 DPLL_PVSS AUX1P AD4 PX@
AUX1N
+DPLL_VDDC AD14 AC11
+DPLL_VDDC DPLL_VDDC DDC2CLK AC13
DDC2DATA
XTALIN AM28 AD13
+1.8VGS +TSVDD XTALOUT AK28 XTALIN AUX2P AD11
L17 PX@ XTALOUT AUX2N
2 1 +TSVDD 2 R335 10_0402_5% AC22 AD20
BLM18AG121SN1D_0603 2 R333 10_0402_5% AB22 XO_IN DDCCLK_AUX3P AC20
10U_0603_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_16V4Z
C335
C336
1 1 1
PX@ AE16
DDCCLK_AUX5P AD16
PX@ PX@ PX@ DDCDATA_AUX5N
2 2 2 AC1 T58
T4 THERMAL DDC6CLK AC3 T59
T2 DPLUS DDC6DATA
A A
PX@ DMINUS
R334 2.61K_0402_5%
1 2 1 2 R5
+3VGS TS_FDO
R337 10M_0402_5% +TSVDD AD17
+TSVDD TSVDD
PX@ AC17
TSVSS
Y6
4 3 XTALOUT
NC OSC 216-0774207-A11ROB_FCBGA631
XTALIN 1 2
OSC NC
PX@
Security Classification Compal Secret Data Compal Electronics, Inc.
2 27MHZ 16PF +-30PPM X3G027000FG1H-HX 2 Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
PX@ PX@ PX@
C341 C350
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SeymourXT-S3 Main Generic/MSIC
15P_0402_50V8J 15P_0402_50V8J AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1 1 C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 02, 2012 Sheet 23 of 55
5 4 3 2 1
5 4 3 2 1
D
55mA@1.0V, in BACO mode D
+BIF_VDDC +VGA_CORE
1 2
R398 0_0805_5%
PX@
1
C342 PX@
22U_0603_6.3V6K
2
+1.8VS TO +1.8VGS +3.3VS TO +3.3VGS
/
+3VALW
/x
+1.8VS +1.8VGS +3VS +3VGS
J4 @ J2 @
1
2 1 2 1
PX@ 1 PX@ 1
C375 2MM C1139 2MM R263 PX@
U15 PX@ 1 1 100K_0402_5%
1
10U_0603_6.3V6M AO4430L_SO8 PX@ @ R290 10U_0603_6.3V6M PX@ @ R284
su
2
2 8 1 C1140 C1141 PX@ 2 C344 C345 PX@
C 7 2 10U_0603_6.3V6M 1U_0402_6.3V6K 470_0603_5% 3 1 10U_0603_6.3V6M 1U_0402_6.3V6K 470_0603_5% PXS_PWREN# C
2
+VSB 6 3 2 +5VALW 2
5 Q26
1
Q27 PX@ DTC124EKAT146_SC59-3
AP2301GN-HF_SOT23-3
OUT
R279 R270
4
2
@ Q36 @ Q35
1
p.
1 2 1R1451 PX@2 D 1 2 1 2 D
PXS_PWREN#1 2 2 PX@ R271
PX@R271 PXS_PWREN#1 2 2 PXS_PWREN 2
[17,49] PXS_PWREN IN
47K_0402_5% @ R287 G 0_0402_5% @ R283 G
GND
PX@ 75K_0402_5% 0_0402_5% 51K_0402_5% 0_0402_5%
S S
3
2N7002K_SOT23-3 PX@ 2N7002K_SOT23-3
1
1
1
D C1142 PX@ D PX@
om
3
PXS_PWREN# 2 0.1U_0402_25V6 PXS_PWREN 2 C1143 PX@
G Q32 PX@ G Q30 PX@ 0.1U_0402_16V4Z
2
S 2N7002K_SOT23-3 S 2N7002K_SOT23-3 2
3
3
yc
m
+1.5V_IO +1.5VGS
J9 @
2 1
2MM
C1145 6 3 PX@ @
PX@ 5 C1146 C1147 PX@ R274
10U_0603_6.3V6M 1U_0402_6.3V6K 470_0603_5%
p:
2
2 2
4
1 2
+VSB @ R285 D
PXS_PWREN#1 2 2
PX@ G
tt
20K_0402_5% 2N7002K_SOT23-3
R278
1 2
h
2
R280
43K_0402_5%
1
D PX@ @ 0.1U_0402_25V6
PXS_PWREN# 2
1
G Q37 PX@
S 2N7002K_SOT23-3
3
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SeymourXT_S3_BACO POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 24 of 55
5 4 3 2 1
5 4 3 2 1
10U_0603_6.3V6M
10U_0603_6.3V6M
C367
C368
C355
C357
C358
C359
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
D
1 1 1 1 1 1 D
MBK1608121YZF_0603 U8G MBK1608121YZF_0603
Change to 0 ohm @ @ @ @ @ @ Change to 0 ohm
2 2 2 DP E/F POWER DP A/B POWER 2 2 2
P/N 130mA P/N
+1.0VGS AG15 AE11 +DPAB_VDD18
AG16 DPE_VDD18#1 DPA_VDD18#1 AF11
+DPEF_VDD10 DPE_VDD18#2 DPA_VDD18#2 +DPAB_VDD10 +1.0VGS
PX@
L20 total:240mA@LVDS L21
PX@
total:220mA@DP 110mA total:220mA
2 1 AG20 AF6 1 2
DPE_VDD10#1 DPA_VDD10#1
10U_0603_6.3V6M
10U_0603_6.3V6M
C356
C360
C361
C362
C363
C364
0.1U_0402_10V6K
0.1U_0402_10V6K
AG21 AF7
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 1 1 DPE_VDD10#2 DPA_VDD10#2 1 1 1
MBK1608121YZF_0603 MBK1608121YZF_0603
Change to 0 ohm
@ @ @ AG14 AE1 @ @ @ Change to 0 ohm
P/N 2 2 2 AH14 DPE_VSSR#1 DPA_VSSR#1 AE3 2 2 2
AM14 DPE_VSSR#2 DPA_VSSR#2 AG1 P/N
AM16 DPE_VSSR#3 DPA_VSSR#3 AG6
AM18 DPE_VSSR#4 DPA_VSSR#4 AH5
/
DPE_VSSR#5 DPA_VSSR#5
+DPEF_VDD18 +DPAB_VDD18
130mA
/x
AF16 AE13 +DPAB_VDD18
AG17 DPF_VDD18#1 DPB_VDD18#1 AF13
C DPF_VDD18#2 DPB_VDD18#2 C
+DPEF_VDD10 +DPAB_VDD10
110mA
su
AF22 AF8 +DPAB_VDD10
AG22 DPF_VDD10#1 DPB_VDD10#1 AF9
DPF_VDD10#2 DPB_VDD10#2
AF23 AF10
p.
AG23 DPF_VSSR#1 DPB_VSSR#1 AG9
AM20 DPF_VSSR#2 DPB_VSSR#2 AH8
AM22 DPF_VSSR#3 DPB_VSSR#3 AM6
AM24 DPF_VSSR#4 DPB_VSSR#4 AM8
DPF_VSSR#5 DPB_VSSR#5
om
R463 PX@
2 1 AF17 AE10 1 R464 2
150_0402_1% DPEF_CALR DPAB_CALR 150_0402_1%
+DPEF_VDD18 PX@ +DPAB_VDD18
yc
20mA 20mA
+DPEF_VDD18 AG18 DP PLL POWER AG8 +DPAB_VDD18
AF19 DPE_PVDD DPA_PVDD AG7
DPE_PVSS DPA_PVSS
B +DPEF_VDD18 +DPAB_VDD18 B
m
20mA 20mA
+DPEF_VDD18 AG19 AG10 +DPAB_VDD18
AF20 DPF_PVDD DPB_PVDD AG11
DPF_PVSS DPB_PVSS
//
216-0774207-A11ROB_FCBGA631
PX@
p:
tt
h
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SeymourXT-S3 DP PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 02, 2012 Sheet 25 of 55
5 4 3 2 1
5 4 3 2 1
+1.5VGS
2.3A(RMS)/2.8A(Peak)
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
C365
C366
C369
C370
C371
C372
C373
C374
C389
C390
C391
C381
C392
1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2
+PCIE_VDDR +1.8VGS
9/28 Reserved for VGA_CORE
504mA L22
U8D +PCIE_VDDR 2 1
10/8 change to B2 size U8E
PX@ PX@ PX@ PX@ PX@
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ MEM I/O MBK1608121YZF_0603
C385
C387
C388
C380
D 1 1 1 1 D
PCIE Change to 0 ohm
H13 AB23 AA27 A3
H16 VDDR1#1 PCIE_VDDR#1 AC23 P/N PX@ AB24 PCIE_VSS#1 GND#1 A30
H19 VDDR1#2 PCIE_VDDR#2 AD24 2 2 2 2 AB32 PCIE_VSS#2 GND#2 AA13
J10 VDDR1#3 PCIE_VDDR#3 AE24 AC24 PCIE_VSS#3 GND#3 AA16
J23 VDDR1#4 PCIE_VDDR#4 AE25 AC26 PCIE_VSS#4 GND#4 AB10
J24 VDDR1#5 PCIE_VDDR#5 AE26 AC27 PCIE_VSS#5 GND#5 AB15
J9 VDDR1#6 PCIE_VDDR#6 AF25 AD25 PCIE_VSS#6 GND#6 AB6
K10 VDDR1#7 PCIE_VDDR#7 AG26 +1.0VGS AD32 PCIE_VSS#7 GND#7 AC9
VDDR1#8 PCIE_VDDR#8 PX@ PX@ PCIE_VSS#8 GND#8
K23 PX@ PX@ AE27 AD6
K24 VDDR1#9 AF32 PCIE_VSS#9 GND#9 AD8
K9 VDDR1#10 L23 1920mA AG27 PCIE_VSS#10 GND#10 AE7
L11 VDDR1#11 PCIE_VDDC#1 L24 AH32 PCIE_VSS#11 GND#11 AG12
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
L12 VDDR1#12 PCIE_VDDC#2 L25 K28 PCIE_VSS#12 GND#12 AH10
C398
C399
C383
C403
C384
VDDR1#13 PCIE_VDDC#3 1 1 1 1 1 PCIE_VSS#13 GND#13
+1.8VGS +VDDC_CT L13 L26 K32 AH28
L20 VDDR1#14 PCIE_VDDC#4 M22 L27 PCIE_VSS#14 GND#14 B10
L46 L21 VDDR1#15 PCIE_VDDC#5 N22 M32 PCIE_VSS#15 GND#15 B12
1 2
110mA L22 VDDR1#16 PCIE_VDDC#6 N23 2 2 2 2 2 N25 PCIE_VSS#16 GND#16 B14
BLM15BD121SN1D_0402 VDDR1#17 PCIE_VDDC#7 N24 N27 PCIE_VSS#17 GND#17 B16
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
C405
C422
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 AA20 PCIE_VDDC#12 T32 PCIE_VSS#22 GND#22 B26
17mA
C427
C410
C428
1 1 1 VDD_CT#1 PCIE_VSS#23 GND#23
AA21 U25 B6
11.8A(RMS)/12.9A(Peak)
/
@ AB20 VDD_CT#2 AA15 U27 PCIE_VSS#24 GND#24 B8
AB21 VDD_CT#3 CORE VDDC#1 N15 V32 PCIE_VSS#25 GND#25 C1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 VDD_CT#4 VDDC#2 N17 W25 PCIE_VSS#26 GND#26 C32
C431
C432
C415
C416
C417
C418
C419
C420
C423
C424
C425
C426
VDDC#3 1 1 1 1 1 1 1 1 1 1 1 1 PCIE_VSS#27 GND#27
R13 W26 E28
/x
PX@ VDDC#4 PCIE_VSS#28 GND#28
PX@ PX@ I/O R16 W27 F10
AA17 VDDC#5 R18 Y25 PCIE_VSS#29 GND#29 F12
60mA VDDR3#1 VDDC#6 PCIE_VSS#30 GND#30
AA18 Y21 2 2 2 2 2 2 2 2 2 2 2 2 Y32 F14
AB17 VDDR3#2 VDDC#7 T12 PCIE_VSS#31 GND#31 F16
PX@ VDDR3#3 VDDC#8 GND#32
PX@ AB18 T15 F18
L24 VDDR3#4 VDDC#9 T17 GND#33 F2
1 2 V12 VDDC#10 T20 GND#34 F20
170mA
su
BLM15BD121SN1D_0402 Y12 VDDR4#1 VDDC#11 U13 M6 GND#35 F22
PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
0.1U_0402_10V6K
1U_0402_6.3V4Z
U12 VDDR4#2 VDDC#12 U16 PX@ PX@ PX@ PX@ N11 GND#56 GND#36 F24
C C
VDDR4#3 VDDC#13 GND#57 GND#37
POWER
U18 N12 F26
C429
C430
Change to
PX@0 ohm 1 1
AA11 VDDC#14 V21
7/22 modify N13 GND#58 GND#38 F6
P/N AA12 NC#1 VDDC#15 V15 N16 GND#59 GND#39 F8
PX@
2
PX@
2 V11
NC#2
NC#3
VDDC#16
VDDC#17
VDDC#18
V17
V20
N18
N21
GND#60
GND#61
GND#62
GND GND#40
GND#41
GND#42
G10
G27
p.
U11 Y13 P6 G31
NC#4 VDDC#19 Y16 P9 GND#63 GND#43 G8
VDDC#20 Y18 R12 GND#64 GND#44 H14
VDDC#21 M11 R15 GND#65 GND#45 H17
L47
0120 change power rail to +PCIE_VDDR VDDC#22 M12 R17 GND#66 GND#46 H2
1 2 MEM CLK VDDC#23 R20 GND#67 GND#47 H20
om
BLM15BD121SN1D_0402 L17 T13 GND#68 GND#48 H6
10U_0603_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_10V6K
C447
C449
1 1 1 GND#70 GND#50
L16 +BIF_VDDC T18 J31
PX@ +PCIE_VDDR NC_VSSRHA GND#71 GND#51
T21 K11
T6 GND#72 GND#52 K2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 For Seymour, PCIE_PVDD is PCIE_VDDR. PLL U15 GND#73 GND#53 K22
C470
C516
1 1 GND#74 GND#54
AM30 U17 K6
PCIE_PVDD R21 U20 GND#75 GND#55
BIF_VDDC#1 U21 U9 GND#76
BIF_VDDC#2 2 2 GND#77
+MPV18 75mA L8 V13
yc
NC_MPV18 V16 GND#78
PX@ GND#79
L48 PX@ PX@ V18
1 2 GND#80
+SPV18 75mA H7 SPV18
Y10
GND#81
BLM15BD121SN1D_0402 ISOLATED Y15
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
GND#82
+SPV10 120mAH8 CORE I/O M13 Y17 A32
C462
C454
C463
m
0_0603_5%
L28 SPVSS VDDCI#3 M17 1 2 T11 GND#85 VSS_MECH#3
2 2 2 1 2 VDDCI#4 M18 GND#86
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
BLM15BD121SN1D_0402 VDDCI#5 M20
C465
C460
C461
C466
1 1 1 1
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
VDDCI#6 M21
C456
C464
C458
PX@
PX@
PX@ 2 2 2
// 2 2 2 2
216-0774207-A11ROB_FCBGA631
PX@
B B
216-0774207-A11ROB_FCBGA631
PX@ PX@
tt
h
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SeymourXT-S3 PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 02, 2012 Sheet 26 of 55
5 4 3 2 1
5 4 3 2 1
U8C +1.8VGS
M_DA[63..0]
[28] M_DA[63..0] 1
GDDR5/DDR3 GDDR5/DDR3 R461 X76@ 2 10K_0402_5% VRAM_ID0
M_MA[13..0] K27 K17 1 VRAM_ID0 [23]
M_DA0 M_MA0 R462 X76@ 2 10K_0402_5%
[28] M_MA[13..0] DQA0_0/DQA_0 MAA0_0/MAA_0
M_DA1 J29 J20 M_MA1 R359 1 X76@ 2 10K_0402_5% VRAM_ID1
M_DQM[7..0] H30 DQA0_1/DQA_1 MAA0_1/MAA_1 H23 1 VRAM_ID1 [23]
M_DA2 M_MA2 R360 X76@ 2 10K_0402_5%
[28] M_DQM[7..0] DQA0_2/DQA_2 MAA0_2/MAA_2
M_DA3 H32 G23 M_MA3 R361 1 X76@ 2 10K_0402_5% VRAM_ID2
M_DQS[7..0] G29 DQA0_3/DQA_3 MAA0_3/MAA_3 G24 1 VRAM_ID2 [23]
M_DA4 M_MA4 R362 X76@ 2 10K_0402_5%
[28] M_DQS[7..0] DQA0_4/DQA_4 MAA0_4/MAA_4
MEMORY INTERFACE
M_DA5 F28 H24 M_MA5
M_DQS#[7..0] M_DA6 F32 DQA0_5/DQA_5 MAA0_5/MAA_5 J19 M_MA6
[28] M_DQS#[7..0] F30 DQA0_6/DQA_6 MAA0_6/MAA0_6 K19
M_DA7 M_MA7
D M_DA8 C30 DQA0_7/DQA_7 MAA0_7/MAA0_7 J14 M_MA8 D
M_DA9 F27 DQA0_8/DQA_8 MAA1_0/MAA_8 K14 M_MA9
M_DA10 A28 DQA0_9/DQA_9 MAA1_1/MAA_9 J11 M_MA10
PARK SCL has DQA0_10/DQA_10 MAA1_2/MAA_10
M_DA11 C28 J13 M_MA11
DQA0_11/DQA_11 MAA1_3/MAA_11
different recommand 9/28 change P/N to
M_DA12 E27
DQA0_12/DQA_12 MAA1_4/MAA_12
H11 M_MA12
M_DA13 G26 G11 M_BA2
DQA0_13/DQA_13 MAA1_5/MAA_13/BA2 M_BA2 [28]
SD034100A80R455 M_DA14 D26
DQA0_14/DQA_14 MAA1_6/MAA_14/BA0
J16 M_BA0
M_BA0 [28]
10_0402_1% M_DA15 F25 L15 M_BA1
DQA0_15/DQA_15 MAA1_7/MAA_15/BA1 M_BA1 [28]
1 R366 2 2 1 DRAM_RST M_DA16 A25
[28] DRAM_RST# C25 DQA0_16/DQA_16 E32
Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2
51.1_0402_1% M_DA17 M_DQM0
PX@ M_DA18 E25 DQA0_17/DQA_17 WCKA0_0/DQMA_0 E30 M_DQM1
DQA0_18/DQA_18 WCKA0B_0/DQMA_1
1
1 M_DA19 D24 A21 M_DQM2 K4W1G1646G-BC11
C469 M_DA20 E23 DQA0_19/DQA_19 WCKA0_1/DQMA_2 C21 M_DQM3 64MX16 (512MB) Samsung 128MB
PX@R456 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 R461 R360 R362
120P_0402_50V8J 4.99K_0402_1% M_DA21 F23 E13 M_DQM4
DQA0_21/DQA_21 WCKA1_0/DQMA_4
M_DA22 D22
DQA0_22/DQA_22 WCKA1B_0/DQMA_5
D12 M_DQM5 PN:SA00004GS00 1 0 0
2 M_DA23 F21 E3 M_DQM6 H5TQ1G63DFR-11C
2
M_DA24 E21 DQA0_23/DQA_23 WCKA1_1/DQMA_6 F4 M_DQM7 64MX16 (512MB) Hynix 128MB
D20 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 R462 R359 R362
PX@ M_DA25
DQA0_25/DQA_25
PX@ M_DA26 F19 H28 M_DQS0 PN:SA000041S20 0 1 0
/
M_DA27 A19 DQA0_26/DQA_26 EDCA0_0/RDQSA_0 C27 M_DQS1 K4W2G1646C-HC11
M_DA28 D18 DQA0_27/DQA_27 EDCA0_1/RDQSA_1 A23 M_DQS2
F17 DQA0_28/DQA_28 EDCA0_2/RDQSA_2 E19
Samsung 256MB R461 R360 R361
M_DA29 M_DQS3 128M16 (1GB)
/x
DQA0_29/DQA_29 EDCA0_3/RDQSA_3
M_DA30 A17
DQA0_30/DQA_30 EDCA1_0/RDQSA_4
E15 M_DQS4 PN:SA000047Q00 1 0 1
M_DA31 C17 D10 M_DQS5 H5TQ2G63BFR-11C/H5TQ2G63DFR-11C
C DQA0_31/DQA_31 EDCA1_1/RDQSA_5 C
+1.5VGS M_DA32 E17 D6 M_DQS6
+1.5VGS D16 DQA1_0/DQA_32 EDCA1_2/RDQSA_6 G5
Hynix 256MB R462 R359 R361
M_DA33 M_DQS7 128M16 (1GB)
DQA1_1/DQA_33 EDCA1_3/RDQSA_7
M_DA34 F15 PN:SA00003YO10/ 0 1 1
su
DQA1_2/DQA_34
1
p.
2
om
R364 C467 R457 C514 M_DA44 A9 L18 VRAM_ODT0
C9 DQA1_12/DQA_44 ADBIA0/ODTA0 K16 VRAM_ODT0 [28]
100_0402_1% 0.1U_0402_16V4Z 100_0402_1% 0.1U_0402_16V4Z M_DA45 VRAM_ODT1
DQA1_13/DQA_45 ADBIA1/ODTA1 VRAM_ODT1 [28]
M_DA46 F9
2 2 M_DA47 D8 DQA1_14/DQA_46 H26 M_CLK0
M_CLK0 [28]
2
yc
DQA1_18/DQA_50 CLKA1 M_CLK1 [28]
M_DA51 F7 H9 M_CLK#1 X7639238L02
A5 DQA1_19/DQA_51 CLKA1B M_CLK#1 [28]
M_DA52
M_DA53 E5 DQA1_20/DQA_52 G22 M_RAS#0
C3 DQA1_21/DQA_53 RASA0B G17 M_RAS#0 [28]
M_DA54 M_RAS#1
E1 DQA1_22/DQA_54 RASA1B M_RAS#1 [28]
B M_DA55 B
m
M_DA56 G7 DQA1_23/DQA_55 G19 M_CAS#0
G6 DQA1_24/DQA_56 CASA0B G16 M_CAS#0 [28]
M_DA57 M_CAS#1
DQA1_25/DQA_57 CASA1B M_CAS#1 [28]
M_DA58 G1
M_DA59 G3 DQA1_26/DQA_58 H22 M_CS#0
M_DA60 J6
// DQA1_27/DQA_59
DQA1_28/DQA_60
CSA0B_0
CSA0B_1
J22 M_CS#0 [28]
M_DA61 J1
M_DA62 J3 DQA1_29/DQA_61 G13 M_CS#1
DQA1_30/DQA_62 CSA1B_0 M_CS#1 [28]
M_DA63 J5 K13
DQA1_31/DQA_63 CSA1B_1
p:
G14
MAA1_8
h
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SeymourXT-S3 MEM Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 02, 2012 Sheet 27 of 55
5 4 3 2 1
5 4 3 2 1
M_DA[63..0]
[27] M_DA[63..0]
M_MA[13..0]
[27] M_MA[13..0]
M_DQM[7..0]
[27] M_DQM[7..0]
M_DQS[7..0]
[27] M_DQS[7..0]
M_DQS#[7..0]
[27] M_DQS#[7..0]
/
[27] M_CLK0 CK VDD CK VDD [27] M_CLK1 CK VDD CK VDD
M_CLK#0 K7 R1 M_CLK#0 K7 R1 M_CLK#1 K7 R1 M_CLK#1 K7 R1
[27] M_CLK#0 K9 CK VDD R9 K9 CK VDD R9 [27] M_CLK#1 K9 CK VDD R9 K9 CK VDD R9
M_CKE0 M_CKE0 M_CKE1 M_CKE1
[27] M_CKE0 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS [27] M_CKE1 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
/x
VRAM_ODT0K1 A1 VRAM_ODT0 K1 A1 VRAM_ODT1K1 A1 VRAM_ODT1 K1 A1
[27] VRAM_ODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ [27] VRAM_ODT1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
M_CS#0 L2 A8 M_CS#0 L2 A8 M_CS#1 L2 A8 M_CS#1 L2 A8
[27] M_CS#0 CS/CS0 VDDQ CS/CS0 VDDQ [27] M_CS#1 CS/CS0 VDDQ CS/CS0 VDDQ
M_RAS#0 J3 C1 M_RAS#0 J3 C1 M_RAS#1 J3 C1 M_RAS#1 J3 C1
[27] M_RAS#0 RAS VDDQ RAS VDDQ [27] M_RAS#1 RAS VDDQ RAS VDDQ
M_CAS#0 K3 C9 M_CAS#0 K3 C9 M_CAS#1 K3 C9 M_CAS#1 K3 C9
[27] M_CAS#0 L3 CAS VDDQ D2 L3 CAS VDDQ D2 [27] M_CAS#1 L3 CAS VDDQ D2 L3 CAS VDDQ D2
M_WE#0 M_WE#0 M_WE#1 M_WE#1
[27] M_WE#0 WE VDDQ WE VDDQ [27] M_WE#1 WE VDDQ WE VDDQ
E9 E9 E9 E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
su
M_DQS2 F3 VDDQ H2 M_DQS3 F3 VDDQ H2 M_DQS4 F3 VDDQ H2 M_DQS6 F3 VDDQ H2
M_DQS0 C7 DQSL VDDQ H9 M_DQS1 C7 DQSL VDDQ H9 M_DQS5 C7 DQSL VDDQ H9 M_DQS7 C7 DQSL VDDQ H9
C C
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
p.
G8 G8 G8 G8
M_DQS#2 G3 VSS J2 M_DQS#3 G3 VSS J2 M_DQS#4 G3 VSS J2 M_DQS#6 G3 VSS J2
M_DQS#0 B7 DQSL VSS J8 M_DQS#1 B7 DQSL VSS J8 M_DQS#5 B7 DQSL VSS J8 M_DQS#7 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
om
T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9
[27] DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
J1 B1 J1 B1 J1 B1 J1 B1
R454 L1 NC/ODT1 VSSQ B9 R451 L1 NC/ODT1 VSSQ B9 R410 L1 NC/ODT1 VSSQ B9 R444 L1 NC/ODT1 VSSQ B9
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
yc
2
2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
PX@ VSSQ G1 PX@ VSSQ G1 PX@ VSSQ G1 PX@ VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
m
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
H5TQ1G63DFR-11C H5TQ1G63DFR-11C H5TQ1G63DFR-11C H5TQ1G63DFR-11C
X76@ X76@ X76@ X76@
//
+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS
B B
1
1
R450 R379 R380 R381 R382 R383 R384 R385
p:
2
+VREFD_Q1 +VREFC_A1 +VREFC_A2 +VREFD_Q2 +VREFC_A3 +VREFD_Q3 +VREFC_A4 +VREFD_Q4
PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
tt
1
1
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
C472
C473
C474
C475
C476
C477
C513
C479
1 1 1 1 1 1 1 1
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
R386 R387 R388 R449 R448 R447 R446 R445
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
2 2 2 2 2 2 2 2
2
2
h
M_CLK0 1 2
R443 56_0402_1% PX@ PX@ PX@
PX@ PX@ PX@ PX@ PX@
PX@
M_CLK#0 1 2 +1.5VGS
R396 56_0402_1% +1.5VGS
PX@ 1 1U_0402_6.3V4Z 1U_0402_6.3V4Z
C506 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
0.01U_0402_16V7K +1.5VGS 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C500
C501
C484
C508
C509
C502
C503
C504
C505
C487
1 1 1 1 1 1 1 1 1 1
C492
C510
C483
C493
C494
C495
C496
C497
C498
C499
C488 C489 C490 C512 C491 C511
PX@
2 2 2 2 2 2 @ 2 2 2 2 2 2 2 2@ 2 2@
10U_0603_6.3V6M 10U_0603_6.3V6M10U_0603_6.3V6M 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
M_CLK1 1 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z
R422 56_0402_1% PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
PX@ PX@ PX@ PX@ PX@ PX@ PX@
A PX@ A
PX@ PX@ PX@ PX@ PX@
M_CLK#1 1 2 PX@ PX@
R436 56_0402_1% 1
PX@ C507
0.01U_0402_16V7K
2
ref 139-02 recommand PX@
VRAM P/N :
add off page Hynix : SA000041S10 (S IC D3 64MX16 H5TQ1G63BFR-11C FBGA C38! ) Security Classification Compal Secret Data Compal Electronics, Inc.
Park SCL recommand pu 60.4 ohm Samsung : SA000041T10 (S IC D3 64MX16 K4W1G1646E-HC11 FBGA C38! ) Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
to 1.5VGS
0619 update update VRAM PN 0619 update THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SeymourXT-S3 VRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 02, 2012 Sheet 28 of 55
5 4 3 2 1
5 4 3 2 1
1
R1454 R1455 C1150
D 150_0603_5% 100K_0402_5% 4.7U_0603_6.3V6K PMV65XP_SOT23-3~D D
2 CMOS@ (20 MIL)
D
3 1 2 1 10U
R1457 1 R1456 1
2
1
3
D 220K_0402_5%
S
CMOS@ 0_0603_5%
G
2 1 2 2 Q72 C1152 C1153 @
G
2
Q71 G PMV65XP_SOT23-3~D 0.1U_0402_16V4Z R02 10U_0603_6.3V6M
2N7002_SOT23 S R1458
CMOS@ 2 2
1
D
W=60mils
1
1
C1154 150K_0402_5%
0.1U_0402_16V4Z
OUT
[37] CMOS_ON#
2 +LCDVDD +LCDVDD_CONN
L29 1
[16] PCH_ENVDD 2 R296 for CMOS shake issue reserve
IN 1 2 C1155 CMOS@
GND
0.1U_0402_16V4Z
Q73 DTC124EK FBMA-L11-201209-221LMA30T_0805 2
1
DTC124EKAT146_SC59-3
/
1 1
3
C1157
@ R1459 C1156
/x
100K_0402_5% 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
2 2
2
su
+LEDVDD B+
C C
1 R1460 2
0_0805_5%
p.
1 1
C1158
680P_0402_50V7K C1159
@ 4.7U_0805_25V6-K
2 2
om
+3VS
JLVDS1 ME@
1
R1462 2 1
yc
2
1
0_0402_5% 3
2 1 R1461 @ 4 3
5 4
4.7K_0402_5% 6 5
6
m
DISPOFF# 7
2
R1464
CH751H-40PT_SOD323-2
// [37] EC_INVT_PWM R1465 1 @ 2 0_0402_5%
[16] LVDS_ACLK#
11
12 11
13 12
B 10K_0402_5% [16] LVDS_A2 13
B
14
[16] LVDS_A2# 14
15
[16] LVDS_A1
2
15
p:
16
[16] LVDS_A1# 16
17
[16] LVDS_A0 18 17
[16] LVDS_A0# 18
[16] PCH_ENBKL R1466 2 1 0_0402_5% [16] EDID_DATA 19
ENBKL [37] 19
tt
[16] EDID_CLK 20
21 20
+3VS 21
1 22
+LCDVDD_CONN 22
(60 MIL) 23
h
23
2
680P_0402_50V7K +3VS 24
R1467 C1160
@ 25 24 31
100K_0402_1% 2 26 25 GND1 32
+3VS_CMOS 26 GND2
[17] USB20_P11 USB20_P11 27 33
USB20_N11 28 27 GND3 34
[17] USB20_N11
1
29 28 GND4 35
30 29 GND5 36
30 GND6
CMOS
STARC_107K30-000001-G2
SP010011S00
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAMERA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 29 of 55
5 4 3 2 1
5 4 3 2 1
+5VS
W=40mils +5VS_HDMI
+5VS RB491D_SC59-3 F1 HDMI@
+3VS D31 HDMI@ 1.1A_6VDC_FUSE
2 1+HDMI_5V 1 2 +5VS_HDMI
2
1
2
C1161
D R1469 HDMI@ D
1M_0402_5% Q74 D32 @ 0.1U_0402_16V4Z 2
HDMI@ HDMI@ BAT54S-7-F_SOT23-3
1
2
G
2N7002H_SOT23-3
1
TMDS_B_HPD# 3 1
[16] TMDS_B_HPD#
2
2
HDMI@ R1470 R1471 HDMI@
R1472 2.2K_0402_5% 2.2K_0402_5%
20K_0402_5%
1
HDMI@
JHDMI1 ME@
1
HDMI_DET 19
18 HP_DET
+5VS_HDMI +5V
17
HDMIDAT_R 16 DDC/CEC_GND
HDMICLK_R 15 SDA
/
14 SCL
13 Reserved
HDMI_CLK-_CK R1473 1 @ 2 0_0402_5% HDMI_CLK-_CONN 12 CEC 20
/x
[16] HDMI_CLK-_CK CK- GND
11 21
HDMI_CLK+_CKR1474 1 @ 2 0_0402_5% HDMI_CLK+_CONN 10 CK_shield GND
C [16] HDMI_CLK+_CK CK+ C
[16] HDMI_TX0-_CK HDMI_TX0-_CK R1475 1 @ 2 0_0402_5% HDMI_TX0-_CONN 9
+3VS 8 D0-
HDMI_TX0+_CK R1476 1 @ 2 0_0402_5% HDMI_TX0+_CONN 7 D0_shield
su
[16] HDMI_TX0+_CK D0+
[16] HDMI_TX1-_CK HDMI_TX1-_CK R1477 1 @ 2 0_0402_5% HDMI_TX1-_CONN 6
5 D1-
HDMI_TX1+_CK R1478 1 @ 2 0_0402_5% HDMI_TX1+_CONN 4 D1_shield
[16] HDMI_TX1+_CK D1+
HDMI@ [16] HDMI_TX2-_CK HDMI_TX2-_CK R1480 1 @ 2 0_0402_5% HDMI_TX2-_CONN 3
D2-
1
p.
R1479 HDMI_TX2+_CK R1481 1 @ 2 0_0402_5% HDMI_TX2+_CONN 1 D2_shield
[16] HDMI_TX2+_CK D2+
0_0402_5%
ACON_HMR2H-AK120C
Pull up R for PCH OR VGA SIDE DC232001400
2
om
Q75A
HDMI@ L30 HDMI@
2
yc
1 6 HDMICLK_R 680 +-5% 8P4R
[16] HDMICLK_NB
HDMI_CLK-_CK 4 3 HDMI_CLK-_CONN HDMI_CLK-_CONN 5 4
4 3
5
HDMI_CLK+_CONN 6 3
WCM-2012HS-900T HDMI_TX1-_CONN 7 2
B 4 3 HDMIDAT_R HDMI_TX1+_CONN 8 1 SD309680080 B
m
[16] HDMIDAT_NB
L31 HDMI@
Q75B HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN RP1 HDMI@ S ROW RES 1/16W 680 +-5% 8P4R
HDMI@ 1 2
2N7002DW-T/R7_SOT363-6 680 +-5% 8P4R
//HDMI_TX0-_CK 4
4 3
3 HDMI_TX0-_CONN HDMI_TX0-_CONN 5 4
HDMI_TX0+_CONN 6 3
WCM-2012HS-900T HDMI_TX2-_CONN 7 2
HDMI_TX2+_CONN 8 1
HDMIDAT_R L32 HDMI@ +3VS
RP2 HDMI@
p:
HDMI_TX1+_CK 1 2 HDMI_TX1+_CONN
1 2
1
D
HDMICLK_R 2
HDMI_TX1-_CK 4 3 HDMI_TX1-_CONN G
4 3 Q76
S
tt
3
WCM-2012HS-900T HDMI@
3
2N7002H_SOT23-3
D33 @ L33 HDMI@
h
HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN
4 3
WCM-2012HS-900T
A A
1
1
R1505 1 2 0_0402_5% EC_WL_WAKE#_R R1520 1 @ 2 0_0402_5% 1 1
1 [37] EC_WL_WAKE# PCH_PCIE_WAKE# [15,32] 1
R1488
0_0603_5% C1172 C1173
0.1U_0402_16V4Z 0.1U_0402_16V4Z
JWLAN1 ME@ 2 2
2
1 2
@ 3 WAKE# 3.3V 4 R1503
R1490 1 2 0_0402_5% BT_DISABLE_R 5 NC GND 6 +1.5VS_WLAN 0_0402_5%
[18] PCH_BT_ON# NC 1.5V
[14] WLAN_CLKREQ# WLAN_CLKREQ# 7 8 LPC_FRAME#_R USB20_N2_WLAN 1 2 USB20_N2
R1491 1 2 0_0402_5% 9 CLKREQ# NC 10 LPC_AD3_R
[18] BT_DISABLE GND NC
11 12 LPC_AD2_R USB20_P2_WLAN 1 2 USB20_P2
[14] CLK_PCIE_WLAN1# REFCLK- NC
13 14 LPC_AD1_R 0_0402_5%
[14] CLK_PCIE_WLAN1 15 REFCLK+ NC 16 LPC_AD0_R R1504
PCI_RST#_R 17 GND NC 18
CLK_PCI_DB 19 NC GND 20 R1492 1 2 0_0402_5%
NC NC PCH_WL_OFF# [17]
21 22 WL_RST# 2 1 PLT_RST#
GND PERST# PLT_RST# [17,32,37] +3VALW
23 24 R1494 1 2 @ 0_0402_5% 0_0402_5% R1493
[14] PCIE_PRX_DTX_N2 PERn0 +3.3Vaux +3VALW
25 26 R1495 1 2 0_0402_5%
[14] PCIE_PRX_DTX_P2 PERp0 GND +3VS_WLAN
27 28
29 GND +1.5V 30 R1496 1 2 0_0402_5% @ SMB_CLK_S3
GND SMB_CLK SMB_CLK_S3 [12,14,38] C1273
31 32 R1497 1 2 0_0402_5% @ SMB_DATA_S3 SMB_DATA_S3 [12,14,38] @
[14] PCIE_PTX_C_DRX_N2 PETn0 SMB_DATA
33 34 7 8 1 2
[14] PCIE_PTX_C_DRX_P2 35 PETp0 GND 36 NC VCC
USB20_N2_WLAN 0.1U_0402_16V4Z
+3VS_WLAN 37 GND USB_D- 38 USB20_P2_WLAN USB20_N2_WLAN 5 6 USB20_N2
39 NC USB_D+ 40 D- HSD- USB20_N2 [17]
41 NC GND 42 USB20_P2_WLAN 3 2 USB20_P2
/
NC LED_WWAN# D+ HSD+ USB20_P2 [17]
43 44
100_0402_1% 45 NC LED_WLAN# 46 4 1
NC LED_WPAN# GND OE# WLAN_USB_ON# [37]
R1498 47 48
1 2 49 NC +1.5V 50
/x
EC_TX U1
[37] EC_TX NC GND
1
EC_RX 1 2 51 52 @
[37] EC_RX NC +3.3V
R1499 TS3USB31RSER_QFN8_1P5X1P5 R1519 @
100_0402_1% 53 54 0_0402_5%
GND GND +3VS +3VS_WLAN +3VS_WLAN_AOAC
2
BELLW_80019-1021 nonAOAC@ AOAC@
2
For EC to detect DC040004X00 R1518 2 1 0_0603_5% R1500 2 1 0_0603_5%
su
R1501
2
debug card insert. 100K_0402_5% 2
1 1
C1170 @
C1171
1
0.1U_0402_16V4Z 10U_0603_6.3V6M
2 2
p.
+3VALW
Q77 AO3413_SOT23-3
D
3 1 1
om
AOAC@
AOAC@ C1174
0.1U_0402_16V4Z
G
2
2
[37] AOAC_ON#
1
R1502 AOAC@
Mini-Express Card(SSD) SSD Active:4.5W(1.5A) 150K_0402_5% C1175
0.1U_0402_16V4Z
AOAC@ 2
+3VS_SSD +3VS +3VS_SSD
yc
J14
0.1U_0402_16V4Z 10U_0603_6.3V6M
1 2
1 2
1 1 1 1
@ 9/18 Increase for Intel AOAC function
C1176 C1177 C1178 C1179 JUMP_43X79
@
m
2 2 2 2 JSSD1 ME@
1 2
10U_0603_6.3V6M 3 WAKE# 3.3V 4
0.01U_0402_16V7K 5 NC GND 6
11/07 Change type to 0603 NC 1.5V
7 8
CLKREQ# NC
9
11
13
GND
REFCLK-
NC
NC
10
12
14
//
15 REFCLK+ NC 16
3
17 GND NC 18 3
19 NC GND 20
0.01U_0402_16V7K C1181 21 NC NC 22
SATA_PRX_DTX_C_P0 2 1 SATA_DTX_IRX_P0 23 GND PERST# 24
p:
[13] SATA_PRX_DTX_C_P0 SATA_PRX_DTX_C_N0 2 1 SATA_DTX_IRX_N0 25 PERn0 +3.3Vaux 26
[13] SATA_PRX_DTX_C_N0 0.01U_0402_16V7K C1180 27 PERp0 GND 28
29 GND +1.5V 30
SATA_PTX_DRX_N0 31 GND SMB_CLK 32
[13] SATA_PTX_DRX_N0 PETn0 SMB_DATA
SATA_PTX_DRX_P0 33 34
[13] SATA_PTX_DRX_P0 PETp0 GND
35 36
tt
37 GND USB_D- 38
+3VS_SSD 39 NC USB_D+ 40
41 NC GND 42
43 NC LED_WWAN# 44
45 NC LED_WLAN# 46
h
@ 47 NC LED_WPAN# 48
R553 0_0402_5% 49 NC +1.5V 50
1 2 mSATA_DET#_R 51 NC GND 52
[18] mSATA_DET# NC +3.3V
For SSD use: 53 54
GND GND
BELLW_80019-1021
DC040004X00
4 4
Security Classification
2011/07/21
Compal Secret Data
2012/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 31 of 55
A B C D E
5 4 3 2 1
+3VALW +3V_LAN
D D
+LAN_VDD10
L34
1 2 J15
U47 8105@ +LAN_REGOUT
2.2UH +-5% NLC252018T-2R2J-N 1 2
1 2
JUMP_43X79
2
Layout Note: L39 must be
@
within 200mil to Pin36, C1184 C1182
RTL8105E-VL-CGT C700,C738 must be within 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
1
SA00003PO40 200mil to LL1 X5R
+LAN_REGOUT: Width
=60mil
U47
/
0_0603_5% L35
2
16 1 MDI0+
[14] LAN_CLKREQ# CLKREQB MDIP0 2 MDI0+ [33]
MDI0- C1187 C1188
/x
25 MDIN0 4 MDI1+ MDI0- [33] +3V_LAN
1U_0402_6.3V4Z 0.1U_0402_16V4Z
[17,31,37] PLT_RST# MDI1+ [33]
1
PERSTB MDIP1 5 MDI1-
19 MDIN1 7 MDI2+ MDI1- [33]
[14] CLK_PCIE_LAN 20 REFCLK_P NC/MDIP2 8 MDI2+ [33] 1 2
[14] CLK_PCIE_LAN# REFCLK_N NC/MDIN2
MDI2-
MDI2- [33] Close to Pin 21
C 10 MDI3+ 0.1U_0402_16V4Z C1189 C
NC/MDIP3 11 MDI3- MDI3+ [33] 1 2
NC/MDIN3 MDI3- [33]
su
Pin 16 and Pin 28 are OD pins LAN_XTALI 43 0.1U_0402_16V4Z C1190
CKXTAL1 1 2
LAN_XTALO 44 13 0.1U_0402_16V4Z C1191
CKXTAL2 DVDD10 +LAN_VDD10
29 1 2
DVDD10 41 GIGA@ 0.1U_0402_16V4Z C1192
1 R1508 2 0_0402_5% PCIE_WAKE#_R 28 DVDD10 +3V_LAN +LAN_VDDREG 1 2
[37] LAN_WAKE# LANW AKEB
p.
1 R1509 2 0_0402_5% GIGA@ 0.1U_0402_16V4Z C1193
[15,31] PCH_PCIE_WAKE#
@ ISOLATEB 26 27
+3V_LAN
2 1 1 2
ISOLATEB DVDD33 39 0_0603_5% L36 GIGA@ 0.1U_0402_16V4Z C1194
DVDD33
2
14 12 C1195 C1196
NC/SMBCLK AVDD33 +3V_LAN
om
@ 2 R1510 1 10K_0402_5% 15 42 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
1
+3V_LAN @ 1 R1511 2 1K_0402_5% 38 NC/SMBDATA AVDD33 47
+3V_LAN GPO/SMBALERT AVDD33 X5R
48
AVDD33
ENSWREG 33
ENSW REG
1
21
EVDD10 +LAN_EVDD10
R1512 34 Close to Pin 3,6,9,13,29,41,45
+LAN_VDDREG VDDREG
10K_0402_5% 35 3
VDDREG AVDD10 +LAN_VDD10 +LAN_VDD10
yc
6
@ AVDD10 9
2
1
49 0.1U_0402_16V4Z C1198
PGND
m
R1514 R1515 1 2
1K_0402_5% 0_0402_5% 0.1U_0402_16V4Z C1199
RTL8111F-CGT_QFN48_6x6 1 2
B B
GIGA@ GIGA@ 0.1U_0402_16V4Z C1200
2
ISOLATEB ENSWREG 1 2
SA00004Y700
// GIGA@ 0.1U_0402_16V4Z
1
C1201
2
R1517 GIGA@ 0.1U_0402_16V4Z C1202
R1516 0_0402_5% 1 2
15K_0402_5% @ GIGA@ 0.1U_0402_16V4Z C1203
p:
LAN_XTALI
NC OSC L: Disable
1 2
OSC NC
27P_0402_50V8J
27P_0402_50V8J
1 25MHZ_20PF_FSX3M-25.M20FDO 1
h
C1204
C1205
R02
2 2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN-RTL8111F/8105E
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 32 of 55
5 4 3 2 1
5 4 3 2 1
T71
MDI3+ 1 16 MDO3+ @
[32] MDI3+ TD+ TX+ J17
MDI3- 2 15 MDO3-
[32] MDI3- 3 TD- TX- 14 1 2
@ MCT3
D D34 4 CT CT 13 CHASSIS1_GND D
AZC099-04S.R7G_SOT23-6 5 NC NC 12
MDI2+ 1 4 MDI3+ 6 NC NC 11 MCT2 Spark Gap
I/O1 I/O3 MDI2+ 7 CT CT 10 MDO2+ JUMP_48X40
[32] MDI2+ 8 RD+ RX+ 9
MDI2- MDO2- R1521
[32] MDI2- RD- RX- 1 2 1 2
2 5 75_0805_5%
GND VDD BOTHHAND_NS0013LF C1206
GIGA@ 10P_0603_50V8-J
Place Close to T1,T2
MDI3- 3 6 MDI2- R02
I/O2 I/O4 2 1
T72 CHASSIS2_GND
LSE-200NX3216TRLF_1206-2
Place Close to T71 MDI0+ 1 16 MDO0+
[32] MDI0+ TD+ TX+
MDI0- 2 15 MDO0- DL2 @
[32] MDI0- 3 TD- TX- 14 MCT0
4 CT CT 13 @
NC NC J18
5 12
/
6 NC NC 11 MCT1 1 2
1 CT CT
MDI1+ 7 10 MDO1+ CHASSIS1_GND
[32] MDI1+ 8 RD+ RX+ 9
@ C1207 MDI1- MDO1-
/x
[32] MDI1- RD- RX- Spark Gap
D35 0.01U_0402_16V7K
AZC099-04S.R7G_SOT23-6 2 JUMP_48X40
C C
MDI1+ 1 4 MDI0+ BOTHHAND_NS0013LF
I/O1 I/O3
@
su
J19
2 5 1 2
GND VDD
Spark Gap
p.
MDI0- 3 6 MDI1- JUMP_48X40
I/O2 I/O4
JRJ1 ME@
om
Place Close to T72
12
GND
11
GND
10
MDO0+ 1 GND
D34/D35
yc
PR1+ 9
MDO0- 2 GND CHASSIS2_GND
1'S PN:SC300001G00 MDO1+ 3
PR1-
PR2+
B
2'S PN:SC300002E00 B
m
MDO2+ 4 CHASSIS1_GND
PR3+
MDO2- 5
PR3-
// MDO1- 6
PR2-
MDO3+ 7
PR4+
MDO3- 8
PR4-
p:
SANTA_130460-3
DC231112261
tt
h
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN_Transformer
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 33 of 55
5 4 3 2 1
5 4 3 2 1
1
REMOTE1+ C
1 @ C1210 2 Q79
1
D 100P_0402_50V8J B MMST3904-7-F_SOT323-3 D
C1211 +3VS R1524 2 E
3
2200P_0402_50V7K 10K_0402_5% REMOTE1-
2 REMOTE1- @
U49
2
1 10 EC_SMB_CK2
VDD SMCLK EC_SMB_CK2 [14,23,37]
REMOTE2+
REMOTE1+ 2 9 EC_SMB_DA2 REMOTE2+
Under mSSD
1 DP1 SMDATA EC_SMB_DA2 [14,23,37]
2 1
1
C1213 @ REMOTE1- 3 8 C
2200P_0402_50V7K C1212 DN1 ALERT# @ C1214 2 Q80
2 REMOTE2- 0.1U_0402_16V4Z REMOTE2+ 4 7 100P_0402_50V8J B MMST3904-7-F_SOT323-3
1 DP2 THERM# 2 E
3
REMOTE2- 5 6 REMOTE2-
DN2 GND
/
EMC1403-2-AIZL-TR_MSOP10
REMOTE1,2+/-:
Trace width/space:10/10 mil
/x
Address 1001_101xb
Trace length:<8"
C
FAN1 Conn C
su
+5VS
0_0603_5%
R1525
JFAN1 ME@
1 2 +5VS_FAN 1
p.
2 1
[37] EC_TACH 2
[37] EC_FAN_PWM 3
4 3
5 4
2 G1 R
om
6
C1215 G2 H25 H17
10U_0603_6.3V6M HOLEA HOLEA
1 ACES_85204-04001
SP02000CW00
1
10U
yc
H_2P5X3P1N H_2P5X3P1N FD1 FD2 FD3 FD4
B
E B
1
R
橢橢橢 橢橢橢
H9 H6 H10 H11 H7 H8 H13 H15
//
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA H29 H14 H16 H12
HOLEA HOLEA HOLEA HOLEA M/B M/B KB
1
p:
1
1
H_2P5 CHASSIS1_GND
H_3P0 H_2P5 H_2P5 H_2P5 H_2P5 H_2P5N
H_2P5 H_4P0 H_5P4X2P5 H_5P4X2P5 H_5P4X2P5
tt
A
h
2P5 * 9 pcd
1 1
R435 0_0805_5% 8
/
1 2 +3VS_HDD 9 3.3V
+3VS 3.3V
10
11 3.3V
/x
12 GND
13 GND
R1526 0_0805_5% 14 GND
1 2 +5VS_HDD 15 V5
+5VS V5
16
17 V5
su
18 GND
2 2
19 RSVD
20 GND
21 V12
+5VS_HDD 10U +3VS_HDD 22 V12
V12
p.
R02
1 1 1 1 SANTA_192701-1
1
@ DC010006J00
C1218 C1219 C1220 @ R02 C1221 C1222
om
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0402_6.3V6K 10U_0603_6.3V6M 0.1U_0402_16V4Z
2
2 2 2 2
yc
m
//
3 3
p:
tt
h
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD/BT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 35 of 55
A B C D E F G H
5 4 3 2 1
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2 1 1 1
0_0603_5%
1
FBMA-L11160808601LMA10T_2P
C1226
C1227
C1228
C1229
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1 1 2 @ @
2
2 2 2
C1231
C1232
C1230
C1233
2 2 2 1
Place near Pin1 Place near Pin9
600ohms @100MHz 2A
P/N: SM01000EE00
D D
R1531 Place near Pin25 Place near Pin38
0_0805_5%
+5VS 1 2 +5VS_PVDD
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
2 1 1 +3VDD_CODEC
C1235
C1236
C1234
1 2 2 +IOVDD_CODEC
+MIC1_VREFO_L
U50
39
46
25
38
9
Power down (PD#) power stage for save power Vendor recommend. 2.2K
2
PVDD1
PVDD2
AVDD1
AVDD2
DVDD1
DVDD-IO
0V: Power down power stage R1537
3.3V: Power up power stage 2.2K_0402_5%
MIC_JD 1 2 COMBOJACK 47 24 Vendor recommend. 2.2u
1
R1533 0_0402_5% DAPD/COMB_JACK LINE1-R(PORT-C-R)
EC_MUTE# 1 2 EC_MUTE#_R 4 23
[37] EC_MUTE# PD# LINE1-L(PORT-C-L)
R1538 0_0402_5%
HDA_SDOUT_AUDIO 5 22 MIC_EXTR_C 1 2 2 1 EXT_MIC
+3VS [13] HDA_SDOUT_AUDIO SDATA-OUT MIC1-R(PORT-B-R) EXT_MIC [38]
C1237 2.2U_0402_6.3V6M R1534 1K_0402_5% external MIC
HDA_BITCLK_AUDIO 6 21 MIC_EXTL_C 1 2
[13] HDA_BITCLK_AUDIO BIT-CLK MIC1-L(PORT-B-L) C1238 2.2U_0402_6.3V6M
/
2
HDA_SDIN0 2 1 SDATA_IN 8 17
[13] HDA_SDIN0 SDATA-IN MIC2-R(PORT-F-R)
R1535 22_0402_5% R1536
4.7K_0402_5% 16 0110 delete R1539
MIC2-L(PORT-F-L)
/x
@
10 15
[13] HDA_SYNC_AUDIO
1
SYNC LINE2-R(PORT-E-R)
HDA_RST_AUDIO# 11 14
[13] HDA_RST_AUDIO# RESET# LINE2-L(PORT-E-L)
PC_BEEP 12
PCBEEP
40 SPK_L2+
su
2 1 JDREF 19 SPK-OUT-L+
20K_0402_1% R1541 JDREF 41 SPK_L1-
C C
20 SPK-OUT-L-
MONO-OUT(PORT-H) 44 SPK_R1-
Internal Speaker
2 1 SENSEA 13 SPK-OUT-R-
[38] PLUG_IN# Sense A
39.2K_0402_1% R1543 45 SPK_R2+
18 SPK-OUT-R+
Sense-B
p.
MIC Sense CBN 35 33 HPOUT_R 2 1
CBN HPOUT-R(PORT-A-R) HP_OUTR [38]
75_0402_5% R1544 Headphone
R939 place near pin13 2 1 CBP 36 32 HPOUT_L 2 1
HP_OUTL [38]
C1239 2.2U_0402_6.3V6M CBP HPOUT-L(PORT-A-L) 75_0402_5% R1545
Capless HP Sense 2 1 34 48
om
C1240 2.2U_0402_6.3V6M CPVEE SPDIF-OUT 0110 delete R1539
R940 place near pin34 2 1 28
C1241 4.7U_0603_6.3V6K LDO-CAP 3 DMIC_CLK_R 2 1
GPIO1/DMIC-CLK DMIC_CLK [38]
0_0402_5% R937
29 2 DMIC_DATA_R 2 1
MIC2-VREFO GPIO0/DMIC-DATA DMIC_DATA [38]
0_0402_5% R1548
30
MIC1-VREFO-R
+MIC1_VREFO_L 31
MIC1-VREFO-L
yc
42 27 Place next to pin 27
PVSS1 VREF
1U_0402_6.3V6K
0.1U_0402_16V4Z
43 26 1
PVSS2 AVSS1
1
C1242
C1243
7 37
DVSS AVSS2
2
49 2
Thermal PAD
// ALC259Q-VC2-GR_QFN48_6X6
R1549
1 2
B B
0_0402_5%
R1550 HDA_RST_AUDIO#
Pin Assignment Location Function 1 2
0_0402_5% HDA_SYNC_AUDIO
EMI
p:
R1551
SPK-OUT (Pin40/41/44/45) Internal Int Speaker 1 2 HDA_SDOUT_AUDIO
@ 0_0402_5%
1 2 HDA_BITCLK_AUDIO
Capless HP-OUT (Pin32/33) External Headphone out
R1552 @ 27_0402_5%
tt
1 1 1 1
MIC1(Pin21/22) External Mic in
C1247
C1244
C1245
C1246
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
@ 33P_0402_50V8J
2 2 2 2
wide 25MIL
h
@ @ @
JSPK1 ME@
SPK_R2+ R1553 1 2 0_0603_5% SPK_R2+_CONN 1
SPK_R1- R1555 1 2 0_0603_5% SPK_R1-_CONN 2 1
SPK_L1- R1554 1 2 0_0603_5% SPK_L1-_CONN 3 2 5
GND GNDA
SPK_L2+ R1556 1 2 0_0603_5% SPK_L2+_CONN 4 3 G1 6
4 G2
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1 1 1 1 ACES_88266-04001
SP02000K200
C1248
C1249
C1250
C1251
SE074102K80
Combo Jack detect (normal open) PC Beep
@ 2 @ 2 @ 2 @ 2
0.1U_0402_16V7K
1
A A
3
1 @
R1558
@ @ 10K_0402_5%
2
D38 D39
PACDN042Y3R_SOT23-3 PACDN042Y3R_SOT23-3
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec_ALC259Q-VC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 36 of 55
5 4 3 2 1
+3VLP
1
C1254
+3VALW 100P_0402_50V8J
2
Vcc 3.3V +/- 5%
L38
FBM-11-160808-601-T_0603 +3VALW
1 1 1 1 1 1
+EC_VCCA R694 100K +/- 5%
0.1U_0402_16V4Z
C1255
0.1U_0402_16V4Z
C1256
0.1U_0402_16V4Z
C1257
0.1U_0402_16V4Z
C1258
1000P_0402_50V7K
C1261
1000P_0402_50V7K
C1259
1 2
+3VALW +EC_VCCA
1 1 Board ID R695 VAD_BID min V AD_BID typ VAD_BID max
C1260
C1262 2 2 2 2 2 2
0 0 0 V 0 V 0 V MP
111
125
0.1U_0402_16V4Z 1000P_0402_50V7K U51
22
33
96
67
9
1 2 2 ECAGND 2
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V PVT
L39
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
FBM-11-160808-601-T_0603 18K +/- 5%
2 0.436 V 0.503 V 0.538 V DVT
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT
1 21
[18] GATEA20 2 GATEA20/GPIO00 GPIO0F 23 BEEP#
[18] KBRST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# [36]
3 26 NOVO#
[13] SERIRQ SERIRQ GPIO12 NOVO# [38]
4 27 ACOFF +3VS +3VALW
[13,31] LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF [43]
LPC_AD3 5
[13,31] LPC_AD3
2
LPC_AD2 7 LPC_AD3 +5VALW
[13,31] LPC_AD2 LPC_AD2 PWM Output
1
LPC_AD1 8 63 BATT_TEMP
[13,31] LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP [42]
LPC_AD0 10 LPC & MISC 64 R1562
[13,31] LPC_AD0 LPC_AD0 GPIO39
2 1 2 1 65 R1561 100K_0402_1%
ADP_I/GPIO3A ADP_I [42,43]
@ C1263 22P_0402_50V8J @ R1560 10_0402_5% 12 AD Input 66 10K_0402_5%
[17] CLK_PCI_EC
1
13 CLK_PCI_EC GPIO3B 75 BRDID @ R1566 BRDID
[17,31,32] PLT_RST#
2
1 2 EC_RST# 37 PCIRST#/GPIO05 GPIO42 76 EC_FAN_PWM USB_ON# 1 2
+3VALW
2
R1563 47K_0402_5% EC_SCI# 20 EC_RST# IMON/GPIO43 R01
[18] EC_SCI# EC_SCII#/GPIO0E
2 BATT_LEN# 38 10K_0402_5% R1564
[42] BATT_LEN# GPIO1D 68
C1264 DAC_BRIG/GPIO3C 70
For DS3 +3VALW
33K_0402_5%
0.1U_0402_16V4Z EN_DFAN1/GPIO3D 71
DA Output
1
1 KSI0 55 IREF/GPIO3E 72 +3VALW
KSI0/GPIO30 CHGVADJ/GPIO3F SUSWARN# [15]
1
KSI1 56
/
KSI2 57 KSI1/GPIO31 EC_MUTE# 1 R1565 2 10K_0402_5% R5118
KSO[0..15] KSI3 58 KSI2/GPIO32 83
EC_MUTE# [36] 10K_0402_5%
[38] KSO[0..15] KSI4 59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 USB_ON#
/x
KSI[0..7] KSI4/GPIO34 USB_EN#/GPIO4B USB_ON# [38,39]
KSI5 60 85 +3VS
2
[38] KSI[0..7] KSI6 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 EC_GPIO4D 1 R4957 2EC_WL_WAKE# EC_WL_WAKE# [31] EC_GPIO4D +3VALW
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D
KSI7 62 87 TP_CLK 0_0402_5% TP_CLK R1567 1 2 2.2K_0402_5%
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK [38]
+3VALW KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA [38]
1
R1568 1 @ 2 47K_0402_5% KSO1 KSO1 40 TP_DATA R1569 1 2 2.2K_0402_5%
KSO2 41 KSO1/GPIO21 R1572
R1570 1 @ 2 47K_0402_5% KSO2 KSO3 42 KSO2/GPIO22 97 CPU1.5V_S3_GATE NTC_V_R @1 2
su
CPU1.5V_S3_GATE [10,40] 100K_0402_1%
KSO4 43 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 98 C1319 100P_0402_50V8J
KSO4/GPIO24 WOL_EN/GPXIOA01 @
KSO5 44 99 BATT_TEMP 1 2
KSO5/GPIO25 Int. K/B ME_FLASH [13]
2
KSO6 45 HDA_SDO/GPXIOA02 109 NTC_V_R 2 R1571 1 0_0402_5% C1265 100P_0402_50V8J
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 NTC_V [42]
PCH_PWR_EN ACIN 1 2
+3VALW KSO7/GPIO27 SPI Device Interface
+3VS KSO8 47 C1266 100P_0402_50V8J
R1574 KSO9 48 KSO8/GPIO28 119 PCH_PWR_EN 1 2
p.
PCH_PWR_EN [40,42]
1
1 2 EC_SMB_CK1 KSO10 49 KSO9/GPIO29 SPIDI/GPIO5B 120 +3VALW R1573 @ 4.7K_0402_5%
2.2K_0402_5% KSO11 50 KSO10/GPIO2A SPIDO/GPIO5C 126 AOAC_ON#
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 AOAC_ON# [31]
R1577 KSO12 51 128 R1634
KSO12/GPIO2C SPICS#/GPIO5A SUSACK# [15]
1
R1575 R1576 1 2 EC_SMB_DA1 KSO13 52 100K_0402_5% @
2.2K_0402_5% KSO14 53 KSO13/GPIO2D +3VALW
2.2K_0402_5% 2.2K_0402_5% For DS3
2
KSO14/GPIO2E
om
KSO15 54 73 R1641
KSO15/GPIO2F ENBKL/GPIO40 ENBKL [29]
KSO16 81 74 100K_0402_5%
DPWROK_EC [15]
1
[38] KSO16 82 KSO16/GPIO48 PECI_KB930/GPIO41 89 WLAN_USB_ON#_R R1595 2 1 0_0402_5%
[31]For WLAN USB switch control
EC_SMB_CK2 KSO17 @
WLAN_USB_ON#
2
EC_SMB_DA2 [38] KSO17 KSO17/GPIO49 FSTCHG/GPIO50 90 BATT_CHG_LED#
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# [38]
1 1 91 WLAN_USB_ON#_R R1640
@ @ EC_SMB_CK1 77 CAPS_LED#/GPIO53 92 100K_0402_5%
[42,43] EC_SMB_CK1 EC_SMB_CK1/GPIO44 GPIO PWR_LED#/GPIO54 PWR_LED# [38] +3VLP
C1267 C1268 EC_SMB_DA1 78 93 BATT_LOW_LED#
[42,43] EC_SMB_DA1 BATT_LOW_LED# [38]
2
100P_0402_50V8J 100P_0402_50V8J EC_SMB_CK2 79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95 SYSON LID_SW#
2 2 [14,23,34] EC_SMB_CK2 SM
EC_SMB_CK2/GPIO46 Bus SYSON/GPIO56 SYSON [40,45,46]
EC_SMB_DA2 80 121 @
yc
[14,23,34] EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON [50]
1
127 PM_SLP_S4# [15] KB9012A2 work around
PM_SLP_S4#/GPIO59 R1578
47K_0402_5% VR_HOT# 1 R1579 2 H_PROCHOT# [42,6]
[50] VR_HOT#
6 100 0_0402_5%
[15] PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# [15]
14 101 EC_LID_OUT#
[15] PM_SLP_S5# EC_LID_OUT# [18]
2
PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04
1
EC_SMI# 15 102 Turbo_V D
m
[18] EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 Turbo_V [42]
16 103 H_PROCHOT#_EC R1580 2 1 0_0402_5% H_PROCHOT#_EC 2
+3VS
For DS3 [29] CMOS_ON#
2 DS3@ 1 17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104 MAINPWON_R R1591 2 @ 1 0_0402_5%
PROCHOT [42]
G
1
[15,40] SLP_SUS# GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON [42,44]
R1590 0_0402_5% 18 GPO 105 BKOFF# Q82 S C1269
[7] DRAMRST_CNTRL_EC BKOFF# [29]
3
19 GPIO0C BKOFF#/GPXIOA08 106 PBTN_OUT# 2N7002H_SOT23-3 47P_0402_50V8J
GPIO0D GPIO PBTN_OUT#/GPXIOA09 PBTN_OUT# [15] 2
EC_INVT_PWM 25 107 PCH_APWROK [15]
1
R1581
2 EC_TACH
10K_0402_5%
[29]
[34]
EC_INVT_PWM
EC_TACH
EC_TACH
EC_PME#
28
29
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
// PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
108 SA_PGOOD [48]
EC_TX 30 EC_PME#/GPIO15
[31] EC_TX EC_TX/GPIO16
EC_RX 31 110 ACIN
[31] EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN [15,23,43]
PCH_PWROK 32 112 EC_ON +3VALW
[15] PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON [44]
EC_FAN_PWM 34 114 ON/OFF [38]
[34] EC_FAN_PWM SUSP_LED#/GPIO19 ON/OFF/GPXIOD03
36 GPI 115 LID_SW#
p:
LID_SW# [38]
2
2 1 NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116
NUM_LED#: NC SUSP#/GPXIOD05
SUSP#
SUSP# [10,40,45,46,47,49]
@ R1582 117 PCH_HOT#_R R1583 2 @ 1 0_0402_5%
GPXIOD06 PCH_HOT# [14]
10K_0402_5% 118 PECI_KB9012 1 2 R1585
PECI_KB9012/GPXIOD07 H_PECI [18,6]
AGND/AGND
[15] SUSCLK
1
0_0402_5% XCLKO/GPIO5E V18R
1
GND0
1
C1270 R1588
1
4.7U_0603_6.3V6K 2 0_0402_5%
1
2 LAN_WAKE# [32]
h
R1587 C1271
11
24
35
94
113
69
100K_0402_5% 20P_0402_50V8
2
2 R1589 1
2
SYSON EC_PME# 1 3
S
PCI_PME# [17]
C1272
ECAGND Q83 @
0.1U_0402_10V6K
2N7002_SOT23
G
2
1 +3VALW
PN : SA00004OB20 S IC KB9012QF A3 LQFP 128P KB CONTROLLER @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 37 of 55
28
KSI[0..7] GND1 27
KSI[0..7] [37] GND2
KSI1 26
KSO[0..17] KSO16 C1277 1 2 @ 100P_0402_50V8J KSI7 25 26
+3VALW KSO[0..17] [37] 25
KSI6 24
KSO17 C1278 1 2 @ 100P_0402_50V8J KSO9 23 24
KSI4 22 23
22
2
KSO2 C1275 1 2 @ 100P_0402_50V8J KSO1 C1279 1 2 @ 100P_0402_50V8J KSI5 21
R1592 KSO0 20 21
100K_0402_5% KSO15 C1280 1 2 @ 100P_0402_50V8J KSO7 C1276 1 2 @ 100P_0402_50V8J KSI2 19 20
KSI3 18 19
KSO6 C1281 1 2 @ 100P_0402_50V8J KSI2 C1282 1 2 @ 100P_0402_50V8J KSO5 17 18
1
D40 KSO1 16 17
NOVO# 2 KSO8 C1283 1 2 @ 100P_0402_50V8J KSO5 C1284 1 2 @ 100P_0402_50V8J KSI0 15 16
[37] NOVO# 15
1 NOVO_BTN# KSO2 14
ON/OFF 3 KSO13 C1285 1 2 @ 100P_0402_50V8J KSI3 C1286 1 2 @ 100P_0402_50V8J KSO4 13 14
[37] ON/OFF KSO7 12 13
KSO12 C1287 1 2 @ 100P_0402_50V8J KSO14 C1288 1 2 @ 100P_0402_50V8J KSO8 11 12
DAN202UT106_SC70-3 KSO6 10 11
KSO11 C1289 1 2 @ 100P_0402_50V8J KSI7 C1290 1 2 @ 100P_0402_50V8J KSO3 9 10
KSO12 8 9
KSO10 C1291 1 2 @ 100P_0402_50V8J KSI6 C1292 1 2 @ 100P_0402_50V8J KSO13 7 8
KSO14 6 7
KSO3 C1293 1 2 @ 100P_0402_50V8J KSI5 C1294 1 2 @ 100P_0402_50V8J KSO11 5 6
+3VLP KSO10 4 5
KSO4 C1295 1 2 @ 100P_0402_50V8J KSI4 C1296 1 2 @ 100P_0402_50V8J KSO15 3 4
KSO16 2 3
2
2
KSI0 C1297 1 2 @ 100P_0402_50V8J KSO9 C1298 1 2 @ 100P_0402_50V8J KSO17 1
1
R1593 KSO0 C1299 1 2 @ 100P_0402_50V8J KSI1 C1300 1 2 @ 100P_0402_50V8J
100K_0402_5% JKB1
ON/OFFBTN# ACES_88514-02601-071
1
ME@
J16
R1596
1 2 2 1
0_0402_5% ON/OFF
SHORT PADS
/
/x
+3VS
su
2A/Active Low
JTP1 ME@
C1301 +5VALW +USB2_VCCA
8
0.1U_0402_16V4Z 7 GND C1320 U55 R02
GND W=80mils
p.
0.1U_0402_16V7K 1 8
6 1 2 2 GND VOUT 7
TP_CLK 5 6 3 VIN VOUT 6
[37] TP_CLK 5 VIN VOUT
TP_DATA 4 4 5
[37] TP_DATA 3 4 [37,39] USB_ON# EN FLG USB_OC4# [17]
1 1 3
SMB_CLK_S3 2 G547I2P81U_MSOP8 1 C1321
[12,14,31] SMB_CLK_S3
om
@ C1302 C1303 @ SMB_DATA_S3 1 2
[12,14,31] SMB_DATA_S3 1
100P_0402_50V8J 100P_0402_50V8J 470P_0402_50V7K
2 2
3
ACES_88514-00601-071 2
C1304
C1305
0.1U_0402_10V6K
0.1U_0402_10V6K
1 1 SP010014M00
@ D42
PSOT24C_SOT23-3 @ @
2 2
1
yc
m
+USB2_VCCA +3VS
//
+3VS +USB2_VCCA
IO Board
C1306
C1307
Power Board
0.1U_0402_10V6K
0.1U_0402_10V6K
1 1
p:
PWR_LED# 4 5 5 6 G2 7 10 9
[37] PWR_LED# 4 5 G1 10
[37] LID_SW# LID_SW# 3 PWR_LED# 4 11
2 3 3 4 [17] USB20_P10 12 11
ON/OFFBTN# BATT_LOW_LED#
2 [37] BATT_LOW_LED# 3 [17] USB20_N10 12
1 BATT_CHG_LED# 2 13
1 [37] BATT_CHG_LED# 2 13
1 DMIC_CLK 14
1 [36] DMIC_CLK 15 14
DMIC_DATA
[36] DMIC_DATA 15
NOVO_BTN# 16
ON/OFFBTN# 17 16
ACES_51524-0080N-001 ACES_51524-0060N-001 18 17
SP01001A900 SP010014M10 PLUG_IN# 19 18
[36] PLUG_IN# 19
3
HP_OUTL 20
[36] HP_OUTL 20
HP_OUTR 21
[36] HP_OUTR 22 21
D43 @ EXT_MIC 23 22
[36] EXT_MIC 23
PJSOT24C 3P C/A SOT-23 24
24
1
25
26 GND1
GND2
ACES_88514-02401-071
SP010015W00
D D
WCM-2012-900T_4P
1 2
/
U2DP2
[17] USB20_P1 1 2
4 3 U2DN2
[17] USB20_N1 4 3
/x
C C
L43 @
1 2
R1608 0_0402_5%
R1609 USB3@
1 2
0_0402_5%
su
+USB3_VCCA
Intel_PCH_USB3.0 WCM-2012-900T_4P
1 2 U3RXDN2 W=80mils
[17] USB3_RX2_N 1 2
JUSB1
LP2
4 3 U3RXDP2 U3TXDP2 9
[17] USB3_RX2_P 4 3 SSTX+
1
L44 @ VBUS
p.
U3TXDN2 8
1 2 U2DP2 3 SSTX-
R1612 0_0402_5% USB3@ 7 D+
U2DN2 2 GND 10
R1613 1 2 USB3@ U3RXDP2 6 D- GND 11
0_0402_5% 4 SSRX+ GND 12
GND GND
om
C1309 U3RXDN2 5 13
0.1U_0402_16V7K WCM-2012-900T_4P SSRX- GND
1 2 U3TXDN2_L 1 2 U3TXDN2 TAITW_PUBAU1-09FNLSCNN4H0
[17] USB3_TX2_N 1 2 ME@
1 2 U3TXDP2_L 4 3 U3TXDP2
[17] USB3_TX2_P 4 3
C1310 L45 @
0.1U_0402_16V7K
1 2
yc
R1616 0_0402_5% USB3@
B B
m
2A/Active Low D44
@
+5VALW +USB3_VCCA D45
U3RXDN2 9 10 1 1U3RXDN2 @
3 6 U2DP2
C1308
0.1U_0402_16V7K 1
U52 R02
GND VOUT
8
W=80mils
// U3RXDP2 8 9 2 2U3RXDP2 I/O2 I/O4
+USB3_VCCA
1 2 2 7 U3TXDN2 7 7 4 4U3TXDN2 0113 EMI request
3 VIN VOUT 6 2 5
4 VIN VOUT 5 U3TXDP2 6 5U3TXDP2 GND VDD
[37,38] USB_ON# USB_OC0# [17] 6 5
EN FLG
G547I2P81U_MSOP8 3 3
U2DN2 1 4
p:
8 I/O1 I/O3
1 AZC099-04S.R7G_SOT23-6
1 C1312
C1311 + YSCLAMP0524P_SLP2510P8-10-9
220U_6.3V_M 470P_0402_50V7K
tt
2 2
For EMI request
h
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0/Left USB Ports
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 02, 2012 Sheet 39 of 55
5 4 3 2 1
A B C D E
+5VALW TO +5VS
+3VALW TO +3VS
+5VALW +5VS +3VALW +3VS +5VALW
U53
U54
2
DMN3030LSS-13_SOP8L-8 DMN3030LSS-13_SOP8L-8
8 1 8 1 R5545
1 7 2 1 1 7 2 1 100K_0402_5%
1
6 3 6 3
C1313 5 C1314 C1315 C1316 5 C1317 C1318
1
1 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K R1617 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K R1618 PCH_PWR_EN# 1
2
2 2 470_0603_5% 2 2 470_0603_5%
4
10U @ @
1 2
1 2
+VSB
1
D +VSB D R5534 D
2 SUSP 2 SUSP [37,42] PCH_PWR_EN 1 2 2 Q5527
1
1
G G 0_0402_5% G
1
R1620 S Q85 S Q86 S SB570020110
3
150K_0402_5% 2N7002_SOT23 R1621 2N7002_SOT23 [15,37] SLP_SUS# 1 2 2N7002E-T1-E3_SOT23-3
@ 470K_0402_1% @ 0_0402_5% R5529
DS3@ R5537 100K_0402_5%
2
2
5VS_GATE 2 R1622 15VS_GATE_R
2
2
1
1
D D R1623
SUSP 2 Q88 82K_0402_5% C1322 SUSP 2 Q89 C1323
0_0402_5%
G 2N7002_SOT23 0.01U_0402_25V7K G 2N7002_SOT23 0.01U_0402_25V7K
2
S S @
3
/
+3VALW +3V_PCH
+1.5V_IO to +1.5VS
/x
@
+1.8VS +1.5V_IO +1.05VS_VTT +0.75VS
2 1
+1.5V_IO Q91 +1.5VS
1
2 2
D
R1626 R1627 R1628 R1629 3 1
su
470_0603_5% 470_0603_5% 470_0603_5% 22_0603_5% Q5510
1 1
1
@ @ @ 2 1 AO3413_SOT23
CPU1.5V_S3_GATE [10,37]
1 2
1 2
1 2
1 2
G
2
D D D D
D
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K R1631 3 1
2
2 SUSP 2 SYSON# 2 SUSP 2 SUSP 2 2 470_0603_5%
G G G G @
0.1U_0402_10V7K~D
p.
2
Q92 Q93 Q94 Q95 10U
20K_0402_5%~D
G
S S S S
3
1
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 1
1
+3VALW D
R5510
@ @ @
2 SUSP R5533 2 1 47K_0402_5%
C5528
PCH_PWR_EN# @
G
om
1
S Q96 2
2
For Intel S3 Power Reduction. 2N7002_SOT23 1
100K_0402_5% @
0.1U_0402_25V6
R1633
C5529
2
2 R1635 1 1.5VS_GATE 2
+RTCBATT +5VALW +5VALW Q98 1 1
1
D 0_0402_5%
SUSP# 2 C1328 C1329
yc
2
G 0.1U_0402_16V4Z
R1636 @ @ 2N7002_SOT23 S 2 2
3
220K_0402_5% R1637 R1638 0.1U_0402_16V4Z
100K_0402_5% 100K_0402_5%
1
SUSP SYSON#
m
[10,45,46] SUSP +5VALW +5V_PCH
1
Q99 @
1
DTC124EKAT146_SC59-3 @ Q100
OUT
DTC124EKAT146_SC59-3 2 1
OUT
3
2
[37,45,46] SYSON
SYSON 2
IN
// 2MM J21 3
GND
[10,37,45,46,47,49] SUSP# IN
GND
QH6
1
AO3413_SOT23
3
1
D
R1594 3 1
3
p:
0.1U_0402_10V7K~D
10K_0402_5%
R1639 @
20K_0402_5%~D
1
100K_0402_5%
G
1
2
RH228
2
CH57
PCH_PWR_EN#
tt
2
h
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sherry and Royal
Date: Thursday, February 02, 2012 Sheet 40 of 55
A B C D E
5 4 3 2 1
VIN
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
3
3
1
D 4 D
4
5
2
GND
PC101
PC102
PC103
PC104
6
GND
/
/x
su
C C
+3VLP
p.
+CHGRTC
2
PR127
- JRTC2 + PR131 PR132 PD109 0_0402_5%
om
560_0603_5% 560_0603_5% RB751V-40_SOD323-2
2 1 1 2 1 2 2 1 +RTCBATT
1
@ MAXEL_ML1220T10 1 2
RTCVREF
PD108
yc
RB751V-40_SOD323-2
RTC Battery
m
//
B B
p:
tt
h
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR DCIN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom C38-G series Chief River Schematic0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 02, 2012 Sheet 41 of 55
5 4 3 2 1
5 4 3 2 1
VMB2 VMB
PF201 PL201
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
1 1 2 1 2
1 2 BATT+
2 3 EC_SMCA
3 4 EC_SMDA
4 5
5 6
1
D D
6 7
1
PC201 PC202
7 8
100_0402_1%
100_0402_1%
1000P_0402_50V7K 0.01U_0402_25V7K
2
GND 9
@ GND PR201
PR202
SUYIN_200082GR007G201ZR
2
/
7 8
PR203
6.49K_0402_1%
+EC_VCCA
GND 9 [37,43] ADP_I
21.5K_0402_1%
GND
1
4.42K_0402_1%
12.7K_0402_1%
@
/x
PR207
SUYIN_200082GR007G201ZR 1 2 @
BATT_TEMP [37] A/D
PR205
PR206
PR204
1
10K_0402_5%
PC203 +3VS
2
0.1U_0603_16V7K PU201
2
1 8 NTC_V_2
su
VCC TMSNS1
100K_0402_1%
C 2 7 OTP_N_002 2 1 C
GND RHYST1
PR208
PR209
[37,6] H_PROCHOT#
3
OT1 TMSNS2
6 Turbo_V_2 +3VLP 10K_0402_1%
PH201
PR210
2
4 5 ADP_OCP_2 1 2
100K_0402_1%_NCP15WF104F03RC
1
OT2 RHYST2
1
p.
PQ201 @ PR231
2
D
10K_0402_1%
G718TM1U_SOT23-8 27.4K_0402_1% 0_0402_5% @ PR235
PR211
2 ADP_OCP_1 @ PR227
OTP_N_003
G 0_0402_5%
1
S SSM3K7002FU_SC70-3 PR232
PR230 0_0402_5%
2
om
2 1 2 1
1
PR212 2 1
2
0_0402_5% @ 47K_0402_1%
[37] PROCHOT 1 2 2 1 PR234 ECAGND
MAINPWON [37,44] 0_0402_5%
@ 0_0402_5%
PR213 0_0402_5%
1
Turbo_V
[37]
yc
90W(DIS) : PR205=4.42K PR233
2 1
PR210=27.4K +3VALW
65W(UMA) : PR205=402(SD034020080) 47K_0402_1%
m
PR210=5.11K
NTC_V
[37]
//
B B
P2
PQ205
p:
+3VLP +3VALW
0.01U_0402_25V7K
TP0610K-T1-E3_SOT23-3
1
PC204
3 1
B+ +VSBP
2
VMB2
tt
100K_0402_1%
0.22U_0603_25V7K
PR214 PR215
2
1
100K_0402_1% 100K_0402_1%
1
PR216
PC205
PR217 PR218 <BOM Structure>
2
1 2 0.1U_0603_25V7K
BATT_OUT [43]
2
PR219
2
10K_0402_1% PR220
8
1 2 PQ202 VL 22K_0402_1%
1
3 D 2N7002KW_SOT323-3 1 2
P
+ 1 2
O
2
PR221 2 G @
-
G
2
LM393DG_SO8 100K_0402_1%
4
+3VLP PR224
1
1U_0402_6.3V6K
G S
3
0_0402_5%
1
PC207
PR223 PR226 S
3
10K_0402_1% 100K_0402_1%
2 1 2 1
RTCVREF [37,40] PCH_PWR_EN
2
PR228
1
A PR225 A
10K_0402_1% 0_0402_5%
@
[37] BATT_LEN#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom C38-G series Chief River Schematic0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 02, 2012 Sheet 42 of 55
5 4 3 2 1
5 4 3 2 1
P3
B+
P2
PQ301 PQ302
AO4407A_SO8 AO4423_SO8
8 1 1 8 PR302
VIN 7 2 2 7 0.01_1206_1% CHG_B+
6 3 3 6
SH00000Q100
5 5 1 4 1 2 PQ303
AO4407A_SO8
2 3 PL301 1 8
4
1UH_MNR-4018-1R0N-F_3A_30% 2 7
3 6
@ 10U_0805_25V6K
@ 10U_0805_25V6K
<BOM Structure>
2200P_0402_50V7K
PQ304 5
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
D D
1 2
47K_0402_5%
1
2
200K_0402_1%
0.1U_0603_25V7K
PC307
4
1
PR301
PC302
PC315
PC303
PC305
PC306
DTA144EUA_SC70-3 PC304 DISCHG_G
PC301
PR303
5600P_0402_25V7K
1
PR304
200K_0402_1%
2
2
2 1 2
2
ACN VIN
2ACOFF-1
1SS355_SOD323-2
2
1
ACP PR305
1DISCHG_G-1
47K_0402_1%
1
2
PD301
P2-1 PR306
0.1U_0603_25V7K
1
2 200K_0402_1%
PQ305 PQ306
1
+3VALW PC308 PC309 DTC115EUA_SC70-3
1
DTC115EUA_SC70-3 +3VALW
PR307 [43] ACPRN 1 2 2 1 PD302
3
20K_0402_1% 1SS355_SOD323-2
/
0.1U_0603_25V7K 2 1 2
100K_0402_1%
1 2
6
10K_0603_1%
PQ308
1
1
D 2N7002KW _SOT323-3 PC310 PQ309
150K_0402_1%
/x
PR308
PR309
PR310
PQ307A
2 BATT_OUT [42,43]
2N7002KDW -2N_SOT363-6 G 0.1U_0603_25V7K P2 2N7002W -T/R7_SOT323-3
1
D
0.1U_0603_25V7K
S
3
@ 2 1 2 PACIN
PR313
1
1
PC311
VIN @ PR312 @ @ G
1
2 1 1 2
2.2K_0402_5%
2.2K_0402_5%
S
3
2
2
390K_0603_1% 4.7M_0603_1%
su
2
1
P2-2
PR315
PR316
10_1206_5%
39.2K_0402_1%
5
6
7
8
C C
PR314
2N7002KDW-2N_SOT363-6
PQ310
PR319
AO4466L_SO8
3
PQ307B
<BOM Structure>
ACOK
CMPIN
CMPOUT
ACP
ACN
1
1
PR318 [37,42] ADP_I
2
47K_0402_1% PR317 21
p. 1
PACIN 1 2 5 1 2 6 TP 4
PACIN @ @ ACDET PC313
1
om
0.1U_0603_25V7K 10UH_PCMB063T-100MS_4A_20% PR320
2
3
2
1
1U_0603_25V6K
1
5
6
7
8
1 2ACOFF-12 [37,42] EC_SMB_CK1 9 2 3
[37] ACOFF SCL SA000051W00
1
PQ312
10K_0402_5% PR324 PC314
AO4466L_SO8
4.7_1206_5%
PR322
PR323 2.2_0603_5% 0.047U_0603_16V7M
1
yc
1 2 10 17 BST_CHG 1 2 2 1 SRP SRN
10U_0805_25V6K
10U_0805_25V6K
ILIM BTST
1
16251_SN
PR325 +3VALW 316K_0402_1%
PD303
3
PR326 4
LODRV
0_0402_5%
1
16 2 1
PC371
PC372
100K_0402_1%
GND
SRN
SRP
REGN
BM
2N7002KW_SOT323-3
2
2
m
PQ313 RB751V-40_SOD323-2
680P_0603_50V7K
11
1 12
13
14
15
3
2
1
1
1
D
PC377
10_0603_5%
6.8_0603_5%
2
2 BQ24727VDD
PR328
PC376
[42,43] BATT_OUT
PR327
G 1U_0603_25V6K
2
S
//
3
2
2
PC373 DL_CHG
B 0.1U_0603_25V7K B
2 1
p:
CHGVADJ=(Vcell-4)/0.10627
1
Vcell CHGVADJ
1
PC374 @
4V 0V 0.1U_0603_25V7K PC375
2
tt
2 0.1U_0603_25V7K
4.2V 1.882V
4.35V 3.2935V
h
BQ24727VDD
CC=0.25A~3A PR337
10K_0402_1%
1
IREF=1.016*Icharge 1 2
ACIN [15,23,37]
PR336
IREF=0.254V~3.048V PR335 10K_0402_1%
47K_0402_1%
VCHLIM need over 95mV PACIN
2
2N7002KW_SOT323-3
PQ316
1
S
3
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-G series Chief River Schematic
Date: Thursday, February 02, 2012 Sheet 43 of 55
5 4 3 2 1
5 4 3 2 1
Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
2VREF_8205 PJ402
+3VALW P 2 1 +3VALW
2 1
@ JUMP_43X118
1U_0603_10V6K
D D
1
PJ403
PC401
+5VALW P 2 1 +5VALW
2
2 1
@ JUMP_43X118
PR401 PR402
13K_0402_1% 30K_0402_1%
1 2 1 2
PR403 PR404
RT8205_B+ 20K_0402_1% 19.6K_0402_1% RT8205_B+
1 2 1 2
PJ401 Typ: 175mA
/
B+ 2 1 +3VLP
0.1U_0603_25V7K
2 1
ENTRIP2
ENTRIP1
/x
@ JUMP_43X118 PR405 PR406
PC405
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0603_25V7K
0.1U_0603_25V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
130K_0402_1% 66.5K_0402_1%
1 2 1 2
PC402
PC410
4.7U_0805_10V6K
1
1
PC403
PC404
PC406
PC407
PC408
PC409
2
8
7
6
5
5
6
7
8
PU401
2
2
su
PC411
ENTRIP2
FB2
TONSEL
FB1
ENTRIP1
REF
1
C PQ401 C
TPC8065-H_SO8
25
PQ402
AO4466L_SO8 P PAD
2
4 4
7 24
p.
VO2 VO1 SPOK [42]
8 23 PR408 PC413
PR407 VREG3 PGOOD 2.2_0603_5% 0.1U_0603_25V7K
1
2
3
3
2
1
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2
BOOT2 BOOT1
om
2.2_0603_5%
PL401 PC412 UG_3V 10
VFB=2.0V 21 UG_5V PL402
4.7UH +-20% PCMC063T-4R7MN 5.5A 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH +-20% PCMC063T-4R7MN 5.5A
1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1
8
7
6
5
1
LG_3V 12 19 LG_5V
4.7_1206_5%
4.7_1206_5%
LGATE2 LGATE1
5
6
7
8
PQ403
PR409
PR410
SKIPSEL
AO4712_SO8
VREG5
yc
PQ404
GND
VIN
RT8205EGQW _W QFN24_4X4
NC
EN
1 1
2
2
4
+ PC415 4 + PC417
13
14
15
16
17
18
1
1
150U_B2_6.3VM_R45M PR411 150U_B2_6.3VM_R45M
680P_0603_50V7K
TPC8A03-H_SO8
m
499K_0402_1%
680P_0603_50V7K
2 1 2 2
PC418
PC419
2
1
2
3
2
B+
3
2
1
1
// 100K_0402_1%
1U_0603_10V6K
VL
1
PC420
1
PR412
PC421
Typ: 175mA
4.7U_0805_10V6K
B B
2
ENTRIP1 ENTRIP2
2
2
p:
RT8205_B+
6
1
PQ405B
PQ405A 2N7002KDW -2N_SOT363-6
0.1U_0603_25V7K
2N7002KDW -2N_SOT363-6 2 5 2VREF_8205 +3.3VALWP OCP(min)=5.81A
2
tt
PC422
+5VALWP OCP(min)=8.44A
1
4
h
PR414
100K_0402_1%
2 1
VL
[37] EC_ON PR418
2.2K_0402_5%
2 1
1
4.7U_0603_6.3V6M
A A
1
1
PR417
PC423
3
2
2
@PJ501
@ PJ501
1.05VS_B+ 1
1 2
2 B+
STATE S3 S5 1.5VP VTT_REFP 0.75VSP
4.7U_0805_25V6-K
4.7U_0805_25V6-K
JUMP_43X118
1
PC509
PC501
S0 Hi Hi On On On
5
1.05VS_B+
Off
2
S3 Lo Hi On On (Hi-Z) +1.5VP PQ503
TPCA8065-H_PPAK56-8-5
UG_1.5V 4
S4/S5 Lo Lo Off Off Off PJ5025
@
1
JUMP_43X39 LX_1.5V
3
2
1
1 1
2
PR507 PC502 PL502
2
2.2_0603_5% 0.1U_0603_25V7K 1UH_PCMC063T-1R0MN_11A_20%
BST_1.5V 1 2 BST_1.5V-1 1 2 1 2
+0.75VSP +1.5VP
10U_0805_25V6K
10U_0805_25V6K
1
5
20
19
18
17
16
TPCA8057-H_PPAK56-8-5
<BOM Structure> <BOM Structure>
PQ502
PC506
PC504
PU501 PR506 @
4.7_1206_5% 1
VTT
VLDOIN
BOOT
UGATE
PHASE
21
2
PAD + PC505
1 15 LG_1.5V 4 330U_D2_2.5VY_R15M
VTTGND LGATE
1
PC510 @ 2
2 14 680P_0402_50V7K
2
VTTSNS PGND PR505
3
2
1
11K_0402_1%
3 13 2 1
/
GND RT8207MZQW _W QFN20_3X3 CS
4 12
/x
+VTT_REFP VTTREF VDDP
5 11 2 1
+1.5VP VDDQ VDD
+5VALW
PGOOD
PR502
+3VALW
1
5.1_0603_5%
1U_0603_10V6K
TON
PC507
FB
S3
S5
su
0.033U_0402_16V7K
2
1
PC503
10K_0402_5%
2 2
10
PR509
PC511
1U_0603_10V6K
S3_1.5V
S5_1.5V
2
PR503
0_0402_5% @
p.
2
,45,46,47,49] SUSP# 1 2 PGOOD_1.5V
PR504 PR501
0_0402_5% 887K_0402_1%
[37,40,46] SYSON 1 2 2 1 1.05VS_B+
om
PR510
1
PQ501@ FB=0.75V
1
D
1
yc
G PR508 To VDD = 1.8V 2 1
[10,40,46] SUSP S
5.76K_0402_1% @ JUMP_43X118
3
PJ506
2 1 +1.5V
m
2 1
@ JUMP_43X118
//
3 3
p:
PJ507
1 2
+0.75VSP 1 2 +0.75VS
tt
PJ504 1UH_PH041H-1R0MS_3.8A_20% @
2 1 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
+5VALW
PG
2 1 PVIN LX +1.8VSP
h
@ JUMP_43X118 9 3
68P_0402_50V8J
PVIN LX
1
1
680P_0603_50V7K 4.7_1206_5%
1
1
PC513 8 PC514
SVIN
PR511
22U_0805_6.3VAM PR512
6 20K_0402_1%
2
2
5 FB
22U_0805_6.3VAM
22U_0805_6.3VAM
1 2
EN
1
NC
NC
PJ503
TP
PC516
PC517
FB=0.6Volt +1.8VSP 2 1 +1.8VS
2 1
[10,37,40,45,46,47,49] SUSP#
PC515
PR513
11
2
1 2 EN_1.8VSP @ JUMP_43X118
2
0_0402_5%
0.1U_0402_10V7K
2
PC518 @
SY8033BDBC_DFN10_3X3
1
4
PR515 4
10K_0402_1%
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+1.5VP/+1.8VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-G series Chief River Schematic
Date: Thursday, February 02, 2012 Sheet 45 of 55
A B C D
A B C D
@ PJ509
1.5V_B+_DDR3L 1
1 2
2 B+
STATE S3 S5 1.5VP VTT_REFP 0.75VSP
4.7U_0805_25V6-K
4.7U_0805_25V6-K
JUMP_43X118
1
PC520
PC519
S0 Hi Hi On On On
5
Off
2
S3 Lo Hi On On (Hi-Z) +1.5VP_DDR3L PQ504
TPCA8065-H_PPAK56-8-5
UG_1.5V_DDR3L 4
@ PJ508
S4/S5 Lo Lo Off Off Off
1
JUMP_43X39 LX_1.5V_DDR3L
3
2
1
1 1
2
PR516 PC521 PL1
2
2.2_0603_5% 0.1U_0603_25V7K 1UH_PCMC063T-1R0MN_11A_20%
1
BST_1.5V_DDR3L 2 BST_1.5V-1_DDR3L
1 2 1 2
+0.75VSP_DDR3L +1.5VP_DDR3L
10U_0805_25V6K
10U_0805_25V6K
1
5
20
19
18
17
16
TPCA8057-H_PPAK56-8-5
1
PQ505
PC522
PC523
PU503 PR517
4.7_1206_5% 1
VTT
VLDOIN
BOOT
UGATE
PHASE
21
2
PAD + PC524
1 15 LG_1.5V_DDR3L 4 330U_D2_2.5VY_R15M
VTTGND LGATE
1
PC525 2
2 14 680P_0402_50V7K
2
VTTSNS PGND PR518
3
2
1
11K_0402_1%
3 13 2 1
/
GND RT8207MZQW _W QFN20_3X3 CS
+VTT_REFP_DDR3L 4 12
/x
VTTREF VDDP
5 11 2 1
VDDQ VDD
+5VALW
PGOOD
PR519
+1.5VP_DDR3L +3VALW
1
5.1_0603_5%
1U_0603_10V6K
TON
PC526
FB
S3
S5
su
0.033U_0402_16V7K
S3_1.5V_DDR3L
S5_1.5V_DDR3L
2
1
PC527
10K_0402_5%
2 2
10
PR520
PC528
1U_0603_10V6K
2
PR521
@
0_0402_5%
p.
2
,40,45,47,49] SUSP# 1 2 PGOOD_1.5V_DDR3L
PR522 PR523
0_0402_5% 887K_0402_1%
[37,40,45,46] SYSON 1 2 2 1 1.5V_B+_DDR3L
om
PR524 PJ510
1
PQ506
1
2N7002KW _SOT323-3 D
2
FB=0.75V PJ511 +1.5V
+1.5VP_DDR3L 2 1
To GND = 1.5V
yc
G 2 1
[10,40,45] SUSP To VDD = 1.8V @ JUMP_43X118
S
3
PJ512
1
PR526
m
PR525 1 2
+0.75VSP_DDR3L 1 2 +0.75VS
12.7K_0402_1%
49.9K_0402_1%
2
JUMP_43X39
2
@
@ PR528
0_0402_5%
//
[37,40,45,46] SYSON 1 2
PQ507
1
3 3
2N7002KW _SOT323-3 D
1 2 2
[18] DDR3L_EN#
0_0402_5% G
p:
PR527 S
3
1
@ PC531
0.1U_0402_16V7K
2
tt
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+1.5VP/+1.8VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-G series Chief River Schematic
Date: Thursday, February 02, 2012 Sheet 46 of 55
A B C D
5 4 3 2 1
D D
PR709
[10,37,40,45,46,49] SUSP# 60.4K_0402_1%
1 2
+1.05VS_VCCPP OCP(min)=20.75A
@ 10K_0402_1%
+3VS
.1U_0402_16V7K
1
PR710
PC710
100K_0402_1%
TPCA8065-H_PPAK56-8-5
2
100K_0402_1%
1
1.05VS_B+
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1.05VS_B+
2
PR711
0.1U_0402_25V6
2
PR712
1
PR713
PC712
PC715
5
0_0402_5% PR714 PC713
PC711
PC714
[48] +V1.05S_VCCP_PW RGOOD 1 2 2.2_0603_5% 0.1U_0603_25V7K
2
/x
1 2 1 2
PQ703
BST_1.05VS_VCCP
1
10.7K_0402_1%
17
16
15
14
13
PU702 4
PAD
PGOOD
EN
MODE
BST
2
PR715
su
C 1 12 LX_1.05VS_VCCP PL2 C
0.1U_0402_25V6
3
2
1
VREF SW 1UH_PCMC063T-1R0MN_11A_20%
+1.05VS_VTTP
1
1 2
12K_0402_1%
1
PC716
2 11 DH_1.05VS_VCCP
p.
2
REFIN DH
2
1
PR716
1000P_0603_50V7K 4.7_1206_5%
5
[9] VSSIO_SENSE_L PC717
TPS51219RTER_QFN16_3X3 PQ704
PR717
PR718 0.01UF_0402_25V7K 1
1
3 10 DL_1.05VS_VCCP
330U_X_2VM_R9M
GSNS DL
om
1 2 +
1
PC718
TPCA8057-H_PPAK56-8-5
0_0402_5% 4
4 9 2
VSNS V5 +5VALW
COMP
1
PGND
TRIP
GND
3
2
1
PC719
yc
2
PC720
PR719
5
1
1 2 1 2
75K_0402_1%
PR720
1
PC721
[9] VCCIO_SENSE 1 2 10_0402_5% 0.01UF_0402_25V7K 1U_0603_10V6K
2
m
@
10_0402_1%
PR721
2
2
PC722
1000P_0402_50V7K
//
1
B PR722 B
1 2
p:
10_0402_1%
2
PC723
1000P_0402_50V7K
1
tt
PJ705
h
2 1
2 1
@ JUMP_43X118
+1.05VS_VTTP PJ706 +1.05VS_VTT
2 1
2 1
@ JUMP_43X118
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR +1.05VS_VCCPP/
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-G series Chief River Schematic
Date: Thursday, February 02, 2012 Sheet 47 of 55
5 4 3 2 1
5 4 3 2 1
+3VS PR601
1K_0402_5%
2 1
VID [0] VID[1] VCCSA Vout PJ602
+VCC_SAP
100K_0402_5%
0 0 0.9V H_VCCSA_VID1 [10] +VCCSAP 2
2 1
1 +VCCSA
1
TDC 4.2A
0 1 0.85V @ JUMP_43X118
PR602
Peak Current 6A
1 0 0.775V OCP current 7.2A
2 +VCCSA_PWRGD
H_VCCSA_VID0 [10]
1 1 0.75V
PR603 1
[37] SA_PGOOD
0.033U_0402_16V7K
1K_0402_5%
output voltage adjustable network
PC620
2 1
D D
2 @
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
+VCCSA_VID0
+VCCSA_VID1
+5VALW
+VCCSA_PWRGD
VCCSA VID is 00 prior to VCCIO stability.
1U_0603_10V6K
2
PC601
PR604 PR605
10_0402_1% 0_0402_5%
1
2 1 +VCCSA_EN 1 2
+V1.05S_VCCP_PWRGOOD [47]
PC602
2.2U_0603_10V7K
1 2
18
17
16
15
14
13
PU601
PR606 PC603
VID1
VID0
PGOOD
EN
V5FILT
V5DRV
0_0603_5% 0.22U_0603_16V7K
12 +VCCSA_BT 1 2+VCCSA_BT_1 1 2
19 BST PL601
PGND 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
SW
11 +VCCSA_PHASE 1 2 +VCCSAP
20
PGND
/ 22U_0805_6.3V6M
22U_0805_6.3V6M
0.1U_0402_10V7K
1
10
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
2200P_0402_50V7K
21 SW
2200P_0402_50V7K
PR607 @ @ @ @
0.1U_0603_25V7K
PGND
2
10U_0805_6.3V6M
10U_0805_6.3V6M
4.7_1206_5%
PC605
PC606
PC608
PC609
PC611
PC612
9
/x
TPS51463RGER_QFN24_4X4
PC607
PC610
22 SW
PC614
1 2 2
1
VIN
2
PC613
PC615
PC616
8
SW
1
23 PC604
1
2 1 1 VIN 1000P_0603_50V7K
PJ601 7
+3VALW
2
2 1 +VCCSA_PWR_SRC +VCCSA_PWR_SRC 24 SW
su
2 1 VIN
C @ JUMP_43X118 25 C
COMP
MODE
TP
SLEW
VOUT
VREF
GND
1
6
@ PR608
p.
2 1
33K_0402_5%
PC617 PR609
2 1 100_0402_5%
2 1
om
0.22U_0402_10V6K
0.01U_0402_25V7K
2
2 1 2 1
PR611
PC619
1
PC618 PR610 0_0402_5%
1
3300P_0402_50V7K 5.1K_0402_1% PR612 2 1
+VCCSA_SENSE [10]
@ 0_0402_5%
2
yc
m
//
B B
p:
tt
h
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR +VCCSAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-G series Chief River Schematic
Date: Thursday, February 02, 2012 Sheet 48 of 55
5 4 3 2 1
A B C D
@ PJ801
+VGA_COREP VGA_CORE_B+ 2 1
2 1 B+
JUMP_43X118
1 1
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
0.1U_0402_25V6
1
1
PR802
PC803
PC802
PC804
PC805
0_0402_5%
2
5
PC806
TPCA8065-H_SOP-ADV8-5
10P_0402_25V8J
2 1
PQ801
2
2
4700P_0402_25V7K
10P_0402_25V8J PR803 4
PC801
41.2K_0402_1%
2
PR801
0_0402_5%
18 PC807
1
1 2
19 1
3
2
1
PL801
21
20
17
16
PU801 0.36UH_PCMC104T-R36MN1R17_30A_20%
1 2
PAD
GND
SLEW
VSNS
TRIP
MODE
+VGA_COREP
PR804
2 1
1 15
GSNS V5IN +5VALW
2
100K_0402_1%
11.8K_0402_1%
1
PR805
1 1 1
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
/
TPCA8057-H 1N PPAK56-8
2 14 PC808 1 1 1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
V3 DRVL 1U_0603_10V6K PR806 + + +
PC809
PC810
PC811
PC812
PC813
PC814
5.11K_0402_1%
2
4.7_1206_5%
PQ802
21
/x
2
3 13 UGATE2_VGA 4 2 2@ 2 2 2 2
PR807
V2 TPS51518RUKR_QFN20_3X3 DRVH
1
PC815
4 12 680P_0603_50V7K
21
V1 SW PR808 PC816
7.68K_0402_1%
3
2
1
2
2.2_0603_5% 0.1U_0603_25V7K
PR809
5 11
BOOT2_VGA 2 1 BOOT2_2_VGA1 2
V0 BST
su
PGOOD
2 2
1 1
VREF
VID0
VID1
EN
97.6K_0402_1%
LGATE2_VGA
PR810
10
+VGA_COREP
p.
2
Iocp=32.5A
0.1U_0402_10V7K
1
+3VS
PC817
2
PJ802
om
1
2 1
10K_0402_1%
+VGA_COREP 2 1 +VGA_CORE
Seymour
PR811
PR812 @ JUMP_43X118
0_0402_5%
[18,22] VGA_PWRGD 1 2 GPU_VID1 GPU_VID0 Core Voltage Level
2
PJ803
PR824 2 1
2 1
[23] GPU_VID0
0_0402_5% 1 1 0.9V
GPU_VID0 1 2 @ JUMP_43X118
yc
PR825 1 0 1.0V
0_0402_5%
[23] GPU_VID1 GPU_VID1 1 2
0 1 1.05V
@ PR813
m
33K_0402_5% 0 0 1.12V
1 2
PX_MODE
PR814
@ 0_0402_5%
[10,37,40,45,46,47] SUSP#
1 2 VRON_VGA
// +1.5V_IO
2
3
PR815 3
+5VALW PJ805
@
1
PXS_PWREN 1 2 2 1
[17,24,49] PXS_PWREN +VGA_PCIEP +1.0VGS
1
PJ804 2 1
1
p:
0_0402_5% PC818 JUMP_43X79 JUMP_43X79
0.1U_0402_16V7K
1
2
PC819
1U_0402_6.3V6K
2
2
@ PR820 PR822
tt
1
10k_0402_5% 10K_0402_5% PC820
6
2
RB751V-40_SOD323-2 7 VIN
@ 1 2 POK 4
h
22U_0603_6.3V6K
1
1
PXS_PWREN 1 2 8 2
[17,24,49] PXS_PWREN EN FB
PR816
PC823
GND
40.2K_0402_1% 9 PR817
2
VIN 1.15K_0402_1%
1
APL5912-KAC-TRL_SO8
0.1U_0603_25V7K
2
1
@ PR818
20K_0402_1% PC821
2
0.01U_0402_25V7K
2
PR819 4.53K 3K
PR819
4.53K_0402_1%
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-VGA_CORE/VGA_PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 02, 2012 Sheet 49 of 55
A B C D
5 4 3 2 1
PL901
HCB4532KF-800T90_1812
B+ 1 2
CPU_B+
33U_D2_25VM_R60
15U_D2_25VM_R90
33U_D2_25VM_R60
15U_D2_25VM_R90
2 1 1 1 1 1
1
+VGFX_CORE @ PC902
+ + + +
PC904
PC903
PC901
PC905
@ PR901 10_0402_1% 1000P_0402_50V7K
[10] VCC_AXG_SENSE
2 2
[10] VSS_AXG_SENSE
2 2 2 2
PC906
2 1 0.01UF_0402_25V7K @
1
D @ PR902 PC907 PC908 D
10_0402_1% 68P_0402_50V8J 470P_0402_50V7K
2 1 2 1 2 1
PR903
PH901 PR904 PC909 499_0402_1%
10K_0402_1%_ERTJ0EG103FA 475_0402_1% 137K_0402_1%
150P_0402_50V8J CPU_B+
PR905 1
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
VSUMG- 2 1 2 2 1 2 1
+VGFX_CORE:
2
PR906
MDU1516URH_POWERDFN56-8-5
1
2.74K_0402_1% VID1=1.23V
1
PC911
PC915
PC916
PC917
PR907
0.047U_0402_16V8J
IccMax=33A
5
154K_0402_1%
0.1U_0402_16V7K
0.022U_0402_16V7K
0.1U_0603_25V7K
2K_0402_1%
1
PC910
PR910
Icc_TDC=21.5A
2 1
2
2
11K_0402_1%
PQ901 @ @
2.61K_0402_1%
1 2
2
2
PR909
PC912
PC918
+3VS Icc_Dyn=20.2A
2
PC913
PR908 PC914 UGATE1G 4 OCP~40A
1
1
2
1.91K_0402_1%
@ 330P_0402_50V7K
2
1
1
PR912 @ PL902
VSUMG+ 0_0402_5% 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
3
2
1
1 2 +5VS
PHASE1G 1 4
+VGFX_CORE
2
LGATE1G
/
5
4.7_1206_5%
2 3
1
PWMG2 PR911
PR913
PHASE1G PQ902
MDU1511RH_POWERDFN56-8-5
2
3.65K_0603_1%
/x
UGATE1G PC919
Rds(on)
1
0.22U_0603_16V7K
1 1
680P_0402_50V7K
1_0402_5%
PR914
PR915
BOOT1G 4 typ=2.6m Ω
1 2
PC920
PR916 max=3.2m Ω
LGATE1G
2.2_0603_5%
+5VS
VSUMG+ 1
2
3
2
1
2
su
VSUMG-
40
39
38
37
36
35
34
33
32
31
2
PU901 BOOT1G
C C
ISUMNG
RTNG
FBG
COMPG
PGOODG
PWM2G
LGATE1G
PHASE1G
UGATE1G
BOOT1G
1
PR917
1
27.4K_0402_1%
2 1 PR921 1 30 PR918 PR919 For ULV 17W 1+1
p.
PR920 0_0402_5% 2 ISUMPG BOOT2 29 0_0603_5% 1_0603_5%
3.83K_0402_1% PH902 +5VS 1 2 ISEN2G 3 ISEN1G UGATE2 28 CPU_CORE LL= -2.9mΩ,
2
ISEN2G PHASE2
1U_0603_10V6K
PC921
1 2 2 1 NTCG 4 27
2
NTCG LGATE2
[9] VR_SVID_CLK
1
470K_0402_5%_ 2
TSM0B474J4702RE SCLK 5
SCLK VCCP
26
GFX_CORE LL= -3.9mΩ,
1
1 2 PR922 0_0402_5% ALERT# 6 25
[9] VR_SVID_ALRT# ALERT# VDD
om
PR923 0_0402_5%1 2 SDA 7 24
[9] VR_SVID_DAT SDA PWM3 L DCR=1.1mΩ
1U_0603_10V6K
PR924 0_0402_5% 8 23 LGATE1
[37] VR_HOT#
2
VR_HOT# LGATE1
PC922
1 2 9 22
[37] VR_ON VR_ON PHASE1
1
54.9_0402_1%
2
0_0402_5%
130_0402_1%
75_0402_5%
ISEN3/FB2
PR926
PR927
PR928
PR929
1
470K_0402_5%_ TSM0B474J4702RE
27.4K_0402_1%
PGOOD
@ PC923 UGATE1
BOOT1
ISUMN
ISUMP
2
COMP
ISEN2
ISEN1
47P_0402_50V8J 41
RTN
TP
1
@ @ BOOT1
FB
2
PR930
yc
1
PH903
ISL95836HRTZ-T_TQFN40_5X5~D
MDU1516URH_POWERDFN56-8-5
MDU1516URH_POWERDFN56-8-5
11
12
13
14
15
16
17
18
19
20
CPU_B+
+1.05VS_VTT +5VS
2
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2
PR932
VGATE [15]
1
5
3.83K_0402_1%
0_0402_5%
1
1
m
PC925
PC926
PC927
PC928
@ PC924 1 2 PR933 1.91K_0402_1% PQ903 PQ904
+3VS
PR931
0.1U_0402_16V7K 2 1
2
2
<BOM Structure> UGATE1 4 4
2
// PL903
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
3
2
1
3
2
1
B VSUM+ PHASE1 1 4 B
PC929 PR934 PR935 @ PC930 +CPU_CORE
11K_0402_1%
2.61K_0402_1%
4.7_1206_5%
470P_0402_50V7K 2K_0402_1% 42.2K_0402_1% 10P_0402_50V8J PR937 2 3
1
0.1U_0603_16V7K
0.047U_0402_16V8J
2 1 2 1 2 1 2 1 2.2_0603_5%
p:
PR936
PR938
BOOT1 2 1 1 2 PQ906 PQ905
MDU1511RH_POWERDFN56-8-5
MDU1511RH_POWERDFN56-8-5
475_0402_1%
PC934
1
680P_0402_50V7K
PC932
PC931
PR939
1 2
2
PC936
470P_0402_50V7K 68P_0402_50V8J 4 4
2
1
tt
PR940
2 1 2 1 2 1 PH904
PR941
Rds(on)
2
2
max=3.2m Ω
1
3
2
1
3
2
1
1
VSUM-
h
2
PR942 PC937 PR945
1.91K_0402_1% 150P_0402_50V8J
Close Phase 1 choke PR944 1_0402_5%
1
0.1U_0402_16V7K
2 1 2 1 2 1 3.65K_0603_1%
PC938
PR943
LGATE1
LGATE1
VSUM- 2
137K_0402_1%
VSUM+
2
1
+CPU_CORE 2 1
@ PR946 @ PC939
10_0402_1% 330P_0402_50V7K
2 1
+CPU_CORE:
[9] VCCSENSE
VID1=0.9V
[9] VSSSENSE
2 1 IccMax=33A
PC940 Icc_TDC=25A
2 1 0.01UF_0402_25V7K
A
@ PR947 Icc_Dyn=28A A
10_0402_1% OCP~40A
Security Classification
2009/12/01
Compal Secret Data
2012/07/11 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom C38-G series Chief River Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 02, 2012 Sheet 50 of 55
5 4 3 2 1
A
B
C
D
2 1 2 1
PC326 PC353
+VGFX_CORE
1U_0402_6.3V6K 1U_0402_6.3V6K
2 1 2 1
PC324 PC352
1U_0402_6.3V6K 1U_0402_6.3V6K
5
5
2 1 2 1
2
1
+
PC323 PC351 PC255
1U_0402_6.3V6K 1U_0402_6.3V6K 330U_D2_2V_Y
2 1 2 1
2 1 2 1
2
1
+
PC322 PC334
1U_0402_6.3V6K 1U_0402_6.3V6K PC256 PC247
2 1 2 1 330U_D2_2V_Y 10U_0603_6.3V6M PC230
1U_0402_6.3V6K
2 1 2 1
PC321 PC333
1U_0402_6.3V6K 1U_0402_6.3V6K PC242
2 1 2 1 10U_0603_6.3V6M PC231
1U_0402_6.3V6K
2 1 2 1
PC289 PC332
1U_0402_6.3V6K 1U_0402_6.3V6K PC243
2 1 2 1 2 1 10U_0603_6.3V6M PC232
2
1 1U_0402_6.3V6K
PC248 2 1 2 1
10U_0603_6.3V6M PC288 PC331 PC241
2 1 1U_0402_6.3V6K 1U_0402_6.3V6K 22U_0805_6.3V6M PC244
2 1 2 1 2 10U_0603_6.3V6M PC233
1
PC263 1U_0402_6.3V6K
10U_0603_6.3V6M PC259 2 1 2 1
PC287 PC330 22U_0805_6.3V6M
2 1 1U_0402_6.3V6K 1U_0402_6.3V6K PC245
2 1 2 1 2 1 10U_0603_6.3V6M PC234
2
1
PC276 1U_0402_6.3V6K
10U_0603_6.3V6M PC279 PC260 2 1 2 1
10U_0603_6.3V6M PC286 PC329 22U_0805_6.3V6M
4
4
PC277 1U_0402_6.3V6K
10U_0603_6.3V6M PC283 PC261
10U_0603_6.3V6M PC285 PC328 22U_0805_6.3V6M 2 1
2 1 1U_0402_6.3V6K 1U_0402_6.3V6K
2 1 2 1 2 1
2
1
PC278 PC363
10U_0603_6.3V6M PC282 PC262 1U_0402_6.3V6K
h
10U_0603_6.3V6M PC284 PC327 22U_0805_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K 2 1
2 1 2 1 2 1
2
1
2
1
+
PC291 PC281 PC358 PC364
tt
330U_D2_2V_Y 10U_0603_6.3V6M PC355 PC354 22U_0805_6.3V6M 1U_0402_6.3V6K
1U_0402_6.3V6K 1U_0402_6.3V6K
2 1 2 1 2 1 2 1
PC280
p:
10U_0603_6.3V6M PC357 PC356 PC365
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
2 1
//
+1.05VS_VTT
PC366
1U_0402_6.3V6K
m
2 1
Issued Date
PC367
1U_0402_6.3V6K
Security Classification
3
3
yc
om
2011/06/24
p.
su
+CPU_CORE
+CPU_CORE
+CPU_CORE
2
1
+
2 1 2 1
PC271
2
1
2
1
/x
22U_0805_6.3V6M 22U_0805_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
Compal Secret Data PC265 PC249 PC236 PC225
330U_D2_2V_Y
Deciphered Date
/
2
1
2
1
2
1
2 1 2 1
22U_0805_6.3V6M 22U_0805_6.3V6M
PC266 PC250 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
PC237 PC226
PC272
2
2
2
1
2
1
2 1 2 1
22U_0805_6.3V6M 22U_0805_6.3V6M 2.2U_0402_6.3V6M
330U_D2_2V_Y
PC238
2
1
2
1
2 1 2 1
PC273
22U_0805_6.3V6M 22U_0805_6.3V6M
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2 1 2 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
22U_0805_6.3V6M 22U_0805_6.3V6M
PC269 PC253 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
Title
Date:
PC240 PC229
Custom
2
1
2
1
2 1 2 1
22U_0805_6.3V6M 22U_0805_6.3V6M
PC270 PC254 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
PC316 PC275
2
1
2
1
2 1 2 1
22U_0805_6.3V6M 22U_0805_6.3V6M
@
@
2 1 2 1
Thursday, February 02, 2012
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
PC320 PC319
1
1
CPU_CORE_CAP
Sheet
51
Compal Electronics, Inc.
of
55
For TOP side
For BOT side
Rev
0.1
A
B
C
D
5 4 3 2 1
1
D D
/
7
/x
8
su
C C
9
p.
10
11
om
12
yc
13
m
14 //
B B
p:
tt
h
15
16
17
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-G series Chief River Schematic0.1
Date: Thursday, February 02, 2012 Sheet 52 of 55
5 4 3 2 1
5 4 3 2 1
COMPAL CONFIDENTIAL
MODEL NAME: Power Sequence Block Diagram
PCB NAME: LA-7981P
D REVISION: D
DATE: 2011/07/13 10
PCH_PWROK
AC A1
MODE VIN +3V_PCH
V V
A2 A3 B5 +5V_PCH
VV
PU301 A5 3
V
PU401
V
B+
+3VALW B7 3 3
BATT BATT V 10
+5VALW
MODE
B1
B2
B+ B4 V PCH_PWROK
V SYS_PWROK 15 14 VGATE
/
V
EC 4
/x
PQ2 11
PCH_RSMRST#_R PM_DRAM_PWRGD
V
V V PCH
B3 A5 B7 5 12
PBTN_OUT# H_CPUPWRGD
su
CPU
V V
13 SVID
V
C C
51ON# EC_ON
PM_SLP_S3#
PM_SLP_S4# PLT_RST# 16
PM_SLP_S5#
p.
A4 B6 PM_SLP_SUS# 6
DGPU_PWROK
V
V
ON/OFF
oVm
SYSON 7 SYSON#
+1.5V
PU501
DGPU_PWR_EN
yc
SUSP#,SUSP 8
Vm
(DIS)
//
V
PU601 U38
8b
B +VCC_SA +5VS B
p:
(DIS)
V
V
PU702 U39
8a
+V1.05S +3VS DGPU
V
tt
V
V
PU602 Q8
h
+V1.05S_VCCP +1.5VS
PU701
V
SA_PGOOD 8a +0.75VS
13 SVID
VR_ON 9 PU901
V
+VCC_CORE
A A
14 VGATE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Sherry and Royal 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 02, 2012 Sheet 53 of 55
5 4 3 2 1
5 4 3 2 1
1 Initial DVT
D D
/
/x
7
su
C C
p.
10
11
om
12
13
yc
14
m
15
16
//
B B
17
p:
18
tt
19
h
20
21
22
23
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Sherry and Royal 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 02, 2012 Sheet 54 of 55
5 4 3 2 1