Ch 1.

Introduction to Embedded Systems

Part B
Embedded ARM Applications

Byung Kook Kim

Dept of EECS
Korea Advanced Institute of Science and Technology
 Overview

„ Trends in embedded system design

„ Integrate all the major system functions apart from some
memory components into a single chip
„ Benefits in terms of component costs, reliability, and
power-efficiency
„ Advance in semiconductor process technology: millions of
transistors built cheaply
„ The era of complex systems on a single chip

„ Several examples of ARM-based ‘system on chips’

Embedded Systems, KAIST 2

 1.7 The VLSI Ruby II Advanced
Communication Processor
„ Ruby II advanced external
interrupts (3)

communication
processor chip clock clock
control ARM 512 x 32 interrupt counter/
„ VLSI core SRAM controller timers

Technology, Inc
„ Organization ->
parallel control
i/f 1,2,3,4
external address (22)
PCMCIA bus
host control
data (8/16/32)
I/O interface ho st
mode FIFOs
select (16 x 8)
UART1

serial I 2 C, ...
UART2 controller
serial
FIFOs 8 data bits
serial (16 x 8) & control
high-speed parallel
serial i/f interface 0

Embedded Systems, KAIST 3

 The VLSI Ruby II Advanced
Communication Processor (II)
„ Ruby II organization
„ Based on an ARM core
„ 2 Kbytes of fast (zero wait state) on-chip SRAM
„ Critical routines can be loaded to get the best performance and
minimum power consumption
„ Peripheral modules
„ PCMCIA interface
„ Four byte-wide parallel interfaces
„ Two UARTs
„ Byte-wide FIFO buffers
„ Synchronous communications controller
„ Serial controller: I2C for battery-backed RAM, real-time clock, E2PROM,
and audio codec
„ External bus interface
„ 8-, 16-, and 32-bit data buses and flexible wait state generation
„ Counter/timer block
„ Three 8-bit counters connected to a 24-bit prescaler
„ Interrupt controller
„ Programmable control of all on- and off-chip interrupt sources
Embedded Systems, KAIST 4
 The VLSI Ruby II Advanced
Communication Processor (III)
„ Ruby II power-management modes
„ 1. On-line – all circuits are clocked at full speed
„ 2. Command – the ARM core runs with 1 to 64 wait states but all
other circuitry runs at full speed. An interrupt switches the system
into on-line mode immediately.
„ 3. Sleep – all circuitry is stopped apart from the timers and
oscillators. Particular interrupts return the system to on-line mode.
„ 4. Stopped – all circuits (including the oscillators) are stopped.
Particular interrupts return the system to on-line mode.

„ Packaging
„ 144- and 176-pin thin quad flat packs
„ Up to 32 MHz at 5 V.
„ At 20 MHz, 30 mA in on-line mode, 7.9 mA in command mode, 1.5
mA in sleep mode, and 150 uA in stop mode.
Embedded Systems, KAIST 5
 1.8 The VLSI ISDN Subscriber
Processor (VIP)
„ VIP
„ Programmable engine for ISDN (Integrated Services Digital Network,
a digital telephony standard) subscriber communications
„ Developed by Hagenuk GmbH
„ Licensed to VLSI Technology for sale as ASSP (Application Specific
Standard Part)

„ Incorporates most of the circuitry required to implement a full-

feature ISDN terminal, supporting voice, data, and video services
„ ISDN S0-interface, a numeric keypad, a number display, a microphone
and an earphone

„ Applications
„ ISDN terminal equipment: PABX telephones, H.320 videophones,
integrated PC communications
„ ISDN to DECT (Digital European Cordless Telephone) controllers
„ ISDN to PCMCIA communication cards.
Embedded Systems, KAIST 6
 The VLSI ISDN Subscriber Processor (II)

„ Typical VIP system configuration

volume

V24 interface
hands-free
Driver
hook switch
S0-ISDN interface ISDN
Subscriber
Processor

power ROM
K E Y
P A D
RAM

Embedded Systems, KAIST 7

 The VLSI ISDN Subscriber Processor (III)
external
„ VIP organization (Inside) interrupts (3)

clock clock
control ARM6 768 x 32 interrupt timer &
core SRAM controller watchdog

ports parallel control

interface
external address (23)
bus
handset/ G.71 1 control
hands-free codec data (8/16/32)

S0 -interface B and D
channels
mux address
DRAM
battery, volume controller ras, cas
ADCs (2)

serial DSP address chip selects

serial i/f decoder

Embedded Systems, KAIST 8

 The VLSI ISDN Subscriber Processor (IV)

„ Memory interface
„ Supports 8-, 16-, and 32-bit off-chip static RAMs and ROMs and 16- and
32-bit dynamic RAMs
„ Divided into 4 ranges, each with programmable number of wait states
„ 3 Kbyte on-chip RAM

„ S0-interface
„ Connection to an S0-interface bus via isolating transformers and surge
protection
„ PLL for data and clock recovery, framing, and low-level protocols
„ 192 Kbit/s raw data includes two 64 Kbit/s B channels (8-bit 8 KHz speech
samples) and one 16 Kbit/s D channel (control purposes)

„ Codec
„ G.711 codec
„ On-chip analog front end: Direct connection to a telephone handset and a
hands-free microphone and speaker
„ Input and output independent programmable gains
„ Amplification stages have power-down modes to save power.
Embedded Systems, KAIST 9
 The VLSI ISDN Subscriber Processor (V)

„ ADCs
„ Based on timing how long it takes to discharge a capacitor to the
input voltage level
„ Very simple way to measure slowly varying voltages
„ Comparator and counter
„ Measure the voltage from a volume control potentiometer or to
check the battery voltage in a portable application

„ Keypad interface
„ Parallel output ports to strobe the columns of the keypad
„ Parallel input ports with internal pull-down resistors to sense the
rows
„ Key press will generate an interrupt:
„ ARM can activate individual columns and sense rows.

„ Clocks and timers

„ 38.864 MHz and 460.8 KHz during power-down
„ Watchdog at every 1.28 sec
„ 2.5 ms timer interrupts for DRAM refresh and multitasking.
Embedded Systems, KAIST 10
 1.9 The OneC VWS22100 GSM
Chip
„ OneC VW22100
„ Developed by VLSI Technology, Inc

„ System-on-chip design for GSM

mobile telephone handset

„ All the functions required in a

handset with addition of external
program and data memory and a
suitable radio module

„ Example: Samsung SGH2400, a

dual-band (GSM 900/1800)
handset with hands-free voice-
activated dialing ->

Embedded Systems, KAIST 11

 The OneC VWS22100 GSM Chip (II)

„ Typical GSM handset architecture

SIM
card eeprom IrDA
speaker

radio
mic module
VWS22100
ringer

ROM
K E Y
P A D
RAM

LCD

Embedded Systems, KAIST 12

The OneC VWS22100 boot

GSM Chip (III)

(6) JTAG ARM7TDMI interrupt ROM
test/debug core controller
(6)
UART1

„ VWS22100 (13)
UART2/
IrDA
(4)

organization audio i/f PCM i/f

high-speed (5)
serial i/f (2)
ARM7TDMI core
(20) DSP radio
„ radio i/f port
(4)
„ General SIM i/f

DSP bus
program program
purpose ROM RAM 32 KHz

hardware
coprocs
controller RTC

„ GSM protocol cntrl (6)

layers external addr (20)

„ DSP core Oak DSP

core
memory
controller
bus
control
data (16)

„ Baseband

ARM bus
DSP
signal subsystem (7)
processing ADC

data data power keypad (10)

ROM RAM manager scanner

interrupt config./ GPIO (11)

controller status PWM

Embedded Systems, KAIST 13

 The OneC VWS22100 GSM Chip (IV)
„ DSP subsystem „ ARM7TDMI subsystem
„ Based on the 16-bit Oak
DSP core
„ Real-time signal
processing functions
„ Voice coding
„ Equalization
„ Channel coding
„ Echo cancellation
„ Noise suppression
„ Voice recognition
„ Data compression
Embedded Systems, KAIST
„ Responsible for the
system control functions
„ The user interface
software
„ The GSM protocol stack
„ Power management
„ Driving the peripheral
interface
„ Running some data
applications
14
 The OneC VWS22100 GSM Chip (V)
„ On-chip debug
„ Single JTAG interface
„ ARM7TDMI EmbeddedICE module
„ Debug technology on the Oak DSP core
„ Other test and debug facilities

„ Power management
„ Global and selective power-down modes
„ The ability to slow down the system clock in idle mode
„ The analog circuits also can operate at reduced power
„ The on-chip pulse-width modulation outputs control battery
charging
„ The on-chip ADCs provide for the monitoring of the
temperature and battery voltage to give optimum operation.
Embedded Systems, KAIST 15
 1.10 The Ericsson-VLSI Bluetooth
Baseband Controller
„ Bluetooth
„ De-facto standard for wireless data communication for the 2.4
GHz band
„ Consortium of Ericsson, IBM, Intel, Nokia, and Toshiba
„ Support short-range communication (to 10 m range) using radio
communication with 1 Mbit/s
„ Robust communication in a noisy and uncoordinated environment
„ Frequency hopping scheme and forward error correction
„ For laptop, cellular telephone, printer, PDA, desktop, fax, keyboards,
and so on
„ Provide bridge to existing networks

„ Bluetooth ‘piconet’
„ Bluetooth units dynamically form ad hoc ‘piconets’, which are
groups of 2 to 8 units that operate the same frequency-hopping
scheme
„ One of the units will operate as master: Defines the clock and
hopping sequence.

Embedded Systems, KAIST 16

 The Ericcson-VLSI Bluetooth Baseband
Controller (II)

„ Bluetooth system
„ A typical Bluetooth system

flash address Bluetooth

Baseband radio
memory
flash module
memory Controller
data

control

host interface
(RS232/USB)

Embedded Systems, KAIST 17

 The Ericcson-VLSI Bluetooth Baseband
Controller (III)

„ Bluetooth controller organization

clock clock
control ARM7TDMI 4 Kbyte internal 16K x 32
core I-cache ROM SRAM
JTAG
signals (5)

control

interrupt counter/ ex ternal address (20)

controller timers bus
control
data (8/16)

UART1,2,3

I/O EBC radio interface

mode 2
I C i/f FIFOs block
select

USB i/f

Embedded Systems, KAIST 18

 The Ericcson-VLSI Bluetooth Baseband
Controller (IV)
„ Ericsson Bluetooth core
„ Power-optimized hardware block
„ Handles all the Link Controller functionality within the Bluetooth
specification
„ Interface logic to a Bluetooth radio communication
„ Performs all the packet-handling functions for point-to-point,
multislot, and point-to-multipoint communications
„ Combination of circuit and packet switching

„ Power management
„ 1. On-line: all blocks are clocked at their normal speed. The
ARM7TDMI core clock 13 to 40 MHz. 40 mA max.
„ 2. Command: The ARM7TDMI clock is slowed down by the insertion
of wait states
„ 3. Sleep: The ARM7TDMI click is stopped. 0.3 mA.
„ 4. Stopped: The clock oscillator is turned off.

Embedded Systems, KAIST 19

 The Ericcson-VLSI Bluetooth Baseband
Controller (V)

„ Bluetooth silicon
„ Photograph of a
Bluetooth die ->
„ Bluetooth
characteristics
„ Process 0.35 um
„ Transistors 4,300,000
„ MIPS 12
„ Metal layers 3
„ Die area 20 mm2
„ Power 75 mW
„ Vdd 2.5 V
„ Clock 0-13 MHz
„ MIPS/W 160
Embedded Systems, KAIST 20
 1.11 The ARM7500 and ARM7500FE
„ Features
„ Highly integrated single-chip computer
„ Combines the major components of the Acorn Risc PC

„ Principal macrocells
„ The ARM CPU core
„ The FPA10 floating-point coprocessor (ARM7500FE)
„ The video and sound macrocell
„ The memory and I/O controller

Embedded Systems, KAIST 21

 The ARM7500 and ARM7500FE (II)
„ The ARM CPU core
„ Contains most of the functionality of the ARM710
„ ARM7TDMI without Thumb and embedded debug support
„ Reduced cache 4 Kbytes (from 8 Kbytes)
„ 4-way set-associative mixed instruction and data cache
„ Memory management unit
„ Based on a 2-level page table
„ 64-entry translation look-aside buffer
„ A write buffer

„ The FPA10 floating-point unit

„ Up to 6 MFLOPS at 40 MHz

Embedded Systems, KAIST 22

 The ARM7500 and ARM7500FE (III)

„ The video and sound macrocell

„ Video controller
„ Generate displays using a pixel clock of up to 120 MHz
„ 256-entry color palette with on-chip 8-bit DACs for RGB
„ Additional control bits for external mixing and fading
„ Support a separate hardware cursor
„ Can drive a high-resolution color monitor or single- or
double-panel grey-scale or color LCD
„ Sound controller
„ 8 independent channels of 8-bit analog stereo sound
„ Played through an on-chip exponential DAC
„ 16-bit sound samples through a serial digital channel and an
external CD-quality DAC
„ DMA controller for video/audio data channels
Embedded Systems, KAIST 23
 The ARM7500 and ARM7500FE (IV)
„ The memory and I/O controller
„ Memory controller
„ Direct connection of up to four banks of DRAM and two banks of ROM
„ Programmed to be 16 or 32 bits wide
„ Double access for 32-bit quantities in 16-bit banks
„ DRAM controller
„ Page mode accesses for sequential cycles in bursts of up to 256
transfers
„ Supports a range of DRAM refresh modes
„ ROM controller
„ Supports burst mode
„ 3 DMA controller
„ Handle data streams for video, cursor, and audio channels
„ I/O controller
„ Manages 16-bit off-chip I/O bus
„ Number of on-chip interfaces: 4 comparators, 2 serial ports,
counter/timers, 8 general-purpose open-drain I/O lines, and
programmable interrupt controller.
Embedded Systems, KAIST 24
 The ARM7500 and ARM7500FE (V)
„ Typical ARM7500
system diagram cas[3:0]

DRAM

DRAM

DRAM

DRAM
DRAM

DRAM

DRAM

DRAM
RA[11:0]

DRAM

DRAM

DRAM

DRAM
video
analogue
sound

DRAM

DRAM

DRAM

DRAM
ras[3:0]
ARM7500
D[31:0]

ROM

ROM
analogue
inputs

LA[28:0]

module

interrupts
selects
keyboard
& mouse
I/O I/O
module module

BD[15:0]

Embedded Systems, KAIST 25

 The ARM7500 and ARM7500FE (VI)

„ Applications
„ Low-cost versions of the Acorn Risc PC
„ Online Media interactive video set-top box
„ Restricting the video data stream to normal DRAM
„ High-resolution displays
„ 1280 x 1024 and above the number of colors become
restricted due to the bandwidth limitations of standard DRAM
„ Ideally suited
„ LCD at VGA (640 x 480)
„ TV quality display
„ Hand-held test equipment
„ Multimedia applications.

Embedded Systems, KAIST 26

The ARM7500 and ARM7500FE (VII)
„ ARM7500 silicon ->
„ 5% ARM core area

„ ARM7500
characteristics
„ Process 0.6 um
„ Transistors 550,000
„ MIPS 30
„ Metal layers 2
„ Die area 70 mm2
„ Power 690 mW
„ Vdd 5 V
„ Clock 0-33 MHz
„ MIPS/W 43

Embedded Systems, KAIST 27

 1.12 The ARM7100
„ Features
„ Highly integrated microcontroller
„ Suited to a range of mobile applications
„ Smart mobile phones and palm-top computers
„ Psion Series 5MX ->

Embedded Systems, KAIST 28

 The ARM7100 (II)
„ The Psion Series 5 hardware
DRAM ROM Flash
organization
„ Principal user input devices
„ Keyboard: parallel I/O
„ Stylus pointing device: PSU

transparent digitizing tablet ARM7100

overlaid on the LCD display PC cards
ADC

„ Infrared via ADC

infrared IrDA Tx/Rx
„ Communication digitizing
tablet
„ RS232C serial interface
RS232
„ IrDA compliant infrared
interface for wireless 640 x 240
LCD
connection to printers,
modems, and host PCs audio codec

„ Audio codec: microphone keyboard

and speaker
Embedded Systems, KAIST 29
 The ARM7100 (III)
„ ARM7100 organization ARM710a

„ ARM710a CPU
ARM7 8 Kbyte LCD interrupt
„ ARM MMU MMU core cache controller controller

„ 8 Kbyte 4-way
associative quad- AMBA

word line cache

„ 4-address 8-data 3.6864 MHz control

word write buffer clock PLL

power counter/ external address (28)
bus
„ AMBA bus 32.786 KHz
mgt. timers
control
data (32)
„ Peripherals RTC
osc.
„ LCD controller
UART DRA(13)
„ Serial & parallel I/O
FIFOs
ports DRAM
controller
RAS, CAS (8)

„ Interrupt controller codec i/f WE , OE(2)

„ 32-bit external bus

interface sync serial expansion

„ DRAM controller
parallel I/O PSU control

Embedded Systems, KAIST 30

 The ARM7100 (IV)
„ Power management
„ Intended for use in battery-powered equipment
„ High performance in response to user input
„ Operate at very low power consumption levels
„ Levels
„ Full operation mode: 14 MIPS, 24 mA at 3 V
„ Idle mode: CPU stopped but other systems running. 33 mW
„ Standby mode: 32 KHz running. 33 uW
„ Other features to enhance power-efficiency
„ Support for self-refresh DRAM.

Embedded Systems, KAIST 31

 The ARM7100 (V)
„ ARM7100 silicon ->

„ ARM7100 principal
characteristics
„ Process 0.6 um
„ Transistor N/A
MIPS 30
„ Metal layers 2
„ Die area N/A
„ Power 14 mW
„ Vdd 3.3 V
„ Clock 18.432 MHz
„ MIPS/W 212

Embedded Systems, KAIST 32

 1.13 The SA-1100

„ Features
„ High-performance integrated system-on-chip
„ Based on a modified version of SA-110 StrongARM CPU core
„ Intended for use in mobile phone handsets, modems, and
other handheld applications
„ High performance with minimal power consumption.

Embedded Systems, KAIST 33

The SA-1100 (II)

mini-cache
cache
data
instruction instruction SA-1 data
MMU cache core MMU

„ SA-1100 organization

CPU core write buffer read buffer

system bus

data (32)
LCD (5) address (26)
LCD DMA memory &
control control bridge PCMCIA control

3.6864 MHz
clock interrupt USB (2)
PLL control serial 0
32.786 KHz
RTC SDLC (2)
osc. RTC serial 1

I/O pins (28) IrDA (2)

general-
purpose I/O serial 2
OS
timer UART (2)
battery (3) serial 3
power
manager
reset (2) reset Codec (4)
control serial 4
peripheral bus

Embedded Systems, KAIST 34

 The SA-1100 (III)
„ CPU core
„ SA-1 processor core
„ Exception vector relocation mechanism (for Windows CE)
„ 16 Kbyte instruction cache using a 32-way associative
CAM-RAM structure with 8-word lines
„ MMU with ProcessID mechanism (for Windows CE)
„ 8 Kbyte 32-way associative data cache in parallel with a
512 byte 2-way set-associative cache
„ Allow large data structures to be cached without causing
major pollution of the main data cache
„ Addition of read buffer
„ Pre-load data before the processor requests
„ Addition of hardware breakpoint and watchpoint registers.

Embedded Systems, KAIST 35

 The SA-1100 (IV)
„ Memory controller
„ Up to 4 banks of 32-bit off-chip DRAM
„ Conventional or ‘extended data out (EDO)’ variety
„ ROM, flash, and SRAM are also supported
„ PCMCIA interface
„ Two card slots are supported with some external ‘glue’ logic

„ System control
„ On-chip
„ A reset controller
„ A power management controller that handles low-battery
warnings and switches the system between its various
operating modes
„ An operating system timer block that supports general timing
and watchdog functions
„ An interrupt controller
„ A real-time clock that runs from a 32 KHz crystal source
„ 28 general-purpose I/O pins.
Embedded Systems, KAIST 36
 The SA-1100 (V)
„ Peripherals
„ LCD controlelr
„ Serial ports: USB, SDLC, IrDA, codec, and standard UART
„ 6-channel DMA
„ Bus structure
„ Two buses connected through a bridge
„ The system bus: connects all the bus masters and the off-chip
memory
„ The peripheral bus: connects all the slave peripheral devices
„ Similar to AMBA ASB-APB split
„ Minimizes the bus width
„ Reduces the complexity and cost
„ Applications
„ Off-chip memory: DRAM and ROM/flash
„ Necessary interface electronics for the various peripheral
interfaces, display, and so on
„ Very simple at the PCB level, yet very powerful processing
capability and sophisticated system architecture.

Embedded Systems, KAIST 37

 The SA-1100 (VI)

„ SA-1100 silicon ->

„ Characteristics
„ Process 0.35 um
„ Transistors
2,500,000
„ MIPS 220/250
„ Metal layers 3
„ Die area 75 mm2
„ Power 330/550 mW
„ Vdd 1.5/2V
„ Clock 180/220 MHz
„ MIPS/W 665/450

Embedded Systems, KAIST 38

 1.14 Mio 168
„ Pocket PC with Integrated GPS
„ Runs on Windows Mobile 2003
for Pocket PC
„ Utilizes an Intel XScale
processor
„ A 16-bit TFT LCD display with LED
backlighting offers up to 65,536
colors

„ Bundled with a complete

navigation software package
„ Routing: Easy-to-follow turn-
by-turn visual and voice
prompts guide you to your
destination
„ Plan trips and optimize routes
with multi-point routing feature
„ Automatic route recalculation
suggests an alternate route if
you take a wrong turn.
Embedded Systems, KAIST 39
 Function Specification
CPU Intel® Xscale 300 MHz
Operating System Windiws Mobile™ software for Pocket PCs
3.5 color Transflective LCD, LED Backlighting, 240 x 320,
Display
65K colors
Memory 32MB Flash ROM. 64MB SDRAM
Audio Voice Recording(Mono). MP3 Playback support. Media Player
Input Method Stylus pen/Software kdyboard/Handwriting Recognition
Expansion Slot SD/MMC. SD IO
Microphone Builit-in type x 1(Mono)
Speaker Builit-in Monaural type speaker x 1

I/O Headphone 2.5mm Mini jack x 1

USB USB 1.1 Client for ActiveSync
Infrared IrDA (SIR). Consumer IR (4 meters)
Embedded Lithium lon Battery 1350mAh
battery Active:12 hours(fully charged main battery, w/o GPS)
Suspend:21 days(fully charged main battery)
Dimension 112.8 mm (H) x 69.6 mm (W) x 16.3~24.15mm (D)
Weight 147g
Input 100~240VAC;
Power Supply
Embedded Systems, KAIST 40
Output 5VDC, 1A DC