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Unit II
ARM7,ARM9,ARM11 processors
ARM - Introduction
Advances RISC Machines (now known as ARM) was established
as a joint venture between Acorn, Apple and VLSI between Acorn,
Apple and VLSI in November 1990
ARM is the industry's leading provider of 16/32-bit embedded
RISC microprocessor solutions
The company licenses its high-performance, low-cost, power-
efficient RISC processors, peripherals, and system-chip designs
to leading international electronics companies
ARM provides comprehensive support required in
developing a complete system
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ARM Processor Versions
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Development of the ARM Architecture
v4 v5 v6 v7
Halfword and Improved SIMD Instructions
Thumb-2
signed halfword / interworking Multi-processing
byte support CLZ v6 Memory architecture
Architecture Profiles
Saturated arithmetic Unaligned data support
System mode DSP MAC 7-A -
instructions Extensions: Applications
Thumb Thumb-2 7-R - Real-time
instruction set Extensions: (6T2) 7-M -
(v4T) Jazelle TrustZone® Microcontroller
(5TEJ) (6Z)
Multicore
(6K)
Thumb only
(6-M)
Note that implementations of the same architecture can be
different
Cortex-A8 - architecture v7-A, with a 13-stage pipeline
Cortex-A9 - architecture v7-A, with an 8-stage pipeline
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ARM - Introduction
Arm 7
– The ARM7 cell is functionally identical to the ARM6 cell in capabilities but may
be clocked faster than the ARM6
– A variant of the ARM7 cell offers an improved hardware multiply, suitable for
DSP work
Arm 8
– Includes a five stage pipeline, a speculative instruction fetcher and internal
tweaks to the processor to allow a higher clock speed
StrongARM
– This is the high speed variant of the ARM chip family
– Architecturally it is similar to the ARM8 core, sharing the five stage pipeline
with that processor
– A further difference is change from a unified data and instruction cache to a
split, Harvard architecture, instruction and data cache
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ARM - Introduction
ARM9
– An incremental improvement over the ARM8 this chip features the
same five stage pipeline but is now a Harvard Architecture chip, like
the StrongARM
ARM 10
– 300 MHz
– 400 MIPS
– 600 mWatts
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Comparisons of ARM Processor
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ARM Powered Products
Consumer
Automotive Digital Imaging
Entertainment
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ARM7 - Features
32-bit RISC processor (32-bit data & address bus)
Big and Little Endian operating modes
High performance RISC (17 MIPS sustained @ 25 MHz (25 MIPS
peak) @ 3V)
Low power consumption (0.6mA/MHz @ 3V fabricated in .8µm
CMOS)
Fully static operation (ideal for power-sensitive applications)
Fast interrupt response (for real-time applications)
Virtual Memory System Support
Excellent high-level language support
Simple but powerful instruction set
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ARM7 - Applications
The ARM7 is ideally suited to those applications requiring RISC
performance from a compact, power-efficient processor
– Telecomms - GSM terminal controller
– Datacomms - Protocol conversion
– Portable Computing - Palmtop computer
– Portable Instrument - Hendheld data acquisition unit
– Automotive - Engine management unit
– Information systems - Smart cards
– Imaging - JPEG controller
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ARM9 - Features
Some of the features offered by the ARM9 processor are:
Java acceleration
DSP extensions
Optional floating point unit
Flexible local memory system with cache and exceptional Tightly
Coupled Memory (TCM) integration
Binary compatibility with the ARM7TDMI® processor
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ARM9 - Applications
Product Type Application
Smartphones, PDA, Set top box,
Consumer PMP, Electronic toys, Digital still
cameras, Digital video cameras etc
Wireless LAN, 802.11, Bluetooth,
Networking Firewire, SCSI, 2.5G/3G Baseband
etc
Power train, ABS, Body systems,
Automotive
Navigation, Infotainment etc
USB controllers,bluetooth controllers,
Embedded
medical scanners etc
HDD controllers, solid state drives
Storage
etc
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ARM11 - Features
Powerful ARMv6 instruction set architecture ARM Thumb® instruction
set reduces memory bandwidth and size requirements by up to 35% ARM
Jazelle® technology for efficient embedded Java execution ARM DSP
extensions SIMD (Single Instruction Multiple Data) media processing
extensions deliver up to 2x performance for video processing ARM
TrustZone® technology for on-chip security foundation (ARM1176JZ-S and
ARM1176JZF-S processors) Thumb-2 technology (ARM1156(F)-S only) for
enhanced performance, energy efficiency and code density Low power
consumption: 0.21 mW/MHz (65G) including cache controllers
Energy saving power-down modes address static leakage currents in
advanced processes
High performance integer processor 8-stage integer pipeline delivers high
clock frequency (9 stages for ARM1156T2(F)-S)
Separate load-store and arithmetic pipelines
Branch Prediction and Return Stack
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ARM11 - Applications
Wireless:-
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ARM7 - Block Diagram
A[31:0]
AL E nEX EC
D AT A32
I B IG EN D
Address R egister n PR O G 32
c
r MCLK
e nW AIT
P m
e nR W
C n
A Address nB W
L B t
U u Increm enter e Instruction nIR Q
s r nF IQ
B Decoder &
u B nR E SE T
s u C ontrol Logic
s AB O R T
R egister B ank nO PC
(31 x 32 bit registers) nT R AN S
(6 status registers) nM R E Q
SEQ
LOCK
nC P I
B CPA
A CPB
B ooth's b
b u nM [4:0]
u M ultiplier s
s
Barrel S hifter
P R O G 32 D AT A[31:0]
C o nfig uratio n D AT A32
B IG E N D D O U T [31:0]
nEN O U T M em o ry
nEXE C Interface
nM R EQ
nIR Q ARM 7 SEQ
Interrup ts nF IQ nR W
nB W
nR E SE T LO C K
AL E nT R AN S M em o ry
B us C ontrols AB O R T M anag em e nt
DBE Interface
nO PC
VD D nC PI C o p ro ce ssor
Po w er V SS CPA Interface
CPB
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ARM7 - Signal Description
Clocks Bus Controls
– MCLK Memory Clock Input – ALE Address latch enable
– nWAIT Not wait – DBE Data bus enable
Configuration Power
– PROG32 32 bit program – VDD Power supply
configuration – VSS Ground
– DATA32 32 bit data configuration Processor Mode
– BIGEND Big Endian configuration – nM[4:0] Not processor mode
Interrupts
– nIRQ Not interrupt request
– nFIQ Not fast interrupt request
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ARM7 - Signal Description
Memory Interface Memory Management Interface
– A[31:0] Addresses – nTRANS Not memory translate
– DATA[31:0] Data bus in – ABORT Memory abort
– DOUT[31:0] Data bus out Coprocessor Interface
– nENOUT Not enable data – nOPC Not op-code fetch
outputs – nCPI Not coprocessor
– nMREQ Not memory request instruction
– SEQ Sequential address – CPA Coprocessor absent
– nRW Not read/write – CPB Coprocessor busy
– nBW Not byte/word Other
– LOCK Locked operation – nEXEC ******************
– nRESET Not reset
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ARM Core data flow
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ARM Core data flow Contd..
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Data Sizes and Instruction Sets
ARM is a 32-bit load / store RISC architecture
– The only memory accesses allowed are loads and stores
– Most internal registers are 32 bits wide
– Most instructions execute in a single cycle
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ARM7 - Programmer’s Model
37 registers
– 31 general 32 bit registers
– 6 status registers
16 general registers and one or two status registers are visible at
any time
The visible registers depend on the processor mode
The other registers (the banked registers) are switched in to
support IRQ, FIQ, Supervisor, Abort and Undefined mode
processing
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ARM7 - Registers
R0 to R15 are directly accessible
– R0 to R14 are general purpose
– R15 holds the Program Counter (PC)
CPSR - Current Program Status Register contains condition code
flags and the current mode bits
5 SPSRs (Saved Program Status Registers) which are loaded with
CPSR when an exceptions occurs
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The ARM Register Set
User mode IRQ FIQ Undef Abort SVC
r0
r1
r2 ARM has 37 registers, all 32-bits long
r3
r4 A subset of these registers is accessible in each
r5 mode
r6 Note: System mode uses the User mode
r7 register set.
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
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ARM7 - Registers
R14 is used as the subroutine link register and receives a copy of
R15 when a Branch and Link instruction is executed
R14_svc, R14_irq, R14_fiq, R14_abt and R14_und are used to
– hold the return values of R15 when interrupts and exceptions arise,
– when Branch and Link instructions are executed within interrupt or
exception routines
FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-
R14_fiq)
User mode, IRQ mode, Supervisor mode, Abort mode and
Undefined mode each have two banked registers mapped to R13
and R14
The two banked registers allow these modes to each have a
private stack pointer and link register
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ARM7 - Registers
The N, Z, C and V are condition code flags
– may be changed as a result of arithmetic and logical operations in the
processor
– may be tested by all instructions to determine if the instruction is to be
executed
The I and F bits are the interrupt disable bits
The M0, M1, M2, M3 and M4 bits are the mode bits
31 30 29 28 27 8 7 6 5 4 3 2 1 0
N Z C V F I M4 M3 M2 M1 M0
O verflo w M o d e B its
C arry/B o rro w /Extend F IQ d isab le
Z ero IR Q d isab le
N eg ative/L ess T han
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ARM7 - Registers
The Mode Bits
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Processor Modes
ARM has seven basic operating modes
– Each mode has access to its own stack space and a different subset of
registers
– Some operations can only be carried out in a privileged mode
Mode Description
Supervisor Entered on reset and when a Supervisor call
(SVC) instruction (SVC) is executed
Exception modes
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ARM7 - Exceptions
Exceptions arise whenever there is a need for the normal flow of
program execution to be broken, so that the processor can be
diverted to handle an interrupt from a peripheral
Many exceptions may arise at the same time
When multiple exceptions arise simultaneously, a fixed priority
determines the order in which they are handled
ARM7 handles exceptions by making use of the banked registers
to save state
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ARM7 - Exceptions
Types of Exceptions
FIQ (Fast Interrupt reQuest)
– The FIQ exception is externally generated by taking the nFIQ input LOW.
– This input can accept asynchronous transitions, and is delayed by one
clock cycle for synchronisation before it can affect the processor
execution flow
IRQ (Interrupt ReQuest)
– The IRQ exception is a normal interrupt caused by a LOW level on the
nIRQ input
ABORT
– An ABORT can be signalled by the external ABORT input
– ABORT indicates that the current memory access cannot be completed
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ARM7 - Exceptions
Types of Exceptions
Software interrupt
– The software interrupt instruction (SWI) is used for getting into
Supervisor mode, usually to request a particular supervisor function
Undefined instruction trap
– When the ARM7 comes across an instruction which it cannot handle it
offers it to any coprocessors which may be present
– If a coprocessor can perform this instruction but is busy at that time,
ARM7 will wait until the coprocessor is ready or until an interrupt
occurs
– If no coprocessor can handle the instruction then ARM7 will take the
undefined instruction trap
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ARM7 - Exceptions
Exception Priorities
(1) Reset (highest priority)
(2) Data abort
(3) FIQ
(4) IRQ
(5) Prefetch abort
(6) Undefined Instruction, Software interrupt (lowest priority)
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ARM7 - Reset
When the nRESET signal goes LOW, ARM7 abandons the
executing instruction and then continues to fetch instructions
from incrementing word addresses
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ARM7 - Instruction Set
Instruction Set Summary
31 28 19 15 11 7 3 0
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ARM7 - Instruction Set
The Condition Field
31 27 0
Cond
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ARM7 - Instruction Set
31 27 0
Cond
Condition field
– 0000 = EQ - Z set (equal)
– 0001 = NE - Z clear (not equal)
– 0010 = CS - C set (unsigned higher or same)
– 0011 = CC - C clear (unsigned lower)
– 0100 = MI - N set (negative)
– 0101 = PL - N clear (positive or zero)
– 0110 = VS - V set (overflow)
– 0111 = VC - V clear (no overflow)
– 1000 = HI - C set and Z clear (unsigned higher)
– 1001 = LS - C clear or Z set (unsigned lower or same)
– 1010 = GE - N set and V set, or N clear and V clear (greater or equal)
– 1011 = LT - N set and V clear, or N clear and V set (less than)
– 1100 = GT - Z clear, and either N set and V set, or N clear and V clear (greater than)
– 1101 = LE - Z set, or N set and V clear, or N clear and V set (less than or equal)
– 1110 = AL - always
– 1111 = NV - never
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ARM7 - Instruction Set
MUL - Multiply Only
MLA - Multiply and Accumulate
B - Branch
BL - Branch with Link
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ARM7 - Instruction Set
Data Processing
Logical Operations
Assembler
OpCode Action
Mnemonic
AND 0000 operand1 AND operand2
EOR 0001 operand1 EOR operand2
TST 1000 as AND, but result is not written
TEQ 1001 as EOR, but result is not written
ORR 1100 operand1 OR operand2
MOV 1101 operand2 (operand1 is ignored)
BIC 1110 operand1 AND NOT operand2 Bit clear)
MVN 1111 NOT operand2 (operand1 is ignored)
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ARM7 - Instruction Set
Data Processing
Arithmetic Operations
Assembler
OpCode Action
Mnemonic
SUB 0010 operand1-operand2
RSB 0011 operand2-operand1
ADD 0100 operand1+operand2
ADC 0101 operand1+operand2+carry
SBC 0110 operand1-operand2+carry-1
RSC 0111 operand2-operand1+carry-1
CMP 1010 as SUB, but result is not written
CMN 1011 as ADD, but result is not written
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ARM7 - Instruction Set
PSR Transfer (MRS, MSR)
The MRS and MSR instructions are formed from a subset of the
Data Processing operations
They are implemented using the TEQ, TST, CMN and CMP
instructions without the S flag set
These instructions allow access to the CPSR and SPSR registers:
– The MRS instruction allows the contents of the CPSR or
SPSR_<mode> to be moved to a general register
– The MSR instruction allows the contents of a general register to be
moved to the CPSR or SPSR_<mode> register
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ARM7 - Instruction Set
Single data transfer (LDR, STR)
The single data transfer instructions are used to load or store
single bytes or words of data
The memory address used in the transfer is calculated by adding
an offset to or subtracting an offset from a base register
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ARM7 - Instruction Set
Block data transfer (LDM, STM)
Block data transfer instructions are used to load (LDM) or store
(STM) any subset of the currently visible registers
They support all possible stacking modes, maintaining full or
empty stacks which can grow up or down memory, and are very
efficient instructions for saving or restoring context, or for moving
large blocks of data around main memory
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ARM7 - Instruction Set
Single data swap (SWP)
The data swap instruction is used to swap a byte or word quantity
between a register and external memory
This instruction is implemented as a memory read followed by a
memory write which are “locked” together (the processor cannot
be interrupted until both operations have completed, and the
memory manager is warned to treat them as inseparable)
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ARM7 - Instruction Set
Software interrupt (SWI)
The software interrupt instruction is used to enter Supervisor
mode in a controlled manner
The instruction causes the software interrupt trap to be taken,
which effects the mode change
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ARM7 - Instruction Set
Coprocessor data operations (CDP)
This class of instruction is used to tell a coprocessor to perform
some internal operation
No result is communicated back to ARM7, and it will not wait for
the operation to complete
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ARM7 - Instruction Set
Coprocessor register transfers (MRC, MCR)
This class of instruction is used to communicate information
directly between ARM7 and a coprocessor
Undefined instruction
If the condition is true, the undefined instruction trap will be taken
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Thank You
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