R.M.K.

ENGINEERING COLLEGE
(An Autonomous Institution)
R.S.M. NAGAR, KAVARAPETTAI.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

20EC602 -Embedded Systems

UNIT - II
TOPIC: INTRODUCTION TO ARM PROCESSOR

By:
Mr. R Babuji,
Assistant Professor,
Dept. of ECE/RMKEC
1 / 11
Contents

1 ARM Architecture Versions

2 ARM Architecture

3 Instruction Set

4 Stacks and Subroutines

2 / 11
Introduction to ARM
Popular Manufacturers of ARM

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Add title here

5 / 11
 What is ARM?

 The ARM stands for Advanced RISC Machine and it is a 32-bit Reduced Instructions Set
Computer (RISC) microcontroller.
 It was first introduced by the Acron computers’ organization in 1987.
 ARM is the world’s leading provider of RISC based microprocessor solutions and other
semiconductor IP’s with more than 85 billion ARM based chips being shipped to date.
 ARM doesn’t manufacture processors or other semiconductor devices but rather licenses
the semiconductor cores as Intellectual Property (IP) to other semiconductor companies
like ATMEL, Phillips (now NXP), Samsung etc.

6 / 11
ARM Introduction
• One of the most licensed and thus widespread processor cores in the
world.
Used in PDA, cell phones, multimedia players, handheld game
console, digital TV and cameras
• ARM7: GBA, iPod
• ARM9: NDS, PSP, Sony Ericsson, Ban
• ARM11: Apple iPhone, Nokia N93, N800
90% of 32-bit embedded RISC processors till 2009
Used especially in portable devices due to its
• low power consumption and reasonable performance

7 / 11
Why ARM?

 Reduced instruction set computing (RISC)

architecture.
 Load and Store type architecture where the data
processing is performed only on the contents of the
registers rather than directly on the memory.
 32-bit ARM Processors have two instruction sets:
General 32-bit ARM Instruction Set and 16-bit
Thumb Instruction Set.'
 ARM supports multiple stages of pipeline to speed
up the flow of instructions.

8 / 11
Three architecture profiles: A, R and M.
A-Profile (Applications) R-Profile (Real-Time) M-Profile (Microcontroller)

 Targeted at
 High
systems with
performance.  Small, highly
real-time
 Designed to run a power-efficient
requirements.
complex devices..
 Commonly found
operating system,  Found at the heart
in networking
such as Linux or of many IoT
equipment, and
Windows. devices.
embedded control
systems.

9 / 11
ARM Versions

Architecture ARM Family The letters or words after “ARM” are used to indicate
the features of a processor.
ARMv4T ARM7TDMI ARMxyzTDMIEJFS
ARMv5TE ARM9E x – Family or series
ARMv6 ARM11 y – Memory Management/Protection Unit
z – Cache
ARMv7-M Cortex-M
T – 16 bit Thumb decoder
ARMv7R Cortex-R D – JTAG Debugger
ARMv7-A Cortex-A (32-bit) M – Fast Multiplier
ARMv8-A Cortex-A (64-bit) I – Embedded In-circuit Emulator (ICE) Macrocell
E – Enhanced Instructions for DSP (assumes TDMI)
J – Jazelle (for accelerated JAVA execution)
F – Vector Floating-point Unit
S – Synthesizable Version
10 / 11
Popular ARM architectures
• ARM7TDMI
– 3 pipeline stages (fetch/decode/execute)
– High code density/low power consumption
– One of the most used ARM-version (for low-end systems)
– All ARM cores after ARM7TDMI include TDMI even if they do not
include TDMI in their labels
• ARM9TDMI
– Compatible with ARM7
– 5 stages (fetch/decode/execute/memory/write)
– Separate instruction and data cache
• ARM11
11 / 11
ARM family comparison

12 / 11
Computer Architecture

Von Neumann Harvard

TEXT

13 / 11
 CISC vs RISC

CISC RISC

• Instructions can take several • Single cycle instructions

clock cycles • Same length in set of
• Complex and variable length of instructions
Instructions. • Register to Register
• Memory to Memory • Low cycles per second large
• Small code sizes,high cycles per code sizes
second

14 / 11
 ARM 7
Architecture

15 / 11
 Processor and memory organization

The ARM architecture supports two

basic types of data:
• The standard ARM word is 32 bits
long.
• The word may be divided into
four 8-bit bytes.

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 Registers
Only 16 registers are visible to a
specific mode.
 A particular set of r0-r12
 r13 - (SP,stack pointer)
 r14 - (lr, link register)
 r15 - (pc, program counter)
 Current program status register
(CPSR)
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 User mode is the usual
ARM program execution
state, and is used for
executing most application
programs.

 Fast Interrupt (FIQ) mode

supports a data transfer or
channel process.

 Interrupt (IRQ) mode is

used for general-purpose
interrupt handling.

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CPSR

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Processor Modes
• The ARM has six operating modes:
– User (unprivileged mode under which most tasks run)
– FIQ (entered when a high priority (fast) interrupt is raised)
– IRQ (entered when a low priority (normal) interrupt is raised)
– Supervisor (entered on reset and when a Software Interrupt instruction is executed)
– Abort (used to handle memory access violations)
– Undef (used to handle undefined instructions)
• ARM Architecture Version 4 adds a seventh mode:
– System (privileged mode using the same registers as user mode)

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Register Organization

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 QUIZ

1.Most of processor designed by ARM is………..

a)16-bit
b)32-bit
c)64-bit
d)8-bit

Answer: 32-bit

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 QUIZ

2. ARM stands for ____________

a)Advanced Rate Machines
b) Advanced RISC Machines
c) Artificial Running Machines
d) Aviary Running Machines

Answer: Advanced RISC Machines

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 QUIZ

3.The main importance of ARM micro-processors is providing

operation with ______
a) Low cost and low power consumption
b) Higher degree of multi-tasking
c) Lower error or glitches
d) Efficient memory management
Answer: a) Low cost and low power consumption

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 QUIZ

4. ARM processors where basically designed for _______

a) Main frame systems
b) Distributed systems
c) Mobile systems
d) Super computers

Answer: c) Mobile systems

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 QUIZ

5. The address space in ARM is ___________

a) 224
b) 264
c) 216
d) 232

Answer: d) 232

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 QUIZ

6. The address system supported by ARM systems is/are

___________
a) Little Endian
b) Big Endian
c) X-Little Endian
d) Both Little & Big Endian

Answer: d) Both Little & Big Endian

27 / 11
ARM Instruction Set
 Instruction Set
ARM defines two separate Instruction Sets
• ARM State Instruction Set- 32 bit wide
• Thumb State Instruction Set- 16 bit wide
Features:
 All instructions are 32 bits long
 Most instructions execute in a single cycle.
 Most instructions can be conditionally executed.
 A load/store architecture
 Data processing instructions act only on registers
 Three operand format
 Instruction set extension via coprocessors
 Very dense 16 bit compressed instruction set (Thumb)
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Types of Instructions
• Data Processing Instructions
• Branch Instructions
• Load -Store Instructions
• Software Interrupt Instructions
• Program Status Register Instructions
• Coprocessor Instructions

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Instruction Format
Syntax:
<Operation>{<cond>}{S} Rd, Rn, Rm
cond- Indicates Flags to test.
S- Set Condition Flags in CPSR
Rd- Destination
Rn- 'Constant' or 1st Operand
Rm- Operand 2

31 / 11
Data Processing Instructions
• Largest family of ARM instructions, all sharing the same instruction
format.
• Contains:
– Arithmetic operations
– Comparisons (no results - just set condition codes)
– Logical operations
– Data movement between registers
• Remember, this is a load / store architecture
– These instruction only work on registers, NOT memory.
• They each perform a specific operation on one or two operands.
– First operand always a register - Rn
– Second operand sent to the ALU via barrel shifter.
• We will examine the barrel shifter shortly
32 / 11
Arithmetic Operations
• Operations are:
– ADD operand1 + operand2
– ADC operand1 + operand2 + carry
– SUB operand1 - operand2
– SBC operand1 - operand2 + carry -1
– RSB operand2 - operand1
– RSC operand2 - operand1 + carry - 1
• Syntax:
– <Operation>{<cond>}{S} Rd, Rn, Operand2
• Examples
– ADD r0, r1, r2
– ADD R0,R1,#2
– RSB r4, r5,r6
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Logical Operation Instructions
• Operations are:
– AND operand1 AND operand2
– EOR operand1 EOR operand2
– ORR operand1 OR operand2
– BIC operand1 AND NOT operand2 [ie bit clear]
• Syntax:
– <Operation>{<cond>}{S} Rd, Rn, Operand2
• Examples:
– AND r0, r1, r2
– BIC r0, r1, r2

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Move Instructions
• Operations are:
– MOV operand2
– MVN NOT operand2
Note that these make no use of operand1.
• Syntax:
– <Operation>{<cond>}{S} Rd, Operand2
• Examples:
– MOV r0, r1
– MVN
– MVN ro, r1

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 QUIZ

1. Memory can be accessed in ARM systems by __________

instructions.
i) Store
ii) MOVE
iii) Load
iv) arithmetic
v) logical
a) i, ii, iii
b) i, ii
c) i, iv, v
d) iii, iv, v

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 QUIZ

2. Each instruction in ARM machines is encoded into __________

Word.
a) 2 byte
b) 3 byte
c) 4 byte
d) 8 byte

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 QUIZ

3. All instructions in ARM are conditionally executed.

a) True
b) False

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 QUIZ

4. The banked registers are used for ______

a) Switching between supervisor and interrupt mode
b) Extended storing
c) Same as other general purpose registers
d) None of the mentioned

Answer: a
Explanation: When switching from one mode to another, instead of
storing the register contents somewhere else it’ll be kept in the
duplicate registers and the new values are stored in the actual
registers.

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 QUIZ

5. In the ARM, PC is implemented using ___________

a) Caches
b) Heaps
c) General purpose register
d) Stack

Answer: c) General purpose register

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COMPARE INSTRUCTIONS
• The only effect of the comparisons is to
– UPDATE THE CONDITION FLAGS. Thus no need to set S bit.
• Operations are:
– CMP operand1 - operand2, but result not written
– CMN operand1 + operand2, but result not written
– TST operand1 AND operand2, but result not written
– TEQ operand1 EOR operand2, but result not written
• Syntax:
– <Operation>{<cond>} Rn, Operand2
• Examples:
– CMP r0, r1
– TST
– TEQ 41 / 11
Shift /Rotate Instructions

LSL R1, R2, #3 ; Logical shift left by 3 bits with flag update
LSR R4, R5, #6 ; Logical shift right by 6 bits
LSL R4, R5, #6 ; Logical shift left by 6 bits
ROR R4, R5, R6 ; Rotate right by the value in the bottom byte of R6
RRX R4, R5 ; Rotate right with extend (one bit only).

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Load and Store Instructions
LDR R0, NUM ;
load R0 with the value of NUM in
memory

STR R0,[R1];
store R0 in the byte address R1

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Condition Codes

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Register usage in subroutine calls
• Branch instructions to call and return from subroutines.
• A subroutine is a block of code that performs a task based on some arguments and
optionally returns a result.
• To call subroutines, use a branch and link instruction.

Syntax: BL destination
The BL instruction:
• Places the return address in the link register.
• Sets the PC to the address of the subroutine.

• After the subroutine code has executed you can use a BX LR instruction to return.

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ADVANCED ARM FEATURES
• DSP:
Multiply –accumulate instructions (MAC) can perform a 16x16 or
32x16 MAC in one clock cycle.
• SIMD:
A single register is treated as having several smaller data elements
such as bytes.
• NEON:
It is beyond SIMD instructions to provide a new set of registers and
additional features

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ADVANCED ARM FEATURES
• Trust Zone:
It is a special monitor mode which allows the processor to enter a
source to perform operations not permitted in normal mode.
• Jazelle:
It allows direct extension of 8-bit Java byte codes, A byte code
interpreter does not need to execute java programs.
• Cortex:
Cortex A5 –Provides Jazelle execution of Java, floating point
processing and NEON multimedia instructions.
Cortex A8 – It is a dual issue in order to superscalar processor.

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ADVANCED ARM FEATURES
• Cortex A9 – It can be used in multiprocessor with upto four
processing elements.
• Cortex A15 – MP core is a multicore processor with upto four
CPUs.
• Cortex R – It is designed for real time embedding computing .It
provides SIMD operations for DSP, a hardware divider and a
memory protection unit for operating system.
• Cortex M –It is designed for microcontroller based systems that
require low cost and low energy operation.

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ARM BOARD -TUTORIAL

https://youtu.be/-02YSdNc-Aw

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 R.M.K. ENGINEERING COLLEGE
R.S.M. NAGAR, KAVARAPETTAI.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

20EC602 -Embedded Systems

TOPIC: LPC214X ARM PROCESSOR AND ITS PERIPHERALS

Presented By:
Mr. R Babuji,
Assistant Professor,
Dept. of ECE/RMKEC

50 / 11
 What is ARM?

 The ARM stands for Advanced RISC Machine and it is a 32-bit Reduced Instructions Set
Computer (RISC) microcontroller.
 It was first introduced by the Acron computers’ organization in 1987.
 ARM is the world’s leading provider of RISC based microprocessor solutions and other
semiconductor IP’s with more than 85 billion ARM based chips being shipped to date.
 ARM doesn’t manufacture processors or other semiconductor devices but rather licenses
the semiconductor cores as Intellectual Property (IP) to other semiconductor companies
like ATMEL, Phillips (now NXP), Samsung etc.

51 / 11
Three architecture profiles: A, R and M.
A-Profile (Applications) R-Profile (Real-Time) M-Profile (Microcontroller)

 Targeted at
 High
systems with
performance.  Small, highly
real-time
 Designed to run a power-efficient
requirements.
complex devices..
 Commonly found
operating system,  Found at the heart
in networking
such as Linux or of many IoT
equipment, and
Windows. devices.
embedded control
systems.

52 / 11
 ARM 7
Architecture

53 / 11
Register Organization

54 / 11
 QUIZ

1. The address system supported by ARM systems is/are

___________
a) Little Endian
b) Big Endian
c) X-Little Endian
d) Both Little & Big Endian

Answer: d) Both Little & Big Endian

55 / 11
 QUIZ

2. In the ARM, PC is implemented using ___________

a) Caches
b) Heaps
c) General purpose register
d) Stack
Answer: c
Explanation: PC is the place where the next
instruction about to be executed is stored.

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 QUIZ

3.The additional duplicate register used in ARM machines are

called as _______
a) Copied-registers
b) Banked registers
c) Extra registers
d) Extential registers
Answer: b
Explanation: The duplicate registers are used in
situations of context switching.
57 / 11
 QUIZ

4. Each instruction in ARM machines is encoded into

__________ Word.
a) 2 byte
b) 3 byte
c) 4 byte
d) 8 byte
Answer: c

58 / 11
 QUIZ
5.Which of the following has a Harvard architecture?
a) EDSAC
b) SSEM
c) PIC
d) CSIRAC
Answer: C
Explanation: PIC follows Harvard architecture in which the
external bus architecture consists of separate buses for
instruction and data whereas SSEM, EDSAC, CSIRAC are
stored program architecture.
59 / 11
ARM Instruction Set
 Instruction Set
ARM defines two separate Instruction Sets
• ARM State Instruction Set- 32 bit wide
• Thumb State Instruction Set- 16 bit wide
Features:
 All instructions are 32 bits long
 Most instructions execute in a single cycle.
 Most instructions can be conditionally executed.
 A load/store architecture
 Data processing instructions act only on registers
 Three operand format
 Instruction set extension via coprocessors
 Very dense 16 bit compressed instruction set (Thumb)
61 / 11
Types of Instructions
• Data Processing Instructions
• Branch Instructions
• Load -Store Instructions
• Software Interrupt Instructions
• Program Status Register Instructions
• Coprocessor Instructions

62 / 11
Instruction Format
Syntax:
<Operation>{<cond>}{S} Rd, Rn, Rm
cond- Indicates Flags to test.
S- Set Condition Flags in CPSR
Rd- Destination
Rn- 'Constant' or 1st Operand
Rm- Operand 2

63 / 11
Data Processing Instructions
• Largest family of ARM instructions, all sharing the same instruction
format.
• Contains:
– Arithmetic operations
– Comparisons (no results - just set condition codes)
– Logical operations
– Data movement between registers
• Remember, this is a load / store architecture
– These instruction only work on registers, NOT memory.
• They each perform a specific operation on one or two operands.
– First operand always a register - Rn
– Second operand sent to the ALU via barrel shifter.
• We will examine the barrel shifter shortly
64 / 11
Arithmetic Operations
• Operations are:
– ADD operand1 + operand2
– ADC operand1 + operand2 + carry
– SUB operand1 - operand2
– SBC operand1 - operand2 + carry -1
– RSB operand2 - operand1
– RSC operand2 - operand1 + carry - 1
• Syntax:
– <Operation>{<cond>}{S} Rd, Rn, Operand2
• Examples
– ADD r0, r1, r2
– ADD R0,R1,#2
– RSB r4, r5,r6
65 / 11
Logical Operation Instructions
• Operations are:
– AND operand1 AND operand2
– EOR operand1 EOR operand2
– ORR operand1 OR operand2
– BIC operand1 AND NOT operand2 [ie bit clear]
• Syntax:
– <Operation>{<cond>}{S} Rd, Rn, Operand2
• Examples:
– AND r0, r1, r2
– BIC r0, r1, r2

66 / 11
Move Instructions
• Operations are:
– MOV operand2
– MVN NOT operand2
Note that these make no use of operand1.
• Syntax:
– <Operation>{<cond>}{S} Rd, Operand2
• Examples:
– MOV r0, r1
– MVN
– MVN ro, r1

67 / 11
 QUIZ

1. Memory can be accessed in ARM systems by __________

instructions.
i) Store
ii) MOVE
iii) Load
iv) arithmetic
v) logical
a) i, ii, iii
b) i, ii
c) i, iv, v
d) iii, iv, v

68 / 11
 QUIZ

2. Each instruction in ARM machines is encoded into __________

Word.
a) 2 byte
b) 3 byte
c) 4 byte
d) 8 byte

69 / 11
 QUIZ

3. All instructions in ARM are conditionally executed.

a) True
b) False

70 / 11
 QUIZ

4. The banked registers are used for ______

a) Switching between supervisor and interrupt mode
b) Extended storing
c) Same as other general purpose registers
d) None of the mentioned

Answer: a
Explanation: When switching from one mode to another, instead of
storing the register contents somewhere else it’ll be kept in the
duplicate registers and the new values are stored in the actual
registers.

71 / 11
 QUIZ

5. Who coined the term RISC?

a) David Patterson
b) von Neumann
c) Michael J Flynn
d) Harvard
Answer: a
Explanation: David Patterson of Berkeley university
coined the term RISC whereas Michael J Flynn who first
views RISC.
72 / 11
COMPARE INSTRUCTIONS
• The only effect of the comparisons is to
– UPDATE THE CONDITION FLAGS. Thus no need to set S bit.
• Operations are:
– CMP operand1 - operand2, but result not written
– CMN operand1 + operand2, but result not written
– TST operand1 AND operand2, but result not written
– TEQ operand1 EOR operand2, but result not written
• Syntax:
– <Operation>{<cond>} Rn, Operand2
• Examples:
– CMP r0, r1
– TST
– TEQ 73 / 11
Shift /Rotate Instructions

LSL R1, R2, #3 ; Logical shift left by 3 bits with flag update
LSR R4, R5, #6 ; Logical shift right by 6 bits
ROR R4, R5, R6 ; Rotate right by the value in the bottom byte of R6
RRX R4, R5 ; Rotate right with extend (one bit only).

74 / 11
Load and Store Instructions
LDR R0, NUM ;
load R0 with the value of NUM in
memory

STR R0,[R1];
store R0 in the byte address R1

75 / 11
Condition Codes

76 / 11
Register usage in subroutine calls
• Branch instructions to call and return from subroutines.
• A subroutine is a block of code that performs a task based on some arguments and
optionally returns a result.
• To call subroutines, use a branch and link instruction.

Syntax: BL destination
The BL instruction:
• Places the return address in the link register.
• Sets the PC to the address of the subroutine.

• After the subroutine code has executed you can use a BX LR instruction to return.

77 / 11
 LPC 214X Family

 ARM 7 type Architecture Manufactured by NXP.

 The LPC2141/2/4/6/8 microcontrollers are based on a 32/16 bit ARM7TDMI CPU with
real-time emulation and embedded trace support, that combines the microcontroller with
embedded high speed flash memory ranging from 32 kB to 512 kB.
 Due to their tiny size and low power consumption.

 45 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make
these microcontrollers particularly suitable for industrial control and medical systems.

78 / 11
LPC214X- Features

 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

 8 to 40 kB of on-chip static RAM and 32 to 512 kB of on-chip flash program memory.
 128 bit wide interface/accelerator enables high speed 60 MHz operation.
 Single flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms.
 USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM.
 One or two (LPC2141/2 vs. LPC2144/6/8) 10-bit A/D converters provide a total of
6/14 analog inputs, with conversion times as low as 2.44 μs per channel.
 Single 10-bit D/A converter provides variable analog output.

79 / 11
Features

 Two 32-bit timers/external event counters and PWM unit (six outputs) and watchdog
timer.
 Multiple serial interfaces including two UARTs
 Two Fast I2C-bus (400 kbit/s), SPI and SSP with buffering and variable data length
capabilities.

80 / 11
Features

 Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.

 Up to nine edge or level sensitive external interrupt pins available.
 60 MHz maximum CPU clock available from programmable on-chip PLL with
settling time of 100 μs.
 On-chip integrated oscillator operates with an external crystal in range from 1 MHz to
30 MHz and with an external oscillator up to 50 MHz.
 CPU operating voltage range of 3.0 V to 3.6 V

81 / 11
LPC2148 Architecture

Interrupt sources
Every peripheral device consists of a single interrupt line allied to the VIC
(vector interrupt controller).

Vectored Interrupt Controller: All input requests are received by vectored

interrupt controller (VIC) and it converts them into fast interrupt request
(FIQ). So, fast interrupt request and non fast interrupt requests are defined
by programming setting in vectored interrupt controller.

82 / 11
Pin Connect Block

 Peripherals must be coupled with the suitable pins previous to being triggered, and
previous to any connected interrupts being permitted.
 The microcontroller functionality can be defined by the pin control module by its pin
selection of registers in a given hardware environment.
 There are 3 Pin Function Select Registers in LPC2148:

1. PINSEL0 : - PINSEL0 is used to configure PORT0 pins P0.0 to P0.15.

2. PINSEL1 : - PINSEL1 is used to configure PORT0 pins P0.16 to P0.31.

3. PINSEL2 : - PINSEL2 is used to configure PORT1 pins P1.16 to P1.31.

83 / 11
GPIO- General Purpose Parallel Input/output
LPC2148 has two 32-bit General Purpose I/O ports.
1. PORT0
2. PORT1

PORT0 is a 32-bit port

 Out of these 32 pins, 28 pins can be configured as either general purpose input or output.

 1 of these 32 pins (P0.31) can be configured as general-purpose output only.

 3 of these 32 pins (P0.24, P0.26 and P0.27) are reserved. Hence, they are not available
for use. Also, these pins are not mentioned in pin diagram.

84 / 11
PORT1 is also a 32-bit port. Only 16 of these 32 pins (P1.16 – P1.31) are available for use as
general-purpose input or output.

85 / 11
 QUIZ

1. Which of the following processors has CISC architecture?

a) AVR
b) Atmel
c) Blackfin
d) Zilog Z80

/ 11
 QUIZ

2. What is the instruction set used by ARM7?

a) 16-bit instruction set
b) 32-bit instruction set
c) 64-bit instruction set
d) 8-bit instruction set
Answer: a
Explanation: ARM introduced the Thumb 16-bit instruction set
providing improved code density compared to previous designs.
The most widely used ARM7 designs implement the ARMv4T
architecture, but some implement ARM3 or ARMv5TEJ.

87 / 11
 QUIZ

3. What is the processor used by ARM7?

a) 8-bit CISC
b) 8-bit RISC
c) 32-bit CISC
d) 32-bit RISC
Answer: d
Explanation: ARM7 is a group 32-bit RISC ARM processor cores
licensed by ARM Holdings for microcontroller use
.

88 / 11
 QUIZ
4.Princeton architecture is also known as
a) von Neumann architecture
b) Harvard
c) RISC
d) CISC
Answer: a
Explanation: The von Neumann architecture is also
known as von Neumann model or Princeton architecture.

89 / 11
 QUIZ

5. 4.The address space in ARM is ___________

a) 224
b) 264
c) 216
d) 232
Answer: d

90 / 11
Memory
• On Chip Static RAM (SRAM): This on chip static ram is used for
storing data or code. This ram could be accessed as 8 bit,16 bit or
32 bit. The memory of this ram could be increased to 8 kB,16 kB
or 32 kB by using USB.

• On Chip Flash Program Memory: LPC 2148 microcontroller

contains 512 kB on chip flash memory this memory is used for
almost data storage or code storage. The programming of this flash
memory could be accomplished with several ways.

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Digital to analog Converter:

Digital to analog Converter: This LPC 2148 microcontroller has one

10 bit digital to analog converter (DAC).This converter converts the
digital input into analog output. The maximum DAC output voltages
are called VREF voltages. Power down mode and buffered output is
also available in this digital to analog converter.

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Analog to Digital Converter:

• Analog to Digital Converter: This LPC 2148 microcontroller also contains

two analog to digital converters whose names are ADC0 and ADC1.
There are 14 total number of inputs of ADC are available and these two
converters successfully converts 10 bit analog input to digital output. The
measurement rang of each convert is 0V to VREF and global star
command is used for both converters.

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UART:

UART: This LPC 2148 microcontroller contains two UART whose name are
UART 0 and UART 1.
These UARTs are provided the full mode control handshake interface during
transmitting or receiving the data lines. These are used 16 Byte data rate
during transmitting or receiving the data.
For covering wide range of baud rate they also contain the built in functional
baud rate generator, therefore there is no need of any external crystal of
specific value.
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I2C Bus Serial I/O Controller:(Inter-Integrated Circuit)
 I2C bus serial is bidirectional multi master bus. It can easily control two or more buses which are
connected to it.
 The data which is transferred for master bus to slave bus is transferred through this bidirectional bus at
baud rate up 400 k.
 Similarly the serial clock synchronization allows the device to communicate the data of different baud
rate pass through only one serial bus.
 This clock synchronization could be used as handshake mechanism for resuming or suspending the data
transfer.

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SPI Serial I/O Control (Serial Peripheral Interface)
 This SPI serial I/O control supports the duplex
data transfer, means this control supports the
device for transferring the data whose range
4 kB to 16 kB from master bus to slave bus.
 This operation is called synchronous serial
communication operation from master but to
slave bus. This data is transmitted or received in
8 frames and each frame is contains 4 bits to 16
bits.

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Timers:

This LPC 2148 microcontroller has two

timers or counters. These timers are 32 bit
programmable with 32 bit pre scaler value as
well as it also has one external event counter.

Each timer has four 32 bit capture channels

which take the snapshot of timer value
during the transition of any input signal.
With the help of this capture event the
interruption could be also generate.

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Watch Dog Timer:

This LPC 2148 microcontroller also contains the

watch dog timer whose main purposes is to reset
the microcontroller with in specific amount of
time during erroneous state.
After this state it again turned on the
microcontroller with in specific amount of time
limit.

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Real Time Clock (RTC):
In this LPC 2148 microcontroller, the RTC is designed to set the counters for the
measuring the whole time when the controller is in operating mode or idle mode.

It has designed to consume little power which make it suitable for battery powered
systems where CPU is not continually in operating mode.

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Crystal Oscillator:
This LPC 2148 microcontroller
contains the on chip integrated
oscillator which operate with an
external crystal whose range is in
between 1 MHz to 25 MHz Its
output frequency is called focs and
controller clock frequency is called
CCLK.

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PLL

PLL: This LPC 2148 microcontroller contains two phase locked loops whose names are
PLL0 and PLL1.The input frequency whose range is in between 1 MHz to 25 MHz is
accepted by this PLL. This frequency range could be extended from 10 MHz to 60 MHz
by using the current controlled oscillator (CCO)

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ARM BOARD PERIPHERALS -VIDEO

https://youtu.be/wMdLTpyFUYo

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 LPC2148
Peripherals

LPC2148-Timer Unit

23/07/2020
LPC214x Timer
 Timer/Counter0 and Timer/Counter1 are functionally identical except for the peripheral base
address.
 A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
- Counter or Timer operation
- Up to four 32-bit capture channels per timer,
 Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
 Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set low on match.
– Set high on match.
– Toggle on match.
– Do nothing on match. 104 / 11
Applications

• Interval Timer for counting internal events.

• Pulse Width Demodulator via Capture inputs.
• Free running timer.

The Timer/Counter is designed to count cycles of the peripheral clock

(PCLK) or an externally-supplied clock, and can optionally generate
interrupts or perform other actions at specified timer values, based on four
match registers.

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Add title here

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TIMER/COUNTER0 and TIMER/COUNTER1 register map
Generic Description
Name
IR Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify
which of eight possible interrupt sources are pending.
TCR Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer
Counter can be disabled or reset through the TCR
TC Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled
through the TCR.
PR Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments
the TC and clears the PC.
PC Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR.
When the value in PR is reached, the TC is incremented and
the PC is cleared. The PC is observable and controllable through the bus interface.
MCR Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is
reset when a Match occurs.

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TIMER/COUNTER0 and TIMER/COUNTER1 register map
Generic Description
Name
MR0 - The Match register values are continuously compared to the Timer Counter
MR3 value. When the two values are equal, actions can be triggered automatically.
The action possibilities are to generate an interrupt, reset the Timer Counter, or
stop the timer. Actions are controlled by the settings in the MCR register.
CR0 - Each Capture register is associated with a device pin and may be loaded with
CR3 the Timer Counter value when a specified event occurs on that pin. The settings
in the Capture Control Register register determine whether the capture function
is enabled, and whether a capture event happens on the rising edge of the
associated pin, the falling edge, or on both edges.
CCR Capture Control Register. The CCR controls which edges of the capture inputs
are used to load the Capture Registers and whether or not an interrupt is
generated when a capture takes place.

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UART
Basics of UART

 The UART Protocol uses only two wires (or pins in a device like microcontroller) to
transmit the data. In that, one is for transmitting the data and the pin is called TX pin
in the device. The other pin is used to receive the data and is called RX pin.
 UART is a serial communication, the data is transmitted in a series of packets.
Usually, a packet consists of 4 parts: a start bit, the actual data, a parity bit and stop
bits. The following image shows a typical structure of the data packet in UART.

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Basics of UART

 Coming to UART in LPC2148, the LPC214x series of MCUs have two UART blocks
called UART0 and UART1. Each UART block is associated with two pins, one for
transmission and the other for receiving.

 In UART0 block, the TXD0 (Transmit) and RXD0 (Receive) pins in the device are
P0.0 and P0.1 respectively. In case of UART1, the TXD1 and RXD1 pins are P0.8 and
P0.9 respectively.

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UART Basic Packet

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Registers associated with UART in LPC2148
Generic Description
Name

U0RBR UART0 Receiver Buffer Register-The UART0 Receiver Buffer Register

contains the oldest received byte in the UART0 Rx FIFO.
U0THR UART0 Transmit Holding Register-Writing to the UART0 Transmit Holding
Register causes the data to be stored in the UART0 transmit FIFO. The byte
will be sent when it reaches the bottom of the FIFO and the transmitter is
available.
U0DLL& UART0 Divisor Latch Registers- The UART0 Divisor Latch LSB Register,
U0DLM along with the U0DLM egister, determines the baud rate of the UART0.
The UART0 Divisor Latch MSB Register, along with the U0DLL register,
determines the baud rate of the UART0.

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Registers associated with UART in LPC2148
Generic Description
Name

U0FDR UART0 Fractional Divider Register-The Fractional Divider Register contains

the bits that control the prescale for the baud rate generator. U0FDR contains
the divisor and multiplier values for prescaling. Both the divisor
(DIVADDVAL) and multiplier (MULVAL) values are stored as 4 – bit values.
U0IER UART0 Interrupt Enable Register-The Interrupt Enable Register is used to
enable or disable the interrupts corresponding to UART0.
U0IIR UART0 Interrupt Identification Register-The Interrupt Identification Register
is used to provide the code for priority and status of the pending interrupt.

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U0LCR ( Line Control Register )

Bit 1:0 – WLS : WordLenghtSelect

Bit 2 – Stop Bit Selection:
Bit 3 – Parity Enable:
Bit 5:4 – Parity Selection:
Bit 6 – Break Control
Bit 8 – DLAB: Divisor Latch Access Bit

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UxLSR (Line Status Register)

Bit 0 – RDR: Receive Data Ready-This bit will be set when there is a received data in RBR register. This bit will be
automatically cleared when RBR is empty.
Bit 1 – OE: Overrun Error-The overrun error condition is set when the UART Rx FIFO is full and a new character is
received. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.
Bit 2 – PE: Parity Error-This bit is set when the receiver detects a error in the Parity.
Bit 3 – FE: Framing Error-This bit is set when there is error in the STOP bit(LOGIC 0)
Bit 4 – BI: Break Interrupt
Bit 5 – THRE: Transmitter Holding Register Empty-THRE is set immediately upon detection of an empty THR. It is
automatically cleared when the THR is written.
Bit 6 – TEMT: Transmitter Empty-TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when any
of them contain valid data.
Bit 7 – RXFE: Error in Rx FIFO-This bit is set when the received data is affected by Framing Error/Parity Error/Break
Error.

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Baud Rate Generation in UART
The following rules must be followed for the Baud rate generation.

Minimum value for MULVAL must be 1 i.e. 0 < MULVAL <= 15.
The value for DIVADDVAL can be between 0 and 15 with both the extremes included
i.e.
0 <= DIVADDVAL <= 15.

Baudrate= PCLK/ (16 * ( 256 * DLM + DLL) * (1+ DivAddVal/MulVal))

U0DLM = 1,U0DLL = 110,DIVADDVAL = 1,MULVAL = 15,PCLK=60MHz
Approximately =9600

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 R.M.K. ENGINEERING COLLEGE
R.S.M. NAGAR, KAVARAPETTAI.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

20EC602 -Embedded Systems

TOPIC: ARM PERIPHERALS – UART & PWM

Presented By:
Mr. R Babuji,
Assistant Professor,
Dept. of ECE/RMKEC

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 RECAP OF PREVIOUS SESSIONS

 ARM version
 ARM Architecture
 Features of ARM
 Instruction set of ARM processor
 PIN diagram of LPC 2148
 ARM peripherals –Timer Logic

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QUESTIONS:
1. List out the features of ARM processors.
ARM processor features include:
Load/store architecture.
An orthogonal instruction set.
Mostly single-cycle execution.
Enhanced power-saving design.
64 and 32-bit execution states for scalable high performance.

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2. Define 2 types of Endians
Both little-endian and big-endian memory addressing. The
ARM processor can be configured at power-up to address the bytes
in a word in either little-endian mode (with the lowest-order byte
residing in the lowest storage address) or Big-endian mode (with
the lowest-order byte residing in the highest storage address).

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3. What is subroutine?
Large programs are hard to handle and so broken into smaller
programs called as subroutines.

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UART
UART
• UART (Universal Asynchronous Receiver/Transmitter) is a serial communication protocol in which data
is transferred serially bit by bit at a time. Asynchronous serial communication is widely used for byte-
oriented transmission. In Asynchronous serial communication, a byte of data is transferred at a time.

• UART serial communication protocol uses a defined frame structure for their data bytes. Frame
structure in Asynchronous communication consists:

 START bit: It is a bit with which indicates that serial communication has started and it is
always low.

 Data bits packet: Data bits can be packets of 5 to 9 bits. Normally we use 8- bit data
packet, which is always sent after the START bit.

 STOP bit: This usually is one or two bits in length. It is sent after data bits packet to
indicate the end of frame. Stop bit is always logic high.

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Basics of UART

 Coming to UART in LPC2148, the LPC214x series of MCUs have two UART blocks
called UART0 and UART1. Each UART block is associated with two pins, one for
transmission and the other for receiving.
 In UART0 block, the TXD0 (Transmit) and RXD0 (Receive) pins in the device are
P0.0 and P0.1 respectively. In case of UART1, the TXD1 and RXD1 pins are P0.8 and
P0.9 respectively.

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FEATURES OF UART0

 16 byte Receive and Transmit FIFOs

 Built-in fractional baud rate generator with autobauding capabilities

 Software flow control through TXEN bit in Transmit Enable Register

FEATURES OF UART1

 16 byte Receive and Transmit FIFOs

 Built-in fractional baud rate generator with autobauding capabilities

 Software and hardware flow control implementation possible

 Standard modem interface signals included with flow control (auto-CTS/RTS) fully supported in hardware

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LPC2148 UART PINS
•LPC2148 has 2 pins for UART0 and 8 pins for UART1.

UART0:

1. TXD0 (Output pin): Serial Transmit data pin.

2. RXD0 (Input pin): Serial Receive data pin.

UART1:

3. TXD1 (Output pin): Serial Transmit data pin.

4. RXD1 (Input pin): Serial Receive data pin.
5. RTS1 (Output pin): Request To Send signal pin. Active low signal indicates that the UART1 would like to transmit
data to the external modem.
6. CTS1 (Input pin): Clear To Send signal pin. Active low signal indicates if the external modem is ready to accept
transmitted data via TXD1 from the UART1.

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5. DSR1 (Input pin): Data Set Ready signal pin. Active low signal indicates if
the external modem is ready to establish a communication link with the UART1.
6. DTR1 (Output pin): Data Terminal Ready signal pin. Active low signal
indicates that the UART1 is ready to establish connection with external modem.
7. DCD1 (Input pin): Data Carrier Detect signal pin. Active low signal indicates
if the external modem has established a communication link with the UART1 and
data may be exchanged.
8. RI1 (Input pin): Ring Indicator signal pin. Active low signal indicates that a
telephone ringing signal has been detected by the modem.

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Registers associated with UART in LPC2148
Generic Description
Name

U0RBR UART0 Receiver Buffer Register-The UART0 Receiver Buffer Register

contains the oldest received byte in the UART0 Rx FIFO.
U0THR UART0 Transmit Holding Register-Writing to the UART0 Transmit Holding
Register causes the data to be stored in the UART0 transmit FIFO. The byte
will be sent when it reaches the bottom of the FIFO and the transmitter is
available.
U0DLL& UART0 Divisor Latch Registers- The UART0 Divisor Latch LSB Register,
U0DLM along with the U0DLM register, determines the baud rate of the UART0.
The UART0 Divisor Latch MSB Register, along with the U0DLL register,
determines the baud rate of the UART0.

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Registers associated with UART in LPC2148
Generic Description
Name

U0FDR UART0 Fractional Divider Register-The Fractional Divider Register contains

the bits that control the prescale for the baud rate generator. U0FDR contains
the divisor and multiplier values for prescaling. Both the divisor
(DIVADDVAL) and multiplier (MULVAL) values are stored as 4 – bit values.
U0IER UART0 Interrupt Enable Register-The Interrupt Enable Register is used to
enable or disable the interrupts corresponding to UART0.
U0IIR UART0 Interrupt Identification Register-The Interrupt Identification Register
is used to provide the code for priority and status of the pending interrupt.

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U0LCR ( Line Control Register )

Bit 1:0 – WLS : WordLenghtSelect

Bit 2 – Stop Bit Selection:
Bit 3 – Parity Enable:
Bit 5:4 – Parity Selection:
Bit 6 – Break Control
Bit 8 – DLAB: Divisor Latch Access Bit

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UxLSR (Line Status Register)

Bit 0 – RDR: Receive Data Ready-This bit will be set when there is a received data in RBR register. This bit will be
automatically cleared when RBR is empty.
Bit 1 – OE: Overrun Error-The overrun error condition is set when the UART Rx FIFO is full and a new character is
received. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.
Bit 2 – PE: Parity Error-This bit is set when the receiver detects a error in the Parity.
Bit 3 – FE: Framing Error-This bit is set when there is error in the STOP bit(LOGIC 0)
Bit 4 – BI: Break Interrupt
Bit 5 – THRE: Transmitter Holding Register Empty-THRE is set immediately upon detection of an empty THR. It is
automatically cleared when the THR is written.
Bit 6 – TEMT: Transmitter Empty-TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when any
of them contain valid data.
Bit 7 – RXFE: Error in Rx FIFO-This bit is set when the received data is affected by Framing Error/Parity Error/Break
Error.

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 QUIZ

1. Which of the following offers external chips for memory and

peripheral interface circuits?
a) Microcontroller
b) Microprocessor
c) Peripheral system
d) Embedded system

Ans: b) Microprocessor

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2. A …………. is a way of working, organizing or doing one or many tasks
according to a fixed plan, program or set of rules.
a) Microcontroller
b) System
c) Embedded System
d) Embedded Processor.

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3. Which one of the following is board based system?
a) Data bus
b) Address bus
c) VMEbus
d) DMA bus

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4. What are the major goals of embedded system design?
a) Performance, cost , and Reliability
b)Requirements, Specification and Design
c) Hardware , Software and System Integration

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5. A logic analyzer records data in either of two modes they
are…………...
a)State and running
b)State and timing
c)Standard and timing
d)Standard time mode.

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PULSE WIDTH MODULATION

• Pulse Width Modulation (PWM) is a technique by which width of a

pulse is varied while keeping the frequency constant.

• A period of a pulse consists of an ON cycle (HIGH) and an OFF

cycle (LOW). The fraction for which the signal is ON over a period
is known as duty cycle.

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• Through PWM technique, we can control the power delivered to the load by using ON- OFF

signal.

• LPC2148 has PWM peripheral through which we can generate multiple PWM signals on PWM

pins. Also, LPC2148 supports two types of controlled PWM outputs as,
• Single Edge Controlled PWM: All the rising (positive going) edges of the output waveform

are positioned/fixed at the beginning of the PWM period. Only falling (negative going) edge

position can be controlled to vary the pulse width of PWM.

• Double Edge Controlled PWM: All the rising (positive going) and falling (negative going)

edge positions can be controlled to vary the pulse width of PWM. Both the rising as well as the

falling edges can be positioned anywhere in the PWM period.

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PWM Signal with different duty cycle

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THE VARIOUS PWM REGISTERS THAT ARE USEFUL IN CONTROLLING AND GENERATING PWM.

1. PWMIR (PWM Interrupt Register)

 It is a 16-bit register.

 It has 7 interrupt bits corresponding to the 7 PWM match registers.

 If an interrupt is generated, then the corresponding bit in this register becomes HIGH.
Otherwise the bit will be LOW.

 Writing a 1 to a bit in this register clears that interrupt.

 Writing a 0 has no effect.

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2. PWMTCR (PWM Timer Control Register)
 It is an 8-bit register.

 It is used to control the operation of the PWM Timer Counter.

3. PWMTC (PWM Timer Counter)

 It is a 32-bit register.

 It is incremented when the PWM Prescale Counter (PWMPC) reaches its terminal count.

4.PWMPR (PWM Prescale Register)

 It is a 32-bit register.

 It holds the maximum value of the Prescale Counter.

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5. PWMPC (PWM Prescale Counter)
 It is a 32-bit register.

 It controls the division of PCLK by some constant value before it is applied to the PWM
Timer Counter.It is incremented on every PCLK.

 When it reaches the value in PWM Prescale Register, the PWM Timer Counter is
incremented and PWM Prescale Counter is reset on next PCLK.
6. PWMMR0-PWMMR6 (PWM Match Registers)
 These are 32-bit registers.

 The values stored in these registers are continuously compared with the PWM Timer Counter
value.When the two values are equal, the timer can be reset or stop or an interrupt may be
generated.
 The PWMMCR controls what action should be taken on a match.

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7. PWMMCR (PWM Match Control Register)

 It is a 32-bit register.

 It controls what action is to be taken on a match between the PWM Match Registers and PWM Timer
Counter.
8. PWMPCR (PWM Control Register)

 It is a 16-bit register.
 It is used to enable and select each type of PWM.

9. PWMLER (PWM Latch Enable Register)

 It is an 8-bit register.

 It is used to control the update of the PWM Match Registers when they are used for PWM generation.

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 ARM 9 PROCESSOR

• This family enables single processor solution for microcontroller,

DSP applications, offering savings in chip area & complexity,
power consumption & time to market.
• ARM9 – enhanced processors are well suited for applications
requiring a mix of DSP+ Microcontroller performance

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 FEATURES OF ARM9

 Pipeline Depth: 5 stage (Fetch, Decode, Execute, Decode, Write)

 Operating frequency: 150 MHz

 Power Consumption: 0.19 mW/MHz

 MIPS/MHz: 1.1
 Architecture used: Harvard
 MMU/MPU: Present
 Cache Memory: Present (separate 16k/8k)
 ARM/ Thumb Instruction: Support both
 ISA (Instruction Set Architecture): V5T(ARM926EJ-S)
 31 (32-Bit size) Registers
 32-bit ALU & Barrel Shifter
 Enhanced 32- bit MAC block

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Applications of ARM9

1. Consumer type: Smart phones, PDA, Set-Top box, Electronics Toys,

Digital Cameras, etc.
2. Networking type: Wireless LAN, 802.11, Bluetooth, etc.
3. Automatic: Power Train, ABS, Navigation, etc.
4. Embedded USB controllers, Bluetooth controllers, Medical scanners,
etc.
5. Storage: HDD controllers, solid state drivers etc.

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ARM 9 Architecture diagram

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Thank You..