Embedded Processors

ARM-based processor

What is ARM(Advanced Risc Machines)?

 ARM : Advanced Risc Machines Ltd.

 ARM is an UK company that designs innovative 32-bit

microprocessors, Cambridge, England (www.arm.com)

 Founded in November 1990 (Acorn Computers) UK

 Designs the ARM range of RISC processor cores

 Licenses ARM core designs to semiconductor partners who fabricate
and sell to their customers.
 ARM does not fabricate silicon itself

 Also develop technologies to assist with the

design-in of the ARM architecture
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 Software tools, boards, debug hardware,

Why use an ARM-based processor?

Sales in billions of dollars

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ARM Partnership Model

ARM Powered Products

ARM Processor Names

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 Architecture Versions
 A Profile (ARMv7-A): Application processors required to run complex
applications such as high-end embedded operating systems (OSs), such
as Symbian, Linux, and Windows Embedded, (virtual memory ,MMUs),
enhanced Java support and a secure program execution environment.
Example products highend mobile phones.

• R Profile (ARMv7-R): Real-time, high-performance processors

targeted hard drive controllers, in which high processing power and
high reliability are essential and for which low latency is important.

• M Profile (ARMv7-M): Processors targeting low-cost applications in

which processing efficiency is important and cost, power consumption,
low interrupt latency,
and ease of use are critical, as well as industrial control applications,
including realtime control systems.

The Evolution of ARM Processor Architecture

e.g. Cortex M3

More Than 28 company

ST, NXP, Atmel, Samsung…
Cortex-A Series, applications processors for complex OS and user applications.
Cortex-R Series, real-time systems profile.
Cortex-M Series, microcontroller profile optimized for cost-sensitive applications..
The number at the end of the Cortex name refers to the relative performance
level, with 1 the lowest and 8 the highest.
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Differences between a processor and a

microcontroller

ARM designs processors

and various components
and licenses these
designs to various silicon
( ex : microcontroller
vendors … )

A microcontroller contains
many different blocks

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Introduction to ARM Cortex-M Processors
ARM and the microcontroller vendors
 After a company licenses the Cortex-M processor design, ARM
provides the design source code of the processor in Verilog-HDL.

 The design engineers in these companies then add their

own design blocks like peripherals and memories,

 ARM also provides other (IP) products, and some can be used by
these companies in their microcontroller products .
 Additional debug components for linking debug systems in multi-
processor design (ARM CoreSight IP products)
 Cortex-M System Design Kit (CMSDK), a design kit for Cortex-M
processor.
 This allows chip designers to start using the Cortex-M processors
quickly and reduces the total chip development effort with
reusable IP.
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Introduction to ARM Cortex-M Processors

Advantages of the Cortex -M processors

 Low power Performance : 1.25 DMIPS/ MHz (
 Energy efficiency :excellent energy efficiency
 Code density : need a smaller program size
 Interrupts : up to 240 vectored interrupts
 Ease of use, C friendly
 Scalability :
 Debug features
 OS support : Versatile system features
 Software portability and reusability

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Introduction to ARM Cortex-M Processors

Applications of the ARM Cortex-M processors
 With their wide range of powerful features, the ARM Cortex-M3 and
Cortex-M4 processors are ideal for a wide variety of applications:
 Microcontrollers
 Automotive
 Data communications
 Industrial control
 Consumer products
 Systems-on-Chips (SoC )
 Mixed signal designs

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About the ARM ecosystem
ARM is working with
 silicon vendors,
 ARM solutions devlopper
 ARM products userd.
 design services providers,
 distributors, training providers, academic researchers

 This close collaboration allows these parties to provide high-quality

products or services, and allows more users to benefit from using the
ARM architecture

 ARM also has a University Program that enables academic

organizations like universities to access ARM technologies such as
processor IP, reference materials,and so on.
(http://www.arm.com/support/university/).

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About the ARM ecosystem

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Chapitre 3 : Technical Overview

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General information about the Cortex-M3
andCortex-M4 processors
 Block diagram of the Cortex-M3 and Cortex-M4 processor

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General information about the Cortex-M3

andCortex-M4 processors
 The top level of the Cortex-M3 and Cortex-M4 processors has a number of
bus interfaces

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Programmer’s model : Registers

Registers
 Most of the C-M3-M4 registers are grouped in a unit called the register
bank

Load-store architecture
if data in memory is to be
processed,
 it has to be loaded from the
memory to registers in the
register bank,
 processed inside the
processor,
 and then written back to the
memory, if needed.

Registers in the register bank 18

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Programmer’s model : Registers
 R0 e R12 :R0 to R12 are general purpose registers.
 (R0 e R7) are also called low registers. Due to the limited available space in
the instruction set, many 16-bit instructions can only access the low
registers.
 The high registers (R8 e R12) can be used with 32-bit instructions, and a
few with 16-bit instructions, like MOV (move).
 The initial values of R0 to R12 are undefined.
 R13, stack pointer (SP) : the stack via PUSH and POP operations.
 Physically there are two different Stack Pointers:
 the Main Stack Pointer (default) ,It is selected after reset, or when the
processor is in Handler Mode.
 The other Stack Pointer is called the Process Stack Pointer (PSP, or
SP_process in some ARM docThe PSP can only be used in Thread Mode.
 The selection of SP is determined by a special register called CONTROL
 Both MSP and PSP are 32-bit, but the lowest two bits of the Stack
Pointers (either MSP or PSP) are always zero, and writes to these two
bits are ignored 19

Programmer’s model : Registers

 R14, link register (LR):used for holding the return address when
calling a function or subroutine
 R15 is the Program Counter (PC). It is readable and writeable: a
read returns the current instruction address plus 4 (this is due to the
pipeline nature of the design, and compatibility requirement with the
ARM7TDMI processor).
 Writing to PC (e.g., using data transfer/processing instructions) causes a
branch operation.

In some assembly tools, such as the ARM assembly you can use either
uppercase, or lowercase,or mixed cases (Table).
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Programmer’s model : Registers

-- Special registers
 These registers contain the processor status and define the operation
states and interrupt/exception masking
 Special registers are not memory mapped, and can be accessed using
special register access instructions such as MSR and MRS.
 MRS <reg>, <special_reg> ; Read special register into register
 MSR <special_reg>, <reg> ; write to
special register

-- Special registers : Program status registers

The Program Status Register is
composed of three status registers:
 • Application PSR (APSR)
 • Execution PSR (EPSR)
 • Interrupt PSR (IPSR)
Special Registers
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Programmer’s model : Registers

APSR, IPSR, and EPSR

Combined xPSR

when accessing xPSR the symbol PSR is used, For example:

MRS r0, PSR ; Read the combined program status word
MSR PSR, r0 ; Write combined program state word

Individual PSR can also be accessed For example:

MRS r0, APSR ; Read Flag state into R0
MRS r0, IPSR ; Read Exception/Interrupt state
MSR APSR, r0 ; Write Flag state
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Programmer’s model : Registers

Bit Fields in : Program Status Registers ( PSR )

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CONTROL register
The CONTROL register defines:
 • The selection of stack pointer (Main Stack Point/Process Stack Pointer)
 • Access level in Thread mode (Privileged/Unprivileged)
The CONTROL register can only be modified in the privileged access level and
can be read in both privileged and unprivileged access levels. The definition of
eachbit field in the CONTROL register is shown in Table After reset, the
CONTROL register is 0. This means the Thread mode uses the Main Stack
Pointer as Stack Pointer and Thread mode has privileged accesses A program
in unprivileged access level cannot switch itself back to privileged access level.
This is essential in order to provide a basic security usage model.

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Bit Fields in CONTROL Register
Bit Function
nPRIV (bit 0) Defines the privileged level in Thread mode:
When 0 (default), it is privileged level when in Thread mode.
When 1, it is unprivileged when in Thread mode.
SPSEL (bit 1) Defines the Stack Pointer selection:
When 0 (default), Thread mode uses Main Stack Pointer (MSP).
When 1, Thread mode uses Process Stack Pointer (PSP).
FPCA (bit 2) Floating Point Context Active – (available in Cortex-M4)
- uses this bit to determine if registers in the floating point unit need
to be saved when an exception has occurred.
- When 0 (default), the FPU has not been used in the current context
and therefore no need to save floating point registers.
- When 1, the current context has used floating point
instructions and therefore need to save floating point registers.
The FPCA bit is set automatically when a floating point instruction is
executed. This bit is clear by hardware on exception entry.
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 Stack Pointer selection

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