Murali Krishna

Agate Drive, #11, San Jose, CA 95131

(408)444-9439
mkkrishna283@gmail.com

Seeking senior level assignments in pre-silicon front-end design/verification area with a growth
oriented organisation

PROFESSIONAL SYNOPSIS

 Over 12+ Years of industry Experience in ASIC & FPGA Verification.

 Experience in ASIC/FPGA Modeling and Verification.
 Area of expertise includes Test Plan creation, Test bench Architecture, Test Environment Development, BFM
Development, Testing, Coverage Driven verification, Assertions, Regression Maintatenance, Functional and code
Coverage Analysis.
 Has knowledge of System Verilog, Verilog, VHDL, has used various EDA tools like Modelsim, Cadence NC-Verilog,
and Xilinx ISE

TECHNICAL SKILLS

 Languages : Verilog, System Verilog, VHDL, System C, Exposure to C++, UVM, and Perl
 Tools : Mentor Graphics ModelSim, Quartus, Cadence NC-Verilog, Xilinx ISE and functional & code coverage tools
 Protocols : XHCI – USB 3.0, EHCI/OHCI – USB 2.0 , AMBA – AHB, PCI, PCIe, SAS, I2C and SPI
 Scripting : Shell and TCL

RELEVANT PROJECTS

1. xHCI – USB3.0 (eXtensible Host Controller Interface)

Environment: System verilog, Cadence, Modelsim
Role:
 Responsible for creating the xHCI Host controller verification Environment

 Class based Bfm and scoreboard support

 Test Environment Specification creation

 Third party BFM Integration

 Coding of test cases and debugging.

 Analysis of results and fixing the environment bugs.

 Code Coverage

Description: The eXtensible Host Controller contains 2 ports. Each port supporting USB3.0 supper speed, USb2.0 High speed,
Full speed and Low speed. Under this port we can connect Device or HUB.
User interface side contains AHB Master/Slave. AHB Master is used to Read and write the Register space.
AHB Slave is used to read the data from the Memory OUT location and command/Transfer ring TRB. AHB Slave is used to write
the data to Memory IN location and writing the completion event.

2. EDK based verification and SW validation

Environment: VHDL, Xilinx XPS

Role:
 Responsible for creating the AMC420 card verification Environment

 Test Environment Specification creation

 Coding of test cases using BFL and debugging

 Analysis of results and fixing the environment bugs.

 Code Coverage

Description: AMC 420 card contains Micro blaze, UART, I2C, Bram controller, NOR, DDRII, DDRIII, Arrora, PCI-express and
Ethernet. All the peripheral connected via PLB bus. In the Block level verification we are using PLB Master BFM instead of
Micro blaze. BFL is used to initiate the Read/Write Transaction from PLB Master BFM to Slave.

3. Verification of STS-1 SONET switch on a 48 port OC-48 platform

Environment: VHDL, Cadence

Role:
 Responsible for creating the MCM module verification Environment

 Test Environment Specification creation

 Coding of test cases and debugging.

 Analysis of results and fixing the environment bugs.

 Code Coverage

Description: Overhead bytes Insertion & Extraction. Alarm Insertion/Extraction. A1/B1 Alignment Check. Bit/2Bit/4Bit/Byte
switching Modes of operation Check.

4. ARM SOC Designer for architectural evaluation and SW validation

Environment: System C, ARM SOC Designer tool

Role:
 Responsible for creating System C based SPI. GPIO, PCI, PLL, and Timer behavioral model

 Integrate the Above model into ARM SOC designer

Description: ARM SOC Designer tool is used to develop the behavioral level peripherals and integrate that into ARM SOC
based environment. Based on this virtual verification Environment we can evaluate our Software testcases before getting the
validation board
5. Verification of Generic Framing Procedure(GFP)

Environment: System verilog, Cadence

Role:

 Test Environment Specification & Acceptance Test Specification creation

 Testbench creation

 Responsible for creating the GFP verification Environment

 Coding of test cases and debugging.

 Analysis of results and fixing the environment bugs.

 Code Coverage

Description: GFP is a multiplexing technique defined by ITU-T G.7041.GFP allows mapping of variable length, higher-layer
client signals over a transport network like SDH/SONET. The client signals can be protocol data unit (PDU) oriented (like IP/PPP
or Ethernet Media Access Control) or can be block-code oriented (like fiber channel)

6. DDR2 Controller verification with AMBA-AHB

Environment: Verilog, modelsim

Role:
 Features Extraction.

 Test plan preparation.

 Coding of test cases for all the combinations.

 Regression Failure Analysis and maintaining regressions.

 Code Coverage Analysis

 DDR2 Verification Environment

Description: The AMBA protocol is an open standard, on-chip bus specification that details a strategy for the interconnection
and management of functional blocks that makes up a System-on-Chip (SoC).
AHB Master BFM sends and receives data to/from DUT block to check the functionality. The AHB slave model emulates an AHB
peripheral device connected to the AHB bus, this model is capable of responding to any transaction initiated by the AHB master
within the DUT. Here the WRAPPER (RTL) is act as a slave. The wrapper contains the DDR2 controller (RTL), it initiates the
memory, gives data to memory to write and get the read data from memory.

7. Verification of PCIE to CSB and CSB to PCIE Interface

Environment: System verilog, Cadence

Role:
  Test Environment Specification & Acceptance Test Specification creation

 Testbench creation

 Responsible for creating verification Environment

 Coding of test cases and debugging.

 Analysis of results and fixing the environment bugs.

 Code Coverage

Description: PCIE to CSB Bridge contains PCI-Express EP controller and AXI Slave. This Bridge is used to convert the PCI-
Express transaction to coherent system Bus. CSB to PCIE Bridge contains PCI-Express EP controller and AXI Master. This
Bridge is used to convert the coherent system bus to PCI-Express transaction.

8. Verification of AES Encryption & Decryption

Environment: System verilog, Cadence

Role:

 Test Environment Specification & Acceptance Test Specification creation

 Testbench creation
 Responsible for creating verification Environment
 Coding of test cases and debugging.
 Analysis of results and fixing the environment bugs.
 Code Coverage

Description: Advanced Encryption Standard is a symmetric-key encryption standard. AES has a fixed block size of 128 bits
and a key size of 128,192 and 256 bits.

9. VLSI Trainer Board / Development Board

Environment: Altera Cyclone III FPGA, Orcad

Role:

 Schematic Design
 CPLD Selection
 Testing the Trainer / Board.

Description: Trainer board contains On Board Oscillator @ 25 MHz, programmable clock facility, 68 user I/O pins, 8 LED’s
interface, 16x2 LCD Display with backlight, AT-PS/2 Keyboard connector support, 8-SPDT switches and RS232X Standard serial
port Interface.

Education:

Master Degree in Electrical &Computer Engineering, Wayne State College, Wayne, NE 2006

Visa Status: US Citizen