library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Asyn_counter is
Port ( clk : in STD_LOGIC;
clr : in STD_LOGIC;
pr : in STD_LOGIC;
mode : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (2 downto 0);
qbar : inout STD_LOGIC_VECTOR (2 downto 0));
end Asyn_counter;

architecture Behavioral of Asyn_counter is

component tff is
port(t,clr,pr,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end component;

component testand is
port(a,b : in STD_LOGIC;
c : out STD_LOGIC);
end component;

component testor is
port(x,y : in STD_LOGIC;
z : out STD_LOGIC);
end component;

component testinv is
port(s : in STD_LOGIC;
t : out STD_LOGIC);
end component;

signal l,k,out1,out2,out3,out4,out5,modebar : STD_LOGIC;

begin

i1 : testinv port map (mode,modebar);

a1 : tff port map ('1',clr,pr,clk,q(0),qbar(0));

ad1 : testand port map(mode,q(0),out1);
ad2 : testand port map(modebar,qbar(0),out2);
or1 : testor port map(out1,out2,k);

a2 : tff port map ('1',clr,pr,k ,q(1),qbar(1));

ad3 : testand port map(mode,q(1),out3);
ad4 : testand port map(modebar,qbar(1),out4);
or21 : testor port map(out3,out4,l);

a3 : tff port map ('1',clr,pr,l,q(2),qbar(2));

end Behavioral;
**************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tff is
Port ( t : in STD_LOGIC;
clr : in STD_LOGIC;
pr : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC;
qb : out STD_LOGIC);
end tff;

architecture Behavioral of tff is

begin
process (clk)
variable x : STD_LOGIC := '0';
begin
if(clk'event and clk='1') then
if clr ='1' then
x:='0';
elsif pr='1' then
x:='1';
elsif t='1' then
x:= not x;
else
x:=x;
end if;
end if;
q<=x;
qb<= not x;

end process;

end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity testand is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end testand;

architecture Behavioral of testand is

begin
c<=a and b;

end Behavioral;

**************************************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity testor is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end testor;

architecture Behavioral of testor is

begin

z<=x or y;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity testinv is
Port ( s : in STD_LOGIC;
t : out STD_LOGIC);
end testinv;

architecture Behavioral of testinv is

begin

t<= not s;
end Behavioral;