LAYOUT BIBLE

Preliminary Draft

Version - 1.0

August 2000
DATE BY VERSION DRAFT
18.08.2k PRIYA MENDHIRTTA v1.0 first

LIPPIKA PARWANI

SWATI KOCCHAR

RAJESH JAIN
Table 1:

SUGGESTIONS ARE WELCOME TO ANY OF THE ABOVE

PERSONS
 PREFACE

The book is an attempt to collect all the technical information

regarding the layouts. The book covers all the problems associated
with layouts , like Electromigration Antenna effect, Latch -up etc.

The book also contains all the Do’s and Don’ts while making Layouts
in order to avoid undesirable results, which can prove fatal, as they
say “Precaution is better than cure.”

Index- 3
 TOPIC OF CONTENTS

PREFACE

SECTION1

A GENERAL REVIEW OF “LAYOUTS”

CHAPTER 1
INTRODUCTION
TECHNOLOGY DEVELOPMENT
LAYERS

SECTION 2

PHYSICAL ASPECTS OF”LAYOUTS”

CHAPTER1
“ELECTRMIGRATION “
DEFINITION
HISTORY
CAUSES
MATERIAL SCIENCE
DESIGNER’S POINT OF VIEW

CHAPTER 2
“ANTENNA EFFECT”
DEFINITION
HISTORY
CAUSES
MATERIAL SCIENCE
DESIGNER’S POINT OF VIEW

Index- 4
CHAPTER 3
“LATCH - UP”
DEFINITION
CAUSES
HISTORY
MATERIAL SCIENCE
PRECAUTIONS AND REMOVAL

CHAPTER 4

“BIRD’S BEAK”

CHAPTER 5

“BODY EFFECT”

CHAPTER 6

“DRAIN PUNCHTHROUGH”

CHAPTER7
“POWER SUPPLY”
DEFINITION
CAUSES
METHODS TO REMOVE
 CHAPTER 8

“YIELD”
DEFINITION
CAUSES
METHODS TO REMOVE

CHAPTER 9
“NOISE”
DEFINITION
CAUSES
METHODS TO REMOVE

SECTION 3

“ELECTRICAL ASPECTS”

CHAPTER1

RESISTANCE

CHAPTER2
CAPACITANCE

SECTION4
“LAYOUT CHALLENGES”
1.0 INTRODUCTION

SEMICONDUCTOR INDUSTRY ASSOCIATION (SIA) proclaimed that in

1995 world chip revenues increased by 41.7% and for the past 5 years
the growth had been exponential, by the year 1999 chip sales was
$234.5 billion, the largest portion of total world wide sales is domi-
nated by the MOS market.

CHIP SIZES ON A 150mm WAFER

MEMORY
CHIPS
4 M@ 0.8 um
284

184 4 M@ 0.8 um

116 16 M@ 0.5 um

70
64 M@ 0.35 um

38
256 M@ 0.25 um

19
1024 M@ 0.15 um

150 mm

Index- 8
 TECHNOLOGY DEVELOPMENT
CMOS technology continues to mature, with minimum features size now approaching
0.1um . the technology progress for cmos is as follows.

TECHNOLOGY YEAR LENGTH

HCMOS 3 1989 1.2um

HCMOS 4 19192 0.7um

HCMOS 5 1994 0.6um

the voltage of 5L is5V and
HCMOS 5L 19195 0.5um of5 is2.3V
HCMOS 6 1997 0.35um

HCMOS 7 1998 0..

25um

HCMOS 8 19199 0.18um

8d is a derivative technology
HCMOS 8D 1999 0.18um of 8

HCMOS 9 2000 0.12um

 LAYOUT DESIGN RULES

➥ The goal of defining a set of rules is to allow for a ready translation of a circuit
concept into an actual geometry in silicon

➥ The design rules act as the interface between the circuit designer and the
process engineer

➥ The fundamental unity in the definition of a set of design rules is the minimum
line width, it stands for the minimum mask dimension that can be safely
transferred to the semiconductor material.

➥ A design rule set consists of the following entities a set of interconnect layers,
relations between objects on the same layer, and relations between objects on
different layers.

LAYER REPRESENTATION

The layer concept translates the intractable set of masks currently used into
a simple set of conceptual layout levels that are easier to visualize by the
circuit designer.

➥ A layout is a combination of polygons, each of which is attached to a certain

layer.

➥ The functionality of the circuit is determined by the choice of layers.

 The different layers that we use while making layouts are as follows;

① TRANSISTOR -A structure consisting of two SOURCE/ DRAIN regions of the

same type separated by a gate.
② SOURCE/DRAIN (S/D) -Heavily doped (N+ or P+), Active enclosed by a well of
opposite type.
③ ACTIVE - the area where transistors can be formed, the region is the diffusion
region. ACTIVE width is defined as the distance between adjacent shallow
trenches after oxidation of the trench. ACTIVE - the area where transistors can
be formed, the region is the diffusion region. ACTIVE width is defined as the
between adjacent shallow trenches after oxidation of the trench.

☞ INVACT -this layer is used to improve CMP uniformily,it is not a drawn layer it
is generated from ACTIVE.

④ SUBSTRATES and/or well being p-type (for NMOS) and n-type for (PMOS).

☞ NWELL width is defined as the distance between metallurgical junctions,

assuming that NWELL and PWELL are complementary
NWELL and the p-substrate form the diode.

⑤ POLY - It forms the gate electrodes of the transistors (but serve as interconnect
layer as well)POLY on ACTIVE is a critical design rule for short transistors.

☞ The poly extension of a transistor gate is the width direction required to insure
that the gate has full control of the channel
⑥ NLDD and PLDD are n-type and p-type lightly doped drains that are used to
insulate between different channels so that source and drain do not overlap or
simply to have separate identity, also to avoid hot carriers effect

⑦ ADHVTP and ADHVTN- A particular circuit can be of two types Low Leakage
High Speed in low leakage circuits speed is reduced and the threshold is high , we
add two layer Adhvtp (for p-type) and Adhvtn for (n-type )

⑧ PPLUS -the width is defined as the width of the resist opening at Source-Drain
implant.

⑨ NISO- it is to isolate all the P-well, we place it below n well.

☞ LIL - Local Interconnect Layer it is used for intra connection of cells, when we
use LIL we do not need contact. WE prefer LIL where distances are short. LIL is
Tungsten. Level of LIL and Poly is same so coupling Capacitance increases, where
matching is done LIL should be avoided. LIL reduces the resistance, from 20 -40
ohm to 1-2 ohm per sq.

☞ ABUTTING STRAP-Active divided between S/D. Active and well strap when both
are at the same potential

☞ NITRIDE - is used to open nitride and glass passivation(helps protect the chip
from contamination).

☞ CONTACTS -This is used to make a connection between the metal1 and the next
lower entity(ACTIVE or POLY). The CONTACT is made of material Tungsten.
➥ A Contact which forms an interconnection between metal1 and ACTIVE or POLY,
is formed by overlapping the two interconnecting layers and providing a contact
hole, filled with metal between the two. There are several available contacts: Metal
to p-active/ n-active Metal to polysilicon Vdd and Vss substrate contacts Split
(Substrate contacts)

➥ VIA1-connects Metal1 and Metal2

 INTRODUCTION
Reliability is as much a key to success in the micro-electronics industry as is
performance. Not only must a product perform as desired, it must also work for an
extended period of time without fail.

Overestimating the capabilities of the materials and the process could spell disaster,
and underestimating them could limit designs so severely that nothing of commercial
interest could be made. Striking a balance between conservatism and judicious use
of the process capabilities is necessary for continuous advancements.

Two types of reliability issues plague the industry

Defect related problem are caused by manufacturing defects, such as missing pro-
cess step, dirt or other unavoidable calamities.

Wear-out. is due to the circuit or the product just wearing out without any initial
defects being present .

Wear out which occurs due to limitations in the “perfect” material is a problem, that
lies within the designer. One of the principal wear out failure mechanisms is ELEC-
TROMIGRATION.
 ELECTROMIGRATION

DEFINITION
Electromigration is the mass transport of a metal due to the momentum transfer
between conducting electrons and diffusing metal atoms.

➥ It refers to the high current stress. As electrons move through a metal wire they
experience collisions with the atoms in the wire.

➥ These collisions cause wires to have resistance and become heated when used.

➥ If enough electrons collide with the metal, atoms move in the direction of the
electron flow causing two major problems;

0.0.1The moved metal atom leaves a gap in the wire. If enough atoms are moved, the
wire effectively breaks.

0.0.2The metal atom must move somewhere. If it moves to a location that causes a
short to a different metal wire, the functionality of the chip is changed.

0.1 HISTORY
Discovered more than 100 years ago it became a concern only when the relatively
severe conditions necessary for operation of ICs made it painfully visible.
In 1966 when theIC made its commercial appearance, EM was rediscovered by a
much larger audience, and with a vengeance.

➥ In IC’s electricity is conducted through thin film stripes that are in direct contact
with an effective heat sink. Since most of the heat generated by the current is
conducted away into the chip, thin film conductors can withstand current
 densities at least two orders of magnitude greater than traditional bulk wires. this
allows current densities of nearly 106A/cm2 with minimal Joule heating. at these
current densities EM becomes significant.

➥ ICs were supposed to be very reliable and great hope was placed in their use. When
the first ICs were placed into service, they failed within weeks. The shock to the
industry was tremendous IC manufacturers were in panic to understand why they
failed.

0.2 ORIGIN
In a perfect lattice, there is no resistance electrons move about in a periodic
potential with no other interaction with the metal atoms.

➥ The problem is that a perfect lattice cannot exist above absolute zero due to
missing atoms(“vacancies”), impurities, boundaries between crystals of different
orientation (“ grain boundaries”) , and regions of imperfections (“dislocations”) ,
also at any temperature above 00K, atomic vibrations occur.

➥ These vibrations put a metal atom out its of perfect position about 10 times each
second and disturb the periodic potential, causing electron scattering.

➥ The scattering event makes the electron change direction; any change in the
direction is accompanied by an acceleration; and for every acceleration there is a
force. After many collisions, the force averages in the direction of electron flow, this
force is called the Momentum Exchange.

In EM, momentum is exchanged between the electrons and the metal atoms and a
change in momentum with time is called force.
➥ To provide sufficient momentum exchange to cause measurable effects ,many
electrons must be available to collide with the atoms. This can only happen in a
metal. In metals, many electrons are easily accelerating in an electric field.
Semiconductors have far fewer electrons and in a true semiconductor ,EM does
not exist because there just aren’t enough charge carriers.

However, EM can occur in a semiconductors like materials , such as SILICON.

0.3 CAUSES

Metal EM result from a conductor carrying too much current. this effect is similar to
the erosion that occurs when a river carries too much water.
The result is a change in the conductor dimensions, causing spots of higher
resistance and eventually failure.
Em is primarily caused by

➥ WEAR OUT
EM in a specific sense is a long -term wear out mechanism of chip interconnect wires.
Failure due to wear out is a stasticial process that can be characterized its Mean
Time To Failure (MTTF)

➥ JOULE HEATING
Joule heating is a specific failure mechanism related to EM. Joule Heating refers the
excessive heating of a specific segment of a wire because of high AC currents wires
are heated as current moves through them
This heating occurs regardless of the direction of the current. If the heating of the wire
becomes too large, thermal expansion and temperature induced EM occurs, risk of
EM increases with temperature.
0.4 MATERIALS SCIENCE

The flux of metal atoms due to EM can be expressed using an electrostatic analogue
and Einstein’s equation for diffusion in a potential field
J=DC (Z*erj)/kt
where,
J =Atomic Flux
D= Diffusion Co-efficient
Z* effective valence or effective charge that represents the sign and the magnitude
of the momentum exchange
r - resistivity
j- current density
kt - average thermal energy per atom

So, EM induced mass flux is directly proportional to the current density, to the
diffusion coefficient and to the concentration of diffusing atoms.
Just having EM- induced mass flux is not enough to cause a problem, for a problem
to exist, either more or less mass must be entering a region than leaving it.
If more mass is leaving than arriving, we can form voids and open circuits.
If more mass is entering than leaving, extrusions will form short circuits or breaks the
passivation and provide an opportunity for corrosion, these regions are called flux
divergences.

0.5 EFFECT OF CURRENT DENSITY ON CONDUCTOR

LIFETIME
The equation states that the EM driving force is proportional to the current density
It could be assumed that EM FAILURE would scale in the same way- linearly with
the current; but that is not always the case traditionally, it has been observed that
 EM failure followed a 1/j*j law rather than 1/j - black’s law

➥ To insure that that EM failure does not occur in the field, we need to limit the
current density such that EM failure will not become significant until long after
the projected useful life time of the circuit.

➥ This is a function of not only the current density in the metal lines and contacts,
but also of temperature and often process variations.

0.6 EFFECT OF TEMPERATURE

➥ The major effect of temperature on EM is in the diffusion coefficient.
Diffusion is a thermal activated process characterized by the Arrhenius relation
and it possesses an activation energy.
➥ EM is very sensitive to temperature. Generally a change in TEMPERATURE OF
20 degrees can double the rate of EM. Therefore, the current permitted in a thin
film conductor is a function of temperature. the higher the temperature, the , the
less current can be permitted and still remain safe from EM failure.

IN DESIGNERS LANGUAGE

☞ EM is the physical dislodging of the ions after continues flow of current causing
permanent damage to the circuit. it is the flow of current from the metal causing
permanent damage to the circuit.
☞ It is an ageing process if this process continues over years ,then the width of the
metal gradually reduces and hence it can cause permanent damage to a device. this
phenomenon is more prominent when there is continuous flow of D.C. current as
regards to ac because in ac the flow of current changes its direction after every cycle

SOLUTIONS

① INCREASE THE METAL WIDTH

The size of metal width is kept larger than the minimum width required; and the
exact width is calculated from the DRM of the technology study

WIDTH

② INCREASE NUMBER OF CONTACTS

To make continuous flow of current, keeping in view the technology study.

contact
④ MAXIMUM NUMBER OF VIAS
0.7 SUMMARY

☞ EM has been with us since the early days of solid state devices,even before ICs
took center stage, like an old soldier, EM never dies and unfortunately it does not
have the good taste to fade away

☞ Cu helps a little, but not nearly enough as was hoped for.

☞ Recent advances have given us hope that although EM,will always exist and
cause problems, we can control it such that the advanced micro circuits can still
be designed with the reliability budgeting, if coupled with a detailed knowledge
of manufacturing process capabilities, can allow advances without
compromising long-term performance.

☞ EM as a design issue will be with us until we develop a room temperature super

conductor with a critical current density of millions of amperes per sq. cm that
is compatible with semiconductor processing. such a development is far in the
future, and we must exercise diligence in controlling the beast and respecting its
potential.

Where is it written that life is to be easy????

1 ANTENNA EFFECT

1.1 DEFINITION
During the manufacturing process, the metals are in the plasma (molten) state,
and these have charges which when passed to the gate can cause permanent
damage to the gate and hence are to be avoided.

➥ WORST CASE
This effect becomes more significant if the length of metal wire that is connected
at the input is very long also, sometimes when these charges are very high they
can even burn the device, causing the complete behavior change of the device.

1.2 HISTORY
➥ In today’s deep sub-micron technologies, more and more plasma enhanced
process steps are used.

➥ When an antenna is placed in the plasma, it is exposed to charged particles,

and electrical fields. a voltage can appear between the antenna and the
substrate , inducing a current through the gate-oxide.

➥ This current can have several impacts of different severity :

① VT Shift
② Oxide degradation
③ Hot carrier performance degradation.

➥ Charging can occur during the process at several steps, the data extracted
from dedicated tests structures, and the failure mode analysis have indicated
that the main contributors can be;
① contact etch
② beginning of metal deposition
③ metal resist removal
④ oxide deposition
⑤ sputter etch before metal deposition
⑥ vias etch and resist removal.

1.3 ORIGIN

➥ Antenna problems have existed in the chip manufacturing industry for more
than one decade.

➥ During Wafer manufacturing if the wire connected to input port is too long the
accumulated charges caused by UV lights on the long wires that are near the
input port damage the device, this reduces the wafer manufacturing yield.

➥ The amount of charges accumulated will depend upon the metal width
hence higher the metal width greater will be the charge accumulated and hence
higher the damage.

1.3.1PROTECTION AGAINST CHARGING

① When the metal is deposited and not yet patterned, it shorts all the modes, and
in particular it connects the gates to the substrate ensuring full protection
against charging.

② Lower charging is coming from POLY antenna, so the POLY antenna maximum
ratio is to be fixed at higher value .
1.4 MATERIALS SCIENCE

➥ ANTEENA RATIO the antenna ratio of a particular net is defined as

ANTEENA RATIO = TOTAL WIRE AREA/TOTAL INPUT PORT AREA

Where ,

TOTAL WIRE AREA starts from the input port before reaching the top most routing
layer

TOTAL INPUT PORT AREA is the total area of the input ports that are connected
with selected net

➥ PARTIAL ANTENNA RATIO (PAR) is defined for each metal node as

PAR {METi(Nj)} = area of the metal i, node j/sum of the areas of all gates
connected below metal i, nodej
 example;

METAL 5 )N1)

METAL 4 (N1)

METAL 3 (N1) METAL 3 (N2)

METAL 2 (N1) METAL 2 (N2) METAL 2 (N3)

METAL 1 (N1) METAL1 (N2) METAL 1 (N1 METAL 1 (N1)

GATE 1 GATE 2 GATE 3 GATE 5 GATE 6

GATE 4

① At metal 1, a metal line can induce charging to the poly gates directly
connected
PAR {MET1(N1)} = area of the metal1, node 1/sum of the areas of gate(1) gate (2)
, At Metal2, the metal 1 lines don’t collect charge as they are not in the direct contact
with the plasma; a metal 2 line can induce charging only to the poly gates
connected through metal 1
PAR {Met 2 (N1) = Area of Metal 2, node 1 / Sum of areas of gate (1), gate(2) gate (3),
gate (4).

Ina similar way the calculation can be extended to metal3,4,5 .

➥ CUMULATED ANTENNA RATIO (CAR) is defined for each METAL1 node as the
sum of the PAR of all the nodes connected on top of the node

from the previous example;

CAR {met1(N1)} = PAR {met1 (N1)} +PAR {met2 (N1)} +PAR {met3 (N1)} +PAR {met4 (N1)}
+PAR {met5 (N1)}

➥ ANTENNA RATIO (AR) is defined for each POLY node as, AR {POLY(Nj) = area of
POLY, nodej/sum of areas of all gates connected with POLY(node j)

➠ this does not includes the gate connected through METAL at metal 6, every gate is
connected to the output of the previous stage, excepted for the inputs; for the inputs,
the gate is connected to the diodes of the ESD clamp. so metal 6 is not used in the
calculation of Antenna Ratio (AR)

SOLUTION

➥ ANTENNA DIODE

A reverse diode is connected near the inputs which passes the changes on to the
ground without affecting the signal integrity. It helps in gate charging effect, the diode
gives low leakage. This diode is a part of Antenna DRC rule, this drives the charges
created during following process steps to substrate, preventing the transistor from
any subsequent damage.

Vdd
Gnd

➥ METAL BRIDGING PROTECTION

By this method ,we reduce the effective length of the metal.

METAL 1

this fig. shows that two devices connected without bridging, here we are
having the problem of Antenna effect.

Now the effective length of the metal 1 can be reduced as; so if there will be
any charges in M1 they will settle down at point A and will not be
 transmitted to metal2 and metal 3 and hence antenna effects can be
reduced.

A (met 5)
A (metal 4)

A2(met6)
A(metal 3)
A(metal 1)

A(poly) A(metal 2)

Bridging at METAL6 can be done with

stacked VIAs

➠ Important in cases where the matching of transistors is of first

importance, strong care has to be taken when designing the connection to
the paired devices.

➠ In order to avoid mismatch between antenna ratios, METAL lines are to be

as much symmetrical as possible.

➠ For same reason , the connection length have to be minimized. Diodes

connected to the gate at METAL1 are recommended.

.
 GUIDLINES TO DECREASE ANTENNA RATIO IN
DESIGNER’S LANGUAGE

① In All Cases where it is possible in term of silicon area availability, diode

connection of metal lines to active area is recommended.

② These diode drive the charges created during following process directly to
the substrate, preventing the transistor from any subsequent damage.

③ To be more efficient such diode protection has to be introduced at Metal 1

level if possible. the eariler (in term of process fabrication steps) the diode is
created, the more efficient is the protection.

④ Any error detected at the DRC must be corrected using one of the following
solutions.
➠ Connect directly the node to the output of the driver with a lower METAL
level and reduce the METAL area.
➠ Connect the node to a diode
➠ Connect the gate to METAL6 as close to the gate as possible. VIAS stacked
on CONTACTS allow to do this connection in a small area.
2 LATCH UP

2.1DEFINITION
If every cloud has a silver lining then the silver lining that has plagued CMOS is a
parasitic circuit effect called “LATCH UP”

The result of this effect is the shorting of the Vdd and the Vss lines, usually
resulting in the chip self - destruction or at least system failure with the
requirement to power down If care is not taken when laying out CMOS circuits,
the parasitic devices present can cause LATCH UP.
2.2 PHYSICAL ORIGIN OF LATCH- UP
The source of LATCH UP effect can be explained by examining the process cross -
section of a CMOS inverter

FIGURE A
2.3LATCH UP PREVENTION

RW1

C1
Q1

RW2

can causeQ2
to turn “ON”
figure B
Q2

C2
RS2

source of n-channel
substrate
 Fig B illustrates the cross sectional view and C illustrates the Schematic

A (inverter input)

n channel p channel ,n2

l ,n1
l ,n1 A1(inverter output)
Substrate well connection
Connection
Vdd

p+ n+ C1 p+ n+
n+
p+

Q2
Q1

N well

C2

figure C
Rs2 Rs1

CROSS SECTIONAL VIEW OF AN INVERTER SHOWING PARASITIC

BIPOLAR TRANSISTORS AND RESISTORS

➥ In Fig. B , the Emitter, base, and the Collector of transistor Q1 are the source
of the p- channel, the n-well and the substrate respectively.
➥ Transistor Q2’s collector, base and emitter are the n -well1 are the source of the
p -channel , the n -well , and the substrate and source of the n -channel
transistor.

➥ Transistors RW1 and RW2 represent the effects of resistance of the n -well and
resistors RS1 and RS2 represent the resistance of substrate.

➥ The capacitors C1 and C2 represent the capacitance between the drains of the
transistors and source and substrate. The parasitic circuit resulting from the
inverter layout is shown in fig.C.

2.4 EXPLANATION

➥ If the output of the inverter switches fast enough, the pulse fed through C2 (for
positive going inputs ) can cause the base -emitter junction of Q2 to become
forward biased.

➥ This then causes the current through RW2 and RW1 to increase, causing Q1
to turn “ON”. When Q1 is turned “ON”, the current through RS1 and RS2
increases, causing Q2 to turn “ON” harder, this positive feedback will
eventually cause Q2 and Q1 to turn “ON” fully and remain the way until the
power is removed and reapplied.

➥ A similar argument can be made for negative going inputs feeding through C1.
① Reduce the resistor value.
② Reduce the gain of parasitic transistors.
③ Increase the holding voltage above the Vdd supply.

2.5STEPS FOR REDUCTION OF LATCH -UP

For the above LATCH-UP condition to reduce, several techniques are applied
① Slow the rise and fall time of the logic gates, reducing the amount of signal fed
through C1 and C2
② Reducing the area’s of M1 and M2’s drains lowers the size of the depletion
capacitance and the amount of signal fed through.
③ Reduce the parasitic resistances RW1 and RS2. If resistances are zero (0), Q1
and Q2 never turn “ON”. The value of these resistances is a strong function of
the distance of well and substrate contacts.
④ The closer these contacts are to the inverter, the fewer are the chances the
inverter will LATCH -UP.
⑤ These contacts should not be only close , but plentiful.

2.6 CAUSES OF LATCH -UP TRIGGERING

➥ Transient currents or voltages that may occur internally to a chip during power
-up externally due to voltage or current beyond normal operating ranges.

➥ Radiation pulses/ Optical excitation.

➥ Increase in device temperature .It uses the carrier generation rate and carrier
lifetimes.

➥ Improper sequencing of power supplies.

➥ Presence of large d.c.currents in substrates.

 PREVENTION TECHNIQUES WHILE MAKING LAYOUT

☞ Every well must have a substrate contact of appropriate type.

☞ Place substrate contact as close as possible to source connection of

transistors connected to supply rails.

☞ Use extra substrate contacts to Vss to reduce R substrate and extra N-well
contacts to Vdd to reduce Rwell.

☞ Retrograde well structure. Highly doped area at the bottom of the well whereas
the lightly doped area at the top of the well.
This preserves good characteristics for MOS transistor but reduces R well or
R substrate.

☞ SOI (SILICON ON INSULATOR) CMOS technology can be used to electrically

isolate pnp and npn transistors.

☞ Apply a negative voltage instead of Vss to the substrate will be lowered.This

can not be then easily turned “ON”.

☞ Include P+ guard rings connected to Vss around n-transistor.

These guard rings act as dummy collectors and spoil the gain of parasitic
transistors by collecting minority carriers and preventing them from being
injected into the respective bases.
☞ Similarly, include N+ guard rings connected to Vdd around p-transistor.

☞ Avoid placing alternate N-Well and P-Well.

☞ Try to put substrate at the boundaries of the N-Well and P-Well because
switching is more at these areas

PRACTISES

When area is not a main consideration, this condition is ideal

FOR N DEVICE

N Device

GUARD RINGS
 FOR P DEVICE
This condition is ideal but its implementation is not always possible because it
takes a lot of space to make these kind of GUARD RINGS

N WELL
➥ But we have limited area, then depending upon the available space we can
choose any of the given conditions.

LONG BODY
CONTACTS

N WELL
 N DEVICE

GND

BODY CONTACT

BODY CONTACT

N WELL
when minimum area is available

N WELL
 IMPORTANT TIPS
➥ Concentrate only on the boundaries of wells.

➥ In chips with more number of transistors make big wells and put straps at the
boundary.

➥ Straps should be connected by metal and never in POLY and less in LIL

➥ Separate strap connections for Vdd and Gnd i.e. split Vdd and Gnd.

Vdd N well

Vdds
2.7 SUMMARY

Large MOSFET’s required to drive off-chip loads, are especially susceptible to

latch -up because of the large drain depletion capacitances. The only way to
design latch-up free output drivers is to use only one type of MOSFET ,in most
cases an n -channel. Eliminating the n -well and p -channel transistor eliminates
the possibility of LATCH -UP.
1 DRAIN PUNCH THROUGH
1.1 DEFINITION
When the drain is at high enough voltage with respect to the source , the depletion
region around the drain may extend to the source, thus causing current to flow irre-
spective of the gate voltage (i.e. even if it zero ). this is known as PUNCH THROUGH
condition.

No channel exists in the vicinity of the drain region. For this phenomenon to occur, it
is essential that the pinch-off condition be met at the drain region or,

Vgs-Vds<=Vt

Currently this effect is used in the I/O protection circuits to limit the voltage across
internal circuit nodes, although it will impact design as devices are scaled down by
requiring that internal circuit voltages be reduced to a point where the effect does not
occur.
Gate
Drain
Source

n+
n+

p-substrate
2 BIRD’S BEAK

2.1 DEFINITION
To prevent active regions from oxidation, they are covered with SiO2/SiN
sandwich. Then Local Oxidation of Silicon (LOCOS) is done to separate these
active device regions.
The oxide grows in both directions vertically and also laterally under the SiO2/
SiN sandwich. this lateral movement results in “BIRD’s BEAK” because of the
shape of the oxide encroachment under the gate oxide mask.
The oxide encroachment results in an active area that is smaller than
patterened.In particular width dimension of a transistor will be reduced from
what might be expected from the photolithography.

2.2 KOOI FOR WHITE RIBBON

Si3N4+6H2O = 3SiO2 +4NH3
The ammonia produced under the nitride in the bird’s beak region can diffuse
through the silicon dioxide to the oxide -silicon interface where it reacts to
form interface nitride layer around the edges under the nitride island. During
gate oxidation , the silicon nitride (white ribbon ) significantly reduces the
thickness of the gate oxide around the perimeter of the gate oxide region, pre-
venting the formation of the highest quality gate oxide.

Bird’s Beak Oxide from Si N

Field oxide

KOOI EFFECT
(100) p type wafer
Stress - relief SiO2
3.0 BODY EFFECT
➥ All devices comprising an MOS device are made on a common substrate.As a
result, the substrate voltage of all devices is normally equal.

➥ In arranging the devices to form gating functions it might be necessary to

connect several devices in series.

➥ This may result in an increase in source - to -substrate voltage as we proceed

vertically along the series chain (Vsb1 =0 ,Vsb2 is not equal to zero).

➥ Under normal conditions i.e. when Vgs>Vt the depletion layer width remains
constant and charge carriers are pulled into the channel from the source.

➥ However as the substrate bias Vsb (V source - V substrate ) is increased the

width of the channel -substrate depletion layer also increases, resulting in an
increase in the density of the trapped carriers in the depletion layer. For charge
neutrality to hold, the channel charge must decrease.

➥ The resultant effect is that the substrate voltage (Vsb) adds to the channel-
substrate junction potential. This increases the gate -channel voltage drop.

➥ The overall effect is an increase in the threshold voltage Vt (Vt2>Vt1).

➥ The threshold voltage Vt is not constant with respect to voltage difference

between the substrate and the source of the MOS transistor.

➥ This is known as the substrate -bias effect or the BODY EFFECT.

➥ The expression for the threshold voltage may be modified to incorporate Vsb,
the difference between the source and the substrate.
1 POWER SUPPLY
1.1 DEFINITION
The power consumption of a gate determines how much heat the
circuit dissipates and how much energy is consumed per operation.
Power Dissipation is an important property of a gate that affects
feasibility

1.2 CAUSES.
The components that establishes the amount of power dissipated in a
CMOS circuit are:

➥ STATIC DISSIPATION - is due to the leakage current or other current

drawn continuously from the power supply.
Ps =summation leakage current* supply voltage
where,
n = number of devices.
Static Dissipation can occur in gates such as pseudo -nMOS gates,
where there is a direct path between power and ground, if such gates
are used, their static dissipation must be factored into the total static
power dissipation of the chip.

➥ DYNAMIC DISSIPATION -It is due switching transient current.

charging and discharging of load capacitances
Pd =ClVdd2fp
where,
Cl=load capacitance
fp = 1/tp (repetition frequency).

➥ SHORT -CIRCUIT DISSIPATION - the short- circuit dissipation is

Psc =Imean *Vdd
so the total power dissipation is sum of the three dissipation
components as,
Ptotal = Ps+ Pd+ Psc.

Index- 51
 ☞ a rule thumb rule while calculating the power dissipation is to add all
capacitances operating at a particular frequency

1.3 POWER ECONOMY - LOW POWER DESIGN

Minimizing the power dissipation can be achieved in a number of ways
➥ DC power dissipation may be reduced to leakage by only using complementary
logic gates.

➥ The leakage is in turn proportional to the area of diffusion, so the use of

minimum sized devices is of advantage.

➥ Dynamic power dissipation can be limited by reducing supply voltage,which

tends to be a system- design consideration, and low power systems use 1.5 to
3Volts.

➥ Minimizing the switched capacitance tends to favor using minimum-sized

devices and optimal allocation of resources such as adders and registers.

➥ The stray capacitances may be reduced by using the smallest number of

transistors to implement a function .

➥ The final parameter that affects speed is the frequency of operation of the
circuit , the reduction in supply voltage is quadratic , while speed is inversely
proportional to the supply voltage.

➥ Power -down modes are important for lower power applications, aan example
for this is that the length of the clock line that remains clocking during power
down, it should be stopped as close as possible to the clock pad. A clock line
traversing a chip can add appreciably to the power - down current.
 ➥ For low - power design one should use the lowest supply voltage and operating
frequency consistent with achieving the required performance.

➥ Manual layouts techniques are also of use to minimize routing capacitance

1.4 MATERIAL SCIENCE

The propagation delay and the power consumption of a gate are related The
propagation delay is mostly determined by the speed at which a given amount
of energy can be stored on the gate capacitors, the faster the energy transfer
the faster the gate.
For a given technology and gate topology,
the product of power consumption and propagation delay is called power
delay product (PDP) and is considered as a quality measure for switching
device,
the PDP is simply the energy consumed by the gate per switching event

→ A single run of conductor can not be made to supply all circuits in a design, in
these cases a layer change must be necessary.

→ The current density in a contact periphery must be kept below about 0.1mA/
um.

→ The direction of the current flow after passing through a contact can also
influence the current-carrying capacity.

→ If the current flow turns at right angles or reverses, a square array of contents
is generally required, while if the flow is in the same direction, fewer contacts
may be used.
Contact structures for
linear and orthogonal
joints.
1.5POWER DISTRIBUTION
At 5 Volts operation, the chip dissipates around 2.5 watts and draws 500 mA.
On average this is 55mA per section with the peak current being much higher
than this to achieve metal migration requirements and reduce switching noise
each section is effectively provided with a power and ground pad. these con-
nections were routed in metal 3, in addition, to reduce power supply noise on
chip bypass were placed under the power lines , these consist of large gate -
area n- transistors, with their gates connected to Vdd and source and drains
connected to Vss (substrate)
 IMPROVEMENTS IN LAYOUTS

➥ Pins should be at proper locations preferably on already used metal.

➥ Substrate to source connection should be made bigger (than minimum

active rule)

➥ Move contact in middle of source and drain of transistors. Increase the

number of contacts for output from higher drivers.

➥ Try to avoid notches in all layers preferably in metal and poly.

➥ Labels (cell name ) should be at correct location

➥ Ports should be made in preferred direction especially for output pins.

➥ Metals should run on grids, if possible (more useful for HC8 /HC8D).

➥ Use less notches on boundary layer to have abstracts.

➥ More substrate connections, if possible.

➥ Use LIL for Vdd/Gnd connection

➥ While taking a connection from Drain/Source by metal, put LIL on top of it

(not more than half of drain/source length)
➥ Avoid usage of 45degree bent poly as far as possible (HCMOS9 onwards, it
is strictly prohibited).

➥ Pins should be of two grids, label must be on origin.

➥ Do not make the line width too small, it is possible for the line to become
discontinues, thus leading to open circuit wire.

➥ If the wire are made too close to one another, it is possible for them to merge
together i.e. shorts can occur between two independent circuit nets.
1.0 YIELD
1.1 DEFINITION
An important issue in the VLSI structures is the Yield, although Yield is
not a performance parameter, it is influenced by factors such as:

➥ TECHNOLOGY
➥ CHIP AREA
➥ LAYOUT

Once the Silicon has been processed, other manufacturing yield factors,
such as scribe yield and packaging yield, also contribute to the overall
yield of a device.

1.2 MATERIAL SCIENCE

Yield is defined as

Y = No. of good Chips on wafer/Total no. of chips.

and may be described as a function of the chip area and defect density.
Over the years, a number of models have been developed by Murphy

Y = (1=eAD/AD) 2
where,

A = area
D = defect density.

➥ The Yield decreases dramatically as the area of the chip is increased.

Memory designers use two approaches to compact low yields and to

reduce the cost of these complex components:

Index- 58
 ☞ REDUNDANCY

Memories have the advantage of being extremely regular structures. Providing

Redundant hardware is easily accomplished. Defective bit lines in a memory array
can be replaced by redundant ones, and the same holds for word lines. When a
defective column is detected during testing of the memory part, it is replaced by a
redundant one by programming the fuse bank connected to the column decoder.

A typical way of doing so is to blow the fuses using a programming laser. A similar
approach is followed for the defective word lines. Whenever a failing word line is
addressed the word redundancy system enables a redundant word line.

① In random logic, yield improvement is minimal due to increase in the area, however
in memory structures, it is possible to gain dramatic improvement in
Yield through incorporation of redundant cells so the
effective yield is given by:(No. of Full passes + repaired chips / Total no. of chips)*1/
area
☞. Increase in the area is the penalty for redundancy.
Row Address
Redundant Rows

Fuse
Bank
Memory
Redundant Array
Columns
Row Decoder

Column Decoder Column Address

Redundancy in memory array increases the Yield
☞ ERROR CORRECTION
Redundancy helps correct faults that affect a large section of the memory such as
defective bit lines or word lines. It is ineffective when dealing with scattered point-
errors such as local errors caused by material defects.
Achieving a reasonable fault coverage requires too much redundancy under these
circumstances and results in a large coverage requires too much redundancy
under these circumstances results in a large area overhead.
A better approach to address these faults is to use ERROR CORRECTION. The
idea behind this scheme is to use redundancy in the data representation so that
an erroneous bit(s) can be detected and even corrected.
1.0 NOISE
The major drawback of the dynamic logic circuits is their noise
immunity.
➥ For a static logic circuit, despite the noise, the output can be recovered
by itself,
➥ In the dynamic logic circuit,

1.1 CAUSES
Due to the procreate/predischarge scheme, once the data at the output
are destroyed by the noise, it cannot be recovered.
In the dynamic logic circuit system,
① Due to the simultaneous operation of the precharge/predischarge and
evaluation schemes, the fluctuation in the current on the power line
can be large, therefore the sudden change in the current on the ground
line (dI/dt) is a major cause of noise.
② In addition alpha particles generated charge in a dynamic mode can
cause noise problems
③ Electromagnetic radiation from external sources
④ Capacitive coupled crosstalk from neighboring wires

1.2 REDUCTION OF NOISE PROBLEM

Noise problem can be reduced by illustrating with the following exam-
ple;
The fig. shows an external inverter with a pull-up PMOS to increase
noise immunity, as shown in the fig., by adding the inverter with a posi-
tive feedback, the noise margin of the CMOS dynamic logic circuit can
be improved. During the discharge of the NMOS logic tree, it is like a
ratioed logic circuit since the pull -up PMOS device also turns “on”. The
pull -up PMOS device turns “off” when the inverter output is high. how-
ever, the speed is lowered and the power consumption is increased.

Index- 61
 Vdd
Vdd

in
LOGIC
Vout

External inverter with feedback to increase the noise

immunity for a CMOS dynamic logic circuit.

Index- 62
1.0 NOISE MARGIN
1.1DEFINITION
Noise Margin is the parameter closely related to the input -output
voltage characteristics.
This parameter allow to determine the allowable noise voltage on the input
of a gate so that the output will not be affected

1.2 MATERIAL SCIENCE

The specification used to specify noise margin is in terms of two
parameters -

➥ LOW NOISE MARGIN (NML)

NML is defined as the difference in magnitude between the maximum LOW

output voltage of the driving gate and the maximum input LOW voltage
recognized by the driven gate.Thus

NML = VIL (max) - VOL(max)

➥ HIGH NOISE MARGIN (NMH)

NMH is the difference in magnitude between the minimum HIGH output

voltage of the driving gate and the minimum input HIGH voltage recognized
by the receiving gate, thus

NMH = VOH(min) - VIH(min).

Where,

VIH(min) = minimum HIGH input voltage.

VIL (max) = maximum LOW input voltage.
VOH(min) = minimum HIGH output voltage.
VOL(max) = maximum LOW output voltage

These definitions are illustrated with the fig.

Index- 63
 Output Characteristics Input Characteristics

Vdd

Logical High VOH(min)

Output
Range Logical High
Input Range
VIH(min)
Interminate
Region

VIL(max)

Logical Low
Logical Low Input Range
Output Range VOL(max)

Vss

NOISE MARGINS DEFINITIONS

Index- 64
 PRACTISES

Some simple practises to reduce noise and other undesired effects Noise and other
unwanted effects may occur due to many reasons one of them is coupling, to
reduce this are

➥ Avoid running parallel lines for signals.

➥ For critical signals like clock etc.provide proper and identical shielding

gnd Vdd
gnd Vdd

x
x
x x

Signal
Signal
➥ Reduce Routing, as the Routing increases the capacitance increases

➥ Try to put all the PMOS’s at one place

➥ At the periphery of folded transistors always provide Vdd or gnd and the
covered sides other critical signals

➥ Shielding of bit and bit bar is done to decrease noise effect.

gnd gnd

x signal
➥ Put as many as contacts as possible for big transistors, this helps in
good flow of electrons, electrons does not love to flow through active
but metal

Index- 67
➥ Avoid using LIL in long transistors as POLY and LIL are on same
level and can give rise to Coupling

➥ Give some extra enclosure to Via this would help in case if Via shifts
during procession secondly to reduce the resistance

VIA

METAL 1

METAL 2

VIA shifts

(increased Resistance)

Index- 69
➥ Good Substrate connections should be provided

➥ Good Power distribution ensured.

➥ Restricted use of LIL on Global Nodes and on matching devices.

➥ Special care is taken to keep input pin capacitance same as in

Schematic.

➥ Layouting should be done taking into account the external pin

positions and specific design guidelines to match schematic
capacitance at the Layout level.

➥ External signals should be tapped as close as possible.

➥ To have equal rise and fall times and balance capacitances even
folds are ensured in maximum transistors.

➥ Avoid metal Capacitances, even folds are ensured in maximum

transistors

➥ Avoid metal Capacitance for clock signals.

➥ Bit and Bit Bar should be shielded properly to avoid Cross talk.

Index- 70
 ELECTRICAL ASPECTS

MOS device requires a gate forming region and a source/drain forming region,
which consists of diffusion, polysilicon, and metal layers separated by insulating
layers.

Each layer has both a resistance and a capacitance that are fundamental compo-
nents in estimating the performance of a circuit or system. They also have induc-
tance characteristics that are important when considering I/O behavior but
usually assumed to be negligible for most on - chip circuits.

RESISTANCE

The RESISTANCE of a material is a function of the material, resistivity and the

material dimensions.explaining with the example, the slab of material between the
two leads has resistance given by,
W

L
W
t L

LAYOUT VIEW

R = RESISTIVITY * LENGTH/THICKNESS *WIDTH

 In semiconductor processing, all the fabricated thickness, are constant, so only
WIDTH(W) and LENGTH (L) have to be considered

R = Rsq * L/W

Where,

Rsq is the sheet resistance of the material in ohm/square

CALCULATION OF RESISTANCE

B
B
2 3

A A

LAYOUT (TOP VIEW)

Fig (a) for the calculation of the R of a corner section

Fig (b) layout to avoid corners.

 The layout shown uses wires to connect separate sections of a resistor avoiding
corners. Avoiding corners in a resistor is the generally preferred method of layout
in analog circuit design where the ratio of two resistors is important.

CONTACT AND VIA RESISTANCE

Contacts and vias also have a resistance associated with them that is dependent
on the contacted materials and proportional to the area of the contact.

As contacts reduce in size ( i.e. processes are scaled down[]) the associated resis-
tance increases. Typical values for processes currently in use range from 0.25 ohm
to a few tens of ohm’s. For low -resistance interlayer connections multiple contacts
are used.

VIA

The via layer is used to make a connection between metal1 and 2.The via layer spec-
ifies where to remove glass so that when metal2 is deposited it makes contact with
metal1, associated with this connection is a contact resistance, this resistance arises
because the metal 2 thins as it is deposited in the hole or as a result of the contact
potential difference between two different materials. minimum contact resistance for
the via is 0.05 ohm maximum contact resistance for the via is 0.08 ohm.
 CAPACITANCE

The switching study of MOS system are strongly dependent on the Parasitic capaci-
tances associated with the MOS device and the interconnection capacitance that are
formed by metal, poly,and diffusion wires in concert with transistor and conductor
resistance.

The total load capacitance on the output of CMOS gate is sum of

➥ gate capacitance (of other input connected to o/p)

➥ diffusion capacitance (of drain region connected to o/p)
➥ routing capacitance (of connection b/w the o/p&other i/p)

CAPACITOR CHARACTERSTIC

The capacitor voltage characteristics of a Mos capacitor depend on the state of

semiconductor surface. Depending on the gate voltage the surface may be in

➥ accumulation
➥ depletion
➥ inversion

Referring to the p-substrate structure, an accumulation layer is formed when Vg<0.

The negative charge on the gate attracts holes toward the silicon surface. when the
accumulation layer is present the Mos structure behaves like a parallel plate
capacitor.

The gate conductor forms one plate of capacitor the high concentration of holes
forms the second plate.

Since the accumulation layer is directly connected to the substrate the gate
capacitance may be estimated by
Co=(Esi02Eo/tox)*A

where
Permittivity of free space

Esio2=dielectric constant
tox=thickness of oxide layer
A= area of gate

when a small Positive voltage is applied to the gate w.r.t substrate a depletion layer
is formed in the P-substrate directly under the gate.

➥ The Positive gate voltage repels holes, having a negatively charge region depleted
of carriers.
➥ Since the magnitude of charge density per unit are in the surface of depleted region
is dependent on the doping concentration (N), electronic charge & depth of surface
depletion region increasing the gate to substrate voltage also increases d.

The depletion capacitance is given by

Cdep=(EsiEo/d)A

where
Esi=dielectric constant of silicon

depletion layer depth

➥ As depth of the depletion region increases the capacitance from gate to

substrate will decrease.

The total capacitance from gate to substrate under depletion condition can be
regarded as series combination of capacitance due to gate oxide capacitance and
that due to Cdep.
so,

Cgb=CoCdep/(Co+Cdep)

➥ As the gate voltage is further increased,minority carriers are attracted toward

surface.

➥ This effectively inverts the silicon at the surface and creates an n-type channel.

MATERIAL SCIENCE

The behavior of gate capacitance of an Mos device can be explained in term of the
following simple models in three region of operation:-

➥ OFF REGION
where Vgs<Vt when the Mos device is “OFF”. There is no channel

➥ NON SATURATED REGION

where Vgs-Vt>Vds as channel is formed the gate to channel capacitance these
capacitance are dependent on gate voltage and Cgb effectively falls to zero

IN DESIGNER’S LANGUAGE
Capacitor is a natural MOS capacitor, realized with N+ ACTIVE area and the POLY
in NWELL, it requires no extra mask

In order to reduce the risk in case of transfer in manufacturing lines using other
equipments and in order to take into account the effect of defectively on large
capacitors, the following rules are recommended

➥ The POLY plate should be connected to a diode at METAL 1

 ➥ If a diode cannot be connected to the POLY, the length and the area of the
METAL connections should be minimized; the number of VIAS should be
minimized as well.

DECOUPLING CAPACITORS

With the improved speed of the products and the increasing number of gates able
to switch at the same time, the need for decoupling capacitors is increasing.

These capacitors are usually made with gate oxide, this extra oxide area is increas-
ing the risk of yield loss and reliability,
So the following rules must be applied.

RULES FOR DECOUPLING CAPACITORS

➥ If large areas of N+POLY/ NWELL capacitors are used for decoupling, this
can reduce the product yield and reliability

➥ POLY plates must be protected against charging with diodes connected with
METAL1

➥ Use only the amount of decoupling capacitor which is strictly necessary.

➥ Use only the number of CONTACTS which is strictly necessary

➥ Use MATRIX of several capacitors with one contact per POLY plate, rather
than a large capacitor with many CONTACTS.
 PRACTISES

➥ Reduce the long running metal 1.

➥ Avoid two rails for metal1 running parallely to increase the

switching and to decrease the delay time we incorporate

➥ Folding in transistors which in turn reduces the SOURCE /

DRAIN capacitance.

➥ Maximum possible substrate connections are to be made

➥ In order to decrease sheet resistance of metal 1 we provide

long LIL in large transistors.

➥ Do not run long POLY’s parallely

Index- 78
 LAYOUT CHALLENGES

Devices layouts parasites are parasitic elements added to the

nominal device or element by the process of generating the specific layout
geometry for example for an MOS device with a large width , there are
many possible layout variants, each corresponding to a different aspect
ratio.

➥ During the layout process the layout designer, needs to be able to

switch between several of the layout variants in order to best fit
the device into the available space.

➥ There is almost a factor of two decrease in the capacitance

between the drain and the well or substrate when going from no
folds in the gate to one fold in the gate.

➥ However, the difference between one fold and three folds is only a
few percentage ( only a difference in the total perimeter of the
drain)

➥ Therefore a common strategy during design is to assume that

devices larger than some minimum width will always be folded at
least once and will have an even number of gate strips

Index- 79
.
 DRAIN

SOURCE

SOURCE

DRAIN

SOURCE

SOURCE

DRAIN

SOURCE

DRAIN

SOURCE

EXAMPLES OF LAYOUT VARIANTS FOR A SINGLE MOS DEVICE

This is an example of the kind of strategies which can be adopted to minimize th
occupying between the circuit design and the impact of layout parasites

SHARING OF DEVICES

Another extremely important impact on device parasites is the possibility of

separate devices sharing pieces of geometry.

For example, the sum of drain -to -substrate capacitance of a cascaded current
mirror can be dramatically decreased by sharing the drain diffusion of the
current mirror transistor.

In essence, this is a generalization to multiple devices of the type of geometry

sharing already introduced in the folding of a single device

ADVANTAGE OF MERGING DIFFUSION REGIONS

➥ Total area of the cell is reduced

➥ The complexity of the routing task is decreased.
THE DEVICES SHOWN HERE ARE NOT MERGED
ABUTMENT ROUTE

3 MERGED DEVICES

THE GROUP OF DEVICES IMPLEMENTS THE SAME CIRCUIT,BUT

EMPLOYS MERGING AND ROUTING BY ABUTMENT
 SHIELDING

An important option to keep in mind when two signals must cross

topologically, but cannot couple capacitively is to insert a shield layer.

For example in a fabrication process with two metal layers, first level metal
can be used as a shield while the two signals cross on second -level metal
and poly.
LAYOUT FOR CROSSING STRUCTURE PICTURE ON LEFT ILLUSTRATES
THE CASE WHERE A TWO WIRES CROSS AND A COUPLING
CAPACITANCE OCCURS. ON THE RIGHT SIDE, THE CAPACITIVE
CROSSTALK IS BLOCKED BY A THIRD SHIELDING LAYER.
Index- 88
Index- 89
Index- 90
Index- 91
Index- 92
Index- 93
Index- 94