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The Modeling and Simulation for Current Regulation of PMSM Drive System
using Verilog HDL and Variable Structure Control
Chiu-Keng Lai and Chia-Che Tsai
 here, we proposed a hardware controller with the VSC
Abstract—In this study, we design the permanent magnet
synchronous motor (PMSM) drive system using field
programmable gate array (FPGA), and adopt variable structure
control (VSC) to the current regulation. The system is first
modeled with Matlab/Simulink, and the controllers in the
system, including the speed PI control and current variable
structure control, are hardware implemented by Verilog HDL
code. Finally, the resulting hardware system is co-simulated
with the software motor model to evaluate the accuracy and
performance. The resulting Verilog HDL codes can be as an IP
format to hardware realize the vector control for PMSM, and
with the properties of robustness to the parameter variations
and fast responses on the current loop control.
Keywords: Field Programmable Gate Array, Permanent Magnet
Synchronous Motor, Vector Control, Variable Structure Control,
Verilog HDL.
I. INTRODUCTION
Permanent magnet synchronous motor (PMSM) drive has
been widely used in various fields due to its characteristics of
rapid response, high tracking precision, strong
anti-disturbance ability and simple structure. However, in a
practical PMSM drive system, which is nonlinear, and there
are large quantities of disturbances and uncertainties, e.g.,
unmodeled dynamics, parameter variation, friction force, and
load disturbances. Thus, it is difficult to achieve a satisfactory
performance in the entire operating range only by linear
control algorithms [1-2].
In recent years, with the development of modern control
theory and motion control technique, various methods of
nonlinear control have been proposed for the PMSM drive
system. Generally, for most of the commercial AC motor
drive system design, the position control, speed control and
current regulation are usually realized by PI controller [3]. On
the other hand, the variable structure control (VSC) scheme
has also been used on AC motor drive, e.g., PMSM [1-2],
induction motor (IM) [4, 5] and synchronous reluctance
motor (SynRM) [6], for current, speed or position control. In
Research supported by the Ministry of Science and Technology of Taiwan
with grant no. MOST 104-2221-E-167-005.
C. K. Lai is with the Department of Electrical Engineering, National
Chin-Yi University of Technology, Taichung City, Taiwan. (corresponding
author TEL: 886-4-23924505 ext. 7216; Fax: 886-4-23924419; e-mail:
chiukl@ncut.edu.tw).
C. C. Tsai is with the Department of Electrical Engineering, National
Chin-Yi University of Technology, Taichung City, Taiwan. (e-mail:
four0924@yahoo.com.tw).

scheme to the d- and q-axes current regulation for PMSM
drive system to achieve the desired performance such as
invariant to parameter variations and fast response
requirements, and reducing the cost to realize the motor
drivers which are usually realized by digital signal processor
(DSP).
Field programmable gate array (FPGA) is fully
customizable to the requirements of the system designer. This
allows a completely flexible design which is custom made for
the particular type of motor control technology [7], and its
further functionality can be added anytime. It can be adapted
to any change in design by dynamic reconfiguration [8]. In
fact, FPGA-based digital controllers have been implemented
with success in many different applications and controller
designs, examples as motor drives for induction motor [9],
permanent magnet synchronous motor [10-11], stepper motor
[12], and brushless DC motor [13]. FPGAs are also used to
the controller design, such as PID controller [14], fuzzy
controller [10], tracking controller [12], and also designed to
implement the space vector pulse width modulation
(SVPWM) [11].
In this paper, we implements all the control loops (inner
current and outer velocity and position) using the FPGA chip.
We first use Matlab/Simulink to model a PMSM drive system
including all the facilities of controllers and signal converters.
And via the functionality of Matlab/Simulink, we create a
Verilog HDL code to digitalize the software system into
hardware code. At last, we use the co-simulation technology
to verify the accuracy and performance of the proposed
hardware controller. The hardware system can be in an
Intellectual Property (IP) format to be used to realize the
PMSM drive design to reduce the cost. Furthermore, the
parameter’s variations of the current loops can be solved by
the proposed variable structure controllers to have a fast
response and robust performance.
II. THE MODELING OF PERMANENT MAGNET
SYNCHRONOUS MOTOR DRIVE SYSTEM
The model of the PMSM expressed in the d-q synchronous
reference frame is given as [3]
ªv ds
e º
ª R s  Ls P 0 º ªids
e º
ª 0  Ze Ls º ªids
e º
ª 0 º
« e » « » « e »« « e »«
¬«v qs ¼» ¬ 0 R s  L P
s ¼¬ « qs ¼» ¬Z e Ls
i 0 ¼ ¬«iqs ¼» ¬Z eI F' »¼
»
(1)
e
where Rs is the stator resistance, Ls is the inductance, vds ,
e e
vqs e
, ids and iqs are respectively the d and q-axis voltages and
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currents. I F' is the flux, Ze is the electrical rotating speed, where a Rs / Ls and b 1 / Ls . To consider the
and P d / dt . The generated torque of PMSM is expressed parameter’s variations, the variables a and b are re-defined
in terms of the rotor flux and stator current as as
a a  'a
I Fc e
Te iqs (2)
c and

where c 2 / 3 or 2 / 3 . b b  'b
The rotor dynamics is described as follows,
where a and b are the nominal values, and 'a and 'b are
dZ m the uncertainties. Thus, we have a set of new function to
J  BZm  TL Te (3)
dt represent the d- and q-axes equivalent circuits as:
where Zm is the rotor mechanical speed, TL is the external e
dids e e e
(a  'a)ids  (b  'b)vds  Zeiqs (6)
load, B and J denote the damping ratio and inertia constant dt
respectively.
The motor drive system for the proposed control scheme e
diqs e e e
can be simplified as Fig. 1. In which, the outer-loop speed (a  'a)iqs  (b  'b)vqs  Zeids  bZeIF' (7)
dt
control is realized by PI controller, and inner current loops are
dominated by VSC, and power converter is with the vector Next, to propose the current controllers with the VSC
control scheme. In this paper, we only present the designs of scheme, we define the d- and q-axes current errors between
d- and q-axes current control by VSC to compensate the current commands and reference currents as follows:
parameter variations on the electrical circuit. Since the power
e * e *
conversion is realized by space vector PWM (SVPWM), and eids ids  ids , eiqs iqs  iqs (8)
the control voltages are directly from the eight discrete type
patterns, they are all switching type signals, the chattering * *
where ids and iqs are respectively the desired d-axis and
phenomenon on current loop would not be considered.
* *
q-axis currents. If ids and iqs are piecewise continuous
constants, the derivatives of (8) can be represented as
e deiqs e
deids dids diqs
, (9)
dt dt dt dt
By substituting (6) and (7) into (9), and with some
manipulations, one has the dynamic equations as (10) and
(11):
deids e
a eids  b vds Ed (10)
dt
deiqs
e (11)
a eiqs  b vqs  Eq
dt
Fig. 1.The block diagram of PMSM speed control system with VSC as the
* * e e
current controller. where Ed a ids  'a(eids  ids )  'bvds  Zeiqs and
* * e e
III. THE VARIABLE STRUCTURE CURRENT CONTROLLER Eq a iqs  'a(eiqs  iqs )  'bvqs  Zeids  bZeIF' . Ed and
DESIGN
Eq can be considered as the terms of disturbances in (10) and
The system (1) can be further rewritten as (11).
e
dids e e e Defining the variable structure current controllers as
aids  bvds  Zeiqs (4)
dt follows:
e
diqs e 1
e e e vds [a eids  qd sgn(eids )] (12)
aiqs  bvqs  b(Ze Ls ids  ZeI F' ) (5) b
dt
e 1
vds [a eiqs  qq sgn(eiqs )] (13)
b


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Fig. 2.The block diagram of PMSM current vector control.

where sgn(˜) is the sign function. The two parameters, qd
and qq , in (12) and (13) are positive real, and denoted by the
upper bound of Ed and Eq as
qd t Ed , q q t Eq
With the VSC control theorem, the control law (12) and (13)
would force the stator’s currents to be equal to the reference
ones.
IV. THE MODELLING AND SIMULATION OF PMSM DRIVE
SYSTEM
The system model created by Matlab/Simulink is shown in
Fig. 2, which includes the variable structure current controller,
the 3I / 2I conversion, the SVPWM block and the PMSM
model. The current-loop control structure is based on a
standard field oriented control. The compensation voltages
are from the errors of reference and feedback currents, and the
control voltages are determined through the variable structure
controller.
(14) Since the generated torque is proportional to the q-axis
e
current, we only demonstrate the response of iqs . To
*
complete the simulations, there are two types of iqs
commands used to verify the performance and accuracy. Fig.
3 is the simulated response with square waveform command,
the amplitude is 1 A and frequency is 100 Hz. And Fig. 4, the
command is a sinusoidal signal with amplitude being 1 A, and
the frequency is also 100 Hz. The two results are shown good
performance.

command command
response response
Current (A)

Current (A)

Time (second) Time (second)

Fig. 3.The current response with 100 Hz square waveform current command. Fig. 4.The current response with 100 Hz sinusoidal command.


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may make the system un-completely realized by one

V. DIGITAL MODEL AND SIMULATION
The FPGA realized system is one of the digital control
systems. In the platform of Matlab/Simulink, we first convert
the continuous system into digital form, and as shown in Fig.
5 where the inputs are the current commands of ids * *
and iqs ,
and the outputs are the six gate driver signals for inverter.
Furthermore, the designed hardware system also considers
the interfaces of feedback signals, they mainly include the
encoder counter with two-phase quadrature channels and the
three phase currents by A/D converter. And Fig. 6 is the
unfolded of VSC controllers as has shown in Fig. 5 with the
block name VSC. Afterwards, the developed control systems
are converted into Verilog HDL represented model. Note that,
the resulting hardware code must be checked and made some
or a lot of modifications since the hardware implementations
depend on the selected FPGA chip, some constraints such as
the amount of multiplier, gate count, and even the I/O pins
unsuitable chip.
Once the designers have made the software model system
into hardware code except the motor model, the resulting
Verilog HDL system could be applied to the Matlab/Simulink
system to make a co-simulation to verify the accuracy and
performance. The hardware system is set to work on 20 kHz
sampling frequency on the current control loop. The resulting
block diagram of the co-simulation system is shown in Fig. 7
where the hardware controller is the one located in the center.
The verification process includes two procedures. First, the
pure model system without the Verilog HDL code is
simulated, and its results have been proved in Figs. 3 and 4.
Second, the hardware controller which includes the current
vector control, the transformations of Park, inverse Park,
Clarke, inverse Clarke and the sine table are checked. Figs. 8
and 9 are the simulated results of hardware systems with iqs *
command as those shown in Figs. 3 and 4. The responses are
similar to the results of Figs. 3 and 4 simulated by pure
software system.

Fig. 5. The digital model of PMSM current vector control.

Fig. 6.The VSC module for current control.


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Fig. 7.The co-simulation system platform by ModelSim and Simulink.

IV. Conclusions
In this paper, we have designed a hardware current
controller for PMSM with the variable structure control
instead of the tradition PI controller, and realized by FPGA
with Verilog HDL code. The next work we are going to do is
hardware implementation by Altera FPGA to practically
realize the variable structure controller to complete the
overall system as full digital and full FPGA control. The
resulting hardware is expected to have low cost as compared
with the DSP based drive system.
command
response
Current (A)
Acknowledgement
This work is financial supported by the Ministry of Science
and Technology of Taiwan with grant no. MOST
104-2221-E-167-005.
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