1 36不行

**** Midterm: Two stage pipeline 8-bit FA ***
*************************************************************
*************************************************************
***************Don't touch settings below********************
*************************************************************
*************************************************************
.lib "umc018.l" L18U18V_TT
.vec 'FA8.vec'
.temp 25
.op
.options brief post
***************** parameter ****************************

.global VDD GND
.param supply = 1.8v
.param load = 10f
.param tr = 0.2n
***************** voltage source ****************************

Vclk CLK GND pulse(0 supply 0 0.1ns 0.1ns "1*period/2-tr" "period*1")
Vd1 VDD GND supply
***************** top-circuit ****************************

XFA CLK A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0]
+ B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] CIN
+ SUM[7] SUM[6] SUM[5] SUM[4] SUM[3] SUM[2] SUM[1] SUM[0] COUT FA8
C0 SUM[0] GND load

C1 SUM[1] GND load
C2 SUM[2] GND load
C3 SUM[3] GND load
C4 SUM[4] GND load
C5 SUM[5] GND load
C6 SUM[6] GND load
C7 SUM[7] GND load
C8 COUT GND load
***************** Average Power ****************************

.meas tran Iavg avg I(Vd1) from=0ns to='99*period'
.meas Pavg param='abs(Iavg)*supply'
.tran 0.1n '99*period'
*************************************************************
*************************************************************
***************Don't touch settings above********************
*************************************************************
*************************************************************
***** you can modify clock cycle here, remember synchronize with clock cycle in
FA8.vec ****
.param period = 1.66n
***** Define your sub-circuit and self-defined parameter here , and only need to
submmit this part ****
.subckt FA8 CLK A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] B[7] B[6] B[5] B[4] B[3]
B[2] B[1] B[0] CIN SUM[7] SUM[6] SUM[5] SUM[4] SUM[3] SUM[2] SUM[1] SUM[0] COUT
X1 A[0] A[1] A[2] A[3] B[0] B[1] B[2] B[3] CIN C4 S0 S1 S2 S3 FA4
XF1 S0 CLK SUM0 DFF
XF2 S1 CLK SUM1 DFF
XF3 S2 CLK SUM2 DFF
XF4 S3 CLK SUM3 DFF
XF5 C4 CLK CIN_C4 DFF
XF6 A[4] CLK A4 DFF
XF7 A[5] CLK A5 DFF
XF8 A[6] CLK A6 DFF
XF9 A[7] CLK A7 DFF
XF10 B[4] CLK B4 DFF
X2 A4 A5 A6 A7 B4 B5 B6 B7 CIN_C4 C8 S4 S5 S6 S7 FA4
XF01 SUM0 CLK SUM[0] DFF
XF05 S4 CLK SUM[4] DFF
XF09 C8 CLK COUT DFF
.ends
.subckt FA4 A[0] A[1] A[2] A[3] B[0] B[1] B[2] B[3] CIN COUT S0 S1 S2
S3
XP0 A[0] B[0] P0 XOR_2

XP1 A[1] B[1] P1 XOR_2
XP2 A[2] B[2] P2 XOR_2
XP3 A[3] B[3] P3 XOR_2
XG0 A[0] B[0] G0 AND_2
XG1 A[1] B[1] G1 AND_2
XG2 A[2] B[2] G2 AND_2
XG3 A[3] B[3] G3 AND_2
X1 P0 CIN A AND_2
X2 A G0 C1 OR_2
X3 P1 G0 B AND_2
X4 P1 P0 CIN C AND_3
X5 G1 B C C2 OR_3
X6 P2 G1 D AND_2
X7 P2 P1 G0 E AND_3
X8 P2 P1 P0 CIN F AND_4
X9 G2 D E F C3 OR_4
X10 P3 G2 G AND_2
X11 P3 P2 G1 H AND_3
X12 P3 P2 P1 G0 I AND_4
X13 P3 P2 P1 P0 CIN J AND_5
X14 G3 G H I J COUT OR_5
X15 P0 CIN S0 XOR_2

X16 P1 C1 S1 XOR_2
X17 P2 C2 S2 XOR_2
X18 P3 C3 S3 XOR_2
.ends
.subckt NOR_2 a b out
Mp1 out a node_1 VDD P_18_G2 l=0.18u w=0.48u
Mp2 node_1 b VDD VDD P_18_G2 l=0.18u w=0.48u
Mn1 out a GND GND N_18_G2 l=0.18u w=0.24u
Mn2 out b GND GND N_18_G2 l=0.18u w=0.24u
.ends
.subckt NOR_3 a b c out
Mp2 node_1 b node_2 VDD P_18_G2 l=0.18u w=0.48u
Mp3 node_2 c VDD VDD P_18_G2 l=0.18u w=0.48u
Mn3 out c GND GND N_18_G2 l=0.18u w=0.24u
.ends
.subckt NOR_4 a b c d out
Mp3 node_2 c node_3 VDD P_18_G2 l=0.18u w=0.48u
Mp4 node_3 d VDD VDD P_18_G2 l=0.18u w=0.48u
Mn4 out d GND GND N_18_G2 l=0.18u w=0.24u
.ends
.subckt NOR_5 a b c d e out
Mp4 node_3 d node_4 VDD P_18_G2 l=0.18u w=0.48u
Mp5 node_4 e VDD VDD P_18_G2 l=0.18u w=0.48u
Mn4 out d GND GND N_18_G2 l=0.18u w=0.24u
Mn5 out e GND GND N_18_G2 l=0.18u w=0.24u
.ends
.subckt NAND_2 a b out
Mp1 out a VDD VDD P_18_G2 l=0.18u w=0.48u
Mp2 out b VDD VDD P_18_G2 l=0.18u w=0.48u
Mn1 out a node_1 GND N_18_G2 l=0.18u w=0.24u
Mn2 node_1 b GND GND N_18_G2 l=0.18u w=0.24u
.ends
.subckt AND_2 a b out
Mp1 out_inv a VDD VDD P_18_G2 l=0.18u w=0.48u
Mp2 out_inv b VDD VDD P_18_G2 l=0.18u w=0.48u
Mn1 out_inv a node_1 GND N_18_G2 l=0.18u w=0.24u
X1 out_inv out inv
.ends
.subckt AND_3 a b c out
Mp3 out_inv c VDD VDD P_18_G2 l=0.18u w=0.48u
Mn2 node_1 b node_2 GND N_18_G2 l=0.18u w=0.24u
Mn3 node_2 c GND GND N_18_G2 l=0.18u w=0.24u
X1 out_inv out inv
.ends
.subckt AND_4 a b c d out
Mp4 out_inv d VDD VDD P_18_G2 l=0.18u w=0.48u
Mn3 node_2 c node_3 GND N_18_G2 l=0.18u w=0.24u
Mn4 node_3 d GND GND N_18_G2 l=0.18u w=0.24u
X1 out_inv out inv
.ends
.subckt AND_5 a b c d e out
Mp4 out_inv d VDD VDD P_18_G2 l=0.18u w=0.48u
Mp5 out_inv e VDD VDD P_18_G2 l=0.18u w=0.48u
Mn3 node_2 c node_3 GND N_18_G2 l=0.18u w=0.24u
Mn4 node_3 d node_4 GND N_18_G2 l=0.18u w=0.24u
Mn5 node_4 e GND GND N_18_G2 l=0.18u w=0.24u
X1 out_inv out inv
.ends
.subckt OR_2 a b out
Mp1 out_inv a node_1 VDD P_18_G2 l=0.18u w=0.48u
Mn1 out_inv a GND GND N_18_G2 l=0.18u w=0.24u
Mn2 out_inv b GND GND N_18_G2 l=0.18u w=0.24u
X1 out_inv out inv
.ends
.subckt OR_3 a b c out
Mp3 node_2 c VDD VDD P_18_G2 l=0.18u w=0.48u
Mn3 out_inv c GND GND N_18_G2 l=0.18u w=0.24u
X1 out_inv out inv
.ends
.subckt OR_4 a b c d out
Mp4 node_3 d VDD VDD P_18_G2 l=0.18u w=0.48u
Mn4 out_inv d GND GND N_18_G2 l=0.18u w=0.24u
X1 out_inv out inv
.ends
.subckt OR_5 a b c d e out
Mp4 node_3 d node_4 VDD P_18_G2 l=0.18u w=0.48u
Mp5 node_4 e VDD VDD P_18_G2 l=0.18u w=0.48u
Mn4 out_inv d GND GND N_18_G2 l=0.18u w=0.24u
Mn5 out_inv e GND GND N_18_G2 l=0.18u w=0.24u
X1 out_inv out inv
.ends
.subckt XOR_2 a b out
X1 a a_inv inv
X2 b b_inv inv
Mp1 node_1 a_inv VDD VDD P_18_G2 l=0.18u w=0.48u
Mp4 out_inv b_inv node_1 VDD P_18_G2 l=0.18u w=0.48u
Mn1 out_inv a_inv node_2 GND N_18_G2 l=0.18u w=0.24u
Mn4 node_3 b_inv GND GND N_18_G2 l=0.18u w=0.24u
X3 out_inv out inv
.ends
.subckt inv in out
Mp out in VDD VDD P_18_G2 l=0.18u w=0.48u
Mn out in GND GND N_18_G2 l=0.18u w=0.24u
.ends
.subckt tri_inv D Ctrl Q_inv
X1 Ctrl Ctrl_inv inv
Mp1 node1 D vdd vdd P_18_G2 w=0.48u l=0.18u
Mp2 Q_inv Ctrl_inv node1 vdd P_18_G2 w=0.48u l=0.18u
Mn1 Q_inv Ctrl node2 gnd N_18_G2 w=0.24u l=0.18u
Mn2 node2 D gnd gnd N_18_G2 w=0.24u l=0.18u
.ends
.subckt DFF D CLK Q
X1 CLK CLK_inv inv
X2 D D_inv inv
Mp1 X CLK D_inv vdd P_18_G2 w=0.48u l=0.18u
Mn1 D_inv CLK_inv X gnd N_18_G2 w=0.24u l=0.18u
X3 X X_inv inv
X4 X_inv CLK X tri_inv
Mp2 node1 CLK_inv X_inv vdd P_18_G2 w=0.48u l=0.18u
Mn2 X_inv CLK node1 gnd N_18_G2 w=0.24u l=0.18u
X5 node1 node2 inv
X6 node2 Q inv
X7 node2 CLK_inv node1 tri_inv
.ends
.meas tran tr_s trig v(sum[7]) val='supply*0.2' rise=1

+targ v(sum[7]) val='supply*0.8' rise=1
.meas tran tr_c trig v(cout) val='supply*0.2' rise=1
+targ v(cout) val='supply*0.8' rise=1
.end

1 36不行

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

1 36不行

Uploaded by

Copyright:

Available Formats

** Midterm: Two stage pipeline 8-bit FA *

* parameter ************

* voltage source ************

* top-circuit ************

C0 SUM[0] GND load

* Average Power ************

.tran 0.1n '99*period'

XP0 A[0] B[0] P0 XOR_2

X15 P0 CIN S0 XOR_2

.meas tran tr_s trig v(sum[7]) val='supply*0.2' rise=1

You might also like