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:2: ESE-2019 Mains Test Series

01. (a)
Sol: (i) The applied voltage V makes D1 – R.B & D2 – F.B

+ V1 – +
V2

D1 ID D2

V = 50 mV

ID = I0
 VV2 
But I D  Is e T  1  for D 2
 
  V1

 Is 1  e VT   for D1
 
 VV2    V1

 Is e  1  Is 1  e VT 
T

   
V2 V1

e VT
1  1 e VT

V2 V1

e eVT
2 VT

But V1 + V2 = 50 mV  V2 = 50 10-3 – V1
50103  V1 V1

e VT
e VT
2
V

 1 e 2 1 
e VT
2
V
 1
2
 e VT

 0.2384
e 1 2

  1 
V

Then, I D  IS 1  e 
VT

 
= IS [1 – 0.2384]
 ID = I0 = 0.7614 IS

(ii) When diodes are F.B,


+ V1 – + V2 –
V1 + V2 = 50 mV
 V1 = V2 = 25mV D1 D2
 VV1 
I D  IS e T  1 = Is [e1 – 1]
 
 ID = 1.71828 IS 50 mV

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:3: Electronics & Telecommunication Engineering
01. (b)
m
sin
Sol: Breadth factor, k b  2
m sin  / 2
180P
  slot angle 
S
180  16
  20 elect
144
144
Slots per pole per phase, m =  3 so,
16  3
3  20
sin
kb  2  0.96
20
3 sin
2
1440
E L  3  4.44  k b fN ph  3  4.44  0.96  0.04  50  = 3544V.
23

01. (c)
Sol: Properties and requirements of good insulating materials:
The requirement of good insulating materials can be classified as electrical, mechanical, thermal
and chemical.
1. Electrical properties:
 Electrically, the insulating material should have high resistivity to reduce the leakage current
and high dielectric strength to enable it to withstand higher voltage without being punctures
or broken down.
 Further, the insulator should have small dielectric loss.
2. Mechanical properties:
 Since the insulators are used on the basis of volume and not weight, a low density is
preferred.
 The insulators should also have small thermal expansion to prevent mechanical damage.
 Further, it should be non-ignitable, or if ignitable, it should be self extinguishable.

3. Thermal properties:
 A uniform viscosity for liquid insulators ensures uniform thermal and electrical properties.
 Liquid and gaseous insulators are used also used as coolants. For example, transformer oil,
hydrogen and helium are used both for insulation and cooling purposes. For such materials,
good thermal conductivity is a desirable property.

4. Chemical properties:
 Chemically, the insulators should be resistant to oil, liquids, gas fumes, acids and alkalies.
 It should not deteriorate by the action of chemicals in soils or by contact with other metals.
 The insulator should not absorb water particles, since water lowers the insulation resistance
and the dielectric strength.
 Insulating materials should have certain mechanical properties depending on the use to
which they are put. Thus when used for electric machine insulation, the insulator should
have sufficient mechanical strength to withstand vibration. Good heat conducting property is
also desirable in such cases.
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:4: ESE-2019 Mains Test Series
 Materials with large electronic and ionic polarizabilities and therefore large permittivity are
used for making dielectric capacitors. Titanium oxide which has a permittivity of about 100
is a good example of such a material.
 The use of molecules with a permanent dipole moment is not desirable because of the
possibility of large dielectric losses at high frequencies.

01. (d)
Sol: V(t )  V()  [V(0)  V()]e t / 
V(0) = 0V
 3k 
V()  5   3V
 5k 
  R eq .C
6
R eq  2k // 3k  k
5
6
T  k  5nF  6 sec
5
V(t )  3[1  e t / 6 ]
V ( t  6)
V(t )  3[1  e1 ]  3[1  0.367]  1.896Volts

01. (e)
Sol: VGS = IS RS  ID RS (∵ IG  0)
2
ID = IDSS (1 – VGS/VP)
Substitute the values in above equation,
VGS = 4RS
4 = 12 (1 – 4 RS/4)2
On solving we get,
RS = 1.58K or 0.42K
Using, RS = 0.42K , KVL for DS loop
–12 – 6 + (RD + RS) ID = 0
With RS = 0.42K , RD = 4.08L
 RD = 4.08K
RS = 0.42K

01. (f)
Sol:
f
CD
AB
1 1 1 
AD
1  1

f  A D  BD
1 1

BD
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:5: Electronics & Telecommunication Engineering

F  A D  BD

F  AD BD

A
AD
D
F  A D BD  A D  BD

B BD

02. (a)
Sol:
(i) Given:
Armature resistance (ra) = 0.6 
Field resistance (rsh) = 231 
Terminal voltage (Vt) = 230 V

Motoring: Generating:

Ia=30A IL=31A Ia=30A IL=29A

ra=0.6  rsh=230  ra=0.6  rsh=230 


Vt= 230V Vt= 230V
M Ish= 1A G Ish= 1A

Line current Il = 31 A Line current Il = 29 A


V V
Ish = t Ish = t
rsh rsh
230 230
= =1A = =1
230 230
Ia = Il  Ish = 31  1 = 30 A Ia = Il + Ish = 29 + 1 = 30 A
Eb1 = Vt – Ia ra = 230 30  0.6 Eb2 = Vt + Ia  ra = 230 + 30  0.6
Eb1 = 212 V Eb2 = 248 V
Change in back emf, Eb2 Eb1 = 36 V increase.

(ii) For lap wound output current


P 100  1000
=   400A
V 250
NZ P N
E  250 V    280 
60 A 60
N 250
Or 
60 280
For wave wound, number of Parallel paths = 2
Therefore, current rating = conductor current  2
= 1002 = 200A
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:6: ESE-2019 Mains Test Series

 N  P 250 4
Voltage rating =   Z   280 
 60  A 280 2
= 500V
Power rating = 500  200 = 100kW

02. (b)
Sol:
(i) Methods to reduce the ratio error of current transformer:
1. Leakage reactance increases ratio error.
 Two windings primary and secondary should be close together to reduce the winding
leakage reactance.
Ex: use of ring shaped cores around which toroidal windings are uniformly distributed.
2. For a particular value of current and burden impedance, ratio error is corrected by reducing
the secondary windings turns. This type of current transformer is called compensated current
transformer.
3. For a particular value of current and burden, with the use of shunts across primary or
secondary windings, the secondary winding current is reduced and ratio error is corrected.
4. Wilson compensation method
5. Two stage design. It utilises a second current transformer to correct the error in secondary
current of first transformer.
6. By using materials of high permeability like Nickel iron cores, ratio errors are reduced.

(ii) Reactance of pressure coil circuit = 2 × 50 ×10 ×10-3 = 3.14


Resistance of pressure coil circuit = 362
Phase angle of pressure coil circuit
 = tan–1 3.14/362  30
Phase angle of current transformer  = +90
Phase angle of potential transformer  = –45
Phase angle of load = 50
Phase angle between pressure coil current Ip and a current Is of wattmeter current coil is
 =  –  –  –  = 50 – 90 – 30 – 45 = 4715
Correction factor
cos cos 50
K= = = 0.947
cos  cos cos 30  cos 4715 Vs reversed I reversed s

 Percentage ratio error


V  
I
K R 
= n  100
R
 Actual ratio 
K n  100 
R= Is Vs
100  percentage error ratio
20 100 Ip
Actual ratio of C.T. = = 20.04
100  0.2
Phasor diagram
100 100
Actual ratio of P.T = = 99.2
100  0.8
Power = K × Actual ratio of P.T × Actual ratio of C.T × Wattmeter reading
 Power of load = 0.947×20.04×99.2×350×10-3 = 658.9kW
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:7: Electronics & Telecommunication Engineering
02. (c)
Sol: 10 Ω I
V 100V
(i)

5A R 20 Ω + 100V

V V  100
5   0    1
R 10
100  V 100
  I  0 ----(2)
10 20
5V = 100 I ----(3)
Solve these three equations
We can get
V = 100, I = 5A
Sub eq (1)
100 100  100
5  0
R 10
R = 20 
0.1i0
(ii) Isc

Isc+0.1io
+
10 V0

Isc–0.9io +
 1V
Isc–io i0
40 20

+ –
2V0
KVL to Loop ➀
20i0 – 2V0 – 40 (Isc – ic) = 0
20i0 – 2V0 – 40Isc + 40 i0 = 0
40Isc = 60i0 – 2V0
6 1
Isc = i 0  V0 .......... (1)
4 20
V0 + 20i0 = 1 ......... (2)
V0 = 10 (Isc + 0.1i0)
V0 = 10Isc + i0 ..........(3)
Solving (1) ,(2) and (3) we get
Isc = 0.03152 A
i0 = 0.0326 A
V0 = 0.3478 V
1
Rth =
I sc
Rth = 31. 72 
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:8: ESE-2019 Mains Test Series
03. (a)
Sol: IE = IB + IL
IL = IC = IB
I
I B  L  .02mA

I E  2  .02mA  2.02mA
For Q2: KVL
12 = VEB2 + VZ + VR1
VR1 = 12 – VEB2 – VZ
= 12 – .7 – 4 = 7.3V
hence,
VR 1 7.3
R1    1.45 k
I Z  IB (0.02  5)  103
VR 2 = Voltage drop across RL
= VEB2 + VZ – VEB1
= 4V
4
R2   1.98k
2.02mA
Voltage drop across Base-to-collector of Q1 (from KVL)
VBC = 12 – VR2 – VEB1 – ILRL
= 12 – 4 – .7 – ILRL
= 7.3 – (2RL)10-3
For Q1 to be in active Region VBC should be +Ve means.
7.3  (2RL)10-3
or 2RL  7.3
or RL  3.65 k
hence
0  RL  3.65 k

03. (b)
Sol: The peak voltage, Vp, is,
Vp = VCC – VCE(sat) = 20 – 0.3
Or, Vp = 19.7V
The ac power Po, is

Po 
Vp2

19.7 2
2R L 2 100
or, Po = 1.94 W
and, dc power drawn by the circuit is,
Pdc = VCC  Idc
Where,
P 1.94 W
I dc  o   0.0985 A
Vp 19.7V
Therefore,
Pdc = 200.0985
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:9: Electronics & Telecommunication Engineering
Pdc = 1.97 W
and the efficiency, , is
P 1.94 W
 o   100  98.5%
Pdc 1.97 W
Now, we proceed to find out the conductance angle .
For the frequency of 3MHz, the period of the wave, T, is
1
T  0.33s
3  106
And transistor's on - time is,
P T
t o
I p  Vp

1.94  0.33 10 6



500 10 3 19.7
or, t = 64.99 10–9 s
or, t = 64.99 ns
and, the conduction angle, , is
t 64.99 10 9
  360   360
T 0.33 10 6
or,  = 70.9o

03.(c)
Sol:
(i) (1) It is a 8-bit microprocessor.
(2) It is manufactured with NMOS technology.
(3) It has 16-bit address bus and hence can address 216 = 65536 bytes (64 KB) memory locations
through A15 - A0.
(4) The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 - AD7.
(5) Data bus is a group of 8 lines D0 - D7.
(6) It supports external interrupt request.
(7) A 16-bit program counter (PC).
(8) A 16-bit stack pointer (SP).
(9) Six 8-bit general purpose register arranged in pairs BC, DE, HL.
(10) It requires a signal +5V power supply and operates at 3.2MHz single phase clock.
(11) It is enclosed with 40 pins DIP [Dual-Inline-Package]

(ii) Registers:
(1) Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store
operations.
(2) Flag register has five 1-bit flags.
(3) Sign-set if the most significant bit of the result is set.
(4) Zero-set if the result is zero.
(5) Auxiliary carry-set if there was a carry out from bit 3 to bit 4 of the result.
(6) Parity-set if the parity (number of set bits in the result) is even.
(7) Carry-set if there was a carry during addition, or borrow during subtraction/comparison.
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: 10 : ESE-2019 Mains Test Series
General Registers:
(1) 8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a pair
the C register contains low-order byte. Some instructions may use BC as a data pointer.
(2) 8-bit D and 8-bit E register can be used as one 16-bit DE register pair. When used as a pair
the E register contains lower-order byte.
(3) 8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. HL register usually
contains a data pointer used to reference memory addresses.
(4) Stack pointer is a 16-bit register. This register is always decremented or incremented during
push and pop operations.
(5) Program counter is 16-bit register, which holds the address of the next instruction to be
executed.

04. (a)
Sol: Ammeter-X:
Rm = 1.2, Im = 150 mA ; I = 20 A
R Rm
Rsh  m 
m 1  I 
  1
 Im 
1.2
= = 9.068  10 3 
20
1
150 10 3
20 A 150 mA 1.2

9.068 m

Ammeter-Y:
Rm = 1.5 , Im = 250 mA
I = 20 A
R Rm 1.5
RSh  m  = = 0.0254 
m 1  I  20
  1 1
 Im  250 10 3

Two Ammeters are in parallel

X-Ammeter
1.2 

20 A 9.068m 

Y-Ammeter

1.5 

0.0254 

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: 11 : Electronics & Telecommunication Engineering

 1.2  9.068  10 3 
 

 1.2  9.068  10 3
 
IY
20A Ix Ix 8.99 10-3

20 Iy
 1.5  0.0254 
  0.249 
 1.5  0.0254 

0.249
I x  20   19.303

0.249  8.99 10 3 
3
8.99 10
Iy = 20  0.6969
8.99 10 3  0.249

04. (b)
Sol:
(i) When both switches are closed
9  0.7
IB   33.2A
250k
IC = IB = 3.32 mA
9  0.2
IC(sat)   5.86mA
1.5K
I B  I c(sat )  Active region
VCE = 9 – 1.5  3.32 = 4.02 volt
Operating point (4 volt, 3.3 mA) and transistor is in Active Region.

(ii) When S1 is closed, S2 is open


9  .7
IB   .0223 mA
(250  101  1.2)  103
IB = IC  2.23 mA
9  0.2
IC(sat)   3.26mA
2.7K
I B  I c(sat )  Active region

VCE  9 – 2.23  2.7 = 2.962 V


Operating point (2.962 V, 2.23 mA) and the transistor is in Active Region.

(iii) When both S1 and S2 are open


IB = 0 = IC Cut-off region.

04. (c)
Sol:
(i) Factors affecting resistivity:
(1) Temperature: The electrical resistance of most metals increases with increase of
temperature while those of semiconductors and electrolytes decreases with increase of
temperature.
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: 12 : ESE-2019 Mains Test Series
(2) Alloying: A solid solution has a less regular structure than a pure metal. Consequently, the
electrical conductivity of a solid solution alloy drops off rapidly with increased alloy content.
In other words, the addition of small amounts of impurities leads to a considerable increase in
resistivity.
 The temperature coefficient of metals is very small. Therefore, increase in resistivity due to
the addition of impurities is temperature independent. This suggests the existence of alloys,
whose resistance varies little with temperature.
 The resistivity may be said to be consists of two parts; one part is resistance at absolute zero
of temperature, and another part, which arises from crystal imperfections and this part
would be zero only in undistorted crystals.
 The residual resistance of alloys is obtained by extrapolating the temperature resistance
curves to absolute zero, therefore, is quite appreciable. Further, different atoms dissolved in
a given solvent metal, affect the resistivity in different ways, which is largely dependent
upon the balance of the solvent and solute atoms.
(3) Cold Work: Mechanical distortion of the crystal structure decreases the conductivity of a
metal because the localized strains interfere with electron movement. Thus, hard drawn
copper wire has a lower conductivity than annealed copper. Subsequent annealing restores the
electrical conductivity by establishing greater regularity in the crystal lattice.

(4) Age Hardening: Age hardening increases the resistivity of an alloy.


(ii) Given data;
L = 1 cm = 110–2m
A = 10–3 10–3 = 10–6 m2
ni = 2.51019/m3
e = 0.39m2V–1s–1
p = 0.19m2V–1s–1
1 1 10 2 10 2  106
  =4.31103 
A n i e p   e A 2.5  1019  1.6  10 19 0.39  0.19  2.5  0.58  1.6
Resistance R= 

04. (d)
Sol:
(i) FA, B, C, D, E  A  DE

DE
A B C D E A B C D E
1 0 0 0 0 0 0 0 1 0
1 0 0 0 1 0 0 1 1 0
16
1 0 0 1 0 . . 8 minterms.
minterms
. . . .
1 1 1 1 1 1 1 1 1 0

A B C D E
1 0 0 1 0 4 common
1 0 1 1 0 minterms
1 1 0 1 0
1 1 1 1 0
So, the number of non-redundant minterms = 16 + 8 – 4 = 20
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: 13 : Electronics & Telecommunication Engineering
(ii) F2 must have m(1, 4, 6) and it may (or) may not have the minterms m(2,3,7,9,11,12,13,14)
0000 0 0 0 0
0000 0 0 0 0

1111 1 1 1 1

So, number of possible functions for F2 is 28 = 256.

05. (a)
Sol:
(i) Induced emf/ph
Eph = (Vph cos   I a R a ) 2  (Vph sin   I a x s ) 2
+  Lag, –  Lead
6.6 103
Vph= = 3810.5 V
3
cos   1, sin   0, Ra  0
1000 103
Ia ph = Ia L-L = =87.477A
3  6.6 103
E ph  (3810 .5 1  0) 2  (3810 .5  0  87.477  20) 2 = 4192.9V
EL-L = 3 E ph  7262 .3 V
= 7.26 kV
(ii) Eph = Vph + jIaxs
= 3810.5 + j87.477 × 20
= 4192.924.60
   24.6 0

05. (b)
Sol: As given Wheatstone bridge is shown below

pR
R(1+x)
+
V0

pR R

+ –

The value of output voltage


 R 1  x  R 
V0  E   
 pR  R 1  x  pR  R 
 1 x 1 
= E  
 p  1  x  1  p 
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: 14 : ESE-2019 Mains Test Series
dV0
For getting the max value of output voltage, 0
dp
dV0   1  x  1 
  E  2
0
 p  1  x  (1  p) 
2
dp
 1 1 x 
 E  2
0
 1  p 2
p  1  x  
1 1 x
 
1  p 2 p  1  x  2
 [p + (1+x)]2 = (1+x)(1+p)2
 p2+(1+x)2 + 2p(1+x) = (1+x) [1+p2 +2p]
= (1+x) + p2 (1+x) + 2p(1+x)
 p2[1+x–1] = (1+x)2 – (1+x)
 p2x = 1 + x2 + 2x – 1 – x
 p2x = x2+x
 p2 = 1+x
p  1 x

05. (c)
Sol: The operating point current and voltages in the circuit are:
| V | 10V
I CQ  I E  EE   1A
RE 10
And,
VCEQ = VCC = 10V
Therefore, maximum ac output power is,
VCEQ.I CQ 10 1
Po max     5W
2 2
To calculate the efficiency, , the dc power drawn by collector-emitter circuit is,
PDC | VCC |  | VEE | I CQ
= (10 + 10)1 = 20W
Therefore efficiency,
Pomax  5W
  100
PDC 20 W
Or  = 25%

05. (d)
Sol: The state diagram is shown below.
1 encoding:
0 S0 0 S1 0
0 So : 00
S1 : 01
0 1 0 1 S2 : 10
S3 : 11

S3 1 S2 0
1

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: 15 : Electronics & Telecommunication Engineering
State table:-

Present State input Next state Output


A B x A+ B+ Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 0 0 1

A   ABx  ABx  AB  ABx


B  A Bx  ABx  Bx
y  AB x  ABx  AB

Implementation using D flip - flops:


DA  A   AB  ABx  A  Bx
DB  B  Bx; output , y  AB

DA QA
x y
QA

x DB QB

CLK QB

05. (e)
Sol: Other
Reactants
Heated Scrapper

Condensation
Reaction Clusters

Heated

Cold
Vapour Finger
Carrier
gas
Precursor Particle
collection

Inductive of
Resistive
Heating

Schematic of a typical chemical vapour deposition reactor

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: 16 : ESE-2019 Mains Test Series
Chemical vapour deposition method nano particles are deposited from gas phase. Material is
heated to form a gas and then allowed to deposit on a solid surface, usually under high vacuum. In
deposition by chemical reaction new produce is formed. Nano powders of oxidises 2nd carbides of
metals can be formed of vapours of carbon or oxygen are present with the metal.
It involves pyrolysis of vapours of metal organic precursors in a reduced precursors atmosphere in
the simplest form shown in figure, a metal-organic precursor is introduced into the hot zone of the
reactor using mass flow controller. The precursor is vaporized either by resistive or inductive
heating. The carrier gas such as Ar or Ne carries the hot atoms to the reaction chamber. The hot
atoms collide with cold atoms and undergo condensation through nucleation and form small
clusters. In side reaction chamber other reactants are added to control the reaction rate. Then these
clusters are allowed to condense on moving belt arrangement with scrapper to collect the nano-
particles. The particle size could be controlled by rate of evaporation (energy input), rate of
cluster formation (energy removal rate) and rate of condensation (cluster removal from the
reaction chamber).
CVD method of synthesis of nano particles has many advantages.
1. The increased yield of nanoparticles
2. A wider range of ceramics including nitrides and carbides can be synthesised.
3. More complex oxides such as BaTiO3 or composite structures can be formed
4. In addition to the formation of single phase nano particles by CVC of a single precursor the
reactor allows the synthesis of
(a) Mixtures of nano particles of two phases or doped nano particles by supplying two precursors
at the front end of the reactor, and
(b) Coated nano particles, i.e., n-ZrO2 coated with n-Al2O3 or vice versa, by supplying a second
precursor at a second stage of the reactor.

06. (a)
Sol:
(i) Given F(A,B,C,D) = m(0,1,3,4,8,9,15)

A B C A BC AB C ABC AB C A B C AB C ABC
D 0 2 4 6 8 10 12 14

D 1 3 5 7 9 11 13 15
Io = 1 I1 = D I 2  D I3 = 0 I4 = 1 I5 = 0 I6 = 0 I7 = 0

1 I0
D I1
D I2
0 I3 81 F
1 I4 MUX
0 I5
0 I6
D I7
S2 S1 S0

A B C

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: 17 : Electronics & Telecommunication Engineering
256k
(ii) (A)  8 chips
32k
(B) 256k = 218
 18 address lines for memory
32k = 215
 15 address lines/chip
(C) For 256k, 18 address lines are required
For 32k, 15 address lines are required
 (18 – 15) = 3 address lines.
So, a 3  8 decoder is used.

(iii) Random Access Memory:


A memory unit is a collection of storage cells together with associated circuits needed to transfer
information in and out of the device. The time it takes to transfer to or from any desired random
location is always the same, hence the name Random-Access memory abbreviated as RAM. The
Capacity of a memory unit is usually stated as the total number of bytes that it can store.
The communication between a memory and its environment is achieved through data input and
output lines, address selection lines, and control lines that specify the direction of transfer. The
block diagram of the memory unit is shown below.
n data input lines

K address Memory unit


lines
Read 2k words

Write N bit per word

n data output lines

The n data input lines provide the information to be stored in memory and the n data output lines
supply the information coming out of memory. The K address lines specify the particular word
chosen among the many available. The write input causes binary data to be transferred into the
memory, and the read input causes binary data to be transferred out of memory.
The memory unit is specified by the number of words it contains and the number of bits in each
word. The address lines select one particular word. Each word in memory is assigned an
identification number, called an address, starting from 0 upto 2k – 1, where K is the number of
address lines. A decoder accepts this address and opens the paths needed to select the word
specified. Memories vary greatly in size and may range from 1024 words, requiring an address of
10 bits to 232 words, requiring 32 address bits.
Consider for example, the memory unit with a capacity of 1k words of 16 bits each since 1K =
1024 = 210 and 16 bits constitute two bytes, we can say that the memory can accommodate 2048 =
2k bytes.

06. (b)
 E 
Sol: n i  CT3 / 2 exp  g 
 2kT 
 2 mk 
3/ 2

Where C = 2  
 h 
2

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: 18 : ESE-2019 Mains Test Series
Conductivity   n i ee   h 
3/ 2
 2  22  9.109  10 31  1.38  10  23 
C  2 

 
7 x 6.626  10 34
2
 

/ 2
 554 .098  10  54 
 2 
 68 
 307 . 327  10 
= 2 (1.7997  10 ) 14 3/2

= 2 2.414  1021
C = 4.829  1021

Taking T = 300K
2 1.38 10 23  300
2kT 
1.6 10 19
= 0.052eV
 E 
n i  CT3 / 2 exp  g 
 2kT 
  1.1 
= 4.829  1021 3003/2 exp  
 0.052 
= 4.829  1021 3003/2 6.50110–10
ni =163124.5  1011/m3
i = nie(e+h)
= 163124.5  10111.610-19 0.493
= 128672.6108
i = 1.28710–3–1m–1

06. (c)
Sol:
(i) A 20-V peak signal across a 16 -  load provides a peak load current of,
V 20V
I LP   L P    1.25A.
RL 16
The dc value of the current drawn from the power supply is then
Idc  .I LP   1.25A  0.796A.
2 2
 
And the input power delivered by the supply voltage is
Pi(dc) = Vcc.Idc = (30V) (0.796A) = 23.9Watts.

The output power delivered to the load is


V 2 LP  20V 
2
Po ( ac)    12.5Watts.
2R L 216
P
 efficiency   %  o ac 100%
Po dc
12.5W
 100%
23.9W
= 52.3%
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: 19 : Electronics & Telecommunication Engineering
(ii) The distortion, DFB in an amplifier with feedback and distortion, D without feedback in the
amplifier are related as,
D
D FB 
1  AB
Where A is open loop gain of amplifier and B is the gain of feedback network.
Now, D  10% 
10
given 
100
and DFB  1% 
1
given 
100
Therefore, using above equation,
1 1

10 1  AB
Or, (1 + AB) = 10
A A
Now, A FB  
1  AB 10
Or, A = 10 AFB = 10120 (∵AFB = 120)
Or, A = 1200

06. (d)
Sol: Let u = R2 = 1002 = 10,000
2R
Percentage error in u   2  5  10%
R
Let v  2 L2  2  50  22  394,784
2

2L
Percentage error in v   2 10  20%
L
Let x  u  v  R 2  2 L2
 100   2  50   22  404,784
2 2

u u v v
Uncertainity in x  .  .
x u x v
 10,000 394,784 
 10   20
 404,784 404,784 
= 0.24+19.5 = 19.74%
Now Z = x1/2
Z 1 x 1
So Z   2 x   2 19.74 = 9.873%

07. (a)
Sol: Advantages:
The main function of a transducer is to respond only for the measurement under specified limits
for which it is designed. It is, therefore, necessary to know the relationship between the input and
output quantities and it should be fixed. Transducers should meet the following basic
requirements.

1. Ruggedness: It should be capable of withstanding overload and some safety arrangement


should be provided overload protection.
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: 20 : ESE-2019 Mains Test Series
2. Linearity: It input-output characteristics should linear and it should produce these
characteristics in symmetrical way.
3. Repeatability: It should reproduce same output signal when the same input signal is applied
again and gain under fixed environmental conditions e.g., temperature, pressure humidity etc.
4. High output signal quality: The quality of output signal should be good i.e., the ratio of the
signal to the noise should be high and the amplitude of the output signal should be enough.
5. High reliability and stability: It should give minimum error in measurement for temperature
variations, vibrations and other various changes in surroundings.
6. Good dynamic response: Its output should be faithful to input when taken as a function of
time. The effect is analyzed as the frequency response.
7. No hysteresis: It should not give any hysteresis during measurement while input signal is
varied from its low value to high value and vice-versa.
8. Residual deformation: There should be no deformation on removal of input signal after
period of application.

Applications:
Parameter Applications
Resistance
i. Potentiometer device Pressure, displacement
ii. Resistance strain gauge Force, torque, displacement.
iii. Resistance thermometer Temperature, radiant heat
iv. Thermistor Temperature, flow
v. Photoconductive cell Photosensitive relay.
Capacitance
i. Variable capacitance Displacement, pressure.
ii. Capacitor microphone Speech, music, noise.
iii. Dielectric gauge Liquid level, thickness.
Inductance
i. Magnetic circuit transducer Pressure, force, displacement,
ii. Differential transformer. Pressure, displacement, position.
iii. Eddy current gauge Displacement, thickness.
Voltage and Current
i. Hall effect pickup Magnetic flux, current, power.
ii. Ionization chamber Particle counting, radiation.
Self Generating Transducers
i. Thermocouple and thermopile Temperature, heat flow,
radiation.
ii. Moving coil generator Velocity, vibrations.
iii. Piezoelectric pickup Sound, vibrations, acceleration,
pressure changes.

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: 21 : Electronics & Telecommunication Engineering
07. (b)
Sol: Given data:
Im = 0.0021 mA at 5 K, TC = 7.18 K,
H0 = 6.510–4
  T 2 
Hc = HC(0) 1    
  TC  
Tc = 7.18 K ; T = 5.0 K
H0 = 6.5 × 10–4
  5 2 
HC = 6.5 × 10–4 1   7.18  
 
= 6.5 × 10–4 × 0.5
= 3.3 × 10–4
Im = 2r HC
0.0021 × 10–3 = 2r × 3.3 × 10–4
0.0021 10 3
r=
2  3.3 10 4
r = 1.012 × 10–3
Diameter of the wire is D = 2r
= 2 × 1.012 × 10–3
= 2.024 × 10–3m

07. (c)
Sol:
(i) Starting torque Test = 1.5 full load torque (TfL)
Maximum torque Tem = 2.5 Tfl
T 2
As we know, e.st 
Te.m s mt  1
1 s mt
1.5 2  s mt
 
2.5 s 2mt  1
s 2mt  3.33s mt  1  0
3.33  3.33 2  4
smt = = 0.333, 2.996
2
In motoring mode, slip range is 0 to 1.
smt = 0.333

(ii) Isc = 6 IfL


2
Te..st I 
 x 2  sc   s fL
Te.fL  I fL 
1 = x2 (6)2  0.05
x = 0.745
Ist = x2Isc
= (0.745)2(6IfL)
= 3.33 IfL
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: 22 : ESE-2019 Mains Test Series
07. (d)
Sol: At t = 0–
2H 2

6

4A
0.02F 14

+ 12V

Vc(t)
Inductor is short circuited
6
IL(0–) at steady state  4   3A
8
Vc(0–) = 0V
At t = 0+
2s 6V 14
–+
IL(s) 1/0.02s +– 12/s
(1)
4
6 iL 
s

4/s
Apply KVL in loop (1)
 1  12  4
6   2s   14 i L   (6) i L    0
 0.02s  s  s
12 24  50 
6   i L 14  2s   6
s s  s 
6s  12
s

 i L 20s  2s 2  50 
6(s  2) 3(s  2)
I L (s)  2  2
2s  20s  50 s  10s  25
3(s  2)

(s  5) 2
3(s  5  3)
iL 
(s  5) 2
3 9
= 
(s  5) (s  5) 2

iL(t) = 3e–5t – 9te–5t = (3 – 9t)e–5tA


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: 23 : Electronics & Telecommunication Engineering
08. (a)
Sol:
(i) All crystalline materials contain defects in some form or other. The nature and effects of such
defects are very important in understanding the properties of materials. Technically important
properties such as mechanical strength, ductility, electrical conduction in semiconductors are
influenced by the defects. such effects of crystal imperfections are as given.
(1) Electrical Properties:
1. When a pure semiconductor is doped with pentavalent or trivalent impurities it results in
extrinsic semiconductors. In such semiconductors electrical conductivity increases with
doping concentration.
2. In the case of metals, the presence of impurity decreases the electrical conductivity.
3. Imperfections account for dielectric strength of a material. Even a micro void present reduces
the dielectric strength drastically.

(2) Optical properties


1. The presence of impurity atoms in the crystal lattice results in characteristic colours to the
crystals. These are called colour centres.
2. When aluminium oxide is doped with chromium atoms, we get ruby which is a very active
laser medium. Many solid state lasers are prepared by proper doping only.

(3) Mechanical properties


The mechanical properties of metals are usually controlled by imperfections.
1. Plastic deformation is mainly due to motion of edge dislocation. By reducing the mobility of
dislocations, the mechanical strength may be enhanced. Restricting or hindering dislocation
motion renders a material harder and stronger.
2. Copper added to gold increases the ductility of gold so that it can be drawn into wires.
3. The presence of carbon atoms as interstitial impurity in iron lattice increases the strength of
iron
4. Tin as substitutional impurity in copper lattice increases the bearing properties of copper.
5. Further imperfections account for creep yield strength, fracture strength, oxidation and
corrosion characteristics.

(ii) a = 2.9A = 2.910–8 cm


Atomic weight (A) = 55.85
Avogadro's number (NA) = 6.0231023 g/mole
Density () = 7.87 g/cc
nA

AN  Vvc
7.87  6.023  10 23  2.9  10 8 
3
  AN  Vvc
n = = 2.069
A 55.85
(iii) Given data;
 = 0.58A
 = 9.5
a
d
h  k 2  2
2

a a
d 200    0.5a
22  02  02 2
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: 24 : ESE-2019 Mains Test Series
From Bragg’s law
2d sin = n
2d200 sin(9.5) = 10.58
20.5 a 0.165 = 0.58
a = 0.52 A

08. (b)
Sol:
(i) Here Y-Parameter of the two-port network is parallel with 1 resistor, so the Y-parameters for
the whole network is the summation of individual Y-parameters of network
Y = Y1 + Y2
 1  1 5 2
Y1    Y2   
 1 1  1 3
 1  1 5 2
Y = Y1 +Y2 =  + 
 1 1  1 3
6 1
Y 
0 4
(ii)
1 I1 1 4
I1 I2
+
+ +
V1 2 V1 +
 2I2
+
 3I1 V2

– – –

V1
Z12  I1  0
I2

V1  V1  2I1  1 I1  2I2


  3I1  2I2

2 2 4
I1  I2 V1  2  I2  I2
3 3 3
V1 = Z11 I1 + Z12I2
V2 = Z21I1 + Z22I2
 V1   Z11 Z12 
V    Z Z 22 
 2   21
4
 Z12  
3

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: 25 : Electronics & Telecommunication Engineering
08. (c)
Sol:
(i) The core loss is
Pc  K h fBmx  K ef 2 B2m

For constant flux density Pc = C1 f + C2f2 (C1 = Kh Bmx , C2 = Ke B2m )


At 40 Hz: 52 = 40 C1 + 402 C2 and
At 60 Hz: 90 = 60 C1 + 602 C2
Or
52 = 40 C1 + 1600 C2
90 = 60 C1 +3600 C2
9 1
By solving above two equations we get, C1  and C2 =
10 100
Thus at 50 Hz
9
Ph  C1f   50  45 Watts
10

 50  25Watts
1
Pe  C2f 2 
2

100
The core loss at 50 Hz = 45 + 25 = 70 Watts

(ii) For mmf balance,


I1 T1
For transformer T1  I1  3 = I21  1
For transformer T2  I1  2 = I22  1 I21
100V I2
KCL at node A gives 3:1
50Hz
2:1 I22
I2 = I21 + I22 = 3I1 + 2I1 = 5I1 R
1
And secondary output voltage V2 =  40  20 V
2 T2

V2
Secondary load current, I2 =  2A  5 I1
R
2
I1 =  0.4 A
5

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