In general, AES encryption and decryption module has been implemented either combined

crypto processor or separate core processor base on the application. In light weight and compact size,
it uses the combined crypto processor. There are many methods has been proposed to implement sub
functions of AES SBOX, Add round Key, Mix column and Key expansion unit that achieves the low
power, less area and high throughput. It can be categorized by architecture model, and function
implementation methods.
Especially function implementation, memory based architecture designs need less design
time and minimum complexity compared to other design structures. However, it uses a simple design
style that occupies more area, consumes high power and requires more access time. The authors
(Good & Benaissa, 2005), (Tillich, Feldhofer, & Großschädl, 2006), (Fischer & Drutarovský, 2001) had
discussed in detail about the memory based design. The various memory based designs; LUT had
been discussed by (Farhan, Khan, & Jamal, 2004), (Hamalainen, Hannikainen, & Hamalainen, 2005)
(Good & Benaissa, 2005), (Verbauwhede, Schaumont, & Kuo, 2003), (Hodjat & Verbauwhede, A 21.54
Gbits/s fully pipelined AES processor on FPGA, 2004) and embedded design by (Rejeb, Kaginele, & Lee,
2006) . Various optimizing methods of power, area and speed had been discussed in (Farhan, Khan, &
Jamal, 2004), (Hamalainen, Hannikainen, & Hamalainen, 2005) (Good & Benaissa, 2005) (Rejeb,
Kaginele, & Lee, 2006).
Secondly, combinational circuit designs also used to achieve the low power, some of the
digital combinational circuit model like encoder, decoder that has been discussed by (Fischer &
Drutarovský, 2001), and reconfigurable design by (Bertoni, Macchetti, Negri, & Fragneto, 2004),
(Zhang, Zuo, & Zhang, 2007). Next, data path folded type scheme had been discussed by (Huang,
Chang, Lin, & Tai, 2007) , and content addressable memory was introduced by (Fan & Hwang, 2008)
to minimize the area. The feature of efficient hardware designs can be used in prime number (Rais &
Qasim, 2009) or LFSR (Das, 2014) to minimize the area and reduce the critical path delay. General
architectures can be used to implement the SBox and MCT (Satoh, Morioka, Takano, & Munetoh,
2001), (Verbauwhede, Schaumont, & Kuo, 2003) . In addition, composite field arithmetic operation
(Satoh, Morioka, Takano, & Munetoh, 2001) (Yu N. , 2005), (Yu N. , 2005) was discussed for reducing
the circuit complexity that reduces the power. The main design has the trade-off between speed and
area. Unrolling architectures pipeline, and sub-pipeline have been used to speed up and reduce the
area in the AES algorithm. It uses the parallelism to speed up the process. But, these approaches
require a large area since the hardware for implementing each round is duplicated. To reduce the
area, rolling and folding architectures have been presented. A rolling architecture uses a feedback
structure to transform data iteratively. The folded architecture, which is based on the rolling
architecture, executes one round of several clock cycles to reduce the hardware resources. High
performance data encryption standard AES has been implemented by (Chen, Hu, & Li, 2019) using full
pipeline and complete unroll architecture that uses the BRAM and distributed RAM model. Mixcolum
parallelism architecture has been elaborated by (Neelima & Brindha, 2018) to reduce the delay of
execution. Composite filed arithmetic SBOx was discussed by (GADED & Deshpande, 2019) to improve
the area and delay performance. Composite field arithmetic AES SBox , Pipelined SBOX , direct
compute Sbox and LFSR based Sbox were discussed by (Wong, Wong, Zhang, & Hijazin, 2018) .
Combined AES encryption and decryption has been discussed by (Rao & Sharma, 2017) to reduce the
area of the cryptocore.